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drm/amdgpu: simplify amdgpu_ras_eeprom.c

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[ Upstream commit 6246059a19d4cd32ef1af42a6ab016b779cd68c4 ]

All chips that support RAS also support IP discovery, so
use the IP versions rather than a mix of IP versions and
asic types.  Checking the validity of the atom_ctx pointer
is not required as the vbios is already fetched at this
point.

v2: add comments to id asic types based on feedback from Luben

Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Luben Tuikov <luben.tuikov@amd.com>
Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Alex Deucher 2023-03-27 20:09:08 -04:00 committed by Greg Kroah-Hartman
parent af6b1f1156
commit 4ccb34d431
1 changed files with 21 additions and 53 deletions
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74
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
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@ -106,48 +106,13 @@
#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
{
if (adev->asic_type == CHIP_IP_DISCOVERY) {
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 10):
return true;
default:
return false;
}
}
return adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_ARCTURUS ||
adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_ALDEBARAN;
}
static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
struct amdgpu_ras_eeprom_control *control)
{
struct atom_context *atom_ctx = adev->mode_info.atom_context;
if (!control || !atom_ctx)
return false;
if (strnstr(atom_ctx->vbios_version,
"D342",
sizeof(atom_ctx->vbios_version)))
control->i2c_address = EEPROM_I2C_MADDR_0;
else
control->i2c_address = EEPROM_I2C_MADDR_4;
return true;
}
static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev,
struct amdgpu_ras_eeprom_control *control)
{ {
switch (adev->ip_versions[MP1_HWIP][0]) { switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */
case IP_VERSION(11, 0, 7): /* Sienna cichlid */
case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 2): /* Aldebaran */
case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 10):
control->i2c_address = EEPROM_I2C_MADDR_4;
return true; return true;
default: default:
return false; return false;
@ -178,29 +143,32 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
return true; return true;
} }
switch (adev->asic_type) { switch (adev->ip_versions[MP1_HWIP][0]) {
case CHIP_VEGA20: case IP_VERSION(11, 0, 2):
/* VEGA20 and ARCTURUS */
if (adev->asic_type == CHIP_VEGA20)
control->i2c_address = EEPROM_I2C_MADDR_0;
else if (strnstr(atom_ctx->vbios_version,
"D342",
sizeof(atom_ctx->vbios_version)))
control->i2c_address = EEPROM_I2C_MADDR_0;
else
control->i2c_address = EEPROM_I2C_MADDR_4;
return true;
case IP_VERSION(11, 0, 7):
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
return true; return true;
case IP_VERSION(13, 0, 2):
case CHIP_ARCTURUS:
return __get_eeprom_i2c_addr_arct(adev, control);
case CHIP_SIENNA_CICHLID:
control->i2c_address = EEPROM_I2C_MADDR_0;
return true;
case CHIP_ALDEBARAN:
if (strnstr(atom_ctx->vbios_version, "D673", if (strnstr(atom_ctx->vbios_version, "D673",
sizeof(atom_ctx->vbios_version))) sizeof(atom_ctx->vbios_version)))
control->i2c_address = EEPROM_I2C_MADDR_4; control->i2c_address = EEPROM_I2C_MADDR_4;
else else
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
return true; return true;
case IP_VERSION(13, 0, 0):
case CHIP_IP_DISCOVERY: case IP_VERSION(13, 0, 10):
return __get_eeprom_i2c_addr_ip_discovery(adev, control); control->i2c_address = EEPROM_I2C_MADDR_4;
return true;
default: default:
return false; return false;
} }