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drm/amd/display: filter out invalid bits in pipe_fuses

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commit 682439fffad9fa9a38d37dd1b1318e9374232213 upstream.

[Why]
Reading pipe_fuses from register may have invalid bits set, which may
 affect the num_pipes erroneously.

[How]
Add read_pipes_fuses() call and filter bits based on expected number
 of pipes.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Samson Tam 2023-04-19 18:17:14 -04:00 committed by Greg Kroah-Hartman
parent c2b2641ecb
commit 4c1e747ca6
2 changed files with 18 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
View File

@ -2037,6 +2037,14 @@ static struct resource_funcs dcn32_res_pool_funcs = {
.remove_phantom_pipes = dcn32_remove_phantom_pipes,
};
static uint32_t read_pipe_fuses(struct dc_context *ctx)
{
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
/* DCN32 support max 4 pipes */
value = value & 0xf;
return value;
}
static bool dcn32_resource_construct(
uint8_t num_virtual_links,
@ -2079,7 +2087,7 @@ static bool dcn32_resource_construct(
pool->base.res_cap = &res_cap_dcn32;
/* max number of pipes for ASIC before checking for pipe fuses */
num_pipes = pool->base.res_cap->num_timing_generator;
pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
pipe_fuses = read_pipe_fuses(ctx);
for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
if (pipe_fuses & 1 << i)

10
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
View File

@ -1621,6 +1621,14 @@ static struct resource_funcs dcn321_res_pool_funcs = {
.remove_phantom_pipes = dcn32_remove_phantom_pipes,
};
static uint32_t read_pipe_fuses(struct dc_context *ctx)
{
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
/* DCN321 support max 4 pipes */
value = value & 0xf;
return value;
}
static bool dcn321_resource_construct(
uint8_t num_virtual_links,
@ -1663,7 +1671,7 @@ static bool dcn321_resource_construct(
pool->base.res_cap = &res_cap_dcn321;
/* max number of pipes for ASIC before checking for pipe fuses */
num_pipes = pool->base.res_cap->num_timing_generator;
pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
pipe_fuses = read_pipe_fuses(ctx);
for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
if (pipe_fuses & 1 << i)