iommu/amd/pgtbl_v2: Fix domain max address
commit 11c439a19466e7feaccdbce148a75372fddaf4e9 upstream.
IOMMU v2 page table supports 4 level (47 bit) or 5 level (56 bit) virtual
address space. Current code assumes it can support 64bit IOVA address
space. If IOVA allocator allocates virtual address > 47/56 bit (depending
on page table level) then it will do wrong mapping and cause invalid
translation.
Hence adjust aperture size to use max address supported by the page table.
Reported-by: Jerry Snitselaar <jsnitsel@redhat.com>
Fixes: aaac38f614
("iommu/amd: Initial support for AMD IOMMU v2 page table")
Cc: <Stable@vger.kernel.org> # v6.0+
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Link: https://lore.kernel.org/r/20230518054351.9626-1-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
[ Modified to work with "V2 with 4 level page table" only - Vasant ]
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
3264d875f5
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@ -2101,6 +2101,15 @@ static struct protection_domain *protection_domain_alloc(unsigned int type)
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return NULL;
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}
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static inline u64 dma_max_address(void)
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{
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if (amd_iommu_pgtable == AMD_IOMMU_V1)
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return ~0ULL;
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/* V2 with 4 level page table */
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return ((1ULL << PM_LEVEL_SHIFT(PAGE_MODE_4_LEVEL)) - 1);
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}
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static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
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{
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struct protection_domain *domain;
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@ -2117,7 +2126,7 @@ static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
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return NULL;
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domain->domain.geometry.aperture_start = 0;
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domain->domain.geometry.aperture_end = ~0ULL;
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domain->domain.geometry.aperture_end = dma_max_address();
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domain->domain.geometry.force_aperture = true;
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return &domain->domain;
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