MIPS: Remove KVM_TE support
After removal of the guest part of KVM TE (trap and emulate), also remove the host part. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer
parent
a1515ec720
commit
45c7e8af4a
@ -39,7 +39,6 @@ CONFIG_MIPS32_O32=y
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CONFIG_MIPS32_N32=y
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CONFIG_VIRTUALIZATION=y
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CONFIG_KVM=m
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CONFIG_KVM_MIPS_VZ=y
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CONFIG_MODULES=y
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CONFIG_MODULE_FORCE_LOAD=y
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CONFIG_MODULE_UNLOAD=y
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@ -88,44 +88,10 @@
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#define KVM_HALT_POLL_NS_DEFAULT 500000
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#ifdef CONFIG_KVM_MIPS_VZ
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extern unsigned long GUESTID_MASK;
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extern unsigned long GUESTID_FIRST_VERSION;
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extern unsigned long GUESTID_VERSION_MASK;
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#endif
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/*
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* Special address that contains the comm page, used for reducing # of traps
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* This needs to be within 32Kb of 0x0 (so the zero register can be used), but
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* preferably not at 0x0 so that most kernel NULL pointer dereferences can be
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* caught.
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*/
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#define KVM_GUEST_COMMPAGE_ADDR ((PAGE_SIZE > 0x8000) ? 0 : \
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(0x8000 - PAGE_SIZE))
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#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
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((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
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#define KVM_GUEST_KUSEG 0x00000000UL
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#define KVM_GUEST_KSEG0 0x40000000UL
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#define KVM_GUEST_KSEG1 0x40000000UL
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#define KVM_GUEST_KSEG23 0x60000000UL
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#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
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#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
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#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
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#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
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#define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
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/*
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* Map an address to a certain kernel segment
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*/
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#define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
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#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
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#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
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#define KVM_INVALID_PAGE 0xdeadbeef
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#define KVM_INVALID_ADDR 0xdeadbeef
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/*
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@ -165,7 +131,6 @@ struct kvm_vcpu_stat {
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u64 fpe_exits;
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u64 msa_disabled_exits;
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u64 flush_dcache_exits;
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#ifdef CONFIG_KVM_MIPS_VZ
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u64 vz_gpsi_exits;
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u64 vz_gsfc_exits;
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u64 vz_hc_exits;
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@ -176,7 +141,6 @@ struct kvm_vcpu_stat {
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u64 vz_resvd_exits;
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#ifdef CONFIG_CPU_LOONGSON64
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u64 vz_cpucfg_exits;
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#endif
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#endif
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u64 halt_successful_poll;
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u64 halt_attempted_poll;
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@ -303,14 +267,6 @@ enum emulation_result {
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EMULATE_HYPERCALL, /* HYPCALL instruction */
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};
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#define mips3_paddr_to_tlbpfn(x) \
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(((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
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#define mips3_tlbpfn_to_paddr(x) \
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((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
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#define MIPS3_PG_SHIFT 6
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#define MIPS3_PG_FRAME 0x3fffffc0
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#if defined(CONFIG_64BIT)
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#define VPN2_MASK GENMASK(cpu_vmbits - 1, 13)
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#else
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@ -337,7 +293,6 @@ struct kvm_mips_tlb {
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#define KVM_MIPS_AUX_FPU 0x1
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#define KVM_MIPS_AUX_MSA 0x2
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#define KVM_MIPS_GUEST_TLB_SIZE 64
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struct kvm_vcpu_arch {
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void *guest_ebase;
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int (*vcpu_run)(struct kvm_vcpu *vcpu);
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@ -370,9 +325,6 @@ struct kvm_vcpu_arch {
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/* COP0 State */
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struct mips_coproc *cop0;
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/* Host KSEG0 address of the EI/DI offset */
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void *kseg0_commpage;
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/* Resume PC after MMIO completion */
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unsigned long io_pc;
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/* GPR used as IO source/target */
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@ -398,19 +350,9 @@ struct kvm_vcpu_arch {
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/* Bitmask of pending exceptions to be cleared */
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unsigned long pending_exceptions_clr;
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/* S/W Based TLB for guest */
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struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
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/* Guest kernel/user [partial] mm */
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struct mm_struct guest_kernel_mm, guest_user_mm;
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/* Guest ASID of last user mode execution */
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unsigned int last_user_gasid;
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/* Cache some mmu pages needed inside spinlock regions */
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struct kvm_mmu_memory_cache mmu_page_cache;
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#ifdef CONFIG_KVM_MIPS_VZ
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/* vcpu's vzguestid is different on each host cpu in an smp system */
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u32 vzguestid[NR_CPUS];
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@ -421,7 +363,6 @@ struct kvm_vcpu_arch {
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/* emulated guest MAAR registers */
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unsigned long maar[6];
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#endif
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/* Last CPU the VCPU state was loaded on */
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int last_sched_cpu;
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@ -651,20 +592,6 @@ static inline void kvm_change_##name1(struct mips_coproc *cop0, \
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__BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \
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__BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
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#ifndef CONFIG_KVM_MIPS_VZ
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/*
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* T&E (trap & emulate software based virtualisation)
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* We generate the common accessors operating exclusively on the saved context
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* in RAM.
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*/
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#define __BUILD_KVM_RW_HW __BUILD_KVM_RW_SW
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#define __BUILD_KVM_SET_HW __BUILD_KVM_SET_SW
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#define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_ATOMIC_SW
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#else
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/*
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* VZ (hardware assisted virtualisation)
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* These macros use the active guest state in VZ mode (hardware registers),
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@ -697,8 +624,6 @@ static inline void kvm_change_##name1(struct mips_coproc *cop0, \
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*/
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#define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_SET_HW
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#endif
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/*
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* Define accessors for CP0 registers that are accessible to the guest. These
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* are primarily used by common emulation code, which may need to access the
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@ -874,42 +799,9 @@ void kvm_drop_fpu(struct kvm_vcpu *vcpu);
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void kvm_lose_fpu(struct kvm_vcpu *vcpu);
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/* TLB handling */
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u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
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u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
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u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
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#ifdef CONFIG_KVM_MIPS_VZ
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int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
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struct kvm_vcpu *vcpu, bool write_fault);
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#endif
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extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
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struct kvm_vcpu *vcpu,
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bool write_fault);
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extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
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struct kvm_vcpu *vcpu);
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extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
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struct kvm_mips_tlb *tlb,
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unsigned long gva,
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bool write_fault);
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extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu,
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bool write_fault);
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extern void kvm_mips_dump_host_tlbs(void);
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extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
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extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi,
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bool user, bool kernel);
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extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
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unsigned long entryhi);
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#ifdef CONFIG_KVM_MIPS_VZ
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int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
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int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
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unsigned long *gpa);
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@ -923,48 +815,13 @@ void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
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void kvm_loongson_clear_guest_vtlb(void);
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void kvm_loongson_clear_guest_ftlb(void);
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#endif
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#endif
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void kvm_mips_suspend_mm(int cpu);
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void kvm_mips_resume_mm(int cpu);
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/* MMU handling */
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/**
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* enum kvm_mips_flush - Types of MMU flushes.
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* @KMF_USER: Flush guest user virtual memory mappings.
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* Guest USeg only.
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* @KMF_KERN: Flush guest kernel virtual memory mappings.
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* Guest USeg and KSeg2/3.
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* @KMF_GPA: Flush guest physical memory mappings.
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* Also includes KSeg0 if KMF_KERN is set.
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*/
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enum kvm_mips_flush {
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KMF_USER = 0x0,
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KMF_KERN = 0x1,
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KMF_GPA = 0x2,
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};
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void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags);
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bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
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int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
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pgd_t *kvm_pgd_alloc(void);
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void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
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void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
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bool user);
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void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu);
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void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu);
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enum kvm_mips_fault_result {
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KVM_MIPS_MAPPED = 0,
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KVM_MIPS_GVA,
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KVM_MIPS_GPA,
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KVM_MIPS_TLB,
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KVM_MIPS_TLBINV,
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KVM_MIPS_TLBMOD,
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};
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enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
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unsigned long gva,
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bool write);
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#define KVM_ARCH_WANT_MMU_NOTIFIER
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int kvm_unmap_hva_range(struct kvm *kvm,
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@ -974,7 +831,6 @@ int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
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int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
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/* Emulation */
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int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
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enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
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int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
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int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
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@ -1006,68 +862,6 @@ static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
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return false;
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}
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extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_handle_ri(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu);
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u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
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@ -1087,26 +881,9 @@ ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count);
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int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
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u32 count, int min_drift);
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#ifdef CONFIG_KVM_MIPS_VZ
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void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu);
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void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu);
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#else
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static inline void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu) {}
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#endif
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enum emulation_result kvm_mips_check_privilege(u32 cause,
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u32 *opc,
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struct kvm_vcpu *vcpu);
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enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
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u32 *opc,
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u32 cause,
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struct kvm_vcpu *vcpu);
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enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
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u32 *opc,
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u32 cause,
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struct kvm_vcpu *vcpu);
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enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
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u32 cause,
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struct kvm_vcpu *vcpu);
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@ -1117,27 +894,12 @@ enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
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/* COP0 */
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enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
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unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
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unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
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unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
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unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
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/* Hypercalls (hypcall.c) */
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enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
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union mips_instruction inst);
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int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
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/* Dynamic binary translation */
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extern int kvm_mips_trans_cache_index(union mips_instruction inst,
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u32 *opc, struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu);
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/* Misc */
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extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
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extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
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@ -30,40 +30,6 @@ config KVM
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help
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Support for hosting Guest kernels.
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|
||||
choice
|
||||
prompt "Virtualization mode"
|
||||
depends on KVM
|
||||
default KVM_MIPS_TE
|
||||
|
||||
config KVM_MIPS_TE
|
||||
bool "Trap & Emulate"
|
||||
depends on CPU_MIPS32_R2
|
||||
help
|
||||
Use trap and emulate to virtualize 32-bit guests in user mode. This
|
||||
does not require any special hardware Virtualization support beyond
|
||||
standard MIPS32 r2 or later, but it does require the guest kernel
|
||||
to be configured with CONFIG_KVM_GUEST=y so that it resides in the
|
||||
user address segment.
|
||||
|
||||
config KVM_MIPS_VZ
|
||||
bool "MIPS Virtualization (VZ) ASE"
|
||||
help
|
||||
Use the MIPS Virtualization (VZ) ASE to virtualize guests. This
|
||||
supports running unmodified guest kernels (with CONFIG_KVM_GUEST=n),
|
||||
but requires hardware support.
|
||||
|
||||
endchoice
|
||||
|
||||
config KVM_MIPS_DYN_TRANS
|
||||
bool "KVM/MIPS: Dynamic binary translation to reduce traps"
|
||||
depends on KVM_MIPS_TE
|
||||
default y
|
||||
help
|
||||
When running in Trap & Emulate mode patch privileged
|
||||
instructions to reduce the number of traps.
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
config KVM_MIPS_DEBUG_COP0_COUNTERS
|
||||
bool "Maintain counters for COP0 accesses"
|
||||
depends on KVM
|
||||
|
||||
@ -9,7 +9,7 @@ EXTRA_CFLAGS += -Ivirt/kvm -Iarch/mips/kvm
|
||||
common-objs-$(CONFIG_CPU_HAS_MSA) += msa.o
|
||||
|
||||
kvm-objs := $(common-objs-y) mips.o emulate.o entry.o \
|
||||
interrupt.o stats.o commpage.o \
|
||||
interrupt.o stats.o \
|
||||
fpu.o
|
||||
kvm-objs += hypcall.o
|
||||
kvm-objs += mmu.o
|
||||
@ -17,11 +17,6 @@ ifdef CONFIG_CPU_LOONGSON64
|
||||
kvm-objs += loongson_ipi.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_KVM_MIPS_VZ
|
||||
kvm-objs += vz.o
|
||||
else
|
||||
kvm-objs += dyntrans.o
|
||||
kvm-objs += trap_emul.o
|
||||
endif
|
||||
obj-$(CONFIG_KVM) += kvm.o
|
||||
obj-y += callback.o tlb.o
|
||||
|
||||
@ -1,32 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* commpage, currently used for Virtual COP0 registers.
|
||||
* Mapped into the guest kernel @ KVM_GUEST_COMMPAGE_ADDR.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
* Authors: Sanjay Lal <sanjayl@kymasys.com>
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/mmu_context.h>
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
|
||||
#include "commpage.h"
|
||||
|
||||
void kvm_mips_commpage_init(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct kvm_mips_commpage *page = vcpu->arch.kseg0_commpage;
|
||||
|
||||
/* Specific init values for fields */
|
||||
vcpu->arch.cop0 = &page->cop0;
|
||||
}
|
||||
@ -1,24 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* KVM/MIPS: commpage: mapped into get kernel space
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
* Authors: Sanjay Lal <sanjayl@kymasys.com>
|
||||
*/
|
||||
|
||||
#ifndef __KVM_MIPS_COMMPAGE_H__
|
||||
#define __KVM_MIPS_COMMPAGE_H__
|
||||
|
||||
struct kvm_mips_commpage {
|
||||
/* COP0 state is mapped into Guest kernel via commpage */
|
||||
struct mips_coproc cop0;
|
||||
};
|
||||
|
||||
#define KVM_MIPS_COMM_EIDI_OFFSET 0x0
|
||||
|
||||
extern void kvm_mips_commpage_init(struct kvm_vcpu *vcpu);
|
||||
|
||||
#endif /* __KVM_MIPS_COMMPAGE_H__ */
|
||||
@ -1,143 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* KVM/MIPS: Binary Patching for privileged instructions, reduces traps.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
* Authors: Sanjay Lal <sanjayl@kymasys.com>
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/highmem.h>
|
||||
#include <linux/kvm_host.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include "commpage.h"
|
||||
|
||||
/**
|
||||
* kvm_mips_trans_replace() - Replace trapping instruction in guest memory.
|
||||
* @vcpu: Virtual CPU.
|
||||
* @opc: PC of instruction to replace.
|
||||
* @replace: Instruction to write
|
||||
*/
|
||||
static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc,
|
||||
union mips_instruction replace)
|
||||
{
|
||||
unsigned long vaddr = (unsigned long)opc;
|
||||
int err;
|
||||
|
||||
retry:
|
||||
/* The GVA page table is still active so use the Linux TLB handlers */
|
||||
kvm_trap_emul_gva_lockless_begin(vcpu);
|
||||
err = put_user(replace.word, opc);
|
||||
kvm_trap_emul_gva_lockless_end(vcpu);
|
||||
|
||||
if (unlikely(err)) {
|
||||
/*
|
||||
* We write protect clean pages in GVA page table so normal
|
||||
* Linux TLB mod handler doesn't silently dirty the page.
|
||||
* Its also possible we raced with a GVA invalidation.
|
||||
* Try to force the page to become dirty.
|
||||
*/
|
||||
err = kvm_trap_emul_gva_fault(vcpu, vaddr, true);
|
||||
if (unlikely(err)) {
|
||||
kvm_info("%s: Address unwriteable: %p\n",
|
||||
__func__, opc);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/*
|
||||
* Try again. This will likely trigger a TLB refill, which will
|
||||
* fetch the new dirty entry from the GVA page table, which
|
||||
* should then succeed.
|
||||
*/
|
||||
goto retry;
|
||||
}
|
||||
__local_flush_icache_user_range(vaddr, vaddr + 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int kvm_mips_trans_cache_index(union mips_instruction inst, u32 *opc,
|
||||
struct kvm_vcpu *vcpu)
|
||||
{
|
||||
union mips_instruction nop_inst = { 0 };
|
||||
|
||||
/* Replace the CACHE instruction, with a NOP */
|
||||
return kvm_mips_trans_replace(vcpu, opc, nop_inst);
|
||||
}
|
||||
|
||||
/*
|
||||
* Address based CACHE instructions are transformed into synci(s). A little
|
||||
* heavy for just D-cache invalidates, but avoids an expensive trap
|
||||
*/
|
||||
int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
|
||||
struct kvm_vcpu *vcpu)
|
||||
{
|
||||
union mips_instruction synci_inst = { 0 };
|
||||
|
||||
synci_inst.i_format.opcode = bcond_op;
|
||||
synci_inst.i_format.rs = inst.i_format.rs;
|
||||
synci_inst.i_format.rt = synci_op;
|
||||
if (cpu_has_mips_r6)
|
||||
synci_inst.i_format.simmediate = inst.spec3_format.simmediate;
|
||||
else
|
||||
synci_inst.i_format.simmediate = inst.i_format.simmediate;
|
||||
|
||||
return kvm_mips_trans_replace(vcpu, opc, synci_inst);
|
||||
}
|
||||
|
||||
int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
|
||||
struct kvm_vcpu *vcpu)
|
||||
{
|
||||
union mips_instruction mfc0_inst = { 0 };
|
||||
u32 rd, sel;
|
||||
|
||||
rd = inst.c0r_format.rd;
|
||||
sel = inst.c0r_format.sel;
|
||||
|
||||
if (rd == MIPS_CP0_ERRCTL && sel == 0) {
|
||||
mfc0_inst.r_format.opcode = spec_op;
|
||||
mfc0_inst.r_format.rd = inst.c0r_format.rt;
|
||||
mfc0_inst.r_format.func = add_op;
|
||||
} else {
|
||||
mfc0_inst.i_format.opcode = lw_op;
|
||||
mfc0_inst.i_format.rt = inst.c0r_format.rt;
|
||||
mfc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR |
|
||||
offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8)
|
||||
mfc0_inst.i_format.simmediate |= 4;
|
||||
#endif
|
||||
}
|
||||
|
||||
return kvm_mips_trans_replace(vcpu, opc, mfc0_inst);
|
||||
}
|
||||
|
||||
int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
|
||||
struct kvm_vcpu *vcpu)
|
||||
{
|
||||
union mips_instruction mtc0_inst = { 0 };
|
||||
u32 rd, sel;
|
||||
|
||||
rd = inst.c0r_format.rd;
|
||||
sel = inst.c0r_format.sel;
|
||||
|
||||
mtc0_inst.i_format.opcode = sw_op;
|
||||
mtc0_inst.i_format.rt = inst.c0r_format.rt;
|
||||
mtc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR |
|
||||
offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8)
|
||||
mtc0_inst.i_format.simmediate |= 4;
|
||||
#endif
|
||||
|
||||
return kvm_mips_trans_replace(vcpu, opc, mtc0_inst);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -305,7 +305,6 @@ static void *kvm_mips_build_enter_guest(void *addr)
|
||||
UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, pc), K1);
|
||||
UASM_i_MTC0(&p, T0, C0_EPC);
|
||||
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
/* Save normal linux process pgd (VZ guarantees pgd_reg is set) */
|
||||
if (cpu_has_ldpte)
|
||||
UASM_i_MFC0(&p, K0, C0_PWBASE);
|
||||
@ -367,21 +366,6 @@ static void *kvm_mips_build_enter_guest(void *addr)
|
||||
/* Set the root ASID for the Guest */
|
||||
UASM_i_ADDIU(&p, T1, S0,
|
||||
offsetof(struct kvm, arch.gpa_mm.context.asid));
|
||||
#else
|
||||
/* Set the ASID for the Guest Kernel or User */
|
||||
UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, cop0), K1);
|
||||
UASM_i_LW(&p, T0, offsetof(struct mips_coproc, reg[MIPS_CP0_STATUS][0]),
|
||||
T0);
|
||||
uasm_i_andi(&p, T0, T0, KSU_USER | ST0_ERL | ST0_EXL);
|
||||
uasm_i_xori(&p, T0, T0, KSU_USER);
|
||||
uasm_il_bnez(&p, &r, T0, label_kernel_asid);
|
||||
UASM_i_ADDIU(&p, T1, K1, offsetof(struct kvm_vcpu_arch,
|
||||
guest_kernel_mm.context.asid));
|
||||
/* else user */
|
||||
UASM_i_ADDIU(&p, T1, K1, offsetof(struct kvm_vcpu_arch,
|
||||
guest_user_mm.context.asid));
|
||||
uasm_l_kernel_asid(&l, p);
|
||||
#endif
|
||||
|
||||
/* t1: contains the base of the ASID array, need to get the cpu id */
|
||||
/* smp_processor_id */
|
||||
@ -406,24 +390,9 @@ static void *kvm_mips_build_enter_guest(void *addr)
|
||||
uasm_i_andi(&p, K0, K0, MIPS_ENTRYHI_ASID);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_KVM_MIPS_VZ
|
||||
/*
|
||||
* Set up KVM T&E GVA pgd.
|
||||
* This does roughly the same as TLBMISS_HANDLER_SETUP_PGD():
|
||||
* - call tlbmiss_handler_setup_pgd(mm->pgd)
|
||||
* - but skips write into CP0_PWBase for now
|
||||
*/
|
||||
UASM_i_LW(&p, A0, (int)offsetof(struct mm_struct, pgd) -
|
||||
(int)offsetof(struct mm_struct, context.asid), T1);
|
||||
|
||||
UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd);
|
||||
uasm_i_jalr(&p, RA, T9);
|
||||
uasm_i_mtc0(&p, K0, C0_ENTRYHI);
|
||||
#else
|
||||
/* Set up KVM VZ root ASID (!guestid) */
|
||||
uasm_i_mtc0(&p, K0, C0_ENTRYHI);
|
||||
skip_asid_restore:
|
||||
#endif
|
||||
uasm_i_ehb(&p);
|
||||
|
||||
/* Disable RDHWR access */
|
||||
@ -720,7 +689,6 @@ void *kvm_mips_build_exit(void *addr)
|
||||
uasm_l_msa_1(&l, p);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
/* Restore host ASID */
|
||||
if (!cpu_has_guestid) {
|
||||
UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi),
|
||||
@ -764,7 +732,6 @@ void *kvm_mips_build_exit(void *addr)
|
||||
MIPS_GCTL1_RID_WIDTH);
|
||||
uasm_i_mtc0(&p, T0, C0_GUESTCTL1);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
|
||||
uasm_i_addiu(&p, AT, ZERO, ~(ST0_EXL | KSU_USER | ST0_IE));
|
||||
|
||||
@ -21,119 +21,6 @@
|
||||
|
||||
#include "interrupt.h"
|
||||
|
||||
void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
|
||||
{
|
||||
set_bit(priority, &vcpu->arch.pending_exceptions);
|
||||
}
|
||||
|
||||
void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
|
||||
{
|
||||
clear_bit(priority, &vcpu->arch.pending_exceptions);
|
||||
}
|
||||
|
||||
void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
/*
|
||||
* Cause bits to reflect the pending timer interrupt,
|
||||
* the EXC code will be set when we are actually
|
||||
* delivering the interrupt:
|
||||
*/
|
||||
kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI));
|
||||
|
||||
/* Queue up an INT exception for the core */
|
||||
kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
|
||||
|
||||
}
|
||||
|
||||
void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI));
|
||||
kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_TIMER);
|
||||
}
|
||||
|
||||
void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_interrupt *irq)
|
||||
{
|
||||
int intr = (int)irq->irq;
|
||||
|
||||
/*
|
||||
* Cause bits to reflect the pending IO interrupt,
|
||||
* the EXC code will be set when we are actually
|
||||
* delivering the interrupt:
|
||||
*/
|
||||
kvm_set_c0_guest_cause(vcpu->arch.cop0, 1 << (intr + 8));
|
||||
kvm_mips_queue_irq(vcpu, kvm_irq_to_priority(intr));
|
||||
}
|
||||
|
||||
void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_interrupt *irq)
|
||||
{
|
||||
int intr = (int)irq->irq;
|
||||
|
||||
kvm_clear_c0_guest_cause(vcpu->arch.cop0, 1 << (-intr + 8));
|
||||
kvm_mips_dequeue_irq(vcpu, kvm_irq_to_priority(-intr));
|
||||
}
|
||||
|
||||
/* Deliver the interrupt of the corresponding priority, if possible. */
|
||||
int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
|
||||
u32 cause)
|
||||
{
|
||||
int allowed = 0;
|
||||
u32 exccode, ie;
|
||||
|
||||
struct kvm_vcpu_arch *arch = &vcpu->arch;
|
||||
struct mips_coproc *cop0 = vcpu->arch.cop0;
|
||||
|
||||
if (priority == MIPS_EXC_MAX)
|
||||
return 0;
|
||||
|
||||
ie = 1 << (kvm_priority_to_irq[priority] + 8);
|
||||
if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
|
||||
&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
|
||||
&& (kvm_read_c0_guest_status(cop0) & ie)) {
|
||||
allowed = 1;
|
||||
exccode = EXCCODE_INT;
|
||||
}
|
||||
|
||||
/* Are we allowed to deliver the interrupt ??? */
|
||||
if (allowed) {
|
||||
if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
|
||||
/* save old pc */
|
||||
kvm_write_c0_guest_epc(cop0, arch->pc);
|
||||
kvm_set_c0_guest_status(cop0, ST0_EXL);
|
||||
|
||||
if (cause & CAUSEF_BD)
|
||||
kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
|
||||
else
|
||||
kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
|
||||
|
||||
kvm_debug("Delivering INT @ pc %#lx\n", arch->pc);
|
||||
|
||||
} else
|
||||
kvm_err("Trying to deliver interrupt when EXL is already set\n");
|
||||
|
||||
kvm_change_c0_guest_cause(cop0, CAUSEF_EXCCODE,
|
||||
(exccode << CAUSEB_EXCCODE));
|
||||
|
||||
/* XXXSL Set PC to the interrupt exception entry point */
|
||||
arch->pc = kvm_mips_guest_exception_base(vcpu);
|
||||
if (kvm_read_c0_guest_cause(cop0) & CAUSEF_IV)
|
||||
arch->pc += 0x200;
|
||||
else
|
||||
arch->pc += 0x180;
|
||||
|
||||
clear_bit(priority, &vcpu->arch.pending_exceptions);
|
||||
}
|
||||
|
||||
return allowed;
|
||||
}
|
||||
|
||||
int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
|
||||
u32 cause)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause)
|
||||
{
|
||||
unsigned long *pending = &vcpu->arch.pending_exceptions;
|
||||
@ -145,10 +32,7 @@ void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause)
|
||||
|
||||
priority = __ffs(*pending_clr);
|
||||
while (priority <= MIPS_EXC_MAX) {
|
||||
if (kvm_mips_callbacks->irq_clear(vcpu, priority, cause)) {
|
||||
if (!KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE)
|
||||
break;
|
||||
}
|
||||
kvm_mips_callbacks->irq_clear(vcpu, priority, cause);
|
||||
|
||||
priority = find_next_bit(pending_clr,
|
||||
BITS_PER_BYTE * sizeof(*pending_clr),
|
||||
@ -157,10 +41,7 @@ void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause)
|
||||
|
||||
priority = __ffs(*pending);
|
||||
while (priority <= MIPS_EXC_MAX) {
|
||||
if (kvm_mips_callbacks->irq_deliver(vcpu, priority, cause)) {
|
||||
if (!KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE)
|
||||
break;
|
||||
}
|
||||
kvm_mips_callbacks->irq_deliver(vcpu, priority, cause);
|
||||
|
||||
priority = find_next_bit(pending,
|
||||
BITS_PER_BYTE * sizeof(*pending),
|
||||
|
||||
@ -31,29 +31,9 @@
|
||||
|
||||
#define C_TI (_ULCAST_(1) << 30)
|
||||
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
#define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (1)
|
||||
#define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (1)
|
||||
#else
|
||||
#define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (0)
|
||||
#define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (0)
|
||||
#endif
|
||||
|
||||
extern u32 *kvm_priority_to_irq;
|
||||
u32 kvm_irq_to_priority(u32 irq);
|
||||
|
||||
void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority);
|
||||
void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority);
|
||||
int kvm_mips_pending_timer(struct kvm_vcpu *vcpu);
|
||||
|
||||
void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu);
|
||||
void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu);
|
||||
void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_interrupt *irq);
|
||||
void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_interrupt *irq);
|
||||
int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
|
||||
u32 cause);
|
||||
int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
|
||||
u32 cause);
|
||||
void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause);
|
||||
|
||||
@ -30,7 +30,6 @@
|
||||
#include <linux/kvm_host.h>
|
||||
|
||||
#include "interrupt.h"
|
||||
#include "commpage.h"
|
||||
|
||||
#define CREATE_TRACE_POINTS
|
||||
#include "trace.h"
|
||||
@ -58,7 +57,6 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
|
||||
VCPU_STAT("fpe", fpe_exits),
|
||||
VCPU_STAT("msa_disabled", msa_disabled_exits),
|
||||
VCPU_STAT("flush_dcache", flush_dcache_exits),
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
VCPU_STAT("vz_gpsi", vz_gpsi_exits),
|
||||
VCPU_STAT("vz_gsfc", vz_gsfc_exits),
|
||||
VCPU_STAT("vz_hc", vz_hc_exits),
|
||||
@ -69,7 +67,6 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
|
||||
VCPU_STAT("vz_resvd", vz_resvd_exits),
|
||||
#ifdef CONFIG_CPU_LOONGSON64
|
||||
VCPU_STAT("vz_cpucfg", vz_cpucfg_exits),
|
||||
#endif
|
||||
#endif
|
||||
VCPU_STAT("halt_successful_poll", halt_successful_poll),
|
||||
VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
|
||||
@ -139,11 +136,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
|
||||
switch (type) {
|
||||
case KVM_VM_MIPS_AUTO:
|
||||
break;
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
case KVM_VM_MIPS_VZ:
|
||||
#else
|
||||
case KVM_VM_MIPS_TE:
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
/* Unsupported KVM type */
|
||||
@ -361,7 +354,7 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
|
||||
|
||||
/* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
|
||||
refill_start = gebase;
|
||||
if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
|
||||
if (IS_ENABLED(CONFIG_64BIT))
|
||||
refill_start += 0x080;
|
||||
refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
|
||||
|
||||
@ -397,20 +390,6 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
|
||||
flush_icache_range((unsigned long)gebase,
|
||||
(unsigned long)gebase + ALIGN(size, PAGE_SIZE));
|
||||
|
||||
/*
|
||||
* Allocate comm page for guest kernel, a TLB will be reserved for
|
||||
* mapping GVA @ 0xFFFF8000 to this page
|
||||
*/
|
||||
vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
|
||||
|
||||
if (!vcpu->arch.kseg0_commpage) {
|
||||
err = -ENOMEM;
|
||||
goto out_free_gebase;
|
||||
}
|
||||
|
||||
kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
|
||||
kvm_mips_commpage_init(vcpu);
|
||||
|
||||
/* Init */
|
||||
vcpu->arch.last_sched_cpu = -1;
|
||||
vcpu->arch.last_exec_cpu = -1;
|
||||
@ -418,12 +397,10 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
|
||||
/* Initial guest state */
|
||||
err = kvm_mips_callbacks->vcpu_setup(vcpu);
|
||||
if (err)
|
||||
goto out_free_commpage;
|
||||
goto out_free_gebase;
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_commpage:
|
||||
kfree(vcpu->arch.kseg0_commpage);
|
||||
out_free_gebase:
|
||||
kfree(gebase);
|
||||
out_uninit_vcpu:
|
||||
@ -439,7 +416,6 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
|
||||
|
||||
kvm_mmu_free_memory_caches(vcpu);
|
||||
kfree(vcpu->arch.guest_ebase);
|
||||
kfree(vcpu->arch.kseg0_commpage);
|
||||
|
||||
kvm_mips_callbacks->vcpu_uninit(vcpu);
|
||||
}
|
||||
@ -1212,10 +1188,6 @@ int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
|
||||
|
||||
vcpu->mode = OUTSIDE_GUEST_MODE;
|
||||
|
||||
/* re-enable HTW before enabling interrupts */
|
||||
if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
|
||||
htw_start();
|
||||
|
||||
/* Set a default exit reason */
|
||||
run->exit_reason = KVM_EXIT_UNKNOWN;
|
||||
run->ready_for_interrupt_injection = 1;
|
||||
@ -1232,22 +1204,6 @@ int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
|
||||
cause, opc, run, vcpu);
|
||||
trace_kvm_exit(vcpu, exccode);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
|
||||
/*
|
||||
* Do a privilege check, if in UM most of these exit conditions
|
||||
* end up causing an exception to be delivered to the Guest
|
||||
* Kernel
|
||||
*/
|
||||
er = kvm_mips_check_privilege(cause, opc, vcpu);
|
||||
if (er == EMULATE_PRIV_FAIL) {
|
||||
goto skip_emul;
|
||||
} else if (er == EMULATE_FAIL) {
|
||||
run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
|
||||
ret = RESUME_HOST;
|
||||
goto skip_emul;
|
||||
}
|
||||
}
|
||||
|
||||
switch (exccode) {
|
||||
case EXCCODE_INT:
|
||||
kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
|
||||
@ -1357,7 +1313,6 @@ int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
|
||||
|
||||
}
|
||||
|
||||
skip_emul:
|
||||
local_irq_disable();
|
||||
|
||||
if (ret == RESUME_GUEST)
|
||||
@ -1406,11 +1361,6 @@ int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
|
||||
read_c0_config5() & MIPS_CONF5_MSAEN)
|
||||
__kvm_restore_msacsr(&vcpu->arch);
|
||||
}
|
||||
|
||||
/* Disable HTW before returning to guest or host */
|
||||
if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
|
||||
htw_stop();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -1429,10 +1379,6 @@ void kvm_own_fpu(struct kvm_vcpu *vcpu)
|
||||
* FR=0 FPU state, and we don't want to hit reserved instruction
|
||||
* exceptions trying to save the MSA state later when CU=1 && FR=1, so
|
||||
* play it safe and save it first.
|
||||
*
|
||||
* In theory we shouldn't ever hit this case since kvm_lose_fpu() should
|
||||
* get called when guest CU1 is set, however we can't trust the guest
|
||||
* not to clobber the status register directly via the commpage.
|
||||
*/
|
||||
if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
|
||||
vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
|
||||
@ -1553,11 +1499,6 @@ void kvm_lose_fpu(struct kvm_vcpu *vcpu)
|
||||
|
||||
preempt_disable();
|
||||
if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
|
||||
if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
|
||||
set_c0_config5(MIPS_CONF5_MSAEN);
|
||||
enable_fpu_hazard();
|
||||
}
|
||||
|
||||
__kvm_save_msa(&vcpu->arch);
|
||||
trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
|
||||
|
||||
@ -1569,11 +1510,6 @@ void kvm_lose_fpu(struct kvm_vcpu *vcpu)
|
||||
}
|
||||
vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
|
||||
} else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
|
||||
if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
|
||||
set_c0_status(ST0_CU1);
|
||||
enable_fpu_hazard();
|
||||
}
|
||||
|
||||
__kvm_save_fpu(&vcpu->arch);
|
||||
vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
|
||||
trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
|
||||
|
||||
@ -756,209 +756,6 @@ static int kvm_mips_map_page(struct kvm_vcpu *vcpu, unsigned long gpa,
|
||||
return err;
|
||||
}
|
||||
|
||||
static pte_t *kvm_trap_emul_pte_for_gva(struct kvm_vcpu *vcpu,
|
||||
unsigned long addr)
|
||||
{
|
||||
struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
|
||||
pgd_t *pgdp;
|
||||
int ret;
|
||||
|
||||
/* We need a minimum of cached pages ready for page table creation */
|
||||
ret = kvm_mmu_topup_memory_cache(memcache, KVM_MMU_CACHE_MIN_PAGES);
|
||||
if (ret)
|
||||
return NULL;
|
||||
|
||||
if (KVM_GUEST_KERNEL_MODE(vcpu))
|
||||
pgdp = vcpu->arch.guest_kernel_mm.pgd;
|
||||
else
|
||||
pgdp = vcpu->arch.guest_user_mm.pgd;
|
||||
|
||||
return kvm_mips_walk_pgd(pgdp, memcache, addr);
|
||||
}
|
||||
|
||||
void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
|
||||
bool user)
|
||||
{
|
||||
pgd_t *pgdp;
|
||||
pte_t *ptep;
|
||||
|
||||
addr &= PAGE_MASK << 1;
|
||||
|
||||
pgdp = vcpu->arch.guest_kernel_mm.pgd;
|
||||
ptep = kvm_mips_walk_pgd(pgdp, NULL, addr);
|
||||
if (ptep) {
|
||||
ptep[0] = pfn_pte(0, __pgprot(0));
|
||||
ptep[1] = pfn_pte(0, __pgprot(0));
|
||||
}
|
||||
|
||||
if (user) {
|
||||
pgdp = vcpu->arch.guest_user_mm.pgd;
|
||||
ptep = kvm_mips_walk_pgd(pgdp, NULL, addr);
|
||||
if (ptep) {
|
||||
ptep[0] = pfn_pte(0, __pgprot(0));
|
||||
ptep[1] = pfn_pte(0, __pgprot(0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* kvm_mips_flush_gva_{pte,pmd,pud,pgd,pt}.
|
||||
* Flush a range of guest physical address space from the VM's GPA page tables.
|
||||
*/
|
||||
|
||||
static bool kvm_mips_flush_gva_pte(pte_t *pte, unsigned long start_gva,
|
||||
unsigned long end_gva)
|
||||
{
|
||||
int i_min = pte_index(start_gva);
|
||||
int i_max = pte_index(end_gva);
|
||||
bool safe_to_remove = (i_min == 0 && i_max == PTRS_PER_PTE - 1);
|
||||
int i;
|
||||
|
||||
/*
|
||||
* There's no freeing to do, so there's no point clearing individual
|
||||
* entries unless only part of the last level page table needs flushing.
|
||||
*/
|
||||
if (safe_to_remove)
|
||||
return true;
|
||||
|
||||
for (i = i_min; i <= i_max; ++i) {
|
||||
if (!pte_present(pte[i]))
|
||||
continue;
|
||||
|
||||
set_pte(pte + i, __pte(0));
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool kvm_mips_flush_gva_pmd(pmd_t *pmd, unsigned long start_gva,
|
||||
unsigned long end_gva)
|
||||
{
|
||||
pte_t *pte;
|
||||
unsigned long end = ~0ul;
|
||||
int i_min = pmd_index(start_gva);
|
||||
int i_max = pmd_index(end_gva);
|
||||
bool safe_to_remove = (i_min == 0 && i_max == PTRS_PER_PMD - 1);
|
||||
int i;
|
||||
|
||||
for (i = i_min; i <= i_max; ++i, start_gva = 0) {
|
||||
if (!pmd_present(pmd[i]))
|
||||
continue;
|
||||
|
||||
pte = pte_offset_kernel(pmd + i, 0);
|
||||
if (i == i_max)
|
||||
end = end_gva;
|
||||
|
||||
if (kvm_mips_flush_gva_pte(pte, start_gva, end)) {
|
||||
pmd_clear(pmd + i);
|
||||
pte_free_kernel(NULL, pte);
|
||||
} else {
|
||||
safe_to_remove = false;
|
||||
}
|
||||
}
|
||||
return safe_to_remove;
|
||||
}
|
||||
|
||||
static bool kvm_mips_flush_gva_pud(pud_t *pud, unsigned long start_gva,
|
||||
unsigned long end_gva)
|
||||
{
|
||||
pmd_t *pmd;
|
||||
unsigned long end = ~0ul;
|
||||
int i_min = pud_index(start_gva);
|
||||
int i_max = pud_index(end_gva);
|
||||
bool safe_to_remove = (i_min == 0 && i_max == PTRS_PER_PUD - 1);
|
||||
int i;
|
||||
|
||||
for (i = i_min; i <= i_max; ++i, start_gva = 0) {
|
||||
if (!pud_present(pud[i]))
|
||||
continue;
|
||||
|
||||
pmd = pmd_offset(pud + i, 0);
|
||||
if (i == i_max)
|
||||
end = end_gva;
|
||||
|
||||
if (kvm_mips_flush_gva_pmd(pmd, start_gva, end)) {
|
||||
pud_clear(pud + i);
|
||||
pmd_free(NULL, pmd);
|
||||
} else {
|
||||
safe_to_remove = false;
|
||||
}
|
||||
}
|
||||
return safe_to_remove;
|
||||
}
|
||||
|
||||
static bool kvm_mips_flush_gva_pgd(pgd_t *pgd, unsigned long start_gva,
|
||||
unsigned long end_gva)
|
||||
{
|
||||
p4d_t *p4d;
|
||||
pud_t *pud;
|
||||
unsigned long end = ~0ul;
|
||||
int i_min = pgd_index(start_gva);
|
||||
int i_max = pgd_index(end_gva);
|
||||
bool safe_to_remove = (i_min == 0 && i_max == PTRS_PER_PGD - 1);
|
||||
int i;
|
||||
|
||||
for (i = i_min; i <= i_max; ++i, start_gva = 0) {
|
||||
if (!pgd_present(pgd[i]))
|
||||
continue;
|
||||
|
||||
p4d = p4d_offset(pgd, 0);
|
||||
pud = pud_offset(p4d + i, 0);
|
||||
if (i == i_max)
|
||||
end = end_gva;
|
||||
|
||||
if (kvm_mips_flush_gva_pud(pud, start_gva, end)) {
|
||||
pgd_clear(pgd + i);
|
||||
pud_free(NULL, pud);
|
||||
} else {
|
||||
safe_to_remove = false;
|
||||
}
|
||||
}
|
||||
return safe_to_remove;
|
||||
}
|
||||
|
||||
void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags)
|
||||
{
|
||||
if (flags & KMF_GPA) {
|
||||
/* all of guest virtual address space could be affected */
|
||||
if (flags & KMF_KERN)
|
||||
/* useg, kseg0, seg2/3 */
|
||||
kvm_mips_flush_gva_pgd(pgd, 0, 0x7fffffff);
|
||||
else
|
||||
/* useg */
|
||||
kvm_mips_flush_gva_pgd(pgd, 0, 0x3fffffff);
|
||||
} else {
|
||||
/* useg */
|
||||
kvm_mips_flush_gva_pgd(pgd, 0, 0x3fffffff);
|
||||
|
||||
/* kseg2/3 */
|
||||
if (flags & KMF_KERN)
|
||||
kvm_mips_flush_gva_pgd(pgd, 0x60000000, 0x7fffffff);
|
||||
}
|
||||
}
|
||||
|
||||
static pte_t kvm_mips_gpa_pte_to_gva_unmapped(pte_t pte)
|
||||
{
|
||||
/*
|
||||
* Don't leak writeable but clean entries from GPA page tables. We don't
|
||||
* want the normal Linux tlbmod handler to handle dirtying when KVM
|
||||
* accesses guest memory.
|
||||
*/
|
||||
if (!pte_dirty(pte))
|
||||
pte = pte_wrprotect(pte);
|
||||
|
||||
return pte;
|
||||
}
|
||||
|
||||
static pte_t kvm_mips_gpa_pte_to_gva_mapped(pte_t pte, long entrylo)
|
||||
{
|
||||
/* Guest EntryLo overrides host EntryLo */
|
||||
if (!(entrylo & ENTRYLO_D))
|
||||
pte = pte_mkclean(pte);
|
||||
|
||||
return kvm_mips_gpa_pte_to_gva_unmapped(pte);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
|
||||
struct kvm_vcpu *vcpu,
|
||||
bool write_fault)
|
||||
@ -972,125 +769,6 @@ int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
|
||||
/* Invalidate this entry in the TLB */
|
||||
return kvm_vz_host_tlb_inv(vcpu, badvaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* XXXKYMA: Must be called with interrupts disabled */
|
||||
int kvm_mips_handle_kseg0_tlb_fault(unsigned long badvaddr,
|
||||
struct kvm_vcpu *vcpu,
|
||||
bool write_fault)
|
||||
{
|
||||
unsigned long gpa;
|
||||
pte_t pte_gpa[2], *ptep_gva;
|
||||
int idx;
|
||||
|
||||
if (KVM_GUEST_KSEGX(badvaddr) != KVM_GUEST_KSEG0) {
|
||||
kvm_err("%s: Invalid BadVaddr: %#lx\n", __func__, badvaddr);
|
||||
kvm_mips_dump_host_tlbs();
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Get the GPA page table entry */
|
||||
gpa = KVM_GUEST_CPHYSADDR(badvaddr);
|
||||
idx = (badvaddr >> PAGE_SHIFT) & 1;
|
||||
if (kvm_mips_map_page(vcpu, gpa, write_fault, &pte_gpa[idx],
|
||||
&pte_gpa[!idx]) < 0)
|
||||
return -1;
|
||||
|
||||
/* Get the GVA page table entry */
|
||||
ptep_gva = kvm_trap_emul_pte_for_gva(vcpu, badvaddr & ~PAGE_SIZE);
|
||||
if (!ptep_gva) {
|
||||
kvm_err("No ptep for gva %lx\n", badvaddr);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Copy a pair of entries from GPA page table to GVA page table */
|
||||
ptep_gva[0] = kvm_mips_gpa_pte_to_gva_unmapped(pte_gpa[0]);
|
||||
ptep_gva[1] = kvm_mips_gpa_pte_to_gva_unmapped(pte_gpa[1]);
|
||||
|
||||
/* Invalidate this entry in the TLB, guest kernel ASID only */
|
||||
kvm_mips_host_tlb_inv(vcpu, badvaddr, false, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_tlb *tlb,
|
||||
unsigned long gva,
|
||||
bool write_fault)
|
||||
{
|
||||
struct kvm *kvm = vcpu->kvm;
|
||||
long tlb_lo[2];
|
||||
pte_t pte_gpa[2], *ptep_buddy, *ptep_gva;
|
||||
unsigned int idx = TLB_LO_IDX(*tlb, gva);
|
||||
bool kernel = KVM_GUEST_KERNEL_MODE(vcpu);
|
||||
|
||||
tlb_lo[0] = tlb->tlb_lo[0];
|
||||
tlb_lo[1] = tlb->tlb_lo[1];
|
||||
|
||||
/*
|
||||
* The commpage address must not be mapped to anything else if the guest
|
||||
* TLB contains entries nearby, or commpage accesses will break.
|
||||
*/
|
||||
if (!((gva ^ KVM_GUEST_COMMPAGE_ADDR) & VPN2_MASK & (PAGE_MASK << 1)))
|
||||
tlb_lo[TLB_LO_IDX(*tlb, KVM_GUEST_COMMPAGE_ADDR)] = 0;
|
||||
|
||||
/* Get the GPA page table entry */
|
||||
if (kvm_mips_map_page(vcpu, mips3_tlbpfn_to_paddr(tlb_lo[idx]),
|
||||
write_fault, &pte_gpa[idx], NULL) < 0)
|
||||
return -1;
|
||||
|
||||
/* And its GVA buddy's GPA page table entry if it also exists */
|
||||
pte_gpa[!idx] = pfn_pte(0, __pgprot(0));
|
||||
if (tlb_lo[!idx] & ENTRYLO_V) {
|
||||
spin_lock(&kvm->mmu_lock);
|
||||
ptep_buddy = kvm_mips_pte_for_gpa(kvm, NULL,
|
||||
mips3_tlbpfn_to_paddr(tlb_lo[!idx]));
|
||||
if (ptep_buddy)
|
||||
pte_gpa[!idx] = *ptep_buddy;
|
||||
spin_unlock(&kvm->mmu_lock);
|
||||
}
|
||||
|
||||
/* Get the GVA page table entry pair */
|
||||
ptep_gva = kvm_trap_emul_pte_for_gva(vcpu, gva & ~PAGE_SIZE);
|
||||
if (!ptep_gva) {
|
||||
kvm_err("No ptep for gva %lx\n", gva);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Copy a pair of entries from GPA page table to GVA page table */
|
||||
ptep_gva[0] = kvm_mips_gpa_pte_to_gva_mapped(pte_gpa[0], tlb_lo[0]);
|
||||
ptep_gva[1] = kvm_mips_gpa_pte_to_gva_mapped(pte_gpa[1], tlb_lo[1]);
|
||||
|
||||
/* Invalidate this entry in the TLB, current guest mode ASID only */
|
||||
kvm_mips_host_tlb_inv(vcpu, gva, !kernel, kernel);
|
||||
|
||||
kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc,
|
||||
tlb->tlb_lo[0], tlb->tlb_lo[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
|
||||
struct kvm_vcpu *vcpu)
|
||||
{
|
||||
kvm_pfn_t pfn;
|
||||
pte_t *ptep;
|
||||
pgprot_t prot;
|
||||
|
||||
ptep = kvm_trap_emul_pte_for_gva(vcpu, badvaddr);
|
||||
if (!ptep) {
|
||||
kvm_err("No ptep for commpage %lx\n", badvaddr);
|
||||
return -1;
|
||||
}
|
||||
|
||||
pfn = PFN_DOWN(virt_to_phys(vcpu->arch.kseg0_commpage));
|
||||
/* Also set valid and dirty, so refill handler doesn't have to */
|
||||
prot = vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED);
|
||||
*ptep = pte_mkyoung(pte_mkdirty(pfn_pte(pfn, prot)));
|
||||
|
||||
/* Invalidate this entry in the TLB, guest kernel ASID only */
|
||||
kvm_mips_host_tlb_inv(vcpu, badvaddr, false, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_mips_migrate_count() - Migrate timer.
|
||||
@ -1153,86 +831,3 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_trap_emul_gva_fault() - Safely attempt to handle a GVA access fault.
|
||||
* @vcpu: Virtual CPU.
|
||||
* @gva: Guest virtual address to be accessed.
|
||||
* @write: True if write attempted (must be dirtied and made writable).
|
||||
*
|
||||
* Safely attempt to handle a GVA fault, mapping GVA pages if necessary, and
|
||||
* dirtying the page if @write so that guest instructions can be modified.
|
||||
*
|
||||
* Returns: KVM_MIPS_MAPPED on success.
|
||||
* KVM_MIPS_GVA if bad guest virtual address.
|
||||
* KVM_MIPS_GPA if bad guest physical address.
|
||||
* KVM_MIPS_TLB if guest TLB not present.
|
||||
* KVM_MIPS_TLBINV if guest TLB present but not valid.
|
||||
* KVM_MIPS_TLBMOD if guest TLB read only.
|
||||
*/
|
||||
enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
|
||||
unsigned long gva,
|
||||
bool write)
|
||||
{
|
||||
struct mips_coproc *cop0 = vcpu->arch.cop0;
|
||||
struct kvm_mips_tlb *tlb;
|
||||
int index;
|
||||
|
||||
if (KVM_GUEST_KSEGX(gva) == KVM_GUEST_KSEG0) {
|
||||
if (kvm_mips_handle_kseg0_tlb_fault(gva, vcpu, write) < 0)
|
||||
return KVM_MIPS_GPA;
|
||||
} else if ((KVM_GUEST_KSEGX(gva) < KVM_GUEST_KSEG0) ||
|
||||
KVM_GUEST_KSEGX(gva) == KVM_GUEST_KSEG23) {
|
||||
/* Address should be in the guest TLB */
|
||||
index = kvm_mips_guest_tlb_lookup(vcpu, (gva & VPN2_MASK) |
|
||||
(kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID));
|
||||
if (index < 0)
|
||||
return KVM_MIPS_TLB;
|
||||
tlb = &vcpu->arch.guest_tlb[index];
|
||||
|
||||
/* Entry should be valid, and dirty for writes */
|
||||
if (!TLB_IS_VALID(*tlb, gva))
|
||||
return KVM_MIPS_TLBINV;
|
||||
if (write && !TLB_IS_DIRTY(*tlb, gva))
|
||||
return KVM_MIPS_TLBMOD;
|
||||
|
||||
if (kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb, gva, write))
|
||||
return KVM_MIPS_GPA;
|
||||
} else {
|
||||
return KVM_MIPS_GVA;
|
||||
}
|
||||
|
||||
return KVM_MIPS_MAPPED;
|
||||
}
|
||||
|
||||
int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (WARN(IS_ENABLED(CONFIG_KVM_MIPS_VZ),
|
||||
"Expect BadInstr/BadInstrP registers to be used with VZ\n"))
|
||||
return -EINVAL;
|
||||
|
||||
retry:
|
||||
kvm_trap_emul_gva_lockless_begin(vcpu);
|
||||
err = get_user(*out, opc);
|
||||
kvm_trap_emul_gva_lockless_end(vcpu);
|
||||
|
||||
if (unlikely(err)) {
|
||||
/*
|
||||
* Try to handle the fault, maybe we just raced with a GVA
|
||||
* invalidation.
|
||||
*/
|
||||
err = kvm_trap_emul_gva_fault(vcpu, (unsigned long)opc,
|
||||
false);
|
||||
if (unlikely(err)) {
|
||||
kvm_err("%s: illegal address: %p\n",
|
||||
__func__, opc);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* Hopefully it'll work now */
|
||||
goto retry;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -30,10 +30,6 @@
|
||||
#include <asm/r4kcache.h>
|
||||
#define CONFIG_MIPS_MT
|
||||
|
||||
#define KVM_GUEST_PC_TLB 0
|
||||
#define KVM_GUEST_SP_TLB 1
|
||||
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
unsigned long GUESTID_MASK;
|
||||
EXPORT_SYMBOL_GPL(GUESTID_MASK);
|
||||
unsigned long GUESTID_FIRST_VERSION;
|
||||
@ -50,91 +46,6 @@ static u32 kvm_mips_get_root_asid(struct kvm_vcpu *vcpu)
|
||||
else
|
||||
return cpu_asid(smp_processor_id(), gpa_mm);
|
||||
}
|
||||
#endif
|
||||
|
||||
static u32 kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
return cpu_asid(cpu, kern_mm);
|
||||
}
|
||||
|
||||
static u32 kvm_mips_get_user_asid(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct mm_struct *user_mm = &vcpu->arch.guest_user_mm;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
return cpu_asid(cpu, user_mm);
|
||||
}
|
||||
|
||||
/* Structure defining an tlb entry data set. */
|
||||
|
||||
void kvm_mips_dump_host_tlbs(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
kvm_info("HOST TLBs:\n");
|
||||
dump_tlb_regs();
|
||||
pr_info("\n");
|
||||
dump_tlb_all();
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_mips_dump_host_tlbs);
|
||||
|
||||
void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct mips_coproc *cop0 = vcpu->arch.cop0;
|
||||
struct kvm_mips_tlb tlb;
|
||||
int i;
|
||||
|
||||
kvm_info("Guest TLBs:\n");
|
||||
kvm_info("Guest EntryHi: %#lx\n", kvm_read_c0_guest_entryhi(cop0));
|
||||
|
||||
for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
|
||||
tlb = vcpu->arch.guest_tlb[i];
|
||||
kvm_info("TLB%c%3d Hi 0x%08lx ",
|
||||
(tlb.tlb_lo[0] | tlb.tlb_lo[1]) & ENTRYLO_V
|
||||
? ' ' : '*',
|
||||
i, tlb.tlb_hi);
|
||||
kvm_info("Lo0=0x%09llx %c%c attr %lx ",
|
||||
(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[0]),
|
||||
(tlb.tlb_lo[0] & ENTRYLO_D) ? 'D' : ' ',
|
||||
(tlb.tlb_lo[0] & ENTRYLO_G) ? 'G' : ' ',
|
||||
(tlb.tlb_lo[0] & ENTRYLO_C) >> ENTRYLO_C_SHIFT);
|
||||
kvm_info("Lo1=0x%09llx %c%c attr %lx sz=%lx\n",
|
||||
(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[1]),
|
||||
(tlb.tlb_lo[1] & ENTRYLO_D) ? 'D' : ' ',
|
||||
(tlb.tlb_lo[1] & ENTRYLO_G) ? 'G' : ' ',
|
||||
(tlb.tlb_lo[1] & ENTRYLO_C) >> ENTRYLO_C_SHIFT,
|
||||
tlb.tlb_mask);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_mips_dump_guest_tlbs);
|
||||
|
||||
int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi)
|
||||
{
|
||||
int i;
|
||||
int index = -1;
|
||||
struct kvm_mips_tlb *tlb = vcpu->arch.guest_tlb;
|
||||
|
||||
for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
|
||||
if (TLB_HI_VPN2_HIT(tlb[i], entryhi) &&
|
||||
TLB_HI_ASID_HIT(tlb[i], entryhi)) {
|
||||
index = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n",
|
||||
__func__, entryhi, index, tlb[i].tlb_lo[0], tlb[i].tlb_lo[1]);
|
||||
|
||||
return index;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_mips_guest_tlb_lookup);
|
||||
|
||||
static int _kvm_mips_host_tlb_inv(unsigned long entryhi)
|
||||
{
|
||||
@ -163,54 +74,6 @@ static int _kvm_mips_host_tlb_inv(unsigned long entryhi)
|
||||
return idx;
|
||||
}
|
||||
|
||||
int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long va,
|
||||
bool user, bool kernel)
|
||||
{
|
||||
/*
|
||||
* Initialize idx_user and idx_kernel to workaround bogus
|
||||
* maybe-initialized warning when using GCC 6.
|
||||
*/
|
||||
int idx_user = 0, idx_kernel = 0;
|
||||
unsigned long flags, old_entryhi;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
old_entryhi = read_c0_entryhi();
|
||||
|
||||
if (user)
|
||||
idx_user = _kvm_mips_host_tlb_inv((va & VPN2_MASK) |
|
||||
kvm_mips_get_user_asid(vcpu));
|
||||
if (kernel)
|
||||
idx_kernel = _kvm_mips_host_tlb_inv((va & VPN2_MASK) |
|
||||
kvm_mips_get_kernel_asid(vcpu));
|
||||
|
||||
write_c0_entryhi(old_entryhi);
|
||||
mtc0_tlbw_hazard();
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
/*
|
||||
* We don't want to get reserved instruction exceptions for missing tlb
|
||||
* entries.
|
||||
*/
|
||||
if (cpu_has_vtag_icache)
|
||||
flush_icache_all();
|
||||
|
||||
if (user && idx_user >= 0)
|
||||
kvm_debug("%s: Invalidated guest user entryhi %#lx @ idx %d\n",
|
||||
__func__, (va & VPN2_MASK) |
|
||||
kvm_mips_get_user_asid(vcpu), idx_user);
|
||||
if (kernel && idx_kernel >= 0)
|
||||
kvm_debug("%s: Invalidated guest kernel entryhi %#lx @ idx %d\n",
|
||||
__func__, (va & VPN2_MASK) |
|
||||
kvm_mips_get_kernel_asid(vcpu), idx_kernel);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_mips_host_tlb_inv);
|
||||
|
||||
#ifdef CONFIG_KVM_MIPS_VZ
|
||||
|
||||
/* GuestID management */
|
||||
|
||||
/**
|
||||
@ -661,40 +524,3 @@ void kvm_loongson_clear_guest_ftlb(void)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_loongson_clear_guest_ftlb);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* kvm_mips_suspend_mm() - Suspend the active mm.
|
||||
* @cpu The CPU we're running on.
|
||||
*
|
||||
* Suspend the active_mm, ready for a switch to a KVM guest virtual address
|
||||
* space. This is left active for the duration of guest context, including time
|
||||
* with interrupts enabled, so we need to be careful not to confuse e.g. cache
|
||||
* management IPIs.
|
||||
*
|
||||
* kvm_mips_resume_mm() should be called before context switching to a different
|
||||
* process so we don't need to worry about reference counting.
|
||||
*
|
||||
* This needs to be in static kernel code to avoid exporting init_mm.
|
||||
*/
|
||||
void kvm_mips_suspend_mm(int cpu)
|
||||
{
|
||||
cpumask_clear_cpu(cpu, mm_cpumask(current->active_mm));
|
||||
current->active_mm = &init_mm;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_mips_suspend_mm);
|
||||
|
||||
/**
|
||||
* kvm_mips_resume_mm() - Resume the current process mm.
|
||||
* @cpu The CPU we're running on.
|
||||
*
|
||||
* Resume the mm of the current process, after a switch back from a KVM guest
|
||||
* virtual address space (see kvm_mips_suspend_mm()).
|
||||
*/
|
||||
void kvm_mips_resume_mm(int cpu)
|
||||
{
|
||||
cpumask_set_cpu(cpu, mm_cpumask(current->mm));
|
||||
current->active_mm = current->mm;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_mips_resume_mm);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -292,9 +292,8 @@ static int kvm_vz_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
|
||||
switch (priority) {
|
||||
case MIPS_EXC_INT_TIMER:
|
||||
/*
|
||||
* Call to kvm_write_c0_guest_compare() clears Cause.TI in
|
||||
* kvm_mips_emulate_CP0(). Explicitly clear irq associated with
|
||||
* Cause.IP[IPTI] if GuestCtl2 virtual interrupt register not
|
||||
* Explicitly clear irq associated with Cause.IP[IPTI]
|
||||
* if GuestCtl2 virtual interrupt register not
|
||||
* supported or if not using GuestCtl2 Hardware Clear.
|
||||
*/
|
||||
if (cpu_has_guestctl2) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user