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net: hns3: fix reset timeout when enable full VF

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[ Upstream commit 6b45d5ff8c2c61baddd67d7510075ae121c5e704 ]

The timeout of the cmdq reset command has been increased to
resolve the reset timeout issue in the full VF scenario.
The timeout of other cmdq commands remains unchanged.

Fixes: 8d307f8e8c ("net: hns3: create new set of unified hclge_comm_cmd_send APIs")
Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jijie Shao 2023-05-12 18:00:14 +08:00 committed by Greg Kroah-Hartman
parent 89982e0501
commit 4147a0cee1
2 changed files with 28 additions and 5 deletions
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25
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
View File

@ -330,9 +330,25 @@ static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw)
return head == hw->cmq.csq.next_to_use;
}
static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw,
static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)
{
static const struct hclge_cmdq_tx_timeout_map cmdq_tx_timeout_map[] = {
{HCLGE_OPC_CFG_RST_TRIGGER, HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS},
};
u32 i;
for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout_map); i++)
if (cmdq_tx_timeout_map[i].opcode == opcode)
return cmdq_tx_timeout_map[i].tx_timeout;
return tx_timeout;
}
static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, u16 opcode,
bool *is_completed)
{
u32 cmdq_tx_timeout = hclge_get_cmdq_tx_timeout(opcode,
hw->cmq.tx_timeout);
u32 timeout = 0;
do {
@ -342,7 +358,7 @@ static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw,
}
udelay(1);
timeout++;
} while (timeout < hw->cmq.tx_timeout);
} while (timeout < cmdq_tx_timeout);
}
static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
@ -406,7 +422,8 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
* if multi descriptors to be sent, use the first one to check
*/
if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))
hclge_comm_wait_for_resp(hw, &is_completed);
hclge_comm_wait_for_resp(hw, le16_to_cpu(desc->opcode),
&is_completed);
if (!is_completed)
ret = -EBADE;
@ -528,7 +545,7 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw)
cmdq->crq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;
/* Setup Tx write back timeout */
cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT;
cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT;
/* Setup queue rings */
ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CSQ);

8
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
View File

@ -54,7 +54,8 @@
#define HCLGE_COMM_NIC_SW_RST_RDY BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S 3
#define HCLGE_COMM_NIC_CMQ_DESC_NUM 1024
#define HCLGE_COMM_CMDQ_TX_TIMEOUT 30000
#define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT 30000
#define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS 500000
enum hclge_opcode_type {
/* Generic commands */
@ -357,6 +358,11 @@ struct hclge_comm_caps_bit_map {
u16 local_bit;
};
struct hclge_cmdq_tx_timeout_map {
u32 opcode;
u32 tx_timeout;
};
struct hclge_comm_firmware_compat_cmd {
__le32 compat;
u8 rsv[20];