Merge "clk: qcom: gpucc-pineapple: Add support for LIMITER reset"

This commit is contained in:
qctecmdr 2023-04-27 11:36:52 -07:00 committed by Gerrit - the friendly Code Review server
commit 3f69f4eee2
2 changed files with 6 additions and 1 deletions

View File

@ -611,6 +611,7 @@ static const struct qcom_reset_map gpu_cc_pineapple_resets[] = {
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
[GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR] = { 0x9538, 0 },
};
static const struct regmap_config gpu_cc_pineapple_regmap_config = {
@ -657,6 +658,9 @@ static int gpu_cc_pineapple_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
/* Enable frequency limiter irq */
regmap_write(regmap, 0x9534, 0x0);
ret = qcom_cc_really_probe(pdev, &gpu_cc_pineapple_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");

View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_PINEAPPLE_H
@ -44,5 +44,6 @@
#define GPUCC_GPU_CC_GMU_BCR 5
#define GPUCC_GPU_CC_GX_BCR 6
#define GPUCC_GPU_CC_XO_BCR 7
#define GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 8
#endif