From 23d6c70b358348014600d697f99d20418eb02c67 Mon Sep 17 00:00:00 2001 From: Sachin Gupta Date: Wed, 30 Aug 2023 17:47:40 +0530 Subject: [PATCH] Revert "mmc: sdhci-msm: Update dll_config_3 as per HSR" This reverts commit 04816e672d46a1aabb1a35d73ca5f90d6d252ca3. Avoid modification of dll_config_3 register based on the clock freq. For EMMC if clock freq is greater than 150Mhz then the existing logic will modify it to 0x10 whereas expected is 0x01. And hence results in dll mismatch. Change-Id: Ibdee59c3c5057c1434a234ad1548d09ae96dd05a Signed-off-by: Sachin Gupta --- drivers/mmc/host/sdhci-msm.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index d0e40648f21e..8cf60227b574 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -87,9 +87,6 @@ #define FINE_TUNE_MODE_EN BIT(27) #define BIAS_OK_SIGNAL BIT(29) -#define DLL_CONFIG_3_LOW_FREQ_VAL 0x08 -#define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10 - #define CORE_VENDOR_SPEC_POR_VAL 0xa9c #define CORE_CLK_PWRSAVE BIT(1) #define CORE_VNDR_SPEC_ADMA_ERR_SIZE_EN BIT(7) @@ -1038,16 +1035,6 @@ static int msm_init_cm_dll(struct sdhci_host *host, ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL; writel_relaxed(config, host->ioaddr + msm_offset->core_dll_usr_ctl); - - config = readl_relaxed(host->ioaddr + - msm_offset->core_dll_config_3); - config &= ~0xFF; - if (msm_host->clk_rate < 150000000) - config |= DLL_CONFIG_3_LOW_FREQ_VAL; - else - config |= DLL_CONFIG_3_HIGH_FREQ_VAL; - writel_relaxed(config, host->ioaddr + - msm_offset->core_dll_config_3); } /* Step 11 - Wait for 52us */