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cxl/region: fix x9 interleave typo

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[ Upstream commit c7ad3dc3649730af483ee1e78be5d0362da25bfe ]

CXL supports x3, x6 and x12 - not x9.

Fixes: 80d10a6cee ("cxl/region: Add interleave geometry attributes")
Signed-off-by: Jim Harris <jim.harris@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Link: https://lore.kernel.org/r/169904271254.204936.8580772404462743630.stgit@ubuntu
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jim Harris 2023-11-03 20:18:34 +00:00 committed by Greg Kroah-Hartman
parent 16cbe4bad8
commit 3a46101871
1 changed files with 1 additions and 1 deletions
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drivers/cxl/core/region.c
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@ -331,7 +331,7 @@ static ssize_t interleave_ways_store(struct device *dev,
return rc;
/*
* Even for x3, x9, and x12 interleaves the region interleave must be a
* Even for x3, x6, and x12 interleaves the region interleave must be a
* power of 2 multiple of the host bridge interleave.
*/
if (!is_power_of_2(val / cxld->interleave_ways) ||