Merge "arm64: defconfig: Enable CONFIG_PHY_QCOM_UFS_V4_SM6375 for blair"
This commit is contained in:
qctecmdr
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commit
18cb516b44
1
arch/arm64/configs/vendor/blair_GKI.config
vendored
1
arch/arm64/configs/vendor/blair_GKI.config
vendored
@ -46,6 +46,7 @@ CONFIG_PANIC_TIMEOUT=5
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CONFIG_PHY_QCOM_UFS=m
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CONFIG_PHY_QCOM_UFS_QRBTC_SDM845=m
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CONFIG_PHY_QCOM_UFS_V4=m
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CONFIG_PHY_QCOM_UFS_V4_SM6375=m
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CONFIG_PINCTRL_BLAIR=m
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CONFIG_PINCTRL_MSM=m
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CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
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@ -55,6 +55,7 @@ def define_blair():
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"drivers/perf/qcom_llcc_pmu.ko",
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"drivers/phy/qualcomm/phy-qcom-ufs.ko",
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"drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.ko",
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"drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-blair.ko",
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"drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.ko",
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"drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-pineapple.ko",
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"drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.ko",
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@ -86,6 +86,12 @@ config PHY_QCOM_UFS_QRBTC_SDM845
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No low power mode support is present.
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Doesn't restrict number of lanes.
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config PHY_QCOM_UFS_V4_SM6375
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tristate "Qualcomm Technologies, Inc. UFS Blair Phy Driver"
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depends on PHY_QCOM_UFS
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help
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Support for UFS phy present on QCOM Blair chipsets.
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endif
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config PHY_QCOM_QUSB2
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@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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obj-$(CONFIG_PHY_QCOM_UFS_V4) += phy-qcom-ufs-qmp-v4-kalama.o phy-qcom-ufs-qmp-v4-pineapple.o phy-qcom-ufs-qmp-v4.o
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obj-$(CONFIG_PHY_QCOM_UFS_QRBTC_SDM845) += phy-qcom-ufs-qrbtc-sdm845.o
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obj-$(CONFIG_PHY_QCOM_UFS_V4_SM6375) += phy-qcom-ufs-qmp-v4-blair.o
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obj-$(CONFIG_PHY_QCOM_QMP) += \
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phy-qcom-qmp.o \
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320
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-blair.c
Normal file
320
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-blair.c
Normal file
@ -0,0 +1,320 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "phy-qcom-ufs-qmp-v4-blair.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_v4_blair"
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static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy);
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static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common);
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static int ufs_qcom_phy_qmp_v4_phy_calibrate(struct phy *generic_phy)
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{
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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struct device *dev = ufs_qcom_phy->dev;
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bool is_g4, is_rate_B;
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int err;
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err = reset_control_assert(ufs_qcom_phy->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to assert UFS PHY reset %d\n", err);
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goto out;
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}
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/* For UFS PHY's submode, 1 = G4, 0 = non-G4 */
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is_g4 = !!ufs_qcom_phy->submode;
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is_rate_B = (ufs_qcom_phy->mode == PHY_MODE_UFS_HS_B) ? true : false;
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writel_relaxed(0x01, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET);
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/* Ensure PHY is in reset before writing PHY calibration data */
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wmb();
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/*
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* Writing PHY calibration in this order:
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* 1. Write Rate-A calibration first (1-lane mode).
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* 2. Write 2nd lane configuration if needed.
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* 3. Write Rate-B calibration overrides
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*/
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if (is_g4) {
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A,
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ARRAY_SIZE(phy_cal_table_rate_A));
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if (ufs_qcom_phy->lanes_per_direction == 2)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_2nd_lane,
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ARRAY_SIZE(phy_cal_table_2nd_lane));
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} else {
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_no_g4,
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ARRAY_SIZE(phy_cal_table_rate_A_no_g4));
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if (ufs_qcom_phy->lanes_per_direction == 2)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_2nd_lane_no_g4,
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ARRAY_SIZE(phy_cal_table_2nd_lane_no_g4));
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}
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if (is_rate_B)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B,
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ARRAY_SIZE(phy_cal_table_rate_B));
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writel_relaxed(0x00, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET);
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/* flush buffered writes */
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wmb();
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err = reset_control_deassert(ufs_qcom_phy->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err);
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goto out;
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}
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ufs_qcom_phy_qmp_v4_start_serdes(ufs_qcom_phy);
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err = ufs_qcom_phy_qmp_v4_is_pcs_ready(ufs_qcom_phy);
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_v4_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy_qmp_v4 *phy = phy_get_drvdata(generic_phy);
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struct ufs_qcom_phy *phy_common = &phy->common_cfg;
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int err;
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err = ufs_qcom_phy_init_clks(phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
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__func__, err);
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goto out;
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}
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err = ufs_qcom_phy_init_vregulators(phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
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__func__, err);
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goto out;
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}
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/* Optional */
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ufs_qcom_phy_get_reset(phy_common);
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_v4_exit(struct phy *generic_phy)
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{
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return 0;
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}
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static
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int ufs_qcom_phy_qmp_v4_set_mode(struct phy *generic_phy,
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enum phy_mode mode, int submode)
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{
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struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
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phy_common->mode = PHY_MODE_INVALID;
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if (mode > 0)
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phy_common->mode = mode;
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phy_common->submode = submode;
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return 0;
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}
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static inline
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void ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(struct ufs_qcom_phy *phy,
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bool enable)
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{
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u32 temp;
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temp = readl_relaxed(phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE);
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if (enable)
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temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
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else
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temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
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writel_relaxed(temp, phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE);
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if (phy->lanes_per_direction == 1)
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goto out;
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temp = readl_relaxed(phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE);
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if (enable)
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temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
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else
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temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
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writel_relaxed(temp, phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE);
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out:
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/* ensure register value is committed */
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mb();
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}
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static
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void ufs_qcom_phy_qmp_v4_power_control(struct ufs_qcom_phy *phy,
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bool power_ctrl)
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{
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if (!power_ctrl) {
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/* apply analog power collapse */
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writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Make sure that PHY knows its analog rail is going to be
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* powered OFF.
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*/
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mb();
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ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, true);
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} else {
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ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, false);
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/* bring PHY out of analog power collapse */
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writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON.
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*/
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mb();
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}
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}
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static inline
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void ufs_qcom_phy_qmp_v4_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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/*
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* v4 PHY does not have TX_LANE_ENABLE register.
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* Implement this function so as not to propagate error to caller.
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*/
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}
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static
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void ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)
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{
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u32 temp;
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temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);
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if (ctrl) /* enable RX LineCfg */
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temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;
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else /* disable RX LineCfg */
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temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;
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writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);
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/* make sure that RX LineCfg config applied before we return */
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mb();
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}
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static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err) {
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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goto out;
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}
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out:
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return err;
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}
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static void ufs_qcom_phy_qmp_v4_dbg_register_dump(struct ufs_qcom_phy *phy)
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{
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ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
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"PHY QSERDES COM Registers ");
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ufs_qcom_phy_dump_regs(phy, PCS2_BASE, PCS2_SIZE,
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"PHY PCS2 Registers ");
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ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE,
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"PHY Registers ");
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ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE,
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"PHY RX0 Registers ");
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ufs_qcom_phy_dump_regs(phy, TX_BASE(0), TX_SIZE,
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"PHY TX0 Registers ");
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ufs_qcom_phy_dump_regs(phy, RX_BASE(1), RX_SIZE,
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"PHY RX1 Registers ");
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ufs_qcom_phy_dump_regs(phy, TX_BASE(1), TX_SIZE,
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"PHY TX1 Registers ");
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}
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static const struct phy_ops ufs_qcom_phy_qmp_v4_phy_ops = {
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.init = ufs_qcom_phy_qmp_v4_init,
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.exit = ufs_qcom_phy_qmp_v4_exit,
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.set_mode = ufs_qcom_phy_qmp_v4_set_mode,
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.calibrate = ufs_qcom_phy_qmp_v4_phy_calibrate,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_v4_ops = {
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.start_serdes = ufs_qcom_phy_qmp_v4_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v4_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_v4_set_tx_lane_enable,
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.ctrl_rx_linecfg = ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg,
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.power_control = ufs_qcom_phy_qmp_v4_power_control,
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.dbg_register_dump = ufs_qcom_phy_qmp_v4_dbg_register_dump,
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};
|
||||
|
||||
static int ufs_qcom_phy_qmp_v4_probe(struct platform_device *pdev)
|
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
|
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struct ufs_qcom_phy_qmp_v4 *phy;
|
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int err = 0;
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||||
|
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
||||
if (!phy) {
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err = -ENOMEM;
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goto out;
|
||||
}
|
||||
|
||||
generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
|
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&ufs_qcom_phy_qmp_v4_phy_ops, &phy_v4_ops);
|
||||
|
||||
if (!generic_phy) {
|
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
|
||||
__func__);
|
||||
err = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
phy_set_drvdata(generic_phy, phy);
|
||||
|
||||
strscpy(phy->common_cfg.name, UFS_PHY_NAME,
|
||||
sizeof(phy->common_cfg.name));
|
||||
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct of_device_id ufs_qcom_phy_qmp_v4_of_match[] = {
|
||||
{.compatible = "qcom,ufs-phy-qmp-v4-blair"},
|
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{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v4_of_match);
|
||||
|
||||
static struct platform_driver ufs_qcom_phy_qmp_v4_driver = {
|
||||
.probe = ufs_qcom_phy_qmp_v4_probe,
|
||||
.driver = {
|
||||
.of_match_table = ufs_qcom_phy_qmp_v4_of_match,
|
||||
.name = "ufs_qcom_phy_qmp_v4_blair",
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(ufs_qcom_phy_qmp_v4_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v4 BLAIR");
|
||||
MODULE_LICENSE("GPL");
|
||||
447
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-blair.h
Normal file
447
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-blair.h
Normal file
@ -0,0 +1,447 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef UFS_QCOM_PHY_QMP_V4_H_
|
||||
#define UFS_QCOM_PHY_QMP_V4_H_
|
||||
|
||||
#include "phy-qcom-ufs-i.h"
|
||||
|
||||
/* QCOM UFS PHY control registers */
|
||||
#define COM_BASE 0x000
|
||||
#define COM_SIZE 0x1C0
|
||||
#define PHY_BASE 0xC00
|
||||
#define PHY_SIZE 0x200
|
||||
#define PCS2_BASE 0x200
|
||||
#define PCS2_SIZE 0x40
|
||||
#define TX_BASE(n) (0x400 + (0x400 * n))
|
||||
#define TX_SIZE 0x170
|
||||
#define RX_BASE(n) (0x600 + (0x400 * n))
|
||||
#define RX_SIZE 0x200
|
||||
#define COM_OFF(x) (COM_BASE + x)
|
||||
#define PHY_OFF(x) (PHY_BASE + x)
|
||||
#define TX_OFF(n, x) (TX_BASE(n) + x)
|
||||
#define RX_OFF(n, x) (RX_BASE(n) + x)
|
||||
|
||||
/* UFS PHY QSERDES COM registers */
|
||||
#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x94)
|
||||
#define QSERDES_COM_HSCLK_SEL COM_OFF(0x158)
|
||||
#define QSERDES_COM_HSCLK_HS_SWITCH_SEL COM_OFF(0x15C)
|
||||
#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xA4)
|
||||
#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x10C)
|
||||
#define QSERDES_COM_PLL_IVCO COM_OFF(0x58)
|
||||
#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x124)
|
||||
#define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL COM_OFF(0x1BC)
|
||||
#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xBC)
|
||||
#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x74)
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x7C)
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x84)
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0xAC)
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0xB0)
|
||||
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 COM_OFF(0x1AC)
|
||||
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 COM_OFF(0x1B0)
|
||||
#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xC4)
|
||||
#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x78)
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x80)
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x88)
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0xB4)
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0xB8)
|
||||
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 COM_OFF(0x1B4)
|
||||
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 COM_OFF(0x1B8)
|
||||
#define QSERDES_COM_CMN_IPTRIM COM_OFF(0x60)
|
||||
|
||||
/* UFS PHY registers */
|
||||
#define UFS_PHY_PHY_START PHY_OFF(0x00)
|
||||
#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
|
||||
#define UFS_PHY_SW_RESET PHY_OFF(0x08)
|
||||
#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x180)
|
||||
#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x148)
|
||||
#define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1E0)
|
||||
#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x158)
|
||||
#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x30)
|
||||
#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x38)
|
||||
#define UFS_PHY_TX_MID_TERM_CTRL1 PHY_OFF(0x1D8)
|
||||
#define UFS_PHY_DEBUG_BUS_CLKSEL PHY_OFF(0x124)
|
||||
#define UFS_PHY_PLL_CNTL PHY_OFF(0x2C)
|
||||
#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x0C)
|
||||
#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x10)
|
||||
#define UFS_PHY_TX_PWM_GEAR_BAND PHY_OFF(0x160)
|
||||
#define UFS_PHY_TX_HS_GEAR_BAND PHY_OFF(0x168)
|
||||
#define UFS_PHY_TX_HSGEAR_CAPABILITY PHY_OFF(0x74)
|
||||
#define UFS_PHY_RX_HSGEAR_CAPABILITY PHY_OFF(0xB4)
|
||||
#define UFS_PHY_RX_MIN_HIBERN8_TIME PHY_OFF(0x150)
|
||||
#define UFS_PHY_BIST_FIXED_PAT_CTRL PHY_OFF(0x60)
|
||||
|
||||
/* UFS PHY TX registers */
|
||||
#define QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(0, 0xD8)
|
||||
#define QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(0, 0xDC)
|
||||
#define QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(0, 0xE0)
|
||||
#define QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(0, 0xE4)
|
||||
#define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x84)
|
||||
#define QSERDES_TX0_TRAN_DRVR_EMP_EN TX_OFF(0, 0xB8)
|
||||
|
||||
#define QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(1, 0xD8)
|
||||
#define QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(1, 0xDC)
|
||||
#define QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(1, 0xE0)
|
||||
#define QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(1, 0xE4)
|
||||
#define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x84)
|
||||
#define QSERDES_TX1_TRAN_DRVR_EMP_EN TX_OFF(1, 0xB8)
|
||||
|
||||
/* UFS PHY RX registers */
|
||||
#define QSERDES_RX0_SIGDET_LVL RX_OFF(0, 0x120)
|
||||
#define QSERDES_RX0_SIGDET_CNTRL RX_OFF(0, 0x11C)
|
||||
#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x124)
|
||||
#define QSERDES_RX0_RX_BAND RX_OFF(0, 0x128)
|
||||
#define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x30)
|
||||
#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(0, 0x34)
|
||||
#define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0x44)
|
||||
#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW RX_OFF(0, 0x3C)
|
||||
#define QSERDES_RX0_UCDR_PI_CTRL2 RX_OFF(0, 0x48)
|
||||
#define QSERDES_RX0_RX_TERM_BW RX_OFF(0, 0x80)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1 RX_OFF(0, 0xE8)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xEC)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(0, 0xF0)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0xF4)
|
||||
#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(0, 0x110)
|
||||
#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 RX_OFF(0, 0x114)
|
||||
#define QSERDES_RX0_RX_IDAC_MEASURE_TIME RX_OFF(0, 0x100)
|
||||
#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW RX_OFF(0, 0xF8)
|
||||
#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH RX_OFF(0, 0xFC)
|
||||
#define QSERDES_RX0_RX_MODE_00_LOW RX_OFF(0, 0x170)
|
||||
#define QSERDES_RX0_RX_MODE_00_HIGH RX_OFF(0, 0x174)
|
||||
#define QSERDES_RX0_RX_MODE_00_HIGH2 RX_OFF(0, 0x178)
|
||||
#define QSERDES_RX0_RX_MODE_00_HIGH3 RX_OFF(0, 0x17C)
|
||||
#define QSERDES_RX0_RX_MODE_00_HIGH4 RX_OFF(0, 0x180)
|
||||
#define QSERDES_RX0_RX_MODE_01_LOW RX_OFF(0, 0x184)
|
||||
#define QSERDES_RX0_RX_MODE_01_HIGH RX_OFF(0, 0x188)
|
||||
#define QSERDES_RX0_RX_MODE_01_HIGH2 RX_OFF(0, 0x18C)
|
||||
#define QSERDES_RX0_RX_MODE_01_HIGH3 RX_OFF(0, 0x190)
|
||||
#define QSERDES_RX0_RX_MODE_01_HIGH4 RX_OFF(0, 0x194)
|
||||
#define QSERDES_RX0_RX_MODE_10_LOW RX_OFF(0, 0x198)
|
||||
#define QSERDES_RX0_RX_MODE_10_HIGH RX_OFF(0, 0x19C)
|
||||
#define QSERDES_RX0_RX_MODE_10_HIGH2 RX_OFF(0, 0x1A0)
|
||||
#define QSERDES_RX0_RX_MODE_10_HIGH3 RX_OFF(0, 0x1A4)
|
||||
#define QSERDES_RX0_RX_MODE_10_HIGH4 RX_OFF(0, 0x1A8)
|
||||
#define QSERDES_RX0_DCC_CTRL1 RX_OFF(0, 0x1BC)
|
||||
#define QSERDES_RX0_GM_CAL RX_OFF(0, 0xDC)
|
||||
#define QSERDES_RX0_AC_JTAG_ENABLE RX_OFF(0, 0x68)
|
||||
#define QSERDES_RX0_UCDR_FO_GAIN RX_OFF(0, 0x08)
|
||||
#define QSERDES_RX0_UCDR_SO_GAIN RX_OFF(0, 0x14)
|
||||
#define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x134)
|
||||
|
||||
#define QSERDES_RX1_SIGDET_LVL RX_OFF(1, 0x120)
|
||||
#define QSERDES_RX1_SIGDET_CNTRL RX_OFF(1, 0x11C)
|
||||
#define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL RX_OFF(1, 0x124)
|
||||
#define QSERDES_RX1_RX_BAND RX_OFF(1, 0x128)
|
||||
#define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN RX_OFF(1, 0x30)
|
||||
#define QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(1, 0x34)
|
||||
#define QSERDES_RX1_UCDR_PI_CONTROLS RX_OFF(1, 0x44)
|
||||
#define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW RX_OFF(1, 0x3C)
|
||||
#define QSERDES_RX1_UCDR_PI_CTRL2 RX_OFF(1, 0x48)
|
||||
#define QSERDES_RX1_RX_TERM_BW RX_OFF(1, 0x80)
|
||||
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1 RX_OFF(1, 0xE8)
|
||||
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(1, 0xEC)
|
||||
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(1, 0xF0)
|
||||
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(1, 0xF4)
|
||||
#define QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(1, 0x110)
|
||||
#define QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2 RX_OFF(1, 0x114)
|
||||
#define QSERDES_RX1_RX_IDAC_MEASURE_TIME RX_OFF(1, 0x100)
|
||||
#define QSERDES_RX1_RX_IDAC_TSETTLE_LOW RX_OFF(1, 0xF8)
|
||||
#define QSERDES_RX1_RX_IDAC_TSETTLE_HIGH RX_OFF(1, 0xFC)
|
||||
#define QSERDES_RX1_RX_MODE_00_LOW RX_OFF(1, 0x170)
|
||||
#define QSERDES_RX1_RX_MODE_00_HIGH RX_OFF(1, 0x174)
|
||||
#define QSERDES_RX1_RX_MODE_00_HIGH2 RX_OFF(1, 0x178)
|
||||
#define QSERDES_RX1_RX_MODE_00_HIGH3 RX_OFF(1, 0x17C)
|
||||
#define QSERDES_RX1_RX_MODE_00_HIGH4 RX_OFF(1, 0x180)
|
||||
#define QSERDES_RX1_RX_MODE_01_LOW RX_OFF(1, 0x184)
|
||||
#define QSERDES_RX1_RX_MODE_01_HIGH RX_OFF(1, 0x188)
|
||||
#define QSERDES_RX1_RX_MODE_01_HIGH2 RX_OFF(1, 0x18C)
|
||||
#define QSERDES_RX1_RX_MODE_01_HIGH3 RX_OFF(1, 0x190)
|
||||
#define QSERDES_RX1_RX_MODE_01_HIGH4 RX_OFF(1, 0x194)
|
||||
#define QSERDES_RX1_RX_MODE_10_LOW RX_OFF(1, 0x198)
|
||||
#define QSERDES_RX1_RX_MODE_10_HIGH RX_OFF(1, 0x19C)
|
||||
#define QSERDES_RX1_RX_MODE_10_HIGH2 RX_OFF(1, 0x1A0)
|
||||
#define QSERDES_RX1_RX_MODE_10_HIGH3 RX_OFF(1, 0x1A4)
|
||||
#define QSERDES_RX1_RX_MODE_10_HIGH4 RX_OFF(1, 0x1A8)
|
||||
#define QSERDES_RX1_DCC_CTRL1 RX_OFF(1, 0x1BC)
|
||||
#define QSERDES_RX1_GM_CAL RX_OFF(1, 0xDC)
|
||||
#define QSERDES_RX1_AC_JTAG_ENABLE RX_OFF(1, 0x68)
|
||||
#define QSERDES_RX1_UCDR_FO_GAIN RX_OFF(1, 0x08)
|
||||
#define QSERDES_RX1_UCDR_SO_GAIN RX_OFF(1, 0x14)
|
||||
#define QSERDES_RX1_RX_INTERFACE_MODE RX_OFF(1, 0x134)
|
||||
|
||||
#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
|
||||
#define QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT BIT(5)
|
||||
|
||||
/*
|
||||
* This structure represents the v4 specific phy.
|
||||
* common_cfg MUST remain the first field in this structure
|
||||
* in case extra fields are added. This way, when calling
|
||||
* get_ufs_qcom_phy() of generic phy, we can extract the
|
||||
* common phy structure (struct ufs_qcom_phy) out of it
|
||||
* regardless of the relevant specific phy.
|
||||
*/
|
||||
struct ufs_qcom_phy_qmp_v4 {
|
||||
struct ufs_qcom_phy common_cfg;
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x11),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xAC),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xDD),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0xE5),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TRAN_DRVR_EMP_EN, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_BAND, 0x18),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x81),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x6F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x09),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x20),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x3F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x7F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x2C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_LOW, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH2, 0xED),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH4, 0x3C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_LOW, 0xE0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH2, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_GM_CAL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_DEBUG_BUS_CLKSEL, 0x1F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_BIST_FIXED_PAT_CTRL, 0x0A),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_no_g4[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x11),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xAC),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xDD),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x35),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TRAN_DRVR_EMP_EN, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_BAND, 0x18),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x1B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xC0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xED),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_LOW, 0xE0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH2, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH4, 0xB1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_LOW, 0xE0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH2, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_DEBUG_BUS_CLKSEL, 0x1F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xD8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWM_GEAR_BAND, 0xAA),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0xE5),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TRAN_DRVR_EMP_EN, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_BAND, 0x18),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0xF1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x81),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x6F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x09),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x20),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x3F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x7F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x2C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_LOW, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH2, 0xED),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH4, 0x3C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_LOW, 0xE0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH2, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_GM_CAL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_no_g4[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x35),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TRAN_DRVR_EMP_EN, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_BAND, 0x18),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0xF1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x1B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0xC0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0x6D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xED),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_LOW, 0xE0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH2, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH4, 0xB1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_LOW, 0xE0),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH2, 0xC8),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x06),
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user