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Merge tag 'v6.0-rc1' into android-mainline

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Linux 6.0-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I2128afdf7110829b70a8c576906092c720749143
This commit is contained in:
Greg Kroah-Hartman 2022-08-23 08:09:22 +02:00
commit 17f82ab1d0
1215 changed files with 138823 additions and 20039 deletions
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1
.clang-format
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@ -516,6 +516,7 @@ ForEachMacros:
- 'of_property_for_each_string'
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
- 'pci_doe_for_each_off'
- 'pcl_for_each_chunk'
- 'pcl_for_each_segment'
- 'pcm_for_each_format'

305
Documentation/ABI/testing/sysfs-bus-cxl
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@ -7,6 +7,7 @@ Description:
all descendant memdevs for unbind. Writing '1' to this attribute
flushes that work.
What: /sys/bus/cxl/devices/memX/firmware_version
Date: December, 2020
KernelVersion: v5.12
@ -16,6 +17,7 @@ Description:
Memory Device Output Payload in the CXL-2.0
specification.
What: /sys/bus/cxl/devices/memX/ram/size
Date: December, 2020
KernelVersion: v5.12
@ -25,6 +27,7 @@ Description:
identically named field in the Identify Memory Device Output
Payload in the CXL-2.0 specification.
What: /sys/bus/cxl/devices/memX/pmem/size
Date: December, 2020
KernelVersion: v5.12
@ -34,6 +37,7 @@ Description:
identically named field in the Identify Memory Device Output
Payload in the CXL-2.0 specification.
What: /sys/bus/cxl/devices/memX/serial
Date: January, 2022
KernelVersion: v5.18
@ -43,6 +47,7 @@ Description:
capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
Memory Device PCIe Capabilities and Extended Capabilities.
What: /sys/bus/cxl/devices/memX/numa_node
Date: January, 2022
KernelVersion: v5.18
@ -52,114 +57,334 @@ Description:
host PCI device for this memory device, emit the CPU node
affinity for this device.
What: /sys/bus/cxl/devices/*/devtype
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
CXL device objects export the devtype attribute which mirrors
the same value communicated in the DEVTYPE environment variable
for uevents for devices on the "cxl" bus.
(RO) CXL device objects export the devtype attribute which
mirrors the same value communicated in the DEVTYPE environment
variable for uevents for devices on the "cxl" bus.
What: /sys/bus/cxl/devices/*/modalias
Date: December, 2021
KernelVersion: v5.18
Contact: linux-cxl@vger.kernel.org
Description:
CXL device objects export the modalias attribute which mirrors
the same value communicated in the MODALIAS environment variable
for uevents for devices on the "cxl" bus.
(RO) CXL device objects export the modalias attribute which
mirrors the same value communicated in the MODALIAS environment
variable for uevents for devices on the "cxl" bus.
What: /sys/bus/cxl/devices/portX/uport
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
CXL port objects are enumerated from either a platform firmware
device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
CXL component registers. The 'uport' symlink connects the CXL
portX object to the device that published the CXL port
(RO) CXL port objects are enumerated from either a platform
firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
port with CXL component registers. The 'uport' symlink connects
the CXL portX object to the device that published the CXL port
capability.
What: /sys/bus/cxl/devices/portX/dportY
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
CXL port objects are enumerated from either a platform firmware
device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
CXL component registers. The 'dportY' symlink identifies one or
more downstream ports that the upstream port may target in its
decode of CXL memory resources. The 'Y' integer reflects the
hardware port unique-id used in the hardware decoder target
list.
(RO) CXL port objects are enumerated from either a platform
firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
port with CXL component registers. The 'dportY' symlink
identifies one or more downstream ports that the upstream port
may target in its decode of CXL memory resources. The 'Y'
integer reflects the hardware port unique-id used in the
hardware decoder target list.
What: /sys/bus/cxl/devices/decoderX.Y
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
CXL decoder objects are enumerated from either a platform
(RO) CXL decoder objects are enumerated from either a platform
firmware description, or a CXL HDM decoder register set in a
PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
Capability Structure). The 'X' in decoderX.Y represents the
cxl_port container of this decoder, and 'Y' represents the
instance id of a given decoder resource.
What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
The 'start' and 'size' attributes together convey the physical
address base and number of bytes mapped in the decoder's decode
window. For decoders of devtype "cxl_decoder_root" the address
range is fixed. For decoders of devtype "cxl_decoder_switch" the
address is bounded by the decode range of the cxl_port ancestor
of the decoder's cxl_port, and dynamically updates based on the
active memory regions in that address space.
(RO) The 'start' and 'size' attributes together convey the
physical address base and number of bytes mapped in the
decoder's decode window. For decoders of devtype
"cxl_decoder_root" the address range is fixed. For decoders of
devtype "cxl_decoder_switch" the address is bounded by the
decode range of the cxl_port ancestor of the decoder's cxl_port,
and dynamically updates based on the active memory regions in
that address space.
What: /sys/bus/cxl/devices/decoderX.Y/locked
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
CXL HDM decoders have the capability to lock the configuration
until the next device reset. For decoders of devtype
"cxl_decoder_root" there is no standard facility to unlock them.
For decoders of devtype "cxl_decoder_switch" a secondary bus
reset, of the PCIe bridge that provides the bus for this
decoders uport, unlocks / resets the decoder.
(RO) CXL HDM decoders have the capability to lock the
configuration until the next device reset. For decoders of
devtype "cxl_decoder_root" there is no standard facility to
unlock them. For decoders of devtype "cxl_decoder_switch" a
secondary bus reset, of the PCIe bridge that provides the bus
for this decoders uport, unlocks / resets the decoder.
What: /sys/bus/cxl/devices/decoderX.Y/target_list
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
Display a comma separated list of the current decoder target
configuration. The list is ordered by the current configured
interleave order of the decoder's dport instances. Each entry in
the list is a dport id.
(RO) Display a comma separated list of the current decoder
target configuration. The list is ordered by the current
configured interleave order of the decoder's dport instances.
Each entry in the list is a dport id.
What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
When a CXL decoder is of devtype "cxl_decoder_root", it
(RO) When a CXL decoder is of devtype "cxl_decoder_root", it
represents a fixed memory window identified by platform
firmware. A fixed window may only support a subset of memory
types. The 'cap_*' attributes indicate whether persistent
memory, volatile memory, accelerator memory, and / or expander
memory may be mapped behind this decoder's memory window.
What: /sys/bus/cxl/devices/decoderX.Y/target_type
Date: June, 2021
KernelVersion: v5.14
Contact: linux-cxl@vger.kernel.org
Description:
When a CXL decoder is of devtype "cxl_decoder_switch", it can
optionally decode either accelerator memory (type-2) or expander
memory (type-3). The 'target_type' attribute indicates the
current setting which may dynamically change based on what
(RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
can optionally decode either accelerator memory (type-2) or
expander memory (type-3). The 'target_type' attribute indicates
the current setting which may dynamically change based on what
memory regions are activated in this decode hierarchy.
What: /sys/bus/cxl/devices/endpointX/CDAT
Date: July, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RO) If this sysfs entry is not present no DOE mailbox was
found to support CDAT data. If it is present and the length of
the data is 0 reading the CDAT data failed. Otherwise the CDAT
data is reported.
What: /sys/bus/cxl/devices/decoderX.Y/mode
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
translates from a host physical address range, to a device local
address range. Device-local address ranges are further split
into a 'ram' (volatile memory) range and 'pmem' (persistent
memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
'mixed', or 'none'. The 'mixed' indication is for error cases
when a decoder straddles the volatile/persistent partition
boundary, and 'none' indicates the decoder is not actively
decoding, or no DPA allocation policy has been set.
'mode' can be written, when the decoder is in the 'disabled'
state, with either 'ram' or 'pmem' to set the boundaries for the
next allocation.
What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
and its 'dpa_size' attribute is non-zero, this attribute
indicates the device physical address (DPA) base address of the
allocation.
What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
translates from a host physical address range, to a device local
address range. The range, base address plus length in bytes, of
DPA allocated to this decoder is conveyed in these 2 attributes.
Allocations can be mutated as long as the decoder is in the
disabled state. A write to 'dpa_size' releases the previous DPA
allocation and then attempts to allocate from the free capacity
in the device partition referred to by 'decoderX.Y/mode'.
Allocate and free requests can only be performed on the highest
instance number disabled decoder with non-zero size. I.e.
allocations are enforced to occur in increasing 'decoderX.Y/id'
order and frees are enforced to occur in decreasing
'decoderX.Y/id' order.
What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RO) The number of targets across which this decoder's host
physical address (HPA) memory range is interleaved. The device
maps every Nth block of HPA (of size ==
'interleave_granularity') to consecutive DPA addresses. The
decoder's position in the interleave is determined by the
device's (endpoint or switch) switch ancestry. For root
decoders their interleave is specified by platform firmware and
they only specify a downstream target order for host bridges.
What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RO) The number of consecutive bytes of host physical address
space this decoder claims at address N before the decode rotates
to the next target in the interleave at address N +
interleave_granularity (assuming N is aligned to
interleave_granularity).
What: /sys/bus/cxl/devices/decoderX.Y/create_pmem_region
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) Write a string in the form 'regionZ' to start the process
of defining a new persistent memory region (interleave-set)
within the decode range bounded by root decoder 'decoderX.Y'.
The value written must match the current value returned from
reading this attribute. An atomic compare exchange operation is
done on write to assign the requested id to a region and
allocate the region-id for the next creation attempt. EBUSY is
returned if the region name written does not match the current
cached value.
What: /sys/bus/cxl/devices/decoderX.Y/delete_region
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(WO) Write a string in the form 'regionZ' to delete that region,
provided it is currently idle / not bound to a driver.
What: /sys/bus/cxl/devices/regionZ/uuid
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) Write a unique identifier for the region. This field must
be set for persistent regions and it must not conflict with the
UUID of another region.
What: /sys/bus/cxl/devices/regionZ/interleave_granularity
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) Set the number of consecutive bytes each device in the
interleave set will claim. The possible interleave granularity
values are determined by the CXL spec and the participating
devices.
What: /sys/bus/cxl/devices/regionZ/interleave_ways
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) Configures the number of devices participating in the
region is set by writing this value. Each device will provide
1/interleave_ways of storage for the region.
What: /sys/bus/cxl/devices/regionZ/size
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) System physical address space to be consumed by the region.
When written trigger the driver to allocate space out of the
parent root decoder's address space. When read the size of the
address space is reported and should match the span of the
region's resource attribute. Size shall be set after the
interleave configuration parameters. Once set it cannot be
changed, only freed by writing 0. The kernel makes no guarantees
that data is maintained over an address space freeing event, and
there is no guarantee that a free followed by an allocate
results in the same address being allocated.
What: /sys/bus/cxl/devices/regionZ/resource
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RO) A region is a contiguous partition of a CXL root decoder
address space. Region capacity is allocated by writing to the
size attribute, the resulting physical address space determined
by the driver is reflected here. It is therefore not useful to
read this before writing a value to the size attribute.
What: /sys/bus/cxl/devices/regionZ/target[0..N]
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) Write an endpoint decoder object name to 'targetX' where X
is the intended position of the endpoint device in the region
interleave and N is the 'interleave_ways' setting for the
region. ENXIO is returned if the write results in an impossible
to map decode scenario, like the endpoint is unreachable at that
position relative to the root decoder interleave. EBUSY is
returned if the position in the region is already occupied, or
if the region is not in a state to accept interleave
configuration changes. EINVAL is returned if the object name is
not an endpoint decoder. Once all positions have been
successfully written a final validation for decode conflicts is
performed before activating the region.
What: /sys/bus/cxl/devices/regionZ/commit
Date: May, 2022
KernelVersion: v5.20
Contact: linux-cxl@vger.kernel.org
Description:
(RW) Write a boolean 'true' string value to this attribute to
trigger the region to transition from the software programmed
state to the actively decoding in hardware state. The commit
operation in addition to validating that the region is in proper
configured state, validates that the decoders are being
committed in spec mandated order (last committed decoder id +
1), and checks that the hardware accepts the commit request.
Reading this value indicates whether the region is committed or
not.

2
Documentation/ABI/testing/sysfs-driver-xen-blkback
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@ -42,5 +42,5 @@ KernelVersion: 5.10
Contact: Maximilian Heyne <mheyne@amazon.de>
Description:
Whether to enable the persistent grants feature or not. Note
that this option only takes effect on newly created backends.
that this option only takes effect on newly connected backends.
The default is Y (enable).

2
Documentation/ABI/testing/sysfs-driver-xen-blkfront
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@ -15,5 +15,5 @@ KernelVersion: 5.10
Contact: Maximilian Heyne <mheyne@amazon.de>
Description:
Whether to enable the persistent grants feature or not. Note
that this option only takes effect on newly created frontends.
that this option only takes effect on newly connected frontends.
The default is Y (enable).

2
Documentation/PCI/endpoint/index.rst
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@ -13,6 +13,8 @@ PCI Endpoint Framework
pci-test-howto
pci-ntb-function
pci-ntb-howto
pci-vntb-function
pci-vntb-howto
function/binding/pci-test
function/binding/pci-ntb

129
Documentation/PCI/endpoint/pci-vntb-function.rst Normal file
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@ -0,0 +1,129 @@
.. SPDX-License-Identifier: GPL-2.0
=================
PCI vNTB Function
=================
:Author: Frank Li <Frank.Li@nxp.com>
The difference between PCI NTB function and PCI vNTB function is
PCI NTB function need at two endpoint instances and connect HOST1
and HOST2.
PCI vNTB function only use one host and one endpoint(EP), use NTB
connect EP and PCI host
.. code-block:: text
+------------+ +---------------------------------------+
| | | |
+------------+ | +--------------+
| NTB | | | NTB |
| NetDev | | | NetDev |
+------------+ | +--------------+
| NTB | | | NTB |
| Transfer | | | Transfer |
+------------+ | +--------------+
| | | | |
| PCI NTB | | | |
| EPF | | | |
| Driver | | | PCI Virtual |
| | +---------------+ | NTB Driver |
| | | PCI EP NTB |<------>| |
| | | FN Driver | | |
+------------+ +---------------+ +--------------+
| | | | | |
| PCI BUS | <-----> | PCI EP BUS | | Virtual PCI |
| | PCI | | | BUS |
+------------+ +---------------+--------+--------------+
PCI RC PCI EP
Constructs used for Implementing vNTB
=====================================
1) Config Region
2) Self Scratchpad Registers
3) Peer Scratchpad Registers
4) Doorbell (DB) Registers
5) Memory Window (MW)
Config Region:
--------------
It is same as PCI NTB Function driver
Scratchpad Registers:
---------------------
It is appended after Config region.
.. code-block:: text
+--------------------------------------------------+ Base
| |
| |
| |
| Common Config Register |
| |
| |
| |
+-----------------------+--------------------------+ Base + span_offset
| | |
| Peer Span Space | Span Space |
| | |
| | |
+-----------------------+--------------------------+ Base + span_offset
| | | + span_count * 4
| | |
| Span Space | Peer Span Space |
| | |
+-----------------------+--------------------------+
Virtual PCI Pcie Endpoint
NTB Driver NTB Driver
Doorbell Registers:
-------------------
Doorbell Registers are used by the hosts to interrupt each other.
Memory Window:
--------------
Actual transfer of data between the two hosts will happen using the
memory window.
Modeling Constructs:
====================
32-bit BARs.
====== ===============
BAR NO CONSTRUCTS USED
====== ===============
BAR0 Config Region
BAR1 Doorbell
BAR2 Memory Window 1
BAR3 Memory Window 2
BAR4 Memory Window 3
BAR5 Memory Window 4
====== ===============
64-bit BARs.
====== ===============================
BAR NO CONSTRUCTS USED
====== ===============================
BAR0 Config Region + Scratchpad
BAR1
BAR2 Doorbell
BAR3
BAR4 Memory Window 1
BAR5
====== ===============================

167
Documentation/PCI/endpoint/pci-vntb-howto.rst Normal file
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@ -0,0 +1,167 @@
.. SPDX-License-Identifier: GPL-2.0
===================================================================
PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
===================================================================
:Author: Frank Li <Frank.Li@nxp.com>
This document is a guide to help users use pci-epf-vntb function driver
and ntb_hw_epf host driver for NTB functionality. The list of steps to
be followed in the host side and EP side is given below. For the hardware
configuration and internals of NTB using configurable endpoints see
Documentation/PCI/endpoint/pci-vntb-function.rst
Endpoint Device
===============
Endpoint Controller Devices
---------------------------
To find the list of endpoint controller devices in the system::
# ls /sys/class/pci_epc/
5f010000.pcie_ep
If PCI_ENDPOINT_CONFIGFS is enabled::
# ls /sys/kernel/config/pci_ep/controllers
5f010000.pcie_ep
Endpoint Function Drivers
-------------------------
To find the list of endpoint function drivers in the system::
# ls /sys/bus/pci-epf/drivers
pci_epf_ntb pci_epf_test pci_epf_vntb
If PCI_ENDPOINT_CONFIGFS is enabled::
# ls /sys/kernel/config/pci_ep/functions
pci_epf_ntb pci_epf_test pci_epf_vntb
Creating pci-epf-vntb Device
----------------------------
PCI endpoint function device can be created using the configfs. To create
pci-epf-vntb device, the following commands can be used::
# mount -t configfs none /sys/kernel/config
# cd /sys/kernel/config/pci_ep/
# mkdir functions/pci_epf_vntb/func1
The "mkdir func1" above creates the pci-epf-ntb function device that will
be probed by pci_epf_vntb driver.
The PCI endpoint framework populates the directory with the following
configurable fields::
# ls functions/pci_epf_ntb/func1
baseclass_code deviceid msi_interrupts pci-epf-ntb.0
progif_code secondary subsys_id vendorid
cache_line_size interrupt_pin msix_interrupts primary
revid subclass_code subsys_vendor_id
The PCI endpoint function driver populates these entries with default values
when the device is bound to the driver. The pci-epf-vntb driver populates
vendorid with 0xffff and interrupt_pin with 0x0001::
# cat functions/pci_epf_vntb/func1/vendorid
0xffff
# cat functions/pci_epf_vntb/func1/interrupt_pin
0x0001
Configuring pci-epf-vntb Device
-------------------------------
The user can configure the pci-epf-vntb device using its configfs entry. In order
to change the vendorid and the deviceid, the following
commands can be used::
# echo 0x1957 > functions/pci_epf_vntb/func1/vendorid
# echo 0x0809 > functions/pci_epf_vntb/func1/deviceid
In order to configure NTB specific attributes, a new sub-directory to func1
should be created::
# mkdir functions/pci_epf_vntb/func1/pci_epf_vntb.0/
The NTB function driver will populate this directory with various attributes
that can be configured by the user::
# ls functions/pci_epf_vntb/func1/pci_epf_vntb.0/
db_count mw1 mw2 mw3 mw4 num_mws
spad_count
A sample configuration for NTB function is given below::
# echo 4 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/db_count
# echo 128 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/spad_count
# echo 1 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/num_mws
# echo 0x100000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1
A sample configuration for virtual NTB driver for virutal PCI bus::
# echo 0x1957 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_vid
# echo 0x080A > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_pid
# echo 0x10 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vbus_number
Binding pci-epf-ntb Device to EP Controller
--------------------------------------------
NTB function device should be attached to PCI endpoint controllers
connected to the host.
# ln -s controllers/5f010000.pcie_ep functions/pci-epf-ntb/func1/primary
Once the above step is completed, the PCI endpoint controllers are ready to
establish a link with the host.
Start the Link
--------------
In order for the endpoint device to establish a link with the host, the _start_
field should be populated with '1'. For NTB, both the PCI endpoint controllers
should establish link with the host (imx8 don't need this steps)::
# echo 1 > controllers/5f010000.pcie_ep/start
RootComplex Device
==================
lspci Output at Host side
-------------------------
Note that the devices listed here correspond to the values populated in
"Creating pci-epf-ntb Device" section above::
# lspci
00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01)
01:00.0 RAM memory: Freescale Semiconductor Inc Device 0809
Endpoint Device / Virtual PCI bus
=================================
lspci Output at EP Side / Virtual PCI bus
-----------------------------------------
Note that the devices listed here correspond to the values populated in
"Creating pci-epf-ntb Device" section above::
# lspci
10:00.0 Unassigned class [ffff]: Dawicontrol Computersysteme GmbH Device 1234 (rev ff)
Using ntb_hw_epf Device
-----------------------
The host side software follows the standard NTB software architecture in Linux.
All the existing client side NTB utilities like NTB Transport Client and NTB
Netdev, NTB Ping Pong Test Client and NTB Tool Test Client can be used with NTB
function device.
For more information on NTB see
:doc:`Non-Transparent Bridge <../../driver-api/ntb>`

8
Documentation/admin-guide/hw-vuln/spectre.rst
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@ -422,6 +422,14 @@ The possible values in this file are:
'RSB filling' Protection of RSB on context switch enabled
============= ===========================================
- EIBRS Post-barrier Return Stack Buffer (PBRSB) protection status:
=========================== =======================================================
'PBRSB-eIBRS: SW sequence' CPU is affected and protection of RSB on VMEXIT enabled
'PBRSB-eIBRS: Vulnerable' CPU is vulnerable
'PBRSB-eIBRS: Not affected' CPU is not affected by PBRSB
=========================== =======================================================
Full mitigation might require a microcode update from the CPU
vendor. When the necessary microcode is not available, the kernel will
report vulnerability.

36
Documentation/admin-guide/kernel-parameters.txt
View File

@ -1735,12 +1735,13 @@
hugetlb_free_vmemmap=
[KNL] Reguires CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
enabled.
Control if HugeTLB Vmemmap Optimization (HVO) is enabled.
Allows heavy hugetlb users to free up some more
memory (7 * PAGE_SIZE for each 2MB hugetlb page).
Format: { [oO][Nn]/Y/y/1 | [oO][Ff]/N/n/0 (default) }
Format: { on | off (default) }
[oO][Nn]/Y/y/1: enable the feature
[oO][Ff]/N/n/0: disable the feature
on: enable HVO
off: disable HVO
Built with CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y,
the default is on.
@ -5281,20 +5282,33 @@
Speculative Code Execution with Return Instructions)
vulnerability.
AMD-based UNRET and IBPB mitigations alone do not stop
sibling threads from influencing the predictions of other
sibling threads. For that reason, STIBP is used on pro-
cessors that support it, and mitigate SMT on processors
that don't.
off - no mitigation
auto - automatically select a migitation
auto,nosmt - automatically select a mitigation,
disabling SMT if necessary for
the full mitigation (only on Zen1
and older without STIBP).
ibpb - mitigate short speculation windows on
basic block boundaries too. Safe, highest
perf impact.
unret - force enable untrained return thunks,
only effective on AMD f15h-f17h
based systems.
unret,nosmt - like unret, will disable SMT when STIBP
is not available.
ibpb - On AMD, mitigate short speculation
windows on basic block boundaries too.
Safe, highest perf impact. It also
enables STIBP if present. Not suitable
on Intel.
ibpb,nosmt - Like "ibpb" above but will disable SMT
when STIBP is not available. This is
the alternative for systems which do not
have STIBP.
unret - Force enable untrained return thunks,
only effective on AMD f15h-f17h based
systems.
unret,nosmt - Like unret, but will disable SMT when STIBP
is not available. This is the alternative for
systems which do not have STIBP.
Selecting 'auto' will choose a mitigation method at run
time according to the CPU.

4
Documentation/admin-guide/mm/hugetlbpage.rst
View File

@ -164,8 +164,8 @@ default_hugepagesz
will all result in 256 2M huge pages being allocated. Valid default
huge page size is architecture dependent.
hugetlb_free_vmemmap
When CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP is set, this enables optimizing
unused vmemmap pages associated with each HugeTLB page.
When CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP is set, this enables HugeTLB
Vmemmap Optimization (HVO).
When multiple huge page sizes are supported, ``/proc/sys/vm/nr_hugepages``
indicates the current number of pre-allocated huge pages of the default size.

4
Documentation/admin-guide/mm/memory-hotplug.rst
View File

@ -653,8 +653,8 @@ block might fail:
- Concurrent activity that operates on the same physical memory area, such as
allocating gigantic pages, can result in temporary offlining failures.
- Out of memory when dissolving huge pages, especially when freeing unused
vmemmap pages associated with each hugetlb page is enabled.
- Out of memory when dissolving huge pages, especially when HugeTLB Vmemmap
Optimization (HVO) is enabled.
Offlining code may be able to migrate huge page contents, but may not be able
to dissolve the source huge page because it fails allocating (unmovable) pages

3
Documentation/admin-guide/sysctl/vm.rst
View File

@ -569,8 +569,7 @@ This knob is not available when the size of 'struct page' (a structure defined
in include/linux/mm_types.h) is not power of two (an unusual system config could
result in this).
Enable (set to 1) or disable (set to 0) the feature of optimizing vmemmap pages
associated with each HugeTLB page.
Enable (set to 1) or disable (set to 0) HugeTLB Vmemmap Optimization (HVO).
Once enabled, the vmemmap pages of subsequent allocation of HugeTLB pages from
buddy allocator will be optimized (7 pages per 2MB HugeTLB page and 4095 pages

25
Documentation/bpf/bpf_design_QA.rst
View File

@ -214,6 +214,12 @@ A: NO. Tracepoints are tied to internal implementation details hence they are
subject to change and can break with newer kernels. BPF programs need to change
accordingly when this happens.
Q: Are places where kprobes can attach part of the stable ABI?
--------------------------------------------------------------
A: NO. The places to which kprobes can attach are internal implementation
details, which means that they are subject to change and can break with
newer kernels. BPF programs need to change accordingly when this happens.
Q: How much stack space a BPF program uses?
-------------------------------------------
A: Currently all program types are limited to 512 bytes of stack
@ -273,3 +279,22 @@ cc (congestion-control) implementations. If any of these kernel
functions has changed, both the in-tree and out-of-tree kernel tcp cc
implementations have to be changed. The same goes for the bpf
programs and they have to be adjusted accordingly.
Q: Attaching to arbitrary kernel functions is an ABI?
-----------------------------------------------------
Q: BPF programs can be attached to many kernel functions. Do these
kernel functions become part of the ABI?
A: NO.
The kernel function prototypes will change, and BPF programs attaching to
them will need to change. The BPF compile-once-run-everywhere (CO-RE)
should be used in order to make it easier to adapt your BPF programs to
different versions of the kernel.
Q: Marking a function with BTF_ID makes that function an ABI?
-------------------------------------------------------------
A: NO.
The BTF_ID macro does not cause a function to become part of the ABI
any more than does the EXPORT_SYMBOL_GPL macro.

4
Documentation/devicetree/bindings/Makefile
View File

@ -42,9 +42,7 @@ quiet_cmd_chk_bindings = CHKDT $@
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
printf '%s\n' $(real-prereqs), \
$(find_all_cmd)) > $$f ; \
$(find_all_cmd) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f

15
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
View File

@ -25,21 +25,6 @@ System Timer (ST) required properties:
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
it also can be "microchip,sam9x60-rstc"
- reg: Should contain registers location and length
- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
"atmel,at91sam9260-sdramc",

15
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
View File

@ -20,13 +20,24 @@ properties:
compatible:
const: google,cros-ec-typec
connector:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^connector@[0-9a-f]+$':
$ref: /schemas/connector/usb-connector.yaml#
unevaluatedProperties: false
properties:
reg:
maxItems: 1
required:
- compatible
additionalProperties: true #fixme
additionalProperties: false
examples:
- |+

1
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
View File

@ -25,6 +25,7 @@ properties:
- description: v2 of CPUFREQ HW (EPSS)
items:
- enum:
- qcom,sm6375-cpufreq-epss
- qcom,sm8250-cpufreq-epss
- const: qcom,cpufreq-epss

7
Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
View File

@ -22,6 +22,13 @@ select:
compatible:
contains:
enum:
- qcom,apq8064
- qcom,apq8096
- qcom,ipq8064
- qcom,msm8939
- qcom,msm8960
- qcom,msm8974
- qcom,msm8996
- qcom,qcs404
required:
- compatible

27
Documentation/devicetree/bindings/display/ilitek,ili9341.txt
View File

@ -1,27 +0,0 @@
Ilitek ILI9341 display panels
This binding is for display panels using an Ilitek ILI9341 controller in SPI
mode.
Required properties:
- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
- dc-gpios: D/C pin
- reset-gpios: Reset pin
The node for this driver must be a child node of a SPI controller, hence
all mandatory properties described in ../spi/spi-bus.txt must be specified.
Optional properties:
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
- backlight: phandle of the backlight device attached to the panel
Example:
display@0{
compatible = "adafruit,yx240qv29", "ilitek,ili9341";
reg = <0>;
spi-max-frequency = <32000000>;
dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
rotation = <270>;
backlight = <&backlight>;
};

49
Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
View File

@ -21,8 +21,10 @@ properties:
compatible:
items:
- enum:
- adafruit,yx240qv29
# ili9341 240*320 Color on stm32f429-disco board
- st,sf-tc240t-9370-t
- canaan,kd233-tft
- const: ilitek,ili9341
reg: true
@ -47,31 +49,50 @@ properties:
vddi-led-supply:
description: Voltage supply for the LED driver (1.65 .. 3.3 V)
additionalProperties: false
unevaluatedProperties: false
required:
- compatible
- reg
- dc-gpios
- port
if:
properties:
compatible:
contains:
enum:
- st,sf-tc240t-9370-t
then:
required:
- port
examples:
- |+
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
panel: display@0 {
compatible = "st,sf-tc240t-9370-t",
"ilitek,ili9341";
reg = <0>;
spi-3wire;
spi-max-frequency = <10000000>;
dc-gpios = <&gpiod 13 0>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
compatible = "st,sf-tc240t-9370-t",
"ilitek,ili9341";
reg = <0>;
spi-3wire;
spi-max-frequency = <10000000>;
dc-gpios = <&gpiod 13 0>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
display@1{
compatible = "adafruit,yx240qv29", "ilitek,ili9341";
reg = <1>;
spi-max-frequency = <10000000>;
dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
rotation = <270>;
backlight = <&backlight>;
};
};
...

1
Documentation/devicetree/bindings/display/simple-framebuffer.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple Framebuffer Device Tree Bindings
maintainers:
- Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
- Hans de Goede <hdegoede@redhat.com>
description: |+

4
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
View File

@ -46,6 +46,10 @@ properties:
maximum: 32
default: 16
gpio-line-names:
minItems: 1
maxItems: 32
gpio-controller: true
required:

6
Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
View File

@ -19,7 +19,13 @@ properties:
oneOf:
- enum:
- x-powers,axp209-gpio
- x-powers,axp221-gpio
- x-powers,axp813-gpio
- items:
- enum:
- x-powers,axp223-gpio
- x-powers,axp809-gpio
- const: x-powers,axp221-gpio
- items:
- const: x-powers,axp803-gpio
- const: x-powers,axp813-gpio

1
Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml
View File

@ -8,7 +8,6 @@ title: Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Beniamin Bia <beniamin.bia@analog.com>
description: |
Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor

1
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
View File

@ -27,6 +27,7 @@ properties:
- const: mediatek,mt8173-i2c
- const: mediatek,mt8183-i2c
- const: mediatek,mt8186-i2c
- const: mediatek,mt8188-i2c
- const: mediatek,mt8192-i2c
- items:
- enum:

96
Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
View File

@ -1,96 +0,0 @@
Qualcomm Camera Control Interface (CCI) I2C controller
PROPERTIES:
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,msm8916-cci"
"qcom,msm8974-cci"
"qcom,msm8996-cci"
"qcom,sdm845-cci"
"qcom,sm8250-cci"
"qcom,sm8450-cci"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: base address CCI I2C controller and length of memory
mapped region.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: specifies the CCI I2C interrupt. The format of the
specifier is defined by the binding document describing
the node's interrupt parent.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: a list of phandle, should contain an entry for each
entries in clock-names.
- clock-names
Usage: required
Value type: <string>
Definition: a list of clock names, must include "cci" clock.
- power-domains
Usage: required for "qcom,msm8996-cci"
Value type: <prop-encoded-array>
Definition:
SUBNODES:
The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8974,
msm8996, sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0"
and "i2c-bus@1".
PROPERTIES:
- reg:
Usage: required
Value type: <u32>
Definition: Index of the CCI bus/master
- clock-frequency:
Usage: optional
Value type: <u32>
Definition: Desired I2C bus clock frequency in Hz, defaults to 100
kHz if omitted.
Example:
cci@a0c000 {
compatible = "qcom,msm8996-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0c000 0x1000>;
interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
<&mmcc CAMSS_TOP_AHB_CLK>,
<&mmcc CAMSS_CCI_AHB_CLK>,
<&mmcc CAMSS_CCI_CLK>,
<&mmcc CAMSS_AHB_CLK>;
clock-names = "mmss_mmagic_ahb",
"camss_top_ahb",
"cci_ahb",
"cci",
"camss_ahb";
i2c-bus@0 {
reg = <0>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c-bus@1 {
reg = <1>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
};

242
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml Normal file
View File

@ -0,0 +1,242 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Control Interface (CCI) I2C controller
maintainers:
- Loic Poulain <loic.poulain@linaro.org>
- Robert Foss <robert.foss@linaro.org>
properties:
compatible:
enum:
- qcom,msm8916-cci
- qcom,msm8974-cci
- qcom,msm8996-cci
- qcom,sdm845-cci
- qcom,sm8250-cci
- qcom,sm8450-cci
"#address-cells":
const: 1
"#size-cells":
const: 0
clocks:
minItems: 4
maxItems: 6
clock-names:
minItems: 4
maxItems: 6
interrupts:
maxItems: 1
power-domains:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^i2c-bus@[01]$":
$ref: /schemas/i2c/i2c-controller.yaml#
unevaluatedProperties: false
properties:
reg:
maxItems: 1
clock-frequency:
default: 100000
required:
- compatible
- clock-names
- clocks
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-cci
then:
required:
- power-domains
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8916-cci
then:
properties:
i2c-bus@1: false
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8916-cci
- qcom,msm8996-cci
then:
properties:
clocks:
maxItems: 4
clock-names:
items:
- const: camss_top_ahb
- const: cci_ahb
- const: cci
- const: camss_ahb
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm845-cci
then:
properties:
clocks:
minItems: 6
clock-names:
items:
- const: camnoc_axi
- const: soc_ahb
- const: slow_ahb_src
- const: cpas_ahb
- const: cci
- const: cci_src
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8250-cci
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: camnoc_axi
- const: slow_ahb_src
- const: cpas_ahb
- const: cci
- const: cci_src
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
cci@ac4a000 {
reg = <0x0ac4a000 0x4000>;
compatible = "qcom,sdm845-cci";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
power-domains = <&clock_camcc TITAN_TOP_GDSC>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CCI_CLK>,
<&clock_camcc CAM_CC_CCI_CLK_SRC>;
clock-names = "camnoc_axi",
"soc_ahb",
"slow_ahb_src",
"cpas_ahb",
"cci",
"cci_src";
assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_CCI_CLK>;
assigned-clock-rates = <80000000>,
<37500000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cci0_default &cci1_default>;
pinctrl-1 = <&cci0_sleep &cci1_sleep>;
i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
camera@10 {
compatible = "ovti,ov8856";
reg = <0x10>;
reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_default>;
clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
clock-names = "xvclk";
clock-frequency = <19200000>;
dovdd-supply = <&vreg_lvs1a_1p8>;
avdd-supply = <&cam0_avdd_2v8>;
dvdd-supply = <&cam0_dvdd_1v2>;
port {
ov8856_ep: endpoint {
link-frequencies = /bits/ 64 <360000000 180000000>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csiphy0_ep>;
};
};
};
};
cci_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
camera@60 {
compatible = "ovti,ov7251";
reg = <0x60>;
enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam3_default>;
clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&vreg_lvs1a_1p8>;
vdda-supply = <&cam3_avdd_2v8>;
port {
ov7251_ep: endpoint {
data-lanes = <0 1>;
remote-endpoint = <&csiphy3_ep>;
};
};
};
};
};

1
Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MMA7455 and MMA7456 three axis accelerometers
maintainers:
- Joachim Eastwood <manabian@gmail.com>
- Jonathan Cameron <jic23@kernel.org>
description:

2
Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD7091R5 4-Channel 12-Bit ADC
maintainers:
- Beniamin Bia <beniamin.bia@analog.com>
- Michael Hennerich <michael.hennerich@analog.com>
description: |
Analog Devices AD7091R5 4-Channel 12-Bit ADC

3
Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml
View File

@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD7606 Simultaneous Sampling ADC
maintainers:
- Beniamin Bia <beniamin.bia@analog.com>
- Stefan Popa <stefan.popa@analog.com>
- Michael Hennerich <michael.hennerich@analog.com>
description: |
Analog Devices AD7606 Simultaneous Sampling ADC

2
Documentation/devicetree/bindings/iio/adc/nxp,lpc1850-adc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC1850 ADC bindings
maintainers:
- Joachim Eastwood <manabian@gmail.com>
- Jonathan Cameron <jic23@kernel.org>
description:
Supports the ADC found on the LPC1850 SoC.

2
Documentation/devicetree/bindings/iio/adc/ti,adc108s102.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments ADC108S102 and ADC128S102
maintainers:
- Bogdan Pricop <bogdan.pricop@emutex.com>
- Jonathan Cameron <jic23@kernel.org>
description: |
Family of 8 channel, 10/12 bit, SPI, single ended ADCs.

2
Documentation/devicetree/bindings/iio/adc/ti,ads124s08.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments' ads124s08 and ads124s06 ADC chip
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
properties:
compatible:

1
Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml
View File

@ -8,7 +8,6 @@ title: HMC425A 6-bit Digital Step Attenuator
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Beniamin Bia <beniamin.bia@analog.com>
description: |
Digital Step Attenuator IIO device with gpio interface.

2
Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale FXOS8700 Inertial Measurement Unit
maintainers:
- Robert Jones <rjones@gateworks.com>
- Jonathan Cameron <jic23@kernel.org>
description: |
Accelerometer and magnetometer combo device with an i2c and SPI interface.

2
Documentation/devicetree/bindings/input/adc-joystick.yaml
View File

@ -45,6 +45,7 @@ additionalProperties: false
patternProperties:
"^axis@[0-9a-f]+$":
type: object
$ref: input.yaml#
description: >
Represents a joystick axis bound to the given ADC channel.
For each entry in the io-channels list, one axis subnode with a matching
@ -57,7 +58,6 @@ patternProperties:
description: Index of an io-channels list entry bound to this axis.
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: EV_ABS specific event code generated by the axis.
abs-range:

67
Documentation/devicetree/bindings/input/adc-keys.txt
View File

@ -1,67 +0,0 @@
ADC attached resistor ladder buttons
------------------------------------
Required properties:
- compatible: "adc-keys"
- io-channels: Phandle to an ADC channel
- io-channel-names = "buttons";
- keyup-threshold-microvolt: Voltage above or equal to which all the keys are
considered up.
Optional properties:
- poll-interval: Poll interval time in milliseconds
- autorepeat: Boolean, Enable auto repeat feature of Linux input
subsystem.
Each button (key) is represented as a sub-node of "adc-keys":
Required subnode-properties:
- label: Descriptive name of the key.
- linux,code: Keycode to emit.
- press-threshold-microvolt: voltage above or equal to which this key is
considered pressed.
No two values of press-threshold-microvolt may be the same.
All values of press-threshold-microvolt must be less than
keyup-threshold-microvolt.
Example:
#include <dt-bindings/input/input.h>
adc-keys {
compatible = "adc-keys";
io-channels = <&lradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <2000000>;
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <1500000>;
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <1000000>;
};
button-enter {
label = "Enter";
linux,code = <KEY_ENTER>;
press-threshold-microvolt = <500000>;
};
};
+--------------------------------+------------------------+
| 2.000.000 <= value | no key pressed |
+--------------------------------+------------------------+
| 1.500.000 <= value < 2.000.000 | KEY_VOLUMEUP pressed |
+--------------------------------+------------------------+
| 1.000.000 <= value < 1.500.000 | KEY_VOLUMEDOWN pressed |
+--------------------------------+------------------------+
| 500.000 <= value < 1.000.000 | KEY_ENTER pressed |
+--------------------------------+------------------------+
| value < 500.000 | no key pressed |
+--------------------------------+------------------------+

103
Documentation/devicetree/bindings/input/adc-keys.yaml Normal file
View File

@ -0,0 +1,103 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/adc-keys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADC attached resistor ladder buttons
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
allOf:
- $ref: input.yaml#
properties:
compatible:
const: adc-keys
io-channels:
maxItems: 1
io-channel-names:
const: buttons
keyup-threshold-microvolt:
description:
Voltage above or equal to which all the keys are considered up.
poll-interval: true
autorepeat: true
patternProperties:
'^button-':
type: object
$ref: input.yaml#
additionalProperties: false
description:
Each button (key) is represented as a sub-node.
properties:
label: true
linux,code: true
press-threshold-microvolt:
description:
Voltage above or equal to which this key is considered pressed. No
two values of press-threshold-microvolt may be the same. All values
of press-threshold-microvolt must be less than
keyup-threshold-microvolt.
required:
- linux,code
- press-threshold-microvolt
required:
- compatible
- io-channels
- io-channel-names
- keyup-threshold-microvolt
additionalProperties: false
examples:
- |
#include <dt-bindings/input/input.h>
// +--------------------------------+------------------------+
// | 2.000.000 <= value | no key pressed |
// +--------------------------------+------------------------+
// | 1.500.000 <= value < 2.000.000 | KEY_VOLUMEUP pressed |
// +--------------------------------+------------------------+
// | 1.000.000 <= value < 1.500.000 | KEY_VOLUMEDOWN pressed |
// +--------------------------------+------------------------+
// | 500.000 <= value < 1.000.000 | KEY_ENTER pressed |
// +--------------------------------+------------------------+
// | value < 500.000 | no key pressed |
// +--------------------------------+------------------------+
adc-keys {
compatible = "adc-keys";
io-channels = <&lradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <2000000>;
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <1500000>;
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <1000000>;
};
button-enter {
label = "Enter";
linux,code = <KEY_ENTER>;
press-threshold-microvolt = <500000>;
};
};
...

5
Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
View File

@ -44,14 +44,13 @@ properties:
patternProperties:
"^button-[0-9]+$":
type: object
$ref: input.yaml#
properties:
label:
$ref: /schemas/types.yaml#/definitions/string
description: Descriptive name of the key
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Keycode to emit
linux,code: true
channel:
$ref: /schemas/types.yaml#/definitions/uint32

1
Documentation/devicetree/bindings/input/ariel-pwrbutton.yaml
View File

@ -17,6 +17,7 @@ description: |
allOf:
- $ref: input.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:

41
Documentation/devicetree/bindings/input/azoteq,iqs7222.yaml
View File

@ -37,10 +37,6 @@ properties:
device is temporarily held in hardware reset prior to initialization if
this property is present.
azoteq,rf-filt-enable:
type: boolean
description: Enables the device's internal RF filter.
azoteq,max-counts:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
@ -421,6 +417,7 @@ patternProperties:
patternProperties:
"^event-(prox|touch)$":
type: object
$ref: input.yaml#
description:
Represents a proximity or touch event reported by the channel.
@ -467,14 +464,9 @@ patternProperties:
The IQS7222B does not feature channel-specific timeouts; the time-
out specified for any one channel applies to all channels.
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Numeric key or switch code associated with the event. Specify
KEY_RESERVED (0) to opt out of event reporting.
linux,code: true
linux,input-type:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 5]
default: 1
description:
@ -537,9 +529,8 @@ patternProperties:
azoteq,bottom-speed:
$ref: /schemas/types.yaml#/definitions/uint32
multipleOf: 4
minimum: 0
maximum: 1020
maximum: 255
description:
Specifies the speed of movement after which coordinate filtering is
linearly reduced.
@ -575,14 +566,13 @@ patternProperties:
patternProperties:
"^event-(press|tap|(swipe|flick)-(pos|neg))$":
type: object
$ref: input.yaml#
description:
Represents a press or gesture (IQS7222A only) event reported by
the slider.
properties:
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric key code associated with the event.
linux,code: true
azoteq,gesture-max-ms:
multipleOf: 4
@ -616,16 +606,15 @@ patternProperties:
azoteq,gpio-select:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 1
maxItems: 3
items:
minimum: 0
maximum: 0
maximum: 2
description: |
Specifies an individual GPIO mapped to a tap, swipe or flick
gesture as follows:
Specifies one or more GPIO mapped to the event as follows:
0: GPIO0
1: GPIO3 (reserved)
2: GPIO4 (reserved)
1: GPIO3 (IQS7222C only)
2: GPIO4 (IQS7222C only)
Note that although multiple events can be mapped to a single
GPIO, they must all be of the same type (proximity, touch or
@ -710,6 +699,14 @@ allOf:
multipleOf: 4
maximum: 1020
patternProperties:
"^event-(press|tap|(swipe|flick)-(pos|neg))$":
properties:
azoteq,gpio-select:
maxItems: 1
items:
maximum: 0
else:
patternProperties:
"^channel-([0-9]|1[0-9])$":
@ -726,8 +723,6 @@ allOf:
azoteq,gesture-dist: false
azoteq,gpio-select: false
required:
- compatible
- reg

4
Documentation/devicetree/bindings/input/fsl,mpr121-touchkey.yaml
View File

@ -57,7 +57,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
mpr121@5a {
touchkey@5a {
compatible = "fsl,mpr121-touchkey";
reg = <0x5a>;
interrupt-parent = <&gpio1>;
@ -77,7 +77,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
mpr121@5a {
touchkey@5a {
compatible = "fsl,mpr121-touchkey";
reg = <0x5a>;
poll-interval = <20>;

197
Documentation/devicetree/bindings/input/gpio-keys.yaml
View File

@ -15,107 +15,106 @@ properties:
- gpio-keys
- gpio-keys-polled
autorepeat: true
label:
description: Name of entire device
poll-interval: true
patternProperties:
".*":
if:
type: object
then:
$ref: input.yaml#
"^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$":
$ref: input.yaml#
properties:
gpios:
maxItems: 1
interrupts:
maxItems: 1
label:
description: Descriptive name of the key.
linux,code:
description: Key / Axis code to emit.
linux,input-type:
default: 1 # EV_KEY
linux,input-value:
description: |
If linux,input-type is EV_ABS or EV_REL then this
value is sent for events this button generates when pressed.
EV_ABS/EV_REL axis will generate an event with a value of 0
when all buttons with linux,input-type == type and
linux,code == axis are released. This value is interpreted
as a signed 32 bit value, e.g. to make a button generate a
value of -1 use:
linux,input-value = <0xffffffff>; /* -1 */
$ref: /schemas/types.yaml#/definitions/uint32
debounce-interval:
description:
Debouncing interval time in milliseconds. If not specified defaults to 5.
$ref: /schemas/types.yaml#/definitions/uint32
default: 5
wakeup-source:
description: Button can wake-up the system.
wakeup-event-action:
description: |
Specifies whether the key should wake the system when asserted, when
deasserted, or both. This property is only valid for keys that wake up the
system (e.g., when the "wakeup-source" property is also provided).
Supported values are defined in linux-event-codes.h:
EV_ACT_ANY - both asserted and deasserted
EV_ACT_ASSERTED - asserted
EV_ACT_DEASSERTED - deasserted
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
linux,can-disable:
description:
Indicates that button is connected to dedicated (not shared) interrupt
which can be disabled to suppress events from the button.
type: boolean
required:
- linux,code
anyOf:
- required:
- interrupts
- required:
- interrupts-extended
- required:
- gpios
dependencies:
wakeup-event-action: [ wakeup-source ]
linux,input-value: [ gpios ]
unevaluatedProperties: false
allOf:
- $ref: input.yaml#
- if:
properties:
gpios:
maxItems: 1
interrupts:
maxItems: 1
label:
description: Descriptive name of the key.
linux,code:
description: Key / Axis code to emit.
$ref: /schemas/types.yaml#/definitions/uint32
linux,input-type:
description:
Specify event type this button/key generates. If not specified defaults to
<1> == EV_KEY.
$ref: /schemas/types.yaml#/definitions/uint32
default: 1
linux,input-value:
description: |
If linux,input-type is EV_ABS or EV_REL then this
value is sent for events this button generates when pressed.
EV_ABS/EV_REL axis will generate an event with a value of 0
when all buttons with linux,input-type == type and
linux,code == axis are released. This value is interpreted
as a signed 32 bit value, e.g. to make a button generate a
value of -1 use:
linux,input-value = <0xffffffff>; /* -1 */
$ref: /schemas/types.yaml#/definitions/uint32
debounce-interval:
description:
Debouncing interval time in milliseconds. If not specified defaults to 5.
$ref: /schemas/types.yaml#/definitions/uint32
default: 5
wakeup-source:
description: Button can wake-up the system.
wakeup-event-action:
description: |
Specifies whether the key should wake the system when asserted, when
deasserted, or both. This property is only valid for keys that wake up the
system (e.g., when the "wakeup-source" property is also provided).
Supported values are defined in linux-event-codes.h:
EV_ACT_ANY - both asserted and deasserted
EV_ACT_ASSERTED - asserted
EV_ACT_DEASSERTED - deasserted
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
linux,can-disable:
description:
Indicates that button is connected to dedicated (not shared) interrupt
which can be disabled to suppress events from the button.
type: boolean
compatible:
const: gpio-keys-polled
then:
required:
- linux,code
anyOf:
- required:
- interrupts
- required:
- gpios
dependencies:
wakeup-event-action: [ wakeup-source ]
linux,input-value: [ gpios ]
unevaluatedProperties: false
if:
properties:
compatible:
const: gpio-keys-polled
then:
properties:
poll-interval:
description:
Poll interval time in milliseconds
$ref: /schemas/types.yaml#/definitions/uint32
required:
- poll-interval
- poll-interval
else:
properties:
poll-interval: false
additionalProperties: false
@ -127,13 +126,13 @@ examples:
compatible = "gpio-keys";
autorepeat;
up {
key-up {
label = "GPIO Key UP";
linux,code = <103>;
gpios = <&gpio1 0 1>;
};
down {
key-down {
label = "GPIO Key DOWN";
linux,code = <108>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;

24
Documentation/devicetree/bindings/input/input.yaml
View File

@ -21,7 +21,26 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
minimum: 0
maximum: 0xff
maximum: 0x2ff
linux,code:
description:
Specifies a single numeric keycode value to be used for reporting
button/switch events. Specify KEY_RESERVED (0) to opt out of event
reporting.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0x2ff
linux,input-type:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 1 # EV_KEY
- 2 # EV_REL
- 3 # EV_ABS
- 5 # EV_SW
description:
Specifies whether the event is to be interpreted as a key, relative,
absolute, or switch.
poll-interval:
description: Poll interval time in milliseconds.
@ -39,4 +58,7 @@ properties:
reset automatically. Device with key pressed reset feature can specify
this property.
dependencies:
linux,input-type: [ "linux,code" ]
additionalProperties: true

17
Documentation/devicetree/bindings/input/iqs269a.yaml
View File

@ -370,6 +370,7 @@ patternProperties:
patternProperties:
"^event-prox(-alt)?$":
type: object
$ref: input.yaml#
description:
Represents a proximity event reported by the channel in response to
a decrease in counts. Node names suffixed with '-alt' instead corre-
@ -396,14 +397,13 @@ patternProperties:
default: 10
description: Specifies the threshold for the event.
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric key or switch code associated with the event.
linux,code: true
additionalProperties: false
"^event-touch(-alt)?$":
type: object
$ref: input.yaml#
description: Represents a touch event reported by the channel.
properties:
@ -421,14 +421,13 @@ patternProperties:
default: 4
description: Specifies the hysteresis for the event.
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric key or switch code associated with the event.
linux,code: true
additionalProperties: false
"^event-deep(-alt)?$":
type: object
$ref: input.yaml#
description: Represents a deep-touch event reported by the channel.
properties:
@ -446,9 +445,7 @@ patternProperties:
default: 0
description: Specifies the hysteresis for the event.
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric key or switch code associated with the event.
linux,code: true
additionalProperties: false
@ -475,7 +472,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
iqs269a@44 {
touch@44 {
#address-cells = <1>;
#size-cells = <0>;

13
Documentation/devicetree/bindings/input/iqs626a.yaml
View File

@ -449,6 +449,7 @@ patternProperties:
patternProperties:
"^event-(prox|touch|deep)(-alt)?$":
type: object
$ref: input.yaml#
description:
Represents a proximity, touch or deep-touch event reported by the
channel in response to a decrease in counts. Node names suffixed with
@ -487,21 +488,15 @@ patternProperties:
Specifies the hysteresis for the event (touch and deep-touch
events only).
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric key or switch code associated with the event.
linux,code: true
linux,input-type:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 5]
description:
Specifies whether the event is to be interpreted as a key (1) or
a switch (5). By default, Hall-channel events are interpreted as
switches and all others are interpreted as keys.
dependencies:
linux,input-type: ["linux,code"]
additionalProperties: false
dependencies:
@ -511,6 +506,7 @@ patternProperties:
"^trackpad-3x[2-3]$":
type: object
$ref: input.yaml#
description:
Represents all channels associated with the trackpad. The channels are
collectively active if the trackpad is defined and inactive otherwise.
@ -679,7 +675,6 @@ patternProperties:
Specifies the raw count filter strength during low-power mode.
linux,keycodes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 6
description: |
@ -751,7 +746,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
iqs626a@44 {
touch@44 {
#address-cells = <1>;
#size-cells = <0>;

9
Documentation/devicetree/bindings/input/iqs62x-keys.yaml
View File

@ -9,6 +9,9 @@ title: Azoteq IQS620A/621/622/624/625 Keys and Switches
maintainers:
- Jeff LaBundy <jeff@labundy.com>
allOf:
- $ref: input.yaml#
description: |
The Azoteq IQS620A, IQS621, IQS622, IQS624 and IQS625 multi-function sensors
feature a variety of self-capacitive, mutual-inductive and Hall-effect sens-
@ -30,7 +33,6 @@ properties:
- azoteq,iqs625-keys
linux,keycodes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 16
description: |
@ -89,15 +91,14 @@ properties:
patternProperties:
"^hall-switch-(north|south)$":
type: object
$ref: input.yaml#
description:
Represents north/south-field Hall-effect sensor touch or proximity
events. Note that north/south-field orientation is reversed on the
IQS620AXzCSR device due to its flip-chip package.
properties:
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric switch code associated with the event.
linux,code: true
azoteq,use-prox:
$ref: /schemas/types.yaml#/definitions/flag

8
Documentation/devicetree/bindings/input/max77650-onkey.yaml
View File

@ -16,15 +16,15 @@ description: |
The onkey controller is represented as a sub-node of the PMIC node on
the device tree.
allOf:
- $ref: input.yaml#
properties:
compatible:
const: maxim,max77650-onkey
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The key-code to be reported when the key is pressed. Defaults
to KEY_POWER.
default: 116 # KEY_POWER
maxim,onkey-slide:
$ref: /schemas/types.yaml#/definitions/flag

2
Documentation/devicetree/bindings/input/microchip,cap11xx.yaml
View File

@ -112,7 +112,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
cap1188@28 {
touch@28 {
compatible = "microchip,cap1188";
interrupt-parent = <&gpio1>;
interrupts = <0 0>;

8
Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
View File

@ -85,6 +85,14 @@ properties:
minimum: 0
maximum: 80
report-rate-hz:
description: |
Allows setting the scan rate in Hertz.
M06 supports range from 30 to 140 Hz.
M12 supports range from 1 to 255 Hz.
minimum: 1
maximum: 255
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-fuzz-x: true

2
Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common properties for the multicolor LED class.
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
Bindings for multi color LEDs show how to describe current outputs of

2
Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: LED driver for LP50XX RGB LED from Texas Instruments.
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into

1
Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
View File

@ -57,6 +57,7 @@ properties:
maxItems: 1
interrupts:
minItems: 2
items:
- description: low-priority non-secure
- description: high-priority non-secure

52
Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml Normal file
View File

@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan K210 SRAM memory controller
description:
The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
of SRAM. The controller is initialised by the bootloader, which configures
its clocks, before OS bringup.
maintainers:
- Conor Dooley <conor@kernel.org>
properties:
compatible:
enum:
- canaan,k210-sram
clocks:
minItems: 1
items:
- description: sram0 clock
- description: sram1 clock
- description: aisram clock
clock-names:
minItems: 1
items:
- const: sram0
- const: sram1
- const: aisram
required:
- compatible
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/k210-clk.h>
memory-controller {
compatible = "canaan,k210-sram";
clocks = <&sysclk K210_CLK_SRAM0>,
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_AI>;
clock-names = "sram0", "sram1", "aisram";
};

1
Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
View File

@ -19,7 +19,6 @@ description: |
maintainers:
- Tim Harvey <tharvey@gateworks.com>
- Robert Jones <rjones@gateworks.com>
properties:
$nodename:

94
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
View File

@ -1,94 +0,0 @@
Qualcomm SPMI PMICs multi-function device bindings
The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
PMICs. These PMICs use a QPNP scheme through SPMI interface.
QPNP is effectively a partitioning scheme for dividing the SPMI extended
register space up into logical pieces, and set of fixed register
locations/definitions within these regions, with some of these regions
specifically used for interrupt handling.
The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
interfaced to the chip via the SPMI (System Power Management Interface) bus.
Support for multiple independent functions are implemented by splitting the
16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
each. A function can consume one or more of these fixed-size register regions.
Required properties:
- compatible: Should contain one of:
"qcom,pm660",
"qcom,pm660l",
"qcom,pm7325",
"qcom,pm8004",
"qcom,pm8005",
"qcom,pm8019",
"qcom,pm8028",
"qcom,pm8110",
"qcom,pm8150",
"qcom,pm8150b",
"qcom,pm8150c",
"qcom,pm8150l",
"qcom,pm8226",
"qcom,pm8350c",
"qcom,pm8841",
"qcom,pm8901",
"qcom,pm8909",
"qcom,pm8916",
"qcom,pm8941",
"qcom,pm8950",
"qcom,pm8953",
"qcom,pm8994",
"qcom,pm8998",
"qcom,pma8084",
"qcom,pmd9635",
"qcom,pmi8950",
"qcom,pmi8962",
"qcom,pmi8994",
"qcom,pmi8998",
"qcom,pmk8002",
"qcom,pmk8350",
"qcom,pmr735a",
"qcom,smb2351",
or generalized "qcom,spmi-pmic".
- reg: Specifies the SPMI USID slave address for this device.
For more information see:
Documentation/devicetree/bindings/spmi/spmi.yaml
Required properties for peripheral child nodes:
- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
Optional properties for peripheral child nodes:
- interrupts: Interrupts are specified as a 4-tuple. For more information
see:
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
- interrupt-names: Corresponding interrupt name to the interrupts property
Each child node of SPMI slave id represents a function of the PMIC. In the
example below the rtc device node represents a peripheral of pm8941
SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
Example:
spmi {
compatible = "qcom,spmi-pmic-arb";
pm8941@0 {
compatible = "qcom,pm8941", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
rtc {
compatible = "qcom,rtc";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm";
};
};
pm8941@1 {
compatible = "qcom,pm8941", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
regulator {
compatible = "qcom,regulator";
regulator-name = "8941_boost";
};
};
};

190
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml Normal file
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@ -0,0 +1,190 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SPMI PMICs multi-function device
description: |
Some Qualcomm PMICs used with the Snapdragon series SoCs are interfaced
to the chip via the SPMI (System Power Management Interface) bus.
Support for multiple independent functions are implemented by splitting the
16-bit SPMI peripheral address space into 256 smaller fixed-size regions, 256 bytes
each. A function can consume one or more of these fixed-size register regions.
The Qualcomm SPMI series includes the PM8941, PM8841, PMA8084, PM8998 and other
PMICs. These PMICs use a "QPNP" scheme through SPMI interface.
QPNP is effectively a partitioning scheme for dividing the SPMI extended
register space up into logical pieces, and set of fixed register
locations/definitions within these regions, with some of these regions
specifically used for interrupt handling.
maintainers:
- Stephen Boyd <sboyd@kernel.org>
properties:
$nodename:
oneOf:
- pattern: '^pmic@.*$'
- pattern: '^pm(a|s)?[0-9]*@.*$'
deprecated: true
compatible:
items:
- enum:
- qcom,pm660
- qcom,pm660l
- qcom,pm6150
- qcom,pm6150l
- qcom,pm6350
- qcom,pm7325
- qcom,pm8004
- qcom,pm8005
- qcom,pm8009
- qcom,pm8019
- qcom,pm8110
- qcom,pm8150
- qcom,pm8150b
- qcom,pm8150l
- qcom,pm8226
- qcom,pm8350
- qcom,pm8350b
- qcom,pm8350c
- qcom,pm8841
- qcom,pm8909
- qcom,pm8916
- qcom,pm8941
- qcom,pm8950
- qcom,pm8994
- qcom,pm8998
- qcom,pma8084
- qcom,pmd9635
- qcom,pmi8950
- qcom,pmi8962
- qcom,pmi8994
- qcom,pmi8998
- qcom,pmk8350
- qcom,pmm8155au
- qcom,pmr735a
- qcom,pmr735b
- qcom,pms405
- qcom,pmx55
- qcom,pmx65
- qcom,smb2351
- const: qcom,spmi-pmic
reg:
minItems: 1
maxItems: 2
'#address-cells':
const: 1
'#size-cells':
const: 0
labibb:
type: object
$ref: /schemas/regulator/qcom-labibb-regulator.yaml#
regulators:
type: object
$ref: /schemas/regulator/regulator.yaml#
patternProperties:
"^adc@[0-9a-f]+$":
type: object
$ref: /schemas/iio/adc/qcom,spmi-vadc.yaml#
"^adc-tm@[0-9a-f]+$":
type: object
$ref: /schemas/thermal/qcom-spmi-adc-tm5.yaml#
"^audio-codec@[0-9a-f]+$":
type: object
additionalProperties: true # FIXME qcom,pm8916-wcd-analog-codec binding not converted yet
"extcon@[0-9a-f]+$":
type: object
$ref: /schemas/extcon/qcom,pm8941-misc.yaml#
"gpio(s)?@[0-9a-f]+$":
type: object
$ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
"pon@[0-9a-f]+$":
type: object
$ref: /schemas/power/reset/qcom,pon.yaml#
"pwm@[0-9a-f]+$":
type: object
$ref: /schemas/leds/leds-qcom-lpg.yaml#
"^rtc@[0-9a-f]+$":
type: object
$ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml#
"^temp-alarm@[0-9a-f]+$":
type: object
$ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml#
"^vibrator@[0-9a-f]+$":
type: object
additionalProperties: true # FIXME qcom,pm8916-vib binding not converted yet
"^mpps@[0-9a-f]+$":
type: object
$ref: /schemas/pinctrl/qcom,pmic-mpp.yaml#
"(.*)?(wled|leds)@[0-9a-f]+$":
type: object
$ref: /schemas/leds/backlight/qcom-wled.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0c440000 0x1100>,
<0x0c600000 0x2000000>,
<0x0e600000 0x100000>,
<0x0e700000 0xa0000>,
<0x0c40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pmi8998_lsid0: pmic@2 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8998_gpio: gpios@c000 {
compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pmi8998_gpio 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

2
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
View File

@ -137,6 +137,8 @@ properties:
max-frequency: true
operating-points-v2: true
patternProperties:
'^opp-table(-[a-z0-9]+)?$':
if:

2
Documentation/devicetree/bindings/net/ti,dp83822.yaml
View File

@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: TI DP83822 ethernet PHY
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It

2
Documentation/devicetree/bindings/net/ti,dp83867.yaml
View File

@ -11,7 +11,7 @@ allOf:
- $ref: "ethernet-controller.yaml#"
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The DP83867 device is a robust, low power, fully featured Physical Layer

2
Documentation/devicetree/bindings/net/ti,dp83869.yaml
View File

@ -11,7 +11,7 @@ allOf:
- $ref: "ethernet-phy.yaml#"
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver

10
Documentation/devicetree/bindings/opp/opp-v2-base.yaml
View File

@ -50,6 +50,16 @@ patternProperties:
property to uniquely identify the OPP nodes exists. Devices like power
domains must have another (implementation dependent) property.
Entries for multiple clocks shall be provided in the same field, as
array of frequencies. The OPP binding doesn't provide any provisions
to relate the values to their clocks or the order in which the clocks
need to be configured and that is left for the implementation
specific binding.
minItems: 1
maxItems: 16
items:
maxItems: 1
opp-microvolt:
description: |
Voltage for the OPP

15
Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
View File

@ -98,6 +98,8 @@ examples:
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
@ -115,6 +117,8 @@ examples:
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
@ -128,6 +132,8 @@ examples:
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
@ -145,6 +151,8 @@ examples:
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
@ -182,18 +190,21 @@ examples:
opp-microvolt = <905000 905000 1140000>;
opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
required-opps = <&cpr_opp1>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x5>;
clock-latency-ns = <200000>;
required-opps = <&cpr_opp2>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
required-opps = <&cpr_opp3>;
};
};
@ -207,24 +218,28 @@ examples:
opp-microvolt = <905000 905000 1140000>;
opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
required-opps = <&cpr_opp1>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x6>;
clock-latency-ns = <200000>;
required-opps = <&cpr_opp4>;
};
opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>;
opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x4>;
clock-latency-ns = <200000>;
required-opps = <&cpr_opp5>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
required-opps = <&cpr_opp6>;
};
};

16
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
View File

@ -46,6 +46,7 @@ properties:
- allwinner,sun8i-v3s-pinctrl
- allwinner,sun9i-a80-pinctrl
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun20i-d1-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-a100-pinctrl
@ -80,9 +81,6 @@ properties:
- const: hosc
- const: losc
resets:
maxItems: 1
gpio-controller: true
interrupt-controller: true
gpio-line-names: true
@ -181,6 +179,18 @@ allOf:
minItems: 7
maxItems: 7
- if:
properties:
compatible:
enum:
- allwinner,sun20i-d1-pinctrl
then:
properties:
interrupts:
minItems: 6
maxItems: 6
- if:
properties:
compatible:

2
Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml
View File

@ -152,7 +152,7 @@ examples:
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
uid {
button-uid {
label = "UID";
linux,code = <102>;
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;

31
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
View File

@ -28,6 +28,8 @@ properties:
gpio-ranges:
maxItems: 1
gpio-line-names: true
reg:
description: |
Physical address base for gpio base registers. There are 8 different GPIO
@ -105,31 +107,8 @@ patternProperties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
@ -291,7 +270,7 @@ examples:
pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
<PINMUX_GPIO128__FUNC_SDA0>;
bias-pull-up = <MTK_PULL_SET_RSEL_001>;
mediatek,drive-strength-adv = <7>;
drive-strength-microamp = <1000>;
};
};
};

60
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
View File

@ -80,46 +80,30 @@ patternProperties:
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
mediatek,pull-up-adv:
description: |
Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
bias-pull-down:
oneOf:
- type: boolean
description: normal pull down.
- enum: [100, 101, 102, 103]
description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_
defines in dt-bindings/pinctrl/mt65xx.h.
- enum: [200, 201, 202, 203]
description: RSEL pull down type. See MTK_PULL_SET_RSEL_
defines in dt-bindings/pinctrl/mt65xx.h.
bias-pull-down: true
bias-pull-up: true
bias-pull-up:
oneOf:
- type: boolean
description: normal pull up.
- enum: [100, 101, 102, 103]
description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_
defines in dt-bindings/pinctrl/mt65xx.h.
- enum: [200, 201, 202, 203]
description: RSEL pull up type. See MTK_PULL_SET_RSEL_
defines in dt-bindings/pinctrl/mt65xx.h.
bias-disable: true

41
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
View File

@ -29,6 +29,8 @@ properties:
description: gpio valid number range.
maxItems: 1
gpio-line-names: true
reg:
description: |
Physical address base for gpio base registers. There are 8 GPIO
@ -49,7 +51,7 @@ properties:
description: The interrupt outputs to sysirq.
maxItems: 1
mediatek,rsel_resistance_in_si_unit:
mediatek,rsel-resistance-in-si-unit:
type: boolean
description: |
Identifying i2c pins pull up/down type which is RSEL. It can support
@ -98,31 +100,8 @@ patternProperties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
@ -142,7 +121,7 @@ patternProperties:
"MTK_PUPD_SET_R1R0_11" define in mt8195.
For pull down type is RSEL, it can add RSEL define & resistance
value(ohm) to set different resistance by identifying property
"mediatek,rsel_resistance_in_si_unit".
"mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
& "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
@ -161,7 +140,7 @@ patternProperties:
};
An example of using si unit resistance value(ohm):
&pio {
mediatek,rsel_resistance_in_si_unit;
mediatek,rsel-resistance-in-si-unit;
}
pincontroller {
i2c0_pin {
@ -190,7 +169,7 @@ patternProperties:
"MTK_PUPD_SET_R1R0_11" define in mt8195.
For pull up type is RSEL, it can add RSEL define & resistance
value(ohm) to set different resistance by identifying property
"mediatek,rsel_resistance_in_si_unit".
"mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
& "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
@ -209,7 +188,7 @@ patternProperties:
};
An example of using si unit resistance value(ohm):
&pio {
mediatek,rsel_resistance_in_si_unit;
mediatek,rsel-resistance-in-si-unit;
}
pincontroller {
i2c0-pins {
@ -302,7 +281,7 @@ examples:
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
<PINMUX_GPIO9__FUNC_SCL0>;
bias-disable;
mediatek,drive-strength-adv = <7>;
drive-strength-microamp = <1000>;
};
};
};

2
Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
View File

@ -144,7 +144,7 @@ examples:
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 80>;
gpio-ranges = <&tlmm 0 0 80>;
serial3-pinmux {
pins = "gpio44", "gpio45";

152
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml Normal file
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@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MSM8909 TLMM block
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
This binding describes the Top Level Mode Multiplexer (TLMM) block found
in the MSM8909 platform.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,msm8909-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-msm8909-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-msm8909-tlmm-state"
$defs:
qcom-msm8909-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
qdsd_data2, qdsd_data3 ]
minItems: 1
maxItems: 16
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3, atest_combodac,
atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1,
bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1,
blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1,
blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1,
blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk,
cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0,
dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd,
ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio,
gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync,
nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2,
pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a,
pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b,
prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s,
smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt,
wcss_bt, wcss_fm, wcss_wlan ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@1000000 {
compatible = "qcom,msm8909-tlmm";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio4";
function = "blsp_uart1";
bias-pull-up;
};
tx {
pins = "gpio5";
function = "blsp_uart1";
bias-disable;
};
};
};
...

4
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -52,6 +52,7 @@ properties:
- qcom,pmi8998-gpio
- qcom,pmk8350-gpio
- qcom,pmm8155au-gpio
- qcom,pmp8074-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
- qcom,pms405-gpio
@ -158,6 +159,7 @@ allOf:
compatible:
contains:
enum:
- qcom,pm8226-gpio
- qcom,pm8350b-gpio
- qcom,pm8950-gpio
then:
@ -233,6 +235,7 @@ allOf:
- qcom,pm8150b-gpio
- qcom,pm8150l-gpio
- qcom,pmc8180c-gpio
- qcom,pmp8074-gpio
- qcom,pms405-gpio
then:
properties:
@ -415,6 +418,7 @@ $defs:
- gpio1-gpio10 for pmi8994
- gpio1-gpio4 for pmk8350
- gpio1-gpio10 for pmm8155au
- gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12)
- gpio1-gpio4 for pmr735a
- gpio1-gpio4 for pmr735b
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9

5
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
View File

@ -19,6 +19,11 @@ properties:
compatible:
const: qcom,sc7280-lpass-lpi-pinctrl
qcom,adsp-bypass-mode:
description:
Tells ADSP is in bypass mode.
type: boolean
reg:
minItems: 2
maxItems: 2

158
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml Normal file
View File

@ -0,0 +1,158 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM6375 TLMM block
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
This binding describes the Top Level Mode Multiplexer (TLMM) block found
in the SM6375 platform.
allOf:
- $ref: "pinctrl.yaml#"
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,sm6375-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-sm6375-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-sm6375-tlmm-state"
$defs:
qcom-sm6375-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
- enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
atest_char2, atest_char3, atest_tsens, atest_tsens2,
atest_usb1, atest_usb10, atest_usb11, atest_usb12,
atest_usb13, atest_usb2, atest_usb20, atest_usb21,
atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist,
ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd,
gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext,
m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio,
nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10,
phase_flag11, phase_flag12, phase_flag13, phase_flag14,
phase_flag15, phase_flag16, phase_flag17, phase_flag18,
phase_flag19, phase_flag2, phase_flag20, phase_flag21,
phase_flag22, phase_flag23, phase_flag24, phase_flag25,
phase_flag26, phase_flag27, phase_flag28, phase_flag29,
phase_flag3, phase_flag30, phase_flag31, phase_flag4,
phase_flag5, phase_flag6, phase_flag7, phase_flag8,
phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2,
qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb,
sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset,
uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac,
usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
wlan2_adc0, wlan2_adc1 ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@500000 {
compatible = "qcom,sm6375-tlmm";
reg = <0x00500000 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio18";
function = "qup13_f2";
bias-pull-up;
};
tx {
pins = "gpio19";
function = "qup13_f2";
bias-disable;
};
};
};
...

1
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
View File

@ -45,6 +45,7 @@ properties:
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-r8a779f0 # R-Car S4-8
- renesas,pfc-r8a779g0 # R-Car V4H
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:

170
Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml Normal file
View File

@ -0,0 +1,170 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2M combined Pin and GPIO controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Phil Edworthy <phil.edworthy@renesas.com>
description:
The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 16 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
const: renesas,r9a09g011-pinctrl # RZ/V2M
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
second cell represents consumer flag as mentioned in ../gpio/gpio.txt
E.g. "RZV2M_GPIO(8, 1)" for P8_1.
gpio-ranges:
maxItems: 1
interrupts:
description: INEXINT[0..38] corresponding to individual pin inputs.
maxItems: 39
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZV2M_PORT_PINMUX()
helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.
pins: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength-microamp:
# Superset of supported values
enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,
9000, 9600, 11000, 12000, 13000, 18000 ]
slew-rate:
description: 0 is slow slew rate, 1 is fast slew rate
enum: [ 0, 1 ]
gpio-hog: true
gpios: true
output-high: true
output-low: true
line-name: true
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- interrupts
- clocks
- power-domains
- resets
examples:
- |
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
#include <dt-bindings/clock/r9a09g011-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl@b6250000 {
compatible = "renesas,r9a09g011-pinctrl";
reg = <0xb6250000 0x800>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 352>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
resets = <&cpg R9A09G011_PFC_PRESETN>;
power-domains = <&cpg>;
i2c2_pins: i2c2 {
pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
<RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
};
};

4
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View File

@ -59,6 +59,7 @@ properties:
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
additionalProperties: false
properties:
gpio-controller: true
'#gpio-cells':
@ -68,8 +69,7 @@ patternProperties:
maxItems: 1
clocks:
maxItems: 1
reset:
minItems: 1
resets:
maxItems: 1
gpio-ranges:
minItems: 1

5
Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml
View File

@ -288,11 +288,14 @@ required:
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
examples:
- |
#include <dt-bindings/pinctrl/sppctl-sp7021.h>
pinctl@9c000100 {
pinctrl@9c000100 {
compatible = "sunplus,sp7021-pctl";
reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
<0x9c0032e4 0x1c>, <0x9c000080 0x20>;

4
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
View File

@ -274,6 +274,10 @@ patternProperties:
slew-rate:
enum: [0, 1]
output-enable:
description:
This will internally disable the tri-state for MIO pins.
drive-strength:
description:
Selects the drive strength for MIO pins, in mA.

17
Documentation/devicetree/bindings/power/reset/msm-poweroff.txt
View File

@ -1,17 +0,0 @@
MSM Restart Driver
A power supply hold (ps-hold) bit is set to power the msm chipsets.
Clearing that bit allows us to restart/poweroff. The difference
between poweroff and restart is determined by unique power manager IC
settings.
Required Properties:
-compatible: "qcom,pshold"
-reg: Specifies the physical address of the ps-hold register
Example:
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};

35
Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml Normal file
View File

@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/reset/qcom,pshold.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SoC restart and power off
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
A power supply hold (ps-hold) bit is set to power the Qualcomm chipsets.
Clearing that bit allows us to restart/power off. The difference between
power off and restart is determined by unique power manager IC settings.
properties:
compatible:
const: qcom,pshold
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
reset-controller@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};

2
Documentation/devicetree/bindings/power/supply/bq24190.yaml
View File

@ -28,7 +28,7 @@ properties:
maxItems: 1
usb-otg-vbus:
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
Regulator that is used to control the VBUS voltage direction for
either USB host mode or for charging on the OTG port

3
Documentation/devicetree/bindings/power/supply/bq2515x.yaml
View File

@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI bq2515x 500-mA Linear charger family
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Ricardo Rivera-Matos <r-rivera-matos@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The BQ2515x family is a highly integrated battery charge management IC that

2
Documentation/devicetree/bindings/power/supply/bq256xx.yaml
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@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI bq256xx Switch Mode Buck Charger
maintainers:
- Ricardo Rivera-Matos <r-rivera-matos@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The bq256xx devices are a family of highly-integrated battery charge

3
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@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI BQ25980 Flash Charger
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Ricardo Rivera-Matos <r-rivera-matos@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The BQ25980, BQ25975, and BQ25960 are a series of flash chargers intended

9
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@ -117,11 +117,18 @@ properties:
be done externally to fully comply with the JEITA safety guidelines if this flag
is set.
usb-charge-current-limit:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 100000
maximum: 2500000
description: |
Default USB charge current limit in uA.
usb-otg-in-supply:
description: Reference to the regulator supplying power to the USB_OTG_IN pin.
otg-vbus:
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
This node defines a regulator used to control the direction of VBUS voltage.
Specifically whether to supply voltage to VBUS for host mode operation of the OTG port,

2
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@ -82,7 +82,7 @@ properties:
- 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH
usb-vbus:
$ref: "../../regulator/regulator.yaml#"
$ref: /schemas/regulator/regulator.yaml#
type: object
properties:

2
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@ -18,6 +18,7 @@ properties:
enum:
- mediatek,mt8183-scp
- mediatek,mt8186-scp
- mediatek,mt8188-scp
- mediatek,mt8192-scp
- mediatek,mt8195-scp
@ -80,6 +81,7 @@ allOf:
enum:
- mediatek,mt8183-scp
- mediatek,mt8186-scp
- mediatek,mt8188-scp
then:
properties:
reg:

74
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@ -67,13 +67,28 @@ properties:
minItems: 1
maxItems: 8
interconnects:
maxItems: 1
interrupts:
minItems: 5
maxItems: 6
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt
interrupt-names:
minItems: 5
maxItems: 6
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack
resets:
minItems: 1
@ -116,7 +131,6 @@ properties:
- description: Stop the modem
qcom,smem-state-names:
$ref: /schemas/types.yaml#/definitions/string-array
description: The names of the state bits used for SMP2P output
items:
- const: stop
@ -134,13 +148,13 @@ properties:
three offsets within syscon for q6, modem and nc halt registers.
smd-edge:
type: object
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
description:
Qualcomm Shared Memory subnode which represents communication edge,
channels and devices related to the ADSP.
glink-edge:
type: object
$ref: /schemas/remoteproc/qcom,glink-edge.yaml#
description:
Qualcomm G-Link subnode which represents communication edge, channels
and devices related to the ADSP.
@ -315,19 +329,9 @@ allOf:
then:
properties:
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
maxItems: 5
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
maxItems: 5
- if:
properties:
@ -345,21 +349,9 @@ allOf:
then:
properties:
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt
minItems: 6
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack
minItems: 6
- if:
properties:
@ -379,6 +371,8 @@ allOf:
- qcom,msm8226-adsp-pil
- qcom,msm8996-adsp-pil
- qcom,msm8998-adsp-pas
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
then:
properties:
power-domains:
@ -442,19 +436,6 @@ allOf:
- const: cx
- const: mx
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- if:
properties:
compatible:
@ -594,11 +575,12 @@ allOf:
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
adsp {
compatible = "qcom,msm8974-adsp-pil";
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@ -620,7 +602,7 @@ examples:
qcom,smem-state-names = "stop";
smd-edge {
interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;

72
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@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,glink-edge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm G-Link Edge communication channel nodes
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
Qualcomm G-Link subnode represents communication edge, channels and devices
related to the remote processor.
properties:
$nodename:
const: "glink-edge"
apr:
$ref: /schemas/soc/qcom/qcom,apr.yaml#
description:
Qualcomm APR/GPR (Asynchronous/Generic Packet Router)
fastrpc:
type: object
description:
See Documentation/devicetree/bindings/misc/qcom,fastrpc.txt
interrupts:
maxItems: 1
label:
description: The names of the state bits used for SMP2P output
mboxes:
maxItems: 1
qcom,remote-pid:
$ref: /schemas/types.yaml#/definitions/uint32
description:
ID of the shared memory used by GLINK for communication with remote
processor.
required:
- interrupts
- label
- mboxes
- qcom,remote-pid
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
remoteproc@8a00000 {
reg = <0x08a00000 0x10000>;
// ...
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "wpss";
qcom,remote-pid = <13>;
};
};

88
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@ -14,8 +14,6 @@ on the Qualcomm Hexagon core.
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
"qcom,msm8998-mss-pil"
"qcom,sc7180-mss-pil"
"qcom,sc7280-mss-pil"
"qcom,sdm845-mss-pil"
- reg:
@ -47,8 +45,6 @@ on the Qualcomm Hexagon core.
must be "wdog", "fatal", "ready", "handover", "stop-ack"
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
qcom,sc7180-mss-pil:
qcom,sc7280-mss-pil:
qcom,sdm845-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack",
"shutdown-ack"
@ -86,11 +82,6 @@ on the Qualcomm Hexagon core.
qcom,msm8998-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "qdss"
qcom,sc7180-mss-pil:
must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
"nav"
qcom,sc7280-mss-pil:
must be "iface", "xo", "snoc_axi", "offline", "pka"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
@ -102,7 +93,7 @@ on the Qualcomm Hexagon core.
reference to the list of 3 reset-controllers for the
wcss sub-system
reference to the list of 2 reset-controllers for the modem
sub-system on SC7180, SC7280, SDM845 SoCs
sub-system on SDM845 SoCs
- reset-names:
Usage: required
@ -111,7 +102,7 @@ on the Qualcomm Hexagon core.
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
must be "mss_restart", "pdc_reset" for the modem
sub-system on SC7180, SC7280, SDM845 SoCs
sub-system on SDM845 SoCs
For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
should be referenced as follows:
@ -176,10 +167,6 @@ For the compatible string below the following supplies are required:
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
must be "cx", "mx"
qcom,sc7180-mss-pil:
must be "cx", "mx", "mss"
qcom,sc7280-mss-pil:
must be "cx", "mss"
qcom,sdm845-mss-pil:
must be "cx", "mx", "mss"
@ -205,36 +192,6 @@ For the compatible string below the following supplies are required:
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for q6, modem and nc
halt registers.
a phandle reference to a syscon representing TCSR followed
by the four offsets within syscon for q6, modem, nc and vq6
halt registers on SC7280 SoCs.
For the compatible strings below the following phandle references are required:
"qcom,sc7180-mss-pil"
- qcom,spare-regs:
Usage: required
Value type: <prop-encoded-array>
Definition: a phandle reference to a syscon representing TCSR followed
by the offset within syscon for conn_box_spare0 register
used by the modem sub-system running on SC7180 SoC.
For the compatible strings below the following phandle references are required:
"qcom,sc7280-mss-pil"
- qcom,ext-regs:
Usage: required
Value type: <prop-encoded-array>
Definition: two phandle references to syscons representing TCSR_REG and
TCSR register space followed by the two offsets within the syscon
to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off
registers respectively.
- qcom,qaccept-regs:
Usage: required
Value type: <prop-encoded-array>
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for mdm, cx and axi
qaccept registers used by the modem sub-system running on
SC7280 SoC.
The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
on platforms which do not have TrustZone.
@ -257,29 +214,23 @@ related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and
The following example describes the resources needed to boot control the
Hexagon, as it is found on MSM8974 boards.
modem-rproc@fc880000 {
compatible = "qcom,q6v5-pil";
reg = <0xfc880000 0x100>,
<0xfc820000 0x020>;
remoteproc@fc880000 {
compatible = "qcom,msm8974-mss-pil";
reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc 0 24 1>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
<&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>;
clock-names = "iface", "bus", "mem";
qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&xo_board>;
clock-names = "iface", "bus", "mem", "xo";
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
@ -289,6 +240,8 @@ Hexagon, as it is found on MSM8974 boards.
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@ -299,4 +252,13 @@ Hexagon, as it is found on MSM8974 boards.
mpss {
memory-region = <&mpss_region>;
};
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 12>;
qcom,smd-edge = <0>;
label = "modem";
};
};

1
Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml
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@ -90,7 +90,6 @@ properties:
- description: Stop the modem
qcom,smem-state-names:
$ref: /schemas/types.yaml#/definitions/string
description: The names of the state bits used for SMP2P output
items:
- const: stop

245
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@ -0,0 +1,245 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7180 MSS Peripheral Image Loader
maintainers:
- Sibi Sankar <quic_sibis@quicinc.com>
description:
This document describes the hardware for a component that loads and boots firmware
on the Qualcomm Technology Inc. SC7180 Modem Hexagon Core.
properties:
compatible:
enum:
- qcom,sc7180-mss-pil
reg:
items:
- description: MSS QDSP6 registers
- description: RMB registers
reg-names:
items:
- const: qdsp6
- const: rmb
iommus:
items:
- description: MSA Stream 1
- description: MSA Stream 2
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack
clocks:
items:
- description: GCC MSS IFACE clock
- description: GCC MSS BUS clock
- description: GCC MSS NAV clock
- description: GCC MSS SNOC_AXI clock
- description: GCC MSS MFAB_AXIS clock
- description: RPMH XO clock
clock-names:
items:
- const: iface
- const: bus
- const: nav
- const: snoc_axi
- const: mnoc_axi
- const: xo
power-domains:
items:
- description: CX power domain
- description: MX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mx
- const: mss
resets:
items:
- description: AOSS restart
- description: PDC reset
reset-names:
items:
- const: mss_restart
- const: pdc_reset
memory-region:
items:
- description: MBA reserved region
- description: modem reserved region
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
items:
- description: Name of MBA firmware
- description: Name of modem firmware
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Halt registers are used to halt transactions of various sub-components
within MSS.
items:
- items:
- description: phandle to TCSR_MUTEX registers
- description: offset to the Q6 halt register
- description: offset to the modem halt register
- description: offset to the nc halt register
qcom,spare-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Spare registers are multipurpose registers used for errata
handling.
items:
- items:
- description: phandle to TCSR_MUTEX registers
- description: offset to the conn_box_spare0 register
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
items:
- description: Stop the modem
qcom,smem-state-names:
description: The names of the state bits used for SMP2P output
const: stop
glink-edge:
$ref: qcom,glink-edge.yaml#
description:
Qualcomm G-Link subnode which represents communication edge, channels
and devices related to the DSP.
properties:
interrupts:
items:
- description: IRQ from MSS to GLINK
mboxes:
items:
- description: Mailbox for communication between APPS and MSS
label:
const: modem
apr: false
fastrpc: false
required:
- compatible
- reg
- reg-names
- iommus
- interrupts
- interrupt-names
- clocks
- clock-names
- power-domains
- power-domain-names
- resets
- reset-names
- qcom,halt-regs
- qcom,spare-regs
- memory-region
- qcom,qmp
- qcom,smem-states
- qcom,smem-state-names
- glink-edge
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7180-mss-pil";
reg = <0x04080000 0x10000>, <0x04180000 0x48>;
reg-names = "qdsp6", "rmb";
iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
<&gcc GCC_MSS_NAV_AXI_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MFAB_AXIS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
power-domain-names = "cx", "mx", "mss";
memory-region = <&mba_mem>, <&mpss_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
qcom,spare-regs = <&tcsr_regs 0xb3e4>;
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 12>;
qcom,remote-pid = <1>;
label = "modem";
};
};

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@ -0,0 +1,266 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7280 MSS Peripheral Image Loader
maintainers:
- Sibi Sankar <quic_sibis@quicinc.com>
description:
This document describes the hardware for a component that loads and boots firmware
on the Qualcomm Technology Inc. SC7280 Modem Hexagon Core.
properties:
compatible:
enum:
- qcom,sc7280-mss-pil
reg:
items:
- description: MSS QDSP6 registers
- description: RMB registers
reg-names:
items:
- const: qdsp6
- const: rmb
iommus:
items:
- description: MSA Stream 1
- description: MSA Stream 2
interconnects:
items:
- description: Path leading to system memory
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack
clocks:
items:
- description: GCC MSS IFACE clock
- description: GCC MSS OFFLINE clock
- description: GCC MSS SNOC_AXI clock
- description: RPMH PKA clock
- description: RPMH XO clock
clock-names:
items:
- const: iface
- const: offline
- const: snoc_axi
- const: pka
- const: xo
power-domains:
items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mss
resets:
items:
- description: AOSS restart
- description: PDC reset
reset-names:
items:
- const: mss_restart
- const: pdc_reset
memory-region:
items:
- description: MBA reserved region
- description: modem reserved region
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
items:
- description: Name of MBA firmware
- description: Name of modem firmware
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Halt registers are used to halt transactions of various sub-components
within MSS.
items:
- items:
- description: phandle to TCSR_MUTEX registers
- description: offset to the Q6 halt register
- description: offset to the modem halt register
- description: offset to the nc halt register
- description: offset to the vq6 halt register
qcom,ext-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: EXT registers are used for various power related functionality
items:
- items:
- description: phandle to TCSR_REG registers
- description: offset to the force_clk_en register
- description: offset to the rscc_disable register
- items:
- description: phandle to TCSR_MUTEX registers
- description: offset to the axim1_clk_off register
- description: offset to the crypto_clk_off register
qcom,qaccept-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: QACCEPT registers are used to bring up/down Q-channels
items:
- items:
- description: phandle to TCSR_MUTEX registers
- description: offset to the mdm qaccept register
- description: offset to the cx qaccept register
- description: offset to the axi qaccept register
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
items:
- description: Stop the modem
qcom,smem-state-names:
description: The names of the state bits used for SMP2P output
const: stop
glink-edge:
$ref: qcom,glink-edge.yaml#
description:
Qualcomm G-Link subnode which represents communication edge, channels
and devices related to the DSP.
properties:
interrupts:
items:
- description: IRQ from MSS to GLINK
mboxes:
items:
- description: Mailbox for communication between APPS and MSS
label:
const: modem
apr: false
fastrpc: false
required:
- compatible
- reg
- reg-names
- iommus
- interconnects
- interrupts
- interrupt-names
- clocks
- clock-names
- power-domains
- power-domain-names
- resets
- reset-names
- qcom,halt-regs
- qcom,ext-regs
- qcom,qaccept-regs
- memory-region
- qcom,qmp
- qcom,smem-states
- qcom,smem-state-names
- glink-edge
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mss-pil";
reg = <0x04080000 0x10000>, <0x04180000 0x48>;
reg-names = "qdsp6", "rmb";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_OFFLINE_AXI_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&rpmhcc RPMH_PKA_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MSS>;
power-domain-names = "cx", "mss";
memory-region = <&mba_mem>, <&mpss_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
qcom,ext-regs = <&tcsr 0x10000 0x10004>, <&tcsr_mutex 0x26004 0x26008>;
qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "modem";
qcom,remote-pid = <1>;
};
};

21
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml
View File

@ -76,7 +76,7 @@ properties:
- const: pdc_sync
memory-region:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
@ -102,13 +102,12 @@ properties:
- description: Stop the modem
qcom,smem-state-names:
$ref: /schemas/types.yaml#/definitions/string
description: The names of the state bits used for SMP2P output
const: stop
glink-edge:
type: object
description: |
$ref: qcom,glink-edge.yaml#
description:
Qualcomm G-Link subnode which represents communication edge, channels
and devices related to the ADSP.
@ -122,21 +121,11 @@ properties:
- description: Mailbox for communication between APPS and WPSS
label:
description: The names of the state bits used for SMP2P output
items:
- const: wpss
qcom,remote-pid:
$ref: /schemas/types.yaml#/definitions/uint32
description: ID of the shared memory used by GLINK for communication with WPSS
required:
- interrupts
- mboxes
- label
- qcom,remote-pid
additionalProperties: false
apr: false
fastrpc: false
required:
- compatible

1
Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml
View File

@ -90,7 +90,6 @@ properties:
- description: Stop the modem
qcom,smem-state-names:
$ref: /schemas/types.yaml#/definitions/string
description: The names of the state bits used for SMP2P output
items:
- const: stop

85
Documentation/devicetree/bindings/remoteproc/qcom,smd-edge.yaml Normal file
View File

@ -0,0 +1,85 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,smd-edge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SMD Edge communication channel nodes
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
Qualcomm SMD subnode represents a remote subsystem or a remote processor of
some sort - or in SMD language an "edge". The name of the edges are not
important.
See also Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml
properties:
$nodename:
const: "smd-edge"
interrupts:
maxItems: 1
label:
description:
Name of the edge, used for debugging and identification purposes. The
node name will be used if this is not present.
mboxes:
maxItems: 1
description:
Reference to the mailbox representing the outgoing doorbell in APCS for
this client.
qcom,ipc:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to a syscon node representing the APCS registers
- description: u32 representing offset to the register within the syscon
- description: u32 representing the ipc bit within the register
description:
Three entries specifying the outgoing ipc bit used for signaling the
remote processor.
qcom,smd-edge:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The identifier of the remote processor in the smd channel allocation
table.
qcom,remote-pid:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The identifier for the remote processor as known by the rest of the
system.
required:
- interrupts
- qcom,smd-edge
oneOf:
- required:
- mboxes
- required:
- qcom,ipc
additionalProperties: true
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
remoteproc {
// ...
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;
};
};

5
Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml
View File

@ -36,17 +36,18 @@ properties:
enum:
- ti,am3356-pru # for AM335x SoC family (AM3356+ SoCs only)
- ti,am4376-pru # for AM437x SoC family (AM4376+ SoCs only)
- ti,am5728-pru # for AM57xx SoC family
- ti,am625-pru # for PRUs in K3 AM62x SoC family
- ti,am642-pru # for PRUs in K3 AM64x SoC family
- ti,am642-rtu # for RTUs in K3 AM64x SoC family
- ti,am642-tx-pru # for Tx_PRUs in K3 AM64x SoC family
- ti,am5728-pru # for AM57xx SoC family
- ti,k2g-pru # for 66AK2G SoC family
- ti,am654-pru # for PRUs in K3 AM65x SoC family
- ti,am654-rtu # for RTUs in K3 AM65x SoC family
- ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
- ti,j721e-pru # for PRUs in K3 J721E SoC family
- ti,j721e-rtu # for RTUs in K3 J721E SoC family
- ti,j721e-tx-pru # for Tx_PRUs in K3 J721E SoC family
- ti,k2g-pru # for 66AK2G SoC family
reg:
items:

68
Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml Normal file
View File

@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel/Microchip System Reset Controller
maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
description: |
The system reset controller can be used to reset the CPU. In case of
SAMA7G5 it can also reset some devices (e.g. USB PHYs).
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at91sam9260-rstc
- atmel,at91sam9g45-rstc
- atmel,sama5d3-rstc
- microchip,sam9x60-rstc
- microchip,sama7g5-rstc
- items:
- const: atmel,sama5d3-rstc
- const: atmel,at91sam9g45-rstc
reg:
minItems: 1
items:
- description: base registers for system reset control
- description: registers for device specific reset control
clocks:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- clocks
allOf:
- if:
properties:
compatible:
contains:
enum:
- microchip,sama7g5-rstc
then:
required:
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/at91.h>
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};

5
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@ -63,6 +63,11 @@ properties:
- riscv,sv48
- riscv,none
riscv,cbom-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The blocksize in bytes for the Zicbom cache operations.
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture

6
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
View File

@ -46,7 +46,7 @@ properties:
const: 2
cache-sets:
const: 1024
enum: [1024, 2048]
cache-size:
const: 2097152
@ -84,6 +84,8 @@ then:
description: |
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
cache-sets:
const: 1024
else:
properties:
@ -91,6 +93,8 @@ else:
description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
cache-sets:
const: 2048
additionalProperties: false

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