powerpc/powernv/pci: Add MSI domains
This is very similar to the MSI domains of the pSeries platform. The MSI allocator is directly handled under the Linux PHB in the in-the-middle "PNV-MSI" domain. Only the XIVE (P9/P10) parent domain is supported for now. Support for XICS will come later. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210701132750.1475580-13-clg@kaod.org
This commit is contained in:
Cédric Le Goater
Michael Ellerman
parent
2c50d7e99e
commit
0fcfe2247e
@ -36,6 +36,7 @@
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#include <asm/firmware.h>
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#include <asm/pnv-pci.h>
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#include <asm/mmzone.h>
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#include <asm/xive.h>
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#include <misc/cxl-base.h>
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@ -2100,6 +2101,189 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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return 0;
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}
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/*
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* The msi_free() op is called before irq_domain_free_irqs_top() when
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* the handler data is still available. Use that to clear the XIVE
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* controller.
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*/
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static void pnv_msi_ops_msi_free(struct irq_domain *domain,
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struct msi_domain_info *info,
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unsigned int irq)
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{
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if (xive_enabled())
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xive_irq_free_data(irq);
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}
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static struct msi_domain_ops pnv_pci_msi_domain_ops = {
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.msi_free = pnv_msi_ops_msi_free,
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};
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static void pnv_msi_shutdown(struct irq_data *d)
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{
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d = d->parent_data;
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if (d->chip->irq_shutdown)
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d->chip->irq_shutdown(d);
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}
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static void pnv_msi_mask(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void pnv_msi_unmask(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip pnv_pci_msi_irq_chip = {
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.name = "PNV-PCI-MSI",
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.irq_shutdown = pnv_msi_shutdown,
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.irq_mask = pnv_msi_mask,
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.irq_unmask = pnv_msi_unmask,
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.irq_eoi = irq_chip_eoi_parent,
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};
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static struct msi_domain_info pnv_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
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.ops = &pnv_pci_msi_domain_ops,
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.chip = &pnv_pci_msi_irq_chip,
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};
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static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg)
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{
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struct msi_desc *entry = irq_data_get_msi_desc(d);
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struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
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struct pci_controller *hose = irq_data_get_irq_chip_data(d);
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struct pnv_phb *phb = hose->private_data;
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int rc;
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rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq,
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entry->msi_attrib.is_64, msg);
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if (rc)
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dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n",
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entry->msi_attrib.is_64 ? "64" : "32", d->hwirq, rc);
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}
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static struct irq_chip pnv_msi_irq_chip = {
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.name = "PNV-MSI",
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.irq_shutdown = pnv_msi_shutdown,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_compose_msi_msg = pnv_msi_compose_msg,
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};
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static int pnv_irq_parent_domain_alloc(struct irq_domain *domain,
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unsigned int virq, int hwirq)
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{
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struct irq_fwspec parent_fwspec;
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int ret;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 2;
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parent_fwspec.param[0] = hwirq;
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parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
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if (ret)
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return ret;
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return 0;
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}
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static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct pci_controller *hose = domain->host_data;
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struct pnv_phb *phb = hose->private_data;
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msi_alloc_info_t *info = arg;
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struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc);
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int hwirq;
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int i, ret;
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hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs);
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if (hwirq < 0) {
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dev_warn(&pdev->dev, "failed to find a free MSI\n");
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return -ENOSPC;
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}
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dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__,
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hose->dn, virq, hwirq, nr_irqs);
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for (i = 0; i < nr_irqs; i++) {
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ret = pnv_irq_parent_domain_alloc(domain, virq + i,
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phb->msi_base + hwirq + i);
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if (ret)
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goto out;
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&pnv_msi_irq_chip, hose);
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}
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return 0;
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out:
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irq_domain_free_irqs_parent(domain, virq, i - 1);
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs);
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return ret;
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}
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static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct pci_controller *hose = irq_data_get_irq_chip_data(d);
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struct pnv_phb *phb = hose->private_data;
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pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn,
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virq, d->hwirq, nr_irqs);
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msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs);
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/* XIVE domain is cleared through ->msi_free() */
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}
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static const struct irq_domain_ops pnv_irq_domain_ops = {
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.alloc = pnv_irq_domain_alloc,
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.free = pnv_irq_domain_free,
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};
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static int pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count)
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{
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struct pnv_phb *phb = hose->private_data;
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struct irq_domain *parent = irq_get_default_host();
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hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id);
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if (!hose->fwnode)
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return -ENOMEM;
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hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count,
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hose->fwnode,
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&pnv_irq_domain_ops, hose);
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if (!hose->dev_domain) {
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pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n",
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hose->dn, hose->global_number);
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irq_domain_free_fwnode(hose->fwnode);
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return -ENOMEM;
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}
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hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn),
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&pnv_msi_domain_info,
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hose->dev_domain);
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if (!hose->msi_domain) {
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pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n",
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hose->dn, hose->global_number);
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irq_domain_free_fwnode(hose->fwnode);
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irq_domain_remove(hose->dev_domain);
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return -ENOMEM;
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}
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return 0;
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}
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static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
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{
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unsigned int count;
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@ -2124,6 +2308,10 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
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phb->msi32_support = 1;
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pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
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count, phb->msi_base);
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/* Only supported by the XIVE driver */
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if (xive_enabled())
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pnv_msi_allocate_domains(phb->hose, count);
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}
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static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
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