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Merge "soc: qcom: llcc_perfmon: Add support for ADDR_MASK filter"

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This commit is contained in:
qctecmdr 2023-02-19 22:49:02 -08:00 committed by Gerrit - the friendly Code Review server
commit 0d6a6ab412
3 changed files with 139 additions and 35 deletions
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5
drivers/soc/qcom/llcc_events.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _SOC_QCOM_LLCC_EVENTS_H_
@ -286,6 +286,7 @@ enum pmgr_events {
};
enum filter_type {
UNKNOWN_FILTER,
SCID,
MID,
PROFILING_TAG,
@ -295,7 +296,7 @@ enum filter_type {
MEMTAGOPS,
MULTISCID,
DIRTYINFO,
UNKNOWN,
ADDR_MASK
};
#endif /* _SOC_QCOM_LLCC_EVENTS_H_ */

126
drivers/soc/qcom/llcc_perfmon.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@ -49,8 +49,8 @@ struct event_port_ops {
unsigned int type, unsigned int *num, bool enable);
void (*event_enable)(struct llcc_perfmon_private *priv, bool enable);
void (*event_filter_config)(struct llcc_perfmon_private *priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable);
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable);
};
/**
@ -344,7 +344,7 @@ static ssize_t perfmon_remove_store(struct device *dev,
static enum filter_type find_filter_type(char *filter)
{
enum filter_type ret = UNKNOWN;
enum filter_type ret = UNKNOWN_FILTER;
if (!strcmp(filter, "SCID"))
ret = SCID;
@ -364,6 +364,8 @@ static enum filter_type find_filter_type(char *filter)
ret = MULTISCID;
else if (!strcmp(filter, "DIRTYINFO"))
ret = DIRTYINFO;
else if (!strcmp(filter, "ADDR_MASK"))
ret = ADDR_MASK;
return ret;
}
@ -373,10 +375,11 @@ static ssize_t perfmon_filter_config_store(struct device *dev,
size_t count)
{
struct llcc_perfmon_private *llcc_priv = dev_get_drvdata(dev);
unsigned long port, mask, match;
unsigned long long mask, match;
unsigned long port;
struct event_port_ops *port_ops;
char *token, *delim = DELIM_CHAR;
enum filter_type filter = UNKNOWN;
enum filter_type filter = UNKNOWN_FILTER;
if (llcc_priv->configured_cntrs) {
pr_err("remove configured events and try\n");
@ -388,7 +391,7 @@ static ssize_t perfmon_filter_config_store(struct device *dev,
if (token != NULL)
filter = find_filter_type(token);
if (filter == UNKNOWN) {
if (filter == UNKNOWN_FILTER) {
pr_err("filter configuration failed, Unsupported filter\n");
goto filter_config_free;
}
@ -399,7 +402,7 @@ static ssize_t perfmon_filter_config_store(struct device *dev,
goto filter_config_free;
}
if (kstrtoul(token, 0, &match)) {
if (kstrtoull(token, 0, &match)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_config_free;
}
@ -415,7 +418,7 @@ static ssize_t perfmon_filter_config_store(struct device *dev,
goto filter_config_free;
}
if (kstrtoul(token, 0, &mask)) {
if (kstrtoull(token, 0, &mask)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_config_free;
}
@ -453,16 +456,17 @@ static ssize_t perfmon_filter_remove_store(struct device *dev,
{
struct llcc_perfmon_private *llcc_priv = dev_get_drvdata(dev);
struct event_port_ops *port_ops;
unsigned long port, mask, match;
unsigned long long mask, match;
unsigned long port;
char *token, *delim = DELIM_CHAR;
enum filter_type filter = UNKNOWN;
enum filter_type filter = UNKNOWN_FILTER;
mutex_lock(&llcc_priv->mutex);
token = strsep((char **)&buf, delim);
if (token != NULL)
filter = find_filter_type(token);
if (filter == UNKNOWN) {
if (filter == UNKNOWN_FILTER) {
pr_err("filter configuration failed, Unsupported filter\n");
goto filter_remove_free;
}
@ -473,7 +477,7 @@ static ssize_t perfmon_filter_remove_store(struct device *dev,
goto filter_remove_free;
}
if (kstrtoul(token, 0, &match)) {
if (kstrtoull(token, 0, &match)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_remove_free;
}
@ -489,7 +493,7 @@ static ssize_t perfmon_filter_remove_store(struct device *dev,
goto filter_remove_free;
}
if (kstrtoul(token, 0, &mask)) {
if (kstrtoull(token, 0, &mask)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_remove_free;
}
@ -772,10 +776,11 @@ static void feac_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void feac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
uint64_t val = 0;
uint32_t mask_val, offset;
if (filter == SCID) {
if (llcc_priv->version == REV_0) {
@ -852,6 +857,29 @@ static void feac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
offset = FEAC_PROF_FILTER_0_CFG7(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
} else if (filter == ADDR_MASK) {
if (enable)
val = (match & ADDR_LOWER_MASK) << FEAC_ADDR_LOWER_MATCH_SHIFT;
mask_val = FEAC_ADDR_LOWER_MATCH_MASK;
offset = FEAC_PROF_FILTER_0_CFG1(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
if (enable)
val = (mask & ADDR_LOWER_MASK) << FEAC_ADDR_LOWER_MASK_SHIFT;
mask_val = FEAC_ADDR_LOWER_MASK_MASK;
offset = FEAC_PROF_FILTER_0_CFG2(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
if (enable) {
match = (match & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
mask = (mask & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
val = (match << FEAC_ADDR_UPPER_MATCH_SHIFT) |
(mask << FEAC_ADDR_UPPER_MASK_SHIFT);
}
mask_val = FEAC_ADDR_UPPER_MATCH_MASK | FEAC_ADDR_UPPER_MASK_MASK;
offset = FEAC_PROF_FILTER_0_CFG3(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
} else {
pr_err("unknown filter/not supported\n");
}
@ -901,8 +929,8 @@ static void ferc_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void ferc_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
@ -949,8 +977,8 @@ static void fewc_event_config(struct llcc_perfmon_private *llcc_priv,
}
static void fewc_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
@ -1057,10 +1085,11 @@ static void beac_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void beac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val;
uint64_t val = 0;
uint32_t mask_val;
unsigned int mc_cnt, offset;
if (filter == PROFILING_TAG) {
@ -1085,6 +1114,38 @@ static void beac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
} else if (filter == ADDR_MASK) {
if (enable)
val = (match & ADDR_LOWER_MASK) << BEAC_ADDR_LOWER_MATCH_SHIFT;
mask_val = BEAC_ADDR_LOWER_MATCH_MASK;
for (mc_cnt = 0; mc_cnt < llcc_priv->num_mc; mc_cnt++) {
offset = BEAC0_PROF_FILTER_0_CFG4(llcc_priv->drv_ver)
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
if (enable)
val = (mask & ADDR_LOWER_MASK) << BEAC_ADDR_LOWER_MASK_SHIFT;
mask_val = BEAC_ADDR_LOWER_MASK_MASK;
for (mc_cnt = 0; mc_cnt < llcc_priv->num_mc; mc_cnt++) {
offset = BEAC0_PROF_FILTER_0_CFG3(llcc_priv->drv_ver)
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
if (enable) {
match = (match & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
mask = (mask & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
val = (match << FEAC_ADDR_UPPER_MATCH_SHIFT) |
(mask << FEAC_ADDR_UPPER_MASK_SHIFT);
}
mask_val = BEAC_ADDR_UPPER_MATCH_MASK | BEAC_ADDR_UPPER_MASK_MASK;
for (mc_cnt = 0; mc_cnt < llcc_priv->num_mc; mc_cnt++) {
offset = BEAC0_PROF_FILTER_0_CFG5(llcc_priv->drv_ver)
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
} else {
pr_err("unknown filter/not supported\n");
return;
@ -1111,7 +1172,8 @@ static void berc_event_config(struct llcc_perfmon_private *llcc_priv,
unsigned int event_type, unsigned int *counter_num,
bool enable)
{
uint32_t val = 0, mask_val, offset;
uint64_t val = 0;
uint32_t mask_val, offset;
mask_val = EVENT_SEL_MASK;
if (llcc_priv->filtered_ports & (1 << EVENT_PORT_BERC))
@ -1144,8 +1206,8 @@ static void berc_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void berc_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
@ -1173,7 +1235,8 @@ static void trp_event_config(struct llcc_perfmon_private *llcc_priv,
unsigned int event_type, unsigned int *counter_num,
bool enable)
{
uint32_t val = 0, mask_val;
uint64_t val = 0;
uint32_t mask_val;
mask_val = EVENT_SEL_MASK;
if (llcc_priv->version >= REV_2)
@ -1198,10 +1261,11 @@ static void trp_event_config(struct llcc_perfmon_private *llcc_priv,
}
static void trp_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val;
uint64_t val = 0;
uint32_t mask_val;
if (filter == SCID) {
if (llcc_priv->version >= REV_2) {

43
drivers/soc/qcom/llcc_perfmon.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _SOC_QCOM_LLCC_PERFMON_H_
@ -17,6 +17,8 @@
#define LLCC_COMMON_STATUS0(v) (VER_CHK(v) ? 0x3400C : 0x3000C)
/* FEAC */
#define FEAC_PROF_FILTER_0_CFG1(v) (VER_CHK(v) ? 0x43004 : 0x037004)
#define FEAC_PROF_FILTER_0_CFG2(v) (VER_CHK(v) ? 0x43008 : 0x037008)
#define FEAC_PROF_FILTER_0_CFG3(v) (VER_CHK(v) ? 0x4300C : 0x03700C)
#define FEAC_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x43014 : 0x037014)
#define FEAC_PROF_FILTER_0_CFG6(v) (VER_CHK(v) ? 0x43018 : 0x037018)
@ -37,6 +39,8 @@
+ 4 * (n))
/* BEAC */
#define BEAC0_PROF_FILTER_0_CFG3(v) (VER_CHK(v) ? 0x6100C : 0x04900C)
#define BEAC0_PROF_FILTER_0_CFG4(v) (VER_CHK(v) ? 0x61010 : 0x049010)
#define BEAC0_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x61014 : 0x049014)
#define BEAC0_PROF_FILTER_0_CFG2(v) (VER_CHK(v) ? 0x61008 : 0x049008)
#define BEAC0_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x61040 : 0x049040) \
@ -247,6 +251,22 @@
+ 0, \
FEAC_RD_BYTE_FILTER_EN_SHIFT)
#define FEAC_RD_BYTE_FILTER_EN BIT(FEAC_RD_BYTE_FILTER_EN_SHIFT)
#define FEAC_ADDR_LOWER_MATCH_SHIFT (0)
#define FEAC_ADDR_LOWER_MATCH_MASK GENMASK(FEAC_ADDR_LOWER_MATCH_SHIFT \
+ 31, \
FEAC_ADDR_LOWER_MATCH_SHIFT)
#define FEAC_ADDR_LOWER_MASK_SHIFT (0)
#define FEAC_ADDR_LOWER_MASK_MASK GENMASK(FEAC_ADDR_LOWER_MASK_SHIFT \
+ 31, \
FEAC_ADDR_LOWER_MASK_SHIFT)
#define FEAC_ADDR_UPPER_MATCH_SHIFT (0)
#define FEAC_ADDR_UPPER_MATCH_MASK GENMASK(FEAC_ADDR_UPPER_MATCH_SHIFT \
+ 4, \
FEAC_ADDR_UPPER_MATCH_SHIFT)
#define FEAC_ADDR_UPPER_MASK_SHIFT (4)
#define FEAC_ADDR_UPPER_MASK_MASK GENMASK(FEAC_ADDR_UPPER_MASK_SHIFT \
+ 4, \
FEAC_ADDR_UPPER_MASK_SHIFT)
/* BEAC */
#define BEAC_PROFTAG_MASK_SHIFT (14)
#define BEAC_PROFTAG_MASK_MASK GENMASK(BEAC_PROFTAG_MASK_SHIFT + 1,\
@ -275,6 +295,23 @@
+ 0, \
BEAC_RD_BEAT_FILTER_EN_SHIFT)
#define BEAC_RD_BEAT_FILTER_EN BIT(BEAC_RD_BEAT_FILTER_EN_SHIFT)
#define BEAC_ADDR_LOWER_MATCH_SHIFT (0)
#define BEAC_ADDR_LOWER_MATCH_MASK GENMASK(BEAC_ADDR_LOWER_MATCH_SHIFT \
+ 31, \
BEAC_ADDR_LOWER_MATCH_SHIFT)
#define BEAC_ADDR_LOWER_MASK_SHIFT (0)
#define BEAC_ADDR_LOWER_MASK_MASK GENMASK(BEAC_ADDR_LOWER_MASK_SHIFT \
+ 31, \
BEAC_ADDR_LOWER_MASK_SHIFT)
#define BEAC_ADDR_UPPER_MATCH_SHIFT (0)
#define BEAC_ADDR_UPPER_MATCH_MASK GENMASK(BEAC_ADDR_UPPER_MATCH_SHIFT \
+ 4, \
BEAC_ADDR_UPPER_MATCH_SHIFT)
#define BEAC_ADDR_UPPER_MASK_SHIFT (4)
#define BEAC_ADDR_UPPER_MASK_MASK GENMASK(BEAC_ADDR_UPPER_MASK_SHIFT \
+ 4, \
BEAC_ADDR_UPPER_MASK_SHIFT)
/* TRP */
#define TRP_SCID_MATCH_SHIFT (0)
#define TRP_SCID_MATCH_MASK GENMASK(TRP_SCID_MATCH_SHIFT + 4,\
@ -306,7 +343,9 @@
TRP_SCID_STATUS_CURRENT_CAP_SHIFT \
+ 14, \
TRP_SCID_STATUS_CURRENT_CAP_SHIFT)
#define ADDR_LOWER_MASK (0xFFFFFFFF)
#define ADDR_UPPER_MASK (0xF00000000)
#define ADDR_UPPER_SHIFT (32)
#define MAJOR_VER_MASK (0xFF000000)
#define BRANCH_MASK (0x00FF0000)
#define MINOR_MASK (0x0000FF00)