usb: cdns3: Fix uvc fail when DMA cross 4k boundery since sg enabled
commit 40c304109e866a7dc123661a5c8ca72f6b5e14e0 upstream.
Supposed DMA cross 4k bounder problem should be fixed at DEV_VER_V2, but
still met problem when do ISO transfer if sg enabled.
Data pattern likes below when sg enabled, package size is 1k and mult is 2
[UVC Header(8B) ] [data(3k - 8)] ...
The received data at offset 0xd000 will get 0xc000 data, len 0x70. Error
happen position as below pattern:
0xd000: wrong
0xe000: wrong
0xf000: correct
0x10000: wrong
0x11000: wrong
0x12000: correct
...
To avoid DMA cross 4k bounder at ISO transfer, reduce burst len according
to start DMA address's alignment.
Cc: <stable@vger.kernel.org>
Fixes: 7733f6c32e
("usb: cdns3: Add Cadence USB3 DRD Driver")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20231224153816.1664687-4-Frank.Li@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
45c766231e
commit
097cdc78c6
@ -1118,6 +1118,7 @@ static int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
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u32 togle_pcs = 1;
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int sg_iter = 0;
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int num_trb_req;
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int trb_burst;
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int num_trb;
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int address;
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u32 control;
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@ -1240,7 +1241,36 @@ static int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
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total_tdl += DIV_ROUND_UP(length,
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priv_ep->endpoint.maxpacket);
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trb->length |= cpu_to_le32(TRB_BURST_LEN(priv_ep->trb_burst_size) |
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trb_burst = priv_ep->trb_burst_size;
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/*
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* Supposed DMA cross 4k bounder problem should be fixed at DEV_VER_V2, but still
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* met problem when do ISO transfer if sg enabled.
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*
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* Data pattern likes below when sg enabled, package size is 1k and mult is 2
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* [UVC Header(8B) ] [data(3k - 8)] ...
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*
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* The received data at offset 0xd000 will get 0xc000 data, len 0x70. Error happen
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* as below pattern:
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* 0xd000: wrong
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* 0xe000: wrong
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* 0xf000: correct
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* 0x10000: wrong
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* 0x11000: wrong
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* 0x12000: correct
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* ...
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*
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* But it is still unclear about why error have not happen below 0xd000, it should
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* cross 4k bounder. But anyway, the below code can fix this problem.
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*
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* To avoid DMA cross 4k bounder at ISO transfer, reduce burst len according to 16.
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*/
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if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && priv_dev->dev_ver <= DEV_VER_V2)
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if (ALIGN_DOWN(trb->buffer, SZ_4K) !=
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ALIGN_DOWN(trb->buffer + length, SZ_4K))
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trb_burst = 16;
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trb->length |= cpu_to_le32(TRB_BURST_LEN(trb_burst) |
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TRB_LEN(length));
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pcs = priv_ep->pcs ? TRB_CYCLE : 0;
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