perf vendor events: Update Intel haswellx
Events are updated to v26, the core metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py with updates at: https://github.com/captain5050/event-converter-for-linux-perf Updates include: - Uncore event updates by Zhengjun Xing <zhengjun.xing@linux.intel.com>. - Rename of topdown TMA metrics from Frontend_Bound to tma_frontend_bound. - _SMT suffix metrics are dropped as the #SMT_On and #EBS_Mode are correctly expanded in the single main metric. - Addition of all 6 levels of TMA metrics. Previously metrics involving topdown events were dropped. Child metrics are placed in a group named after their parent allowing children of a metric to be easily measured using the metric name with a _group suffix. - ## and ##? operators are correctly expanded. - The locate-with column is added to the long description describing a sampling event. - Metrics are written in terms of other metrics to reduce the expression size and increase readability. - Latest metrics from: https://github.com/intel/perfmon-metrics Tested with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers <irogers@google.com> Cc: Ahmad Yasin <ahmad.yasin@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Florian Fischer <florian.fischer@muhq.space> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Miaoqian Lin <linmq006@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Samantha Alt <samantha.alt@intel.com> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Richter <tmricht@linux.ibm.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Link: https://lore.kernel.org/r/20221004021612.325521-13-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers
Arnaldo Carvalho de Melo
parent
dd7aae2c2d
commit
08ce57dd1b
@ -691,7 +691,7 @@
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Cacheable and noncachaeble code read requests",
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"BriefDescription": "Cacheable and noncacheable code read requests",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB0",
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@ -161,7 +161,7 @@
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"CounterMask": "1",
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@ -172,7 +172,7 @@
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"UMask": "0x30"
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},
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{
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"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
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"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"CounterMask": "1",
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@ -182,7 +182,7 @@
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
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"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"CounterMask": "1",
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@ -193,7 +193,7 @@
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x79",
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@ -203,7 +203,7 @@
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x79",
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@ -224,7 +224,7 @@
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"UMask": "0x30"
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},
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{
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x79",
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File diff suppressed because it is too large
Load Diff
@ -980,6 +980,14 @@
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"PerPkg": "1",
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"Unit": "QPI LL"
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},
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{
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"BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
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"Counter": "0,1,2,3",
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"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
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"PerPkg": "1",
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"UMask": "0x2",
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"Unit": "QPI LL"
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},
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{
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"BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
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"Counter": "0,1,2,3",
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@ -990,12 +998,11 @@
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"Unit": "QPI LL"
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},
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{
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"BriefDescription": "Number of data flits transmitted ",
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"BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
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"Counter": "0,1,2,3",
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"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
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"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
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"PerPkg": "1",
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"ScaleUnit": "8Bytes",
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"UMask": "0x2",
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"UMask": "0x4",
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"Unit": "QPI LL"
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},
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{
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@ -1007,15 +1014,6 @@
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"UMask": "0x4",
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"Unit": "QPI LL"
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},
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{
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"BriefDescription": "Number of non data (control) flits transmitted ",
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"Counter": "0,1,2,3",
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"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
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"PerPkg": "1",
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"ScaleUnit": "8Bytes",
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"UMask": "0x4",
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"Unit": "QPI LL"
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},
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{
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"BriefDescription": "Flits Transferred - Group 1; SNP Flits",
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"Counter": "0,1,2,3",
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@ -72,20 +72,19 @@
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"Unit": "iMC"
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},
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{
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"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
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"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "LLC_MISSES.MEM_READ",
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"EventName": "UNC_M_CAS_COUNT.RD",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0x3",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "read requests to memory controller",
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"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "UNC_M_CAS_COUNT.RD",
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"EventName": "LLC_MISSES.MEM_READ",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0x3",
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@ -110,20 +109,19 @@
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"Unit": "iMC"
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},
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{
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"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
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"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "LLC_MISSES.MEM_WRITE",
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"EventName": "UNC_M_CAS_COUNT.WR",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0xC",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "write requests to memory controller",
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"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "UNC_M_CAS_COUNT.WR",
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"EventName": "LLC_MISSES.MEM_WRITE",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0xC",
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@ -9,7 +9,7 @@ GenuineIntel-6-9[6C],v1.03,elkhartlake,core
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GenuineIntel-6-5[CF],v13,goldmont,core
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GenuineIntel-6-7A,v1.01,goldmontplus,core
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GenuineIntel-6-(3C|45|46),v32,haswell,core
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GenuineIntel-6-3F,v25,haswellx,core
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GenuineIntel-6-3F,v26,haswellx,core
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GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core
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GenuineIntel-6-6[AC],v1.15,icelakex,core
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GenuineIntel-6-3A,v22,ivybridge,core
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