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stmmac: intel: Enable SERDES PHY rx clk for PSE

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EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.

Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Voon Weifeng 2021-04-06 09:32:50 +08:00 committed by David S. Miller
parent 56f15e2cb1
commit 017d6250ad
2 changed files with 11 additions and 0 deletions
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10
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
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@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
return data;
}
/* PSE only - ungate SGMII PHY Rx Clock */
if (intel_priv->is_pse)
mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
0, SERDES_PHY_RX_CLK);
return 0;
}
@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
/* PSE only - gate SGMII PHY Rx Clock */
if (intel_priv->is_pse)
mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
SERDES_PHY_RX_CLK, 0);
/* move power state to P3 */
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);

1
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
View File

@ -14,6 +14,7 @@
/* SERDES defines */
#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
#define SERDES_RST BIT(2) /* Serdes Reset */
#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
#define SERDES_PWR_ST_SHIFT 4