2019-05-27 08:55:01 +02:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2016-09-30 10:32:54 +08:00
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/*
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* Ptrace test for GPR/FPR registers in TM context
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*
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* Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
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*/
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#include "ptrace.h"
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#include "ptrace-gpr.h"
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#include "tm.h"
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/* Tracer and Tracee Shared Data */
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int shm_id;
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unsigned long *cptr, *pptr;
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float a = FPR_1;
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float b = FPR_2;
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float c = FPR_3;
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void tm_gpr(void)
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{
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unsigned long gpr_buf[18];
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unsigned long result, texasr;
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float fpr_buf[32];
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printf("Starting the child\n");
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cptr = (unsigned long *)shmat(shm_id, NULL, 0);
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trans:
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cptr[1] = 0;
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asm __volatile__(
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ASM_LOAD_GPR_IMMED(gpr_1)
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ASM_LOAD_FPR_SINGLE_PRECISION(flt_1)
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"1: ;"
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"tbegin.;"
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"beq 2f;"
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ASM_LOAD_GPR_IMMED(gpr_2)
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ASM_LOAD_FPR_SINGLE_PRECISION(flt_2)
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"tsuspend.;"
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"li 7, 1;"
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"stw 7, 0(%[cptr1]);"
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"tresume.;"
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"b .;"
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"tend.;"
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"li 0, 0;"
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"ori %[res], 0, 0;"
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"b 3f;"
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/* Transaction abort handler */
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"2: ;"
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"li 0, 1;"
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"ori %[res], 0, 0;"
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"mfspr %[texasr], %[sprn_texasr];"
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"3: ;"
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: [res] "=r" (result), [texasr] "=r" (texasr)
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: [gpr_1]"i"(GPR_1), [gpr_2]"i"(GPR_2),
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selftests/powerpc: Allocate base registers
Some ptrace selftests are passing input operands using a constraint that
can allocate any register for the operand, and using these registers on
load/store operations.
If the register allocated by the compiler happens to be zero (r0), it might
cause an invalid memory address access, since load and store operations
consider the content of 0x0 address if the base register is r0, instead of
the content of the r0 register. For example:
r1 := 0xdeadbeef
r0 := 0xdeadbeef
ld r2, 0(1) /* will load into r2 the content of r1 address */
ld r2, 0(0) /* will load into r2 the content of 0x0 */
In order to avoid this possible problem, the inline assembly constraint
should be aware that these registers will be used as a base register, thus,
r0 should not be allocated.
Other than that, this patch removes inline assembly operands that are not
used by the tests.
Signed-off-by: Breno Leitao <leitao@debian.org>
Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-10-31 11:38:20 -03:00
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[sprn_texasr] "i" (SPRN_TEXASR), [flt_1] "b" (&a),
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[flt_2] "b" (&b), [cptr1] "b" (&cptr[1])
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2016-09-30 10:32:54 +08:00
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: "memory", "r7", "r8", "r9", "r10",
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"r11", "r12", "r13", "r14", "r15", "r16",
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"r17", "r18", "r19", "r20", "r21", "r22",
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"r23", "r24", "r25", "r26", "r27", "r28",
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"r29", "r30", "r31"
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);
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if (result) {
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if (!cptr[0])
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goto trans;
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shmdt((void *)cptr);
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store_gpr(gpr_buf);
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store_fpr_single_precision(fpr_buf);
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if (validate_gpr(gpr_buf, GPR_3))
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exit(1);
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if (validate_fpr_float(fpr_buf, c))
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exit(1);
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exit(0);
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}
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shmdt((void *)cptr);
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exit(1);
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}
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int trace_tm_gpr(pid_t child)
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{
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unsigned long gpr[18];
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unsigned long fpr[32];
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FAIL_IF(start_trace(child));
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FAIL_IF(show_gpr(child, gpr));
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FAIL_IF(validate_gpr(gpr, GPR_2));
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FAIL_IF(show_fpr(child, fpr));
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FAIL_IF(validate_fpr(fpr, FPR_2_REP));
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FAIL_IF(show_ckpt_fpr(child, fpr));
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FAIL_IF(validate_fpr(fpr, FPR_1_REP));
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FAIL_IF(show_ckpt_gpr(child, gpr));
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FAIL_IF(validate_gpr(gpr, GPR_1));
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FAIL_IF(write_ckpt_gpr(child, GPR_3));
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FAIL_IF(write_ckpt_fpr(child, FPR_3_REP));
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pptr[0] = 1;
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FAIL_IF(stop_trace(child));
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return TEST_PASS;
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}
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int ptrace_tm_gpr(void)
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{
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pid_t pid;
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int ret, status;
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SKIP_IF(!have_htm());
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shm_id = shmget(IPC_PRIVATE, sizeof(int) * 2, 0777|IPC_CREAT);
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pid = fork();
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if (pid < 0) {
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perror("fork() failed");
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return TEST_FAIL;
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}
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if (pid == 0)
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tm_gpr();
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if (pid) {
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pptr = (unsigned long *)shmat(shm_id, NULL, 0);
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while (!pptr[1])
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asm volatile("" : : : "memory");
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ret = trace_tm_gpr(pid);
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if (ret) {
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kill(pid, SIGTERM);
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return TEST_FAIL;
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}
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shmdt((void *)pptr);
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ret = wait(&status);
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shmctl(shm_id, IPC_RMID, NULL);
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if (ret != pid) {
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printf("Child's exit status not captured\n");
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return TEST_FAIL;
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}
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return (WIFEXITED(status) && WEXITSTATUS(status)) ? TEST_FAIL :
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TEST_PASS;
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}
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return TEST_PASS;
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}
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int main(int argc, char *argv[])
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{
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return test_harness(ptrace_tm_gpr, "ptrace_tm_gpr");
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}
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