ad4eb1f407
To improve code readability address multiple warnings and errors. Fixed coding style issues such as indentation, spacing, semicolon, etc. Change-Id: Id0f87f055ae69b92902d181ed61e0cf2fd77e6e2 Signed-off-by: Sanjay Yadav <quic_sanjyada@quicinc.com>
265 lines
7.7 KiB
C
265 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _KGSL_UTIL_H_
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#define _KGSL_UTIL_H_
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#include <linux/version.h>
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#define KGSL_DRIVER "kgsl_driver"
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#define KGSL_ADRENO_DEVICE "kgsl_adreno_device"
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#define KGSL_A6XX_DEVICE "kgsl_a6xx_device"
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#define KGSL_GEN7_DEVICE "kgsl_gen7_device"
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#define KGSL_HWSCHED_DEVICE "kgsl_hwsched_device"
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#define KGSL_GEN8_DEVICE "kgsl_gen8_device"
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#define KGSL_SCRATCH_ENTRY "kgsl_scratch"
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#define KGSL_MEMSTORE_ENTRY "kgsl_memstore"
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#define KGSL_GMU_LOG_ENTRY "kgsl_gmu_log"
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#define KGSL_GMU_TRACE_ENTRY "kgsl_gmu_trace"
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#define KGSL_HFIMEM_ENTRY "kgsl_hfi_mem"
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#define KGSL_GMU_DUMPMEM_ENTRY "kgsl_gmu_dump_mem"
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#define KGSL_GMU_RB_ENTRY "kgsl_gmu_rb"
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#define KGSL_GMU_KERNEL_PROF_ENTRY "kgsl_gmu_kernel_profiling"
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#define KGSL_GMU_USER_PROF_ENTRY "kgsl_gmu_user_profiling"
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#define KGSL_GMU_CMD_BUFFER_ENTRY "kgsl_gmu_cmd_buffer"
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#define KGSL_HFI_BIG_IB_ENTRY "kgsl_hfi_big_ib"
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#define KGSL_HFI_BIG_IB_REC_ENTRY "kgsl_hfi_big_ib_rec"
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#define KGSL_ADRENO_CTX_ENTRY "kgsl_adreno_ctx"
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#define KGSL_PROC_PRIV_ENTRY "kgsl_proc_priv"
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#define KGSL_PGTABLE_ENTRY "kgsl_pgtable"
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#define KGSL_GMU_VRB_ENTRY "kgsl_gmu_vrb"
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#define MAX_VA_MINIDUMP_STR_LEN 32
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/**
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* Request TZ to program set of access controlled registers that KGSL needs
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* irrespective of any features
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*/
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#define GPU_ALWAYS_EN_REQ BIT(0)
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/**
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* Request TZ to program BCL id to access controlled register when BCL is
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* enabled
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*/
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#define GPU_BCL_EN_REQ BIT(1)
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/**
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* Request TZ to program set of access controlled register for CLX feature
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* when enabled
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*/
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#define GPU_CLX_EN_REQ BIT(2)
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/**
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* Request TZ to program tsense ids to access controlled registers for reading
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* gpu temperature sensors
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*/
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#define GPU_TSENSE_EN_REQ BIT(3)
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struct regulator;
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struct clk_bulk_data;
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/**
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* struct cpu_gpu_lock - CP spinlock structure for power up list
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* @gpu_req: flag value set by CP
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* @cpu_req: flag value set by KMD
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* @turn: turn variable set by both CP and KMD
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* @list_length: this tells CP the last dword in the list:
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* 16 + (4 * (List_Length - 1))
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* @list_offset: this tells CP the start of preemption only list:
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* 16 + (4 * List_Offset)
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* @ifpc_list_len: number of static ifpc duplets in the list
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* @preemption_list_len: number of static preemption duplets in the list
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* @dynamic_list_len: number of dynamically added triplets in the list
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*/
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struct cpu_gpu_lock {
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u32 gpu_req;
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u32 cpu_req;
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u32 turn;
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union {
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struct {
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u16 list_length;
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u16 list_offset;
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};
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struct {
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u8 ifpc_list_len;
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u8 preemption_list_len;
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u16 dynamic_list_len;
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};
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};
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};
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/**
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* kgsl_hwlock - Try to get the spinlock
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* @lock: cpu_gpu_lock structure
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*
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* Spin while the GPU has the lock.
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*
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* Return: 0 if lock is successful, -EBUSY if timed out waiting for lock
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*/
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int kgsl_hwlock(struct cpu_gpu_lock *lock);
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/**
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* kgsl_hwunlock - Release a previously grabbed lock
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* @lock: cpu_gpu_lock structure
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*/
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void kgsl_hwunlock(struct cpu_gpu_lock *lock);
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/**
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* kgsl_regulator_disable_wait - Disable a regulator and wait for it
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* @reg: A &struct regulator handle
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* @timeout: Time to wait (in milliseconds)
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*
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* Disable the regulator and wait @timeout milliseconds for it to enter the
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* disabled state.
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*
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* Return: True if the regulator was disabled or false if it timed out
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*/
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bool kgsl_regulator_disable_wait(struct regulator *reg, u32 timeout);
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/**
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* kgsl_of_clk_by_name - Return a clock device for a given name
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* @clks: Pointer to an array of bulk clk data
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* @count: Number of entries in the array
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* @id: Name of the clock to search for
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*
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* Returns: A pointer to the clock device for the given name or NULL if not
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* found
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*/
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struct clk *kgsl_of_clk_by_name(struct clk_bulk_data *clks, int count,
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const char *id);
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/**
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* kgsl_regulator_set_voltage - Set voltage level for regulator
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* @dev: A &struct device pointer
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* @reg: A &struct regulator handle
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* @voltage: Voltage value to set regulator
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*
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* Return: 0 on success and negative error on failure.
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*/
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int kgsl_regulator_set_voltage(struct device *dev,
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struct regulator *reg, u32 voltage);
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/**
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* kgsl_clk_set_rate - Set a clock to a given rate
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* @clks: Pointer to an array of bulk clk data
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* @count: Number of entries in the array
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* @id: Name of the clock to search for
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* @rate: Rate to st the clock to
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*
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* Return: 0 on success or negative error on failure
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*/
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int kgsl_clk_set_rate(struct clk_bulk_data *clks, int num_clks,
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const char *id, unsigned long rate);
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/**
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* kgsl_scm_gpu_init_regs - Load secure registers through tz
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* @dev: Pointer to the GPU platform device
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* @gpu_req: Bit mask of requests to enable
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*
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* Return: 0 on success or negative on failure and EOPNOTSUPP if scm call
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* not supported
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*/
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#if (KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE)
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int kgsl_scm_gpu_init_regs(struct device *dev, u32 gpu_req);
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#else
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static inline int kgsl_scm_gpu_init_regs(struct device *dev, u32 gpu_req)
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{
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return -EOPNOTSUPP;
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}
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#endif
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/**
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* kgsl_zap_shader_load - Load a zap shader
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* @dev: Pointer to the struct device for the GPU platform device
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* @name: Basename of the zap shader to load (without the postfix)
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*
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* Load and install the zap shader named @name. Name should be specified without
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* the extension for example "a660_zap" instead of "a660_zap.mdt".
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*
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* Return: 0 on success or negative on failure
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*/
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int kgsl_zap_shader_load(struct device *dev, const char *name);
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/**
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* kgsl_zap_shader_unload - Unload a zap shader
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* @dev: Pointer to the struct device for the GPU platform device
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*
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* Unload zap_shader and shutdown the peripheral
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* Return: 0 on success or negative on failure
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*/
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int kgsl_zap_shader_unload(struct device *dev);
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#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP)
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/**
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* kgsl_add_to_minidump - Add a physically contiguous section to minidump
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* @name: Name of the section
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* @virt_addr: Virtual address of the section
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* @phy_addr: Physical address of the section
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* @size: Size of the section
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*/
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void kgsl_add_to_minidump(char *name, u64 virt_addr, u64 phy_addr, size_t size);
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/**
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* kgsl_remove_from_minidump - Remove a contiguous section from minidump
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* @name: Name of the section
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* @virt_addr: Virtual address of the section
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* @phy_addr: Physical address of the section
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* @size: Size of the section
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*/
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void kgsl_remove_from_minidump(char *name, u64 virt_addr, u64 phy_addr, size_t size);
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/**
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* kgsl_add_va_to_minidump - Add a physically non-contiguous section to minidump
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* @dev: Pointer to the struct device for the GPU platform device
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* @name: Name of the section
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* @ptr: Virtual address of the section
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* @size: Size of the section
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*/
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int kgsl_add_va_to_minidump(struct device *dev, const char *name, void *ptr,
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size_t size);
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/**
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* kgsl_qcom_va_md_register - Register driver with va-minidump
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* @device: Pointer to kgsl device
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*/
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void kgsl_qcom_va_md_register(struct kgsl_device *device);
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/**
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* kgsl_qcom_va_md_unregister - Unregister driver with va-minidump
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* @device: Pointer to kgsl device
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*/
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void kgsl_qcom_va_md_unregister(struct kgsl_device *device);
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#else
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static inline void kgsl_add_to_minidump(char *name, u64 virt_addr, u64 phy_addr, size_t size)
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{
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}
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static inline void kgsl_remove_from_minidump(char *name, u64 virt_addr, u64 phy_addr, size_t size)
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{
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}
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static inline int kgsl_add_va_to_minidump(struct device *dev, const char *name, void *ptr,
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size_t size)
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{
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return 0;
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}
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static inline void kgsl_qcom_va_md_register(struct kgsl_device *device)
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{
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}
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static inline void kgsl_qcom_va_md_unregister(struct kgsl_device *device)
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{
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}
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#endif
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/**
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* isdb_write - Program isdb registers to issue break commands to SP
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* @base: Base address of qdss registers to be programmed
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* @offset: offset to the SP block
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*/
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void isdb_write(void __iomem *base, u32 offset);
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#endif
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