37683929f0
Do a major reorganization of the coresight code. Move all the coresight definitions to their own files that are conditional on CONFIG_QCOM_KGSL_CORESIGHT. Next, add the regmap for "cx_dbgc" so that we can get rid of the single purpose cx_dgbc registers and replace them with the standard register read/write functions. Then finish making the coresight functions more generic and have the individual targets register themselves with coresight instead of keeping a pointer in the gpudev struct. Change-Id: Ic479934ef2ec6413cbac7498206d0202e7f76d5a Signed-off-by: Nitheesh Muthuraj <quic_nmuthuraj@quicinc.com> Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __A3XX_H
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#define __A3XX_H
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#include "a3xx_reg.h"
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/**
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* struct adreno_a3xx_core - a3xx specific GPU core definitions
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*/
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struct adreno_a3xx_core {
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/** @base: Container for the generic &struct adreno_gpu_core */
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struct adreno_gpu_core base;
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/** pm4fw_name: Name of the PM4 microcode file */
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const char *pm4fw_name;
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/** pfpfw_name: Name of the PFP microcode file */
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const char *pfpfw_name;
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/** @vbif: List of registers and values to write for VBIF */
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const struct kgsl_regmap_list *vbif;
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/** @vbif_count: Number of registers in @vbif */
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u32 vbif_count;
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};
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struct adreno_device;
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/**
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* to_a3xx_core - return the a3xx specific GPU core struct
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* @adreno_dev: An Adreno GPU device handle
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*
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* Returns:
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* A pointer to the a3xx specific GPU core struct
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*/
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static inline const struct adreno_a3xx_core *
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to_a3xx_core(struct adreno_device *adreno_dev)
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{
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const struct adreno_gpu_core *core = adreno_dev->gpucore;
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return container_of(core, struct adreno_a3xx_core, base);
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}
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void a3xx_snapshot(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot);
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extern const struct adreno_perfcounters adreno_a3xx_perfcounters;
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/**
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* a3xx_ringbuffer_init - Initialize the ringbuffer
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* @adreno_dev: An Adreno GPU handle
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*
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* Initialize the ringbuffer for a3xx.
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* Return: 0 on success or negative on failure
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*/
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int a3xx_ringbuffer_init(struct adreno_device *adreno_dev);
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/**
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* a3xx_ringbuffer_submitcmd - Submit a user command to the ringbuffer
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* @adreno_dev: An Adreno GPU handle
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* @cmdobj: Pointer to a user command object
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* @flags: Internal submit flags
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* @time: Optional pointer to a adreno_submit_time container
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*
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* Return: 0 on success or negative on failure
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*/
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int a3xx_ringbuffer_submitcmd(struct adreno_device *adreno_dev,
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struct kgsl_drawobj_cmd *cmdobj, u32 flags,
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struct adreno_submit_time *time);
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#ifdef CONFIG_QCOM_KGSL_CORESIGHT
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void a3xx_coresight_init(struct adreno_device *device);
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#else
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static inline void a3xx_coresight_init(struct adreno_device *device) { }
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#endif
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#endif /*__A3XX_H */
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