880d405719
git-subtree-dir: qcom/opensource/graphics-kernel git-subtree-mainline:992813d9c1git-subtree-split:b4fdc4c042Change-Id: repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel tag: GRAPHICS.LA.14.0.r1-07700-lanai.0
215 lines
7.0 KiB
C
215 lines
7.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __KGSL_IOMMU_H
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#define __KGSL_IOMMU_H
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#include <linux/adreno-smmu-priv.h>
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#include <linux/io-pgtable.h>
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/*
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* These defines control the address range for allocations that
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* are mapped into all pagetables.
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*/
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#define KGSL_IOMMU_GLOBAL_MEM_SIZE (20 * SZ_1M)
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#define KGSL_IOMMU_GLOBAL_MEM_BASE32 0xf8000000
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#define KGSL_IOMMU_GLOBAL_MEM_BASE64 \
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(KGSL_MEMSTORE_TOKEN_ADDRESS - KGSL_IOMMU_GLOBAL_MEM_SIZE)
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/*
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* This is a dummy token address that we use to identify memstore when the user
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* wants to map it. mmap() uses a unsigned long for the offset so we need a 32
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* bit value that works with all sized apps. We chose a value that was purposely
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* unmapped so if you increase the global memory size make sure it doesn't
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* conflict
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*/
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#define KGSL_MEMSTORE_TOKEN_ADDRESS (KGSL_IOMMU_SECURE_BASE32 - SZ_4K)
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#define KGSL_IOMMU_GLOBAL_MEM_BASE(__mmu) \
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(test_bit(KGSL_MMU_64BIT, &(__mmu)->features) ? \
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KGSL_IOMMU_GLOBAL_MEM_BASE64 : KGSL_IOMMU_GLOBAL_MEM_BASE32)
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#define KGSL_IOMMU_SVM_BASE32(__mmu) \
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(ADRENO_DEVICE(KGSL_MMU_DEVICE(__mmu))->uche_gmem_base + \
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ADRENO_DEVICE(KGSL_MMU_DEVICE(__mmu))->gpucore->gmem_size)
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#define KGSL_IOMMU_SVM_END32(__mmu) \
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(test_bit(KGSL_MMU_64BIT, &(__mmu)->features) ? \
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(test_bit(KGSL_MMU_IOPGTABLE, &(__mmu)->features) ? \
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KGSL_MEMSTORE_TOKEN_ADDRESS : \
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KGSL_IOMMU_GLOBAL_MEM_BASE64) : \
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(0xC0000000 - SZ_16M))
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/*
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* Limit secure size to 256MB for 32bit kernels.
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*/
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#define KGSL_IOMMU_SECURE_SIZE32 SZ_256M
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#define KGSL_IOMMU_SECURE_BASE32 \
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(KGSL_IOMMU_SECURE_BASE64 - KGSL_IOMMU_SECURE_SIZE32)
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#define KGSL_IOMMU_SECURE_END32 KGSL_IOMMU_SECURE_BASE64
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#define KGSL_IOMMU_SECURE_BASE64 0x100000000ULL
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#define KGSL_IOMMU_SECURE_END64 \
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(KGSL_IOMMU_SECURE_BASE64 + KGSL_IOMMU_SECURE_SIZE64)
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#define KGSL_IOMMU_MAX_SECURE_SIZE 0xFFFFF000
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#define KGSL_IOMMU_SECURE_SIZE64 \
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(KGSL_IOMMU_MAX_SECURE_SIZE - KGSL_IOMMU_SECURE_SIZE32)
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#define KGSL_IOMMU_SECURE_BASE(_mmu) (test_bit(KGSL_MMU_64BIT, \
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&(_mmu)->features) ? KGSL_IOMMU_SECURE_BASE64 : \
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KGSL_IOMMU_SECURE_BASE32)
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#define KGSL_IOMMU_SECURE_END(_mmu) (test_bit(KGSL_MMU_64BIT, \
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&(_mmu)->features) ? KGSL_IOMMU_SECURE_END64 : \
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KGSL_IOMMU_SECURE_END32)
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#define KGSL_IOMMU_SECURE_SIZE(_mmu) (test_bit(KGSL_MMU_64BIT, \
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&(_mmu)->features) ? KGSL_IOMMU_MAX_SECURE_SIZE : \
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KGSL_IOMMU_SECURE_SIZE32)
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/* The CPU supports 39 bit addresses */
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#define KGSL_IOMMU_SVM_BASE64 0x1000000000ULL
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#define KGSL_IOMMU_SVM_END64 0x4000000000ULL
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#define KGSL_IOMMU_VA_BASE64 0x4000000000ULL
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#define KGSL_IOMMU_VA_END64 0x8000000000ULL
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#define CP_APERTURE_REG 0
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#define CP_SMMU_APERTURE_ID 0x1B
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/* Global SMMU register offsets */
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#define KGSL_IOMMU_PRR_CFG_LADDR 0x6008
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#define KGSL_IOMMU_PRR_CFG_UADDR 0x600c
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/* Register offsets */
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#define KGSL_IOMMU_CTX_SCTLR 0x0000
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#define KGSL_IOMMU_CTX_ACTLR 0x0004
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#define KGSL_IOMMU_CTX_TTBR0 0x0020
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#define KGSL_IOMMU_CTX_CONTEXTIDR 0x0034
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#define KGSL_IOMMU_CTX_FSR 0x0058
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#define KGSL_IOMMU_CTX_TLBIALL 0x0618
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#define KGSL_IOMMU_CTX_RESUME 0x0008
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#define KGSL_IOMMU_CTX_FSYNR0 0x0068
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#define KGSL_IOMMU_CTX_FSYNR1 0x006c
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#define KGSL_IOMMU_CTX_TLBSYNC 0x07f0
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#define KGSL_IOMMU_CTX_TLBSTATUS 0x07f4
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/* TLBSTATUS register fields */
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#define KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE BIT(0)
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/* SCTLR fields */
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#define KGSL_IOMMU_SCTLR_HUPCF_SHIFT 8
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#define KGSL_IOMMU_SCTLR_CFCFG_SHIFT 7
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#define KGSL_IOMMU_SCTLR_CFIE_SHIFT 6
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#define KGSL_IOMMU_ACTLR_PRR_ENABLE BIT(5)
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/* FSR fields */
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#define KGSL_IOMMU_FSR_SS_SHIFT 30
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/* ASID field in TTBR register */
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#define KGSL_IOMMU_ASID_START_BIT 48
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/* offset at which a nop command is placed in setstate */
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#define KGSL_IOMMU_SETSTATE_NOP_OFFSET 1024
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/*
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* struct kgsl_iommu_context - Structure holding data about an iommu context
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* bank
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* @pdev: pointer to the iommu context's platform device
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* @name: context name
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* @id: The id of the context, used for deciding how it is used.
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* @cb_num: The hardware context bank number, used for calculating register
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* offsets.
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* @kgsldev: The kgsl device that uses this context.
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* @stalled_on_fault: Flag when set indicates that this iommu device is stalled
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* on a page fault
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*/
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struct kgsl_iommu_context {
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struct platform_device *pdev;
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const char *name;
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int cb_num;
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struct kgsl_device *kgsldev;
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bool stalled_on_fault;
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/** ratelimit: Ratelimit state for the context */
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struct ratelimit_state ratelimit;
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struct iommu_domain *domain;
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struct adreno_smmu_priv adreno_smmu;
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};
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/*
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* struct kgsl_iommu - Structure holding iommu data for kgsl driver
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* @regbase: Virtual address of the IOMMU register base
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* @regstart: Physical address of the iommu registers
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* @regsize: Length of the iommu register region.
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* @setstate: Scratch GPU memory for IOMMU operations
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* @clk_enable_count: The ref count of clock enable calls
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* @clks: Array of pointers to IOMMU clocks
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* @smmu_info: smmu info used in a5xx preemption
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*/
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struct kgsl_iommu {
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/** @user_context: Container for the user iommu context */
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struct kgsl_iommu_context user_context;
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/** @secure_context: Container for the secure iommu context */
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struct kgsl_iommu_context secure_context;
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/** @lpac_context: Container for the LPAC iommu context */
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struct kgsl_iommu_context lpac_context;
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void __iomem *regbase;
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struct kgsl_memdesc *setstate;
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atomic_t clk_enable_count;
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struct clk_bulk_data *clks;
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int num_clks;
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struct kgsl_memdesc *smmu_info;
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/** @pdev: Pointer to the platform device for the IOMMU device */
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struct platform_device *pdev;
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/**
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* @ppt_active: Set when the first per process pagetable is created.
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* This is used to warn when global buffers are created that might not
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* be mapped in all contexts
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*/
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bool ppt_active;
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/** @cb0_offset: Offset of context bank 0 from iommu register base */
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u32 cb0_offset;
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/** @pagesize: Size of each context bank register space */
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u32 pagesize;
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/** @cx_gdsc: CX GDSC handle in case the IOMMU needs it */
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struct regulator *cx_gdsc;
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};
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/*
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* struct kgsl_iommu_pt - Iommu pagetable structure private to kgsl driver
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* @base: Container of the base kgsl pagetable
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* @ttbr0: register value to set when using this pagetable
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* @pgtbl_ops: Pagetable operations for mapping/unmapping buffers
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* @info: Pagetable info used to allocate pagetable operations
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*/
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struct kgsl_iommu_pt {
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struct kgsl_pagetable base;
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u64 ttbr0;
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struct io_pgtable_ops *pgtbl_ops;
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struct qcom_io_pgtable_info info;
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};
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/**
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* kgsl_set_smmu_aperture - set SMMU Aperture for user context
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* @device: A GPU device handle
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*
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* Return: 0 on success or negative on failure.
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*/
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int kgsl_set_smmu_aperture(struct kgsl_device *device,
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struct kgsl_iommu_context *context);
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/**
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* kgsl_set_smmu_lpac_aperture - set SMMU Aperture for LPAC context
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* @device: Pointer to the KGSL device
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* @context: Pointer to the LPAC iommu context
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*
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* Return: 0 on success or negative on failure.
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*/
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int kgsl_set_smmu_lpac_aperture(struct kgsl_device *device,
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struct kgsl_iommu_context *context);
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#endif
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