880d405719
git-subtree-dir: qcom/opensource/graphics-kernel git-subtree-mainline:992813d9c1git-subtree-split:b4fdc4c042Change-Id: repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel tag: GRAPHICS.LA.14.0.r1-07700-lanai.0
107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __ADRENO_A6XX_RGMU_H
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#define __ADRENO_A6XX_RGMU_H
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#define RGMU_AO_IRQ_FENCE_ERR BIT(3)
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#define RGMU_AO_IRQ_MASK RGMU_AO_IRQ_FENCE_ERR
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#define RGMU_OOB_IRQ_ERR_MSG BIT(24)
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#define RGMU_OOB_IRQ_ACK_MASK GENMASK(23, 16)
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#define RGMU_OOB_IRQ_ERR_MSG_MASK GENMASK(31, 24)
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#define RGMU_OOB_IRQ_MASK RGMU_OOB_IRQ_ERR_MSG_MASK
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#define MAX_RGMU_CLKS 8
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enum {
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/* @RGMU_PRIV_FIRST_BOOT_DONE: The very first ggpu boot is done */
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RGMU_PRIV_FIRST_BOOT_DONE,
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/* @RGMU_PRIV_GPU_STARTED: GPU has been started */
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RGMU_PRIV_GPU_STARTED,
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/* @RGMU_PRIV_PM_SUSPEND: The rgmu driver is suspended */
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RGMU_PRIV_PM_SUSPEND,
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};
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/**
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* struct a6xx_rgmu_device - rGMU device structure
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* @ver: RGMU firmware version
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* @rgmu_interrupt_num: RGMU interrupt number
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* @oob_interrupt_num: number of RGMU asserted OOB interrupt
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* @fw_hostptr: Buffer which holds the RGMU firmware
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* @fw_size: Size of RGMU firmware buffer
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* @clks: RGMU clocks including the GPU
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* @gpu_clk: Pointer to GPU core clock
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* @rgmu_clk: Pointer to rgmu clock
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* @flags: RGMU flags
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* @idle_level: Minimal GPU idle power level
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* @fault_count: RGMU fault count
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*/
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struct a6xx_rgmu_device {
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u32 ver;
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struct platform_device *pdev;
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unsigned int rgmu_interrupt_num;
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unsigned int oob_interrupt_num;
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unsigned int *fw_hostptr;
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uint32_t fw_size;
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struct clk_bulk_data *clks;
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/** @num_clks: Number of clocks in @clks */
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int num_clks;
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struct clk *gpu_clk;
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struct clk *rgmu_clk;
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unsigned int idle_level;
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unsigned int fault_count;
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/** @flags: rgmu internal flags */
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unsigned long flags;
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/** @num_oob_perfcntr: Number of active oob_perfcntr requests */
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u32 num_oob_perfcntr;
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};
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/**
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* a6xx_rgmu_device_probe - Probe a6xx rgmu resources
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* @pdev: Pointer to the platform device
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* @chipid: Chipid of the target
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* @gpucore: Pointer to the gpucore
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*
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* The target specific probe function for rgmu based a6xx targets.
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*/
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int a6xx_rgmu_device_probe(struct platform_device *pdev,
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u32 chipid, const struct adreno_gpu_core *gpucore);
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/**
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* a6xx_rgmu_reset - Reset and restart the rgmu
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* @adreno_dev: Pointer to the adreno device
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*
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* Return: 0 on success or negative error on failure
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*/
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int a6xx_rgmu_reset(struct adreno_device *adreno_dev);
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/**
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* a6xx_rgmu_snapshot - Take snapshot for rgmu based targets
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* @adreno_dev: Pointer to the adreno device
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* @snapshot: Pointer to the snapshot
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*
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* This function halts rgmu execution if we hit a rgmu
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* fault. And then, it takes rgmu and gpu snapshot.
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*/
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void a6xx_rgmu_snapshot(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot);
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/**
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* a6xx_rgmu_add_to_minidump - Register a6xx_device with va minidump
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* @adreno_dev: Pointer to the adreno device
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*/
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int a6xx_rgmu_add_to_minidump(struct adreno_device *adreno_dev);
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/**
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* a6xx_rgmu_gx_is_on() - Check if GX is on using pwr status register
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* @adreno_dev: Pointer to the adreno device
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*
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* This check should only be performed if the keepalive bit is set or it
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* can be guaranteed that the power state of the GPU will remain unchanged
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*/
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bool a6xx_rgmu_gx_is_on(struct adreno_device *adreno_dev);
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#endif
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