android/android_kernel_samsung_sm8650-modules
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Merge 06c05ba719 on remote branch

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Change-Id: I8db32ae2d34eb3cb03f63fa319223245a2b0ab9a
This commit is contained in:
Linux Build Service Account 2024-07-21 22:51:39 -07:00
commit ec377a993b
11 changed files with 158 additions and 91 deletions
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13
adreno.c
View File

@ -1602,6 +1602,12 @@ static int adreno_pm_suspend(struct device *dev)
if (status)
return status;
/*
* When the device enters in suspend state, the CX can be collapsed causing
* the GPU CX timer to pause. Clear the ADRENO_DEVICE_CX_TIMER_INITIALIZED
* flag to ensure that the CX timer is reseeded during resume.
*/
clear_bit(ADRENO_DEVICE_CX_TIMER_INITIALIZED, &adreno_dev->priv);
kgsl_reclaim_close();
kthread_flush_worker(device->events_worker);
flush_workqueue(kgsl_driver.lockless_workqueue);
@ -3698,6 +3704,13 @@ static int adreno_hibernation_suspend(struct device *dev)
if (status)
goto err;
/*
* When the device enters in hibernation state, the CX will be collapsed causing
* the GPU CX timer to pause. Clear the ADRENO_DEVICE_CX_TIMER_INITIALIZED flag
* to ensure that the CX timer is reseeded during resume.
*/
clear_bit(ADRENO_DEVICE_CX_TIMER_INITIALIZED, &adreno_dev->priv);
/*
* Unload zap shader during device hibernation and reload it
* during resume as there is possibility that TZ driver

5
adreno_gen7.c
View File

@ -354,7 +354,10 @@ void gen7_cx_timer_init(struct adreno_device *adreno_dev)
int i;
unsigned long flags;
/* Only gen7_9_x has the CX timer. Set it up just once */
/*
* Only gen7_9_x has the CX timer. Set it up during first boot or
* after suspend resume.
*/
if (!adreno_is_gen7_9_x(adreno_dev) ||
test_bit(ADRENO_DEVICE_CX_TIMER_INITIALIZED, &adreno_dev->priv))
return;

3
adreno_gen7_gmu.c
View File

@ -2032,6 +2032,9 @@ static int gen7_gmu_boot(struct adreno_device *adreno_dev)
*/
gen7_enable_ahb_timeout_detection(adreno_dev);
/* Initialize the CX timer */
gen7_cx_timer_init(adreno_dev);
ret = gen7_rscc_wakeup_sequence(adreno_dev);
if (ret)
goto clks_gdsc_off;

3
adreno_gen7_hwsched.c
View File

@ -620,6 +620,9 @@ static int gen7_hwsched_gmu_boot(struct adreno_device *adreno_dev)
*/
gen7_enable_ahb_timeout_detection(adreno_dev);
/* Initialize the CX timer */
gen7_cx_timer_init(adreno_dev);
ret = gen7_rscc_wakeup_sequence(adreno_dev);
if (ret)
goto clks_gdsc_off;

12
adreno_gen8.c
View File

@ -496,7 +496,7 @@ void gen8_cx_timer_init(struct adreno_device *adreno_dev)
int i;
unsigned long flags;
/* Set up the CX timer just once */
/* Set it up during first boot or after suspend resume */
if (test_bit(ADRENO_DEVICE_CX_TIMER_INITIALIZED, &adreno_dev->priv))
return;
@ -680,6 +680,9 @@ static void gen8_protect_init(struct adreno_device *adreno_dev)
FIELD_PREP(GENMASK(30, 18), count) |
FIELD_PREP(BIT(31), regs[i].noaccess),
PIPE_LPAC, 0, 0);
/* Clear aperture register */
gen8_host_aperture_set(adreno_dev, 0, 0, 0);
}
static void gen8_nonctxt_regconfig(struct adreno_device *adreno_dev)
@ -906,6 +909,9 @@ static void gen8_patch_pwrup_reglist(struct adreno_device *adreno_dev)
}
mutex_unlock(&gen8_dev->nc_mutex);
/* Clear aperture register */
gen8_host_aperture_set(adreno_dev, 0, 0, 0);
lock->dynamic_list_len = gen8_dev->ext_pwrup_list_len;
}
@ -2603,7 +2609,7 @@ static void gen8_lpac_fault_header(struct adreno_device *adreno_dev,
pr_context(device, drawobj->context, "lpac cmdline: %s\n",
drawctxt->base.proc_priv->cmdline);
if (!gx_on)
if (!gen8_gmu_rpmh_pwr_state_is_active(device) || !gx_on)
goto done;
kgsl_regread(device, GEN8_RBBM_LPAC_STATUS, &status);
@ -2659,7 +2665,7 @@ static void gen8_fault_header(struct adreno_device *adreno_dev,
drawctxt->base.proc_priv->cmdline);
}
if (!gx_on)
if (!gen8_gmu_rpmh_pwr_state_is_active(device) || !gx_on)
goto done;
kgsl_regread(device, GEN8_RBBM_STATUS, &status);

21
adreno_gen8_3_0_snapshot.h
View File

@ -1920,11 +1920,6 @@ static struct gen8_reg_list gen8_3_0_ahb_registers[] = {
{ UNSLICE, gen8_3_0_ahb_secure_gpu_registers },
};
static struct gen8_reg_list gen8_3_0_gmu_gx_regs[] = {
{ UNSLICE, gen8_3_0_gmugx_registers },
{ SLICE, gen8_3_0_gmugx_slice_registers },
};
/*
* Block : ['GDPM_LKG']
* REGION : UNSLICE
@ -2098,10 +2093,16 @@ static const u32 *gen8_3_0_external_core_regs[] = {
gen8_3_0_gpu_cc_ahb2phy_swman_registers,
gen8_3_0_gpu_cc_gpu_cc_reg_registers,
gen8_3_0_gpu_cc_pll0_cm_pll_lucid_ole_registers,
gen8_3_0_acd_acd_mnd_registers,
gen8_3_0_gx_clkctl_ahb2phy_broadcast_swman_registers,
gen8_3_0_gx_clkctl_ahb2phy_swman_registers,
gen8_3_0_gx_clkctl_pll0_cm_pll_lucid_ole_registers,
gen8_3_0_gx_clkctl_gx_clkctl_reg_registers,
};
static struct gen8_reg_list gen8_3_0_gmu_gx_regs[] = {
{ UNSLICE, gen8_3_0_gmugx_registers },
{ UNSLICE, gen8_3_0_gx_clkctl_ahb2phy_broadcast_swman_registers },
{ UNSLICE, gen8_3_0_gx_clkctl_ahb2phy_swman_registers },
{ UNSLICE, gen8_3_0_gx_clkctl_pll0_cm_pll_lucid_ole_registers },
{ UNSLICE, gen8_3_0_gx_clkctl_gx_clkctl_reg_registers },
{ UNSLICE, gen8_3_0_acd_acd_mnd_registers },
{ SLICE, gen8_3_0_gmugx_registers },
};
#endif /*_ADRENO_GEN8_3_0_SNAPSHOT_H */

14
adreno_gen8_gmu.c
View File

@ -686,6 +686,14 @@ bool gen8_gmu_gx_is_on(struct adreno_device *adreno_dev)
return is_on(val);
}
bool gen8_gmu_rpmh_pwr_state_is_active(struct kgsl_device *device)
{
u32 val;
gmu_core_regread(device, GEN8_GMUCX_RPMH_POWER_STATE, &val);
return (val == GPU_HW_ACTIVE) ? true : false;
}
static const char *idle_level_name(int level)
{
if (level == GPU_HW_ACTIVE)
@ -857,6 +865,9 @@ void gen8_gmu_register_config(struct adreno_device *adreno_dev)
/* Clear any previously set cm3 fault */
atomic_set(&gmu->cm3_fault, 0);
/* Init the power state register before GMU turns on GX */
gmu_core_regwrite(device, GEN8_GMUCX_RPMH_POWER_STATE, 0xF);
/* Vote veto for FAL10 */
gmu_core_regwrite(device, GEN8_GMUCX_CX_FALNEXT_INTF, 0x1);
gmu_core_regwrite(device, GEN8_GMUCX_CX_FAL_INTF, 0x1);
@ -1942,6 +1953,9 @@ static int gen8_gmu_boot(struct adreno_device *adreno_dev)
*/
gen8_enable_ahb_timeout_detection(adreno_dev);
/* Initialize the CX timer */
gen8_cx_timer_init(adreno_dev);
ret = gen8_rscc_wakeup_sequence(adreno_dev);
if (ret)
goto clks_gdsc_off;

9
adreno_gen8_gmu.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __ADRENO_GEN8_GMU_H
@ -495,4 +495,11 @@ size_t gen8_snapshot_gmu_mem(struct kgsl_device *device,
*/
u32 gen8_bus_ab_quantize(struct adreno_device *adreno_dev, u32 ab);
/**
* gen8_gmu_rpmh_pwr_state_is_active - Check the state of GPU HW
* @device: Pointer to the kgsl device
*
* Returns true on active or false otherwise
*/
bool gen8_gmu_rpmh_pwr_state_is_active(struct kgsl_device *device);
#endif

3
adreno_gen8_gmu_snapshot.c
View File

@ -264,7 +264,8 @@ static void gen8_gmu_device_snapshot(struct kgsl_device *device,
adreno_snapshot_registers_v2,
(void *) gen8_snapshot_block_list->gmu_cx_unsliced_regs);
if (!gen8_gmu_gx_is_on(adreno_dev))
if (!gen8_gmu_rpmh_pwr_state_is_active(device) ||
!gen8_gmu_gx_is_on(adreno_dev))
goto dtcm;
/* Set fence to ALLOW mode so registers can be read */

3
adreno_gen8_hwsched.c
View File

@ -562,6 +562,9 @@ static int gen8_hwsched_gmu_boot(struct adreno_device *adreno_dev)
*/
gen8_enable_ahb_timeout_detection(adreno_dev);
/* Initialize the CX timer */
gen8_cx_timer_init(adreno_dev);
ret = gen8_rscc_wakeup_sequence(adreno_dev);
if (ret)
goto clks_gdsc_off;

159
adreno_gen8_snapshot.c
View File

@ -187,6 +187,7 @@ size_t gen8_legacy_snapshot_registers(struct kgsl_device *device,
if (info->regs->sel)
kgsl_regwrite(device, info->regs->sel->host_reg, info->regs->sel->val);
if (info->regs->slice_region)
kgsl_regwrite(device, GEN8_CP_APERTURE_CNTL_HOST, GEN8_CP_APERTURE_REG_VAL
(info->slice_id, 0, 0, 0));
@ -598,8 +599,6 @@ static void gen8_snapshot_shader(struct kgsl_device *device,
size_t (*func)(struct kgsl_device *device, u8 *buf, size_t remain,
void *priv) = gen8_legacy_snapshot_shader;
kgsl_regrmw(device, GEN8_SP_DBG_CNTL, GENMASK(1, 0), 3);
if (CD_SCRIPT_CHECK(device)) {
for (i = 0; i < num_shader_blocks; i++) {
struct gen8_shader_block *block = &shader_blocks[i];
@ -623,7 +622,7 @@ static void gen8_snapshot_shader(struct kgsl_device *device,
}
}
goto done;
return;
}
for (i = 0; i < num_shader_blocks; i++) {
@ -674,9 +673,6 @@ static void gen8_snapshot_shader(struct kgsl_device *device,
}
}
}
done:
kgsl_regrmw(device, GEN8_SP_DBG_CNTL, GENMASK(1, 0), 0x0);
}
static void gen8_rmw_aperture(struct kgsl_device *device,
@ -720,6 +716,9 @@ static void gen8_snapshot_mempool(struct kgsl_device *device,
cp_indexed_reg->pipe_id, j, 1);
}
}
/* Clear aperture register */
gen8_host_aperture_set(ADRENO_DEVICE(device), 0, 0, 0);
}
static u32 gen8_read_dbgahb(struct kgsl_device *device,
@ -757,7 +756,7 @@ static size_t gen8_legacy_snapshot_cluster_dbgahb(struct kgsl_device *device,
header->slice_id = info->slice_id;
read_sel = GEN8_SP_READ_SEL_VAL(info->slice_id, info->location_id,
info->pipe_id, info->statetype_id, info->sp_id, info->usptp_id);
info->pipe_id, info->statetype_id, info->usptp_id, info->sp_id);
kgsl_regwrite(device, GEN8_SP_READ_SEL, read_sel);
@ -852,6 +851,7 @@ static void gen8_snapshot_dbgahb_regs(struct kgsl_device *device,
info.usptp_id = usptp;
info.sp_id = sp;
info.slice_id = SLICE_ID(cluster->slice_region, j);
info.statetype_id = cluster->statetype;
info.cluster_id = cluster->cluster_id;
info.context_id = cluster->context_id;
kgsl_snapshot_add_section(device,
@ -864,9 +864,6 @@ static void gen8_snapshot_dbgahb_regs(struct kgsl_device *device,
return;
}
/* Build the crash script */
ptr = gen8_capturescript->hostptr;
for (i = 0; i < num_sptp_clusters; i++) {
struct gen8_sptp_cluster_registers *cluster = &sptp_clusters[i];
@ -890,10 +887,13 @@ static void gen8_snapshot_dbgahb_regs(struct kgsl_device *device,
info.context_id = cluster->context_id;
info.offset = offset;
/* Build the crash script */
ptr = gen8_capturescript->hostptr;
/* Program the aperture */
ptr += CD_WRITE(ptr, GEN8_SP_READ_SEL, GEN8_SP_READ_SEL_VAL
(j, cluster->location_id, cluster->pipe_id,
cluster->statetype, sp, usptp));
cluster->statetype, usptp, sp));
for (; regs[0] != UINT_MAX; regs += 2) {
count = REG_COUNT(regs);
@ -1050,9 +1050,6 @@ static void gen8_snapshot_mvc_regs(struct kgsl_device *device,
return;
}
/* Build the crash script */
ptr = gen8_capturescript->hostptr;
for (i = 0; i < num_cluster; i++) {
struct gen8_cluster_registers *cluster = &clusters[i];
@ -1069,6 +1066,9 @@ static void gen8_snapshot_mvc_regs(struct kgsl_device *device,
info.slice_id = SLICE_ID(cluster->slice_region, j);
info.offset = offset;
/* Build the crash script */
ptr = gen8_capturescript->hostptr;
ptr += CD_WRITE(ptr, GEN8_CP_APERTURE_CNTL_CD, GEN8_CP_APERTURE_REG_VAL
(j, cluster->pipe_id, cluster->cluster_id, cluster->context_id));
@ -1295,6 +1295,61 @@ static size_t gen8_snapshot_cx_side_dbgc_debugbus_block(struct kgsl_device *devi
return size;
}
static void gen8_snapshot_cx_debugbus(struct adreno_device *adreno_dev,
struct kgsl_snapshot *snapshot)
{
u32 i;
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_CNTLT,
FIELD_PREP(GENMASK(31, 28), 0xf));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_CNTLM,
FIELD_PREP(GENMASK(27, 24), 0xf));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_0, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_1, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_2, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_3, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_BYTEL_0,
FIELD_PREP(GENMASK(3, 0), 0x0) |
FIELD_PREP(GENMASK(7, 4), 0x1) |
FIELD_PREP(GENMASK(11, 8), 0x2) |
FIELD_PREP(GENMASK(15, 12), 0x3) |
FIELD_PREP(GENMASK(19, 16), 0x4) |
FIELD_PREP(GENMASK(23, 20), 0x5) |
FIELD_PREP(GENMASK(27, 24), 0x6) |
FIELD_PREP(GENMASK(31, 28), 0x7));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_BYTEL_1,
FIELD_PREP(GENMASK(3, 0), 0x8) |
FIELD_PREP(GENMASK(7, 4), 0x9) |
FIELD_PREP(GENMASK(11, 8), 0xa) |
FIELD_PREP(GENMASK(15, 12), 0xb) |
FIELD_PREP(GENMASK(19, 16), 0xc) |
FIELD_PREP(GENMASK(23, 20), 0xd) |
FIELD_PREP(GENMASK(27, 24), 0xe) |
FIELD_PREP(GENMASK(31, 28), 0xf));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_MASKL_0, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_MASKL_1, 0);
/* Dump the CX debugbus data if the block exists */
if (!kgsl_regmap_valid_offset(&device->regmap, GEN8_CX_DBGC_CFG_DBGBUS_SEL_A))
return;
for (i = 0; i < gen8_snapshot_block_list->cx_debugbus_blocks_len; i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
snapshot, gen8_snapshot_cx_dbgc_debugbus_block,
(void *) &gen8_snapshot_block_list->cx_debugbus_blocks[i]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen8_snapshot_cx_side_dbgc_debugbus_block,
(void *) &gen8_snapshot_block_list->cx_debugbus_blocks[i]);
}
}
/* gen8_snapshot_debugbus() - Capture debug bus data */
static void gen8_snapshot_debugbus(struct adreno_device *adreno_dev,
struct kgsl_snapshot *snapshot)
@ -1337,41 +1392,6 @@ static void gen8_snapshot_debugbus(struct adreno_device *adreno_dev,
kgsl_regwrite(device, GEN8_DBGC_CFG_DBGBUS_MASKL_2, 0);
kgsl_regwrite(device, GEN8_DBGC_CFG_DBGBUS_MASKL_3, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_CNTLT,
FIELD_PREP(GENMASK(31, 28), 0xf));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_CNTLM,
FIELD_PREP(GENMASK(27, 24), 0xf));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_0, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_1, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_2, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_IVTL_3, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_BYTEL_0,
FIELD_PREP(GENMASK(3, 0), 0x0) |
FIELD_PREP(GENMASK(7, 4), 0x1) |
FIELD_PREP(GENMASK(11, 8), 0x2) |
FIELD_PREP(GENMASK(15, 12), 0x3) |
FIELD_PREP(GENMASK(19, 16), 0x4) |
FIELD_PREP(GENMASK(23, 20), 0x5) |
FIELD_PREP(GENMASK(27, 24), 0x6) |
FIELD_PREP(GENMASK(31, 28), 0x7));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_BYTEL_1,
FIELD_PREP(GENMASK(3, 0), 0x8) |
FIELD_PREP(GENMASK(7, 4), 0x9) |
FIELD_PREP(GENMASK(11, 8), 0xa) |
FIELD_PREP(GENMASK(15, 12), 0xb) |
FIELD_PREP(GENMASK(19, 16), 0xc) |
FIELD_PREP(GENMASK(23, 20), 0xd) |
FIELD_PREP(GENMASK(27, 24), 0xe) |
FIELD_PREP(GENMASK(31, 28), 0xf));
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_MASKL_0, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_MASKL_1, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_MASKL_2, 0);
kgsl_regwrite(device, GEN8_CX_DBGC_CFG_DBGBUS_MASKL_3, 0);
for (i = 0; i < gen8_snapshot_block_list->debugbus_blocks_len; i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
@ -1393,20 +1413,6 @@ static void gen8_snapshot_debugbus(struct adreno_device *adreno_dev,
snapshot, gen8_snapshot_dbgc_side_debugbus_block,
(void *) &gen8_snapshot_block_list->gbif_debugbus_blocks[i]);
}
/* Dump the CX debugbus data if the block exists */
if (kgsl_regmap_valid_offset(&device->regmap, GEN8_CX_DBGC_CFG_DBGBUS_SEL_A)) {
for (i = 0; i < gen8_snapshot_block_list->cx_debugbus_blocks_len; i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
snapshot, gen8_snapshot_cx_dbgc_debugbus_block,
(void *) &gen8_snapshot_block_list->cx_debugbus_blocks[i]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen8_snapshot_cx_side_dbgc_debugbus_block,
(void *) &gen8_snapshot_block_list->cx_debugbus_blocks[i]);
}
}
}
/* gen8_snapshot_sqe() - Dump SQE data in snapshot */
@ -1508,9 +1514,6 @@ static void gen8_reglist_snapshot(struct kgsl_device *device,
return;
}
/* Build the crash script */
ptr = (u64 *)gen8_capturescript->hostptr;
for (i = 0; reg_list[i].regs; i++) {
struct gen8_reg_list *regs = &reg_list[i];
@ -1520,6 +1523,9 @@ static void gen8_reglist_snapshot(struct kgsl_device *device,
for (j = 0; j < slices; j++) {
const u32 *regs_ptr = regs->regs;
/* Build the crash script */
ptr = gen8_capturescript->hostptr;
ptr += CD_WRITE(ptr, GEN8_CP_APERTURE_CNTL_CD, GEN8_CP_APERTURE_REG_VAL
(j, 0, 0, 0));
/* Program the SEL_CNTL_CD register appropriately */
@ -1588,7 +1594,8 @@ static void gen8_cx_misc_regs_snapshot(struct kgsl_device *device,
u64 *ptr, offset = 0;
const u32 *regs_ptr = (const u32 *)gen8_snapshot_block_list->cx_misc_regs;
if (CD_SCRIPT_CHECK(device) || !adreno_gx_is_on(ADRENO_DEVICE(device)))
if (CD_SCRIPT_CHECK(device) || !gen8_gmu_rpmh_pwr_state_is_active(device)
|| !gen8_gmu_gx_is_on(ADRENO_DEVICE(device)))
goto legacy_snapshot;
/* Build the crash script */
@ -1660,12 +1667,14 @@ void gen8_snapshot(struct adreno_device *adreno_dev,
if (!gmu_core_isenabled(device))
gen8_snapshot_external_core_regs(device, snapshot);
gen8_snapshot_trace_buffer(device, snapshot);
gen8_snapshot_debugbus(adreno_dev, snapshot);
gen8_cx_misc_regs_snapshot(device, snapshot);
gen8_snapshot_cx_debugbus(adreno_dev, snapshot);
if (!gen8_gmu_rpmh_pwr_state_is_active(device) ||
!gen8_gmu_gx_is_on(adreno_dev))
return;
/* SQE Firmware */
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
snapshot, gen8_snapshot_sqe, NULL);
@ -1674,8 +1683,9 @@ void gen8_snapshot(struct adreno_device *adreno_dev,
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
snapshot, gen8_snapshot_aqe, NULL);
if (!adreno_gx_is_on(adreno_dev))
return;
gen8_snapshot_trace_buffer(device, snapshot);
gen8_snapshot_debugbus(adreno_dev, snapshot);
is_current_rt = rt_task(current);
@ -1706,6 +1716,9 @@ void gen8_snapshot(struct adreno_device *adreno_dev,
&snapshot->ib2size_lpac, PIPE_LPAC, 0, 0);
}
/* Clear aperture register */
gen8_host_aperture_set(adreno_dev, 0, 0, 0);
/* Assert the isStatic bit before triggering snapshot */
kgsl_regwrite(device, GEN8_RBBM_SNAPSHOT_STATUS, 0x1);