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Add 'qcom/opensource/wlan/fw-api/' from commit '723e0826fb765910584c52099191c2d16b1ca7b6'

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git-subtree-dir: qcom/opensource/wlan/fw-api
git-subtree-mainline: f1b172d58b
git-subtree-split: 723e0826fb
Change-Id:
repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api
tag: LA.VENDOR.14.3.0.r1-17300-lanai.QSSI15.0
This commit is contained in:
David Wronek 2024-10-06 16:46:01 +02:00
commit c74a556fc1
3355 changed files with 2717897 additions and 0 deletions
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71
qcom/opensource/wlan/fw-api/fw/a_osapi.h Normal file
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/* ============================================================================== */
/* This file contains the definitions of the basic atheros data types. */
/* It is used to map the data types in atheros files to a platform specific */
/* type. */
/* */
/* Author(s): ="Atheros" */
/* ============================================================================== */
#ifndef _A_OSAPI_H_
#define _A_OSAPI_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "osapi_linux.h"
#endif
/*=== the following primitives have the same definition for all platforms ===*/
#define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \
typedef char assertion_name[(predicate) ? 1 : -1]
/*
* If N is a power of 2, then N and N-1 are orthogonal
* (N-1 has all the least-significant bits set which are zero in N)
* so N ^ (N-1) = (N << 1) - 1
*/
#define A_COMPILE_TIME_ASSERT_IS_PWR2(assertion_name, value) \
A_COMPILE_TIME_ASSERT (assertion_name, \
(((value) ^ ((value)-1)) == ((value) << 1) - 1))
#ifndef __ubicom32__
#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
os_malloc_CONSISTENT(osdev, size, pa, context, retry)
#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
OS_FREE_CONSISTENT(osdev, size, vaddr, pa, context)
#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context)
#else
#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
os_malloc_NONCONSISTENT(osdev, size, pa, context, retry)
#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
OS_FREE_NONCONSISTENT(osdev, size, vaddr, pa, context)
#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context) \
OS_SYNC_SINGLE(osdev, pa, size, dir, context)
#endif /* ubicom32 */
#endif /* _OSAPI_H_ */

108
qcom/opensource/wlan/fw-api/fw/a_usb_defs.h Normal file
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/*
* Copyright (c) 2012, 2018 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/* USB definitions shared between host and target */
#ifndef __A_USB_DEFS_H__
#define __A_USB_DEFS_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* USB endpoint definitions */
#ifdef PLATFORM_GENOA
#define USB_EP_ADDR_APP_CTRL_IN 0x88
#define USB_EP_ADDR_APP_DATA_IN 0x89
#define USB_EP_ADDR_APP_QMI_IN 0x8A
#define USB_EP_ADDR_APP_DIAG_IN 0x8B
#define USB_EP_ADDR_APP_CTRL_OUT 0x08
#define USB_EP_ADDR_APP_DATA_OUT 0x09
#define USB_EP_ADDR_APP_QMI_OUT 0x0A
#define USB_EP_ADDR_APP_DIAG_OUT 0x0B
#else /* PLATFORM_GENOA */
#define USB_EP_ADDR_APP_CTRL_IN 0x81
#define USB_EP_ADDR_APP_DATA_IN 0x82
#define USB_EP_ADDR_APP_DATA2_IN 0x83
#define USB_EP_ADDR_APP_INT_IN 0x84
#define USB_EP_ADDR_APP_CTRL_OUT 0x01
#define USB_EP_ADDR_APP_DATA_LP_OUT 0x02
#define USB_EP_ADDR_APP_DATA_MP_OUT 0x03
#define USB_EP_ADDR_APP_DATA_HP_OUT 0x04
#endif /* PLATFORM_GENOA */
#define USB_CONTROL_REQ_SEND_BMI_CMD 1
#define USB_CONTROL_REQ_RECV_BMI_RESP 2
#define USB_CONTROL_REQ_DIAG_CMD 3
#define USB_CONTROL_REQ_DIAG_RESP 4
//#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64
#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 252
#define HIF_BMI_MAX_TRANSFER_SIZE USB_CONTROL_MAX_BMI_TRANSFER_SIZE
#define USB_HS_BULK_MAXP_SIZE 0x200 //512 Bytes Maxp for High Speed for BULK EP
#define USB_FS_BULK_MAXP_SIZE 0x40 //64 Bytes Maxp for Full Speed for BULK EP
/* diagnostic command defnitions */
#define USB_CTRL_DIAG_CC_READ 0
#define USB_CTRL_DIAG_CC_WRITE 1
#define USB_CTRL_DIAG_CC_WARM_RESET 2
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
A_UINT32 Value;
A_UINT32 _pad[1];
} POSTPACK USB_CTRL_DIAG_CMD_WRITE;
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
} POSTPACK USB_CTRL_DIAG_CMD_READ;
typedef PREPACK struct {
A_UINT32 ReadValue;
} POSTPACK USB_CTRL_DIAG_RESP_READ;
#define USB_CTRL_MAX_DIAG_CMD_SIZE (sizeof(USB_CTRL_DIAG_CMD_WRITE))
#define USB_CTRL_MAX_DIAG_RESP_SIZE (sizeof(USB_CTRL_DIAG_RESP_READ))
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif

59
qcom/opensource/wlan/fw-api/fw/apb_athr_wlan_map.h Normal file
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _APB_ATHR_WLAN_MAP_H_
#define _APB_ATHR_WLAN_MAP_H_
#define RTC_SOC_BASE_ADDRESS 0x00004000
#define RTC_WMAC_BASE_ADDRESS 0x00005000
#define MAC_COEX_BASE_ADDRESS 0x00006000
#define BT_COEX_BASE_ADDRESS 0x00007000
#define SOC_PCIE_BASE_ADDRESS 0x00008000
#define SOC_CORE_BASE_ADDRESS 0x00009000
#define WLAN_UART_BASE_ADDRESS 0x0000c000
#define WLAN_SI_BASE_ADDRESS 0x00010000
#define WLAN_GPIO_BASE_ADDRESS 0x00014000
#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
#define WLAN_MAC_BASE_ADDRESS 0x00020000
#define EFUSE_BASE_ADDRESS 0x00030000
#define FPGA_REG_BASE_ADDRESS 0x00039000
#define WLAN_UART2_BASE_ADDRESS 0x00054c00
#define CE_WRAPPER_BASE_ADDRESS 0x00057000
#define CE0_BASE_ADDRESS 0x00057400
#define CE1_BASE_ADDRESS 0x00057800
#define CE2_BASE_ADDRESS 0x00057c00
#define CE3_BASE_ADDRESS 0x00058000
#define CE4_BASE_ADDRESS 0x00058400
#define CE5_BASE_ADDRESS 0x00058800
#define CE6_BASE_ADDRESS 0x00058c00
#define CE7_BASE_ADDRESS 0x00059000
#define DBI_BASE_ADDRESS 0x00060000
#define WLAN_MBOX_BASE_ADDRESS 0x00068000
#define WLAN_DBG_UART_BASE_ADDRESS 0x00069000
#define USB_DMA_BASE_ADDRESS 0x0006a000
#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */

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qcom/opensource/wlan/fw-api/fw/athdefs.h Normal file
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/*
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __ATHDEFS_H__
#define __ATHDEFS_H__
/*
* This file contains definitions that may be used across both
* Host and Target software. Nothing here is module-dependent
* or platform-dependent.
*/
/*
* Generic error codes that can be used by hw, sta, ap, sim, dk
* and any other environments. Since these are enums, feel free to
* add any more codes that you need.
*/
typedef enum {
A_ERROR = -1, /* Generic error return */
A_OK = 0, /* success */
/* Following values start at 1 */
A_DEVICE_NOT_FOUND, /* not able to find PCI device */
A_NO_MEMORY, /* not able to allocate memory, not available */
A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
A_NO_FREE_DESC, /* no free descriptors available */
A_BAD_ADDRESS, /* address does not match descriptor */
A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
A_REGS_NOT_MAPPED, /* registers not correctly mapped */
A_EPERM, /* Not superuser */
A_EACCES, /* Access denied */
A_ENOENT, /* No such entry, search failed, etc. */
A_EEXIST, /* The object already exists (can't create) */
A_EFAULT, /* Bad address fault */
A_EBUSY, /* Object is busy */
A_EINVAL, /* Invalid parameter */
A_EMSGSIZE, /* Inappropriate message buffer length */
A_ECANCELED, /* Operation canceled */
A_ENOTSUP, /* Operation not supported */
A_ECOMM, /* Communication error on send */
A_EPROTO, /* Protocol error */
A_ENODEV, /* No such device */
A_EDEVNOTUP, /* device is not UP */
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED, /* Object was consumed */
A_CLONE, /* The buffer is cloned */
} A_STATUS;
#define A_SUCCESS(x) (x == A_OK)
#define A_FAILED(x) (!A_SUCCESS(x))
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* __ATHDEFS_H__ */

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qcom/opensource/wlan/fw-api/fw/athendpack.h Normal file
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifdef VXWORKS
#endif /* VXWORKS */
#if defined(LINUX) || defined(__linux__)
#endif /* LINUX */
#ifdef QNX
#endif /* QNX */

43
qcom/opensource/wlan/fw-api/fw/bin_sig.h Normal file
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/*
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef BIN_SIGN_H_
#define BIN_SIGN_H_
/* Signed binary MetaData */
typedef struct {
unsigned int magic_num;
unsigned int total_len;
unsigned int rampatch_len;
unsigned int product_id;
unsigned int patch_ver;
unsigned short sign_format_ver;
unsigned short sign_algorithm;
unsigned char reserved[8];
} SIGN_HEADER_T;
#endif /* BIN_SIGN_H_ */

380
qcom/opensource/wlan/fw-api/fw/bmi_msg.h Normal file
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/*
* Copyright (c) 2012, 2018 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __BMI_MSG_H__
#define __BMI_MSG_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Bootloader Messaging Interface (BMI)
*
* BMI is a very simple messaging interface used during initialization
* to read memory, write memory, execute code, and to define an
* application entry PC.
*
* It is used to download an application to AR6K, to provide
* patches to code that is already resident on AR6K, and generally
* to examine and modify state. The Host has an opportunity to use
* BMI only once during bootup. Once the Host issues a BMI_DONE
* command, this opportunity ends.
*
* The Host writes BMI requests to mailbox0, and reads BMI responses
* from mailbox0. BMI requests all begin with a command
* (see below for specific commands), and are followed by
* command-specific data.
*
* Flow control:
* The Host can only issue a command once the Target gives it a
* "BMI Command Credit", using AR6K Counter #4. As soon as the
* Target has completed a command, it issues another BMI Command
* Credit (so the Host can issue the next command).
*
* BMI handles all required Target-side cache flushing.
*/
/* Maximum data size used for BMI transfers */
#define BMI_DATASZ_MAX 256
/* BMI Commands */
#define BMI_NO_COMMAND 0
#define BMI_DONE 1
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* Response format: none
*/
#define BMI_READ_MEMORY 2
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* Response format:
* A_UINT8 data[length]
*/
#define BMI_WRITE_MEMORY 3
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
/*
* Capbility to write "segmented files" is provided for two reasons
* 1) backwards compatibility for certain situations where Hosts
* have limited flexibility
* 2) because it's darn convenient.
*
* A segmented file consists of a file header followed by an arbitrary number
* of segments. Each segment contains segment metadata -- a Target address and
* a length -- followed by "length" bytes of data. A segmented file ends with
* a segment that specifies length=BMI_SGMTFILE_DONE. When a segmented file
* is sent to the Target, firmware writes each segment to the specified address.
*
* Special cases:
* 1) If a segment's metadata indicates length=BMI_SGMTFILE_EXEC, then the
* specified address is used as a function entry point for a brief function
* with prototype "(void *)(void)". That function is called immediately.
* After execution of the function completes, firmware continues with the
* next segment. No data is expected when length=BMI_SGMTFILE_EXEC.
*
* 2) If a segment's metadata indicates length=BMI_SGMTFILE_BEGINADDR, then
* the specified address is established as the application start address
* so that a subsequent BMI_DONE jumps there.
*
* 3) If a segment's metadata indicates length=BMI_SGMTFILE_BDDATA, then
* the specified address is used as the (possibly compressed) length of board
* data, which is loaded into the proper Target address as specified by
* hi_board_data. In addition, the hi_board_data_initialized flag is set.
*
* A segmented file is sent to the Target using a sequence of 1 or more
* BMI_WRITE_MEMORY commands. The first such command must have
* address=BMI_SEGMENTED_WRITE_ADDR. Subsequent BMI_WRITE_MEMORY commands
* can use an arbitrary address. In each BMI_WRITE_MEMORY command, the
* length specifies the number of data bytes transmitted (except for the
* special cases listed above).
*
* Alternatively, a segmented file may be sent to the Target using a
* BMI_LZ_STREAM_START command with address=BMI_SEGMENTED_WRITE_ADDR
* followed by a series of BMI_LZ_DATA commands that each send the next portion
* of the segmented file.
*
* The data segments may be lz77 compressed. In this case, the segmented file
* header flag, BMI_SGMTFILE_FLAG_COMPRESS, must be set. Note that segmented
* file METAdata is never compressed; only the data segments themselves are
* compressed. There is no way to mix compressed and uncompressed data segments
* in a single segmented file. Compressed (or uncompressed) segments are handled
* by both BMI_WRITE_MEMORY and by BMI_LZ_DATA commands. (Compression is an
* attribute of the segmented file rather than of the command used to transmit
* it.)
*/
#define BMI_SEGMENTED_WRITE_ADDR 0x1234
/* File header for a segmented file */
struct bmi_segmented_file_header {
A_UINT32 magic_num;
A_UINT32 file_flags;
};
#define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */
#define BMI_SGMTFILE_FLAG_COMPRESS 1
/* Metadata for a segmented file segment */
struct bmi_segmented_metadata {
A_UINT32 addr;
A_UINT32 length;
};
/* Special values for bmi_segmented_metadata.length (all have high bit set) */
#define BMI_SGMTFILE_DONE 0xffffffff /* end of segmented data */
#define BMI_SGMTFILE_BDDATA 0xfffffffe /* Board Data segment */
#define BMI_SGMTFILE_BEGINADDR 0xfffffffd /* set beginning address */
#define BMI_SGMTFILE_EXEC 0xfffffffc /* immediate function execution */
#define BMI_EXECUTE 4
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* Response format:
* A_UINT32 return value
*/
/*
* Note: In order to support the segmented file feature
* (see BMI_WRITE_MEMORY), when the address specified in a
* BMI_EXECUTE command matches (same physical address)
* BMI_SEGMENTED_WRITE_ADDR, it is ignored. Instead, execution
* begins at the address specified by hi_app_start.
*/
#define BMI_SET_APP_START 5
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* Response format: none
*/
#define BMI_READ_SOC_REGISTER 6
#define BMI_READ_SOC_WORD 6
/*
* Semantics: Read a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* Response format:
* A_UINT32 value
*/
#define BMI_WRITE_SOC_REGISTER 7
#define BMI_WRITE_SOC_WORD 7
/*
* Semantics: Write a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
*
* Response format: none
*/
#define BMI_GET_TARGET_ID 8
#define BMI_GET_TARGET_INFO 8
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
*
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
*
* Response format2 (intermediate firmware, during transition):
* A_UINT32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*
* Response format3 (newest firmware)
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
A_UINT32 target_info_byte_count; /* size of this structure */
A_UINT32 target_ver; /* Target Version ID */
A_UINT32 target_type; /* Target type */
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_UNKNOWN 0
#define TARGET_TYPE_AR6001 1
#define TARGET_TYPE_AR6002 2
#define TARGET_TYPE_AR6003 3
#define TARGET_TYPE_AR6004 5
#define TARGET_TYPE_AR6006 6
#define TARGET_TYPE_AR9888 7
#define TARGET_TYPE_AR6320 8
#define TARGET_TYPE_AR900B 9
/* For attach Peregrine 2.0 board target_reg_tbl only */
#define TARGET_TYPE_AR9888V2 10
/* For attach Rome1.0 target_reg_tbl only*/
#define TARGET_TYPE_AR6320V1 11
/* For Rome2.0/2.1 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V2 12
/* For Rome3.0 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V3 13
/* For Tufello1.0 target_reg_tbl ID*/
#define TARGET_TYPE_QCA9377V1 14
#define TARGET_TYPE_QCA9984 15 /* cascade */
#define TARGET_TYPE_IPQ4019 16 /* dakota */
#define TARGET_TYPE_QCA9888 17 /* besra */
#define BMI_ROMPATCH_INSTALL 9
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
*/
#define BMI_ROMPATCH_UNINSTALL 10
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
*
* Response format: none
*/
#define BMI_ROMPATCH_ACTIVATE 11
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_ROMPATCH_DEACTIVATE 12
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_LZ_STREAM_START 13
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
* be sufficiently large to hold the uncompressed
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_LZ_DATA 14
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* at most BMI_DATASZ_MAX
* A_UINT8 CompressedData[length]
* Response format: none
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_NVRAM_PROCESS 15
#define BMI_NVRAM_SEG_NAME_SZ 16
/*
* Semantics: Cause Target to search NVRAM (if any) for a
* segment with the specified name and process it according
* to NVRAM metadata.
* Request format:
* A_UINT32 command (BMI_NVRAM_PROCESS)
* A_UCHAR name[BMI_NVRAM_SEG_NAME_SZ] name (LE format)
* Response format:
* A_UINT32 0, if nothing was executed;
* otherwise the value returned from the
* last NVRAM segment that was executed
*/
#define BMI_SIGN_STREAM_START 17
/*
* Semantics: Trigger target start/end binary signature verification
* flow.
* Request format:
* A_UINT32 command (BMI_SIGN_STREAM_START)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
/* TBDXXX: Need a better place for these */
#define BMI_CE_NUM_TO_TARG 0
#define BMI_CE_NUM_TO_HOST 1
#endif /* __BMI_MSG_H__ */

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/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __CEPCI_H__
#define __CEPCI_H__
/*
* Support for Copy Engine over PCI.
* Structures shared between Host software and Target firmware.
*/
#include <a_types.h> /* A_UINT32 */
/*
* Total number of PCIe MSI interrupts requested for all interrupt sources.
* PCIe standard forces this to be a power of 2.
* Some Host OS's limit MSI requests that can be granted to 8
* so for now we abide by this limit and avoid requesting more
* than that.
*/
#define MSI_NUM_REQUEST_LOG2 3
#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
/*
* Granted MSIs are assigned as follows:
* Firmware uses the first
* Remaining MSIs, if any, are used by Copy Engines
* This mapping is known to both Target firmware and Host software.
* It may be changed as long as Host and Target are kept in sync.
*/
#define MSI_ASSIGN_FW 0 /* 1 MSI for firmware (errors, etc.) */
#define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */
#define MSI_ASSIGN_CE_MAX 7
/*
* PCI-specific Target state. Much of this may be of interest
* to the Host so HOST_INTEREST->hi_interconnect_state points
* here (and all members are 32-bit quantities in order to
* facilitate Host access). In particular, Host software is
* required to initialize pipe_cfg_addr and svc_to_pipe_map.
*/
struct pcie_state_s {
A_UINT32 pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
A_UINT32 svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
A_UINT32 MSI_requested; /* number of MSI interrupts requested */
A_UINT32 MSI_granted; /* number of MSI interrupts granted */
A_UINT32 MSI_addr; /* Message Signalled Interrupt address */
A_UINT32 MSI_data; /* Base data */
A_UINT32 MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
A_UINT32 power_mgmt_method; /* PCIE_PWR_METHOD_* */
A_UINT32 config_flags; /* PCIE_CONFIG_FLAG_* */
};
/*
* PCIE_CONFIG_FLAG definitions
*/
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
#define CE_PKTLOG_PIPE 8 /* used by both host and target side */
#define PCIE_CONFIG_FLAG_CLK_GATING_L1 0x0000001
#define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002
#define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004
#define PCIE_CONFIG_FLAG_CLK_REQ_L1 0x0000008
#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
/*
* Configuration information for a Copy Engine pipe.
* Passed from Host to Target during startup (one per CE).
*/
struct CE_pipe_config {
A_UINT32 pipenum;
A_UINT32 pipedir;
A_UINT32 nentries;
A_UINT32 nbytes_max;
A_UINT32 flags;
A_UINT32 reserved;
};
#endif /* __CEPCI_H__ */

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/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _DBGLOG_H_
#define _DBGLOG_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#include <a_types.h> /* A_UINT32 */
#include <a_osapi.h> /* PREPACK */
#include <wlan_module_ids.h>
#ifdef __cplusplus
extern "C" {
#endif
#define DBGLOG_TIMESTAMP_OFFSET 0
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF /* Bit 0-15. Contains bit
8-23 of the LF0 timer */
#define DBGLOG_DBGID_OFFSET 0
#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */
#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
#define DBGLOG_MODULEID_OFFSET 10
#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */
#define DBGLOG_MODULEID_NUM_MAX 32 /* Upper limit is width of mask */
#define DBGLOG_VDEVID_OFFSET 18
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25*/
#define DBGLOG_VDEVID_NUM_MAX 16
#define DBGLOG_NUM_ARGS_OFFSET 26
#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */
#define DBGLOG_NUM_ARGS_MAX 9 /* it is bcoz of limitation
of corebsp MSG*() to accept max 9 arg */
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE
#define DBGLOG_GET_DBGID(arg) \
((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
#define DBGLOG_GET_MODULEID(arg) \
((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
#define DBGLOG_GET_VDEVID(arg) \
((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
#define DBGLOG_GET_NUMARGS(arg) \
((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
#define DBGLOG_GET_TIME_STAMP(arg) \
((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
/* Debug Log levels*/
typedef enum {
DBGLOG_ML = 0,
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
DBGLOG_INFO_LVL_2,
DBGLOG_WARN,
DBGLOG_ERR,
DBGLOG_LVL_MAX,
DBGLOG_INVALID = 0xf
}DBGLOG_LOG_LVL;
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
} POSTPACK;
PREPACK struct dbglog_hdr_s {
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
} POSTPACK;
#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_H_ */

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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _EFUSE_REG_REG_H_
#define _EFUSE_REG_REG_H_
#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
#define EFUSE_WR_ENABLE_REG_V_MSB 0
#define EFUSE_WR_ENABLE_REG_V_LSB 0
#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
#define EFUSE_INT_ENABLE_REG_V_MSB 0
#define EFUSE_INT_ENABLE_REG_V_LSB 0
#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
#define EFUSE_INT_STATUS_REG_V_MSB 0
#define EFUSE_INT_STATUS_REG_V_LSB 0
#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
#define BITMASK_WR_REG_ADDRESS 0x0000000c
#define BITMASK_WR_REG_OFFSET 0x0000000c
#define BITMASK_WR_REG_V_MSB 31
#define BITMASK_WR_REG_V_LSB 0
#define BITMASK_WR_REG_V_MASK 0xffffffff
#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
#define VDDQ_SETTLE_TIME_REG_V_MSB 31
#define VDDQ_SETTLE_TIME_REG_V_LSB 0
#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
#define VDDQ_HOLD_TIME_REG_ADDRESS 0x00000014
#define VDDQ_HOLD_TIME_REG_OFFSET 0x00000014
#define VDDQ_HOLD_TIME_REG_V_MSB 31
#define VDDQ_HOLD_TIME_REG_V_LSB 0
#define VDDQ_HOLD_TIME_REG_V_MASK 0xffffffff
#define VDDQ_HOLD_TIME_REG_V_GET(x) (((x) & VDDQ_HOLD_TIME_REG_V_MASK) >> VDDQ_HOLD_TIME_REG_V_LSB)
#define VDDQ_HOLD_TIME_REG_V_SET(x) (((x) << VDDQ_HOLD_TIME_REG_V_LSB) & VDDQ_HOLD_TIME_REG_V_MASK)
#define RD_STROBE_PW_REG_ADDRESS 0x00000018
#define RD_STROBE_PW_REG_OFFSET 0x00000018
#define RD_STROBE_PW_REG_V_MSB 31
#define RD_STROBE_PW_REG_V_LSB 0
#define RD_STROBE_PW_REG_V_MASK 0xffffffff
#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
#define PG_STROBE_PW_REG_ADDRESS 0x0000001c
#define PG_STROBE_PW_REG_OFFSET 0x0000001c
#define PG_STROBE_PW_REG_V_MSB 31
#define PG_STROBE_PW_REG_V_LSB 0
#define PG_STROBE_PW_REG_V_MASK 0xffffffff
#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
#define PGENB_SETUP_HOLD_TIME_REG_ADDRESS 0x00000020
#define PGENB_SETUP_HOLD_TIME_REG_OFFSET 0x00000020
#define PGENB_SETUP_HOLD_TIME_REG_V_MSB 31
#define PGENB_SETUP_HOLD_TIME_REG_V_LSB 0
#define PGENB_SETUP_HOLD_TIME_REG_V_MASK 0xffffffff
#define PGENB_SETUP_HOLD_TIME_REG_V_GET(x) (((x) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) >> PGENB_SETUP_HOLD_TIME_REG_V_LSB)
#define PGENB_SETUP_HOLD_TIME_REG_V_SET(x) (((x) << PGENB_SETUP_HOLD_TIME_REG_V_LSB) & PGENB_SETUP_HOLD_TIME_REG_V_MASK)
#define STROBE_PULSE_INTERVAL_REG_ADDRESS 0x00000024
#define STROBE_PULSE_INTERVAL_REG_OFFSET 0x00000024
#define STROBE_PULSE_INTERVAL_REG_V_MSB 31
#define STROBE_PULSE_INTERVAL_REG_V_LSB 0
#define STROBE_PULSE_INTERVAL_REG_V_MASK 0xffffffff
#define STROBE_PULSE_INTERVAL_REG_V_GET(x) (((x) & STROBE_PULSE_INTERVAL_REG_V_MASK) >> STROBE_PULSE_INTERVAL_REG_V_LSB)
#define STROBE_PULSE_INTERVAL_REG_V_SET(x) (((x) << STROBE_PULSE_INTERVAL_REG_V_LSB) & STROBE_PULSE_INTERVAL_REG_V_MASK)
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_ADDRESS 0x00000028
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_OFFSET 0x00000028
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MSB 31
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB 0
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK 0xffffffff
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_GET(x) (((x) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) >> CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB)
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_SET(x) (((x) << CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK)
#define EFUSE_INTF0_ADDRESS 0x00000800
#define EFUSE_INTF0_OFFSET 0x00000800
#define EFUSE_INTF0_R_MSB 31
#define EFUSE_INTF0_R_LSB 0
#define EFUSE_INTF0_R_MASK 0xffffffff
#define EFUSE_INTF0_R_GET(x) (((x) & EFUSE_INTF0_R_MASK) >> EFUSE_INTF0_R_LSB)
#define EFUSE_INTF0_R_SET(x) (((x) << EFUSE_INTF0_R_LSB) & EFUSE_INTF0_R_MASK)
#define EFUSE_INTF1_ADDRESS 0x00001000
#define EFUSE_INTF1_OFFSET 0x00001000
#define EFUSE_INTF1_R_MSB 31
#define EFUSE_INTF1_R_LSB 0
#define EFUSE_INTF1_R_MASK 0xffffffff
#define EFUSE_INTF1_R_GET(x) (((x) & EFUSE_INTF1_R_MASK) >> EFUSE_INTF1_R_LSB)
#define EFUSE_INTF1_R_SET(x) (((x) << EFUSE_INTF1_R_LSB) & EFUSE_INTF1_R_MASK)
#ifndef __ASSEMBLER__
typedef struct efuse_reg_reg_s {
volatile unsigned int efuse_wr_enable_reg;
volatile unsigned int efuse_int_enable_reg;
volatile unsigned int efuse_int_status_reg;
volatile unsigned int bitmask_wr_reg;
volatile unsigned int vddq_settle_time_reg;
volatile unsigned int vddq_hold_time_reg;
volatile unsigned int rd_strobe_pw_reg;
volatile unsigned int pg_strobe_pw_reg;
volatile unsigned int pgenb_setup_hold_time_reg;
volatile unsigned int strobe_pulse_interval_reg;
volatile unsigned int csb_addr_load_setup_hold_reg;
unsigned char pad0[2004]; /* pad to 0x800 */
volatile unsigned int efuse_intf0[512];
volatile unsigned int efuse_intf1[512];
} efuse_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _EFUSE_REG_H_ */

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/*
* Copyright (c) 2012-2014, 2017, 2021 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _ENET__H_
#define _ENET__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
#define ETHERNET_ADDR_LEN 6 /* bytes */
#define ETHERNET_TYPE_LEN 2 /* bytes - length of the Ethernet type field */
struct ethernet_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 ethertype[ETHERNET_TYPE_LEN];
};
#define ETHERNET_HDR_LEN (sizeof(struct ethernet_hdr_t))
#define ETHERNET_CRC_LEN 4 /* bytes - length of the Ethernet CRC */
#define ETHERNET_MAX_LEN 1518 /* bytes */
#define ETHERNET_MTU (ETHERNET_MAX_LEN - (ETHERNET_HDR_LEN + ETHERNET_CRC_LEN))
typedef struct llc_snap_hdr_t {
A_UINT8 dsap;
A_UINT8 ssap;
A_UINT8 cntl;
A_UINT8 org_code[3];
A_UINT8 ethertype[2];
} LLC_SNAP_HDR;
#define LLC_SNAP_HDR_LEN (sizeof(struct llc_snap_hdr_t))
#define LLC_SNAP_HDR_OFFSET_ETHERTYPE \
(offsetof(struct llc_snap_hdr_t, ethertype[0]))
#define ETHERTYPE_VLAN_LEN 4
struct ethernet_vlan_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 vlan_tpid[2];
A_UINT8 vlan_tci[2];
A_UINT8 ethertype[2];
};
typedef PREPACK struct _wai_hdr {
A_UINT8 version[2];
A_UINT8 type;
A_UINT8 stype;
A_UINT8 reserve[2];
A_UINT8 length[2];
A_UINT8 rxseq[2];
A_UINT8 frag_sc;
A_UINT8 more_frag;
/* followed octets of data */
} POSTPACK wai_hdr;
typedef PREPACK struct {
A_UINT16 vlan_tci;
A_UINT16 vlan_encap_p;
} POSTPACK vlan_hdr_t;
#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
#ifndef ETHERTYPE_IPV4
#define ETHERTYPE_IPV4 0x0800 /* Internet Protocol, Version 4 (IPv4) */
#endif
#ifndef ETHERTYPE_AARP
#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */
#endif
#ifndef ETHERTYPE_IPX
#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */
#endif
#ifndef ETHERTYPE_ARP
#define ETHERTYPE_ARP 0x0806 /* Address Resolution Protocol (ARP) */
#endif
#ifndef ETHERTYPE_RARP
#define ETHERTYPE_RARP 0x8035 /* Reverse Address Resolution Protocol (RARP) */
#endif
#ifndef ETHERTYPE_VLAN
#define ETHERTYPE_VLAN 0x8100 /* VLAN TAG protocol */
#endif
#ifndef ETHERTYPE_SNMP
#define ETHERTYPE_SNMP 0x814C /* Simple Network Management Protocol (SNMP) */
#endif
#ifndef ETHERTYPE_IPV6
#define ETHERTYPE_IPV6 0x86DD /* Internet Protocol, Version 6 (IPv6) */
#endif
#ifndef ETHERTYPE_PAE
#define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */
#endif
#ifndef ETHERTYPE_WAI
#define ETHERTYPE_WAI 0x88B4 /* WAPI */
#endif
#ifndef ETHERTYPE_TDLS
#define ETHERTYPE_TDLS 0x890D /* TDLS */
#endif
#define LLC_SNAP_LSAP 0xaa
#define LLC_UI 0x3
#define RFC1042_SNAP_ORGCODE_0 0x00
#define RFC1042_SNAP_ORGCODE_1 0x00
#define RFC1042_SNAP_ORGCODE_2 0x00
#define BTEP_SNAP_ORGCODE_0 0x00
#define BTEP_SNAP_ORGCODE_1 0x00
#define BTEP_SNAP_ORGCODE_2 0xf8
#define WAI_FRAME_TYPE 0X01
#define WAPI_M4_TYPE 0x0c
#define WAPI_M2_TYPE 0x09
#define ICMP_PROTOCOL 1
#define TCP_PROTOCOL 6
#define UDP_PROTOCOL 17
#define IGMP_PROTOCOL 2
#define ICMPV6_PROTOCOL 58
#define BOOTP_SERVER_PORT 67
#define BOOTP_CLIENT_PORT 68
#define MLD_QUERY 130
#define MLD_DONE 132
#define IS_EAPOL(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
#define IS_SNAP(_llc) \
((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)
#define IS_RFC1042(_llc) \
((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
#define IS_BTEP(_llc) \
((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
#define IS_MULTICAST(_hdr) (*(A_UINT8 *)(_hdr) & 0x1)
#define IS_BROADCAST(_hdr) \
((*((A_UINT8 *)(_hdr) + 0) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 1) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 2) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 3) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 4) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 5) == 0xff))
#endif /* _ENET__H_ */

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/*
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/* This file contains shared definitions for the host/target endpoint ping test */
#ifndef EPPING_TEST_H_
#define EPPING_TEST_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* enable EPPING_TEST macro to enable endpoint ping */
//#define EPPING_TEST
extern unsigned int eppingtest;
extern unsigned int bypasswmi;
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
#endif
#define EPPING_RSVD_FILL 0xCC
#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
typedef PREPACK struct {
A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
A_UINT8 _pad[2]; /* padding for alignment */
A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
A_UINT16 Cmd_h; /* ping command (filled by host) */
A_UINT16 CmdFlags_h; /* optional flags */
A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
A_UINT16 DataLength; /* length of data */
A_UINT16 DataCRC; /* 16 bit CRC of data */
A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
} POSTPACK EPPING_HEADER;
#define EPPING_PING_MAGIC_0 0xAA
#define EPPING_PING_MAGIC_1 0x55
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */
#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
/* test command parameters may be no more than 8 bytes */
typedef PREPACK struct {
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
A_UINT16 Flags; /* flags */
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
#define EPPING_CONT_RX_NO_DATA_FILL (1 << 3) /* target will not fill buffers */
A_UINT16 Context; /* flags */
} POSTPACK EPPING_CONT_RX_PARAMS;
#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /*EPPING_TEST_H_*/

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/*
* Copyright (c) 2012, 2014-2016, 2018 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __HTC_H__
#define __HTC_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#ifdef ATHR_WIN_NWF
#pragma warning( disable:4214 ) //bit field types other than int
#endif
#undef MS
#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
#undef WO
#define WO(_f) ((_f##_OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f##_MASK) | SM(_val, _f))
#define HTC_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
#define HTC_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
#define HTC_WRITE32(_addr, _val) \
(*(A_UINT32 *)(_addr) = (_val))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#endif
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
/****** DANGER DANGER ***************
*
* The frame header length and message formats defined herein were
* selected to accommodate optimal alignment for target processing. This reduces code
* size and improves performance.
*
* Any changes to the header length may alter the alignment and cause exceptions
* on the target. When adding to the message structures insure that fields are
* properly aligned.
*
*/
/* HTC frame header */
typedef PREPACK struct _HTC_FRAME_HDR{
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT32 EndpointID : 8,
Flags : 8,
PayloadLen : 16; /* length of data (including trailer) that follows the header */
/***** end of 4-byte lookahead ****/
A_UINT32 ControlBytes0 : 8, /* used for CRC check if CRC_CHECK flag set */
ControlBytes1 : 8, /* used for seq check if SEQ_CHECK flag set */
reserved : 16; /* used by bundle processing in SDIO systems */
/* message payload starts after the header */
} POSTPACK HTC_FRAME_HDR;
#define HTC_FRAME_HDR_ENDPOINTID_LSB 0
#define HTC_FRAME_HDR_ENDPOINTID_MASK 0x000000ff
#define HTC_FRAME_HDR_ENDPOINTID_OFFSET 0x00000000
#define HTC_FRAME_HDR_FLAGS_LSB 8
#define HTC_FRAME_HDR_FLAGS_MASK 0x0000ff00
#define HTC_FRAME_HDR_FLAGS_OFFSET 0x00000000
#define HTC_FRAME_HDR_PAYLOADLEN_LSB 16
#define HTC_FRAME_HDR_PAYLOADLEN_MASK 0xffff0000
#define HTC_FRAME_HDR_PAYLOADLEN_OFFSET 0x00000000
#define HTC_FRAME_HDR_CONTROLBYTES0_LSB 0
#define HTC_FRAME_HDR_CONTROLBYTES0_MASK 0x000000ff
#define HTC_FRAME_HDR_CONTROLBYTES0_OFFSET 0x00000004
#define HTC_FRAME_HDR_CONTROLBYTES1_LSB 8
#define HTC_FRAME_HDR_CONTROLBYTES1_MASK 0x0000ff00
#define HTC_FRAME_HDR_CONTROLBYTES1_OFFSET 0x00000004
#define HTC_FRAME_HDR_RESERVED_LSB 16
#define HTC_FRAME_HDR_RESERVED_MASK 0xffff0000
#define HTC_FRAME_HDR_RESERVED_OFFSET 0x00000004
/* frame header flags */
/* send direction */
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
#define HTC_FLAGS_SEQ_CHECK (1 << 2) /* seq check on rx side */
#define HTC_FLAGS_CRC_CHECK (1 << 3) /* CRC check on rx side */
/* HTC_FLAGS_PADDING_CHECK
* Set by the sender to inform the receiver that the HTC packet begins
* with continuation (block) alignment padding from the prior HTC packet.
*/
#define HTC_FLAGS_PADDING_CHECK (1 << 4)
/* receive direction */
#define HTC_FLAGS_RECV_1MORE_BLOCK (1 << 0) /* bit 0 bundle trailer present */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xFC) /* bits 7..2 */
#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 2
/*
* To be compatible with an older definition of a smaller (4-bit)
* bundle count field, the bundle count is stored in a segmented
* format - the 4 LSbs of the bundle count value are stored in bits 5:2
* of the BUNDLE_CNT field, which is bits 7:4 of the HTC_FLAGS word;
* the next 2 bits of the bundle count value are stored in bits 1:0 of
* the BUNDLE_CNT field, which is bits 3:2 of the HTC_FLAGS word.
*/
#define HTC_FLAGS_RECV_BUNDLE_CNT_SET(x) \
((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT)
#define HTC_FLAGS_RECV_BUNDLE_CNT_GET(x) \
((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> (HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4))
#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
#define HTC_HDR_ALIGNMENT_PADDING \
(((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#define HTC_MAX_TRAILER_LENGTH 255
#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR))
/* HTC control message IDs */
#define HTC_MSG_READY_ID 1
#define HTC_MSG_CONNECT_SERVICE_ID 2
#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
#define HTC_MSG_SETUP_COMPLETE_ID 4
#define HTC_MSG_SETUP_COMPLETE_EX_ID 5
#define HTC_MSG_SEND_SUSPEND_COMPLETE 6
#define HTC_MSG_NACK_SUSPEND 7
#define HTC_MSG_WAKEUP_FROM_SUSPEND_ID 8
#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
/* base message ID header */
typedef PREPACK struct {
A_UINT32 MessageID: 16,
MetaData: 8,
reserved: 8;
} POSTPACK HTC_UNKNOWN_MSG;
#define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0
#define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_UNKNOWN_MSG_METADATA_LSB 16
#define HTC_UNKNOWN_MSG_METADATA_MASK 0X00ff0000
#define HTC_UNKNOWN_MSG_METADATA_OFFSET 0x00000000
/* HTC ready message
* direction : target-to-host */
typedef PREPACK struct {
A_UINT32 MessageID : 16, /* ID */
CreditCount: 16; /* number of credits the target can offer */
A_UINT32 CreditSize : 16, /* size of each credit */
MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */
_Pad1 : 8;
} POSTPACK HTC_READY_MSG;
#define HTC_READY_MSG_MESSAGEID_LSB 0
#define HTC_READY_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_READY_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_READY_MSG_CREDITCOUNT_LSB 16
#define HTC_READY_MSG_CREDITCOUNT_MASK 0xffff0000
#define HTC_READY_MSG_CREDITCOUNT_OFFSET 0x00000000
#define HTC_READY_MSG_CREDITSIZE_LSB 0
#define HTC_READY_MSG_CREDITSIZE_MASK 0x0000ffff
#define HTC_READY_MSG_CREDITSIZE_OFFSET 0x00000004
#define HTC_READY_MSG_MAXENDPOINTS_LSB 16
#define HTC_READY_MSG_MAXENDPOINTS_MASK 0x00ff0000
#define HTC_READY_MSG_MAXENDPOINTS_OFFSET 0x00000004
/* extended HTC ready message */
typedef PREPACK struct {
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT32 HTCVersion : 8,
MaxMsgsPerHTCBundle : 8, /* used in SDIO systems */
AltDataCreditSize : 12, /* used in HL (SDIO/USB) systems */
reserved : 4;
} POSTPACK HTC_READY_EX_MSG;
#define HTC_READY_EX_MSG_HTCVERSION_LSB 0
#define HTC_READY_EX_MSG_HTCVERSION_MASK 0x000000ff
#define HTC_READY_EX_MSG_HTCVERSION_OFFSET sizeof(HTC_READY_MSG)
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_LSB 8
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_MASK 0x0000ff00
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_OFFSET sizeof(HTC_READY_MSG)
#define HTC_VERSION_2P0 0x00
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
/* connect service
* direction : host-to-target */
typedef PREPACK struct {
A_UINT32 MessageID : 16,
ServiceID : 16; /* service ID of the service to connect to */
A_UINT32 ConnectionFlags : 16, /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
the host needs credits */
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
/* disable credit flow control on a specific service */
#define HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL (1 << 3)
/* enable htc schedule on a specific service */
#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE (1 << 4)
ServiceMetaLength : 8, /* length of meta data that follows */
LookAheadV2 : 1, /* 1 if host supports HTC_LOOKAHEAD_REPORT_V2 */
_Pad1 : 7;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_MSG;
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_LSB 0
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_LSB 16
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_LSB 0
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_LSB 16
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_MASK 0x00ff0000
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_OFFSET 0x00000004
#define HTC_SET_RECV_ALLOC_SHIFT 8
#define HTC_SET_RECV_ALLOC_MASK 0xFF00
#define HTC_CONNECT_FLAGS_SET_RECV_ALLOCATION(value) (((A_UINT8)value) << HTC_SET_RECV_ALLOC_SHIFT)
#define HTC_CONNECT_FLAGS_GET_RECV_ALLOCATION(value) (A_UINT8)(((value) & HTC_SET_RECV_ALLOC_MASK) >> HTC_SET_RECV_ALLOC_SHIFT)
/* connect response
* direction : target-to-host */
typedef PREPACK struct {
A_UINT32 MessageID : 16,
ServiceID : 16; /* service ID that the connection request was made */
A_UINT32 Status : 8, /* service connection status */
EndpointID : 8, /* assigned endpoint ID */
MaxMsgSize : 16; /* maximum expected message size on this endpoint */
A_UINT32 ServiceMetaLength : 8, /* length of meta data that follows */
LookAheadV2 : 1,/* 1 if target supports HTC_LOOKAHEAD_REPORT_V2 */
_Pad1 : 7,
reserved : 16;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_LSB 16
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_MASK 0x000000ff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_LSB 8
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_MASK 0x0000ff00
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_LSB 16
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_MASK 0x000000ff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 MessageID : 16,
reserved : 16;
/* currently, no other fields */
} POSTPACK HTC_SETUP_COMPLETE_MSG;
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_LSB 0
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_OFFSET 0x00000000
/* extended setup completion message */
typedef PREPACK struct {
A_UINT32 MessageID : 16,
reserved : 16;
A_UINT32 SetupFlags : 32;
A_UINT32 MaxMsgsPerBundledRecv : 8,
Rsvd0 : 8,
Rsvd1 : 8,
Rsvd2 : 8;
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_MASK 0xffffffff
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_OFFSET 0x00000004
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_MASK 0x000000ff
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_LSB 8
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_MASK 0x0000ff00
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_LSB 16
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_MASK 0x00ff0000
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_LSB 24
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_MASK 0xff000000
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) /* enable recv bundling from target */
#define HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW (1 << 1) /* disable credit based flow control,
only supported on some interconnects */
/* connect response status codes */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
/* report record IDs */
#define HTC_RECORD_NULL 0
#define HTC_RECORD_CREDITS 1
#define HTC_RECORD_LOOKAHEAD 2
#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
typedef PREPACK struct {
A_UINT32 RecordID : 8, /* Record ID */
Length : 8, /* Length of record */
reserved : 16;
} POSTPACK HTC_RECORD_HDR;
#define HTC_RECORD_HDR_RECORDID_LSB 0
#define HTC_RECORD_HDR_RECORDID_MASK 0x000000ff
#define HTC_RECORD_HDR_RECORDID_OFFSET 0x00000000
#define HTC_RECORD_HDR_LENGTH_LSB 8
#define HTC_RECORD_HDR_LENGTH_MASK 0x0000ff00
#define HTC_RECORD_HDR_LENGTH_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 EndpointID : 8, /* Endpoint that owns these credits */
Credits : 8, /* credits to report since last report */
reserved : 16;
} POSTPACK HTC_CREDIT_REPORT;
#define HTC_CREDIT_REPORT_ENDPOINTID_LSB 0
#define HTC_CREDIT_REPORT_ENDPOINTID_MASK 0x000000ff
#define HTC_CREDIT_REPORT_ENDPOINTID_OFFSET 0x00000000
#define HTC_CREDIT_REPORT_CREDITS_LSB 8
#define HTC_CREDIT_REPORT_CREDITS_MASK 0x0000ff00
#define HTC_CREDIT_REPORT_CREDITS_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 PreValid : 8, /* pre valid guard */
reserved0 : 24;
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8,
LookAhead2 : 8,
LookAhead3 : 8;
A_UINT32 PostValid : 8, /* post valid guard */
reserved1 : 24;
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
} POSTPACK HTC_LOOKAHEAD_REPORT;
/*
* If the host sets the HTC_CONNECT_SERVICE_MSG.LookAheadV2 flag and the
* target sets the HTC_CONNECT_SERVICE_RESPONSE_MSG.LookAheadV2 flag,
* HTC_LOOKAHEAD_REPORT_V2 is used; otherwise HTC_LOOKAHEAD_REPORT is used.
*/
typedef PREPACK struct {
A_UINT32 PreValid : 8, /* pre valid guard */
reserved0 : 24;
A_UINT32 LookAhead0 : 8, /* 8 byte lookahead */
LookAhead1 : 8,
LookAhead2 : 8,
LookAhead3 : 8;
A_UINT32 LookAhead4 : 8, /* 8 byte lookahead */
LookAhead5 : 8,
LookAhead6 : 8,
LookAhead7 : 8;
A_UINT32 PostValid : 8, /* post valid guard */
reserved1 : 24;
/* NOTE: the LookAhead array is guarded by PreValid and Post Valid
* guard bytes.
* The PreValid byte must equal the inverse of the PostValid byte.
*/
} POSTPACK HTC_LOOKAHEAD_REPORT_V2;
#define HTC_LOOKAHEAD_REPORT_PREVALID_LSB 0
#define HTC_LOOKAHEAD_REPORT_PREVALID_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_PREVALID_OFFSET 0x00000000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_POSTVALID_LSB 0
#define HTC_LOOKAHEAD_REPORT_POSTVALID_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_POSTVALID_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8,
LookAhead2 : 8,
LookAhead3 : 8;
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000000
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */

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/*
* Copyright (c) 2012, 2014-2017, 2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __HTC_SERVICES_H__
#define __HTC_SERVICES_H__
/* Current service IDs */
typedef enum {
RSVD_SERVICE_GROUP = 0,
WMI_SERVICE_GROUP = 1,
NMI_SERVICE_GROUP = 2,
HTT_SERVICE_GROUP = 3,
CFG_NV_SERVICE_GROUP = 4,
WDI_IPA_SERVICE_GROUP = 5,
PACKET_LOG_SERVICE_GROUP = 6,
LPASS_SERVICE_GROUP = 7,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
}HTC_SERVICE_GROUP_IDS;
#define MAKE_SERVICE_ID(group,index) \
(int)(((int)group << 8) | (int)(index))
/* NOTE: service ID of 0x0000 is reserved and should never be used */
#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
/* WMI_CONTROL_SVC: WMI service for MAC 0 */
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
/* WMI_CONTROL_SVC_WMAC1,2: WMI service for MACs 1 and 2 (where applicable) */
#define WMI_CONTROL_SVC_WMAC1 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,5)
#define WMI_CONTROL_SVC_WMAC2 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,6)
#define WMI_CONTROL_DIAG_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,7)
#define WMI_CONTROL_DBR_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,8)
/* WMI_CONTROL_SVC_WMAC3,4: WMI service for MACs 3 and 4 (where applicable) */
#define WMI_CONTROL_SVC_WMAC3 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,9)
#define WMI_CONTROL_SVC_WMAC4 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,10)
#define WMI_MAX_SERVICES 11
#define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
#define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
/* HTT_DATA_MSG_SVC
* This service is the regular (mandatory) HTT service
* used for transferring data-path messages betwween host and target.
*/
#define HTT_DATA_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,0)
/* HTT_DATA2_MSG_SVG
* This is an optional service, used for downloading short tx frames
* over a communication channel parallel to the regular HTT comm channel.
* This can only be used for protocols where frame reordering is permitted (TCP).
* This is helpful for minimizing latency and maximizing efficiency of TCP acks.
* This service is also for sending Rx In-order indication packets over copy engine 9 for
* for dual-band systems with multi-core hosts.
*/
#define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,1)
/* This service is only for sending Rx In-order indication packets over copy engine 10
* for dual-band systems with multi-core hosts, in which rx indications from one pdev/MAC
* can be routed to one host processor core in parallel with rx indications from another
* pdev/MAC being routed to another host core over another copy engine, such that these
* rx indications can be processed in parallel.
*/
#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,2)
/* raw stream service (i.e. flash, tcmd, calibration apps) */
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
#define CFG_NV_SVC MAKE_SERVICE_ID(CFG_NV_SERVICE_GROUP,0)
#define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP,0)
#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP,0)
#define LPASS_DATA_MSG_SVC MAKE_SERVICE_ID(LPASS_SERVICE_GROUP,0)
/*
* Directions for interconnect pipe configuration.
* These definitions may be used during configuration and are shared
* between Host and Target.
*
* Pipe Directions are relative to the Host, so PIPEDIR_IN means
* "coming IN over air through Target to Host" as with a WiFi Rx operation.
* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
* over the interconnect.
*/
typedef A_UINT32 PIPEDIR;
#define PIPEDIR_NONE 0
#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
#define PIPEDIR_INOUT 3 /* bidirectional, target to target */
#define PIPEDIR_INOUT_T2T PIPEDIR_INOUT
#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
#define PIPEDIR_MATCH(d1, d2) (((PIPEDIR)(d1) & (PIPEDIR)(d2)) != 0)
#define INVALID_PIPE_NO (-1)
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
A_UINT32 service_id;
A_UINT32 pipedir;
A_UINT32 pipenum;
};
#endif /*HTC_SERVICES_H_*/

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/*
* Copyright (c) 2012-2016, 2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/**
* @file htt_common.h
*
* @details the public header file of HTT layer shared between host and firmware
*/
#ifndef _HTT_COMMON_H_
#define _HTT_COMMON_H_
#include <htt_deps.h> /* A_UINT32 */
enum htt_sec_type {
htt_sec_type_none,
htt_sec_type_wep128,
htt_sec_type_wep104,
htt_sec_type_wep40,
htt_sec_type_tkip,
htt_sec_type_tkip_nomic,
htt_sec_type_aes_ccmp,
htt_sec_type_wapi,
htt_sec_type_aes_ccmp_256,
htt_sec_type_aes_gcmp,
htt_sec_type_aes_gcmp_256,
/* keep this last! */
htt_num_sec_types
};
enum htt_rx_ind_mpdu_status {
HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
HTT_RX_IND_MPDU_STATUS_OK,
HTT_RX_IND_MPDU_STATUS_ERR_FCS,
HTT_RX_IND_MPDU_STATUS_ERR_DUP,
HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscuous mode */
HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
/*
* MISC: discard for unspecified reasons.
* Leave this enum value last.
*/
HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
};
#define HTT_INVALID_PEER 0xffff
#define HTT_INVALID_VDEV 0xff
#define HTT_NON_QOS_TID 16
#define HTT_INVALID_TID 31
#define HTT_TX_EXT_TID_DEFAULT 0
#define HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST HTT_NON_QOS_TID
#define HTT_TX_EXT_TID_MGMT 17
#define HTT_TX_EXT_TID_INVALID HTT_INVALID_TID
#define HTT_TX_EXT_TID_NONPAUSE 19
#define HTT_TX_L3_CKSUM_OFFLOAD 1
#define HTT_TX_L4_CKSUM_OFFLOAD 2
/**
* @brief General specification of the tx frame contents
*
* @details
* For efficiency, the HTT packet type values correspond
* to the bit positions of the WAL packet type values, so the
* translation is a simple shift operation.
* The exception is the "mgmt" type, which specifies frame payload
* type rather than L2 header type.
*/
enum htt_pkt_type {
htt_pkt_type_raw = 0,
htt_pkt_type_native_wifi = 1,
htt_pkt_type_ethernet = 2,
htt_pkt_type_mgmt = 3,
htt_pkt_type_eth2 = 4,
/* keep this last */
htt_pkt_num_types
};
/*
* TX MSDU ID partition -
* FW supports bigger MSDU ID partition which is defined as
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* When both host and FW support new partition, FW uses
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* If host doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
* Handshaking is done through WMI_READY and WMI_INIT
*/
#define HTT_TX_HOST_MSDU_ID_SPACE_BEGIN 0
#define HTT_TX_IPA_MSDU_ID_SPACE_BEGIN 3000
#define TGT_RX2TX_MSDU_ID_SPACE_BEGIN 6000
#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192 /* = 0x2000 = b10,0000,0000,0000 */
#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288 /* = 0x3000 = b11,0000,0000,0000 */
/* HTT Access Category values */
enum HTT_AC_WMM {
/* WMM Access Categories */
HTT_AC_WMM_BE = 0x0,
HTT_AC_WMM_BK = 0x1,
HTT_AC_WMM_VI = 0x2,
HTT_AC_WMM_VO = 0x3,
HTT_NUM_AC_WMM = 0x4,
/* extension Access Categories */
HTT_AC_EXT_NON_QOS = 0x4,
HTT_AC_EXT_UCAST_MGMT = 0x5,
HTT_AC_EXT_MCAST_DATA = 0x6,
HTT_AC_EXT_MCAST_MGMT = 0x7,
};
enum HTT_AC_WMM_MASK {
/* WMM Access Categories */
HTT_AC_WMM_BE_MASK = (1 << HTT_AC_WMM_BE),
HTT_AC_WMM_BK_MASK = (1 << HTT_AC_WMM_BK),
HTT_AC_WMM_VI_MASK = (1 << HTT_AC_WMM_VI),
HTT_AC_WMM_VO_MASK = (1 << HTT_AC_WMM_VO),
/* extension Access Categories */
HTT_AC_EXT_NON_QOS_MASK = (1 << HTT_AC_EXT_NON_QOS),
HTT_AC_EXT_UCAST_MGMT_MASK = (1 << HTT_AC_EXT_UCAST_MGMT),
HTT_AC_EXT_MCAST_DATA_MASK = (1 << HTT_AC_EXT_MCAST_DATA),
HTT_AC_EXT_MCAST_MGMT_MASK = (1 << HTT_AC_EXT_MCAST_MGMT),
};
#define HTT_AC_MASK_WMM \
(HTT_AC_WMM_BE_MASK | HTT_AC_WMM_BK_MASK | \
HTT_AC_WMM_VI_MASK | HTT_AC_WMM_VO_MASK)
#define HTT_AC_MASK_EXT \
(HTT_AC_EXT_NON_QOS_MASK | HTT_AC_EXT_UCAST_MGMT_MASK | \
HTT_AC_EXT_MCAST_DATA_MASK | HTT_AC_EXT_MCAST_MGMT_MASK)
#define HTT_AC_MASK_ALL (HTT_AC_MASK_WMM | HTT_AC_MASK_EXT)
/** 2 word representation of MAC addr */
typedef struct {
/** upper 4 bytes of MAC address */
A_UINT32 mac_addr31to0;
/** lower 2 bytes of MAC address */
A_UINT32 mac_addr47to32;
} htt_mac_addr;
#define HTT_STATS_MAX_CHAINS 8
#endif /* _HTT_COMMON_H_ */

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/*
* Copyright (c) 2011-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/**
* @file htt_deps.h
*
* @details list other header files that contain the defs for data types,
* constants, and compiler pragmas used in the HTT header files
*/
#ifndef _HTT_DEPS_H_
#define _HTT_DEPS_H_
#include <a_types.h> /* A_UINT32 */
#ifndef QCA_WIFI_WIFISTATS_EXTBUILD
#include <a_osapi.h> /* PREPACK, POSTPACK */
#endif
#ifdef ATHR_WIN_NWF
#pragma warning(disable:4214) /* bit field types other than int */
#endif
#include "wlan_defs.h"
#endif /* _HTT_DEPS_H_ */

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/*
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _IP_PROT__H_
#define _IP_PROT__H_
#define IP_PROTOCOL_ICMP 0x01 /* Internet Control Message Protocol */
#define IP_PROTOCOL_IGMP 0x02 /* Internet Group Management Protocol */
#define IP_PROTOCOL_IPV4 0x04 /* IPv4 (encapsulation) */
#define IP_PROTOCOL_TCP 0x06 /* Transmission Control Protocol */
#define IP_PROTOCOL_UDP 0x11 /* User Datagram Protocol */
#define IP_PROTOCOL_RDP 0x1B /* Reliable Datagram Protocol */
#define IP_PROTOCOL_IPV6 0x29 /* IPv6 (encapsulation) */
#define IP_PROTOCOL_IPV6_ROUTE 0x2B /* Routing Header for IPv6 */
#define IP_PROTOCOL_IPV6_FRAG 0x2C /* Fragment Header for IPv6 */
#define IP_PROTOCOL_RSVP 0x2E /* Resource Reservation Protocol */
#define IP_PROTOCOL_GRE 0x2F /* Generic Routing Encapsulation */
#define IP_PROTOCOL_MHRP 0x30 /* Mobile Host Routing Protocol */
#define IP_PROTOCOL_BNA 0x31 /* BNA */
#define IP_PROTOCOL_ESP 0x32 /* Encapsulating Security Payload */
#define IP_PROTOCOL_MOBILE 0x37 /* IP Mobility (Min Encap) */
#define IP_PROTOCOL_IPV6_ICMP 0x3A /* ICMP for IPv6 */
#define IP_PROTOCOL_IPV6_NONXT 0x3B /* No Next Header for IPv6 */
#define IP_PROTOCOL_IPV6_OPTS 0x3C /* Destination Options for IPv6 */
#define IP_PROTOCOL_IPCOMP 0x6C /* IP Payload Compression Protocol */
#define IP_PROTOCOL_L2TP 0x73 /* Layer Two Tunneling Protocol Version 3 */
#define IP_PROTOCOL_SMP 0x79 /* Simple Message Protocol */
#define IP_PROTOCOL_SCTP 0x84 /* Stream Control Transmission Protocol */
#define IP_PROTOCOL_SHIM6 0x8C /* Site Multihoming by IPv6 Intermediation */
/* IPv6 ICMP types */
#define IPV6_ICMP_TYPE_MLD 0x8F
#endif /* _IP_PROT__H_ */

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/*
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _IPV4__H_
#define _IPV4__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
#define IPV4_ADDR_LEN 4 /* bytes */
struct ipv4_hdr_t {
A_UINT8 ver_hdrlen; /* version and hdr length */
A_UINT8 tos; /* type of service */
A_UINT8 len[2]; /* total length */
A_UINT8 id[2];
A_UINT8 flags_fragoff[2]; /* flags and fragment offset field */
A_UINT8 ttl; /* time to live */
A_UINT8 protocol;
A_UINT8 hdr_checksum[2];
A_UINT8 src_addr[IPV4_ADDR_LEN];
A_UINT8 dst_addr[IPV4_ADDR_LEN];
};
#define IPV4_HDR_LEN (sizeof(struct ipv4_hdr_t))
#define IPV4_HDR_OFFSET_PROTOCOL (offsetof(struct ipv4_hdr_t, protocol))
#define IPV4_HDR_OFFSET_DST_ADDR (offsetof(struct ipv4_hdr_t, dst_addr[0]))
#endif /* _IPV4__H_ */

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/*
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/**
* @file ol_fw_tx_dbg.h
*
* @details data structs used for uploading summary info about the FW's tx
*/
#ifndef _OL_FW_TX_DBG__H_
#define _OL_FW_TX_DBG__H_
/*
* Undef ATH_SUPPORT_FW_TX_DBG to remove the FW tx debug feature.
* Removing the FW tx debug feature saves a modest amount of program memory.
* The data memory allocation for the FW tx debug feature is controlled
* by the host --> target resource configuration parameters; even if
* ATH_SUPPORT_FW_TX_DBG is defined, no data memory will be allocated for
* the FW tx debug log unless the host --> target resource configuration
* specifies it.
*/
#define ATH_SUPPORT_FW_TX_DBG 1 /* enabled */
//#undef ATH_SUPPORT_FW_TX_DBG /* disabled */
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#include <a_osapi.h> /* PREPACK, POSTPACK */
#endif
enum ol_fw_tx_dbg_log_mode {
ol_fw_tx_dbg_log_mode_wraparound, /* overwrite old data with new */
ol_fw_tx_dbg_log_mode_single, /* fill log once, then stop */
};
/*
* tx PPDU stats upload message header
*/
struct ol_fw_tx_dbg_ppdu_msg_hdr {
/* word 0 */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff
A_UINT8 mpdu_bytes_array_len; /* length of array of per-MPDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00
A_UINT8 msdu_bytes_array_len; /* length of array of per-MSDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000
A_UINT8 mpdu_msdus_array_len; /* length of array of per-MPDU MSDU counts */
A_UINT8 reserved;
/* word 1 */
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff
A_UINT32 microsec_per_tick; /* conversion for timestamp entries */
};
/*
* tx PPDU log element / stats upload message element
*/
struct ol_fw_tx_dbg_ppdu_base {
/* word 0 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff
A_UINT16 start_seq_num;
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000
A_UINT16 start_pn_lsbs;
/* word 1 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff
A_UINT32 num_bytes;
/* word 2 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff
A_UINT8 num_msdus;
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00
A_UINT8 num_mpdus;
A_UINT16
#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2
#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16
#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000
ext_tid : 5,
#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2
#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21
#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000
peer_id : 11;
/* word 3 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff
A_UINT32 timestamp_enqueue;
/* word 4 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff
A_UINT32 timestamp_completion;
/* word 5 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_lsbs;
/* word 6 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_msbs;
/* word 7 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_lsbs;
/* word 8 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_msbs;
/* word 9 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0
#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff
A_UINT8 rate_code;
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00
A_UINT8 rate_flags; /* includes dynamic bandwidth info */
#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9
#define OL_FW_TX_DBG_PPDU_TRIES_S 16
#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000
A_UINT8 tries;
#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9
#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24
#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000
A_UINT8 complete;
};
#endif /* _OL_FW_TX_DBG__H_ */

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/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __TARGADDRS_H__
#define __TARGADDRS_H__
#if defined(ATH_TARGET)
#include "soc_addrs.h"
#endif
#if !defined(ATH_TARGET)
#include "athstartpack.h"
#endif
/*
* SOC option bits, to enable/disable various features.
* By default, all option bits are 0.
* AR6004: These bits can be set in LOCAL_SCRATCH register 0.
* AR9888: These bits can be set in soc_core register SCRATCH_0.
*/
#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
/*
* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
* host_interest structure. It must match the address of the _host_interest
* symbol (see linker script).
*
* Host Interest is shared between Host and Target in order to coordinate
* between the two, and is intended to remain constant (with additions only
* at the end) across software releases.
*
* All addresses are available here so that it's possible to
* write a single binary that works with all Target Types.
* May be used in assembler code as well as C.
*/
#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
#define AR6003_HOST_INTEREST_ADDRESS 0x00540600
#define AR6004_HOST_INTEREST_ADDRESS 0x00400800
#define AR9888_HOST_INTEREST_ADDRESS 0x00400800
#define AR900B_HOST_INTEREST_ADDRESS 0x00400800
#define AR6320_HOST_INTEREST_ADDRESS 0x00400800
#define QCA9377_HOST_INTEREST_ADDRESS 0x00400800
#define AR6004_SOC_RESET_ADDRESS 0X00004000
#define AR6004_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
#if defined(AR6006_MEMORY_NEW_ARCH)
#define AR6006_HOST_INTEREST_ADDRESS 0x00428800
#else
#define AR6006_HOST_INTEREST_ADDRESS 0x00400800
#endif
#define AR6006_SOC_RESET_ADDRESS 0X00004000
#define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
#define QCA9984_HOST_INTEREST_ADDRESS 0x00400800
#define IPQ4019_HOST_INTEREST_ADDRESS 0x00400800
#define QCA9888_HOST_INTEREST_ADDRESS 0x00400800
#define HOST_INTEREST_MAX_SIZE 0x200
#if !defined(__ASSEMBLER__)
struct register_dump_s;
struct dbglog_hdr_s;
/*
* These are items that the Host may need to access
* via BMI or via the Diagnostic Window. The position
* of items in this structure must remain constant
* across firmware revisions!
*
* Types for each item must be fixed size across
* target and host platforms.
*
* More items may be added at the end.
*/
PREPACK64 struct host_interest_s {
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Save SW ROM version */
A_UINT32 hi_sw_rom_version; /* 0x0c */
/*
* General-purpose flag bits, similar to SOC_OPTION_* flags.
* Can be used by application rather than by OS.
*/
volatile A_UINT32 hi_option_flag; /* 0x10 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/* Start address of DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/* Host uses BE CPU or not */
A_UINT32 hi_be; /* 0x44 */
A_UINT32 hi_stack; /* normal stack */ /* 0x48 */
A_UINT32 hi_err_stack; /* error stack */ /* 0x4c */
A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
/*
* Indication of Board Data state:
* 0: board data is not yet initialized.
* 1: board data is initialized; unknown size
* >1: number of bytes of initialized board data (varies with board type)
*/
A_UINT32 hi_board_data_initialized; /* 0x58 */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
A_UINT32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
A_UINT32 hi_reset_flag_valid; /* 0xb8 */
A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
A_UINT32 hi_acs_flags; /* 0xc0 */
A_UINT32 hi_console_flags; /* 0xc4 */
A_UINT32 hi_nvram_state; /* 0xc8 */
volatile A_UINT32 hi_option_flag2; /* 0xcc */
/* If non-zero, override values sent to Host in WMI_READY event. */
A_UINT32 hi_sw_version_override; /* 0xd0 */
A_UINT32 hi_abi_version_override; /* 0xd4 */
/* Percentage of high priority RX traffic to total expected RX traffic -
* applicable only to ar6004 */
A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* test applications flags */
A_UINT32 hi_test_apps_related ; /* 0xdc */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
A_UINT32 hi_cal_data; /* 0xe4 */
/* Number of packet log buffers */
volatile A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */
/* wow extension configuration */
A_UINT32 hi_wow_ext_config; /* 0xec */
A_UINT32 hi_pwr_save_flags; /* 0xf0 */
/* Spatial Multiplexing Power Save (SMPS) options */
A_UINT32 hi_smps_options; /* 0xf4 */
/* Interconnect-specific state */
A_UINT32 hi_interconnect_state; /* 0xf8 */
/* Coex configuration flags */
A_UINT32 hi_coex_config; /* 0xfc */
/* Early allocation support */
A_UINT32 hi_early_alloc; /* 0x100 */
/* FW swap field */
/* Bits of this 32bit word will be used to pass specific swap
instruction to FW */
/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
FW will not swap TX descriptor. Meaning packets are formed
on the target processor.*/
/* Bit 1 -- TBD */
A_UINT32 hi_fw_swap; /* 0x104 */
/* global arenas pointer address, used by host driver debug */
A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */
/* allocated bytes of DRAM use by allocated */
A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */
/* remaining bytes of DRAM */
A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */
/* memory track count, configured by host */
A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */
/* minidump buffer */
A_UINT32 hi_minidump; /* 0x118 */
/* bdata's sig and key addr */
A_UINT32 hi_bd_sig_key; /* 0x11c */
} POSTPACK64;
/* bitmap for hi_test_apps_related */
#define HI_TEST_APPS_TESTSCRIPT_LOADED 0x00000001
#define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_NUM_DEV_LSB 0x200
#define HI_OPTION_NUM_DEV_MSB 0x800
#define HI_OPTION_DEV_MODE_LSB 0x1000
#define HI_OPTION_DEV_MODE_MSB 0x8000000
#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before
* sending WMI ready event to host */
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */
#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
/* 2 bits of hi_option flag are usedto represent 4 submodes */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
/* Num dev Mask */
#define HI_OPTION_NUM_DEV_MASK 0x7
#define HI_OPTION_NUM_DEV_SHIFT 0x9
/* firmware bridging */
#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
/* Fw Mode/SubMode Mask
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|-------------------------------------------------------------------------------|
*/
#define HI_OPTION_FW_MODE_BITS 0x2
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0xC
#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
#define HI_OPTION_FW_SUBMODE_BITS 0x2
#define HI_OPTION_FW_SUBMODE_MASK 0x3
#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
/* hi_option_flag2 options */
#define HI_OPTION_OFFLOAD_AMSDU 0x01
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/
#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
#define HI_OPTION_RF_KILL_SHIFT 0x2
#define HI_OPTION_RF_KILL_MASK 0x1
#define HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX 0x20
#define HTT_TGT_DEBUG_TX_COMPL_IDX_VALUE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
/* AR9888 1.0 only. Enable/disable CDC max perf support from host */
#define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20
#define CDC_MAX_PERF_WAR_ENABLED() \
(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
#define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU. */
#define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/
#define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */
/*
* If both SDIO_CRASH_DUMP_ENHANCEMENT_HOST and SDIO_CRASH_DUMP_ENHANCEMENT_FW
* flags are set, then crashdump upload will be done using the BMI host/target
* communication channel.
*/
#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST 0x400 /* HOST to support using BMI dump FW memory when hit assert */
#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW 0x800 /* FW to support using BMI dump FW memory when hit assert */
/* USB_RESET_RESUME
* The host will set this flag, based on platform configuration specs.
* The target will check this flag at the time USB becomes suspended.
* If the flag is set, the target will invoke its reset / resume code.
* If the flag is not set, the target will do nothing, other than wait.
*/
#define HI_OPTION_USB_RESET_RESUME 0x1000
#define USB_RESET_RESUME() \
(HOST_INTEREST->hi_option_flag2 & HI_OPTION_USB_RESET_RESUME)
#define GPIO_WAKEUP_ENABLED() \
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
/* hi_reset_flag */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
#define HI_RESET_FLAG_WARM_RESET 0x20
/* define hi_fw_swap bits */
#define HI_DESC_IN_FW_BIT 0x01
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
#define ON_RESET_FLAGS_VALID() \
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_INVALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = 0)
#define ON_RESET_PRESERVE_APP_START() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_HOST_INTEREST() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
#define ON_RESET_PRESERVE_ROMDATA() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
#define ON_RESET_PRESERVE_BOOT_INFO() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
#define ON_RESET_WARM_RESET() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
/* host CPU endianness */
#define HOST_ON_BE_CPU() \
(HOST_INTEREST->hi_be)
/* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */
#define DESC_IN_FW() \
(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
/* redefine for hi_acs_flags since no product ever use it
* NOTE:
* This flag was only used in AR6004 for a customer project that has
* been canceled, we are reusing it to avoid extending the Host interest
* area.
* BIT Range Meaning
* --------- ----------------------------------
* 0 HOST wants to swap MBOX usage
* 1 HOST supports HTT reduced tx completion
* 2 HOST supports HTT alternate credit size for data frames
* 15..3 reserved for HOST
* 16 FW set it before sending HTC_Ready to HOST to indicate MBOX swap is done
* 17 same as above but to indicate HTT reduced tx completion capability
* 31..18 reserved for FW
*/
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0) /* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) /* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) /* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16) /* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17) /* FW support HTT reduced tx completion */
/* CONSOLE FLAGS
*
* Bit Range Meaning
* --------- --------------------------------
* 2..0 UART ID (0 = Default)
* 3 Baud Select (0 = 9600, 1 = 115200)
* 30..4 Reserved
* 31 Enable Console
*
* */
#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
#define HI_CONSOLE_FLAGS_UART_SHIFT 0
#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
/* SM power save options */
#define HI_SMPS_ALLOW_MASK (0x00000001)
#define HI_SMPS_MODE_MASK (0x00000002)
#define HI_SMPS_MODE_STATIC (0x00000000)
#define HI_SMPS_MODE_DYNAMIC (0x00000002)
#define HI_SMPS_DISABLE_AUTO_MODE (0x00000004)
#define HI_SMPS_DATA_THRESH_MASK (0x000007f8)
#define HI_SMPS_DATA_THRESH_SHIFT (3)
#define HI_SMPS_RSSI_THRESH_MASK (0x0007f800)
#define HI_SMPS_RSSI_THRESH_SHIFT (11)
#define HI_SMPS_LOWPWR_CM_MASK (0x00380000)
#define HI_SMPS_LOWPWR_CM_SHIFT (15)
#define HI_SMPS_HIPWR_CM_MASK (0x03c00000)
#define HI_SMPS_HIPWR_CM_SHIFT (19)
#define HOST_INTEREST_SMPS_GET_MODE() (HOST_INTEREST->hi_smps_options & HI_SMPS_MODE_MASK)
#define HOST_INTEREST_SMPS_GET_DATA_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_DATA_THRESH_MASK) >> HI_SMPS_DATA_THRESH_SHIFT)
#define HOST_INTEREST_SMPS_SET_DATA_THRESH(x) (((x) << HI_SMPS_DATA_THRESH_SHIFT) & HI_SMPS_DATA_THRESH_MASK)
#define HOST_INTEREST_SMPS_GET_RSSI_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_RSSI_THRESH_MASK) >> HI_SMPS_RSSI_THRESH_SHIFT)
#define HOST_INTEREST_SMPS_SET_RSSI_THRESH(x) (((x) << HI_SMPS_RSSI_THRESH_SHIFT) & HI_SMPS_RSSI_THRESH_MASK)
#define HOST_INTEREST_SMPS_SET_LOWPWR_CM() ((HOST_INTEREST->hi_smps_options & HI_SMPS_LOWPWR_CM_MASK) >> HI_SMPS_LOWPWR_CM_SHIFT)
#define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT)
#define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE)
/* WOW Extension configuration
*
* Bit Range Meaning
* --------- --------------------------------
* 8..0 Size of each WOW pattern (max 511)
* 15..9 Number of patterns per list (max 127)
* 17..16 Number of lists (max 4)
* 30..18 Reserved
* 31 Enabled
*
* set values (except enable) to zeros for default settings
*
* */
#define HI_WOW_EXT_ENABLED_MASK (1 << 31)
#define HI_WOW_EXT_NUM_LIST_SHIFT 16
#define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT)
#define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9
#define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT)
#define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0
#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
#define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \
((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \
(((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \
(((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
#define HI_WOW_EXT_GET_NUM_LISTS(config) \
(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
/*
* Early allocation configuration
* Support RAM bank configuration before BMI done and this eases the memory
* allocation at very early stage
* Bit Range Meaning
* --------- ----------------------------------
* [0:3] number of bank assigned to be IRAM
* [4:15] reserved
* [16:31] magic number
*
* Note:
* 1. target firmware would check magic number and if it's a match, firmware
* would consider the bits[0:15] are valid and base on that to calculate
* the end of DRAM. Early allocation would be located at that area and
* may be reclaimed when necesary
* 2. if no magic number is found, early allocation would happen at "_end"
* symbol of ROM which is located before the app-data and might NOT be
* re-claimable. If this is adopted, link script should keep this in
* mind to avoid data corruption.
*/
#define HI_EARLY_ALLOC_MAGIC 0x6d8a
#define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000
#define HI_EARLY_ALLOC_MAGIC_SHIFT 16
#define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f
#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
#define HI_EARLY_ALLOC_VALID() \
((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
== (HI_EARLY_ALLOC_MAGIC))
#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
/*
* Intended for use by Host software, this macro returns the Target RAM
* address of any item in the host_interest structure.
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
*/
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
((HOST_INTEREST->hi_pktlog_num_buffers))
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
#define LF_TIMER_STABILIZATION_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
#define IS_AMSDU_OFFLAOD_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
#define HOST_INTEREST_DFS_IS_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
#define HOST_INTEREST_EARLY_CFG_DONE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
/*power save flag bit definitions*/
#define HI_PWR_SAVE_LPL_ENABLED 0x1
/*b1-b3 reserved*/
/*b4-b5 : dev0 LPL type : 0 - none
1- Reduce Pwr Search
2- Reduce Pwr Listen*/
/*b6-b7 : dev1 LPL type and so on for Max 8 devices*/
#define HI_PWR_SAVE_LPL_DEV0_LSB 4
#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
/*power save related utility macros*/
#define HI_LPL_ENABLED() \
((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
#define HI_DEV_LPL_TYPE_GET(_devix) \
(HOST_INTEREST->hi_pwr_save_flags & \
((HI_PWR_SAVE_LPL_DEV_MASK) << \
(HI_PWR_SAVE_LPL_DEV0_LSB + \
(_devix)*2)))
#define HOST_INTEREST_SMPS_IS_ALLOWED() \
((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6004_VTOP(vaddr) (vaddr)
#define AR6006_VTOP(vaddr) (vaddr)
#define AR9888_VTOP(vaddr) (vaddr)
#define AR6320_VTOP(vaddr) (vaddr)
#define AR900B_VTOP(vaddr) (vaddr)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
0)))))))
#define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
0)))))))
#define AR6002_BOARD_DATA_SZ 768
#define AR6002_BOARD_EXT_DATA_SZ 0
#define AR6003_BOARD_DATA_SZ 1024
/* Reserve 1024 bytes for extended board data */
#if defined(AR6002_REV43)
#define AR6003_BOARD_EXT_DATA_SZ 1024
#else
#define AR6003_BOARD_EXT_DATA_SZ 768
#endif
#define AR6004_BOARD_DATA_SZ 7168
#define AR6004_BOARD_EXT_DATA_SZ 0
#define AR9888_BOARD_DATA_SZ 7168
#define AR9888_BOARD_EXT_DATA_SZ 0
#define AR6320_BOARD_DATA_SZ 8192
#define AR6320_BOARD_EXT_DATA_SZ 0
#define QCA9377_BOARD_DATA_SZ 8192
#define QCA9377_BOARD_EXT_DATA_SZ 0
#define AR900B_BOARD_DATA_SZ (14 * 1024)
#define AR900B_BOARD_EXT_DATA_SZ 0
#define QCA9984_BOARD_DATA_SZ (14 * 1024)
#define QCA9984_BOARD_EXT_DATA_SZ 0
#define QCA9888_BOARD_DATA_SZ (14 * 1024)
#define QCA9888_BOARD_EXT_DATA_SZ 0
#define IPQ4019_BOARD_DATA_SZ (14 * 1024)
#define IPQ4019_BOARD_EXT_DATA_SZ 0
/* Allocate board data right at the begining of AXI SRAM,
* Current size for beeliner is 14K.
* Allocate it towards the end of DRAM, until AXI SRAM is functional.
*/
#define AR900B_BOARD_DATA_ADDR 0xc0000
#define QCA9984_BOARD_DATA_ADDR 0xc0000
#define QCA9888_BOARD_DATA_ADDR 0xc0000
#define IPQ4019_BOARD_DATA_ADDR 0xc0000
#define AR6003_REV3_APP_START_OVERRIDE 0x946100
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74
#define AR6003_REV3_RAM_RESERVE_SIZE 4096
#define AR6004_REV1_BOARD_DATA_ADDRESS 0x423900
#define AR6004_REV1_RAM_RESERVE_SIZE 19456
#define AR6004_REV1_DATASET_PATCH_ADDRESS 0x425294
#define AR6004_REV2_BOARD_DATA_ADDRESS 0x426400
#define AR6004_REV2_RAM_RESERVE_SIZE 7168
#define AR6004_REV2_DATASET_PATCH_ADDRESS 0x435294
#define AR6004_REV5_BOARD_DATA_ADDRESS 0x436400
#define AR6004_REV5_RAM_RESERVE_SIZE 7168
#define AR6004_REV5_DATASET_PATCH_ADDRESS 0x437860
/* Reserve 4K for OTA test script */
#define AR6004_REV1_RAM_RESERVE_SIZE_FOR_TEST_SCRIPT 4096
#define AR6004_REV1_TEST_SCRIPT_ADDRESS 0x422900
/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
#define AR6003_FETCH_TARG_REGS_COUNT 64
#define AR6004_FETCH_TARG_REGS_COUNT 64
#define AR9888_FETCH_TARG_REGS_COUNT 64
#define AR6320_FETCH_TARG_REGS_COUNT 64
#define AR900B_FETCH_TARG_REGS_COUNT 64
#endif /* !__ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __TARGADDRS_H__ */

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/*
* Copyright (c) 2010-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __TARGCFG_H__
#define __TARGCFG_H__
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#endif
typedef struct _targcfg_t {
A_UINT32 num_vdev;
A_UINT32 num_peers;
A_UINT32 num_peer_ast;
A_UINT32 num_peer_keys;
A_UINT32 num_peer_tid;
A_UINT32 num_mcast_keys;
A_UINT32 num_tx;
A_UINT32 num_rx;
A_UINT32 num_mgmt_tx;
A_UINT32 num_mgmt_rx;
A_UINT32 tx_chain_mask;
A_UINT32 rx_chain_mask;
A_UINT32 override; /* Override target with the values supplied above */
} targcfg_t;
#endif /* __TARGCFG_H__ */

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/*
* Copyright (c) 2022,2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TXMON_TLVS_H_
#define _TXMON_TLVS_H_
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_M 0x0000ffff
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_S 0
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_M 0xffff0000
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_S 16
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_M 0x000000ff
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_S 0
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_M 0x00ffff00
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_S 8
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_M 0xffffffff
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_S 0
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_M 0x000fffff
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_S 0
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM_M 0x000007ff
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM_S 0
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_HW_LINK_ID_M 0x00003800
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_HW_LINK_ID_S 11
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID_M 0x0007c000
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID_S 14
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID_M 0x00080000
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID_S 19
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_M) >> \
TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_S)
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_M) >> \
TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_S)
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_M) >> \
TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_S)
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_PHY_MODE, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_MHZ_M) >> \
TXMON_FW2SW_MON_FES_SETUP_MHZ_S)
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_MHZ, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_MHZ_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_M) >> \
TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_S)
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_M) >> \
TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_S)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM_M) >> \
TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM_S)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_SEQ_NUM_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_HW_LINK_ID_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_HW_LINK_ID_M) >> \
TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_HW_LINK_ID_S)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_HW_LINK_ID_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_FW_COOKIEHW_LINK_ID, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_HW_LINK_ID_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID_M) >> \
TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID_S)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_PACKET_ID_S)); \
} while (0)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID_M) >> \
TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID_S)
#define TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_FW_COOKIE_VALID_S)); \
} while (0)
enum txmon_fw2sw_user_id {
TXMON_FW2SW_TYPE_FES_SETUP = 0, /* Placed after FES_SETUP */
TXMON_FW2SW_TYPE_FES_SETUP_USER = 1, /* Placed before FES_SETUP_COMPLETE */
TXMON_FW2SW_TYPE_FES_SETUP_EXT = 2, /* Placed after FES_SETUP_COMPLETE */
TXMON_FW2SW_TYPE_MAX = 4
};
typedef struct txmon_fw2sw_fes_setup {
A_UINT32 band_center_freq1 : 16,
band_center_freq2 : 16;
A_UINT32 phy_mode : 8, /* this field is filled with WLAN_PHY_MODE enum value */
mhz : 16,
reserved : 8;
A_UINT32 schedule_id;
A_UINT32 fw_cookie : 20,
rsvd : 12;
} txmon_fw2sw_fes_setup_t;
typedef struct txmon_fw2sw_fes_setup_ext {
A_UINT32 reserved;
} txmon_fw2sw_fes_setup_ext_t;
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_M 0x0000003f
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_S 0
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_GET(_var) \
(((_var) & TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_M) >> \
TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_S)
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID, _val); \
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_S)); \
} while (0)
typedef struct txmon_fw2sw_fes_setup_user {
A_UINT32 user_id : 6,
reserved : 24;
} txmon_fw2sw_fes_setup_user_t;
struct txmon_fw2sw_mon_fes_setup_tlv {
struct tlv_usr_32_hdr tag; /* tlv_usrid => TXMON_FW2SW_TYPE_FES_SETUP */
struct txmon_fw2sw_fes_setup setup;
};
struct txmon_fw2sw_mon_fes_setup_ext_tlv {
struct tlv_usr_32_hdr tag; /* tlv_usrid => TXMON_FW2SW_TYPE_FES_SETUP_EXT*/
struct txmon_fw2sw_fes_setup_ext setup_ext;
};
struct txmon_fw2sw_mon_fes_setup_user_tlv {
struct tlv_usr_32_hdr tag; /* tlv_usrid => TXMON_FW2SW_TYPE_FES_SETUP_USER */
struct txmon_fw2sw_fes_setup_user user_setup;
};
#endif /* _TXMON_TLVS_H_ */

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/*
* Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WAL_RX_DESC__H_
#define _WAL_RX_DESC__H_
#if defined(ATH_TARGET)
#include <athdefs.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
/*
* As this header is used by host also,
* and host will access target registers by target reg tbl,
* so disable direct-reference here for host.
*
*/
#if !defined(ATH_PERF_PWR_OFFLOAD)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) //FIXME_WIFI2 beeliner enbled by default (will be removed once we have target aware HTT)
#include <hw/interface/rx_location_info.h>
#include <hw/interface/rx_pkt_end.h>
#include <hw/interface/rx_phy_ppdu_end.h>
#include <hw/interface/rx_timing_offset.h>
#include <hw/interface/rx_location_info.h>
#include <hw/tlv/rx_attention.h>
#include <hw/tlv/rx_frag_info.h>
#include <hw/tlv/rx_msdu_start.h>
#include <hw/tlv/rx_msdu_end.h>
#include <hw/tlv/rx_mpdu_start.h>
#include <hw/tlv/rx_mpdu_end.h>
#include <hw/tlv/rx_ppdu_start.h>
#include <hw/tlv/rx_ppdu_end.h>
#else
/* HW rx descriptor definitions */
#include <mac_descriptors/rx_attention.h>
#include <mac_descriptors/rx_frag_info.h>
#include <mac_descriptors/rx_msdu_start.h>
#include <mac_descriptors/rx_msdu_end.h>
#include <mac_descriptors/rx_mpdu_start.h>
#include <mac_descriptors/rx_mpdu_end.h>
#include <mac_descriptors/rx_ppdu_start.h>
#include <mac_descriptors/rx_ppdu_end.h>
#endif
/*
* This struct defines the basic descriptor information, which is
* written by the 11ac HW MAC into the WAL's rx status descriptor
* ring.
*/
struct hw_rx_desc_base {
struct rx_attention attention;
struct rx_frag_info frag_info;
struct rx_mpdu_start mpdu_start;
struct rx_msdu_start msdu_start;
struct rx_msdu_end msdu_end;
struct rx_mpdu_end mpdu_end;
struct rx_ppdu_start ppdu_start;
struct rx_ppdu_end ppdu_end;
};
#endif
/*
* This struct defines the basic MSDU rx descriptor created by FW.
*/
struct fw_rx_desc_base {
union {
struct {
A_UINT8 discard : 1,
forward : 1,
any_err : 1,
dup_err : 1,
ipa_ind : 1,
inspect : 1,
extension: 2;
}bits;
A_UINT8 val;
}u;
};
#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
#define FW_RX_DESC_DISCARD_M 0x1
#define FW_RX_DESC_DISCARD_S 0
#define FW_RX_DESC_FORWARD_M 0x2
#define FW_RX_DESC_FORWARD_S 1
#define FW_RX_DESC_ANY_ERR_M 0x4
#define FW_RX_DESC_ANY_ERR_S 2
#define FW_RX_DESC_DUP_ERR_M 0x8
#define FW_RX_DESC_DUP_ERR_S 3
#define FW_RX_DESC_INSPECT_M 0x20
#define FW_RX_DESC_INSPECT_S 5
#define FW_RX_DESC_EXT_M 0xc0
#define FW_RX_DESC_EXT_S 6
#define FW_RX_DESC_CNT_2_BYTES(_fw_desc_cnt) (_fw_desc_cnt)
enum {
FW_RX_DESC_EXT_NONE = 0,
FW_RX_DESC_EXT_LRO_ONLY,
FW_RX_DESC_EXT_LRO_AND_OTHER,
FW_RX_DESC_EXT_OTHER
};
#define FW_RX_DESC_DISCARD_GET(_var) \
(((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
#define FW_RX_DESC_DISCARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
#define FW_RX_DESC_FORWARD_GET(_var) \
(((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
#define FW_RX_DESC_FORWARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
#define FW_RX_DESC_INSPECT_GET(_var) \
(((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
#define FW_RX_DESC_INSPECT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
#define FW_RX_DESC_EXT_GET(_var) \
(((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
#define FW_RX_DESC_EXT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_EXT_S))
/*
* This struct defines TCP_CHKSUM_OFFLOAD bit fields which are needed by host.
*/
struct fw_rx_msdu_info {
union {
/*
* The "bits" struct defines the flags in fw_rx_msdu_info used
* during regular operation.
*/
struct {
A_UINT8 tcp_udp_chksum_fail : 1, /* for tcp checksum offload use */
ip_chksum_fail : 1,
ipv6_proto : 1,
tcp_proto : 1,
udp_proto : 1,
ip_frag : 1,
first_wakeup : 1,
reserved : 1;
} bits;
/*
* The "mon" struct defines the flags in fw_rx_msdu_info used
* during monitor mode.
*/
struct {
A_UINT8 last_frag : 1,
reserved : 7;
} mon;
A_UINT8 val;
} u;
};
/* regular operation flags */
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M 0x1
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S 0
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M 0x2
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S 1
#define FW_RX_MSDU_INFO_IPV6_PROTO_M 0x4
#define FW_RX_MSDU_INFO_IPV6_PROTO_S 2
#define FW_RX_MSDU_INFO_TCP_PROTO_M 0x8
#define FW_RX_MSDU_INFO_TCP_PROTO_S 3
#define FW_RX_MSDU_INFO_UDP_PROTO_M 0x10
#define FW_RX_MSDU_INFO_UDP_PROTO_S 4
#define FW_RX_MSDU_INFO_IP_FRAG_M 0x20
#define FW_RX_MSDU_INFO_IP_FRAG_S 5
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_S 6
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IPV6_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
#define FW_RX_MSDU_INFO_IPV6_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
#define FW_RX_MSDU_INFO_TCP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
#define FW_RX_MSDU_INFO_TCP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
#define FW_RX_MSDU_INFO_UDP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
#define FW_RX_MSDU_INFO_UDP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
#define FW_RX_MSDU_INFO_IP_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
#define FW_RX_MSDU_INFO_IP_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
/* monitor mode flags */
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_M 0x1
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_S 0
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
#endif /* _WAL_RX_DESC__H_ */

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/*
* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WLAN_MODULE_IDS_H_
#define _WLAN_MODULE_IDS_H_
/* Wlan module ids , global across all the modules */
typedef enum {
WLAN_MODULE_ID_MIN = 0,
WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
WLAN_MODULE_WMI, /* 0x1 */
WLAN_MODULE_STA_PWRSAVE, /* 0x2 */
WLAN_MODULE_WHAL, /* 0x3 */
WLAN_MODULE_COEX, /* 0x4 */
WLAN_MODULE_ROAM, /* 0x5 */
WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */
WLAN_MODULE_RESMGR, /* 0x7 */
WLAN_MODULE_VDEV_MGR, /* 0x8 */
WLAN_MODULE_SCAN, /* 0x9 */
WLAN_MODULE_RATECTRL, /* 0xa */
WLAN_MODULE_AP_PWRSAVE, /* 0xb */
WLAN_MODULE_BLOCKACK, /* 0xc */
WLAN_MODULE_MGMT_TXRX, /* 0xd */
WLAN_MODULE_DATA_TXRX, /* 0xe */
WLAN_MODULE_HTT, /* 0xf */
WLAN_MODULE_HOST, /* 0x10 */
WLAN_MODULE_BEACON, /* 0x11 */
WLAN_MODULE_OFFLOAD, /* 0x12 */
WLAN_MODULE_WAL, /* 0x13 */
WAL_MODULE_DE, /* 0x14 */
WLAN_MODULE_PCIELP, /* 0x15 */
WLAN_MODULE_RTT, /* 0x16 */
WLAN_MODULE_RESOURCE, /* 0x17 */
WLAN_MODULE_DCS, /* 0x18 */
WLAN_MODULE_CACHEMGR, /* 0x19 */
WLAN_MODULE_ANI, /* 0x1a */
WLAN_MODULE_P2P, /* 0x1b */
WLAN_MODULE_CSA, /* 0x1c */
WLAN_MODULE_NLO, /* 0x1d */
WLAN_MODULE_CHATTER, /* 0x1e */
WLAN_MODULE_WOW, /* 0x1f */
WLAN_MODULE_WAL_VDEV, /* 0x20 */
WLAN_MODULE_WAL_PDEV, /* 0x21 */
WLAN_MODULE_TEST, /* 0x22 */
WLAN_MODULE_STA_SMPS, /* 0x23 */
WLAN_MODULE_SWBMISS, /* 0x24 */
WLAN_MODULE_WMMAC, /* 0x25 */
WLAN_MODULE_TDLS, /* 0x26 */
WLAN_MODULE_HB, /* 0x27 */
WLAN_MODULE_TXBF, /* 0x28 */
WLAN_MODULE_BATCH_SCAN, /* 0x29 */
WLAN_MODULE_THERMAL_MGR, /* 0x2a */
WLAN_MODULE_PHYERR_DFS, /* 0x2b */
WLAN_MODULE_RMC, /* 0x2c */
WLAN_MODULE_STATS, /* 0x2d */
WLAN_MODULE_NAN, /* 0x2e */
WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */
WLAN_MODULE_HIF_UART, /* 0x30 */
WLAN_MODULE_LPI, /* 0x31 */
WLAN_MODULE_EXTSCAN, /* 0x32 */
WLAN_MODULE_UNIT_TEST, /* 0x33 */
WLAN_MODULE_MLME, /* 0x34 */
WLAN_MODULE_SUPPL, /* 0x35 */
WLAN_MODULE_ERE, /* 0x36 */
WLAN_MODULE_OCB, /* 0x37 */
WLAN_MODULE_RSSI_MONITOR, /* 0x38 */
WLAN_MODULE_WPM, /* 0x39 */
WLAN_MODULE_CSS, /* 0x3a */
WLAN_MODULE_PPS, /* 0x3b */
WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */
WLAN_MODULE_MAWC, /* 0x3d */
WLAN_MODULE_CMC_QMIC, /* 0x3e */
WLAN_MODULE_EGAP, /* 0x3f */
WLAN_MODULE_NAN20, /* 0x40 */
WLAN_MODULE_QBOOST, /* 0x41 */
WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */
WLAN_MODULE_HALPHY, /* 0x43 */
WAL_MODULE_ENQ, /* 0x44 */
WLAN_MODULE_GNSS, /* 0x45 */
WLAN_MODULE_WAL_MEM, /* 0x46 */
WLAN_MODULE_SCHED_ALGO, /* 0x47 */
WLAN_MODULE_TX, /* 0x48 */
WLAN_MODULE_RX, /* 0x49 */
WLAN_MODULE_WLM, /* 0x4a */
WLAN_MODULE_RU_ALLOCATOR, /* 0x4b */
WLAN_MODULE_11K_OFFLOAD, /* 0x4c */
WLAN_MODULE_STA_TWT, /* 0x4d */
WLAN_MODULE_AP_TWT, /* 0x4e */
WLAN_MODULE_UL_OFDMA, /* 0x4f */
WLAN_MODULE_HPCS_PULSE, /* 0x50 */
WLAN_MODULE_DTF, /* 0x51 */ /* Deterministic Test Framework */
WLAN_MODULE_QUIET_IE, /* 0x52 */
WLAN_MODULE_SHMEM_MGR, /* 0x53 */
WLAN_MODULE_CFIR, /* 0x54 */ /* Channel Capture */
WLAN_MODULE_CODE_COVER, /* 0x55 */ /* code coverage */
WLAN_MODULE_SHO, /* 0x56 */ /* SAP HW offload */
WLAN_MODULE_MLO_MGR, /* 0x57 */ /* MLO manager */
WLAN_MODULE_PEER_INIT, /* 0x58 */ /* peer init connection handling */
WLAN_MODULE_STA_MLO_PS, /* 0x59 */ /* MLO PS manager */
WLAN_MODULE_MLO_SYNC_SEQ_NUM, /* 0x5a */ /* sync seq num after rm MPDU */
WLAN_MODULE_PLCMGR, /* 0x5b */ /* Policy Manager */
/* OEM module IDs:
* Reserve a small series of module IDs for use in OEM WLAN FW that
* interacts with WLAN FW SDK.
*/
WLAN_MODULE_OEM0, /* 0x5c */
WLAN_MODULE_OEM1, /* 0x5d */
WLAN_MODULE_OEM2, /* 0x5e */
WLAN_MODULE_OEM3, /* 0x5f */
WLAN_MODULE_OEM4, /* 0x60 */
WLAN_MODULE_OEM5, /* 0x61 */
WLAN_MODULE_OEM6, /* 0x62 */
WLAN_MODULE_OEM7, /* 0x63 */
WLAN_MODULE_T2LM, /* 0x64 */
WLAN_MODULE_HEALTH_MON, /* 0x65 */
WLAN_MODULE_XGAP, /* 0x66 */
WLAN_MODULE_MLO_OWNERSHIP_UPDATE, /* 0x67 */
WLAN_MODULE_SCHED_ALGO_TXBF, /* 0x68 */
WLAN_MODULE_SCHED_ALGO_DL_MU_MIMO, /* 0x69 */
WLAN_MODULE_SCHED_ALGO_UL_MU_MIMO, /* 0x6a */
WLAN_MODULE_SCHED_ALGO_DL_MU_OFDMA, /* 0x6b */
WLAN_MODULE_SCHED_ALGO_UL_MU_OFDMA, /* 0x6c */
WLAN_MODULE_SCHED_ALGO_SU, /* 0x6d */
WLAN_MODULE_SCHED_ALGO_MLO, /* 0x6e */
WLAN_MODULE_SCHED_ALGO_SAWF, /* 0x6f */
WLAN_MODULE_BAR, /* 0x70 */
WLAN_MODULE_SMART_TX, /* 0x71 */
WLAN_MODULE_BRIDGE_PEER, /* 0x72 */
WLAN_MODULE_AUX_MAC_MGR, /* 0x73 */
WLAN_MODULE_TCAM, /* 0x74 */
WLAN_MODULE_P2P_R2, /* 0x75 */
WLAN_MODULE_SYSSW, /* 0x76 */
/* HDL MODULE IDS */
WLAN_MODULE_PHYLIB_RXDCOCAL, /* 0x77 */
WLAN_MODULE_PHYLIB_COMBCAL, /* 0x78 */
WLAN_MODULE_PHYLIB_TPCCAL, /* 0x79 */
WLAN_MODULE_PHYLIB_BBFILTCAL, /* 0x7a */
WLAN_MODULE_PHYLIB_PKTDETCAL, /* 0x7b */
WLAN_MODULE_PHYLIB_PAPRDCAL, /* 0x7c */
WLAN_MODULE_PHYLIB_NFCAL, /* 0x7d */
WLAN_MODULE_PHYLIB_ADCCAL, /* 0x7e */
WLAN_MODULE_PHYLIB_DACCAL, /* 0x7f */
WLAN_MODULE_PHYLIB_PALCAL, /* 0x80 */
WLAN_MODULE_PHYLIB_RXGAINCAL, /* 0x81 */
WLAN_MODULE_PHYLIB_CALUTILS, /* 0x82 */
WLAN_MODULE_PHYLIB_PHYRESET, /* 0x83 */
WLAN_MODULE_PHYLIB_RFACONFIG, /* 0x84 */
WLAN_MODULE_PHYLIB_SETCHAINMASK, /* 0x85 */
WLAN_MODULE_PHYLIB_SETXBAR, /* 0x86 */
WLAN_MODULE_PHYLIB_M3, /* 0x87 */
WLAN_MODULE_PHYLIB_COMMON, /* 0x88 */
WLAN_MODULE_PHYLIB_SPURMITT, /* 0x89 */
WLAN_MODULE_PHYLIB_RTT, /* 0x8a */
WLAN_MODULE_PHYLIB_FTPG, /* 0x8b */
WLAN_MODULE_PHYLIB_RSTCAL, /* 0x8c */
WLAN_MODULE_PHYLIB_RXBBFCAL, /* 0x8d */
WLAN_MODULE_PHYLIB_TIADCCAL, /* 0x8e */
WLAN_MODULE_PHYLIB_IM2CAL, /* 0x8f */
WLAN_MODULE_PHYLIB_PACCAL, /* 0x90 */
WLAN_MODULE_PHYLIB_PDCCAL, /* 0x91 */
WLAN_MODULE_PHYLIB_SPURCAL, /* 0x92 */
WLAN_MODULE_PHYLIB_PHYDBG, /* 0x93 */
WLAN_MODULE_PHYLIB_RRI, /* 0x94 */
WLAN_MODULE_PHYLIB_SSCAN, /* 0x95 */
WLAN_MODULE_PHYLIB_RSVD, /* 0x96 */
WLAN_MODULE_USD, /* 0x97 */
WLAN_MODULE_ID_MAX,
WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
WLAN_MODULE_ID_ALL = 0xffff /* wildcard to indicate all modules */
} WLAN_MODULE_ID;
#endif /* _WLAN_MODULE_IDS_H_ */

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/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _WLAN_NAN_MSG_COMMON_V2_H_
#define _WLAN_NAN_MSG_COMMON_V2_H_
/*
* WLAN NAN CONSTANTS
*/
#ifndef PACKED_PRE
#define PACKED_PRE PREPACK
#endif
#ifndef PACKED_POST
#define PACKED_POST POSTPACK
#endif
/* ALL THE INTERFACE DEFINITIONS ARE ASSUMED TO BE IN LITTLE ENDIAN ORDER.
* BIG ENDIAN HOST IS RESPONSIBLE TO SEND/INTERPRET MESSAGES IN LITTLE
* ENDIAN FORMAT ONLY
*/
/* NAN message IDs */
typedef enum {
NAN_MSG_ID_ERROR_RSP = 0,
NAN_MSG_ID_CONFIGURATION_REQ = 1,
NAN_MSG_ID_CONFIGURATION_RSP = 2,
NAN_MSG_ID_PUBLISH_SERVICE_REQ = 3,
NAN_MSG_ID_PUBLISH_SERVICE_RSP = 4,
NAN_MSG_ID_PUBLISH_SERVICE_CANCEL_REQ = 5,
NAN_MSG_ID_PUBLISH_SERVICE_CANCEL_RSP = 6,
NAN_MSG_ID_PUBLISH_REPLIED_IND = 7,
NAN_MSG_ID_PUBLISH_TERMINATED_IND = 8,
NAN_MSG_ID_SUBSCRIBE_SERVICE_REQ = 9,
NAN_MSG_ID_SUBSCRIBE_SERVICE_RSP = 10,
NAN_MSG_ID_SUBSCRIBE_SERVICE_CANCEL_REQ = 11,
NAN_MSG_ID_SUBSCRIBE_SERVICE_CANCEL_RSP = 12,
NAN_MSG_ID_MATCH_IND = 13,
NAN_MSG_ID_UNMATCH_IND = 14,
NAN_MSG_ID_SUBSCRIBE_TERMINATED_IND = 15,
NAN_MSG_ID_DE_EVENT_IND = 16,
NAN_MSG_ID_TRANSMIT_FOLLOWUP_REQ = 17,
NAN_MSG_ID_TRANSMIT_FOLLOWUP_RSP = 18,
NAN_MSG_ID_FOLLOWUP_IND = 19,
NAN_MSG_ID_STATS_REQ = 20,
NAN_MSG_ID_STATS_RSP = 21,
NAN_MSG_ID_ENABLE_REQ = 22,
NAN_MSG_ID_ENABLE_RSP = 23,
NAN_MSG_ID_DISABLE_REQ = 24,
NAN_MSG_ID_DISABLE_RSP = 25,
NAN_MSG_ID_DISABLE_IND = 26,
NAN_MSG_ID_TCA_REQ = 27,
NAN_MSG_ID_TCA_RSP = 28,
NAN_MSG_ID_TCA_IND = 29,
NAN_MSG_ID_BEACON_SDF_REQ = 30,
NAN_MSG_ID_BEACON_SDF_RSP = 31,
NAN_MSG_ID_BEACON_SDF_IND = 32,
NAN_MSG_ID_CAPABILITIES_REQ = 33,
NAN_MSG_ID_CAPABILITIES_RSP = 34,
NAN_MSG_ID_SELF_TRANSMIT_FOLLOWUP_IND = 35,
NAN_MSG_ID_RANGING_REQUEST_IND = 36,
NAN_MSG_ID_RANGING_RESULT_IND = 37,
/* Add regular/non-test mode messages here */
NAN_MSG_ID_TESTMODE_REQ = 1025,
} nan_msg_id_t;
/* 8-byte control message header used by NAN */
typedef PACKED_PRE struct PACKED_POST {
A_UINT16 msg_version:4;
A_UINT16 msg_id:12;
A_UINT16 msg_len;
A_UINT16 handle;
A_UINT16 transaction_id;
} nan_msg_header_t, *nan_msg_header_tp;
#endif /* WLAN_NAN_MSG_COMMON_V2_H */

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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __WLANFW_HEALTH_MON_H__
#define __WLANFW_HEALTH_MON_H__
#include <a_types.h> /* A_UINT32 */
/* WLAN Health monitor data structure shared by host and FW */
/*
* Version 1 of the upload metric structs (i.e. wlanfw_health_mon_metric_upload_t)
* provides a fixed allocation of 8 bytes of scratch space after each metric,
* to optionally hold metric-specific data, e.g. from intermediate calculations when computing the score_pct.
*/
#define WLANFW_HEALTH_MON_EXTRA_WORDS32 2
/* word0:
* Extract bitfields from the A_UINT32 "word" containing them.
* The target produces the data in little-endian order.
* If the host uses big-endian order, it needs to account for the endianness
* difference when reading the data.
* Definition of bitfields within 32-bit word:
* bits 7:0 = module ID (M7...M0)
* bits 14:8 = module local ID (m6...m0)
* bits 31:15 = instance ID (I16...I0)
* bits
* |31 15|14 8|7 0|
* +-------------------------------+-----------------+-------------------+
* | instance ID | metric local ID | module ID |
* |I16 ... I0|m6 ... m0|M7 ... M0|
*
* Layout in memory:
* bits
* |7 |6 0|
* +---+--------------------------+
* byte 0 |M7 M6 M5 M4 M3 M2 M1 M0|
* +---+--------------------------+
* byte 1 |I0 |m6 m5 m4 m3 m2 m1 m0|
* +---+--------------------------+
* byte 2 |I8 I7 I6 I5 I4 I3 I2 I1|
* +------------------------------+
* byte 3 |I16 I15 I14 I13 I12 I11 I10 I9|
*/
#ifdef LITTLE_ENDIAN
/* The little-endian version of the macro to extract the module id and metric id */
#define WLANFW_HEALTH_MON_MODULE_ID_GET(word32) \
(((word32) & 0x000000ff) >> 0)
#define WLANFW_HEALTH_MON_METRIC_LOCAL_ID_GET(word32) \
(((word32) & 0x00007f00) >> 8)
#define WLANFW_HEALTH_MON_INSTANCE_ID_GET(word32) \
(((word32) & 0xffff8000) >> 15)
#else
/*
* When read into a big-endian 32-bit word:
* bits
* |31 24|23|22 16|15 8|7 0|
* +--------------+--+--------------+------------------+-----------------+
* |M7 M0|I0|m6 m0|I8 I1|I16 I9|
*
*/
/*
* big-endian macro def to extract module ID = M7:M0 = byte3
*/
#define WLANFW_HEALTH_MON_MODULE_ID_GET(word32) \
(((word32) >> 24) && 0xff)
/*
* big-endian macro def to extract metric local ID = m6:m0 = byte2 & 0x7f
*/
#define WLANFW_HEALTH_MON_METRIC_LOCAL_ID_GET(word32) \
(((word32) >> 16) && 0x7f)
/*
* big-endian macro def to extract instance ID = I16:I0 =
* (I16:I9 << 9) | (I8:I1 << 1) | I0
* (byte0 << 9) | (byte1 << 1) | (byte2 >> 7)
*/
#define WLANFW_HEALTH_MON_INSTANCE_ID_GET(word32) \
(((((word32) >> 0) & 0xff) << 9) | /* I16:I9 */ \
((((word32) >> 8) & 0xff) << 1) | /* I8:I1 */ \
((((word32) >> 23) & 0x01) << 0)) /* I0 */
#endif
/* word1:
* Extract bitfields from the A_UINT32 "word" containing them.
* The target produces the data in little-endian order.
* If the host uses big-endian order, it needs to account for the endianness
* difference when reading the data.
* Definition of bitfields within 32-bit word:
* bits 7:0 = score_pct (S7...S0)
* bits 15:8 = alarm_threshold (A7...A0)
* bit 16 = old_alarm_state (P)
* bits 20:17 = num_extra_bytes (N3..N0)
* bit 21 = valid_data_flag (V)
* bits 31:22 = reserved (R9...R0)
* bits
* |31 22|21|20 17|16|15 8|7 0|
* +------------------+--+---------+--+-----------------+----------------+
* | reserved |V |num bytes|P | alarm threshold | score_pct |
* |R9 R0|V |N3 N0|P |A7 A0|S7 S0|
*
* Layout in memory:
* bits
* |7 6| 5 |4 2|1 0|
* +-------+---+---------------+---+
* byte 0 |S7 S6 S5 S4 S3 S2 S1 S0 |
* +-------------------------------+
* byte 1 |A7 A6 A5 A4 A3 A2 A1 A0 |
* +-------+---+---------------+---+
* byte 2 |R1 R0 | V |N3 N2 N1 N0 | P |
* +-------------------------------+
* byte 3 |R9 R8 R7 R6 R5 R4 R3 R2 |
* +-------------------------------+
*/
#ifdef LITTLE_ENDIAN
#define WLANFW_HEALTH_MON_SCORE_PCT_GET(word32) \
(((word32) & 0x000000ff) >> 0)
#define WLANFW_HEALTH_MON_SCORE_ALARM_THRESHOLD_GET(word32) \
(((word32) & 0x0000ff00) >> 8)
#define WLANFW_HEALTH_MON_SCORE_OLD_ALARM_STATE_GET(word32) \
(((word32) & 0x00010000) >> 16)
#define WLANFW_HEALTH_MON_SCORE_NUM_EXTRA_BYTES_GET(word32) \
(((word32) & 0x001e0000) >> 17)
#define WLANFW_HEALTH_MON_SCORE_VALID_DATA_FLAG_GET(word32) \
(((word32) & 0x00200000) >> 21)
#else
/*
* When read into a big-endian 32-bit word:
* bits
* |31 24|23 16|15 14|13|12 9|8 |7 0|
* +----------------+--------------+-------------------+-----------------+
* |S7 S0|A7 A0|R1 R0|V |N3 N0|P |R9 R2|
*/
/*
* big-endian macro def to extract score_pct = S7:S0 = byte3
*/
#define WLANFW_HEALTH_MON_SCORE_PCT_GET(word32) \
(((word32) >> 24) && 0xff)
/*
* big-endian macro def to extract alarm_threshold = A7:A0 = byte2
*/
#define WLANFW_HEALTH_MON_SCORE_ALARM_THRESHOLD_GET(word32) \
(((word32) >> 16) && 0xff)
/*
* big-endian macro def to extract old_alarm_state = P = byte1 & 0x1
*/
#define WLANFW_HEALTH_MON_SCORE_OLD_ALARM_STATE_GET(word32) \
(((word32) >> 8) && 0x01)
/*
* big-endian macro def to extract num_extra_bytes = N3:N0 = (byte1>>1) & 0xf
*/
#define WLANFW_HEALTH_MON_SCORE_NUM_EXTRA_BYTES_GET(word32) \
(((word32) >> 9) && 0x0f)
/*
* big-endian macro def to extract valid_data_flag = V = (byte1 >> 5) & 0x1
*/
#define WLANFW_HEALTH_MON_SCORE_VALID_DATA_FLAG_GET(word32) \
(((word32) >> 13) && 0x01)
#endif
typedef struct _wlanfw_health_mon_metric_upload {
union {
A_UINT32 metric_id; /* Metric ID
* Unique ID assigned to every metric registered
*/
struct {
A_UINT32 module_id:8, /* module_id:
* Unique ID assigned to the FW module that owns the metric.
* Refer to WLAN_MODULE_ID enum.
*/
metric_local_id:7, /* metric_local_id:
* Unique ID (within the module) assigned to this type of metric by the module that owns the metric.
*/
instance_id:17; /* instance_id:
* The ID of the owner of this particular instance of the metric.
* E.g. for a per-pdev metric, this is the pdev_id, for a per-vdev metric this is the vdev_id, etc.
*/
};
};
union {
A_UINT32 word1;
struct {
A_UINT32 score_pct:8, /* range: 0 (bad) - 100 (perfect) */
alarm_threshold:8, /* alarm_threshold:
* If the metric's score falls below this threshold, the characteristic measured by the metric is a concern.
* If the score is above this threshold the characteristic in question is behaving normally.
* Any metrics that are purely for measurement (i.e. not for fault detection) should have alarm_threshold = 0.
*/
old_alarm_state:1, /* old_alarm_state:
* This flag indicates whether a score_pct below the alarm_threshold is new (old_alarm_state = 0) or ongoing (old_alarm_state = 1).
*/
num_extra_bytes:4, /* num_extra_words32:
* How many valid extra 4-byte words of metric-specific context follow this struct.
*/
valid_data_flag:1, /* valid_data_flag:
* Indication of whether this metric is in-use and containing valid data, or unallocated and invalid.
* Since the target may upload all metric objects, both those that are in use and those that are available but unused, the host must check this flag to see whether the metric object contains valid data.
*/
reserved:10;
};
};
/* Extra scratch space for metric specific context data, e.g. the raw data used to compute the score_pct. */
A_UINT32 extra_data[WLANFW_HEALTH_MON_EXTRA_WORDS32];
} wlanfw_health_mon_metric_upload_t;
typedef enum {
WLANFW_HEALTH_MON_UPLOAD_FMT_INVALID = 0,
/* V1: metrics use the wlanfw_health_mon_metric_upload_t format */
WLANFW_HEALTH_MON_UPLOAD_FMT_V1 = 1,
} wlanfw_health_mon_upload_fmt;
typedef struct _wlanfw_health_mon_upload_ring {
wlanfw_health_mon_upload_fmt version_number; /* version_number:
* Specifies the format of the uploaded records.
* 0 - unused
* 1 - the upload records use the wlanfw_health_mon_metric_upload_t format.
* (WLANFW_HEALTH_MON_UPLOAD_FMT_V1)
* All other values are reserved.
*/
/* specifies how large each element within the upload ring is */
A_UINT32 ring_element_bytes;
/* specifies how many spaces the ring contains */
A_UINT32 num_ring_elements;
/* specifies which ring element was last written by the target */
A_UINT32 write_index;
} wlanfw_health_mon_upload_ring_t;
typedef struct _wlanfw_health_mon_upload_ring_elem_t {
A_UINT32 timestamp;
/* how much of the head portion of the ring element contains valid data */
A_UINT32 num_valid_bytes;
} wlanfw_health_mon_upload_ring_elem_t;
#endif /* __WLANFW_HEALTH_MON_H__*/

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/*
* Copyright (c) 2010-2017 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* This file contains the definitions of the WMI protocol specified in the
* Wireless Module Interface (WMI). It includes definitions of all the
* commands and events. Commands are messages from the host to the WM.
* Events and Replies are messages from the WM to the host.
*
* Ownership of correctness in regards to commands
* belongs to the host driver and the WMI is not required to validate
* parameters for value, proper range, or any other checking.
*
*/
#ifndef _WMI_H_
#define _WMI_H_
#include "wlan_defs.h"
#include "wmix.h"
#include "wmi_unified.h"
#include "wmi_tlv_helper.h"
#include "wmi_tlv_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HTC_PROTOCOL_VERSION 0x0002
#define WMI_PROTOCOL_VERSION 0x0002
#define WMI_MODE_MAX 8
#define WMI_MAX_RATE_MASK 6
PREPACK struct host_app_area_s {
A_UINT32 wmi_protocol_ver;
} POSTPACK;
#undef MS
#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
#undef WO
#define WO(_f) ((_f##_OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f##_MASK) | SM(_val, _f))
#define WMI_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
#define WMI_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
#define WMI_EP_APASS WMI_EP_APSS /* TYPO: leave incorrect name as an alias for the correct name */
#define WMI_EP_APSS 0x0 /* WLAN driver running on apps processor sub-system */
#define WMI_EP_LPASS 0x1
#define WMI_EP_SENSOR 0x2
#define WMI_EP_NANOHUB 0x3 /* WLAN driver running on NANO Hub */
#define WMI_EP_MODEM 0x4
#define WMI_EP_LOCATION 0x5
/*
* Control Path
*/
typedef PREPACK struct {
A_UINT32 commandId : 24,
reserved : 2, /* used for WMI endpoint ID */
plt_priv : 6; /* platform private */
} POSTPACK WMI_CMD_HDR; /* used for commands and events */
#define WMI_CMD_HDR_COMMANDID_LSB 0
#define WMI_CMD_HDR_COMMANDID_MASK 0x00ffffff
#define WMI_CMD_HDR_COMMANDID_OFFSET 0x00000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK 0x03000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET 24
#define WMI_CMD_HDR_PLT_PRIV_LSB 24
#define WMI_CMD_HDR_PLT_PRIV_MASK 0xff000000
#define WMI_CMD_HDR_PLT_PRIV_OFFSET 0x00000000
/*
* List of Commands
*/
typedef enum {
WMI_EXTENSION_CMDID, //used in wmi_svc.c /* Non-wireless extensions */
WMI_IGNORE_CMDID, //used in wlan_wmi.c
} WMI_COMMAND_ID;
typedef enum {
NONE_CRYPT = 0x01,
WEP_CRYPT = 0x02,
TKIP_CRYPT = 0x04,
AES_CRYPT = 0x08,
#ifdef WAPI_ENABLE
WAPI_CRYPT = 0x10,
#endif /*WAPI_ENABLE*/
} CRYPTO_TYPE;
#define WMI_MAX_SSID_LEN 32
/*
* WMI_SET_PMK_CMDID
*/
#define WMI_PMK_LEN 32
/*
* WMI_ADD_CIPHER_KEY_CMDID
*/
typedef enum {
PAIRWISE_USAGE = 0x00,
GROUP_USAGE = 0x01,
TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
PMK_USAGE = 0x04, /* PMK cache */
LTF_USAGE = 0x08, /* LTF key seed */
} KEY_USAGE;
/*
* List of Events (target to host)
*/
typedef enum {
WMI_EXTENSION_EVENTID //wmi_profhook.c and umac_wmi_events.c
} WMI_EVENT_ID;
typedef enum {
WMI_11A_CAPABILITY = 1,
WMI_11G_CAPABILITY = 2,
WMI_11AG_CAPABILITY = 3,
WMI_11NA_CAPABILITY = 4,
WMI_11NG_CAPABILITY = 5,
WMI_11NAG_CAPABILITY = 6,
WMI_11AC_CAPABILITY = 7,
WMI_11AX_CAPABILITY = 8,
// END CAPABILITY
WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
} WMI_PHY_CAPABILITY;
/* Deprecated, need clean up */
#define WMI_MAX_RX_META_SZ (12)
typedef PREPACK struct {
A_INT8 rssi;
A_UINT8 info; /* usage of 'info' field(8-bit):
* b1:b0 - WMI_MSG_TYPE
* b4:b3:b2 - UP(tid)
* b5 - Used in AP mode. More-data in tx dir, PS in rx.
* b7:b6 - Dot3 header(0),
* Dot11 Header(1),
* ACL data(2)
*/
A_UINT16 info2; /* usage of 'info2' field(16-bit):
* b11:b0 - seq_no
* b12 - A-MSDU?
* b15:b13 - META_DATA_VERSION 0 - 7
*/
A_UINT16 info3; /* b3:b2:b1:b0 - device id
* b4 - Used in AP mode. uAPSD trigger in rx, EOSP in tx
* b7:b5 - unused?
* b15:b8 - pad before data start(irrespective of meta version)
*/
} POSTPACK WMI_DATA_HDR;
#ifdef __cplusplus
}
#endif
#endif /* _WMI_H_ */

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/*
* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WMI_SERVICES_H_
#define _WMI_SERVICES_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WMI_SERVICE_BEACON_OFFLOAD=0, /* beacon offload */
WMI_SERVICE_SCAN_OFFLOAD=1, /* scan offload */
WMI_SERVICE_ROAM_SCAN_OFFLOAD=2, /* roam scan offload */
WMI_SERVICE_BCN_MISS_OFFLOAD=3, /* beacon miss offload */
WMI_SERVICE_STA_PWRSAVE=4, /* fake sleep + basic power save */
WMI_SERVICE_STA_ADVANCED_PWRSAVE=5, /* uapsd, pspoll, force sleep */
WMI_SERVICE_AP_UAPSD=6, /* uapsd on AP */
WMI_SERVICE_AP_DFS=7, /* DFS on AP */
WMI_SERVICE_11AC=8, /* supports 11ac */
WMI_SERVICE_BLOCKACK=9, /* Supports triggering ADDBA/DELBA from host*/
WMI_SERVICE_PHYERR=10, /* PHY error */
WMI_SERVICE_BCN_FILTER=11, /* Beacon filter support */
WMI_SERVICE_RTT=12, /* RTT (round trip time) support */
WMI_SERVICE_WOW=13, /* WOW Support */
WMI_SERVICE_RATECTRL_CACHE=14, /* Rate-control caching */
WMI_SERVICE_IRAM_TIDS=15, /* TIDs in IRAM */
WMI_SERVICE_ARPNS_OFFLOAD=16, /* ARP NS Offload support for STA vdev */
WMI_SERVICE_NLO=17, /* Network list offload service */
WMI_SERVICE_GTK_OFFLOAD=18, /* GTK offload */
WMI_SERVICE_SCAN_SCH=19, /* Scan Scheduler Service */
WMI_SERVICE_CSA_OFFLOAD=20, /* CSA offload service */
WMI_SERVICE_CHATTER=21, /* Chatter service */
WMI_SERVICE_COEX_FREQAVOID=22, /* FW report freq range to avoid */
WMI_SERVICE_PACKET_POWER_SAVE=23, /* packet power save service */
WMI_SERVICE_FORCE_FW_HANG=24, /* Service to test the firmware recovery mechanism */
WMI_SERVICE_GPIO=25, /* GPIO service */
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM=26, /* Modulated DTIM support */
WMI_STA_UAPSD_BASIC_AUTO_TRIG=27, /* Basic version of station UAPSD AC Trigger Generation Method with
* variable trigger periods (service, delay, and suspend intervals) */
WMI_STA_UAPSD_VAR_AUTO_TRIG=28, /* Station UAPSD AC Trigger Generation Method with variable
* trigger periods (service, delay, and suspend intervals) */
WMI_SERVICE_STA_KEEP_ALIVE=29, /* Service to support the STA KEEP ALIVE mechanism */
WMI_SERVICE_TX_ENCAP=30, /* Packet type for TX encapsulation */
WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC=31, /* detect out-of-sync sleeping stations */
WMI_SERVICE_EARLY_RX=32, /* adaptive early-rx feature */
WMI_SERVICE_STA_SMPS=33, /* STA MIMO-PS */
WMI_SERVICE_FWTEST=34, /* Firmware test service */
WMI_SERVICE_STA_WMMAC=35, /* STA WMMAC */
WMI_SERVICE_TDLS=36, /* TDLS support */
WMI_SERVICE_BURST=37, /* SIFS spaced burst support */
WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE=38, /* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */
WMI_SERVICE_ADAPTIVE_OCS=39, /* Service to support adaptive off-channel scheduler */
WMI_SERVICE_BA_SSN_SUPPORT=40, /* target will provide Sequence number for the peer/tid combo */
WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE=41,
WMI_SERVICE_WLAN_HB=42, /* wlan HB service */
WMI_SERVICE_LTE_ANT_SHARE_SUPPORT=43, /* support LTE/WLAN antenna sharing */
WMI_SERVICE_BATCH_SCAN=44, /* Service to support batch scan */
WMI_SERVICE_QPOWER=45, /* QPower service */
WMI_SERVICE_PLMREQ=46,
WMI_SERVICE_THERMAL_MGMT=47, /* thermal throttling support,
* compared with
* WMI_SERVICE_THERM_THROT,
* this service only reports
* current temperature to host,
* and host will do the thermal
* throttling. */
WMI_SERVICE_RMC=48, /* RMC support */
WMI_SERVICE_MHF_OFFLOAD=49, /* multi-hop forwarding offload */
WMI_SERVICE_COEX_SAR=50, /* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */
WMI_SERVICE_BCN_TXRATE_OVERRIDE=51, /* Will support the bcn/prb rsp rate override */
WMI_SERVICE_NAN=52, /* Neighbor Awareness Network */
WMI_SERVICE_L1SS_STAT=53, /* L1SS statistics counter report */
WMI_SERVICE_ESTIMATE_LINKSPEED=54, /* Linkspeed Estimation per peer */
WMI_SERVICE_OBSS_SCAN=55, /* Service to support OBSS scan */
WMI_SERVICE_TDLS_OFFCHAN=56, /* TDLS off channel support */
WMI_SERVICE_TDLS_UAPSD_BUFFER_STA=57, /* TDLS UAPSD Buffer STA support */
WMI_SERVICE_TDLS_UAPSD_SLEEP_STA=58, /* TDLS UAPSD Sleep STA support */
WMI_SERVICE_IBSS_PWRSAVE=59, /* IBSS power save support */
WMI_SERVICE_LPASS=60, /* Service to support LPASS */
WMI_SERVICE_EXTSCAN=61, /* Extended Scans */
WMI_SERVICE_D0WOW=62, /* D0-WOW Support */
WMI_SERVICE_HSOFFLOAD=63, /* Hotspot offload feature Support */
WMI_SERVICE_ROAM_HO_OFFLOAD=64, /* roam handover offload */
WMI_SERVICE_RX_FULL_REORDER=65, /* target-based Rx full reorder */
WMI_SERVICE_DHCP_OFFLOAD=66, /* DHCP offload support */
WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT=67, /* STA RX DATA offload to IPA support */
WMI_SERVICE_MDNS_OFFLOAD=68, /* mDNS responder offload support */
WMI_SERVICE_SAP_AUTH_OFFLOAD=69, /* softap auth offload */
WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT=70, /* Dual Band Simultaneous support */
WMI_SERVICE_OCB=71, /* OCB mode support */
WMI_SERVICE_AP_ARPNS_OFFLOAD=72, /* arp offload support for ap mode vdev */
WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT=73, /* Per band chainmask support */
WMI_SERVICE_PACKET_FILTER_OFFLOAD=74, /* Per vdev packet filters */
WMI_SERVICE_MGMT_TX_HTT=75, /* Mgmt Tx via HTT interface */
WMI_SERVICE_MGMT_TX_WMI=76, /* Mgmt Tx via WMI interface */
WMI_SERVICE_EXT_MSG=77, /* WMI_SERVICE_READY_EXT msg follows */
WMI_SERVICE_MAWC=78, /* Motion Aided WiFi Connectivity (MAWC)*/
WMI_SERVICE_PEER_ASSOC_CONF=79, /* target will send ASSOC_CONF after ASSOC_CMD is processed */
WMI_SERVICE_EGAP=80, /* enhanced green ap support */
WMI_SERVICE_STA_PMF_OFFLOAD=81, /* FW supports 11W PMF Offload for STA */
WMI_SERVICE_UNIFIED_WOW_CAPABILITY=82, /* FW supports unified D0 and D3 wow */
WMI_SERVICE_ENHANCED_PROXY_STA=83, /* Enhanced ProxySTA mode support */
WMI_SERVICE_ATF=84, /* Air Time Fairness support */
WMI_SERVICE_COEX_GPIO=85, /* BTCOEX GPIO support */
WMI_SERVICE_AUX_SPECTRAL_INTF=86, /* Aux Radio enhancement support for ignoring spectral scan intf from main radios */
WMI_SERVICE_AUX_CHAN_LOAD_INTF=87, /* Aux Radio enhancement support for ignoring chan load intf from main radios*/
WMI_SERVICE_BSS_CHANNEL_INFO_64=88, /* BSS channel info (freq, noise floor, 64-bit counters) event support */
WMI_SERVICE_ENTERPRISE_MESH=89, /* Enterprise MESH Service Support */
WMI_SERVICE_RESTRT_CHNL_SUPPORT=90, /* Restricted Channel Support */
WMI_SERVICE_BPF_OFFLOAD=91, /* FW supports bpf offload */
WMI_SERVICE_SYNC_DELETE_CMDS=92, /* FW sends response event for Peer, Vdev delete commands */
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT=93,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT=94,
WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES=95, /* allow per-peer tx MCS min/max limits by host */
WMI_SERVICE_NAN_DATA=96, /* FW supports NAN data */
WMI_SERVICE_NAN_RTT=97, /* FW supports NAN RTT */
WMI_SERVICE_11AX=98, /* FW supports 802.11ax */
/* WMI_SERVICE_DEPRECATED_REPLACE
* FW supports these new WMI commands, to be used rather than
* deprecated matching commands:
* - WMI_PDEV_SET_PCL_CMDID (vs. WMI_SOC_SET_PCL_CMDID)
* - WMI_PDEV_SET_HW_MODE_CMDID (vs. WMI_SOC_SET_HW_MODE_CMDID)
* - WMI_PDEV_SET_MAC_CONFIG_CMDID (vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID)
* - WMI_PDEV_SET_ANTENNA_MODE_CMDID (vs. WMI_SOC_SET_ANTENNA_MODE_CMDID)
* - WMI_VDEV_SET_DSCP_TID_MAP_CMDID (vs. WMI_VDEV_SET_WMM_PARAMS_CMDID)
*/
WMI_SERVICE_DEPRECATED_REPLACE=99,
WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE=100, /* FW supports a new mode that allows to run connection tracker in host */
WMI_SERVICE_ENHANCED_MCAST_FILTER=101, /* FW supports enhanced multicast filtering (of mcast IP inside ucast WLAN) */
WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT=102, /* periodic channel stats service */
WMI_SERVICE_MESH_11S=103, /* 11s mesh service support */
WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT=104, /* FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate) channel bandwidth */
WMI_SERVICE_VDEV_RX_FILTER=105, /* Support per-vdev specs of which rx frames to filter out */
WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT=106,
WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET=107, /* FW supports marking the first data packet which wakes the host from suspend */
WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET=108, /* FW supports command that can add/delete multiple mcast filters */
/* WMI_SERVICE_HOST_MANAGED_RX_REORDER -
* FW supports host-managed RX reorder.
* Host managed RX reorder involves RX BA state machine handling
* on peer/TID basis, REO configuration for HW based reordering/PN
* check and processing reorder exceptions generated by HW.
*/
WMI_SERVICE_HOST_MANAGED_RX_REORDER=109,
/* Specify whether the target supports the following WMI messages for
* reading / writing its flash memory:
* WMI_READ_DATA_FROM_FLASH_CMDID,
* WMI_READ_DATA_FROM_FLASH_EVENTID,
* WMI_TRANSFER_DATA_TO_FLASH_CMDID,
* WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
*/
WMI_SERVICE_FLASH_RDWR_SUPPORT=110,
WMI_SERVICE_WLAN_STATS_REPORT=111, /* support WLAN stats report */
/* WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT -
* FW supports bigger MSDU ID partition which is defined as HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* When both host and FW support new partition, FW uses HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* If host doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
* Handshaking is done through WMI_INIT and WMI service ready
*/
WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT=112, /* support bigger MSDU ID partition */
WMI_SERVICE_DFS_PHYERR_OFFLOAD=113,
WMI_SERVICE_RCPI_SUPPORT=114,
WMI_SERVICE_FW_MEM_DUMP_SUPPORT=115, /* Support FW Memory dump */
WMI_SERVICE_PEER_STATS_INFO=116, /* support per peer stats info */
WMI_SERVICE_REGULATORY_DB=117, /* support regulatory database in FW */
WMI_SERVICE_11D_OFFLOAD=118, /* support 11D scan offload in FW */
WMI_SERVICE_HW_DATA_FILTERING=119,
WMI_SERVICE_MULTIPLE_VDEV_RESTART=120, /* Support for single command for multiple vdev restart */
WMI_SERVICE_PKT_ROUTING=121, /* Support for routing specific data packets to selected destination rings */
WMI_SERVICE_CHECK_CAL_VERSION=122, /* Support cal version check */
WMI_SERVICE_OFFCHAN_TX_WMI=123, /* Support offchan data/mgmt tx over wmi */
WMI_SERVICE_8SS_TX_BFEE = 124, /* support for 8Ant Bfee */
WMI_SERVICE_EXTENDED_NSS_SUPPORT=125, /* Extend NSS support for 80Mhz and 160Mhz */
WMI_SERVICE_ACK_TIMEOUT=126, /* Support TX ack timeout configurations */
WMI_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, /* BSS channel info (freq, noise floor, rx clear, cycles 64-bit counters) event support */
WMI_MAX_SERVICE=128, /* max service */
/* NOTE:
* The above service flags are delivered in the wmi_service_bitmap field
* of the WMI_SERVICE_READY_EVENT message.
* The below service flags are not delivered in the
* WMI_SERVICE_READY_EVENT message's wmi_service_bitmap field,
* but instead are delivered in the
* fixed_param.wmi_service_segment_bitmap portion
* of the WMI_SERVICE_AVAILABLE_EVENT message, with
* fixed_param.wmi_service_segment_offset
* set to 128.
* The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the
* WMI_SERVICE_READY_EVENT message.
*/
WMI_SERVICE_CHAN_LOAD_INFO=128, /* The values in WMI_CHAN_INFO_EVENTID is the difference in cycle counters */
WMI_SERVICE_TX_PPDU_INFO_STATS_SUPPORT=129, /* support to report tx ppdu info stats via htt events */
WMI_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT=130, /* support to report the offchannel duration limiting capability on connected interface */
WMI_SERVICE_FILS_SUPPORT=131, /* support for FILS */
WMI_SERVICE_WLAN_OIC_PING_OFFLOAD=132, /* Support for wlan OIC ping service */
WMI_SERVICE_WLAN_DHCP_RENEW=133, /* Support for wlan DHCP Renew service */
WMI_SERVICE_MAWC_SUPPORT = 134, /* Support for MAWC service */
WMI_SERVICE_VDEV_LATENCY_CONFIG=135, /* support for vdev latency config */
WMI_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT=136, /* support for pdev update ctl table */
WMI_SERVICE_PKTLOG_SUPPORT_OVER_HTT=137, /* upload pktlog data over HTT communication channel */
WMI_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT=138, /* Support for vdev level multi group key */
WMI_SERVICE_SCAN_PHYMODE_SUPPORT=139, /* Support for phymode also with channel in offchan WMI_START_SCAN_CMDID */
WMI_SERVICE_THERM_THROT = 140, /* Support thermal cfg and indication on AP.
* Compared with WMI_SERVICE_THERMAL_MGMT,
* this service is to allow thermal tool to
* configure thermal throttling threshold
* for different levels and pass down duty
* cycle value. FW will also report thermal
* throttling status to host through this
* service. */
WMI_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT=141, /* support dynamically enabling / disabling beacon tx offload */
WMI_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN=142, /* fw to support waking up host from wow pattern timer */
WMI_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT=143, /* Support for HTT peer map/unmap V2 */
WMI_SERVICE_OFFCHAN_DATA_TID_SUPPORT=144, /* Support new tid for offchan data/mgmt tx over wmi */
WMI_SERVICE_RX_PROMISC_ENABLE_SUPPORT=145, /* Support enabling/disabling rx promiscuous mode as directed by a WMI message from the host */
WMI_SERVICE_SUPPORT_DIRECT_DMA=146, /* indicates target supports direct DMA,
* host will rely on WMI_DMA_RING_CAPABILITIES to get supported modules */
WMI_SERVICE_AP_OBSS_DETECTION_OFFLOAD=147, /* Support SAP mode OBSS detection offload */
WMI_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT=148, /* Support for 11k neighbor report */
WMI_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT=149, /* Support listen interval offload */
WMI_SERVICE_BSS_COLOR_OFFLOAD=150, /* Support BSS color change for STA, OBSS color collision detection in FW for AP and STA */
WMI_SERVICE_RUNTIME_DPD_RECAL=151, /* Runtime DPD recalibration support */
WMI_SERVICE_STA_TWT=152, /* support for TWT (Target Wake Time) of STA */
WMI_SERVICE_AP_TWT=153, /* support for TWT (Target Wake Time) on AP */
WMI_SERVICE_GMAC_OFFLOAD_SUPPORT=154, /* Support for GMAC */
WMI_SERVICE_SPOOF_MAC_SUPPORT=155, /* support for SERVICE_SPOOF_MAC */
WMI_SERVICE_PEER_TID_CONFIGS_SUPPORT=156, /* Support TID specific configurations per peer (ack,aggr,retry,rate) */
WMI_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT=157, /* Support vdev software retries configuration per AC (non aggr retry/aggr retry) */
WMI_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT=158, /* Support dual beacon on same channel on single MAC */
WMI_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT=159, /* Support dual beacon on different channel on single MAC */
WMI_SERVICE_MOTION_DET=160, /* support for motion detection config */
WMI_SERVICE_INFRA_MBSSID=161, /* support infra multi-BSSID feature */
WMI_SERVICE_OBSS_SPATIAL_REUSE=162, /* support spatial reuse feature */
WMI_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT=163, /* Support different beacon intervals on different VDEVs */
WMI_SERVICE_NAN_DBS_SUPPORT=164, /* Support DBS for NAN discovery interface */
WMI_SERVICE_NDI_DBS_SUPPORT=165, /* Support DBS for NAN data interface */
WMI_SERVICE_NAN_SAP_SUPPORT=166, /* Support SAP Concurrency for NAN Discovery interface */
WMI_SERVICE_NDI_SAP_SUPPORT=167, /* Support SAP Concurrency for NAN Data interface */
WMI_SERVICE_CFR_CAPTURE_SUPPORT=168, /* Support to capture uncompressed Channel Frequency Response (CFR) */
WMI_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1=169, /* Message type HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 in HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND */
WMI_SERVICE_ESP_SUPPORT=170, /* Support for Estimated Service Params IE */
WMI_SERVICE_PEER_CHWIDTH_CHANGE = 171, /* Support for host to update/re-intersect the node capability */
WMI_SERVICE_WLAN_HPCS_PULSE=172, /* Support for High Precision Clock Synchronization feature */
WMI_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT=173, /* Support for configuring chainmask per VDEV */
WMI_SERVICE_TX_DATA_MGMT_ACK_RSSI=174, /* ACK RSSI indication to host for host TX data and mgmt frame */
WMI_SERVICE_NAN_DISABLE_SUPPORT=175, /* indicates firmware is dependent on host to disable NAN incase of concurrencies */
WMI_SERVICE_NAN_DISABLE_SUPPORT__prototype = WMI_SERVICE_NAN_DISABLE_SUPPORT, /* alias, to clarify that NAN_DISABLE_SUPPORT is for prototype testing purposes */
WMI_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN=176, /* indicates FW supports uniformly excluding the HTC header length from the HTT H2T message length */
WMI_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION=177, /* indicates FW supports FDD coex with unequal isolation between BT and each of the WLAN chains */
/* WMI_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT:
* Support HW+FW db2dbm conversion for RSSI fields in rx descriptors
* and host/target messages.
* If enabled, HW and FW will convert SNR to RSSI by adding noise floor
* and rssi_offset from BDF to RSSI values that formerly had units of
* dB w.r.t. noise floor to convert the units to dBm.
* MAC beacon RSSI average register return a signed value for RSSI,
* as well as hw descriptors.
*-------------------------------------------------------------------------
* The RSSI field of below WMI messages will be changed to dBm units:
* WMI_MGMT_RX_EVENTID:
* wmi_mgmt_rx_hdr.rssi_ctl;
* WMI_UPDATE_STATS_EVENTID:
* wmi_rssi_stats.rssi_avg_beacon;
* wmi_rssi_stats.rssi_avg_data;
* wmi_snr_info.bcn_snr;
* wmi_snr_info.dat_snr;
* wmi_vdev_stats.bcn_rssi_history; (NOT USED IN FW)
* wmi_peer_stats.peer_rssi;
* WMI_WOW_WAKEUP_HOST_EVENTID:
* wmi_rssi_breach_event_fixed_param.rssi;
* wmi_roam_event_fixed_param.rssi;
* WMI_PEER_STA_KICKOUT_EVENTID:
* wmi_peer_sta_kickout_event_fixed_param.rssi;
* WMI_PASSPOINT_MATCH_EVENTID:
* wmi_passpoint_event_hdr.rssi;(NOT USED IN FW)
* WMI_PEER_INFO_EVENTID:
* wmi_peer_info.rssi;
* WMI_ROAM_SYNCH_EVENTID:
* wmi_roam_synch_event_fixed_param.rssi;
* WMI_ROAM_SCAN_STATS_EVENTID:
* wmi_roam_scan_stats_event_fixed_param.rssi;
* wmi_pdev_div_rssi_antid_event_id:
* wmi_pdev_div_rssi_antid_event_fixed_param.chain_rssi;
* wmi_rssi_breach_event_id
* WMI_INST_RSSI_STATS_EVENTID:
* wmi_inst_rssi_stats_resp_fixed_param.iRSSI;
* RSSI thresholds configured by host
* WMI_ROAM_SCAN_RSSI_THRESHOLD
* roam_scan_rssi_thresh snr
* boost_threshold_5g snr
* penalty_threshold_5g snr
* good_rssi_threshold snr
* roam_bg_scan_bad_rssi_thresh snr
* roam_earlystop_thres_min snr
* roam_earlystop_thres_max snr
* WMI_ROAM_AP_PROFILE
* rssi_abs_thresh snr
* WMI_ROAM_CONFIGURE_MAWC_CMDID:
* best_ap_rssi_threshold Snr
* wmi_ap_profile.rssi_abs_thresh;
* WMI_ROAM_SCAN_RSSI_THRESHOLD:
* wmi_roam_scan_extended_threshold_param.boost_threshold_5g;
* wmi_roam_scan_extended_threshold_param.penalty_threshold_5g;
* wmi_roam_scan_extended_threshold_param.good_rssi_threshold;
* wmi_roam_scan_rssi_threshold_fixed_param.roam_scan_rssi_thresh;
* wmi_roam_bg_scan_roaming_param.roam_bg_scan_bad_rssi_thresh;
* WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID:
* wmi_vdev_spectral_configure_cmd_fixed_param.spectral_scan_rssi_rpt_mode;
* wmi_vdev_spectral_configure_cmd_fixed_param.spectral_scan_rssi_thr;
* WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID:
* wmi_rssi_breach_monitor_config_fixed_param.low_rssi_breach_threshold;
* wmi_rssi_breach_monitor_config_fixed_param.hi_rssi_breach_threshold;
* WMI_STA_SMPS_PARAM_CMDID:
* wmi_sta_smps_param.value of below cmd IDs:
* // RSSI threshold to enter Dynamic SMPS mode from inactive mode
* WMI_STA_SMPS_PARAM_UPPER_RSSI_THRESH = 0,
* // RSSI threshold to enter Stalled-D-SMPS mode from D-SMPS mode
* // or to enter D-SMPS mode from Stalled-D-SMPS mode
* WMI_STA_SMPS_PARAM_STALL_RSSI_THRESH = 1,
* // RSSI threshold to disable SMPS modes
* WMI_STA_SMPS_PARAM_LOWER_RSSI_THRESH = 2,
* // Upper threshold for beacon-RSSI. Used to reduce RX chainmask.
* WMI_STA_SMPS_PARAM_UPPER_BRSSI_THRESH = 3,
* // Lower threshold for beacon-RSSI. Used to increase RX chainmask
* WMI_STA_SMPS_PARAM_LOWER_BRSSI_THRESH = 4,
* // Enable/Disable DTIM 1chRx feature
* WMI_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5
* WMI_TDLS_SET_STATE_CMDID:
* wmi_tdls_set_state_cmd_fixed_param.rssi_teardown_threshold;
* wmi_tdls_set_state_cmd_fixed_param.rssi_delta;
*-------------------------------------------------------------------------
* The RSSI fields of below HTT data type will change to dBm units:
* PREPACK struct htt_tx_wbm_completion.ack_frame_rssi;
* PREPACK struct htt_tx_wbm_transmit_status.ack_frame_rssi;
* htt_ppdu_stats_user_cmpltn_common_tlv.ack_rssi;
*/
WMI_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178,
WMI_SERVICE_SUPPORT_EXTEND_ADDRESS=179, /* indicates firmware supports host memory addresses larger than 32 bit */
WMI_SERVICE_BEACON_RECEPTION_STATS=180, /* Support per vdev beacon stats info */
WMI_SERVICE_FETCH_TX_PN=181,
WMI_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, /* support peer ids unmap response from host */
WMI_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, /* indicate FW support per peer TX AMPDU size */
WMI_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, /* Firmware supports bss-color switch count handling */
WMI_SERVICE_HTT_PEER_STATS_SUPPORT = 185, /* Supports the feature where FW sends peer stats autonomously to Host via the HTT_T2H PEER_STATS_IND message */
WMI_SERVICE_UL_RU26_ALLOWED = 186, /* indicates support for RU26 in UL OFDMA */
WMI_SERVICE_GET_MWS_COEX_STATE = 187, /* FW provides MWS Coex info */
WMI_SERVICE_GET_MWS_DPWB_STATE = 188, /* FW provides LTE-Coex Dynamic Power Back-off info */
WMI_SERVICE_GET_MWS_TDM_STATE = 189, /* FW provides LTE-Coex TDM info */
WMI_SERVICE_GET_MWS_IDRX_STATE = 190, /* FW provides LTE-Coex IDRx info */
WMI_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, /* FW provides LTE-Coex Antenna sharing info */
WMI_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, /* FW provides enhanced tx power control configuration dump */
WMI_SERVICE_WLM_STATS_REQUEST = 193, /* FW supports WLAN latency manager stats request */
WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, /* Extended Peer Tid configuration support for QoS related settings */
WMI_SERVICE_WPA3_FT_SAE_SUPPORT = 195, /* FW roaming support for WPA3_FT_SAE */
WMI_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, /* FW roaming support for WPA3_FT_SUITE_B */
WMI_SERVICE_VOW_ENABLE=197, /* FW supports a set of features to optimize VoW performance */
WMI_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, /* support WMI_PEER_CFR_CAPTURE_EVENT msg */
WMI_SERVICE_BROADCAST_TWT = 199, /* support of Broadcast TWT (Target Wake Time) for STA/AP */
WMI_SERVICE_RAP_DETECTION_SUPPORT = 200, /* indicate FW supports rogue AP detection */
WMI_SERVICE_PS_TDCC = 201, /* FW support tx_duty_cycle_control powersave */
WMI_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, /* BTCOEX Three-way CoEx Config Legacy Feature support */
WMI_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, /* BTCOEX Three-way CoEx Config Override Feature support */
WMI_SERVICE_TX_PWR_PER_PEER = 204, /* target supports per-peer tx pwr spec via WMI_PEER_USE_FIXED_PWR */
WMI_SERVICE_STA_PLUS_STA_SUPPORT = 205, /* indicates target supports STA + STA concurrency */
WMI_SERVICE_WPA3_FT_FILS = 206,
WMI_SERVICE_ADAPTIVE_11R_ROAM = 207, /* Indicates FW supports adaptive 11r roaming */
WMI_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, /* FW provides RF scores for chans in the service ready extension msg */
WMI_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, /* FW sends WMI_IFACE_COMBINATION_IND_EVENT msg immediately after WMI_SERVICE_READY_EXT_EVENT msg */
WMI_SERVICE_TX_COMPL_TSF64 = 210, /* FW supports 64-bit tx TSF in HTT_T2H TX_COMPL_IND msg */
WMI_SERVICE_DSM_ROAM_FILTER = 211, /* FW supports data stall AP mitigation while roaming */
WMI_SERVICE_PACKET_CAPTURE_SUPPORT = 212, /* target supports packet capture Mode (SMART MU) */
WMI_SERVICE_PER_PEER_HTT_STATS_RESET = 213, /* FW supports HTT per peer stats reset facility */
WMI_SERVICE_DELETE_ALL_PEER_SUPPORT = 214, /* target supports cmd to delete all peers within a vdev */
WMI_SERVICE_DYNAMIC_HW_MODE_SWITCH_SUPPORT = 215, /* target supports Dynamic HW mode switch */
WMI_SERVICE_MSDU_FLOW_OVERRIDE_BY_HOST = 216, /* target supports flow override feature */
WMI_SERVICE_WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENT= 217, /* target will send WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENT */
WMI_SERVICE_RX_FSE_SUPPORT = 218, /* target supports flow search through RxOLE FSE hw block */
WMI_SERVICE_FREQINFO_IN_METADATA = 219, /* FW provides freq_info during spectral scan */
WMI_SERVICE_EXT2_MSG = 220, /* WMI_SERVICE_READY_EXT2 msg is sent by target */
WMI_SERVICE_WPA3_SAE_ROAM_SUPPORT = 221, /* Indicates FW supports WPA3 SAE roaming */
WMI_SERVICE_WPA3_OWE_ROAM_SUPPORT = 222, /* Indicates FW supports WPA3 OWE roaming */
WMI_SERVICE_AUDIO_AGGR = 223, /* Indicates FW supports audio frame aggregation */
WMI_SERVICE_6GHZ_SUPPORT = 224, /* Indicates FW supports 6GHZ (scan, connection and so on) */
/* WMI_SERVICE_QMI_STATS_SUPPORT
* Indicates FW supports stat request command WMI_REQUEST_LINK_STATS_CMDID
* and WMI_REQUEST_STATS_CMDID coming from QMI which will be used in
* runtime PM suspend.
*/
WMI_SERVICE_QMI_STATS_SUPPORT = 225,
WMI_SERVICE_CFR_CAPTURE_FILTER_SUPPORT = 226, /* Indicate FW Supports Channel Frequency Response (CFR) via WMI_CFR_CAPTURE_FILTER_CMDID */
WMI_SERVICE_STA_BSS_MAX_IDLE_TIME = 227, /* Indicate FW supports BSS Max Idle time feature via WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID */
WMI_SERVICE_BIP_CIPHER_SUPPORT = 228, /* FW supports new BIP_CIPHER suites (WMI_CIPHER_BIP_xxx) */
WMI_SERVICE_BW_165MHZ_SUPPORT = 229, /* Indicate FW supports bandwidth 165MHz (i.e. 6 GHz in addition to 2.4 and 5) */
WMI_SERVICE_BW_RESTRICTED_80P80_SUPPORT = WMI_SERVICE_BW_165MHZ_SUPPORT,
WMI_SERVICE_NAN_NDI_SAP_SAP_SCC_SUPPORT = 230, /* Support SAP + SAP + NAN discovery + NDI concurrency in SCC mode */
WMI_SERVICE_NAN_VDEV_SUPPORT = 231, /* indicates firmware is dependent on host to create NAN vdev */
WMI_SERVICE_AUDIO_SYNC_SUPPORT = 232, /* Indicate FW supports Audio sync feature */
WMI_SERVICE_DUAL_STA_ROAM_SUPPORT = 233, /* Indidate FW support dual STA roaming */
WMI_SERVICE_PEER_CREATE_CONF = 234, /* Target will send WMI_PEER_CREATE_CONF_EVENTID after WMI_PEER_CREATE_CMDID is processed */
WMI_SERVICE_MULTIPLE_VDEV_RESTART_RESPONSE_SUPPORT = 235, /* indicates firmware supports Multiple vdev restart response */
WMI_SERVICE_ROAM_SCAN_CHANNEL_LIST_TO_HOST_SUPPORT = 236, /* Indicates firmware supports sending roam scan channel list to host */
WMI_SERVICE_PEER_DELETE_NO_PEER_FLUSH_TIDS_CMD = 237, /* Host should not send WMI_PEER_FLUSH_TIDS_CMD as part of peer delete */
WMI_SERVICE_NSS_RATIO_TO_HOST_SUPPORT = 238, /* Indicates firmware supports sending NSS ratio info to host */
WMI_SERVICE_WPA3_SUITEB_ROAM_SUPPORT = 239, /* Indicates FW supports WPA3 SUITE B roaming */
WMI_SERVICE_PERIODIC_FRAME_INJECT_SUPPORT = 240, /* Indicates FW supports periodic frame injection */
WMI_SERVICE_NDI_NDI_STA_SUPPORT = 241, /* Indicates FW support for STA+NDI+NDI */
WMI_SERVICE_BW_TRUE_160_SUPPORT = 242, /* Indicates FW supports true 160 BW */
WMI_SERVICE_HOST_SCAN_STOP_VDEV_ALL_SUPPORT = 243, /* Indicates FW supports scan stop mode WMI_SCN_STOP_HOST_VAP_ALL */
WMI_SERVICE_BEACON_PROTECTION_SUPPORT = 244, /* Indicates FW supports WPA3 Beacon protection */
WMI_SERVICE_EMA_AP_SUPPORT = 245, /* FW supports EMA AP feature */
WMI_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, /* Support for adding Power save duration per client */
WMI_SERVICE_5_DOT_9GHZ_SUPPORT = 247, /* Indicates FW supports new 5.9GHZ (scan, connection and so on) */
WMI_SERVICE_MU_PREAMBLE_PUNCTURE_SUPPORT = 248, /* Indicates FW supports MU preamble puncture */
WMI_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, /* Support for SRG, SRP based spatial reuse support */
WMI_REQUEST_CTRL_PATH_STATS_REQUEST = 250, /* FW supports control path stats */
WMI_SERVICE_TPC_STATS_EVENT = 251, /* FW support to dump the TPC tables */
WMI_SERVICE_NO_INTERBAND_MCC_SUPPORT = 252, /* Indicates FW doesn't support interband MCC */
WMI_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, /* FW supports VDEV's MBSS param exchange in VDEV start command */
WMI_SERVICE_CONFIGURE_ROAM_TRIGGER_PARAM_SUPPORT = 254, /* FW supports ROAM trigger configuration param TLV */
WMI_SERVICE_CFR_TA_RA_AS_FP_SUPPORT = 255, /* indicates FW support to program CFR TA/RA filtered packets as Filter pass */
/******* ADD NEW SERVICES UP TO 256 HERE *******/
WMI_MAX_EXT_SERVICE = 256,
/* NOTE:
* The above service flags are delivered in the
* fixed_param.wmi_service_segment_bitmap portion
* of the WMI_SERVICE_AVAILABLE_EVENT message, with
* fixed_param.wmi_service_segment_offset
* set to 128.
* The below service flags can be delivered in one of two ways:
* 1. The target can deliver a 2nd SERVICE_AVAILABLE message, with
* fixed_param.wmi_service_segment_offset
* set to 256.
* (This method is acceptable, but not recommended.)
* 2. The target can populate the wmi_service_ext_bitmap[] TLV array
* within the WMI_SERVICE_AVAILABLE_EVENT message.
* (This method is recommended.)
*/
/******* ADD NEW SERVICES 256 AND BEYOND HERE *******/
WMI_SERVICE_CFR_CAPTURE_COUNT_SUPPORT = 256, /* indicates FW support to program CFR capture mode and capture count */
WMI_SERVICE_OCV_SUPPORT = 257, /* FW supports OCV (Operating Channel Validation) */
WMI_SERVICE_LL_STATS_PER_CHAN_RX_TX_TIME_SUPPORT = 258, /* Indicates firmware support sending per channel own tx & rx time in radio stats of LL stats. */
WMI_SERVICE_THERMAL_MULTI_CLIENT_SUPPORT = 259, /* Indicates FW Thermal Mgr will support multiple clients for mitigation */
WMI_SERVICE_NAN_SEND_NAN_ENABLE_RESPONSE_TO_HOST = 260, /* Indicates FW will include an additional TLV in nan enable response for Host driver to parse */
WMI_SERVICE_UNIFIED_LL_GET_STA_CMD_SUPPORT = 261, /* Indicates that FW supports handling Link Layer and Get Station stats Commands together (WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID) */
WMI_SERVICE_FSE_CMEM_ALLOC_SUPPORT = 262, /* Indicates that FW supports non-secure CMEM allocation for FSE table */
WMI_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, /* Indicates FW support to not skip beacon if passive scan dwell time + channel switch delay is lesser than beacon interval */
WMI_SERVICE_QOS_NULL_FRAME_TX_OVER_WMI = 264, /* Indicates that FW supports tx of QoS null frame downloaded through WMI interface */
WMI_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, /* Indicates that FW supports per channel configuration support in the scan start command */
WMI_SERVICE_CSA_BEACON_TEMPLATE = 266, /* Indicates that FW supports updating CSA count in beacon template */
WMI_SERVICE_BROADCAST_TWT_REQUESTER = 267, /* Indicates FW supports Broadcast TWT REQUESTER */
WMI_SERVICE_BROADCAST_TWT_RESPONDER = 268, /* Indicates FW supports Broadcast TWT RESPONDER */
WMI_SERVICE_TWT_NUDGE = 269, /* Indicates that FW supports TWT Nudge command and event */
WMI_SERVICE_TWT_STATS = 270, /* Indicates that FW supports TWT Get_stats command and event */
WMI_SERVICE_TWT_ALL_DIALOG_ID = 271, /* Indicates that FW supports TWT ALL dialog ID(255) for all commands and events, except for TWT add dialog and TWT get stats */
WMI_SERVICE_SPLIT_AST_SUPPORT = 272, /* Indicate that FW supports SPLIT AST table */
WMI_SERVICE_SPECTRAL_SCAN_DISABLED = 273, /* Indicates that SKU does not support normal spectral scan capabilities */
/* WMI_SERVICE_UNIFIED_LL_GET_STA_OVER_QMI_SUPPORT:
* This service flag indicates that FW can support receiving a
* WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID command request from the host
* over the QMI communication link.
* If the target receives WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID over QMI,
* any of the event messages sent in response (WMI_UPDATE_STATS_EVENTID,
* WMI_IFACE_LINK_STATS_EVENTID, WMI_PEER_LINK_STATS_EVENTID,
* WMI_RADIO_LINK_STATS_EVENTID, WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID)
* will be delivered over the QMI communication link.
* Any such messages delivered over QMI will use the same message format
* as if they had been delivered over the usual WMI communication link.
* This service flag indicates QMI is supported for these stats messages
* in addition to WMI, not instead of WMI - if the host sends the
* WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID over the usual WMI communication
* link, the stats event messages sent by the target in response will
* be sent on the WMI communication link.
*/
WMI_SERVICE_UNIFIED_LL_GET_STA_OVER_QMI_SUPPORT = 274,
/*
* Indicates FW supports EAPOL offload for SAE roaming if PMK of
* candidate AP is present in FW.
*/
WMI_SERVICE_SAE_EAPOL_OFFLOAD_SUPPORT = 275,
/*
* Indicates FW supports sending events to host during Thermal Throttling
* every duty cycle on detecting temperature change when dc_per_event is 0.
*/
WMI_SERVICE_THERM_THROT_TEMP_CHANGE_DYNAMIC_EVENT_SUPPORT = 276,
WMI_SERVICE_WAPI_CONCURRENCY_SUPPORTED = 277, /* Indicates FW support for WAPI concurrency */
WMI_SERVICE_SAP_CONNECTED_D3WOW = 278, /* Indicates FW support for D3WoW for SAP connected case */
WMI_SERVICE_GO_CONNECTED_D3WOW = 279, /* Indicates FW support for D3WoW for P2P GO connected case */
WMI_SERVICE_EXT_TPC_REG_SUPPORT = 280, /* Support for new 6 GHz TPC power limits */
WMI_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, /* Support for Extended REG_CC Event with additional params for 6 GHz */
WMI_SERVICE_NDI_TXBF_SUPPORT = 282, /* Indicates FW support for Tx beamforming with NDI VDEV */
WMI_SERVICE_ENABLE_LOWER_6G_EDGE_CH_SUPP = 283, /* Indicates FW support for enabling lower 6 GHz edge channel 5935 */
WMI_SERVICE_DISABLE_UPPER_6G_EDGE_CH_SUPP = 284, /* Indicates FW support for disabling upper 6 GHz edge channel 7115 */
WMI_SERVICE_FORCED_DTIM_SUPP = 285, /* Indicates FW supports forced DTIM configuration */
WMI_SERVICE_DCS_AWGN_INT_SUPPORT = 286, /* Indicates FW supports AWGN Int */
WMI_SERVICE_IGMP_OFFLOAD_SUPPORT = 287, /* FW supports igmp offload during APPS suspend */
WMI_SERVICE_11AX_TDLS_SUPPORT = 288, /* Indicates FW supports 11ax TDLS. Host should enable 11ax on TDLS only when FW indicates the support. */
WMI_SERVICE_11BE = 289, /* Indicates FW supports 11be */
WMI_SERVICE_BIG_DATA_SUPPORT = 290, /* Indicates FW supports Big Data feature */
WMI_SERVICE_EAPOL_OVER_NWIFI = 291, /* Indicates FW supports sending eapol frames in native wifi mode even when the vdev is brought up in raw ethernet mode */
WMI_SERVICE_AMPDU_TX_BUF_SIZE_256_SUPPORT = 292, /* Indicates FW supports MAX 256 MPDUs in A-MPDU instead of 64 */
WMI_SERVICE_HALPHY_CAL_STATUS = 293, /* Indicates FW supports sending online HALPHY Calibration status to host */
WMI_SERVICE_HALPHY_CAL_ENABLE_DISABLE_SUPPORT = 294, /* Indicates Calibraton enable/disable support by FW */
WMI_SERVICE_AFC_SUPPORT = 295, /* Indicates FW supports AFC_CMD,AFC_EVENT */
WMI_SERVICE_RTT_AP_INITIATOR_STAGGERED_MODE_SUPPORTED = 296, /* FW supports RTT in AP Initiator for Staggered beacon mode */
WMI_SERVICE_RTT_AP_INITIATOR_BURSTED_MODE_SUPPORTED = 297, /* FW supports RTT in AP Initiator for BURSTED beacon mode */
WMI_SERVICE_P2P_P2P_CONCURRENCY_SUPPORT = 298, /* Indicates FW supports P2P + P2P conncurency both in SCC, MCC, SBS and DBS */
WMI_SERVICE_MGMT_RX_REO_SUPPORTED = 299, /* Indicates FW supports Management RX Reorder */
WMI_SERVICE_EMA_MULTIPLE_GROUP_SUPPORT = 300, /* FW support for EMA multi group support */
WMI_SERVICE_LARGE_BEACON_SUPPORT = 301, /* FW support for Large beacon support greater then 1.5K */
WMI_SERVICE_AOA_FOR_RCC_SUPPORTED = 302,
WMI_SERVICE_DYN_NSS_MASK_SUPPORT = 303, /* Indicates FW support for DYN NSS feature */
WMI_SERVICE_HW_MODE_POLICY_OFFLOAD_SUPPORT = 304, /* FW supports HW mode selection offload */
WMI_SERVICE_THERMAL_THROT_STATS_TEMP_RANGE_SUPPORT = 305, /* FW supports thermal throttling temperature range stats based on wmi_thermal_stats_action */
/*
* Indicates FW support for spatial reuse enhancements.
* Below commands are added for the enhancements:
* WMI_PDEV_PARAM_OBSS_MIN_DURATION_CHECK_FOR_SR,
* WMI_PDEV_PARAM_TRUNCATE_SR,
* WMI_PDEV_PARAM_CTRL_FRAME_OBSS_PD_THRESHOLD
*/
WMI_SERVICE_SPATIAL_REUSE_ENHANCEMENT_SUPPORT = 306,
WMI_SERVICE_MU_SNIF = 307, /* FW support MU sniffer */
WMI_SERVICE_ICMP_OFFLOAD = 308, /* FW supports ping offload during APPS suspend */
WMI_SERVICE_RTSCTS_FOR_UNICAST_MGMT_SUPPORT = 309, /* Indicates FW support RTSCTS for unicast management */
WMI_SERVICE_DYNAMIC_VDEV_MAC_ADDR_UPDATE_SUPPORT = 310, /* FW supports dynamic vdev mac address updating */
WMI_SERVICE_SAWF_LEVEL0 = 311, /* FW supports WMI_SAWF_SVC_CLASS CFG_CMD + DISABLE_CMD msgs */
WMI_SERVICE_RTT_11AZ_NTB_SUPPORT = 312, /* FW support for 11AZ non trigger based ranging */
WMI_SERVICE_RTT_11AZ_TB_SUPPORT = 313, /* FW support for 11AZ trigger based ranging ISTA role */
WMI_SERVICE_RTT_11AZ_MAC_SEC_SUPPORT = 314, /* FW support for 11AZ secure FTM */
WMI_SERVICE_RTT_11AZ_MAC_PHY_SEC_SUPPORT = 315, /* FW support for 11AZ secure LTF + FTM */
WMI_SERVICE_SPECTRAL_SESSION_INFO_SUPPORT = 316, /* Information corresponding to each Spectral scan session will be sent by the FW before the reports corresponding to that session are sent */
WMI_SERVICE_PDEV_RATE_CONFIG_SUPPORT = 317, /* Support rate configurations per PDEV */
WMI_SERVICE_MLO_STA_NAN_NDI_SUPPORT = 318, /* FW support for NAN and NDP support with MLO STA */
WMI_SERVICE_PROBE_ALL_BW_SUPPORT = 319, /* FW support to probe on higher BW even if the probe fails on lower BW - IOT issue */
WMI_SERVICE_PKTLOG_DECODE_INFO_SUPPORT = 320, /* FW supports embedding Pktlog decode info in the Pktlog trace file level header */
WMI_SERVICE_PNO_SCAN_CONFIG_PER_CHANNEL = 321, /* Indicates that FW supports per channel configuration support in the PNO scan start command */
WMI_SERVICE_MULTIPLE_PEER_GROUP_CMD_SUPPORT = 322, /* FW support for multiple peer group command */
WMI_SERVICE_AFC_RESET_SUPPORT = 323, /* Indicates FW supports AFC reset */
WMI_SERVICE_FP_PHY_ERR_FILTER_SUPPORT = 324, /* FW supports monitor ring configurations for filtering in PHY error packets */
WMI_IS_RADAR_FOUND_CHAN_FREQ_IS_CENTER_FREQ = 325, /* FW Supporting radar event on the actual center frequency radar was detected */
WMI_SERVICE_BIOS_SAR_SUPPORT = 326, /* FW support for SAR parameter stored in BIOS */
WMI_SERVICE_REO_QREF_SUPPORT = 327, /* FW supports REO QREF */
WMI_SERVICE_DELETE_ALL_PEER_BITMAP_SUPPORT = 328, /* target supports cmd to delete all specific peer type within a vdev */
WMI_SERVICE_PN_REPLAY_CHECK_SUPPORT = 329, /* FW support to check RX mgmt frames has invalid PN in packets */
WMI_SERVICE_COMBINED_SET_PARAM_SUPPORT = 330, /* FW Supporting set param cmd combined for multiple params */
WMI_SERVICE_PDEV_RSSI_DBM_CONV_EVENT_SUPPORT = 331, /* FW supports advertising RSSI dB to dBm conversion params to host via WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID */
WMI_SERVICE_PDEV_TELEMETRY_STATS_SUPPORT = 332,
WMI_SERVICE_ROAM_STAT_PER_CANDIDATE_FRAME_INFO_SUPPORT = 333, /* FW supports to send frame info for each candidate in roam stat */
WMI_SERVICE_HW_TX_POWER_CAPS_SIGNED_SUPPORT = 334, /* Indicates FW supports updating of Tx power capabilities as signed value */
WMI_SERVICE_MULTI_CLIENT_LL_SUPPORT = 335, /* FW supports set param cmd combined for multiple params */
WMI_SERVICE_AFC_PAYLOAD_CLEAR_SUPPORT = 336, /* FW supports clearing the AFC response payload in proxy mode */
WMI_SERVICE_FW_INI_PARSE_SUPPORT = 337, /* FW supports parsing ini configuration file */
WMI_SERVICE_TDLS_6GHZ_SUPPORT = 338, /* FW supports 6GHz TDLS both on base channel and offchannel */
WMI_SERVICE_LINKSPEED_ROAM_TRIGGER_SUPPORT = 339, /* FW supports linkspeed trigger roam */
WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT = 340, /* FW supports recovering system from UMAC hang condition */
WMI_SERVICE_COAP_OFFLOAD_SUPPORT = 341, /* FW supports CoAP (the Constrained Application Protocol) offload */
WMI_SERVICE_TDLS_WIDEBAND_SUPPORT = 342, /* FW supports Wideband TDLS */
WMI_SERVICE_FEATURE_SET_EVENT_SUPPORT = 343, /* FW supports sending of supported feature set event during init time */
WMI_SERVICE_HALPHY_CTRL_PATH_STATS = 344, /* HALPHY STATS through control path */
WMI_SERVICE_PEER_CHWIDTH_PUNCTURE_BITMAP_SUPPORT = 345, /* FW supports puncture bitmap change with channel width switch */
WMI_SERVICE_BANG_RADAR_320_SUPPORT = 346, /* Host to send frequency offset for bang radar in extended field for 320M support */
WMI_SERVICE_XGAP_SUPPORT = 347, /* FW support for XGAP */
WMI_SERVICE_OBSS_PER_PACKET_SR_SUPPORT = 348, /* Spatial Reuse support for per PPDU setting */
WMI_SERVICE_MULTIPLE_VDEV_RESTART_BITMAP_SUPPORT = 349, /* Extended Multiple VDEV Restart with Bitmap Support */
WMI_SERVICE_WMI_SERVICE_WPA3_SHA384_ROAM_SUPPORT = 350, /* Indicates FW supports WPA3 SHA384 roaming */
WMI_SERVICE_ODD_LIVEDUMP_SUPPORT = 351, /* Support for ODD Livedump from the FW */
WMI_SERVICE_EIRP_PREFERRED_SUPPORT = 352, /* Support for OOBE feature where only EIRP powers will be sent in 6 GHz TPC WMI */
WMI_SERVICE_RTT_TX_RX_CHAIN_IDX_SUPPORT = 353, /* FW Supports configuring Tx and Rx Chainmask in intiator and Responder */
WMI_SERVICE_RESTRICTED_TWT = 354, /* Support for R-TWT feature */
WMI_SERVICE_SLO_SUPPORTED = 355, /* Support for Single Link 11BE */
WMI_SERVICE_RTT_11AZ_TB_RSTA_SUPPORT = 356, /* FW support for 11AZ trigger based ranging Responder (RSTA) role */
WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357,
WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */
WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */
WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */
WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */
WMI_SERVICE_PRE_RX_TO = 362, /* Support for Pre RX timeout */
WMI_SERVICE_TDLS_CONCURRENCY_SUPPORT = 363, /* Support for TDLS concurrency in FW */
WMI_SERVICE_SELF_MLD_ROAM_BETWEEN_DBS_AND_HBS = 364, /* Suppport roam between DBS(2G+5G/6G) to HBS(5G+6G) with self AP MLD. */
WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */
WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */
WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */
WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */
WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */
WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */
WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */
WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */
WMI_SERVICE_RF_PATH_SEL_INIT_SUPPORT = 373, /* FW supports RF Path selection using WMI Init command field */
WMI_SERVICE_VDEV_PARAM_CHWIDTH_WITH_NOTIFY_SUPPORT = 374, /* FW supports VDEV param channel width switch with OMN/OMI notification */
WMI_SERVICE_RESTRICTED_TWT_REQUESTER = 375, /* Indicates FW supports Restricted TWT REQUESTER */
WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */
WMI_SERVICE_AUX_MAC_SUPPORT = 377,
WMI_SERVICE_NAN_PAIRING_PEER_CREATE_BY_HOST = 378, /* Indicate FW supports creation of PASN Peer by Host for NAN pairing usecase */
WMI_SERVICE_MLO_TID_TO_LINK_MAPPING_SUPPORT = 379, /* Indicates FW supports TID-TO-LINK mapping */
WMI_SERVICE_PER_LINK_STATS_SUPPORT = 380, /* Indicates FW supports per link stats for MLO */
WMI_SERVICE_N_LINK_MLO_SUPPORT = 381, /* Indicate FW supports N MLO link & vdev re-purpose between links */
WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */
WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */
WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */
WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */
WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */
WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */
WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */
WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */
WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */
WMI_SERVICE_XPAN_SUPPORT = 391, /* Indicate FW support XPAN configuration */
WMI_SERVICE_5GHZ_HI_RSSI_ROAM_SUPPORT = 392, /* Indicate FW supports High RSSI Roam from 5 GHz Band to 6 GHz Band */
WMI_SERVICE_BOTH_PSD_EIRP_FOR_AP_SP_CLIENT_SP_SUPPORT = 393, /* Support for CTL regeneration where both PSD and EIRP will be sent in 6GHZ SET_TPC WMI for SP and SP_CLIENT power modes */
WMI_SERVICE_PDEV_PARAM_IN_UTF_WMI = 394, /* FW supports receiving and sending pdev_id parameter in WMI_PDEV_UTF_(CMD/EVENT) */
WMI_SERVICE_SW_PROG_DFS_SUPPORT = 395, /* Indicate FW support SW progressive DFS */
WMI_SERVICE_MULTIPLE_REORDER_QUEUE_SETUP_SUPPORT = 396, /* Indicate FW supports multiple TID reorder queues setup in one cmd */
WMI_SERVICE_MULTIPLE_COEX_CONFIG_SUPPORT = 397, /* FW supports mutiple coex configs in one cmd */
WMI_SERVICE_PCIE_DATA_RATE_LED_BLINK_SUPPORT = 398, /* FW supports Data Rate based LED blinking for PCI chips */
WMI_SERVICE_VDEV_DCS_STATS_SUPPORT = 399, /* FW supports VDEV level DCS stats reporting */
WMI_SERVICE_WIFI_RADAR_SUPPORT = 400, /* FW supports wifi radar */
WMI_SERVICE_P2P_DEVICE_UPDATE_MAC_ADDR_SUPPORT = 401, /* indicate FW support dynamic update mac address for P2P device */
WMI_SERVICE_DCS_OBSS_INT_SUPPORT = 402, /* Indicates FW supports OBSS Interference detection */
WMI_SERVICE_DYNAMIC_WSI_REMAP_SUPPORT = 403, /* WSI bypass remap is supported by Firmware */
WMI_SERVICE_QMS_DLKM_SUPPORT = 404, /* DEPRECATED */
WMI_SERVICE_SMEM_MAILBOX_SUPPORT = 404, /* FW code has smem_mailbox support enabled */
WMI_SERVICE_REG_CC_EXT2_EVENT_SUPPORT = 405, /* DEPRECATED */
WMI_SERVICE_MLO_MODE2_RECOVERY_SUPPORTED = 406, /* Indicate FW support for MLO mode2 recovery */
WMI_SERVICE_MSDUQ_RECFG = 407, /* FW support the HTT MSDUQ_RECFG_REQ + MSDUQ_CFG_IND messages */
WMI_SERVICE_TRAFFIC_CONTEXT_SUPPORT = 408, /* FW supports traffic context aware manager */
WMI_SERVICE_STA_SAP_NDP_CONCURRENCY_SUPPORT = 409, /* FW supports STA + SAP + NDP concurrency */
WMI_SERVICE_THERM_THROT_POUT_REDUCTION = 410, /* FW supports thermal throttling Pout reduction */
WMI_SERVICE_E2E_SDWF_SUPPORT = 411, /* FW supports end-to-end SDWF features like SDWF scheduler */
WMI_SERVICE_EPM = 412, /* FW supports enhanced power management */
WMI_SERVICE_CHIPSET_LOGGING_SUPPORT = 413, /* FW supports chipset logging feature */
WMI_SERVICE_SUPPORT_AP_SUSPEND_RESUME = 414, /* FW supports SAP suspend feature */
WMI_SERVICE_STA_P2P_NDP_CONCURRENCY_SUPPORT = 415, /* FW supports STA + P2P + NAN concurrency */
WMI_SERVICE_USE_STA_VDEV_FOR_P2P_DEVICE = 416, /* FW supports use of sta vdev to be repurposed for p2p device */
WMI_SERVICE_AP_ASSISTED_DFS_CHAN_P2P_SESSION = 417, /* FW supports P2P session on DFS chan enabled by DFS master AP */
WMI_SERVICE_MLO_SAP_EMLSR_SUPPORT = 418, /* Indicates FW MLO SAP supports EMLSR Mode */
WMI_SERVICE_PKTLOG_ML_TSTMP_SUPPORT = 419, /* Indicates ML timestamp for pktlog */
WMI_SERVICE_MGMT_SRNG_SUPPORT = 420, /* FW supports MGMT frame forwarding via host provided SRNG instead of WMI */
WMI_SERVICE_WDS_NULL_FRAME_SUPPORT = 421,
WMI_SERVICE_MLO_SAP_CONCURRENCY_SUPPORT = 422, /* Indicates FW supports MLO SAP+STA Concurrency */
WMI_SERVICE_MEC_AGING_TIMER_SUPPORT = 423, /* FW supports multicast echo check aging timer */
WMI_SERVICE_MULTI_RSNO_SUPPORT = 424, /* FW supports parsing of multiple RSN override IEs */
/* WMI_SERVICE_IS_TARGET_IPA:
* FW indicates to host whether the target is IPA or xFEM.
* If this flag is 0, the target is XFEM or unspecified.
* If this flag is 1, the target is IPA.
*/
WMI_SERVICE_IS_TARGET_IPA = 425,
WMI_SERVICE_THERM_THROT_TX_CHAIN_MASK = 426, /*FW supports thermal throttling dynamic Tx ChainMask update */
WMI_SERVICE_SPLIT_PHY_PDEV_SUSPEND_RESUME_SUPPORT = 427, /* Indicates FW support pdev suspend/resume in split-phy radio */
WMI_MAX_EXT2_SERVICE
} WMI_SERVICE;
#define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(A_UINT32)- 1)/sizeof(A_UINT32))
#define WMI_NUM_EXT_SERVICES (WMI_MAX_EXT_SERVICE - WMI_MAX_SERVICE)
#define WMI_NUM_EXT2_SERVICES (WMI_MAX_EXT2_SERVICE - WMI_MAX_EXT_SERVICE)
/*
* TEMPORARY WORKAROUND
* Virtually all branches of the target utilize an incorrect check on
* the value of WMI_SERVICE_EXT_BM_SIZE32, checking that
* WMI_SERVICE_EXT_BM_SIZE32 < 4, rather than WMI_SERVICE_EXT_BM_SIZE32 <= 4.
* Until all target branches are fixed, this check is being disabled
* by artificially setting WMI_SERVICE_EXT_BM_SIZE32 to 0, rather than
* the number of 4-byte words required for holding the WMI extension
* service flags.
*/
#if 0
#define WMI_SERVICE_EXT_BM_SIZE32 ((WMI_NUM_EXT_SERVICES + 31) / 32)
#else
#define WMI_SERVICE_EXT_BM_SIZE32 0
#endif
#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD /* depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help compiling with old host driver */
/*
* turn on the WMI service bit corresponding to the WMI service.
*/
#define WMI_SERVICE_ENABLE(pwmi_svc_bmap,svc_id) \
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \
((A_UINT32) 1 << ((svc_id)%(sizeof(A_UINT32)))) )
#define WMI_SERVICE_DISABLE(pwmi_svc_bmap,svc_id) \
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &= \
( ~((A_UINT32) 1 << ((svc_id)%(sizeof(A_UINT32)))) ) )
#define WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap,svc_id) \
( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] & \
((A_UINT32) 1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)
#define WMI_SERVICE_EXT_ENABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] |= ((A_UINT32) 1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT_DISABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] &= ~((A_UINT32) 1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT_IS_ENABLED(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
/* If the service ID is beyond the known limit, treat it as disabled */ \
((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \
/* If service ID is in the non-extension range, use the old check */ \
(svc_id) < WMI_MAX_SERVICE ? \
WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \
/* If service ID is in the extended range, check ext_bmap */ \
(((pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \
((svc_id) & 0x1f)) & 0x1))
#define WMI_SERVICE_EXT2_ENABLE( \
pwmi_svc_bmap, pwmi_svc_ext_bmap, pwmi_svc_ext2_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \
} else if (svc_id < WMI_MAX_EXT_SERVICE) { \
WMI_SERVICE_EXT_ENABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_EXT_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext2_bmap)[word] |= ((A_UINT32) 1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT2_DISABLE( \
pwmi_svc_bmap, pwmi_svc_ext_bmap, pwmi_svc_ext2_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \
} else if (svc_id < WMI_MAX_EXT_SERVICE) { \
WMI_SERVICE_EXT_DISABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_EXT_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext2_bmap)[word] &= ~((A_UINT32) 1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT2_IS_ENABLED( \
pwmi_svc_bmap, pwmi_svc_ext_bmap, pwmi_svc_ext2_bmap, svc_id) \
/* If the service ID is beyond the known limit, treat it as disabled */ \
((svc_id) >= WMI_MAX_EXT2_SERVICE ? 0 : \
/* If service ID is in the non-extension range, use the old check */ \
(svc_id) < WMI_MAX_SERVICE ? \
WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \
/* If service ID is in the 1st extended range, check ext_bmap */ \
(svc_id) < WMI_MAX_EXT_SERVICE ? \
WMI_SERVICE_EXT_IS_ENABLED( \
pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) : \
/* \
* If service ID is in the 2nd extended range, check ext2_bmap \
*/ \
(((pwmi_svc_ext2_bmap)[((svc_id) - WMI_MAX_EXT_SERVICE) / 32] >> \
((svc_id) & 0x1f)) & 0x1))
#ifdef __cplusplus
}
#endif
#endif /*_WMI_SERVICES_H_*/

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/*
* Copyright (c) 2012-2017 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WMI_TLV_HELPER_H_
#define _WMI_TLV_HELPER_H_
/*
* Every command or event parameter structure will need a TLV definition.
* The macro WMITLV_TABLE is used to help build this TLV definition. Inside this macro define, the
* individual TLV's are specified. The parameters for WMITLV_ELEM are:
* (1) the list of parameters that are passed unchanged from the WMITLV_TABLE. Currently, they are id,op,buf,len
* (2) The TLV Tag. You should create a new tag for each cmd/event in WMITLV_TAG_ID. The name of the
* tag is <WMI_TLVTAG_STRUC_><CMD or Event ID name>. There are special tags,
* e.g. WMI_TLVTAG_ARRAY_UINT32 and WMI_TLVTAG_ARRAY_STRUC. WMI_TLVTAG_ARRAY_UINT32 is for a
* variable size array of UINT32 elements. WMI_TLVTAG_ARRAY_STRUC is for a varialbe size array
* of structures.
* (3) type of the TLV. For WMI_TLVTAG_ARRAY_* tag, then it is the type of each element.
* (4) Name of this TLV. It must be unique in this TLV TABLE.
* (5) Either WMITLV_SIZE_FIX or WMITLV_SIZE_VAR to indicate if this TLV is variable size.
*
* Note: It is important that the last TLV_ELEM does not have the "\" character.
*/
/* Size of the TLV Header which is the Tag and Length fields */
#define WMI_TLV_HDR_SIZE (1 * sizeof(A_UINT32))
/** TLV Helper macro to get the TLV Header given the pointer
* to the TLV buffer. */
#define WMITLV_GET_HDR(tlv_buf) (((A_UINT32 *)(tlv_buf))[0])
/** TLV Helper macro to set the TLV Header given the pointer
* to the TLV buffer. */
#define WMITLV_SET_HDR(tlv_buf, tag, len) (((A_UINT32 *)(tlv_buf))[0]) = ((tag << 16) | (len & 0x0000FFFF))
/** TLV Helper macro to get the TLV Tag given the TLV header. */
#define WMITLV_GET_TLVTAG(tlv_header) ((A_UINT32)((tlv_header)>>16))
/** TLV Helper macro to get the TLV Buffer Length (minus TLV
* header size) given the TLV header. */
#define WMITLV_GET_TLVLEN(tlv_header) ((A_UINT32)((tlv_header) & 0x0000FFFF))
/** TLV Helper macro to get the TLV length from TLV structure size by removing TLV header size */
#define WMITLV_GET_STRUCT_TLVLEN(tlv_struct) ((A_UINT32)(sizeof(tlv_struct)-WMI_TLV_HDR_SIZE))
/* Indicates whether the TLV is fixed size or variable length */
#define WMITLV_SIZE_FIX 0
#define WMITLV_SIZE_VAR 1
typedef struct {
A_UINT32 tag_order;
A_UINT32 tag_id;
A_UINT32 tag_struct_size;
A_UINT32 tag_varied_size;
A_UINT32 tag_array_size;
A_UINT32 cmd_num_tlv;
} wmitlv_attributes_struc;
/* Template structure definition for a variable size array of UINT32 */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */
A_UINT32 uint32_array[1]; /* variable length Array of UINT32 */
} wmitlv_array_uint32;
/* Template structure definition for a variable size array of unknown structure */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */
A_UINT32 struc_array[1]; /* variable length Array of structures */
} wmitlv_array_struc;
/*
* Used to fill in the "arr_size" parameter when it is not specified and hence, invalid. Can be used to
* indicate if the original TLV definition specify this fixed array size.
*/
#define WMITLV_ARR_SIZE_INVALID 0x1FE
#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id) \
WMI_TLV_HLPR_NUM_TLVS_FOR_##wmi_cmd_event_id
void
wmitlv_set_static_param_tlv_buf(void *param_tlv_buf, A_UINT32 max_tlvs_accomodated);
void
wmitlv_set_static_param_tlv_buf_ext(void *param_tlv_buf, A_UINT32 max_tlvs_accomodated, A_UINT32 indx);
void
wmitlv_free_allocated_command_tlvs(
A_UINT32 cmd_id,
void **wmi_cmd_struct_ptr);
void
wmitlv_free_allocated_event_tlvs(
A_UINT32 event_id,
void **wmi_cmd_struct_ptr);
int
wmitlv_check_command_tlv_params(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id);
int
wmitlv_check_event_tlv_params(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id);
int
wmitlv_check_and_pad_command_tlvs(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr);
int
wmitlv_check_and_pad_event_tlvs(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr);
/** This structure is the element for the Version WhiteList
* table. */
typedef struct {
A_UINT32 major;
A_UINT32 minor;
A_UINT32 namespace_0;
A_UINT32 namespace_1;
A_UINT32 namespace_2;
A_UINT32 namespace_3;
} wmi_whitelist_version_info;
struct _wmi_abi_version; /* Forward declaration to make the ARM compiler happy */
int
wmi_cmp_and_set_abi_version(int num_whitelist, wmi_whitelist_version_info *version_whitelist_table,
struct _wmi_abi_version *my_vers,
struct _wmi_abi_version *opp_vers,
struct _wmi_abi_version *out_vers);
int
wmi_versions_are_compatible(struct _wmi_abi_version *vers1, struct _wmi_abi_version *vers2);
#endif /*_WMI_TLV_HELPER_H_*/

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/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/** @file
* This File provides dummy defs for the vendor-specific message content structs defined in wmi_unified.h.
* Vendor may replace this file wmi_unified_vendor.h with there own vendor defs header file containing the real vendor defs.
**/
#ifndef _WMI_UNIFIED_VENDOR_H_
#define _WMI_UNIFIED_VENDOR_H_
typedef union
{
A_UINT32 pdev_sample1_cmd;
A_UINT32 pdev_sample2_cmd;
} wmi_pdev_vendor_cmd_val;
typedef union
{
A_UINT32 pdev_sample1_event;
A_UINT32 pdev_sample2_event;
} wmi_pdev_vendor_event_val;
typedef union
{
A_UINT32 vdev_sample1_cmd;
A_UINT32 vdev_sample2_cmd;
} wmi_vdev_vendor_cmd_val;
typedef union
{
A_UINT32 vdev_sample1_event;
A_UINT32 vdev_sample2_event;
} wmi_vdev_vendor_event_val;
typedef union
{
A_UINT32 peer_sample1_cmd;
A_UINT32 peer_sample2_cmd;
} wmi_peer_vendor_cmd_val;
typedef union
{
A_UINT32 peer_sample1_event;
A_UINT32 peer_sample2_event;
} wmi_peer_vendor_event_val;
#endif /* _WMI_UNIFIED_VENDOR_H_ */

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/*
* Copyright (c) 2012-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* IMPORTANT NOTE: For all change to WMI Interface, the ABI version number _must_ be updated.
*/
/** Major version number is incremented when there are significant changes to WMI Interface that break compatibility. */
#define __WMI_VER_MAJOR_ 1
/** Minor version number is incremented when there are changes
* (however minor) to WMI Interface that break
* compatibility. */
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
#define __WMI_REVISION_ 1514
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
* together.
* For example, "QCA_ML" converts to 0x4C, 0x4D5F414351.
* where 'Q'=0x51, 'C'=0x43, 'A'=0x41, '_'=0x5F. 'M'=4D, 'L'=4C
*/
#define __NAMESPACE_0_ 0x5F414351
#define __NAMESPACE_1_ 0x00004C4D
#define __NAMESPACE_2_ 0x00000000
#define __NAMESPACE_3_ 0x00000000
/* Format of the version number. */
#define WMI_VER_MAJOR_BIT_OFFSET 24
#define WMI_VER_MINOR_BIT_OFFSET 0
#define WMI_VER_MAJOR_BIT_MASK 0xFF000000
#define WMI_VER_MINOR_BIT_MASK 0x00FFFFFF
/* Macros to extract the sw_version components.
*/
#define WMI_VER_GET_MAJOR(x) (((x) & WMI_VER_MAJOR_BIT_MASK)>>WMI_VER_MAJOR_BIT_OFFSET)
#define WMI_VER_GET_MINOR(x) (((x) & WMI_VER_MINOR_BIT_MASK)>>WMI_VER_MINOR_BIT_OFFSET)
#define WMI_VER_GET_VERSION_0(major, minor) ( (( major << WMI_VER_MAJOR_BIT_OFFSET ) & WMI_VER_MAJOR_BIT_MASK) + (( minor << WMI_VER_MINOR_BIT_OFFSET ) & WMI_VER_MINOR_BIT_MASK) )
/*
* The version has the following format:
* Bits 24-31: Major version
* Bits 0-23: Minor version
* Bits 0-31: Build number
* E.g. Build 1.1.7 would be represented as 0x01000001 for Major/Minor & 0x00000007 for buildnum.
*
* DO NOT split the following macro into multiple lines as this may confuse the build scripts.
*/
/* ABI Version. Reflects the version of binary interface exposed by Target firmware. */
#define WMI_ABI_VERSION_0 WMI_VER_GET_VERSION_0(__WMI_VER_MAJOR_, __WMI_VER_MINOR_)
#define WMI_ABI_VERSION_1 __WMI_REVISION_
#define WMI_ABI_VERSION_NS_0 __NAMESPACE_0_
#define WMI_ABI_VERSION_NS_1 __NAMESPACE_1_
#define WMI_ABI_VERSION_NS_2 __NAMESPACE_2_
#define WMI_ABI_VERSION_NS_3 __NAMESPACE_3_

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/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* This file contains extensions of the WMI protocol specified in the
* Wireless Module Interface (WMI). It includes definitions of all
* extended commands and events. Extensions include useful commands
* that are not directly related to wireless activities. They may
* be hardware-specific, and they might not be supported on all
* implementations.
*
* Extended WMIX commands are encapsulated in a WMI message with
* cmd=WMI_EXTENSION_CMD.
*/
#ifndef _WMIX_H_
#define _WMIX_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Extended WMI commands are those that are needed during wireless
* operation, but which are not really wireless commands. This allows,
* for instance, platform-specific commands. Extended WMI commands are
* embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
* Extended WMI events are similarly embedded in a WMI event message with
* WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
*/
typedef struct {
A_UINT32 commandId;
} POSTPACK WMIX_CMD_HDR;
typedef enum {
WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
WMIX_DSETDATA_REPLY_CMDID,
WMIX_HB_CHALLENGE_RESP_CMDID,
WMIX_DBGLOG_CFG_MODULE_CMDID,
WMIX_PROF_CFG_CMDID, /* 0x200a */
WMIX_PROF_ADDR_SET_CMDID,
WMIX_PROF_START_CMDID,
WMIX_PROF_STOP_CMDID,
WMIX_PROF_COUNT_GET_CMDID,
} WMIX_COMMAND_ID;
typedef enum {
WMIX_DSETOPENREQ_EVENTID = 0x3001,
WMIX_DSETCLOSE_EVENTID,
WMIX_DSETDATAREQ_EVENTID,
WMIX_HB_CHALLENGE_RESP_EVENTID,
WMIX_DBGLOG_EVENTID,
WMIX_PROF_COUNT_EVENTID,
WMIX_PKTLOG_EVENTID,
} WMIX_EVENT_ID;
/*
* =============DataSet support=================
*/
/*
* WMIX_DSETOPENREQ_EVENTID
* DataSet Open Request Event
*/
typedef struct {
A_UINT32 dset_id;
A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} POSTPACK WMIX_DSETOPENREQ_EVENT;
/*
* WMIX_DSETCLOSE_EVENTID
* DataSet Close Event
*/
typedef struct {
A_UINT32 access_cookie;
} POSTPACK WMIX_DSETCLOSE_EVENT;
/*
* WMIX_DSETDATAREQ_EVENTID
* DataSet Data Request Event
*/
typedef struct {
A_UINT32 access_cookie;
A_UINT32 offset;
A_UINT32 length;
A_UINT32 targ_buf; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} WMIX_DSETDATAREQ_EVENT;
typedef struct {
A_UINT32 status;
A_UINT32 targ_dset_handle;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 access_cookie;
A_UINT32 size;
A_UINT32 version;
} WMIX_DSETOPEN_REPLY_CMD;
typedef struct {
A_UINT32 status;
A_UINT32 targ_buf;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 length;
A_UINT8 buf[1];
} WMIX_DSETDATA_REPLY_CMD;
/*
* =============Error Detection support=================
*/
/*
* WMIX_HB_CHALLENGE_RESP_CMDID
* Heartbeat Challenge Response command
*/
typedef struct {
A_UINT32 cookie;
A_UINT32 source;
} WMIX_HB_CHALLENGE_RESP_CMD;
/*
* WMIX_HB_CHALLENGE_RESP_EVENTID
* Heartbeat Challenge Response Event
*/
#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
/*
* =============Target Profiling support=================
*/
typedef struct {
A_UINT32 period; /* Time (in 30.5us ticks) between samples */
A_UINT32 nbins;
} WMIX_PROF_CFG_CMD;
typedef struct {
A_UINT32 addr;
} WMIX_PROF_ADDR_SET_CMD;
/*
* Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
* using a WMIX_PROF_COUNT_EVENT with
* addr set to the next address
* count set to the corresponding count
*/
typedef struct {
A_UINT32 addr;
A_UINT32 count;
} WMIX_PROF_COUNT_EVENT;
#ifdef __cplusplus
}
#endif
#endif /* _WMIX_H_ */

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_COMDEF_H
#define HAL_COMDEF_H
#ifndef _ARM_ASM_
#ifdef __cplusplus
extern "C" {
#endif
#include "com_dtypes.h"
#ifndef _BOOL32_DEFINED
typedef unsigned long int bool32;
#define _BOOL32_DEFINED
#endif
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
#define inp(port) (*((volatile byte *) (port)))
#define inpw(port) (*((volatile word *) (port)))
#define inpdw(port) (*((volatile dword *)(port)))
#define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
#ifdef __cplusplus
}
#endif
#endif
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_HWIO_H
#define HAL_HWIO_H
#include "HALcomdef.h"
#define HWIO_BASE_PTR(base) base##_BASE_PTR
#ifdef __ARMCC_VERSION
#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 * HWIO_BASE_PTR(base)
#else
#define DECLARE_HWIO_BASE_PTR(base) uint8 * HWIO_BASE_PTR(base)
#endif
#ifdef CONFIG_WHAL_MM
#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET
#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET
#endif
#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3))
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4))
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index, val)
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index, val)
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
}
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
}
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
HWIO_##hwiosym##_OUTM(base, mask4, val4); \
}
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
#define HWIO_INTLOCK()
#define HWIO_INTFREE()
#define __inp(port) (*((volatile uint8 *) (port)))
#define __inpw(port) (*((volatile uint16 *) (port)))
#define __inpdw(port) (*((volatile uint32 *) (port)))
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
#ifdef HAL_HWIO_EXTERNAL
#undef __inp
#undef __inpw
#undef __inpdw
#undef __outp
#undef __outpw
#undef __outpdw
#define __inp(port) __inp_extern(port)
#define __inpw(port) __inpw_extern(port)
#define __inpdw(port) __inpdw_extern(port)
#define __outp(port, val) __outp_extern(port, val)
#define __outpw(port, val) __outpw_extern(port, val)
#define __outpdw(port, val) __outpdw_extern(port, val)
extern uint8 __inp_extern(uint32 nAddr);
extern uint16 __inpw_extern(uint32 nAddr);
extern uint32 __inpdw_extern(uint32 nAddr);
extern void __outp_extern(uint32 nAddr, uint8 nData);
extern void __outpw_extern(uint32 nAddr, uint16 nData);
extern void __outpdw_extern(uint32 nAddr, uint32 nData);
#endif
#define in_byte(addr) (__inp(addr))
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
#define out_byte(addr, val) __outp(addr, val)
#define out_byte_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
out_byte(io, shadow); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
HWIO_INTFREE()
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
out_byte(io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))))
#define in_word(addr) (__inpw(addr))
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
#define out_word(addr, val) __outpw(addr, val)
#define out_word_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
out_word(io, shadow); \
HWIO_INTFREE()
#define out_word_masked_ns(io, mask, val, current_reg_content) \
out_word(io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))))
#define in_dword(addr) (__inpdw(addr))
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
#define out_dword(addr, val) __outpdw(addr, val)
#define out_dword_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
out_dword(io, shadow); \
HWIO_INTFREE()
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
out_dword(io, ((current_reg_content & (uint32)(~(mask))) | \
((uint32)((val) & (mask)))))
#endif

29
qcom/opensource/wlan/fw-api/hw/kiwi/v1/beryllium_top_reg.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef BERYLLIUM_TOP_REG_H
#define BERYLLIUM_TOP_REG_H
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
#endif

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qcom/opensource/wlan/fw-api/hw/kiwi/v1/buffer_addr_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BUFFER_ADDR_INFO_H_
#define _BUFFER_ADDR_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
struct buffer_addr_info {
uint32_t buffer_addr_31_0 : 32;
uint32_t buffer_addr_39_32 : 8,
return_buffer_manager : 4,
sw_buffer_cookie : 20;
};
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#endif

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qcom/opensource/wlan/fw-api/hw/kiwi/v1/ce_src_desc.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _CE_SRC_DESC_H_
#define _CE_SRC_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_CE_SRC_DESC 4
struct ce_src_desc {
uint32_t src_buffer_low : 32;
uint32_t src_buffer_high : 8,
toeplitz_en : 1,
src_swap : 1,
dest_swap : 1,
gather : 1,
ce_res_0 : 4,
length : 16;
uint32_t fw_metadata : 16,
ce_res_1 : 16;
uint32_t ce_res_2 : 20,
ring_id : 8,
looping_count : 4;
};
#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000
#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0
#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31
#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff
#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004
#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff
#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004
#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8
#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8
#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100
#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_SRC_SWAP_LSB 9
#define CE_SRC_DESC_SRC_SWAP_MSB 9
#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200
#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_DEST_SWAP_LSB 10
#define CE_SRC_DESC_DEST_SWAP_MSB 10
#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400
#define CE_SRC_DESC_GATHER_OFFSET 0x00000004
#define CE_SRC_DESC_GATHER_LSB 11
#define CE_SRC_DESC_GATHER_MSB 11
#define CE_SRC_DESC_GATHER_MASK 0x00000800
#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004
#define CE_SRC_DESC_CE_RES_0_LSB 12
#define CE_SRC_DESC_CE_RES_0_MSB 15
#define CE_SRC_DESC_CE_RES_0_MASK 0x0000f000
#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004
#define CE_SRC_DESC_LENGTH_LSB 16
#define CE_SRC_DESC_LENGTH_MSB 31
#define CE_SRC_DESC_LENGTH_MASK 0xffff0000
#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008
#define CE_SRC_DESC_FW_METADATA_LSB 0
#define CE_SRC_DESC_FW_METADATA_MSB 15
#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff
#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000008
#define CE_SRC_DESC_CE_RES_1_LSB 16
#define CE_SRC_DESC_CE_RES_1_MSB 31
#define CE_SRC_DESC_CE_RES_1_MASK 0xffff0000
#define CE_SRC_DESC_CE_RES_2_OFFSET 0x0000000c
#define CE_SRC_DESC_CE_RES_2_LSB 0
#define CE_SRC_DESC_CE_RES_2_MSB 19
#define CE_SRC_DESC_CE_RES_2_MASK 0x000fffff
#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c
#define CE_SRC_DESC_RING_ID_LSB 20
#define CE_SRC_DESC_RING_ID_MSB 27
#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000
#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_SRC_DESC_LOOPING_COUNT_LSB 28
#define CE_SRC_DESC_LOOPING_COUNT_MSB 31
#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _CE_STAT_DESC_H_
#define _CE_STAT_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_CE_STAT_DESC 4
struct ce_stat_desc {
uint32_t ce_res_5 : 8,
toeplitz_en : 1,
src_swap : 1,
dest_swap : 1,
gather : 1,
ce_res_6 : 4,
length : 16;
uint32_t toeplitz_hash_0 : 32;
uint32_t toeplitz_hash_1 : 32;
uint32_t fw_metadata : 16,
ce_res_7 : 4,
ring_id : 8,
looping_count : 4;
};
#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000
#define CE_STAT_DESC_CE_RES_5_LSB 0
#define CE_STAT_DESC_CE_RES_5_MSB 7
#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff
#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000
#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8
#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8
#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100
#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_SRC_SWAP_LSB 9
#define CE_STAT_DESC_SRC_SWAP_MSB 9
#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200
#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_DEST_SWAP_LSB 10
#define CE_STAT_DESC_DEST_SWAP_MSB 10
#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400
#define CE_STAT_DESC_GATHER_OFFSET 0x00000000
#define CE_STAT_DESC_GATHER_LSB 11
#define CE_STAT_DESC_GATHER_MSB 11
#define CE_STAT_DESC_GATHER_MASK 0x00000800
#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000
#define CE_STAT_DESC_CE_RES_6_LSB 12
#define CE_STAT_DESC_CE_RES_6_MSB 15
#define CE_STAT_DESC_CE_RES_6_MASK 0x0000f000
#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000
#define CE_STAT_DESC_LENGTH_LSB 16
#define CE_STAT_DESC_LENGTH_MSB 31
#define CE_STAT_DESC_LENGTH_MASK 0xffff0000
#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004
#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff
#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008
#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff
#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c
#define CE_STAT_DESC_FW_METADATA_LSB 0
#define CE_STAT_DESC_FW_METADATA_MSB 15
#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff
#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c
#define CE_STAT_DESC_CE_RES_7_LSB 16
#define CE_STAT_DESC_CE_RES_7_MSB 19
#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000
#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c
#define CE_STAT_DESC_RING_ID_LSB 20
#define CE_STAT_DESC_RING_ID_MSB 27
#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000
#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_STAT_DESC_LOOPING_COUNT_LSB 28
#define CE_STAT_DESC_LOOPING_COUNT_MSB 31
#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000
#endif

217
qcom/opensource/wlan/fw-api/hw/kiwi/v1/com_dtypes.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef COM_DTYPES_H
#define COM_DTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef T_WINNT
#ifndef WIN32
#define WIN32
#endif
#include <stdlib.h>
#endif
#ifdef TRUE
#undef TRUE
#endif
#ifdef FALSE
#undef FALSE
#endif
#define TRUE 1
#define FALSE 0
#define ON 1
#define OFF 0
#ifndef NULL
#define NULL 0
#endif
#ifndef _ARM_ASM_
#ifndef _BOOLEAN_DEFINED
typedef unsigned char boolean;
#define _BOOLEAN_DEFINED
#endif
#if defined(DALSTDDEF_H)
#define _BOOLEAN_DEFINED
#define _UINT32_DEFINED
#define _UINT16_DEFINED
#define _UINT8_DEFINED
#define _INT32_DEFINED
#define _INT16_DEFINED
#define _INT8_DEFINED
#define _UINT64_DEFINED
#define _INT64_DEFINED
#define _BYTE_DEFINED
#endif
#ifndef _UINT32_DEFINED
typedef unsigned long int uint32;
#define _UINT32_DEFINED
#endif
#ifndef _UINT16_DEFINED
typedef unsigned short uint16;
#define _UINT16_DEFINED
#endif
#ifndef _UINT8_DEFINED
typedef unsigned char uint8;
#define _UINT8_DEFINED
#endif
#ifndef _INT32_DEFINED
typedef signed long int int32;
#define _INT32_DEFINED
#endif
#ifndef _INT16_DEFINED
typedef signed short int16;
#define _INT16_DEFINED
#endif
#ifndef _INT8_DEFINED
typedef signed char int8;
#define _INT8_DEFINED
#endif
#ifndef _BYTE_DEFINED
typedef unsigned char byte;
#define _BYTE_DEFINED
#endif
typedef unsigned short word;
typedef unsigned long dword;
typedef unsigned char uint1;
typedef unsigned short uint2;
typedef unsigned long uint4;
typedef signed char int1;
typedef signed short int2;
typedef long int int4;
typedef signed long sint31;
typedef signed short sint15;
typedef signed char sint7;
typedef uint16 UWord16;
typedef uint32 UWord32;
typedef int32 Word32;
typedef int16 Word16;
typedef uint8 UWord8;
typedef int8 Word8;
typedef int32 Vect32;
#if (!defined T_WINNT) && (!defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
#if (defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
typedef __int64 int64;
#ifndef _UINT64_DEFINED
typedef unsigned __int64 uint64;
#define _UINT64_DEFINED
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

241
qcom/opensource/wlan/fw-api/hw/kiwi/v1/he_sig_a_mu_dl_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_MU_DL_INFO_H_
#define _HE_SIG_A_MU_DL_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
struct he_sig_a_mu_dl_info {
uint32_t dl_ul_flag : 1,
mcs_of_sig_b : 3,
dcm_of_sig_b : 1,
bss_color_id : 6,
spatial_reuse : 4,
transmit_bw : 3,
num_sig_b_symbols : 4,
comp_mode_sig_b : 1,
cp_ltf_size : 2,
doppler_indication : 1,
reserved_0a : 6;
uint32_t txop_duration : 7,
reserved_1a : 1,
num_ltf_symbols : 3,
ldpc_extra_symbol : 1,
stbc : 1,
packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
crc : 4,
tail : 6,
reserved_1b : 5,
rx_integrity_check_passed : 1;
};
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800
#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12
#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12
#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16
#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19
#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20
#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25
#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

151
qcom/opensource/wlan/fw-api/hw/kiwi/v1/he_sig_a_mu_ul_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_MU_UL_INFO_H_
#define _HE_SIG_A_MU_UL_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
struct he_sig_a_mu_ul_info {
uint32_t format_indication : 1,
bss_color_id : 6,
spatial_reuse : 16,
reserved_0a : 1,
transmit_bw : 2,
reserved_0b : 6;
uint32_t txop_duration : 7,
reserved_1a : 9,
crc : 4,
tail : 6,
reserved_1b : 5,
rx_integrity_check_passed : 1;
};
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80
#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16
#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19
#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20
#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25
#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

286
qcom/opensource/wlan/fw-api/hw/kiwi/v1/he_sig_a_su_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_SU_INFO_H_
#define _HE_SIG_A_SU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
struct he_sig_a_su_info {
uint32_t format_indication : 1,
beam_change : 1,
dl_ul_flag : 1,
transmit_mcs : 4,
dcm : 1,
bss_color_id : 6,
reserved_0a : 1,
spatial_reuse : 4,
transmit_bw : 2,
cp_ltf_size : 2,
nsts : 3,
reserved_0b : 6;
uint32_t txop_duration : 7,
coding : 1,
ldpc_extra_symbol : 1,
stbc : 1,
txbf : 1,
packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
reserved_1a : 1,
doppler_indication : 1,
crc : 4,
tail : 6,
dot11ax_su_extended : 1,
dot11ax_ext_ru_size : 3,
rx_ndp : 1,
rx_integrity_check_passed : 1;
};
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078
#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_DCM_LSB 7
#define HE_SIG_A_SU_INFO_DCM_MSB 7
#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00
#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14
#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14
#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000
#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_NSTS_LSB 23
#define HE_SIG_A_SU_INFO_NSTS_MSB 25
#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000
#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26
#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31
#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000
#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_CODING_LSB 7
#define HE_SIG_A_SU_INFO_CODING_MSB 7
#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100
#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_STBC_LSB 9
#define HE_SIG_A_SU_INFO_STBC_MSB 9
#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200
#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TXBF_LSB 10
#define HE_SIG_A_SU_INFO_TXBF_MSB 10
#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14
#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14
#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000
#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_CRC_LSB 16
#define HE_SIG_A_SU_INFO_CRC_MSB 19
#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TAIL_LSB 20
#define HE_SIG_A_SU_INFO_TAIL_MSB 25
#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30
#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30
#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

70
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B1_MU_INFO_H_
#define _HE_SIG_B1_MU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
struct he_sig_b1_mu_info {
uint32_t ru_allocation : 8,
reserved_0 : 23,
rx_integrity_check_passed : 1;
};
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff
#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8
#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30
#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

133
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B2_MU_INFO_H_
#define _HE_SIG_B2_MU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
struct he_sig_b2_mu_info {
uint32_t sta_id : 11,
sta_spatial_config : 4,
sta_mcs : 4,
reserved_set_to_1 : 1,
sta_coding : 1,
reserved_0a : 7,
nsts : 3,
rx_integrity_check_passed : 1;
uint32_t user_order : 8,
reserved_1a : 24;
};
#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0
#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10
#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800
#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15
#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18
#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000
#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20
#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20
#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000
#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000
#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_NSTS_LSB 28
#define HE_SIG_B2_MU_INFO_NSTS_MSB 30
#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004
#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0
#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7
#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff
#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 8
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffffff00
#endif

133
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B2_OFDMA_INFO_H_
#define _HE_SIG_B2_OFDMA_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
struct he_sig_b2_ofdma_info {
uint32_t sta_id : 11,
nsts : 3,
txbf : 1,
sta_mcs : 4,
sta_dcm : 1,
sta_coding : 1,
reserved_0 : 10,
rx_integrity_check_passed : 1;
uint32_t user_order : 8,
reserved_1a : 24;
};
#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff
#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11
#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13
#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800
#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14
#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14
#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 8
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffffff00
#endif

187
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HT_SIG_INFO_H_
#define _HT_SIG_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HT_SIG_INFO 2
struct ht_sig_info {
uint32_t mcs : 7,
cbw : 1,
length : 16,
reserved_0 : 8;
uint32_t smoothing : 1,
not_sounding : 1,
ht_reserved : 1,
aggregation : 1,
stbc : 2,
fec_coding : 1,
short_gi : 1,
num_ext_sp_str : 2,
crc : 8,
signal_tail : 6,
reserved_1 : 7,
rx_integrity_check_passed : 1;
};
#define HT_SIG_INFO_MCS_OFFSET 0x00000000
#define HT_SIG_INFO_MCS_LSB 0
#define HT_SIG_INFO_MCS_MSB 6
#define HT_SIG_INFO_MCS_MASK 0x0000007f
#define HT_SIG_INFO_CBW_OFFSET 0x00000000
#define HT_SIG_INFO_CBW_LSB 7
#define HT_SIG_INFO_CBW_MSB 7
#define HT_SIG_INFO_CBW_MASK 0x00000080
#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000
#define HT_SIG_INFO_LENGTH_LSB 8
#define HT_SIG_INFO_LENGTH_MSB 23
#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00
#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000
#define HT_SIG_INFO_RESERVED_0_LSB 24
#define HT_SIG_INFO_RESERVED_0_MSB 31
#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000
#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004
#define HT_SIG_INFO_SMOOTHING_LSB 0
#define HT_SIG_INFO_SMOOTHING_MSB 0
#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001
#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004
#define HT_SIG_INFO_NOT_SOUNDING_LSB 1
#define HT_SIG_INFO_NOT_SOUNDING_MSB 1
#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002
#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004
#define HT_SIG_INFO_HT_RESERVED_LSB 2
#define HT_SIG_INFO_HT_RESERVED_MSB 2
#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004
#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004
#define HT_SIG_INFO_AGGREGATION_LSB 3
#define HT_SIG_INFO_AGGREGATION_MSB 3
#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008
#define HT_SIG_INFO_STBC_OFFSET 0x00000004
#define HT_SIG_INFO_STBC_LSB 4
#define HT_SIG_INFO_STBC_MSB 5
#define HT_SIG_INFO_STBC_MASK 0x00000030
#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004
#define HT_SIG_INFO_FEC_CODING_LSB 6
#define HT_SIG_INFO_FEC_CODING_MSB 6
#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040
#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004
#define HT_SIG_INFO_SHORT_GI_LSB 7
#define HT_SIG_INFO_SHORT_GI_MSB 7
#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080
#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004
#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8
#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9
#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300
#define HT_SIG_INFO_CRC_OFFSET 0x00000004
#define HT_SIG_INFO_CRC_LSB 10
#define HT_SIG_INFO_CRC_MSB 17
#define HT_SIG_INFO_CRC_MASK 0x0003fc00
#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004
#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18
#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23
#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000
#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004
#define HT_SIG_INFO_RESERVED_1_LSB 24
#define HT_SIG_INFO_RESERVED_1_MSB 30
#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

124
qcom/opensource/wlan/fw-api/hw/kiwi/v1/l_sig_a_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _L_SIG_A_INFO_H_
#define _L_SIG_A_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_L_SIG_A_INFO 1
struct l_sig_a_info {
uint32_t rate : 4,
lsig_reserved : 1,
length : 12,
parity : 1,
tail : 6,
pkt_type : 4,
captured_implicit_sounding : 1,
reserved : 2,
rx_integrity_check_passed : 1;
};
#define L_SIG_A_INFO_RATE_OFFSET 0x00000000
#define L_SIG_A_INFO_RATE_LSB 0
#define L_SIG_A_INFO_RATE_MSB 3
#define L_SIG_A_INFO_RATE_MASK 0x0000000f
#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4
#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4
#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010
#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000
#define L_SIG_A_INFO_LENGTH_LSB 5
#define L_SIG_A_INFO_LENGTH_MSB 16
#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0
#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000
#define L_SIG_A_INFO_PARITY_LSB 17
#define L_SIG_A_INFO_PARITY_MSB 17
#define L_SIG_A_INFO_PARITY_MASK 0x00020000
#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000
#define L_SIG_A_INFO_TAIL_LSB 18
#define L_SIG_A_INFO_TAIL_MSB 23
#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000
#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000
#define L_SIG_A_INFO_PKT_TYPE_LSB 24
#define L_SIG_A_INFO_PKT_TYPE_MSB 27
#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_RESERVED_LSB 29
#define L_SIG_A_INFO_RESERVED_MSB 30
#define L_SIG_A_INFO_RESERVED_MASK 0x60000000
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

79
qcom/opensource/wlan/fw-api/hw/kiwi/v1/l_sig_b_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _L_SIG_B_INFO_H_
#define _L_SIG_B_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_L_SIG_B_INFO 1
struct l_sig_b_info {
uint32_t rate : 4,
length : 12,
reserved : 15,
rx_integrity_check_passed : 1;
};
#define L_SIG_B_INFO_RATE_OFFSET 0x00000000
#define L_SIG_B_INFO_RATE_LSB 0
#define L_SIG_B_INFO_RATE_MSB 3
#define L_SIG_B_INFO_RATE_MASK 0x0000000f
#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000
#define L_SIG_B_INFO_LENGTH_LSB 4
#define L_SIG_B_INFO_LENGTH_MSB 15
#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0
#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000
#define L_SIG_B_INFO_RESERVED_LSB 16
#define L_SIG_B_INFO_RESERVED_MSB 30
#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

61
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACRX_ABORT_REQUEST_INFO_H_
#define _MACRX_ABORT_REQUEST_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
struct macrx_abort_request_info {
uint16_t macrx_abort_reason : 8,
reserved_0 : 8;
};
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __MSMHWIOBASE_H__
#define __MSMHWIOBASE_H__
#define WCSS_WCSS_BASE 0x00000000
#define WCSS_WCSS_BASE_SIZE 0x01000000
#define WCSS_WCSS_BASE_PHYS 0x00000000
#define QDSS_STM_SIZE_BASE 0x00100000
#define QDSS_STM_SIZE_BASE_SIZE 0x100000000
#define QDSS_STM_SIZE_BASE_PHYS 0x00100000
#define BOOT_ROM_SIZE_BASE 0x00200000
#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000
#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000
#define SYSTEM_IRAM_SIZE_BASE 0x00400000
#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000
#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000
#define BOOT_ROM_START_ADDRESS_BASE 0x01200000
#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000
#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000
#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff
#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000
#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff
#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000
#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000
#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000
#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff
#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000
#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff
#define QDSS_STM_BASE 0x01800000
#define QDSS_STM_BASE_SIZE 0x100000000
#define QDSS_STM_BASE_PHYS 0x01800000
#define QDSS_STM_END_BASE 0x018fffff
#define QDSS_STM_END_BASE_SIZE 0x100000000
#define QDSS_STM_END_BASE_PHYS 0x018fffff
#define TLMM_BASE 0x01900000
#define TLMM_BASE_SIZE 0x00200000
#define TLMM_BASE_PHYS 0x01900000
#define CORE_TOP_CSR_BASE 0x01b00000
#define CORE_TOP_CSR_BASE_SIZE 0x00040000
#define CORE_TOP_CSR_BASE_PHYS 0x01b00000
#define BLSP1_BLSP_BASE 0x01b40000
#define BLSP1_BLSP_BASE_SIZE 0x00040000
#define BLSP1_BLSP_BASE_PHYS 0x01b40000
#define SOC_WFSS_CE_REG_BASE 0x01b80000
#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000
#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000
#define WL_TLMM_BASE 0x01bc0000
#define WL_TLMM_BASE_SIZE 0x00020000
#define WL_TLMM_BASE_PHYS 0x01bc0000
#define MEMSS_CSR_BASE 0x01be0000
#define MEMSS_CSR_BASE_SIZE 0x0000001c
#define MEMSS_CSR_BASE_PHYS 0x01be0000
#define TSENS_SROT_BASE 0x01bf0000
#define TSENS_SROT_BASE_SIZE 0x00001000
#define TSENS_SROT_BASE_PHYS 0x01bf0000
#define TSENS_TM_BASE 0x01bf1000
#define TSENS_TM_BASE_SIZE 0x00001000
#define TSENS_TM_BASE_PHYS 0x01bf1000
#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000
#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000
#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000
#define QDSS_WRAPPER_TOP_BASE 0x01c80000
#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd
#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000
#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000
#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000
#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000
#define SECURITY_CONTROL_WLAN_BASE 0x01e20000
#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000
#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000
#define EDPD_CAL_ACC_BASE 0x01e28000
#define EDPD_CAL_ACC_BASE_SIZE 0x00003000
#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000
#define CPR_CX_CPR3_BASE 0x01e30000
#define CPR_CX_CPR3_BASE_SIZE 0x00004000
#define CPR_CX_CPR3_BASE_PHYS 0x01e30000
#define CPR_MX_CPR3_BASE 0x01e34000
#define CPR_MX_CPR3_BASE_SIZE 0x00004000
#define CPR_MX_CPR3_BASE_PHYS 0x01e34000
#define GCC_GCC_BASE 0x01e40000
#define GCC_GCC_BASE_SIZE 0x000003e8
#define GCC_GCC_BASE_PHYS 0x01e40000
#define PRNG_PRNG_TOP_BASE 0x01e50000
#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000
#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000
#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000
#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000
#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000
#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000
#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000
#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000
#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000
#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000
#define RRI_PREFETCH_REG_BASE 0x01e70000
#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000
#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000
#define SYSTEM_NOC_BASE 0x01e80000
#define SYSTEM_NOC_BASE_SIZE 0x0000a000
#define SYSTEM_NOC_BASE_PHYS 0x01e80000
#define PC_NOC_BASE 0x01f00000
#define PC_NOC_BASE_SIZE 0x00003880
#define PC_NOC_BASE_PHYS 0x01f00000
#define WLAON_WL_AON_REG_BASE 0x01f80000
#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8
#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000
#define SYSPM_SYSPM_REG_BASE 0x01f82000
#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000
#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000
#define PMU_WLAN_PMU_TOP_BASE 0x01f88000
#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340
#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000
#define PMU_NOC_BASE 0x01f8a000
#define PMU_NOC_BASE_SIZE 0x00000080
#define PMU_NOC_BASE_PHYS 0x01f8a000
#define PCIE_ATU_REGION_BASE 0x04000000
#define PCIE_ATU_REGION_BASE_SIZE 0x100000000
#define PCIE_ATU_REGION_BASE_PHYS 0x04000000
#define PCIE_ATU_REGION_SIZE_BASE 0x40000000
#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000
#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000
#define PCIE_ATU_REGION_END_BASE 0x43ffffff
#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000
#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __MSMHWIOREG_H__
#define __MSMHWIOREG_H__
#include "msmhwiobase.h"
#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc
#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2
#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m, v, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m, v, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m, v, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m, v, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400)
#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m, v, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m, v, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058)
#endif

88
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_abort_request_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
#define _PHYRX_ABORT_REQUEST_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
struct phyrx_abort_request_info {
uint32_t phyrx_abort_reason : 8,
phy_enters_nap_state : 1,
phy_enters_defer_state : 1,
reserved_0 : 6,
receive_duration : 16;
};
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000
#endif

216
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_common_user_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_COMMON_USER_INFO_H_
#define _PHYRX_COMMON_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2
struct phyrx_common_user_info {
uint32_t receive_duration : 16,
reserved_0a : 16;
uint32_t u_sig_puncture_pattern_encoding : 6,
reserved_1a : 26;
uint32_t eht_ppdu_type : 2,
bss_color_id : 6,
dl_ul_flag : 1,
txop_duration : 7,
cp_setting : 2,
ltf_size : 2,
spatial_reuse : 4,
rx_ndp : 1,
dot11be_su_extended : 1,
reserved_2a : 6;
uint32_t eht_duplicate : 2,
eht_sig_cmn_field_type : 2,
doppler_indication : 1,
sta_id : 11,
puncture_bitmap : 16;
};
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 38
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 63
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0xffffffc000000000
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x0000000000000003
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00
#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000
#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24
#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24
#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x0000000002000000
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 34
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 35
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000
#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37
#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47
#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000
#endif

226
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_he_sig_a_mu_dl.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
#define _PHYRX_HE_SIG_A_MU_DL_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_mu_dl_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1
struct phyrx_he_sig_a_mu_dl {
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
};
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

146
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_he_sig_a_mu_ul.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
#define _PHYRX_HE_SIG_A_MU_UL_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_mu_ul_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1
struct phyrx_he_sig_a_mu_ul {
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
};
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

266
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_he_sig_a_su.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_SU_H_
#define _PHYRX_HE_SIG_A_SU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_su_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1
struct phyrx_he_sig_a_su {
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
};
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

83
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_he_sig_b1_mu.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B1_MU_H_
#define _PHYRX_HE_SIG_B1_MU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b1_mu_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
struct phyrx_he_sig_b1_mu {
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
uint32_t tlv64_padding : 32;
};
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
#endif

130
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_he_sig_b2_mu.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B2_MU_H_
#define _PHYRX_HE_SIG_B2_MU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b2_mu_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1
struct phyrx_he_sig_b2_mu {
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
};
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 40
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffffff0000000000
#endif

130
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_he_sig_b2_ofdma.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
#define _PHYRX_HE_SIG_B2_OFDMA_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b2_ofdma_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1
struct phyrx_he_sig_b2_ofdma {
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
};
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 40
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffffff0000000000
#endif

178
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_ht_sig.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HT_SIG_H_
#define _PHYRX_HT_SIG_H_
#if !defined(__ASSEMBLER__)
#endif
#include "ht_sig_info.h"
#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
#define NUM_OF_QWORDS_PHYRX_HT_SIG 1
struct phyrx_ht_sig {
struct ht_sig_info phyrx_ht_sig_info_details;
};
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

131
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_l_sig_a.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_L_SIG_A_H_
#define _PHYRX_L_SIG_A_H_
#if !defined(__ASSEMBLER__)
#endif
#include "l_sig_a_info.h"
#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2
#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1
struct phyrx_l_sig_a {
struct l_sig_a_info phyrx_l_sig_a_info_details;
uint32_t tlv64_padding : 32;
};
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32
#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63
#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000
#endif

91
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_l_sig_b.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_L_SIG_B_H_
#define _PHYRX_L_SIG_B_H_
#if !defined(__ASSEMBLER__)
#endif
#include "l_sig_b_info.h"
#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2
#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1
struct phyrx_l_sig_b {
struct l_sig_b_info phyrx_l_sig_b_info_details;
uint32_t tlv64_padding : 32;
};
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32
#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63
#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000
#endif

554
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_location.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_LOCATION_H_
#define _PHYRX_LOCATION_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_location_info.h"
#define NUM_OF_DWORDS_PHYRX_LOCATION 28
#define NUM_OF_QWORDS_PHYRX_LOCATION 14
struct phyrx_location {
struct rx_location_info rx_location_info_details;
};
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x000000000000000c
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000
#endif

81
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_other_receive_info_ru_details.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4
#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2
struct phyrx_other_receive_info_ru_details {
uint32_t ru_details_channel_0 : 32;
uint32_t ru_details_channel_1 : 32;
uint32_t spare : 32;
uint32_t tlv64_padding : 32;
};
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000
#endif

704
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_pkt_end.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_PKT_END_H_
#define _PHYRX_PKT_END_H_
#if !defined(__ASSEMBLER__)
#endif
#include "phyrx_pkt_end_info.h"
#define NUM_OF_DWORDS_PHYRX_PKT_END 24
#define NUM_OF_QWORDS_PHYRX_PKT_END 12
struct phyrx_pkt_end {
struct phyrx_pkt_end_info rx_pkt_end_details;
};
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x0000000000000001
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000
#endif

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qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_pkt_end_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_PKT_END_INFO_H_
#define _PHYRX_PKT_END_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#include "receive_rssi_info.h"
#include "rx_timing_offset_info.h"
#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
struct phyrx_pkt_end_info {
uint32_t phy_internal_nap : 1,
location_info_valid : 1,
timing_info_valid : 1,
rssi_info_valid : 1,
reserved_0a : 1,
frameless_frame_received : 1,
reserved_0b : 2,
rssi_comb : 8,
reserved_0c : 16;
uint32_t phy_timestamp_1_lower_32 : 32;
uint32_t phy_timestamp_1_upper_32 : 32;
uint32_t phy_timestamp_2_lower_32 : 32;
uint32_t phy_timestamp_2_upper_32 : 32;
struct rx_timing_offset_info rx_timing_offset_info_details;
struct receive_rssi_info post_rssi_info_details;
uint32_t phy_sw_status_31_0 : 32;
uint32_t phy_sw_status_63_32 : 32;
};
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_LSB 0
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MSB 0
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MASK 0x00000001
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008
#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4
#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4
#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6
#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7
#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0
#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8
#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15
#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16
#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31
#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff
#endif

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qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_rssi_legacy.h Normal file
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qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_user_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_USER_INFO_H_
#define _PHYRX_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#include "receive_user_info.h"
#define NUM_OF_DWORDS_PHYRX_USER_INFO 12
#define NUM_OF_QWORDS_PHYRX_USER_INFO 6
struct phyrx_user_info {
struct receive_user_info receive_user_info_details;
};
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 38
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x000000c000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_OFFSET 0x0000000000000010
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_OFFSET 0x0000000000000010
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_MASK 0xffffffff00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_OFFSET 0x0000000000000018
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_OFFSET 0x0000000000000018
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_MASK 0xffffffff00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_OFFSET 0x0000000000000020
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_OFFSET 0x0000000000000020
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_MASK 0xffffffff00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_OFFSET 0x0000000000000028
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_OFFSET 0x0000000000000028
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_MASK 0xffffffff00000000
#endif

194
qcom/opensource/wlan/fw-api/hw/kiwi/v1/phyrx_vht_sig_a.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_VHT_SIG_A_H_
#define _PHYRX_VHT_SIG_A_H_
#if !defined(__ASSEMBLER__)
#endif
#include "vht_sig_a_info.h"
#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1
struct phyrx_vht_sig_a {
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
};
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

619
qcom/opensource/wlan/fw-api/hw/kiwi/v1/receive_rssi_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RECEIVE_RSSI_INFO_H_
#define _RECEIVE_RSSI_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
struct receive_rssi_info {
uint32_t rssi_pri20_chain0 : 8,
rssi_ext20_chain0 : 8,
rssi_ext40_low20_chain0 : 8,
rssi_ext40_high20_chain0 : 8;
uint32_t rssi_ext80_low20_chain0 : 8,
rssi_ext80_low_high20_chain0 : 8,
rssi_ext80_high_low20_chain0 : 8,
rssi_ext80_high20_chain0 : 8;
uint32_t rssi_ext160_0_chain0 : 8,
rssi_ext160_1_chain0 : 8,
rssi_ext160_2_chain0 : 8,
rssi_ext160_3_chain0 : 8;
uint32_t rssi_ext160_4_chain0 : 8,
rssi_ext160_5_chain0 : 8,
rssi_ext160_6_chain0 : 8,
rssi_ext160_7_chain0 : 8;
uint32_t rssi_pri20_chain1 : 8,
rssi_ext20_chain1 : 8,
rssi_ext40_low20_chain1 : 8,
rssi_ext40_high20_chain1 : 8;
uint32_t rssi_ext80_low20_chain1 : 8,
rssi_ext80_low_high20_chain1 : 8,
rssi_ext80_high_low20_chain1 : 8,
rssi_ext80_high20_chain1 : 8;
uint32_t rssi_ext160_0_chain1 : 8,
rssi_ext160_1_chain1 : 8,
rssi_ext160_2_chain1 : 8,
rssi_ext160_3_chain1 : 8;
uint32_t rssi_ext160_4_chain1 : 8,
rssi_ext160_5_chain1 : 8,
rssi_ext160_6_chain1 : 8,
rssi_ext160_7_chain1 : 8;
uint32_t rssi_pri20_chain2 : 8,
rssi_ext20_chain2 : 8,
rssi_ext40_low20_chain2 : 8,
rssi_ext40_high20_chain2 : 8;
uint32_t rssi_ext80_low20_chain2 : 8,
rssi_ext80_low_high20_chain2 : 8,
rssi_ext80_high_low20_chain2 : 8,
rssi_ext80_high20_chain2 : 8;
uint32_t rssi_ext160_0_chain2 : 8,
rssi_ext160_1_chain2 : 8,
rssi_ext160_2_chain2 : 8,
rssi_ext160_3_chain2 : 8;
uint32_t rssi_ext160_4_chain2 : 8,
rssi_ext160_5_chain2 : 8,
rssi_ext160_6_chain2 : 8,
rssi_ext160_7_chain2 : 8;
uint32_t rssi_pri20_chain3 : 8,
rssi_ext20_chain3 : 8,
rssi_ext40_low20_chain3 : 8,
rssi_ext40_high20_chain3 : 8;
uint32_t rssi_ext80_low20_chain3 : 8,
rssi_ext80_low_high20_chain3 : 8,
rssi_ext80_high_low20_chain3 : 8,
rssi_ext80_high20_chain3 : 8;
uint32_t rssi_ext160_0_chain3 : 8,
rssi_ext160_1_chain3 : 8,
rssi_ext160_2_chain3 : 8,
rssi_ext160_3_chain3 : 8;
uint32_t rssi_ext160_4_chain3 : 8,
rssi_ext160_5_chain3 : 8,
rssi_ext160_6_chain3 : 8,
rssi_ext160_7_chain3 : 8;
};
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RECEIVE_USER_INFO_H_
#define _RECEIVE_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RECEIVE_USER_INFO 12
struct receive_user_info {
uint32_t phy_ppdu_id : 16,
user_rssi : 8,
pkt_type : 4,
stbc : 1,
reception_type : 3;
uint32_t rate_mcs : 4,
sgi : 2,
reserved_1a : 2,
mimo_ss_bitmap : 8,
receive_bandwidth : 3,
reserved_1b : 5,
dl_ofdma_user_index : 8;
uint32_t dl_ofdma_content_channel : 1,
reserved_2a : 7,
nss : 3,
stream_offset : 3,
sta_dcm : 1,
ldpc : 1,
ru_type_80_0 : 4,
ru_type_80_1 : 4,
ru_type_80_2 : 4,
ru_type_80_3 : 4;
uint32_t ru_start_index_80_0 : 6,
reserved_3a : 2,
ru_start_index_80_1 : 6,
reserved_3b : 2,
ru_start_index_80_2 : 6,
reserved_3c : 2,
ru_start_index_80_3 : 6,
reserved_3d : 2;
uint32_t user_fd_rssi_ss0 : 32;
uint32_t user_fd_rssi_ss1 : 32;
uint32_t user_fd_rssi_ss2 : 32;
uint32_t user_fd_rssi_ss3 : 32;
uint32_t user_fd_rssi_ss4 : 32;
uint32_t user_fd_rssi_ss5 : 32;
uint32_t user_fd_rssi_ss6 : 32;
uint32_t user_fd_rssi_ss7 : 32;
};
#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000
#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff
#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000
#define RECEIVE_USER_INFO_USER_RSSI_LSB 16
#define RECEIVE_USER_INFO_USER_RSSI_MSB 23
#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000
#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24
#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27
#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000
#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000
#define RECEIVE_USER_INFO_STBC_LSB 28
#define RECEIVE_USER_INFO_STBC_MSB 28
#define RECEIVE_USER_INFO_STBC_MASK 0x10000000
#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000
#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RATE_MCS_LSB 0
#define RECEIVE_USER_INFO_RATE_MCS_MSB 3
#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f
#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004
#define RECEIVE_USER_INFO_SGI_LSB 4
#define RECEIVE_USER_INFO_SGI_MSB 5
#define RECEIVE_USER_INFO_SGI_MASK 0x00000030
#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RESERVED_1A_LSB 6
#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7
#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x000000c0
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000
#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19
#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23
#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1
#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7
#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe
#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008
#define RECEIVE_USER_INFO_NSS_LSB 8
#define RECEIVE_USER_INFO_NSS_MSB 10
#define RECEIVE_USER_INFO_NSS_MASK 0x00000700
#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008
#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11
#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13
#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800
#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008
#define RECEIVE_USER_INFO_STA_DCM_LSB 14
#define RECEIVE_USER_INFO_STA_DCM_MSB 14
#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000
#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008
#define RECEIVE_USER_INFO_LDPC_LSB 15
#define RECEIVE_USER_INFO_LDPC_MSB 15
#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000
#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000
#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000
#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000
#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f
#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6
#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7
#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00
#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14
#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15
#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000
#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22
#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23
#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000
#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30
#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31
#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_OFFSET 0x00000010
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_OFFSET 0x00000014
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_OFFSET 0x00000018
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_OFFSET 0x0000001c
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_OFFSET 0x00000020
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_OFFSET 0x00000024
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_OFFSET 0x00000028
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_OFFSET 0x0000002c
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_MASK 0xffffffff
#endif

360
qcom/opensource/wlan/fw-api/hw/kiwi/v1/reo_descriptor_threshold_reached_status.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26
#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13
struct reo_descriptor_threshold_reached_status {
struct uniform_reo_status_header status_header;
uint32_t threshold_index : 2,
reserved_2 : 30;
uint32_t link_descriptor_counter0 : 24,
reserved_3 : 8;
uint32_t link_descriptor_counter1 : 24,
reserved_4 : 8;
uint32_t link_descriptor_counter2 : 24,
reserved_5 : 8;
uint32_t link_descriptor_counter_sum : 26,
reserved_6 : 6;
uint32_t reserved_7 : 32;
uint32_t reserved_8 : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

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qcom/opensource/wlan/fw-api/hw/kiwi/v1/reo_destination_ring.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_DESTINATION_RING_H_
#define _REO_DESTINATION_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_msdu_desc_info.h"
#include "rx_mpdu_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
struct reo_destination_ring {
struct buffer_addr_info buf_or_link_desc_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t reo_dest_buffer_type : 1,
reo_push_reason : 2,
reo_error_code : 5,
captured_msdu_data_size : 4,
sw_exception : 1,
src_link_id : 3,
reo_destination_struct_signature : 4,
ring_id : 8,
looping_count : 4;
};
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_LSB 15
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MSB 22
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MASK 0x007f8000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 23
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 26
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x07800000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001
#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1
#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2
#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006
#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3
#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7
#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c
#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12
#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12
#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000
#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13
#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15
#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_RING_ID_LSB 20
#define REO_DESTINATION_RING_RING_ID_MSB 27
#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000
#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31
#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

339
qcom/opensource/wlan/fw-api/hw/kiwi/v1/reo_destination_ring_with_pn.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_DESTINATION_RING_WITH_PN_H_
#define _REO_DESTINATION_RING_WITH_PN_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_msdu_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
struct reo_destination_ring_with_pn {
struct buffer_addr_info buf_or_link_desc_addr_info;
uint32_t msdu_count : 8,
prev_pn_23_0 : 24;
uint32_t prev_pn_55_24 : 32;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t reo_dest_buffer_type : 1,
reo_push_reason : 2,
reo_error_code : 5,
captured_msdu_data_size : 4,
sw_exception : 1,
src_link_id : 3,
reo_destination_struct_signature : 4,
ring_id : 8,
looping_count : 4;
};
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET 0x0000000c
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB 0
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB 31
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20
#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27
#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000
#endif

370
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_ENTRANCE_RING_H_
#define _REO_ENTRANCE_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_mpdu_details.h"
#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
struct reo_entrance_ring {
struct rx_mpdu_details reo_level_mpdu_frame_info;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
rounded_mpdu_byte_count : 14,
reo_destination_indication : 5,
frameless_bar : 1,
reserved_5a : 4;
uint32_t rxdma_push_reason : 2,
rxdma_error_code : 5,
mpdu_fragment_number : 4,
sw_exception : 1,
sw_exception_mpdu_delink : 1,
sw_exception_destination_ring_valid : 1,
sw_exception_destination_ring : 5,
mpdu_sequence_number : 12,
reserved_6a : 1;
uint32_t phy_ppdu_id : 16,
src_link_id : 3,
reserved_7a : 1,
ring_id : 8,
looping_count : 4;
};
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_LSB 15
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MSB 22
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MASK 0x007f8000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 23
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 26
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x07800000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000
#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014
#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000
#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014
#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28
#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31
#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11
#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11
#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000
#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018
#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31
#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31
#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000
#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff
#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16
#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18
#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000
#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19
#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19
#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000
#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_RING_ID_LSB 20
#define REO_ENTRANCE_RING_RING_ID_MSB 27
#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000
#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28
#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31
#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

227
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_CACHE_H_
#define _REO_FLUSH_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
struct reo_flush_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_addr_31_0 : 32;
uint32_t flush_addr_39_32 : 8,
forward_all_mpdus_in_queue : 1,
release_cache_block_index : 1,
cache_block_resource_index : 2,
flush_without_invalidate : 1,
block_cache_usage_after_flush : 1,
flush_entire_cache : 1,
flush_queue_1k_desc : 1,
reserved_2b : 16;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000
#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16
#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31
#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000
#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32
#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63
#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

396
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_CACHE_STATUS_H_
#define _REO_FLUSH_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13
struct reo_flush_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
block_error_details : 2,
reserved_2a : 5,
cache_controller_flush_status_hit : 1,
cache_controller_flush_status_desc_type : 3,
cache_controller_flush_status_client_id : 4,
cache_controller_flush_status_error : 2,
cache_controller_flush_count : 8,
flush_queue_1k_desc : 1,
reserved_2b : 5;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

191
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_QUEUE_H_
#define _REO_FLUSH_QUEUE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
struct reo_flush_queue {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_desc_addr_31_0 : 32;
uint32_t flush_desc_addr_39_32 : 8,
block_desc_addr_usage_after_flush : 1,
block_resource_index : 2,
invalidate_queue_and_flush : 1,
reserved_2a : 20;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_LSB 11
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_MSB 11
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x0000000000000800
#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 12
#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff000
#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32
#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63
#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

324
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_QUEUE_STATUS_H_
#define _REO_FLUSH_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13
struct reo_flush_queue_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
reserved_2a : 31;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

173
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
#define _REO_FLUSH_TIMEOUT_LIST_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
struct reo_flush_timeout_list {
struct uniform_reo_cmd_header cmd_header;
uint32_t ac_timout_list : 2,
reserved_1 : 30;
uint32_t minimum_release_desc_count : 16,
minimum_forward_buf_count : 16;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000
#endif

342
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13
struct reo_flush_timeout_list_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
timout_list_empty : 1,
reserved_2a : 30;
uint32_t release_desc_count : 16,
forward_buf_count : 16;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_GET_QUEUE_STATS_H_
#define _REO_GET_QUEUE_STATS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10
#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5
struct reo_get_queue_stats {
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
clear_stats : 1,
reserved_2a : 23;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8
#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8
#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100
#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9
#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00
#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32
#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63
#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
#define _REO_GET_QUEUE_STATS_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26
#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13
struct reo_get_queue_stats_status {
struct uniform_reo_status_header status_header;
uint32_t ssn : 12,
current_index : 10,
reserved_2 : 10;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t last_rx_enqueue_timestamp : 32;
uint32_t last_rx_dequeue_timestamp : 32;
uint32_t rx_bitmap_31_0 : 32;
uint32_t rx_bitmap_63_32 : 32;
uint32_t rx_bitmap_95_64 : 32;
uint32_t rx_bitmap_127_96 : 32;
uint32_t rx_bitmap_159_128 : 32;
uint32_t rx_bitmap_191_160 : 32;
uint32_t rx_bitmap_223_192 : 32;
uint32_t rx_bitmap_255_224 : 32;
uint32_t rx_bitmap_287_256 : 32;
uint32_t current_mpdu_count : 7,
current_msdu_count : 25;
uint32_t window_jump_2k : 4,
timeout_count : 6,
forward_due_to_bar_count : 6,
duplicate_count : 16;
uint32_t frames_in_order_count : 24,
bar_received_count : 8;
uint32_t mpdu_frames_processed_count : 32;
uint32_t msdu_frames_processed_count : 32;
uint32_t total_processed_byte_count : 32;
uint32_t late_receive_mpdu_count : 12,
hole_count : 16,
get_queue_1k_stats_status_to_follow : 1,
reserved_24a : 3;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11
#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x0000000000000fff
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x00000000003ff000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0x00000000ffc00000
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000000000000028
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x0000000000000028
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x0000000000000030
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x0000000000000030
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000000000000038
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x0000000000000038
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x0000000000000040
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x0000000000000040
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x000000000000007f
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0x00000000ffffff80
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 35
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f00000000
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 36
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 41
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f000000000
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 42
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 47
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc0000000000
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 48
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff000000000000
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x0000000000ffffff
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0x00000000ff000000
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000058
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000000000000058
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x0000000000000fff
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x000000000ffff000
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x0000000010000000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0x00000000e0000000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 59
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 60
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

173
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UNBLOCK_CACHE_H_
#define _REO_UNBLOCK_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10
#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5
struct reo_unblock_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t unblock_type : 1,
cache_block_resource_index : 2,
reserved_1a : 29;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000
#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35
#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000
#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32
#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63
#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

333
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
#define _REO_UNBLOCK_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26
#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13
struct reo_unblock_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
unblock_type : 1,
reserved_2a : 30;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

569
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
#define _REO_UPDATE_RX_REO_QUEUE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10
#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5
struct reo_update_rx_reo_queue {
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
update_receive_queue_number : 1,
update_vld : 1,
update_associated_link_descriptor_counter : 1,
update_disable_duplicate_detection : 1,
update_soft_reorder_enable : 1,
update_ac : 1,
update_bar : 1,
update_rty : 1,
update_chk_2k_mode : 1,
update_oor_mode : 1,
update_ba_window_size : 1,
update_pn_check_needed : 1,
update_pn_shall_be_even : 1,
update_pn_shall_be_uneven : 1,
update_pn_handling_enable : 1,
update_pn_size : 1,
update_ignore_ampdu_flag : 1,
update_svld : 1,
update_ssn : 1,
update_seq_2k_error_detected_flag : 1,
update_pn_error_detected_flag : 1,
update_pn_valid : 1,
update_pn : 1,
clear_stat_counters : 1;
uint32_t receive_queue_number : 16,
vld : 1,
associated_link_descriptor_counter : 2,
disable_duplicate_detection : 1,
soft_reorder_enable : 1,
ac : 2,
bar : 1,
rty : 1,
chk_2k_mode : 1,
oor_mode : 1,
pn_check_needed : 1,
pn_shall_be_even : 1,
pn_shall_be_uneven : 1,
pn_handling_enable : 1,
ignore_ampdu_flag : 1;
uint32_t ba_window_size : 10,
pn_size : 2,
svld : 1,
ssn : 12,
seq_2k_error_detected_flag : 1,
pn_error_detected_flag : 1,
pn_valid : 1,
flush_from_cache : 1,
reserved_4a : 3;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t tlv64_padding : 32;
};
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000
#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48
#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48
#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000
#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53
#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54
#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000
#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55
#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55
#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000
#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56
#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56
#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00
#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000
#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13
#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24
#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

315
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26
#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13
struct reo_update_rx_reo_queue_status {
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

504
qcom/opensource/wlan/fw-api/hw/kiwi/v1/rx_attention.h Normal file
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@ -0,0 +1,504 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_ATTENTION_H_
#define _RX_ATTENTION_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_ATTENTION 4
#define NUM_OF_QWORDS_RX_ATTENTION 2
struct rx_attention {
uint32_t rxpcu_mpdu_filter_in_category : 2,
sw_frame_group_id : 7,
reserved_0 : 7,
phy_ppdu_id : 16;
uint32_t first_mpdu : 1,
reserved_1a : 1,
mcast_bcast : 1,
ast_index_not_found : 1,
ast_index_timeout : 1,
power_mgmt : 1,
non_qos : 1,
null_data : 1,
mgmt_type : 1,
ctrl_type : 1,
more_data : 1,
eosp : 1,
a_msdu_error : 1,
fragment_flag : 1,
order : 1,
cce_match : 1,
overflow_err : 1,
msdu_length_err : 1,
tcp_udp_chksum_fail : 1,
ip_chksum_fail : 1,
sa_idx_invalid : 1,
da_idx_invalid : 1,
reserved_1b : 1,
rx_in_tx_decrypt_byp : 1,
encrypt_required : 1,
directed : 1,
buffer_fragment : 1,
mpdu_length_err : 1,
tkip_mic_err : 1,
decrypt_err : 1,
unencrypted_frame_err : 1,
fcs_err : 1;
uint32_t flow_idx_timeout : 1,
flow_idx_invalid : 1,
wifi_parser_error : 1,
amsdu_parser_error : 1,
sa_idx_timeout : 1,
da_idx_timeout : 1,
msdu_limit_error : 1,
da_is_valid : 1,
da_is_mcbc : 1,
sa_is_valid : 1,
decrypt_status_code : 3,
rx_bitmap_not_updated : 1,
reserved_2 : 17,
msdu_done : 1;
uint32_t tlv64_padding : 32;
};
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2
#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8
#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000
#define RX_ATTENTION_RESERVED_0_LSB 9
#define RX_ATTENTION_RESERVED_0_MSB 15
#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00
#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_ATTENTION_PHY_PPDU_ID_LSB 16
#define RX_ATTENTION_PHY_PPDU_ID_MSB 31
#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000
#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000
#define RX_ATTENTION_FIRST_MPDU_LSB 32
#define RX_ATTENTION_FIRST_MPDU_MSB 32
#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000
#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000
#define RX_ATTENTION_RESERVED_1A_LSB 33
#define RX_ATTENTION_RESERVED_1A_MSB 33
#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000
#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000
#define RX_ATTENTION_MCAST_BCAST_LSB 34
#define RX_ATTENTION_MCAST_BCAST_MSB 34
#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000
#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000
#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36
#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36
#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000
#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000
#define RX_ATTENTION_POWER_MGMT_LSB 37
#define RX_ATTENTION_POWER_MGMT_MSB 37
#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000
#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000
#define RX_ATTENTION_NON_QOS_LSB 38
#define RX_ATTENTION_NON_QOS_MSB 38
#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000
#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000
#define RX_ATTENTION_NULL_DATA_LSB 39
#define RX_ATTENTION_NULL_DATA_MSB 39
#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000
#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000
#define RX_ATTENTION_MGMT_TYPE_LSB 40
#define RX_ATTENTION_MGMT_TYPE_MSB 40
#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000
#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000
#define RX_ATTENTION_CTRL_TYPE_LSB 41
#define RX_ATTENTION_CTRL_TYPE_MSB 41
#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000
#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000
#define RX_ATTENTION_MORE_DATA_LSB 42
#define RX_ATTENTION_MORE_DATA_MSB 42
#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000
#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000
#define RX_ATTENTION_EOSP_LSB 43
#define RX_ATTENTION_EOSP_MSB 43
#define RX_ATTENTION_EOSP_MASK 0x0000080000000000
#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000
#define RX_ATTENTION_A_MSDU_ERROR_LSB 44
#define RX_ATTENTION_A_MSDU_ERROR_MSB 44
#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000
#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000
#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45
#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45
#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000
#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000
#define RX_ATTENTION_ORDER_LSB 46
#define RX_ATTENTION_ORDER_MSB 46
#define RX_ATTENTION_ORDER_MASK 0x0000400000000000
#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000
#define RX_ATTENTION_CCE_MATCH_LSB 47
#define RX_ATTENTION_CCE_MATCH_MSB 47
#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000
#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_OVERFLOW_ERR_LSB 48
#define RX_ATTENTION_OVERFLOW_ERR_MSB 48
#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000
#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49
#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49
#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000
#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000
#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51
#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51
#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000
#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000
#define RX_ATTENTION_SA_IDX_INVALID_LSB 52
#define RX_ATTENTION_SA_IDX_INVALID_MSB 52
#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000
#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000
#define RX_ATTENTION_DA_IDX_INVALID_LSB 53
#define RX_ATTENTION_DA_IDX_INVALID_MSB 53
#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000
#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000
#define RX_ATTENTION_RESERVED_1B_LSB 54
#define RX_ATTENTION_RESERVED_1B_MSB 54
#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000
#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000
#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56
#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56
#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000
#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000
#define RX_ATTENTION_DIRECTED_LSB 57
#define RX_ATTENTION_DIRECTED_MSB 57
#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000
#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000
#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58
#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58
#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000
#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59
#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59
#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000
#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60
#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60
#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000
#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_DECRYPT_ERR_LSB 61
#define RX_ATTENTION_DECRYPT_ERR_MSB 61
#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000
#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_FCS_ERR_LSB 63
#define RX_ATTENTION_FCS_ERR_MSB 63
#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001
#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008
#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1
#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1
#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002
#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008
#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2
#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2
#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004
#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008
#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3
#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3
#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008
#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008
#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4
#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4
#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010
#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008
#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5
#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5
#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020
#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008
#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6
#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6
#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040
#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008
#define RX_ATTENTION_DA_IS_VALID_LSB 7
#define RX_ATTENTION_DA_IS_VALID_MSB 7
#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080
#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008
#define RX_ATTENTION_DA_IS_MCBC_LSB 8
#define RX_ATTENTION_DA_IS_MCBC_MSB 8
#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100
#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008
#define RX_ATTENTION_SA_IS_VALID_LSB 9
#define RX_ATTENTION_SA_IS_VALID_MSB 9
#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200
#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008
#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10
#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12
#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000
#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008
#define RX_ATTENTION_RESERVED_2_LSB 14
#define RX_ATTENTION_RESERVED_2_MSB 30
#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000
#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008
#define RX_ATTENTION_MSDU_DONE_LSB 31
#define RX_ATTENTION_MSDU_DONE_MSB 31
#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000
#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008
#define RX_ATTENTION_TLV64_PADDING_LSB 32
#define RX_ATTENTION_TLV64_PADDING_MSB 63
#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000
#endif

277
qcom/opensource/wlan/fw-api/hw/kiwi/v1/rx_flow_search_entry.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_FLOW_SEARCH_ENTRY_H_
#define _RX_FLOW_SEARCH_ENTRY_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
struct rx_flow_search_entry {
uint32_t src_ip_127_96 : 32;
uint32_t src_ip_95_64 : 32;
uint32_t src_ip_63_32 : 32;
uint32_t src_ip_31_0 : 32;
uint32_t dest_ip_127_96 : 32;
uint32_t dest_ip_95_64 : 32;
uint32_t dest_ip_63_32 : 32;
uint32_t dest_ip_31_0 : 32;
uint32_t src_port : 16,
dest_port : 16;
uint32_t l4_protocol : 8,
valid : 1,
reserved_9 : 14,
use_ppe : 1,
reo_destination_indication : 5,
msdu_drop : 1,
reo_destination_handler : 2;
uint32_t metadata : 32;
uint32_t aggregation_count : 7,
lro_eligible : 1,
msdu_count : 24;
uint32_t msdu_byte_count : 32;
uint32_t timestamp : 32;
uint32_t cumulative_l4_checksum : 16,
cumulative_ip_length : 16;
uint32_t tcp_sequence_number : 32;
};
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff
#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8
#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8
#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 22
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x007ffe00
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000
#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028
#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0
#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31
#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_LSB 0
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_MSB 15
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff
#endif

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qcom/opensource/wlan/fw-api/hw/kiwi/v1/rx_location_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_LOCATION_INFO_H_
#define _RX_LOCATION_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_LOCATION_INFO 28
struct rx_location_info {
uint32_t rx_location_info_valid : 1,
rtt_hw_ifft_mode : 1,
rtt_11az_mode : 2,
reserved_0 : 4,
rtt_num_fac : 8,
rtt_rx_chain_mask : 8,
rtt_num_streams : 8;
uint32_t rtt_first_selected_chain : 8,
rtt_second_selected_chain : 8,
rtt_cfr_status : 8,
rtt_cir_status : 8;
uint32_t rtt_che_buffer_pointer_low32 : 32;
uint32_t rtt_che_buffer_pointer_high8 : 8,
reserved_3 : 8,
rtt_pkt_bw_vht : 4,
rtt_pkt_bw_leg : 4,
rtt_mcs_rate : 8;
uint32_t rtt_cfo_measurement : 16,
rtt_preamble_type : 8,
rtt_gi_type : 8;
uint32_t rx_start_ts : 32;
uint32_t rx_start_ts_upper : 32;
uint32_t rx_end_ts : 32;
uint32_t gain_chain0 : 16,
gain_chain1 : 16;
uint32_t gain_chain2 : 16,
gain_chain3 : 16;
uint32_t gain_report_status : 8,
rtt_timing_backoff_sel : 8,
rtt_fac_combined : 16;
uint32_t rtt_fac_0 : 16,
rtt_fac_1 : 16;
uint32_t rtt_fac_2 : 16,
rtt_fac_3 : 16;
uint32_t rtt_fac_4 : 16,
rtt_fac_5 : 16;
uint32_t rtt_fac_6 : 16,
rtt_fac_7 : 16;
uint32_t rtt_fac_8 : 16,
rtt_fac_9 : 16;
uint32_t rtt_fac_10 : 16,
rtt_fac_11 : 16;
uint32_t rtt_fac_12 : 16,
rtt_fac_13 : 16;
uint32_t rtt_fac_14 : 16,
rtt_fac_15 : 16;
uint32_t rtt_fac_16 : 16,
rtt_fac_17 : 16;
uint32_t rtt_fac_18 : 16,
rtt_fac_19 : 16;
uint32_t rtt_fac_20 : 16,
rtt_fac_21 : 16;
uint32_t rtt_fac_22 : 16,
rtt_fac_23 : 16;
uint32_t rtt_fac_24 : 16,
rtt_fac_25 : 16;
uint32_t rtt_fac_26 : 16,
rtt_fac_27 : 16;
uint32_t rtt_fac_28 : 16,
rtt_fac_29 : 16;
uint32_t rtt_fac_30 : 16,
rtt_fac_31 : 16;
uint32_t reserved_27a : 32;
};
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002
#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2
#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3
#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c
#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000
#define RX_LOCATION_INFO_RESERVED_0_LSB 4
#define RX_LOCATION_INFO_RESERVED_0_MSB 7
#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0
#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8
#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15
#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16
#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23
#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000
#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24
#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31
#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff
#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RESERVED_3_LSB 8
#define RX_LOCATION_INFO_RESERVED_3_MSB 15
#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000
#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24
#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31
#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000
#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010
#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24
#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31
#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000
#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014
#define RX_LOCATION_INFO_RX_START_TS_LSB 0
#define RX_LOCATION_INFO_RX_START_TS_MSB 31
#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff
#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018
#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0
#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31
#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff
#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c
#define RX_LOCATION_INFO_RX_END_TS_LSB 0
#define RX_LOCATION_INFO_RX_END_TS_MSB 31
#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff
#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020
#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0
#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15
#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff
#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020
#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16
#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31
#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000
#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024
#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0
#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15
#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff
#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024
#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16
#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31
#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c
#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c
#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030
#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030
#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034
#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034
#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038
#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038
#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c
#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c
#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040
#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040
#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044
#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044
#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048
#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048
#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c
#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c
#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050
#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050
#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054
#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054
#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058
#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058
#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c
#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c
#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060
#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060
#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064
#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064
#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068
#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068
#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000
#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c
#define RX_LOCATION_INFO_RESERVED_27A_LSB 0
#define RX_LOCATION_INFO_RESERVED_27A_MSB 31
#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff
#endif

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