diff --git a/asoc/codecs/wcd9378/wcd9378-registers.h b/asoc/codecs/wcd9378/wcd9378-registers.h index 91dfa80ab8..ed5b6030e1 100644 --- a/asoc/codecs/wcd9378/wcd9378-registers.h +++ b/asoc/codecs/wcd9378/wcd9378-registers.h @@ -875,6 +875,16 @@ enum { #define WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT 0x02 #define WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT 0x00 +#define WCD9378_CN_MBQ_ENABLE_MASK (0x6000) +#define WCD9378_CN_ENABLE_MASK (0x4000) + +#define WCD9378_FU42_CH_VOL_CH1_MSB (WCD9378_FU42_CH_VOL_CH1 | WCD9378_CN_MBQ_ENABLE_MASK) +#define WCD9378_FU42_CH_VOL_CH1_LSB (WCD9378_FU42_CH_VOL_CH1 | WCD9378_CN_ENABLE_MASK) +#define WCD9378_FU42_CH_VOL_CH2_MSB (WCD9378_FU42_CH_VOL_CH2 | WCD9378_CN_MBQ_ENABLE_MASK) +#define WCD9378_FU42_CH_VOL_CH2_LSB (WCD9378_FU42_CH_VOL_CH2 | WCD9378_CN_ENABLE_MASK) +#define WCD9378_FU42_MUTE_CH1_CN (WCD9378_FU42_MUTE_CH1 | WCD9378_CN_ENABLE_MASK) +#define WCD9378_FU42_MUTE_CH2_CN (WCD9378_FU42_MUTE_CH2 | WCD9378_CN_ENABLE_MASK) + #define SWRS_SCP_BASE_CLK_BASE (0x004d) #define SWRS_SCP_BUSCLOCK_SCALE_BANK0 (0x0062) #define SWRS_SCP_BUSCLOCK_SCALE_BANK1 (0x0072) diff --git a/asoc/codecs/wcd9378/wcd9378-regmap.c b/asoc/codecs/wcd9378/wcd9378-regmap.c index f616788aea..e35701bad2 100644 --- a/asoc/codecs/wcd9378/wcd9378-regmap.c +++ b/asoc/codecs/wcd9378/wcd9378-regmap.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -769,8 +769,14 @@ static struct reg_default wcd9378_defaults[] = { {WCD9378_PDE42_REQ_PS, 0x03}, {WCD9378_FU42_MUTE_CH1, 0x01}, {WCD9378_FU42_MUTE_CH2, 0x01}, + {WCD9378_FU42_MUTE_CH1_CN, 0x01}, + {WCD9378_FU42_MUTE_CH2_CN, 0x01}, {WCD9378_FU42_CH_VOL_CH1, 0xe200}, + {WCD9378_FU42_CH_VOL_CH1_MSB, 0xe2}, + {WCD9378_FU42_CH_VOL_CH1_LSB, 0x00}, {WCD9378_FU42_CH_VOL_CH2, 0xe200}, + {WCD9378_FU42_CH_VOL_CH2_MSB, 0xe2}, + {WCD9378_FU42_CH_VOL_CH2_LSB, 0x00}, {WCD9378_SU43_SELECTOR, 0x01}, {WCD9378_SU45_SELECTOR, 0x01}, {WCD9378_PDE47_REQ_PS, 0x03}, diff --git a/asoc/codecs/wcd9378/wcd9378-tables.c b/asoc/codecs/wcd9378/wcd9378-tables.c index 335424aa89..744e808c79 100644 --- a/asoc/codecs/wcd9378/wcd9378-tables.c +++ b/asoc/codecs/wcd9378/wcd9378-tables.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -767,8 +767,14 @@ const u8 wcd9378_reg_access[] = { [WCD9378_REG(WCD9378_PDE42_REQ_PS)] = RD_WR_REG, [WCD9378_REG(WCD9378_FU42_MUTE_CH1)] = RD_WR_REG, [WCD9378_REG(WCD9378_FU42_MUTE_CH2)] = RD_WR_REG, + [WCD9378_REG(WCD9378_FU42_MUTE_CH1_CN)] = RD_WR_REG, + [WCD9378_REG(WCD9378_FU42_MUTE_CH2_CN)] = RD_WR_REG, [WCD9378_REG(WCD9378_FU42_CH_VOL_CH1)] = RD_WR_REG, + [WCD9378_REG(WCD9378_FU42_CH_VOL_CH1_MSB)] = RD_WR_REG, + [WCD9378_REG(WCD9378_FU42_CH_VOL_CH1_LSB)] = RD_WR_REG, [WCD9378_REG(WCD9378_FU42_CH_VOL_CH2)] = RD_WR_REG, + [WCD9378_REG(WCD9378_FU42_CH_VOL_CH2_MSB)] = RD_WR_REG, + [WCD9378_REG(WCD9378_FU42_CH_VOL_CH2_LSB)] = RD_WR_REG, [WCD9378_REG(WCD9378_SU43_SELECTOR)] = RD_REG, [WCD9378_REG(WCD9378_SU45_SELECTOR)] = RD_REG, [WCD9378_REG(WCD9378_PDE47_REQ_PS)] = RD_WR_REG, diff --git a/asoc/codecs/wcd9378/wcd9378.c b/asoc/codecs/wcd9378/wcd9378.c index 63620e705b..f70052ea0c 100644 --- a/asoc/codecs/wcd9378/wcd9378.c +++ b/asoc/codecs/wcd9378/wcd9378.c @@ -48,8 +48,6 @@ #define PWR_LEVEL_HIFI_VAL 0x02 #define PWR_LEVEL_ULP_VAL 0x03 -#define WCD9378_MBQ_ENABLE_MASK 0x2000 - #define MICB_USAGE_VAL_DISABLE 0x00 #define MICB_USAGE_VAL_PULL_DOWN 0x01 #define MICB_USAGE_VAL_1P2V 0x02 @@ -1914,30 +1912,21 @@ static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component) { struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component); + u8 msb_val = 0, lsb_val = 0; if ((!wcd9378->comp1_enable) && (!wcd9378->comp2_enable)) { - snd_soc_component_update_bits(component, - (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK), - WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK, - wcd9378->hph_gain >> 8); - snd_soc_component_update_bits(component, - WCD9378_FU42_CH_VOL_CH1, - WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK, - wcd9378->hph_gain & 0x00ff); + msb_val = (wcd9378->hph_gain >> 8); + lsb_val = (wcd9378->hph_gain & 0x00ff); - snd_soc_component_update_bits(component, - (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK), - WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK, - wcd9378->hph_gain >> 8); - snd_soc_component_update_bits(component, - WCD9378_FU42_CH_VOL_CH2, - WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK, - wcd9378->hph_gain & 0x00ff); + regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH1_MSB, msb_val); + regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH1_LSB, lsb_val); + + regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH2_MSB, msb_val); + regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH2_LSB, lsb_val); } } - static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -1947,7 +1936,7 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w, snd_soc_component_get_drvdata(component); int power_level, ret = 0; struct swr_device *swr_dev = wcd9378->tx_swr_dev; - u8 scp_commit_val = 0x2; + u8 commit_val = 0x02; dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__, w->name, event); @@ -1956,6 +1945,8 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_PRE_PMU: wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, true); + regmap_write(wcd9378->regmap, WCD9378_CMT_GRP_MASK, 0x02); + if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) { snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7, WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07); @@ -1991,30 +1982,23 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w, /*COMP delay is 9400us*/ usleep_range(9500, 9510); - /*RX0 unmute*/ - snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1, - WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00); - - /*RX1 unmute*/ - snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2, - WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00); + regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH1_CN, 0x00); + regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH2_CN, 0x00); if (wcd9378->sys_usage == SYS_USAGE_10) /*FU23 UNMUTE*/ snd_soc_component_update_bits(component, WCD9378_FU23_MUTE, WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00); - swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val); + swr_write(swr_dev, swr_dev->dev_num, 0x004c, &commit_val); wcd9378_swr_slvdev_datapath_control(wcd9378->dev, RX_PATH, true); break; case SND_SOC_DAPM_POST_PMD: - /*RX0 mute*/ - snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1, - WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01); - /*RX1 mute*/ - snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2, - WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01); + regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH1_CN, 0x01); + regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH2_CN, 0x01); + + swr_write(swr_dev, swr_dev->dev_num, 0x004c, &commit_val); /*TEAR DOWN HPH SEQUENCER*/ snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,