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Merge "asoc: codec: wcd9378: optimize the micbias usage set logic"

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This commit is contained in:
qctecmdr 2024-01-07 02:11:24 -08:00 committed by Gerrit - the friendly Code Review server
commit a30841251b
31 changed files with 13127 additions and 33 deletions
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37
Android.mk
View File

@ -18,10 +18,14 @@ ifeq ($(call is-board-platform-in-list,holi blair),true)
AUDIO_SELECT := CONFIG_SND_SOC_HOLI=m
endif
ifeq ($(call is-board-platform-in-list,pineapple cliffs pitti volcano),true)
ifeq ($(call is-board-platform-in-list,pineapple cliffs volcano),true)
AUDIO_SELECT := CONFIG_SND_SOC_PINEAPPLE=m
endif
ifeq ($(call is-board-platform-in-list,pitti),true)
AUDIO_SELECT := CONFIG_SND_SOC_PITTI=m
endif
ifeq ($(ENABLE_AUDIO_LEGACY_TECHPACK),true)
include $(call all-subdir-makefiles)
LOCAL_PATH := vendor/qcom/opensource/audio-kernel
@ -392,7 +396,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
########################### WCD939x CODEC ################################
ifneq ($(call is-board-platform-in-list, niobe),true)
ifneq ($(call is-board-platform-in-list, niobe pitti),true)
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wcd939x_dlkm.ko
@ -411,6 +415,35 @@ LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
endif
ifeq ($(call is-board-platform-in-list, pitti),true)
###########################################################
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wsa881x_analog_dlkm.ko
LOCAL_MODULE_KBUILD_NAME := asoc/codecs/wsa881x_analog_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
###########################################################
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wcd9378_dlkm.ko
LOCAL_MODULE_KBUILD_NAME := asoc/codecs/wcd9378/wcd9378_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
###########################################################
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wcd9378_slave_dlkm.ko
LOCAL_MODULE_KBUILD_NAME := asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
endif
###########################################################
ifeq ($(AUDIO_DLKM_ENABLE), true)
include $(CLEAR_VARS)

2
BUILD.bazel
View File

@ -46,11 +46,13 @@ ddk_headers(
)
load(":build/pineapple.bzl", "define_pineapple")
load(":build/pitti.bzl", "define_pitti")
load(":build/kalama.bzl", "define_kalama")
load(":build/blair.bzl", "define_blair")
load(":build/niobe.bzl", "define_niobe")
define_kalama()
define_pineapple()
define_pitti()
define_blair()
define_niobe()

77
EnableBazel.mk
View File

@ -38,6 +38,47 @@ LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd939x/wcd939x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list,pitti),true)
LOCAL_MODULE_DDK_BUILD := true
LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_dmic_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_haptics_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa881x_analog_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa883x/wsa883x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa884x/wsa884x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list,blair),true)
LOCAL_MODULE_DDK_BUILD := true
@ -108,3 +149,39 @@ LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list,pitti),true)
LOCAL_MODULE_DDK_BUILD := true
LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_haptics_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa881x_analog_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif

2
Kbuild
View File

@ -1 +1 @@
obj-y := dsp/ ipc/ soc/ asoc/ asoc/codecs/ asoc/codecs/lpass-cdc/ asoc/codecs/bolero/ asoc/codecs/wcd939x/ asoc/codecs/wsa884x/ asoc/codecs/wcd938x/ asoc/codecs/wsa883x/ asoc/codecs/wcd937x/
obj-y := dsp/ ipc/ soc/ asoc/ asoc/codecs/ asoc/codecs/lpass-cdc/ asoc/codecs/bolero/ asoc/codecs/wcd939x/ asoc/codecs/wsa884x/ asoc/codecs/wcd938x/ asoc/codecs/wsa883x/ asoc/codecs/wcd937x/ asoc/codecs/wcd9378/

12
asoc/Kbuild
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@ -81,8 +81,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
@ -206,6 +206,11 @@ ifdef CONFIG_SND_SOC_PINEAPPLE
MACHINE_OBJS += pineapple.o
endif
# for PITTI sound card driver
ifdef CONFIG_SND_SOC_PITTI
MACHINE_OBJS += pineapple.o
endif
# for HOLI sound card driver
ifdef CONFIG_SND_SOC_HOLI
MACHINE_OBJS += holi.o
@ -309,6 +314,9 @@ machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_PINEAPPLE) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_PITTI) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_HOLI) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)

5
asoc/codecs/Kbuild
View File

@ -80,8 +80,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
@ -283,6 +283,7 @@ ifeq ($(KERNEL_BUILD), 1)
obj-y += wcd937x/
obj-y += wcd938x/
obj-y += wcd939x/
obj-y += wcd9378/
obj-y += bolero/
obj-y += lpass-cdc/
obj-y += wsa884x/

4
asoc/codecs/lpass-cdc/Kbuild
View File

@ -43,8 +43,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

125
asoc/codecs/wcd9378/Kbuild Normal file
View File

@ -0,0 +1,125 @@
# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
ifeq ($(CONFIG_ARCH_WAIPIO), y)
include $(AUDIO_ROOT)/config/waipioauto.conf
INCS += -include $(AUDIO_ROOT)/config/waipioautoconf.h
endif
ifeq ($(CONFIG_ARCH_KALAMA), y)
include $(AUDIO_ROOT)/config/kalamaauto.conf
INCS += -include $(AUDIO_ROOT)/config/kalamaautoconf.h
endif
ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi/audio
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ WCD9378 ############
# for WCD9378 Codec
ifdef CONFIG_SND_SOC_WCD9378
WCD9378_OBJS += wcd9378.o
WCD9378_OBJS += wcd9378-regmap.o
WCD9378_OBJS += wcd9378-tables.o
WCD9378_OBJS += wcd9378-mbhc.o
endif
ifdef CONFIG_SND_SOC_WCD9378_SLAVE
WCD9378_SLAVE_OBJS += wcd9378-slave.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
ccflags-y += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
ccflags-y += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
ccflags-y += -Wheader-guard
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_WCD9378) += wcd9378_dlkm.o
wcd9378_dlkm-y := $(WCD9378_OBJS)
obj-$(CONFIG_SND_SOC_WCD9378_SLAVE) += wcd9378_slave_dlkm.o
wcd9378_slave_dlkm-y := $(WCD9378_SLAVE_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

6
asoc/codecs/wcd9378/Makefile Normal file
View File

@ -0,0 +1,6 @@
modules:
$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
modules_install:
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

230
asoc/codecs/wcd9378/internal.h Normal file
View File

@ -0,0 +1,230 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _WCD9378_INTERNAL_H
#define _WCD9378_INTERNAL_H
#include <asoc/wcd-mbhc-v2.h>
#include <asoc/wcd-irq.h>
#include <asoc/wcd-clsh.h>
#include <soc/soundwire.h>
#include "wcd9378-mbhc.h"
#include "wcd9378.h"
#define SWR_SCP_CONTROL 0x44
#define SWR_SCP_HOST_CLK_DIV2_CTL_BANK 0xE0
#define WCD9378_MAX_MICBIAS 3
#define SIM_MIC_NUM 3
/* Convert from vout ctl to micbias voltage in mV */
#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
#define MAX_PORT 8
#define MAX_CH_PER_PORT 8
#define TX_ADC_MAX 3
#define SWR_NUM_PORTS 4
enum {
TX_HDR12 = 0,
TX_HDR34,
TX_HDR_MAX,
};
enum {
SIM_MIC0,
SIM_MIC1,
SIM_MIC2,
SIM_JACK,
MICB_VAL_NUM,
};
extern struct regmap_config wcd9378_regmap_config;
struct codec_port_info {
u32 slave_port_type;
u32 master_port_type;
u32 ch_mask;
u32 num_ch;
u32 ch_rate;
};
enum {
RX_CLK_9P6MHZ,
RX_CLK_12P288MHZ,
RX_CLK_11P2896MHZ,
};
enum {
RX_PATH,
TX_PATH,
};
struct wcd9378_priv {
struct device *dev;
u32 sys_usage;
u32 wcd_mode;
int variant;
struct snd_soc_component *component;
struct device_node *rst_np;
struct regmap *regmap;
bool sjmic_support;
struct swr_device *rx_swr_dev;
struct swr_device *tx_swr_dev;
s32 micb_ref[WCD9378_MAX_MICBIAS];
s32 pullup_ref[WCD9378_MAX_MICBIAS];
u32 micb_sel[SIM_MIC_NUM];
u32 micb_val[MICB_VAL_NUM];
struct device_node *wcd_rst_np;
struct mutex micb_lock;
struct mutex wakeup_lock;
s32 dmic_0_1_clk_cnt;
s32 dmic_2_3_clk_cnt;
s32 dmic_4_5_clk_cnt;
int hdr_en[TX_HDR_MAX];
/* class h specific info */
struct wcd_clsh_cdc_info clsh_info;
/* mbhc module */
struct wcd9378_mbhc *mbhc;
u32 hph_mode;
u16 hph_gain;
u32 rx2_clk_mode;
u32 tx_mode[TX_ADC_MAX];
s32 adc_count;
bool comp1_enable;
bool comp2_enable;
bool va_amic_en;
bool ear_enable;
bool aux_enable;
bool ldoh;
bool bcs_dis;
bool dapm_bias_off;
struct irq_domain *virq;
struct wcd_irq_info irq_info;
u32 rx_clk_cnt;
int num_irq_regs;
/* to track the status */
unsigned long status_mask;
u8 num_tx_ports;
u8 num_rx_ports;
struct codec_port_info
tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
struct codec_port_info
rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
struct swr_port_params tx_port_params[SWR_UC_MAX][SWR_NUM_PORTS];
struct swr_dev_frame_config swr_tx_port_params[SWR_UC_MAX];
struct regulator_bulk_data *supplies;
struct notifier_block nblock;
/* wcd callback to bolero */
void *handle;
int (*update_wcd_event)(void *handle, u16 event, u32 data);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
int (*wakeup)(void *handle, bool enable);
u32 version;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
struct snd_info_entry *variant_entry;
int flyback_cur_det_disable;
int ear_rx_path;
int aux_rx_path;
bool dev_up;
u8 tx_master_ch_map[WCD9378_MAX_SLAVE_CH_TYPES];
bool usbc_hs_status;
/* wcd to swr dmic notification */
bool notify_swr_dmic;
u8 swr_base_clk;
u8 swr_clk_scale;
struct blocking_notifier_head notifier;
};
struct wcd9378_micbias_setting {
u8 ldoh_v;
u32 cfilt1_mv;
u32 micb1_mv;
u32 micb2_mv;
u32 micb3_mv;
u32 micb1_usage_val;
u32 micb2_usage_val;
u32 micb3_usage_val;
u8 bias1_cfilt_sel;
};
struct wcd9378_pdata {
struct device_node *rst_np;
struct device_node *rx_slave;
struct device_node *tx_slave;
struct wcd9378_micbias_setting micbias;
struct cdc_regulator *regulator;
int num_supplies;
};
struct wcd_ctrl_platform_data {
void *handle;
int (*update_wcd_event)(void *handle, u16 event, u32 data);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
enum {
WCD_RX1,
WCD_RX2,
WCD_RX3
};
enum {
/* INTR_CTRL_INT_MASK_0 */
WCD9378_IRQ_MBHC_BUTTON_PRESS_DET = 0,
WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET,
WCD9378_IRQ_MBHC_ELECT_INS_REM_DET,
WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
WCD9378_IRQ_MBHC_SW_DET,
WCD9378_IRQ_HPHR_OCP_INT,
WCD9378_IRQ_HPHR_CNP_INT,
WCD9378_IRQ_HPHL_OCP_INT,
/* INTR_CTRL_INT_MASK_1 */
WCD9378_IRQ_HPHL_CNP_INT,
WCD9378_IRQ_EAR_CNP_INT,
WCD9378_IRQ_EAR_SCD_INT,
WCD9378_IRQ_AUX_CNP_INT,
WCD9378_IRQ_AUX_SCD_INT,
WCD9378_IRQ_HPHL_PDM_WD_INT,
WCD9378_IRQ_HPHR_PDM_WD_INT,
WCD9378_IRQ_AUX_PDM_WD_INT,
/* INTR_CTRL_INT_MASK_2 */
WCD9378_IRQ_LDORT_SCD_INT,
WCD9378_IRQ_MBHC_MOISTURE_INT,
WCD9378_IRQ_HPHL_SURGE_DET_INT,
WCD9378_IRQ_HPHR_SURGE_DET_INT,
WCD9378_IRQ_SAPU_PROT_MODE_CHG,
WCD9378_NUM_IRQS,
};
extern struct wcd9378_mbhc *wcd9378_soc_get_mbhc(
struct snd_soc_component *component);
extern void wcd9378_disable_bcs_before_slow_insert(
struct snd_soc_component *component,
bool bcs_disable);
extern int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
int volt, int micb_num);
extern int wcd9378_get_micb_vout_ctl_val(u32 micb_mv);
extern int wcd9378_micbias_control(struct snd_soc_component *component,
unsigned char tx_path, int req, bool is_dapm);
#endif /* _WCD9378_INTERNAL_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __WCD9378_MBHC_H__
#define __WCD9378_MBHC_H__
#include <asoc/wcd-mbhc-v2.h>
struct wcd9378_mbhc {
struct wcd_mbhc wcd_mbhc;
struct blocking_notifier_head notifier;
struct fw_info *fw_data;
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD9378)
extern int wcd9378_mbhc_init(struct wcd9378_mbhc **mbhc,
struct snd_soc_component *component);
extern void wcd9378_mbhc_hs_detect_exit(struct snd_soc_component *component);
extern int wcd9378_mbhc_hs_detect(struct snd_soc_component *component,
struct wcd_mbhc_config *mbhc_cfg);
extern void wcd9378_mbhc_deinit(struct snd_soc_component *component);
extern void wcd9378_mbhc_ssr_down(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component);
extern int wcd9378_mbhc_post_ssr_init(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component);
extern int wcd9378_mbhc_get_impedance(struct wcd9378_mbhc *wcd9378_mbhc,
uint32_t *zl, uint32_t *zr);
#else
static inline int wcd9378_mbhc_init(struct wcd9378_mbhc **mbhc,
struct snd_soc_component *component)
{
return 0;
}
static inline void wcd9378_mbhc_hs_detect_exit(
struct snd_soc_component *component)
{
}
static inline int wcd9378_mbhc_hs_detect(struct snd_soc_component *component,
struct wcd_mbhc_config *mbhc_cfg)
{
return 0;
}
static inline void wcd9378_mbhc_deinit(struct snd_soc_component *component)
{
}
static inline void wcd9378_mbhc_ssr_down(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component)
{
}
static inline int wcd9378_mbhc_post_ssr_init(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component)
{
return 0;
}
static inline int wcd9378_mbhc_get_impedance(struct wcd9378_mbhc *wcd9378_mbhc,
uint32_t *zl, uint32_t *zr)
{
if (zl)
*zl = 0;
if (zr)
*zr = 0;
return -EINVAL;
}
#endif
#endif /* __WCD9378_MBHC_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef WCD9378_REGISTERS_H
#define WCD9378_REGISTERS_H
enum {
REG_NO_ACCESS,
RD_REG,
WR_REG,
RD_WR_REG,
};
#define WCD9378_BASE 0x3fffffff
#define WCD9378_REG(reg) (((reg & 0x0ff00000) >> 8) | (reg & 0xfff))
#define WCD9378_FUNC0_BASE (WCD9378_BASE+0x01)
#define WCD9378_FUNC_EXT_ID_0 (WCD9378_FUNC0_BASE+0x48)
#define WCD9378_FUNC_EXT_ID_1 (WCD9378_FUNC0_BASE+0x49)
#define WCD9378_FUNC_EXT_VER (WCD9378_FUNC0_BASE+0x50)
#define WCD9378_FUNC_STAT (WCD9378_FUNC0_BASE+0x80000)
#define WCD9378_DEV_MANU_ID_0 (WCD9378_FUNC0_BASE+0x100060)
#define WCD9378_DEV_MANU_ID_1 (WCD9378_FUNC0_BASE+0x100061)
#define WCD9378_DEV_PART_ID_0 (WCD9378_FUNC0_BASE+0x100068)
#define WCD9378_DEV_PART_ID_1 (WCD9378_FUNC0_BASE+0x100069)
#define WCD9378_DEV_VER (WCD9378_FUNC0_BASE+0x100070)
#define WCD9378_A_BASE (WCD9378_BASE+0x180001)
#define WCD9378_ANA_PAGE (WCD9378_A_BASE+0x00)
#define WCD9378_ANA_BIAS (WCD9378_A_BASE+0x01)
#define WCD9378_ANA_RX_SUPPLIES (WCD9378_A_BASE+0x08)
#define WCD9378_ANA_HPH (WCD9378_A_BASE+0x09)
#define WCD9378_ANA_EAR (WCD9378_A_BASE+0x0a)
#define WCD9378_ANA_EAR_COMPANDER_CTL (WCD9378_A_BASE+0x0b)
#define WCD9378_ANA_TX_CH1 (WCD9378_A_BASE+0x0e)
#define WCD9378_ANA_TX_CH2 (WCD9378_A_BASE+0x0f)
#define WCD9378_ANA_TX_CH3 (WCD9378_A_BASE+0x10)
#define WCD9378_ANA_TX_CH3_HPF (WCD9378_A_BASE+0x11)
#define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC (WCD9378_A_BASE+0x12)
#define WCD9378_ANA_MICB3_DSP_EN_LOGIC (WCD9378_A_BASE+0x13)
#define WCD9378_ANA_MBHC_MECH (WCD9378_A_BASE+0x14)
#define WCD9378_ANA_MBHC_ELECT (WCD9378_A_BASE+0x15)
#define WCD9378_ANA_MBHC_ZDET (WCD9378_A_BASE+0x16)
#define WCD9378_ANA_MBHC_RESULT_1 (WCD9378_A_BASE+0x17)
#define WCD9378_ANA_MBHC_RESULT_2 (WCD9378_A_BASE+0x18)
#define WCD9378_ANA_MBHC_RESULT_3 (WCD9378_A_BASE+0x19)
#define WCD9378_ANA_MBHC_BTN0 (WCD9378_A_BASE+0x1a)
#define WCD9378_ANA_MBHC_BTN1 (WCD9378_A_BASE+0x1b)
#define WCD9378_ANA_MBHC_BTN2 (WCD9378_A_BASE+0x1c)
#define WCD9378_ANA_MBHC_BTN3 (WCD9378_A_BASE+0x1d)
#define WCD9378_ANA_MBHC_BTN4 (WCD9378_A_BASE+0x1e)
#define WCD9378_ANA_MBHC_BTN5 (WCD9378_A_BASE+0x1f)
#define WCD9378_ANA_MBHC_BTN6 (WCD9378_A_BASE+0x20)
#define WCD9378_ANA_MBHC_BTN7 (WCD9378_A_BASE+0x21)
#define WCD9378_ANA_MICB1 (WCD9378_A_BASE+0x22)
#define WCD9378_ANA_MICB2 (WCD9378_A_BASE+0x23)
#define WCD9378_ANA_MICB2_RAMP (WCD9378_A_BASE+0x24)
#define WCD9378_ANA_MICB3 (WCD9378_A_BASE+0x25)
#define WCD9378_BIAS_CTL (WCD9378_A_BASE+0x28)
#define WCD9378_BIAS_VBG_FINE_ADJ (WCD9378_A_BASE+0x29)
#define WCD9378_LDOL_VDDCX_ADJUST (WCD9378_A_BASE+0x40)
#define WCD9378_LDOL_DISABLE_LDOL (WCD9378_A_BASE+0x41)
#define WCD9378_MBHC_CTL_CLK (WCD9378_A_BASE+0x56)
#define WCD9378_MBHC_CTL_ANA (WCD9378_A_BASE+0x57)
#define WCD9378_MBHC_CTL_SPARE_1 (WCD9378_A_BASE+0x58)
#define WCD9378_MBHC_CTL_SPARE_2 (WCD9378_A_BASE+0x59)
#define WCD9378_MBHC_CTL_BCS (WCD9378_A_BASE+0x5a)
#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS (WCD9378_A_BASE+0x5b)
#define WCD9378_MBHC_TEST_CTL (WCD9378_A_BASE+0x5c)
#define WCD9378_LDOH_MODE (WCD9378_A_BASE+0x67)
#define WCD9378_LDOH_BIAS (WCD9378_A_BASE+0x68)
#define WCD9378_LDOH_STB_LOADS (WCD9378_A_BASE+0x69)
#define WCD9378_LDOH_SLOWRAMP (WCD9378_A_BASE+0x6a)
#define WCD9378_MICB1_TEST_CTL_1 (WCD9378_A_BASE+0x6b)
#define WCD9378_MICB1_TEST_CTL_2 (WCD9378_A_BASE+0x6c)
#define WCD9378_MICB1_TEST_CTL_3 (WCD9378_A_BASE+0x6d)
#define WCD9378_MICB2_TEST_CTL_1 (WCD9378_A_BASE+0x6e)
#define WCD9378_MICB2_TEST_CTL_2 (WCD9378_A_BASE+0x6f)
#define WCD9378_MICB2_TEST_CTL_3 (WCD9378_A_BASE+0x70)
#define WCD9378_MICB3_TEST_CTL_1 (WCD9378_A_BASE+0x71)
#define WCD9378_MICB3_TEST_CTL_2 (WCD9378_A_BASE+0x72)
#define WCD9378_MICB3_TEST_CTL_3 (WCD9378_A_BASE+0x73)
#define WCD9378_TX_COM_ADC_VCM (WCD9378_A_BASE+0x77)
#define WCD9378_TX_COM_BIAS_ATEST (WCD9378_A_BASE+0x78)
#define WCD9378_TX_COM_SPARE1 (WCD9378_A_BASE+0x79)
#define WCD9378_TX_COM_SPARE2 (WCD9378_A_BASE+0x7a)
#define WCD9378_TX_COM_TXFE_DIV_CTL (WCD9378_A_BASE+0x7b)
#define WCD9378_TX_COM_TXFE_DIV_START (WCD9378_A_BASE+0x7c)
#define WCD9378_TX_COM_SPARE3 (WCD9378_A_BASE+0x7d)
#define WCD9378_TX_COM_SPARE4 (WCD9378_A_BASE+0x7e)
#define WCD9378_TX_1_2_TEST_EN (WCD9378_A_BASE+0x7f)
#define WCD9378_TX_1_2_ADC_IB (WCD9378_A_BASE+0x80)
#define WCD9378_TX_1_2_ATEST_REFCTL (WCD9378_A_BASE+0x81)
#define WCD9378_TX_1_2_TEST_CTL (WCD9378_A_BASE+0x82)
#define WCD9378_TX_1_2_TEST_BLK_EN1 (WCD9378_A_BASE+0x83)
#define WCD9378_TX_1_2_TXFE1_CLKDIV (WCD9378_A_BASE+0x84)
#define WCD9378_TX_1_2_SAR2_ERR (WCD9378_A_BASE+0x85)
#define WCD9378_TX_1_2_SAR1_ERR (WCD9378_A_BASE+0x86)
#define WCD9378_TX_3_TEST_EN (WCD9378_A_BASE+0x87)
#define WCD9378_TX_3_ADC_IB (WCD9378_A_BASE+0x88)
#define WCD9378_TX_3_ATEST_REFCTL (WCD9378_A_BASE+0x89)
#define WCD9378_TX_3_TEST_CTL (WCD9378_A_BASE+0x8a)
#define WCD9378_TX_3_TEST_BLK_EN3 (WCD9378_A_BASE+0x8b)
#define WCD9378_TX_3_TXFE3_CLKDIV (WCD9378_A_BASE+0x8c)
#define WCD9378_TX_3_SAR4_ERR (WCD9378_A_BASE+0x8d)
#define WCD9378_TX_3_SAR3_ERR (WCD9378_A_BASE+0x8e)
#define WCD9378_TX_3_TEST_BLK_EN2 (WCD9378_A_BASE+0x8f)
#define WCD9378_TX_3_TXFE2_CLKDIV (WCD9378_A_BASE+0x90)
#define WCD9378_TX_3_SPARE1 (WCD9378_A_BASE+0x91)
#define WCD9378_TX_3_TEST_BLK_EN4 (WCD9378_A_BASE+0x92)
#define WCD9378_TX_3_SPARE2 (WCD9378_A_BASE+0x93)
#define WCD9378_TX_3_SPARE3 (WCD9378_A_BASE+0x94)
#define WCD9378_RX_AUX_SW_CTL (WCD9378_A_BASE+0xb3)
#define WCD9378_RX_PA_AUX_IN_CONN (WCD9378_A_BASE+0xb4)
#define WCD9378_RX_TIMER_DIV (WCD9378_A_BASE+0xb5)
#define WCD9378_RX_OCP_CTL (WCD9378_A_BASE+0xb6)
#define WCD9378_RX_OCP_COUNT (WCD9378_A_BASE+0xb7)
#define WCD9378_RX_BIAS_EAR_DAC (WCD9378_A_BASE+0xb8)
#define WCD9378_RX_BIAS_EAR_AMP (WCD9378_A_BASE+0xb9)
#define WCD9378_RX_BIAS_HPH_LDO (WCD9378_A_BASE+0xba)
#define WCD9378_RX_BIAS_HPH_PA (WCD9378_A_BASE+0xbb)
#define WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2 (WCD9378_A_BASE+0xbc)
#define WCD9378_RX_BIAS_HPH_RDAC_LDO (WCD9378_A_BASE+0xbd)
#define WCD9378_RX_BIAS_HPH_CNP1 (WCD9378_A_BASE+0xbe)
#define WCD9378_RX_BIAS_HPH_LOWPOWER (WCD9378_A_BASE+0xbf)
#define WCD9378_RX_BIAS_AUX_DAC (WCD9378_A_BASE+0xc0)
#define WCD9378_RX_BIAS_AUX_AMP (WCD9378_A_BASE+0xc1)
#define WCD9378_RX_SPARE_1 (WCD9378_A_BASE+0xc2)
#define WCD9378_RX_SPARE_2 (WCD9378_A_BASE+0xc3)
#define WCD9378_RX_SPARE_3 (WCD9378_A_BASE+0xc4)
#define WCD9378_RX_SPARE_4 (WCD9378_A_BASE+0xc5)
#define WCD9378_RX_SPARE_5 (WCD9378_A_BASE+0xc6)
#define WCD9378_RX_SPARE_6 (WCD9378_A_BASE+0xc7)
#define WCD9378_RX_SPARE_7 (WCD9378_A_BASE+0xc8)
#define WCD9378_HPH_L_STATUS (WCD9378_A_BASE+0xc9)
#define WCD9378_HPH_R_STATUS (WCD9378_A_BASE+0xca)
#define WCD9378_HPH_CNP_EN (WCD9378_A_BASE+0xcb)
#define WCD9378_HPH_CNP_WG_CTL (WCD9378_A_BASE+0xcc)
#define WCD9378_HPH_CNP_WG_TIME (WCD9378_A_BASE+0xcd)
#define WCD9378_HPH_OCP_CTL (WCD9378_A_BASE+0xce)
#define WCD9378_HPH_AUTO_CHOP (WCD9378_A_BASE+0xcf)
#define WCD9378_HPH_CHOP_CTL (WCD9378_A_BASE+0xd0)
#define WCD9378_HPH_PA_CTL1 (WCD9378_A_BASE+0xd1)
#define WCD9378_HPH_PA_CTL2 (WCD9378_A_BASE+0xd2)
#define WCD9378_HPH_L_EN (WCD9378_A_BASE+0xd3)
#define WCD9378_HPH_L_TEST (WCD9378_A_BASE+0xd4)
#define WCD9378_HPH_L_ATEST (WCD9378_A_BASE+0xd5)
#define WCD9378_HPH_R_EN (WCD9378_A_BASE+0xd6)
#define WCD9378_HPH_R_TEST (WCD9378_A_BASE+0xd7)
#define WCD9378_HPH_R_ATEST (WCD9378_A_BASE+0xd8)
#define WCD9378_HPH_RDAC_CLK_CTL1 (WCD9378_A_BASE+0xd9)
#define WCD9378_HPH_RDAC_CLK_CTL2 (WCD9378_A_BASE+0xda)
#define WCD9378_HPH_RDAC_LDO_CTL (WCD9378_A_BASE+0xdb)
#define WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL (WCD9378_A_BASE+0xdc)
#define WCD9378_HPH_REFBUFF_UHQA_CTL (WCD9378_A_BASE+0xdd)
#define WCD9378_HPH_REFBUFF_LP_CTL (WCD9378_A_BASE+0xde)
#define WCD9378_HPH_L_DAC_CTL (WCD9378_A_BASE+0xdf)
#define WCD9378_HPH_R_DAC_CTL (WCD9378_A_BASE+0xe0)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL (WCD9378_A_BASE+0xe1)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN (WCD9378_A_BASE+0xe2)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1 (WCD9378_A_BASE+0xe3)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS (WCD9378_A_BASE+0xe4)
#define WCD9378_EAR_EAR_EN_REG (WCD9378_A_BASE+0xe9)
#define WCD9378_EAR_EAR_PA_CON (WCD9378_A_BASE+0xea)
#define WCD9378_EAR_EAR_SP_CON (WCD9378_A_BASE+0xeb)
#define WCD9378_EAR_EAR_DAC_CON (WCD9378_A_BASE+0xec)
#define WCD9378_EAR_EAR_CNP_FSM_CON (WCD9378_A_BASE+0xed)
#define WCD9378_EAR_TEST_CTL (WCD9378_A_BASE+0xee)
#define WCD9378_EAR_STATUS_REG_1 (WCD9378_A_BASE+0xef)
#define WCD9378_EAR_STATUS_REG_2 (WCD9378_A_BASE+0xf0)
#define WCD9378_ANA_NEW_PAGE (WCD9378_A_BASE+0x100)
#define WCD9378_HPH_NEW_ANA_HPH2 (WCD9378_A_BASE+0x101)
#define WCD9378_HPH_NEW_ANA_HPH3 (WCD9378_A_BASE+0x102)
#define WCD9378_SLEEP_CTL (WCD9378_A_BASE+0x103)
#define WCD9378_SLEEP_WATCHDOG_CTL (WCD9378_A_BASE+0x104)
#define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL (WCD9378_A_BASE+0x11f)
#define WCD9378_MBHC_NEW_CTL_1 (WCD9378_A_BASE+0x120)
#define WCD9378_MBHC_NEW_CTL_2 (WCD9378_A_BASE+0x121)
#define WCD9378_MBHC_NEW_PLUG_DETECT_CTL (WCD9378_A_BASE+0x122)
#define WCD9378_MBHC_NEW_ZDET_ANA_CTL (WCD9378_A_BASE+0x123)
#define WCD9378_MBHC_NEW_ZDET_RAMP_CTL (WCD9378_A_BASE+0x124)
#define WCD9378_MBHC_NEW_FSM_STATUS (WCD9378_A_BASE+0x125)
#define WCD9378_MBHC_NEW_ADC_RESULT (WCD9378_A_BASE+0x126)
#define WCD9378_AUX_AUXPA (WCD9378_A_BASE+0x128)
#define WCD9378_DIE_CRACK_DIE_CRK_DET_EN (WCD9378_A_BASE+0x12c)
#define WCD9378_DIE_CRACK_DIE_CRK_DET_OUT (WCD9378_A_BASE+0x12d)
#define WCD9378_TX_NEW_TX_CH12_MUX (WCD9378_A_BASE+0x12e)
#define WCD9378_TX_NEW_TX_CH34_MUX (WCD9378_A_BASE+0x12f)
#define WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL (WCD9378_A_BASE+0x132)
#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L (WCD9378_A_BASE+0x133)
#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL (WCD9378_A_BASE+0x134)
#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL (WCD9378_A_BASE+0x135)
#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R (WCD9378_A_BASE+0x136)
#define WCD9378_HPH_NEW_INT_PA_MISC1 (WCD9378_A_BASE+0x137)
#define WCD9378_HPH_NEW_INT_PA_MISC2 (WCD9378_A_BASE+0x138)
#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC (WCD9378_A_BASE+0x139)
#define WCD9378_HPH_NEW_INT_HPH_TIMER1 (WCD9378_A_BASE+0x13a)
#define WCD9378_HPH_NEW_INT_HPH_TIMER2 (WCD9378_A_BASE+0x13b)
#define WCD9378_HPH_NEW_INT_HPH_TIMER3 (WCD9378_A_BASE+0x13c)
#define WCD9378_HPH_NEW_INT_HPH_TIMER4 (WCD9378_A_BASE+0x13d)
#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC2 (WCD9378_A_BASE+0x13e)
#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC3 (WCD9378_A_BASE+0x13f)
#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (WCD9378_A_BASE+0x145)
#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP (WCD9378_A_BASE+0x146)
#define WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP (WCD9378_A_BASE+0x147)
#define WCD9378_CP_CLASSG_CP_CTRL_0 (WCD9378_A_BASE+0x150)
#define WCD9378_CP_CLASSG_CP_CTRL_1 (WCD9378_A_BASE+0x151)
#define WCD9378_CP_CLASSG_CP_CTRL_2 (WCD9378_A_BASE+0x152)
#define WCD9378_CP_CLASSG_CP_CTRL_3 (WCD9378_A_BASE+0x153)
#define WCD9378_CP_CLASSG_CP_CTRL_4 (WCD9378_A_BASE+0x154)
#define WCD9378_CP_CLASSG_CP_CTRL_5 (WCD9378_A_BASE+0x155)
#define WCD9378_CP_CLASSG_CP_CTRL_6 (WCD9378_A_BASE+0x156)
#define WCD9378_CP_CLASSG_CP_CTRL_7 (WCD9378_A_BASE+0x157)
#define WCD9378_CP_VNEGDAC_CTRL_0 (WCD9378_A_BASE+0x158)
#define WCD9378_CP_VNEGDAC_CTRL_1 (WCD9378_A_BASE+0x159)
#define WCD9378_CP_VNEGDAC_CTRL_2 (WCD9378_A_BASE+0x15a)
#define WCD9378_CP_VNEGDAC_CTRL_3 (WCD9378_A_BASE+0x15b)
#define WCD9378_CP_CP_DTOP_CTRL_0 (WCD9378_A_BASE+0x15c)
#define WCD9378_CP_CP_DTOP_CTRL_1 (WCD9378_A_BASE+0x15d)
#define WCD9378_CP_CP_DTOP_CTRL_2 (WCD9378_A_BASE+0x15e)
#define WCD9378_CP_CP_DTOP_CTRL_3 (WCD9378_A_BASE+0x15f)
#define WCD9378_CP_CP_DTOP_CTRL_4 (WCD9378_A_BASE+0x160)
#define WCD9378_CP_CP_DTOP_CTRL_5 (WCD9378_A_BASE+0x161)
#define WCD9378_CP_CP_DTOP_CTRL_6 (WCD9378_A_BASE+0x162)
#define WCD9378_CP_CP_DTOP_CTRL_7 (WCD9378_A_BASE+0x163)
#define WCD9378_CP_CP_DTOP_CTRL_8 (WCD9378_A_BASE+0x164)
#define WCD9378_CP_CP_DTOP_CTRL_9 (WCD9378_A_BASE+0x165)
#define WCD9378_CP_CP_DTOP_CTRL_10 (WCD9378_A_BASE+0x166)
#define WCD9378_CP_CP_DTOP_CTRL_11 (WCD9378_A_BASE+0x167)
#define WCD9378_CP_CP_DTOP_CTRL_12 (WCD9378_A_BASE+0x168)
#define WCD9378_CP_CP_DTOP_CTRL_13 (WCD9378_A_BASE+0x169)
#define WCD9378_CP_CP_DTOP_CTRL_14 (WCD9378_A_BASE+0x16a)
#define WCD9378_CP_CP_DTOP_CTRL_15 (WCD9378_A_BASE+0x16b)
#define WCD9378_CP_CP_DTOP_CTRL_16 (WCD9378_A_BASE+0x16c)
#define WCD9378_CP_CP_DTOP_CTRL_17 (WCD9378_A_BASE+0x16d)
#define WCD9378_CP_CP_DTOP_CTRL_18 (WCD9378_A_BASE+0x16e)
#define WCD9378_CP_CP_DTOP_CTRL_19 (WCD9378_A_BASE+0x16f)
#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (WCD9378_A_BASE+0x1af)
#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (WCD9378_A_BASE+0x1b0)
#define WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT (WCD9378_A_BASE+0x1b1)
#define WCD9378_MBHC_NEW_INT_SPARE_2 (WCD9378_A_BASE+0x1b2)
#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON (WCD9378_A_BASE+0x1b7)
#define WCD9378_EAR_INT_NEW_CNP_VCM_CON1 (WCD9378_A_BASE+0x1b8)
#define WCD9378_EAR_INT_NEW_CNP_VCM_CON2 (WCD9378_A_BASE+0x1b9)
#define WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS (WCD9378_A_BASE+0x1ba)
#define WCD9378_AUX_INT_EN_REG (WCD9378_A_BASE+0x1bd)
#define WCD9378_AUX_INT_PA_CTRL (WCD9378_A_BASE+0x1be)
#define WCD9378_AUX_INT_SP_CTRL (WCD9378_A_BASE+0x1bf)
#define WCD9378_AUX_INT_DAC_CTRL (WCD9378_A_BASE+0x1c0)
#define WCD9378_AUX_INT_CLK_CTRL (WCD9378_A_BASE+0x1c1)
#define WCD9378_AUX_INT_TEST_CTRL (WCD9378_A_BASE+0x1c2)
#define WCD9378_AUX_INT_STATUS_REG (WCD9378_A_BASE+0x1c3)
#define WCD9378_AUX_INT_MISC (WCD9378_A_BASE+0x1c4)
#define WCD9378_SLEEP_INT_WATCHDOG_CTL_1 (WCD9378_A_BASE+0x1d0)
#define WCD9378_SLEEP_INT_WATCHDOG_CTL_2 (WCD9378_A_BASE+0x1d1)
#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1 (WCD9378_A_BASE+0x1d3)
#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2 (WCD9378_A_BASE+0x1d4)
#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2 (WCD9378_A_BASE+0x1d5)
#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1 (WCD9378_A_BASE+0x1d6)
#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0 (WCD9378_A_BASE+0x1d7)
#define WCD9378_TX_COM_NEW_INT_SPARE1 (WCD9378_A_BASE+0x1d8)
#define WCD9378_TX_COM_NEW_INT_SPARE2 (WCD9378_A_BASE+0x1d9)
#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2 (WCD9378_A_BASE+0x1da)
#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1 (WCD9378_A_BASE+0x1db)
#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0 (WCD9378_A_BASE+0x1dc)
#define WCD9378_TX_COM_NEW_INT_SPARE3 (WCD9378_A_BASE+0x1dd)
#define WCD9378_TX_COM_NEW_INT_SPARE4 (WCD9378_A_BASE+0x1de)
#define WCD9378_TX_COM_NEW_INT_SPARE5 (WCD9378_A_BASE+0x1df)
#define WCD9378_TX_COM_NEW_INT_SPARE6 (WCD9378_A_BASE+0x1e0)
#define WCD9378_TX_COM_NEW_INT_SPARE7 (WCD9378_A_BASE+0x1e1)
#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1 (WCD9378_A_BASE+0x1e2)
#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0 (WCD9378_A_BASE+0x1e3)
#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L2 (WCD9378_A_BASE+0x1e4)
#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L1 (WCD9378_A_BASE+0x1e5)
#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L0 (WCD9378_A_BASE+0x1e6)
#define WCD9378_TX_COM_NEW_INT_SPARE8 (WCD9378_A_BASE+0x1e7)
#define WCD9378_TAMBORA_BASE (WCD9378_BASE+0x180401)
#define WCD9378_TAMBORA_PAGE (WCD9378_TAMBORA_BASE+0x00)
#define WCD9378_CHIP_ID0 (WCD9378_TAMBORA_BASE+0x01)
#define WCD9378_CHIP_ID1 (WCD9378_TAMBORA_BASE+0x02)
#define WCD9378_CHIP_ID2 (WCD9378_TAMBORA_BASE+0x03)
#define WCD9378_CHIP_ID3 (WCD9378_TAMBORA_BASE+0x04)
#define WCD9378_SWR_TX_CLK_RATE (WCD9378_TAMBORA_BASE+0x05)
#define WCD9378_CDC_RST_CTL (WCD9378_TAMBORA_BASE+0x06)
#define WCD9378_TOP_CLK_CFG (WCD9378_TAMBORA_BASE+0x07)
#define WCD9378_CDC_ANA_CLK_CTL (WCD9378_TAMBORA_BASE+0x08)
#define WCD9378_CDC_DIG_CLK_CTL (WCD9378_TAMBORA_BASE+0x09)
#define WCD9378_SWR_RST_EN (WCD9378_TAMBORA_BASE+0x0a)
#define WCD9378_CDC_PATH_MODE (WCD9378_TAMBORA_BASE+0x0b)
#define WCD9378_CDC_RX_RST (WCD9378_TAMBORA_BASE+0x0c)
#define WCD9378_CDC_RX0_CTL (WCD9378_TAMBORA_BASE+0x0d)
#define WCD9378_CDC_RX1_CTL (WCD9378_TAMBORA_BASE+0x0e)
#define WCD9378_CDC_RX2_CTL (WCD9378_TAMBORA_BASE+0x0f)
#define WCD9378_CDC_TX_ANA_MODE_0_1 (WCD9378_TAMBORA_BASE+0x10)
#define WCD9378_CDC_TX_ANA_MODE_2_3 (WCD9378_TAMBORA_BASE+0x11)
#define WCD9378_CDC_COMP_CTL_0 (WCD9378_TAMBORA_BASE+0x14)
#define WCD9378_CDC_ANA_TX_CLK_CTL (WCD9378_TAMBORA_BASE+0x17)
#define WCD9378_CDC_HPH_DSM_A1_0 (WCD9378_TAMBORA_BASE+0x18)
#define WCD9378_CDC_HPH_DSM_A1_1 (WCD9378_TAMBORA_BASE+0x19)
#define WCD9378_CDC_HPH_DSM_A2_0 (WCD9378_TAMBORA_BASE+0x1a)
#define WCD9378_CDC_HPH_DSM_A2_1 (WCD9378_TAMBORA_BASE+0x1b)
#define WCD9378_CDC_HPH_DSM_A3_0 (WCD9378_TAMBORA_BASE+0x1c)
#define WCD9378_CDC_HPH_DSM_A3_1 (WCD9378_TAMBORA_BASE+0x1d)
#define WCD9378_CDC_HPH_DSM_A4_0 (WCD9378_TAMBORA_BASE+0x1e)
#define WCD9378_CDC_HPH_DSM_A4_1 (WCD9378_TAMBORA_BASE+0x1f)
#define WCD9378_CDC_HPH_DSM_A5_0 (WCD9378_TAMBORA_BASE+0x20)
#define WCD9378_CDC_HPH_DSM_A5_1 (WCD9378_TAMBORA_BASE+0x21)
#define WCD9378_CDC_HPH_DSM_A6_0 (WCD9378_TAMBORA_BASE+0x22)
#define WCD9378_CDC_HPH_DSM_A7_0 (WCD9378_TAMBORA_BASE+0x23)
#define WCD9378_CDC_HPH_DSM_C_0 (WCD9378_TAMBORA_BASE+0x24)
#define WCD9378_CDC_HPH_DSM_C_1 (WCD9378_TAMBORA_BASE+0x25)
#define WCD9378_CDC_HPH_DSM_C_2 (WCD9378_TAMBORA_BASE+0x26)
#define WCD9378_CDC_HPH_DSM_C_3 (WCD9378_TAMBORA_BASE+0x27)
#define WCD9378_CDC_HPH_DSM_R1 (WCD9378_TAMBORA_BASE+0x28)
#define WCD9378_CDC_HPH_DSM_R2 (WCD9378_TAMBORA_BASE+0x29)
#define WCD9378_CDC_HPH_DSM_R3 (WCD9378_TAMBORA_BASE+0x2a)
#define WCD9378_CDC_HPH_DSM_R4 (WCD9378_TAMBORA_BASE+0x2b)
#define WCD9378_CDC_HPH_DSM_R5 (WCD9378_TAMBORA_BASE+0x2c)
#define WCD9378_CDC_HPH_DSM_R6 (WCD9378_TAMBORA_BASE+0x2d)
#define WCD9378_CDC_HPH_DSM_R7 (WCD9378_TAMBORA_BASE+0x2e)
#define WCD9378_CDC_AUX_DSM_A1_0 (WCD9378_TAMBORA_BASE+0x2f)
#define WCD9378_CDC_AUX_DSM_A1_1 (WCD9378_TAMBORA_BASE+0x30)
#define WCD9378_CDC_AUX_DSM_A2_0 (WCD9378_TAMBORA_BASE+0x31)
#define WCD9378_CDC_AUX_DSM_A2_1 (WCD9378_TAMBORA_BASE+0x32)
#define WCD9378_CDC_AUX_DSM_A3_0 (WCD9378_TAMBORA_BASE+0x33)
#define WCD9378_CDC_AUX_DSM_A3_1 (WCD9378_TAMBORA_BASE+0x34)
#define WCD9378_CDC_AUX_DSM_A4_0 (WCD9378_TAMBORA_BASE+0x35)
#define WCD9378_CDC_AUX_DSM_A4_1 (WCD9378_TAMBORA_BASE+0x36)
#define WCD9378_CDC_AUX_DSM_A5_0 (WCD9378_TAMBORA_BASE+0x37)
#define WCD9378_CDC_AUX_DSM_A5_1 (WCD9378_TAMBORA_BASE+0x38)
#define WCD9378_CDC_AUX_DSM_A6_0 (WCD9378_TAMBORA_BASE+0x39)
#define WCD9378_CDC_AUX_DSM_A7_0 (WCD9378_TAMBORA_BASE+0x3a)
#define WCD9378_CDC_AUX_DSM_C_0 (WCD9378_TAMBORA_BASE+0x3b)
#define WCD9378_CDC_AUX_DSM_C_1 (WCD9378_TAMBORA_BASE+0x3c)
#define WCD9378_CDC_AUX_DSM_C_2 (WCD9378_TAMBORA_BASE+0x3d)
#define WCD9378_CDC_AUX_DSM_C_3 (WCD9378_TAMBORA_BASE+0x3e)
#define WCD9378_CDC_AUX_DSM_R1 (WCD9378_TAMBORA_BASE+0x3f)
#define WCD9378_CDC_AUX_DSM_R2 (WCD9378_TAMBORA_BASE+0x40)
#define WCD9378_CDC_AUX_DSM_R3 (WCD9378_TAMBORA_BASE+0x41)
#define WCD9378_CDC_AUX_DSM_R4 (WCD9378_TAMBORA_BASE+0x42)
#define WCD9378_CDC_AUX_DSM_R5 (WCD9378_TAMBORA_BASE+0x43)
#define WCD9378_CDC_AUX_DSM_R6 (WCD9378_TAMBORA_BASE+0x44)
#define WCD9378_CDC_AUX_DSM_R7 (WCD9378_TAMBORA_BASE+0x45)
#define WCD9378_CDC_HPH_GAIN_RX_0 (WCD9378_TAMBORA_BASE+0x46)
#define WCD9378_CDC_HPH_GAIN_RX_1 (WCD9378_TAMBORA_BASE+0x47)
#define WCD9378_CDC_HPH_GAIN_DSD_0 (WCD9378_TAMBORA_BASE+0x48)
#define WCD9378_CDC_HPH_GAIN_DSD_1 (WCD9378_TAMBORA_BASE+0x49)
#define WCD9378_CDC_HPH_GAIN_DSD_2 (WCD9378_TAMBORA_BASE+0x4a)
#define WCD9378_CDC_AUX_GAIN_DSD_0 (WCD9378_TAMBORA_BASE+0x4b)
#define WCD9378_CDC_AUX_GAIN_DSD_1 (WCD9378_TAMBORA_BASE+0x4c)
#define WCD9378_CDC_AUX_GAIN_DSD_2 (WCD9378_TAMBORA_BASE+0x4d)
#define WCD9378_CDC_HPH_GAIN_CTL (WCD9378_TAMBORA_BASE+0x4e)
#define WCD9378_CDC_AUX_GAIN_CTL (WCD9378_TAMBORA_BASE+0x4f)
#define WCD9378_CDC_PATH_CTL (WCD9378_TAMBORA_BASE+0x50)
#define WCD9378_CDC_SWR_CLG (WCD9378_TAMBORA_BASE+0x51)
#define WCD9378_SWR_CLG_BYP (WCD9378_TAMBORA_BASE+0x52)
#define WCD9378_CDC_TX0_CTL (WCD9378_TAMBORA_BASE+0x53)
#define WCD9378_CDC_TX1_CTL (WCD9378_TAMBORA_BASE+0x54)
#define WCD9378_CDC_TX2_CTL (WCD9378_TAMBORA_BASE+0x55)
#define WCD9378_CDC_TX_RST (WCD9378_TAMBORA_BASE+0x56)
#define WCD9378_CDC_REQ_CTL (WCD9378_TAMBORA_BASE+0x57)
#define WCD9378_CDC_RST (WCD9378_TAMBORA_BASE+0x58)
#define WCD9378_CDC_AMIC_CTL (WCD9378_TAMBORA_BASE+0x5a)
#define WCD9378_CDC_DMIC_CTL (WCD9378_TAMBORA_BASE+0x5b)
#define WCD9378_CDC_DMIC1_CTL (WCD9378_TAMBORA_BASE+0x5c)
#define WCD9378_CDC_DMIC2_CTL (WCD9378_TAMBORA_BASE+0x5d)
#define WCD9378_CDC_DMIC3_CTL (WCD9378_TAMBORA_BASE+0x5e)
#define WCD9378_EFUSE_PRG_CTL (WCD9378_TAMBORA_BASE+0x60)
#define WCD9378_EFUSE_CTL (WCD9378_TAMBORA_BASE+0x61)
#define WCD9378_CDC_DMIC_RATE_1_2 (WCD9378_TAMBORA_BASE+0x62)
#define WCD9378_CDC_DMIC_RATE_3_4 (WCD9378_TAMBORA_BASE+0x63)
#define WCD9378_PDM_WD_EN_OVRD (WCD9378_TAMBORA_BASE+0x64)
#define WCD9378_PDM_WD_CTL0 (WCD9378_TAMBORA_BASE+0x65)
#define WCD9378_PDM_WD_CTL1 (WCD9378_TAMBORA_BASE+0x66)
#define WCD9378_PDM_WD_CTL2 (WCD9378_TAMBORA_BASE+0x67)
#define WCD9378_RAMP_CTL (WCD9378_TAMBORA_BASE+0x68)
#define WCD9378_ACT_DET_CTL (WCD9378_TAMBORA_BASE+0x69)
#define WCD9378_ACT_DET_HOOKUP0 (WCD9378_TAMBORA_BASE+0x6a)
#define WCD9378_ACT_DET_HOOKUP1 (WCD9378_TAMBORA_BASE+0x6b)
#define WCD9378_ACT_DET_HOOKUP2 (WCD9378_TAMBORA_BASE+0x6c)
#define WCD9378_ACT_DET_DLY_BUF_EN (WCD9378_TAMBORA_BASE+0x6d)
#define WCD9378_INTR_MODE (WCD9378_TAMBORA_BASE+0x6e)
#define WCD9378_INTR_STATUS_0 (WCD9378_TAMBORA_BASE+0x6f)
#define WCD9378_INTR_STATUS_1 (WCD9378_TAMBORA_BASE+0x70)
#define WCD9378_INTR_STATUS_2 (WCD9378_TAMBORA_BASE+0x71)
#define WCD9378_INTR_STATUS_3 (WCD9378_TAMBORA_BASE+0x72)
#define WCD9378_INTR_MASK_0 (WCD9378_TAMBORA_BASE+0x73)
#define WCD9378_INTR_MASK_1 (WCD9378_TAMBORA_BASE+0x74)
#define WCD9378_INTR_MASK_2 (WCD9378_TAMBORA_BASE+0x75)
#define WCD9378_INTR_MASK_3 (WCD9378_TAMBORA_BASE+0x76)
#define WCD9378_INTR_SET_0 (WCD9378_TAMBORA_BASE+0x77)
#define WCD9378_INTR_SET_1 (WCD9378_TAMBORA_BASE+0x78)
#define WCD9378_INTR_SET_2 (WCD9378_TAMBORA_BASE+0x79)
#define WCD9378_INTR_SET_3 (WCD9378_TAMBORA_BASE+0x7a)
#define WCD9378_INTR_TEST_0 (WCD9378_TAMBORA_BASE+0x7b)
#define WCD9378_INTR_TEST_1 (WCD9378_TAMBORA_BASE+0x7c)
#define WCD9378_INTR_TEST_2 (WCD9378_TAMBORA_BASE+0x7d)
#define WCD9378_INTR_TEST_3 (WCD9378_TAMBORA_BASE+0x7e)
#define WCD9378_TX_MODE_DBG_EN (WCD9378_TAMBORA_BASE+0x7f)
#define WCD9378_TX_MODE_DBG_0_1 (WCD9378_TAMBORA_BASE+0x80)
#define WCD9378_TX_MODE_DBG_2_3 (WCD9378_TAMBORA_BASE+0x81)
#define WCD9378_LB_IN_SEL_CTL (WCD9378_TAMBORA_BASE+0x82)
#define WCD9378_LOOP_BACK_MODE (WCD9378_TAMBORA_BASE+0x83)
#define WCD9378_SWR_DAC_TEST (WCD9378_TAMBORA_BASE+0x84)
#define WCD9378_SWR_HM_TEST_RX_0 (WCD9378_TAMBORA_BASE+0x85)
#define WCD9378_SWR_HM_TEST_TX_0 (WCD9378_TAMBORA_BASE+0x86)
#define WCD9378_SWR_HM_TEST_RX_1 (WCD9378_TAMBORA_BASE+0x87)
#define WCD9378_SWR_HM_TEST_TX_1 (WCD9378_TAMBORA_BASE+0x88)
#define WCD9378_SWR_HM_TEST_0 (WCD9378_TAMBORA_BASE+0x8a)
#define WCD9378_PAD_CTL_SWR_0 (WCD9378_TAMBORA_BASE+0x8c)
#define WCD9378_PAD_CTL_SWR_1 (WCD9378_TAMBORA_BASE+0x8d)
#define WCD9378_I2C_CTL (WCD9378_TAMBORA_BASE+0x8e)
#define WCD9378_LEGACY_SW_MODE (WCD9378_TAMBORA_BASE+0x8f)
#define WCD9378_EFUSE_TEST_CTL_0 (WCD9378_TAMBORA_BASE+0x90)
#define WCD9378_EFUSE_TEST_CTL_1 (WCD9378_TAMBORA_BASE+0x91)
#define WCD9378_EFUSE_T_DATA_0 (WCD9378_TAMBORA_BASE+0x92)
#define WCD9378_PAD_CTL_PDM_RX0 (WCD9378_TAMBORA_BASE+0x94)
#define WCD9378_PAD_CTL_PDM_RX1 (WCD9378_TAMBORA_BASE+0x95)
#define WCD9378_PAD_CTL_PDM_TX0 (WCD9378_TAMBORA_BASE+0x96)
#define WCD9378_PAD_CTL_PDM_TX1 (WCD9378_TAMBORA_BASE+0x97)
#define WCD9378_PAD_INP_DIS_0 (WCD9378_TAMBORA_BASE+0x99)
#define WCD9378_DRIVE_STRENGTH_0 (WCD9378_TAMBORA_BASE+0x9b)
#define WCD9378_DRIVE_STRENGTH_1 (WCD9378_TAMBORA_BASE+0x9c)
#define WCD9378_RX_DATA_EDGE_CTL (WCD9378_TAMBORA_BASE+0x9e)
#define WCD9378_TX_DATA_EDGE_CTL (WCD9378_TAMBORA_BASE+0x9f)
#define WCD9378_GPIO_MODE (WCD9378_TAMBORA_BASE+0xa0)
#define WCD9378_PIN_CTL_OE (WCD9378_TAMBORA_BASE+0xa1)
#define WCD9378_PIN_CTL_DATA_0 (WCD9378_TAMBORA_BASE+0xa2)
#define WCD9378_PIN_STATUS_0 (WCD9378_TAMBORA_BASE+0xa4)
#define WCD9378_DIG_DEBUG_CTL (WCD9378_TAMBORA_BASE+0xa6)
#define WCD9378_DIG_DEBUG_EN (WCD9378_TAMBORA_BASE+0xa7)
#define WCD9378_ANA_CSR_DBG_ADD (WCD9378_TAMBORA_BASE+0xa8)
#define WCD9378_ANA_CSR_DBG_CTL (WCD9378_TAMBORA_BASE+0xa9)
#define WCD9378_SSP_DBG (WCD9378_TAMBORA_BASE+0xaa)
#define WCD9378_MODE_STATUS_0 (WCD9378_TAMBORA_BASE+0xab)
#define WCD9378_MODE_STATUS_1 (WCD9378_TAMBORA_BASE+0xac)
#define WCD9378_SPARE_0 (WCD9378_TAMBORA_BASE+0xad)
#define WCD9378_SPARE_1 (WCD9378_TAMBORA_BASE+0xae)
#define WCD9378_SPARE_2 (WCD9378_TAMBORA_BASE+0xaf)
#define WCD9378_EFUSE_REG_0 (WCD9378_TAMBORA_BASE+0xb0)
#define WCD9378_EFUSE_REG_1 (WCD9378_TAMBORA_BASE+0xb1)
#define WCD9378_EFUSE_REG_2 (WCD9378_TAMBORA_BASE+0xb2)
#define WCD9378_EFUSE_REG_3 (WCD9378_TAMBORA_BASE+0xb3)
#define WCD9378_EFUSE_REG_4 (WCD9378_TAMBORA_BASE+0xb4)
#define WCD9378_EFUSE_REG_5 (WCD9378_TAMBORA_BASE+0xb5)
#define WCD9378_EFUSE_REG_6 (WCD9378_TAMBORA_BASE+0xb6)
#define WCD9378_EFUSE_REG_7 (WCD9378_TAMBORA_BASE+0xb7)
#define WCD9378_EFUSE_REG_8 (WCD9378_TAMBORA_BASE+0xb8)
#define WCD9378_EFUSE_REG_9 (WCD9378_TAMBORA_BASE+0xb9)
#define WCD9378_EFUSE_REG_10 (WCD9378_TAMBORA_BASE+0xba)
#define WCD9378_EFUSE_REG_11 (WCD9378_TAMBORA_BASE+0xbb)
#define WCD9378_EFUSE_REG_12 (WCD9378_TAMBORA_BASE+0xbc)
#define WCD9378_EFUSE_REG_13 (WCD9378_TAMBORA_BASE+0xbd)
#define WCD9378_EFUSE_REG_14 (WCD9378_TAMBORA_BASE+0xbe)
#define WCD9378_EFUSE_REG_15 (WCD9378_TAMBORA_BASE+0xbf)
#define WCD9378_EFUSE_REG_16 (WCD9378_TAMBORA_BASE+0xc0)
#define WCD9378_EFUSE_REG_17 (WCD9378_TAMBORA_BASE+0xc1)
#define WCD9378_EFUSE_REG_18 (WCD9378_TAMBORA_BASE+0xc2)
#define WCD9378_EFUSE_REG_19 (WCD9378_TAMBORA_BASE+0xc3)
#define WCD9378_EFUSE_REG_20 (WCD9378_TAMBORA_BASE+0xc4)
#define WCD9378_EFUSE_REG_21 (WCD9378_TAMBORA_BASE+0xc5)
#define WCD9378_EFUSE_REG_22 (WCD9378_TAMBORA_BASE+0xc6)
#define WCD9378_EFUSE_REG_23 (WCD9378_TAMBORA_BASE+0xc7)
#define WCD9378_EFUSE_REG_24 (WCD9378_TAMBORA_BASE+0xc8)
#define WCD9378_EFUSE_REG_25 (WCD9378_TAMBORA_BASE+0xc9)
#define WCD9378_EFUSE_REG_26 (WCD9378_TAMBORA_BASE+0xca)
#define WCD9378_EFUSE_REG_27 (WCD9378_TAMBORA_BASE+0xcb)
#define WCD9378_EFUSE_REG_28 (WCD9378_TAMBORA_BASE+0xcc)
#define WCD9378_EFUSE_REG_29 (WCD9378_TAMBORA_BASE+0xcd)
#define WCD9378_EFUSE_REG_30 (WCD9378_TAMBORA_BASE+0xce)
#define WCD9378_EFUSE_REG_31 (WCD9378_TAMBORA_BASE+0xcf)
#define WCD9378_TX_REQ_FB_CTL_2 (WCD9378_TAMBORA_BASE+0xd2)
#define WCD9378_TX_REQ_FB_CTL_3 (WCD9378_TAMBORA_BASE+0xd3)
#define WCD9378_TX_REQ_FB_CTL_4 (WCD9378_TAMBORA_BASE+0xd4)
#define WCD9378_DEM_BYPASS_DATA0 (WCD9378_TAMBORA_BASE+0xd5)
#define WCD9378_DEM_BYPASS_DATA1 (WCD9378_TAMBORA_BASE+0xd6)
#define WCD9378_DEM_BYPASS_DATA2 (WCD9378_TAMBORA_BASE+0xd7)
#define WCD9378_DEM_BYPASS_DATA3 (WCD9378_TAMBORA_BASE+0xd8)
#define WCD9378_RX0_PCM_RAMP_STEP (WCD9378_TAMBORA_BASE+0xd9)
#define WCD9378_RX0_DSD_RAMP_STEP (WCD9378_TAMBORA_BASE+0xda)
#define WCD9378_RX1_PCM_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdb)
#define WCD9378_RX1_DSD_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdc)
#define WCD9378_RX2_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdd)
#define WCD9378_PLATFORM_CTL (WCD9378_TAMBORA_BASE+0xf0)
#define WCD9378_CLK_DIV_CFG (WCD9378_TAMBORA_BASE+0xf1)
#define WCD9378_DRE_DLY_VAL (WCD9378_TAMBORA_BASE+0xf2)
#define WCD9378_SEQR_BASE (WCD9378_BASE+0x180501)
#define WCD9378_SYS_USAGE_CTRL (WCD9378_SEQR_BASE+0x01)
#define WCD9378_SURGE_CTL (WCD9378_SEQR_BASE+0x02)
#define WCD9378_SEQ_CTL (WCD9378_SEQR_BASE+0x03)
#define WCD9378_HPH_UP_T0 (WCD9378_SEQR_BASE+0x10)
#define WCD9378_HPH_UP_T1 (WCD9378_SEQR_BASE+0x11)
#define WCD9378_HPH_UP_T2 (WCD9378_SEQR_BASE+0x12)
#define WCD9378_HPH_UP_T3 (WCD9378_SEQR_BASE+0x13)
#define WCD9378_HPH_UP_T4 (WCD9378_SEQR_BASE+0x14)
#define WCD9378_HPH_UP_T5 (WCD9378_SEQR_BASE+0x15)
#define WCD9378_HPH_UP_T6 (WCD9378_SEQR_BASE+0x16)
#define WCD9378_HPH_UP_T7 (WCD9378_SEQR_BASE+0x17)
#define WCD9378_HPH_UP_T8 (WCD9378_SEQR_BASE+0x18)
#define WCD9378_HPH_UP_T9 (WCD9378_SEQR_BASE+0x19)
#define WCD9378_HPH_UP_T10 (WCD9378_SEQR_BASE+0x1a)
#define WCD9378_HPH_DN_T0 (WCD9378_SEQR_BASE+0x1b)
#define WCD9378_HPH_DN_T1 (WCD9378_SEQR_BASE+0x1c)
#define WCD9378_HPH_DN_T2 (WCD9378_SEQR_BASE+0x1d)
#define WCD9378_HPH_DN_T3 (WCD9378_SEQR_BASE+0x1e)
#define WCD9378_HPH_DN_T4 (WCD9378_SEQR_BASE+0x1f)
#define WCD9378_HPH_DN_T5 (WCD9378_SEQR_BASE+0x20)
#define WCD9378_HPH_DN_T6 (WCD9378_SEQR_BASE+0x21)
#define WCD9378_HPH_DN_T7 (WCD9378_SEQR_BASE+0x22)
#define WCD9378_HPH_DN_T8 (WCD9378_SEQR_BASE+0x23)
#define WCD9378_HPH_DN_T9 (WCD9378_SEQR_BASE+0x24)
#define WCD9378_HPH_DN_T10 (WCD9378_SEQR_BASE+0x25)
#define WCD9378_HPH_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x26)
#define WCD9378_HPH_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x27)
#define WCD9378_HPH_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x28)
#define WCD9378_HPH_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x29)
#define WCD9378_HPH_UP_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x2a)
#define WCD9378_HPH_UP_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x2b)
#define WCD9378_HPH_UP_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x2c)
#define WCD9378_HPH_UP_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x2d)
#define WCD9378_HPH_UP_STAGE_LOC_8 (WCD9378_SEQR_BASE+0x2e)
#define WCD9378_HPH_UP_STAGE_LOC_9 (WCD9378_SEQR_BASE+0x2f)
#define WCD9378_HPH_UP_STAGE_LOC_10 (WCD9378_SEQR_BASE+0x30)
#define WCD9378_HPH_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x31)
#define WCD9378_HPH_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x32)
#define WCD9378_HPH_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x33)
#define WCD9378_HPH_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x34)
#define WCD9378_HPH_DN_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x35)
#define WCD9378_HPH_DN_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x36)
#define WCD9378_HPH_DN_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x37)
#define WCD9378_HPH_DN_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x38)
#define WCD9378_HPH_DN_STAGE_LOC_8 (WCD9378_SEQR_BASE+0x39)
#define WCD9378_HPH_DN_STAGE_LOC_9 (WCD9378_SEQR_BASE+0x3a)
#define WCD9378_HPH_DN_STAGE_LOC_10 (WCD9378_SEQR_BASE+0x3b)
#define WCD9378_SA_UP_T0 (WCD9378_SEQR_BASE+0x40)
#define WCD9378_SA_UP_T1 (WCD9378_SEQR_BASE+0x41)
#define WCD9378_SA_UP_T2 (WCD9378_SEQR_BASE+0x42)
#define WCD9378_SA_UP_T3 (WCD9378_SEQR_BASE+0x43)
#define WCD9378_SA_UP_T4 (WCD9378_SEQR_BASE+0x44)
#define WCD9378_SA_UP_T5 (WCD9378_SEQR_BASE+0x45)
#define WCD9378_SA_UP_T6 (WCD9378_SEQR_BASE+0x46)
#define WCD9378_SA_UP_T7 (WCD9378_SEQR_BASE+0x47)
#define WCD9378_SA_DN_T0 (WCD9378_SEQR_BASE+0x48)
#define WCD9378_SA_DN_T1 (WCD9378_SEQR_BASE+0x49)
#define WCD9378_SA_DN_T2 (WCD9378_SEQR_BASE+0x4a)
#define WCD9378_SA_DN_T3 (WCD9378_SEQR_BASE+0x4b)
#define WCD9378_SA_DN_T4 (WCD9378_SEQR_BASE+0x4c)
#define WCD9378_SA_DN_T5 (WCD9378_SEQR_BASE+0x4d)
#define WCD9378_SA_DN_T6 (WCD9378_SEQR_BASE+0x4e)
#define WCD9378_SA_DN_T7 (WCD9378_SEQR_BASE+0x4f)
#define WCD9378_SA_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x50)
#define WCD9378_SA_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x51)
#define WCD9378_SA_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x52)
#define WCD9378_SA_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x53)
#define WCD9378_SA_UP_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x54)
#define WCD9378_SA_UP_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x55)
#define WCD9378_SA_UP_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x56)
#define WCD9378_SA_UP_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x57)
#define WCD9378_SA_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x58)
#define WCD9378_SA_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x59)
#define WCD9378_SA_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x5a)
#define WCD9378_SA_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x5b)
#define WCD9378_SA_DN_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x5c)
#define WCD9378_SA_DN_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x5d)
#define WCD9378_SA_DN_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x5e)
#define WCD9378_SA_DN_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x5f)
#define WCD9378_TX0_UP_T0 (WCD9378_SEQR_BASE+0x60)
#define WCD9378_TX0_UP_T1 (WCD9378_SEQR_BASE+0x61)
#define WCD9378_TX0_UP_T2 (WCD9378_SEQR_BASE+0x62)
#define WCD9378_TX0_UP_T3 (WCD9378_SEQR_BASE+0x63)
#define WCD9378_TX0_DN_T0 (WCD9378_SEQR_BASE+0x64)
#define WCD9378_TX0_DN_T1 (WCD9378_SEQR_BASE+0x65)
#define WCD9378_TX0_DN_T2 (WCD9378_SEQR_BASE+0x66)
#define WCD9378_TX0_DN_T3 (WCD9378_SEQR_BASE+0x67)
#define WCD9378_TX0_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x68)
#define WCD9378_TX0_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x69)
#define WCD9378_TX0_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x6a)
#define WCD9378_TX0_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x6b)
#define WCD9378_TX0_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x6c)
#define WCD9378_TX0_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x6d)
#define WCD9378_TX0_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x6e)
#define WCD9378_TX0_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x6f)
#define WCD9378_TX1_UP_T0 (WCD9378_SEQR_BASE+0x70)
#define WCD9378_TX1_UP_T1 (WCD9378_SEQR_BASE+0x71)
#define WCD9378_TX1_UP_T2 (WCD9378_SEQR_BASE+0x72)
#define WCD9378_TX1_UP_T3 (WCD9378_SEQR_BASE+0x73)
#define WCD9378_TX1_DN_T0 (WCD9378_SEQR_BASE+0x74)
#define WCD9378_TX1_DN_T1 (WCD9378_SEQR_BASE+0x75)
#define WCD9378_TX1_DN_T2 (WCD9378_SEQR_BASE+0x76)
#define WCD9378_TX1_DN_T3 (WCD9378_SEQR_BASE+0x77)
#define WCD9378_TX1_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x78)
#define WCD9378_TX1_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x79)
#define WCD9378_TX1_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x7a)
#define WCD9378_TX1_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x7b)
#define WCD9378_TX1_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x7c)
#define WCD9378_TX1_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x7d)
#define WCD9378_TX1_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x7e)
#define WCD9378_TX1_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x7f)
#define WCD9378_TX2_UP_T0 (WCD9378_SEQR_BASE+0x80)
#define WCD9378_TX2_UP_T1 (WCD9378_SEQR_BASE+0x81)
#define WCD9378_TX2_UP_T2 (WCD9378_SEQR_BASE+0x82)
#define WCD9378_TX2_UP_T3 (WCD9378_SEQR_BASE+0x83)
#define WCD9378_TX2_DN_T0 (WCD9378_SEQR_BASE+0x84)
#define WCD9378_TX2_DN_T1 (WCD9378_SEQR_BASE+0x85)
#define WCD9378_TX2_DN_T2 (WCD9378_SEQR_BASE+0x86)
#define WCD9378_TX2_DN_T3 (WCD9378_SEQR_BASE+0x87)
#define WCD9378_TX2_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x88)
#define WCD9378_TX2_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x89)
#define WCD9378_TX2_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x8a)
#define WCD9378_TX2_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x8b)
#define WCD9378_TX2_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x8c)
#define WCD9378_TX2_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x8d)
#define WCD9378_TX2_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x8e)
#define WCD9378_TX2_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x8f)
#define WCD9378_SEQ_HPH_STAT (WCD9378_SEQR_BASE+0x90)
#define WCD9378_SEQ_SA_STAT (WCD9378_SEQR_BASE+0x91)
#define WCD9378_SEQ_TX0_STAT (WCD9378_SEQR_BASE+0x92)
#define WCD9378_SEQ_TX1_STAT (WCD9378_SEQR_BASE+0x93)
#define WCD9378_SEQ_TX2_STAT (WCD9378_SEQR_BASE+0x94)
#define WCD9378_MICB_REMAP_TABLE_VAL_0 (WCD9378_SEQR_BASE+0xa0)
#define WCD9378_MICB_REMAP_TABLE_VAL_1 (WCD9378_SEQR_BASE+0xa1)
#define WCD9378_MICB_REMAP_TABLE_VAL_2 (WCD9378_SEQR_BASE+0xa2)
#define WCD9378_MICB_REMAP_TABLE_VAL_3 (WCD9378_SEQR_BASE+0xa3)
#define WCD9378_MICB_REMAP_TABLE_VAL_4 (WCD9378_SEQR_BASE+0xa4)
#define WCD9378_MICB_REMAP_TABLE_VAL_5 (WCD9378_SEQR_BASE+0xa5)
#define WCD9378_MICB_REMAP_TABLE_VAL_6 (WCD9378_SEQR_BASE+0xa6)
#define WCD9378_MICB_REMAP_TABLE_VAL_7 (WCD9378_SEQR_BASE+0xa7)
#define WCD9378_MICB_REMAP_TABLE_VAL_8 (WCD9378_SEQR_BASE+0xa8)
#define WCD9378_MICB_REMAP_TABLE_VAL_9 (WCD9378_SEQR_BASE+0xa9)
#define WCD9378_MICB_REMAP_TABLE_VAL_10 (WCD9378_SEQR_BASE+0xaa)
#define WCD9378_MICB_REMAP_TABLE_VAL_11 (WCD9378_SEQR_BASE+0xab)
#define WCD9378_MICB_REMAP_TABLE_VAL_12 (WCD9378_SEQR_BASE+0xac)
#define WCD9378_MICB_REMAP_TABLE_VAL_13 (WCD9378_SEQR_BASE+0xad)
#define WCD9378_MICB_REMAP_TABLE_VAL_14 (WCD9378_SEQR_BASE+0xae)
#define WCD9378_MICB_REMAP_TABLE_VAL_15 (WCD9378_SEQR_BASE+0xaf)
#define WCD9378_SM0_MB_SEL (WCD9378_SEQR_BASE+0xb0)
#define WCD9378_SM1_MB_SEL (WCD9378_SEQR_BASE+0xb1)
#define WCD9378_SM2_MB_SEL (WCD9378_SEQR_BASE+0xb2)
#define WCD9378_MB_PULLUP_EN (WCD9378_SEQR_BASE+0xb3)
#define WCD9378_BYP_EN_CTL0 (WCD9378_SEQR_BASE+0xc0)
#define WCD9378_BYP_EN_CTL1 (WCD9378_SEQR_BASE+0xc1)
#define WCD9378_BYP_EN_CTL2 (WCD9378_SEQR_BASE+0xc2)
#define WCD9378_SEQ_OVRRIDE_CTL0 (WCD9378_SEQR_BASE+0xc3)
#define WCD9378_SEQ_OVRRIDE_CTL1 (WCD9378_SEQR_BASE+0xc4)
#define WCD9378_SEQ_OVRRIDE_CTL2 (WCD9378_SEQR_BASE+0xc5)
#define WCD9378_HPH_SEQ_OVRRIDE_CTL0 (WCD9378_SEQR_BASE+0xc7)
#define WCD9378_HPH_SEQ_OVRRIDE_CTL1 (WCD9378_SEQR_BASE+0xc8)
#define WCD9378_SA_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xc9)
#define WCD9378_TX0_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xca)
#define WCD9378_TX1_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xcb)
#define WCD9378_TX2_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xcc)
#define WCD9378_FORCE_CTL (WCD9378_SEQR_BASE+0xcd)
#define WCD9378_MBHC_BASE (WCD9378_BASE+0x180601)
#define WCD9378_DEVICE_DET (WCD9378_MBHC_BASE+0x01)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x10)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0 (WCD9378_MBHC_BASE+0x11)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x12)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x13)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x14)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0 (WCD9378_MBHC_BASE+0x15)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x20)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1 (WCD9378_MBHC_BASE+0x21)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x22)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x23)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x24)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1 (WCD9378_MBHC_BASE+0x25)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x30)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2 (WCD9378_MBHC_BASE+0x31)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x32)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x33)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x34)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2 (WCD9378_MBHC_BASE+0x35)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x40)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3 (WCD9378_MBHC_BASE+0x41)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x42)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x43)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x44)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3 (WCD9378_MBHC_BASE+0x45)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x50)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0 (WCD9378_MBHC_BASE+0x51)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x52)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x53)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x54)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0 (WCD9378_MBHC_BASE+0x55)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x56)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x57)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x58)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0 (WCD9378_MBHC_BASE+0x59)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x5b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0 (WCD9378_MBHC_BASE+0x5c)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x60)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1 (WCD9378_MBHC_BASE+0x61)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x62)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x63)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x64)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1 (WCD9378_MBHC_BASE+0x65)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x66)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x67)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x68)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1 (WCD9378_MBHC_BASE+0x69)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x6b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1 (WCD9378_MBHC_BASE+0x6c)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x70)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2 (WCD9378_MBHC_BASE+0x71)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x72)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x73)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x74)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2 (WCD9378_MBHC_BASE+0x75)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x76)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x77)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x78)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2 (WCD9378_MBHC_BASE+0x79)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x7b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2 (WCD9378_MBHC_BASE+0x7c)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x80)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3 (WCD9378_MBHC_BASE+0x81)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x82)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x83)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x84)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3 (WCD9378_MBHC_BASE+0x85)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x86)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x87)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x88)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3 (WCD9378_MBHC_BASE+0x89)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x8b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3 (WCD9378_MBHC_BASE+0x8c)
#define WCD9378_SDCA_MESSAGE_GATE (WCD9378_MBHC_BASE+0x8d)
#define WCD9378_MBHC_DATA_IN_EDGE (WCD9378_MBHC_BASE+0x90)
#define WCD9378_MBHC_RESET (WCD9378_MBHC_BASE+0x91)
#define WCD9378_MBHC_DEBUG (WCD9378_MBHC_BASE+0x92)
#define WCD9378_MBHC_DEBUG_UMP_0 (WCD9378_MBHC_BASE+0x93)
#define WCD9378_MBHC_DEBUG_UMP_1 (WCD9378_MBHC_BASE+0x94)
#define WCD9378_MBHC_DEBUG_UMP_2 (WCD9378_MBHC_BASE+0x95)
#define WCD9378_HID_BASE (WCD9378_BASE+0x400001)
#define WCD9378_HID_FUNC_EXT_ID_0 (WCD9378_HID_BASE+0x48)
#define WCD9378_HID_FUNC_EXT_ID_1 (WCD9378_HID_BASE+0x49)
#define WCD9378_HID_FUNC_EXT_VER (WCD9378_HID_BASE+0x50)
#define WCD9378_HID_FUNC_STAT (WCD9378_HID_BASE+0x80000)
#define WCD9378_HID_CUR_OWNER (WCD9378_HID_BASE+0x80080)
#define WCD9378_HID_MSG_OFFSET (WCD9378_HID_BASE+0x80090)
#define WCD9378_HID_MSG_LENGTH (WCD9378_HID_BASE+0x80098)
#define WCD9378_HID_DEV_MANU_ID_0 (WCD9378_HID_BASE+0x100060)
#define WCD9378_HID_DEV_MANU_ID_1 (WCD9378_HID_BASE+0x100061)
#define WCD9378_HID_DEV_PART_ID_0 (WCD9378_HID_BASE+0x100068)
#define WCD9378_HID_DEV_PART_ID_1 (WCD9378_HID_BASE+0x100069)
#define WCD9378_HID_DEV_VER (WCD9378_HID_BASE+0x100070)
#define WCD9378_SMP_AMP_BASE (WCD9378_BASE+0x800001)
#define WCD9378_SMP_AMP_FUNC_EXT_ID_0 (WCD9378_SMP_AMP_BASE+0x48)
#define WCD9378_SMP_AMP_FUNC_EXT_ID_1 (WCD9378_SMP_AMP_BASE+0x49)
#define WCD9378_SMP_AMP_FUNC_EXT_VER (WCD9378_SMP_AMP_BASE+0x50)
#define WCD9378_XU22_BYP (WCD9378_SMP_AMP_BASE+0x188)
#define WCD9378_PDE22_REQ_PS (WCD9378_SMP_AMP_BASE+0x208)
#define WCD9378_FU23_MUTE (WCD9378_SMP_AMP_BASE+0x388)
#define WCD9378_PDE23_REQ_PS (WCD9378_SMP_AMP_BASE+0x408)
#define WCD9378_SMP_AMP_FUNC_STAT (WCD9378_SMP_AMP_BASE+0x80000)
#define WCD9378_FUNC_ACT (WCD9378_SMP_AMP_BASE+0x80008)
#define WCD9378_PDE22_ACT_PS (WCD9378_SMP_AMP_BASE+0x80200)
#define WCD9378_SAPU29_PROT_MODE (WCD9378_SMP_AMP_BASE+0x80280)
#define WCD9378_SAPU29_PROT_STAT (WCD9378_SMP_AMP_BASE+0x80288)
#define WCD9378_PDE23_ACT_PS (WCD9378_SMP_AMP_BASE+0x80400)
#define WCD9378_SMP_AMP_DEV_MANU_ID_0 (WCD9378_SMP_AMP_BASE+0x100060)
#define WCD9378_SMP_AMP_DEV_MANU_ID_1 (WCD9378_SMP_AMP_BASE+0x100061)
#define WCD9378_SMP_AMP_DEV_PART_ID_0 (WCD9378_SMP_AMP_BASE+0x100068)
#define WCD9378_SMP_AMP_DEV_PART_ID_1 (WCD9378_SMP_AMP_BASE+0x100069)
#define WCD9378_SMP_AMP_DEV_VER (WCD9378_SMP_AMP_BASE+0x100070)
#define WCD9378_SMP_JACK_BASE (WCD9378_BASE+0xc00001)
#define WCD9378_CMT_GRP_MASK (WCD9378_SMP_JACK_BASE+0x08)
#define WCD9378_SMP_JACK_FUNC_EXT_ID_0 (WCD9378_SMP_JACK_BASE+0x48)
#define WCD9378_SMP_JACK_FUNC_EXT_ID_1 (WCD9378_SMP_JACK_BASE+0x49)
#define WCD9378_SMP_JACK_FUNC_EXT_VER (WCD9378_SMP_JACK_BASE+0x50)
#define WCD9378_IT41_USAGE (WCD9378_SMP_JACK_BASE+0xa0)
#define WCD9378_XU42_BYP (WCD9378_SMP_JACK_BASE+0x208)
#define WCD9378_PDE42_REQ_PS (WCD9378_SMP_JACK_BASE+0x288)
#define WCD9378_FU42_MUTE_CH1 (WCD9378_SMP_JACK_BASE+0x309)
#define WCD9378_FU42_MUTE_CH2 (WCD9378_SMP_JACK_BASE+0x30a)
#define WCD9378_FU42_CH_VOL_CH1 (WCD9378_SMP_JACK_BASE+0x311)
#define WCD9378_FU42_CH_VOL_CH2 (WCD9378_SMP_JACK_BASE+0x312)
#define WCD9378_SU43_SELECTOR (WCD9378_SMP_JACK_BASE+0x388)
#define WCD9378_SU45_SELECTOR (WCD9378_SMP_JACK_BASE+0x408)
#define WCD9378_PDE47_REQ_PS (WCD9378_SMP_JACK_BASE+0x488)
#define WCD9378_GE35_SEL_MODE (WCD9378_SMP_JACK_BASE+0x608)
#define WCD9378_GE35_DET_MODE (WCD9378_SMP_JACK_BASE+0x610)
#define WCD9378_IT31_MICB (WCD9378_SMP_JACK_BASE+0x798)
#define WCD9378_IT31_USAGE (WCD9378_SMP_JACK_BASE+0x7a0)
#define WCD9378_PDE34_REQ_PS (WCD9378_SMP_JACK_BASE+0x808)
#define WCD9378_SU45_TX_SELECTOR (WCD9378_SMP_JACK_BASE+0x908)
#define WCD9378_XU36_BYP (WCD9378_SMP_JACK_BASE+0x988)
#define WCD9378_PDE36_REQ_PS (WCD9378_SMP_JACK_BASE+0xa08)
#define WCD9378_OT36_USAGE (WCD9378_SMP_JACK_BASE+0xb20)
#define WCD9378_SMP_JACK_FUNC_STAT (WCD9378_SMP_JACK_BASE+0x80000)
#define WCD9378_SMP_JACK_FUNC_ACT (WCD9378_SMP_JACK_BASE+0x80008)
#define WCD9378_PDE42_ACT_PS (WCD9378_SMP_JACK_BASE+0x80280)
#define WCD9378_PDE47_ACT_PS (WCD9378_SMP_JACK_BASE+0x80480)
#define WCD9378_PDE34_ACT_PS (WCD9378_SMP_JACK_BASE+0x80800)
#define WCD9378_PDE36_ACT_PS (WCD9378_SMP_JACK_BASE+0x80a00)
#define WCD9378_SMP_JACK_DEV_MANU_ID_0 (WCD9378_SMP_JACK_BASE+0x100060)
#define WCD9378_SMP_JACK_DEV_MANU_ID_1 (WCD9378_SMP_JACK_BASE+0x100061)
#define WCD9378_SMP_JACK_DEV_PART_ID_0 (WCD9378_SMP_JACK_BASE+0x100068)
#define WCD9378_SMP_JACK_DEV_PART_ID_1 (WCD9378_SMP_JACK_BASE+0x100069)
#define WCD9378_SMP_JACK_DEV_VER (WCD9378_SMP_JACK_BASE+0x100070)
#define WCD9378_SMP_MIC_CTRL0_BASE (WCD9378_BASE+0x1000001)
#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x48)
#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x49)
#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL0_BASE+0x50)
#define WCD9378_IT11_MICB (WCD9378_SMP_MIC_CTRL0_BASE+0x98)
#define WCD9378_IT11_USAGE (WCD9378_SMP_MIC_CTRL0_BASE+0xa0)
#define WCD9378_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL0_BASE+0x108)
#define WCD9378_OT10_USAGE (WCD9378_SMP_MIC_CTRL0_BASE+0x3a0)
#define WCD9378_SMP_MIC_CTRL0_FUNC_STAT (WCD9378_SMP_MIC_CTRL0_BASE+0x80000)
#define WCD9378_SMP_MIC_CTRL0_FUNC_ACT (WCD9378_SMP_MIC_CTRL0_BASE+0x80008)
#define WCD9378_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL0_BASE+0x80100)
#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x100060)
#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x100061)
#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x100068)
#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x100069)
#define WCD9378_SMP_MIC_CTRL0_DEV_VER (WCD9378_SMP_MIC_CTRL0_BASE+0x100070)
#define WCD9378_SMP_MIC_CTRL1_BASE (WCD9378_BASE+0x1400001)
#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x48)
#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x49)
#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL1_BASE+0x50)
#define WCD9378_SMP_MIC_CTRL1_IT11_MICB (WCD9378_SMP_MIC_CTRL1_BASE+0x98)
#define WCD9378_SMP_MIC_CTRL1_IT11_USAGE (WCD9378_SMP_MIC_CTRL1_BASE+0xa0)
#define WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL1_BASE+0x108)
#define WCD9378_SMP_MIC_CTRL1_OT10_USAGE (WCD9378_SMP_MIC_CTRL1_BASE+0x3a0)
#define WCD9378_SMP_MIC_CTRL1_FUNC_STAT (WCD9378_SMP_MIC_CTRL1_BASE+0x80000)
#define WCD9378_SMP_MIC_CTRL1_FUNC_ACT (WCD9378_SMP_MIC_CTRL1_BASE+0x80008)
#define WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL1_BASE+0x80100)
#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x100060)
#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x100061)
#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x100068)
#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x100069)
#define WCD9378_SMP_MIC_CTRL1_DEV_VER (WCD9378_SMP_MIC_CTRL1_BASE+0x100070)
#define WCD9378_SMP_MIC_CTRL2_BASE (WCD9378_BASE+0x1800001)
#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x48)
#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x49)
#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL2_BASE+0x50)
#define WCD9378_SMP_MIC_CTRL2_IT11_MICB (WCD9378_SMP_MIC_CTRL2_BASE+0x98)
#define WCD9378_SMP_MIC_CTRL2_IT11_USAGE (WCD9378_SMP_MIC_CTRL2_BASE+0xa0)
#define WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL2_BASE+0x108)
#define WCD9378_SMP_MIC_CTRL2_OT10_USAGE (WCD9378_SMP_MIC_CTRL2_BASE+0x3a0)
#define WCD9378_SMP_MIC_CTRL2_FUNC_STAT (WCD9378_SMP_MIC_CTRL2_BASE+0x80000)
#define WCD9378_SMP_MIC_CTRL2_FUNC_ACT (WCD9378_SMP_MIC_CTRL2_BASE+0x80008)
#define WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL2_BASE+0x80100)
#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x100060)
#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x100061)
#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x100068)
#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x100069)
#define WCD9378_SMP_MIC_CTRL2_DEV_VER (WCD9378_SMP_MIC_CTRL2_BASE+0x100070)
#define WCD9378_HID_MEM_BASE (WCD9378_BASE+0x4000001)
#define WCD9378_REPORT_ID (WCD9378_HID_MEM_BASE+0x01)
#define WCD9378_MESSAGE0 (WCD9378_HID_MEM_BASE+0x02)
#define WCD9378_MESSAGE1 (WCD9378_HID_MEM_BASE+0x03)
#define WCD9378_MESSAGE2 (WCD9378_HID_MEM_BASE+0x04)
#define WCD9378_NUM_REGISTERS (WCD9378_SMP_MIC_CTRL2_DEV_VER - WCD9378_BASE + 1)
#define WCD9378_MAX_REGISTER (WCD9378_MESSAGE2 + 1)
#define WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT 0x03
#define WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT 0x00
#define WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT 0x00
#define WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT 0x03
#define WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT 0x02
#define SWRS_SCP_BASE_CLK_BASE (0x004d)
#define SWRS_SCP_BUSCLOCK_SCALE_BANK0 (0x0062)
#define SWRS_SCP_BUSCLOCK_SCALE_BANK1 (0x0072)
#define SWRS_SCP_SDCA_INTMASK_1 (0x0000005c)
#define SWRS_SCP_SDCA_INTMASK_2 (0x0000005d)
#define SWRS_SCP_SDCA_INTMASK_3 (0x0000005e)
#define SWRS_SCP_SDCA_INTSTAT_1 (0x00000058)
#define SWRS_SCP_SDCA_INTSTAT_2 (0x00000059)
#define SWRS_SCP_SDCA_INTSTAT_3 (0x0000005a)
#define SWRS_SCP_SDCA_INTRTYPE_1 (0x000000f4)
#define SWRS_SCP_SDCA_INTRTYPE_2 (0x000000f8)
#define SWRS_SCP_SDCA_INTRTYPE_3 (0x000000fc)
#endif /* WCD9378_REGISTERS_H */

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/regmap.h>
#include <linux/device.h>
#include "wcd9378-registers.h"
extern const u8 wcd9378_reg_access[WCD9378_NUM_REGISTERS];
static struct reg_default wcd9378_defaults[] = {
{SWRS_SCP_SDCA_INTSTAT_1, 0x00},
{SWRS_SCP_SDCA_INTSTAT_2, 0x00},
{SWRS_SCP_SDCA_INTSTAT_2, 0x00},
{SWRS_SCP_SDCA_INTMASK_1, 0x00},
{SWRS_SCP_SDCA_INTMASK_2, 0x00},
{SWRS_SCP_SDCA_INTMASK_3, 0x00},
{SWRS_SCP_SDCA_INTRTYPE_1, 0x00},
{SWRS_SCP_SDCA_INTRTYPE_2, 0x00},
{SWRS_SCP_SDCA_INTRTYPE_3, 0x00},
{WCD9378_FUNC_EXT_ID_0, 0x00},
{WCD9378_FUNC_EXT_ID_1, 0x00},
{WCD9378_FUNC_EXT_VER, 0x00},
{WCD9378_FUNC_STAT, 0x67},
{WCD9378_DEV_MANU_ID_0, 0x17},
{WCD9378_DEV_MANU_ID_1, 0x02},
{WCD9378_DEV_PART_ID_0, 0x10},
{WCD9378_DEV_PART_ID_1, 0x01},
{WCD9378_DEV_VER, 0x10},
{WCD9378_ANA_PAGE, 0x00},
{WCD9378_ANA_BIAS, 0x00},
{WCD9378_ANA_RX_SUPPLIES, 0x00},
{WCD9378_ANA_HPH, 0x0c},
{WCD9378_ANA_EAR, 0x00},
{WCD9378_ANA_EAR_COMPANDER_CTL, 0x02},
{WCD9378_ANA_TX_CH1, 0x20},
{WCD9378_ANA_TX_CH2, 0x00},
{WCD9378_ANA_TX_CH3, 0x20},
{WCD9378_ANA_TX_CH3_HPF, 0x00},
{WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
{WCD9378_ANA_MICB3_DSP_EN_LOGIC, 0x00},
{WCD9378_ANA_MBHC_MECH, 0x39},
{WCD9378_ANA_MBHC_ELECT, 0x08},
{WCD9378_ANA_MBHC_ZDET, 0x00},
{WCD9378_ANA_MBHC_RESULT_1, 0x00},
{WCD9378_ANA_MBHC_RESULT_2, 0x00},
{WCD9378_ANA_MBHC_RESULT_3, 0x00},
{WCD9378_ANA_MBHC_BTN0, 0x00},
{WCD9378_ANA_MBHC_BTN1, 0x10},
{WCD9378_ANA_MBHC_BTN2, 0x20},
{WCD9378_ANA_MBHC_BTN3, 0x30},
{WCD9378_ANA_MBHC_BTN4, 0x40},
{WCD9378_ANA_MBHC_BTN5, 0x50},
{WCD9378_ANA_MBHC_BTN6, 0x60},
{WCD9378_ANA_MBHC_BTN7, 0x70},
{WCD9378_ANA_MICB1, 0x10},
{WCD9378_ANA_MICB2, 0x10},
{WCD9378_ANA_MICB2_RAMP, 0x00},
{WCD9378_ANA_MICB3, 0x00},
{WCD9378_BIAS_CTL, 0x2a},
{WCD9378_BIAS_VBG_FINE_ADJ, 0x55},
{WCD9378_LDOL_VDDCX_ADJUST, 0x01},
{WCD9378_LDOL_DISABLE_LDOL, 0x00},
{WCD9378_MBHC_CTL_CLK, 0x00},
{WCD9378_MBHC_CTL_ANA, 0x00},
{WCD9378_MBHC_CTL_SPARE_1, 0x02},
{WCD9378_MBHC_CTL_SPARE_2, 0x00},
{WCD9378_MBHC_CTL_BCS, 0x00},
{WCD9378_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
{WCD9378_MBHC_TEST_CTL, 0x00},
{WCD9378_LDOH_MODE, 0x2b},
{WCD9378_LDOH_BIAS, 0x68},
{WCD9378_LDOH_STB_LOADS, 0x00},
{WCD9378_LDOH_SLOWRAMP, 0x50},
{WCD9378_MICB1_TEST_CTL_1, 0x1a},
{WCD9378_MICB1_TEST_CTL_2, 0x00},
{WCD9378_MICB1_TEST_CTL_3, 0xa4},
{WCD9378_MICB2_TEST_CTL_1, 0x1a},
{WCD9378_MICB2_TEST_CTL_2, 0x00},
{WCD9378_MICB2_TEST_CTL_3, 0x24},
{WCD9378_MICB3_TEST_CTL_1, 0x9a},
{WCD9378_MICB3_TEST_CTL_2, 0x80},
{WCD9378_MICB3_TEST_CTL_3, 0x24},
{WCD9378_TX_COM_ADC_VCM, 0x39},
{WCD9378_TX_COM_BIAS_ATEST, 0xe0},
{WCD9378_TX_COM_SPARE1, 0x00},
{WCD9378_TX_COM_SPARE2, 0x00},
{WCD9378_TX_COM_TXFE_DIV_CTL, 0x22},
{WCD9378_TX_COM_TXFE_DIV_START, 0x00},
{WCD9378_TX_COM_SPARE3, 0x00},
{WCD9378_TX_COM_SPARE4, 0x00},
{WCD9378_TX_1_2_TEST_EN, 0xcc},
{WCD9378_TX_1_2_ADC_IB, 0xe9},
{WCD9378_TX_1_2_ATEST_REFCTL, 0x0b},
{WCD9378_TX_1_2_TEST_CTL, 0x38},
{WCD9378_TX_1_2_TEST_BLK_EN1, 0xff},
{WCD9378_TX_1_2_TXFE1_CLKDIV, 0x00},
{WCD9378_TX_1_2_SAR2_ERR, 0x00},
{WCD9378_TX_1_2_SAR1_ERR, 0x00},
{WCD9378_TX_3_TEST_EN, 0xcc},
{WCD9378_TX_3_ADC_IB, 0xe9},
{WCD9378_TX_3_ATEST_REFCTL, 0x0b},
{WCD9378_TX_3_TEST_CTL, 0x38},
{WCD9378_TX_3_TEST_BLK_EN3, 0xff},
{WCD9378_TX_3_TXFE3_CLKDIV, 0x00},
{WCD9378_TX_3_SAR4_ERR, 0x00},
{WCD9378_TX_3_SAR3_ERR, 0x00},
{WCD9378_TX_3_TEST_BLK_EN2, 0xfb},
{WCD9378_TX_3_TXFE2_CLKDIV, 0x00},
{WCD9378_TX_3_SPARE1, 0x00},
{WCD9378_TX_3_TEST_BLK_EN4, 0xfb},
{WCD9378_TX_3_SPARE2, 0x00},
{WCD9378_TX_3_SPARE3, 0x00},
{WCD9378_RX_AUX_SW_CTL, 0x00},
{WCD9378_RX_PA_AUX_IN_CONN, 0x00},
{WCD9378_RX_TIMER_DIV, 0x32},
{WCD9378_RX_OCP_CTL, 0x1f},
{WCD9378_RX_OCP_COUNT, 0x77},
{WCD9378_RX_BIAS_EAR_DAC, 0xa0},
{WCD9378_RX_BIAS_EAR_AMP, 0xaa},
{WCD9378_RX_BIAS_HPH_LDO, 0xa9},
{WCD9378_RX_BIAS_HPH_PA, 0xaa},
{WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8a},
{WCD9378_RX_BIAS_HPH_RDAC_LDO, 0x88},
{WCD9378_RX_BIAS_HPH_CNP1, 0x82},
{WCD9378_RX_BIAS_HPH_LOWPOWER, 0x82},
{WCD9378_RX_BIAS_AUX_DAC, 0xa0},
{WCD9378_RX_BIAS_AUX_AMP, 0xaa},
{WCD9378_RX_SPARE_1, 0x50},
{WCD9378_RX_SPARE_2, 0x00},
{WCD9378_RX_SPARE_3, 0x08},
{WCD9378_RX_SPARE_4, 0x44},
{WCD9378_RX_SPARE_5, 0x40},
{WCD9378_RX_SPARE_6, 0xaa},
{WCD9378_RX_SPARE_7, 0x14},
{WCD9378_HPH_L_STATUS, 0x04},
{WCD9378_HPH_R_STATUS, 0x04},
{WCD9378_HPH_CNP_EN, 0x80},
{WCD9378_HPH_CNP_WG_CTL, 0x9a},
{WCD9378_HPH_CNP_WG_TIME, 0x14},
{WCD9378_HPH_OCP_CTL, 0x28},
{WCD9378_HPH_AUTO_CHOP, 0x16},
{WCD9378_HPH_CHOP_CTL, 0x83},
{WCD9378_HPH_PA_CTL1, 0x46},
{WCD9378_HPH_PA_CTL2, 0x50},
{WCD9378_HPH_L_EN, 0x80},
{WCD9378_HPH_L_TEST, 0xe0},
{WCD9378_HPH_L_ATEST, 0x50},
{WCD9378_HPH_R_EN, 0x80},
{WCD9378_HPH_R_TEST, 0xe0},
{WCD9378_HPH_R_ATEST, 0x54},
{WCD9378_HPH_RDAC_CLK_CTL1, 0x99},
{WCD9378_HPH_RDAC_CLK_CTL2, 0x9b},
{WCD9378_HPH_RDAC_LDO_CTL, 0x33},
{WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
{WCD9378_HPH_REFBUFF_UHQA_CTL, 0xa8},
{WCD9378_HPH_REFBUFF_LP_CTL, 0x0e},
{WCD9378_HPH_L_DAC_CTL, 0x20},
{WCD9378_HPH_R_DAC_CTL, 0x20},
{WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
{WCD9378_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
{WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1, 0xa0},
{WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
{WCD9378_EAR_EAR_EN_REG, 0x22},
{WCD9378_EAR_EAR_PA_CON, 0x44},
{WCD9378_EAR_EAR_SP_CON, 0xdb},
{WCD9378_EAR_EAR_DAC_CON, 0x80},
{WCD9378_EAR_EAR_CNP_FSM_CON, 0xb2},
{WCD9378_EAR_TEST_CTL, 0x00},
{WCD9378_EAR_STATUS_REG_1, 0x00},
{WCD9378_EAR_STATUS_REG_2, 0x00},
{WCD9378_ANA_NEW_PAGE, 0x00},
{WCD9378_HPH_NEW_ANA_HPH2, 0x00},
{WCD9378_HPH_NEW_ANA_HPH3, 0x00},
{WCD9378_SLEEP_CTL, 0x16},
{WCD9378_SLEEP_WATCHDOG_CTL, 0x00},
{WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
{WCD9378_MBHC_NEW_CTL_1, 0x0e},
{WCD9378_MBHC_NEW_CTL_2, 0x05},
{WCD9378_MBHC_NEW_PLUG_DETECT_CTL, 0xe9},
{WCD9378_MBHC_NEW_ZDET_ANA_CTL, 0x0f},
{WCD9378_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
{WCD9378_MBHC_NEW_FSM_STATUS, 0x00},
{WCD9378_MBHC_NEW_ADC_RESULT, 0x00},
{WCD9378_AUX_AUXPA, 0x00},
{WCD9378_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
{WCD9378_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
{WCD9378_TX_NEW_TX_CH12_MUX, 0x11},
{WCD9378_TX_NEW_TX_CH34_MUX, 0x23},
{WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
{WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
{WCD9378_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
{WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
{WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
{WCD9378_HPH_NEW_INT_PA_MISC1, 0x22},
{WCD9378_HPH_NEW_INT_PA_MISC2, 0x00},
{WCD9378_HPH_NEW_INT_PA_RDAC_MISC, 0x01},
{WCD9378_HPH_NEW_INT_HPH_TIMER1, 0xfe},
{WCD9378_HPH_NEW_INT_HPH_TIMER2, 0x02},
{WCD9378_HPH_NEW_INT_HPH_TIMER3, 0x4e},
{WCD9378_HPH_NEW_INT_HPH_TIMER4, 0x54},
{WCD9378_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
{WCD9378_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
{WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
{WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
{WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
{WCD9378_CP_CLASSG_CP_CTRL_0, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_1, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_2, 0x23},
{WCD9378_CP_CLASSG_CP_CTRL_3, 0x03},
{WCD9378_CP_CLASSG_CP_CTRL_4, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_5, 0x0a},
{WCD9378_CP_CLASSG_CP_CTRL_6, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_7, 0x00},
{WCD9378_CP_VNEGDAC_CTRL_0, 0x23},
{WCD9378_CP_VNEGDAC_CTRL_1, 0x00},
{WCD9378_CP_VNEGDAC_CTRL_2, 0x00},
{WCD9378_CP_VNEGDAC_CTRL_3, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_0, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_1, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_2, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_3, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_4, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_5, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_6, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_7, 0x03},
{WCD9378_CP_CP_DTOP_CTRL_8, 0x33},
{WCD9378_CP_CP_DTOP_CTRL_9, 0x63},
{WCD9378_CP_CP_DTOP_CTRL_10, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_11, 0x03},
{WCD9378_CP_CP_DTOP_CTRL_12, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_13, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_14, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_15, 0xff},
{WCD9378_CP_CP_DTOP_CTRL_16, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_17, 0x06},
{WCD9378_CP_CP_DTOP_CTRL_18, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_19, 0x00},
{WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
{WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
{WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
{WCD9378_MBHC_NEW_INT_SPARE_2, 0x00},
{WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON, 0xa8},
{WCD9378_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
{WCD9378_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
{WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
{WCD9378_AUX_INT_EN_REG, 0x00},
{WCD9378_AUX_INT_PA_CTRL, 0x06},
{WCD9378_AUX_INT_SP_CTRL, 0xd2},
{WCD9378_AUX_INT_DAC_CTRL, 0x80},
{WCD9378_AUX_INT_CLK_CTRL, 0x50},
{WCD9378_AUX_INT_TEST_CTRL, 0x00},
{WCD9378_AUX_INT_STATUS_REG, 0x00},
{WCD9378_AUX_INT_MISC, 0x00},
{WCD9378_SLEEP_INT_WATCHDOG_CTL_1, 0x0a},
{WCD9378_SLEEP_INT_WATCHDOG_CTL_2, 0x0a},
{WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
{WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xff},
{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7f},
{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3f},
{WCD9378_TX_COM_NEW_INT_SPARE1, 0x1f},
{WCD9378_TX_COM_NEW_INT_SPARE2, 0x0f},
{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2, 0xd7},
{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1, 0xc8},
{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0, 0xc6},
{WCD9378_TX_COM_NEW_INT_SPARE3, 0x95},
{WCD9378_TX_COM_NEW_INT_SPARE4, 0x6a},
{WCD9378_TX_COM_NEW_INT_SPARE5, 0x05},
{WCD9378_TX_COM_NEW_INT_SPARE6, 0xa5},
{WCD9378_TX_COM_NEW_INT_SPARE7, 0x13},
{WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
{WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0, 0x42},
{WCD9378_TX_COM_NEW_INT_TXADC_INT_L2, 0xff},
{WCD9378_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
{WCD9378_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
{WCD9378_TX_COM_NEW_INT_SPARE8, 0x77},
{WCD9378_TAMBORA_PAGE, 0x00},
{WCD9378_CHIP_ID0, 0x00},
{WCD9378_CHIP_ID1, 0x00},
{WCD9378_CHIP_ID2, 0x10},
{WCD9378_CHIP_ID3, 0x01},
{WCD9378_SWR_TX_CLK_RATE, 0x00},
{WCD9378_CDC_RST_CTL, 0x03},
{WCD9378_TOP_CLK_CFG, 0x00},
{WCD9378_CDC_ANA_CLK_CTL, 0x00},
{WCD9378_CDC_DIG_CLK_CTL, 0x70},
{WCD9378_SWR_RST_EN, 0x1f},
{WCD9378_CDC_PATH_MODE, 0x00},
{WCD9378_CDC_RX_RST, 0x00},
{WCD9378_CDC_RX0_CTL, 0xfc},
{WCD9378_CDC_RX1_CTL, 0xfc},
{WCD9378_CDC_RX2_CTL, 0xfc},
{WCD9378_CDC_TX_ANA_MODE_0_1, 0x00},
{WCD9378_CDC_TX_ANA_MODE_2_3, 0x00},
{WCD9378_CDC_COMP_CTL_0, 0x00},
{WCD9378_CDC_ANA_TX_CLK_CTL, 0x0e},
{WCD9378_CDC_HPH_DSM_A1_0, 0x00},
{WCD9378_CDC_HPH_DSM_A1_1, 0x01},
{WCD9378_CDC_HPH_DSM_A2_0, 0x63},
{WCD9378_CDC_HPH_DSM_A2_1, 0x04},
{WCD9378_CDC_HPH_DSM_A3_0, 0xac},
{WCD9378_CDC_HPH_DSM_A3_1, 0x04},
{WCD9378_CDC_HPH_DSM_A4_0, 0x1a},
{WCD9378_CDC_HPH_DSM_A4_1, 0x03},
{WCD9378_CDC_HPH_DSM_A5_0, 0xbc},
{WCD9378_CDC_HPH_DSM_A5_1, 0x02},
{WCD9378_CDC_HPH_DSM_A6_0, 0xc7},
{WCD9378_CDC_HPH_DSM_A7_0, 0xf8},
{WCD9378_CDC_HPH_DSM_C_0, 0x47},
{WCD9378_CDC_HPH_DSM_C_1, 0x43},
{WCD9378_CDC_HPH_DSM_C_2, 0xb1},
{WCD9378_CDC_HPH_DSM_C_3, 0x17},
{WCD9378_CDC_HPH_DSM_R1, 0x4d},
{WCD9378_CDC_HPH_DSM_R2, 0x29},
{WCD9378_CDC_HPH_DSM_R3, 0x34},
{WCD9378_CDC_HPH_DSM_R4, 0x59},
{WCD9378_CDC_HPH_DSM_R5, 0x66},
{WCD9378_CDC_HPH_DSM_R6, 0x87},
{WCD9378_CDC_HPH_DSM_R7, 0x64},
{WCD9378_CDC_AUX_DSM_A1_0, 0x00},
{WCD9378_CDC_AUX_DSM_A1_1, 0x01},
{WCD9378_CDC_AUX_DSM_A2_0, 0x96},
{WCD9378_CDC_AUX_DSM_A2_1, 0x09},
{WCD9378_CDC_AUX_DSM_A3_0, 0xab},
{WCD9378_CDC_AUX_DSM_A3_1, 0x05},
{WCD9378_CDC_AUX_DSM_A4_0, 0x1c},
{WCD9378_CDC_AUX_DSM_A4_1, 0x02},
{WCD9378_CDC_AUX_DSM_A5_0, 0x17},
{WCD9378_CDC_AUX_DSM_A5_1, 0x02},
{WCD9378_CDC_AUX_DSM_A6_0, 0xaa},
{WCD9378_CDC_AUX_DSM_A7_0, 0xe3},
{WCD9378_CDC_AUX_DSM_C_0, 0x69},
{WCD9378_CDC_AUX_DSM_C_1, 0x54},
{WCD9378_CDC_AUX_DSM_C_2, 0x02},
{WCD9378_CDC_AUX_DSM_C_3, 0x15},
{WCD9378_CDC_AUX_DSM_R1, 0xa4},
{WCD9378_CDC_AUX_DSM_R2, 0xb5},
{WCD9378_CDC_AUX_DSM_R3, 0x86},
{WCD9378_CDC_AUX_DSM_R4, 0x85},
{WCD9378_CDC_AUX_DSM_R5, 0xaa},
{WCD9378_CDC_AUX_DSM_R6, 0xe2},
{WCD9378_CDC_AUX_DSM_R7, 0x62},
{WCD9378_CDC_HPH_GAIN_RX_0, 0x55},
{WCD9378_CDC_HPH_GAIN_RX_1, 0xa9},
{WCD9378_CDC_HPH_GAIN_DSD_0, 0x3d},
{WCD9378_CDC_HPH_GAIN_DSD_1, 0x2e},
{WCD9378_CDC_HPH_GAIN_DSD_2, 0x01},
{WCD9378_CDC_AUX_GAIN_DSD_0, 0x00},
{WCD9378_CDC_AUX_GAIN_DSD_1, 0xfc},
{WCD9378_CDC_AUX_GAIN_DSD_2, 0x01},
{WCD9378_CDC_HPH_GAIN_CTL, 0x00},
{WCD9378_CDC_AUX_GAIN_CTL, 0x00},
{WCD9378_CDC_PATH_CTL, 0x00},
{WCD9378_CDC_SWR_CLG, 0x00},
{WCD9378_SWR_CLG_BYP, 0x00},
{WCD9378_CDC_TX0_CTL, 0x68},
{WCD9378_CDC_TX1_CTL, 0x68},
{WCD9378_CDC_TX2_CTL, 0x68},
{WCD9378_CDC_TX_RST, 0x00},
{WCD9378_CDC_REQ_CTL, 0x01},
{WCD9378_CDC_RST, 0x00},
{WCD9378_CDC_AMIC_CTL, 0x07},
{WCD9378_CDC_DMIC_CTL, 0x04},
{WCD9378_CDC_DMIC1_CTL, 0x01},
{WCD9378_CDC_DMIC2_CTL, 0x01},
{WCD9378_CDC_DMIC3_CTL, 0x01},
{WCD9378_EFUSE_PRG_CTL, 0x00},
{WCD9378_EFUSE_CTL, 0x2b},
{WCD9378_CDC_DMIC_RATE_1_2, 0x11},
{WCD9378_CDC_DMIC_RATE_3_4, 0x01},
{WCD9378_PDM_WD_EN_OVRD, 0x00},
{WCD9378_PDM_WD_CTL0, 0x0f},
{WCD9378_PDM_WD_CTL1, 0x0f},
{WCD9378_PDM_WD_CTL2, 0x01},
{WCD9378_RAMP_CTL, 0x07},
{WCD9378_ACT_DET_CTL, 0x00},
{WCD9378_ACT_DET_HOOKUP0, 0x00},
{WCD9378_ACT_DET_HOOKUP1, 0x07},
{WCD9378_ACT_DET_HOOKUP2, 0x00},
{WCD9378_ACT_DET_DLY_BUF_EN, 0x1f},
{WCD9378_INTR_MODE, 0x00},
{WCD9378_INTR_STATUS_0, 0x00},
{WCD9378_INTR_STATUS_1, 0x00},
{WCD9378_INTR_STATUS_2, 0x00},
{WCD9378_INTR_STATUS_3, 0x00},
{WCD9378_INTR_MASK_0, 0xff},
{WCD9378_INTR_MASK_1, 0xff},
{WCD9378_INTR_MASK_2, 0x3f},
{WCD9378_INTR_MASK_3, 0x00},
{WCD9378_INTR_SET_0, 0x00},
{WCD9378_INTR_SET_1, 0x00},
{WCD9378_INTR_SET_2, 0x00},
{WCD9378_INTR_SET_3, 0x00},
{WCD9378_INTR_TEST_0, 0x00},
{WCD9378_INTR_TEST_1, 0x00},
{WCD9378_INTR_TEST_2, 0x00},
{WCD9378_INTR_TEST_3, 0x3e},
{WCD9378_TX_MODE_DBG_EN, 0x00},
{WCD9378_TX_MODE_DBG_0_1, 0x00},
{WCD9378_TX_MODE_DBG_2_3, 0x00},
{WCD9378_LB_IN_SEL_CTL, 0x00},
{WCD9378_LOOP_BACK_MODE, 0x00},
{WCD9378_SWR_DAC_TEST, 0x00},
{WCD9378_SWR_HM_TEST_RX_0, 0x40},
{WCD9378_SWR_HM_TEST_TX_0, 0x40},
{WCD9378_SWR_HM_TEST_RX_1, 0x00},
{WCD9378_SWR_HM_TEST_TX_1, 0x00},
{WCD9378_SWR_HM_TEST_0, 0x00},
{WCD9378_PAD_CTL_SWR_0, 0x8f},
{WCD9378_PAD_CTL_SWR_1, 0x06},
{WCD9378_I2C_CTL, 0x00},
{WCD9378_LEGACY_SW_MODE, 0x00},
{WCD9378_EFUSE_TEST_CTL_0, 0x00},
{WCD9378_EFUSE_TEST_CTL_1, 0x00},
{WCD9378_EFUSE_T_DATA_0, 0x00},
{WCD9378_PAD_CTL_PDM_RX0, 0xf1},
{WCD9378_PAD_CTL_PDM_RX1, 0xf1},
{WCD9378_PAD_CTL_PDM_TX0, 0xf1},
{WCD9378_PAD_CTL_PDM_TX1, 0xf1},
{WCD9378_PAD_INP_DIS_0, 0x2a},
{WCD9378_DRIVE_STRENGTH_0, 0x00},
{WCD9378_DRIVE_STRENGTH_1, 0x00},
{WCD9378_RX_DATA_EDGE_CTL, 0x1c},
{WCD9378_TX_DATA_EDGE_CTL, 0x10},
{WCD9378_GPIO_MODE, 0x00},
{WCD9378_PIN_CTL_OE, 0x00},
{WCD9378_PIN_CTL_DATA_0, 0x00},
{WCD9378_PIN_STATUS_0, 0x00},
{WCD9378_DIG_DEBUG_CTL, 0x00},
{WCD9378_DIG_DEBUG_EN, 0x00},
{WCD9378_ANA_CSR_DBG_ADD, 0x00},
{WCD9378_ANA_CSR_DBG_CTL, 0x48},
{WCD9378_SSP_DBG, 0x00},
{WCD9378_MODE_STATUS_0, 0x00},
{WCD9378_MODE_STATUS_1, 0x00},
{WCD9378_SPARE_0, 0x00},
{WCD9378_SPARE_1, 0x00},
{WCD9378_SPARE_2, 0x00},
{WCD9378_EFUSE_REG_0, 0x00},
{WCD9378_EFUSE_REG_1, 0xff},
{WCD9378_EFUSE_REG_2, 0xff},
{WCD9378_EFUSE_REG_3, 0xff},
{WCD9378_EFUSE_REG_4, 0xff},
{WCD9378_EFUSE_REG_5, 0xff},
{WCD9378_EFUSE_REG_6, 0xff},
{WCD9378_EFUSE_REG_7, 0xff},
{WCD9378_EFUSE_REG_8, 0xff},
{WCD9378_EFUSE_REG_9, 0xff},
{WCD9378_EFUSE_REG_10, 0xff},
{WCD9378_EFUSE_REG_11, 0xff},
{WCD9378_EFUSE_REG_12, 0xff},
{WCD9378_EFUSE_REG_13, 0xff},
{WCD9378_EFUSE_REG_14, 0xff},
{WCD9378_EFUSE_REG_15, 0xff},
{WCD9378_EFUSE_REG_16, 0xff},
{WCD9378_EFUSE_REG_17, 0xff},
{WCD9378_EFUSE_REG_18, 0xff},
{WCD9378_EFUSE_REG_19, 0xff},
{WCD9378_EFUSE_REG_20, 0x0e},
{WCD9378_EFUSE_REG_21, 0x00},
{WCD9378_EFUSE_REG_22, 0x00},
{WCD9378_EFUSE_REG_23, 0xf6},
{WCD9378_EFUSE_REG_24, 0x17},
{WCD9378_EFUSE_REG_25, 0x00},
{WCD9378_EFUSE_REG_26, 0x00},
{WCD9378_EFUSE_REG_27, 0x00},
{WCD9378_EFUSE_REG_28, 0x00},
{WCD9378_EFUSE_REG_29, 0x00},
{WCD9378_EFUSE_REG_30, 0x09},
{WCD9378_EFUSE_REG_31, 0xf6},
{WCD9378_TX_REQ_FB_CTL_2, 0x11},
{WCD9378_TX_REQ_FB_CTL_3, 0x00},
{WCD9378_TX_REQ_FB_CTL_4, 0x00},
{WCD9378_DEM_BYPASS_DATA0, 0x55},
{WCD9378_DEM_BYPASS_DATA1, 0x55},
{WCD9378_DEM_BYPASS_DATA2, 0x55},
{WCD9378_DEM_BYPASS_DATA3, 0x01},
{WCD9378_RX0_PCM_RAMP_STEP, 0x05},
{WCD9378_RX0_DSD_RAMP_STEP, 0x0e},
{WCD9378_RX1_PCM_RAMP_STEP, 0x05},
{WCD9378_RX1_DSD_RAMP_STEP, 0x0e},
{WCD9378_RX2_RAMP_STEP, 0x0e},
{WCD9378_PLATFORM_CTL, 0x01},
{WCD9378_CLK_DIV_CFG, 0x03},
{WCD9378_DRE_DLY_VAL, 0x88},
{WCD9378_SYS_USAGE_CTRL, 0x00},
{WCD9378_SURGE_CTL, 0x00},
{WCD9378_SEQ_CTL, 0x00},
{WCD9378_HPH_UP_T0, 0x02},
{WCD9378_HPH_UP_T1, 0x02},
{WCD9378_HPH_UP_T2, 0x02},
{WCD9378_HPH_UP_T3, 0x02},
{WCD9378_HPH_UP_T4, 0x02},
{WCD9378_HPH_UP_T5, 0x03},
{WCD9378_HPH_UP_T6, 0x02},
{WCD9378_HPH_UP_T7, 0x06},
{WCD9378_HPH_UP_T8, 0x02},
{WCD9378_HPH_UP_T9, 0x02},
{WCD9378_HPH_UP_T10, 0x00},
{WCD9378_HPH_DN_T0, 0x05},
{WCD9378_HPH_DN_T1, 0x06},
{WCD9378_HPH_DN_T2, 0x02},
{WCD9378_HPH_DN_T3, 0x02},
{WCD9378_HPH_DN_T4, 0x02},
{WCD9378_HPH_DN_T5, 0x02},
{WCD9378_HPH_DN_T6, 0x02},
{WCD9378_HPH_DN_T7, 0x02},
{WCD9378_HPH_DN_T8, 0x02},
{WCD9378_HPH_DN_T9, 0x02},
{WCD9378_HPH_DN_T10, 0x02},
{WCD9378_HPH_UP_STAGE_LOC_0, 0x00},
{WCD9378_HPH_UP_STAGE_LOC_1, 0x01},
{WCD9378_HPH_UP_STAGE_LOC_2, 0x02},
{WCD9378_HPH_UP_STAGE_LOC_3, 0x03},
{WCD9378_HPH_UP_STAGE_LOC_4, 0x04},
{WCD9378_HPH_UP_STAGE_LOC_5, 0x05},
{WCD9378_HPH_UP_STAGE_LOC_6, 0x06},
{WCD9378_HPH_UP_STAGE_LOC_7, 0x07},
{WCD9378_HPH_UP_STAGE_LOC_8, 0x08},
{WCD9378_HPH_UP_STAGE_LOC_9, 0x09},
{WCD9378_HPH_UP_STAGE_LOC_10, 0x0a},
{WCD9378_HPH_DN_STAGE_LOC_0, 0x08},
{WCD9378_HPH_DN_STAGE_LOC_1, 0x09},
{WCD9378_HPH_DN_STAGE_LOC_2, 0x06},
{WCD9378_HPH_DN_STAGE_LOC_3, 0x05},
{WCD9378_HPH_DN_STAGE_LOC_4, 0x04},
{WCD9378_HPH_DN_STAGE_LOC_5, 0x03},
{WCD9378_HPH_DN_STAGE_LOC_6, 0x07},
{WCD9378_HPH_DN_STAGE_LOC_7, 0x01},
{WCD9378_HPH_DN_STAGE_LOC_8, 0x02},
{WCD9378_HPH_DN_STAGE_LOC_9, 0x0a},
{WCD9378_HPH_DN_STAGE_LOC_10, 0x00},
{WCD9378_SA_UP_T0, 0x02},
{WCD9378_SA_UP_T1, 0x02},
{WCD9378_SA_UP_T2, 0x02},
{WCD9378_SA_UP_T3, 0x02},
{WCD9378_SA_UP_T4, 0x02},
{WCD9378_SA_UP_T5, 0x06},
{WCD9378_SA_UP_T6, 0x02},
{WCD9378_SA_UP_T7, 0x00},
{WCD9378_SA_DN_T0, 0x05},
{WCD9378_SA_DN_T1, 0x06},
{WCD9378_SA_DN_T2, 0x02},
{WCD9378_SA_DN_T3, 0x02},
{WCD9378_SA_DN_T4, 0x02},
{WCD9378_SA_DN_T5, 0x03},
{WCD9378_SA_DN_T6, 0x02},
{WCD9378_SA_DN_T7, 0x06},
{WCD9378_SA_UP_STAGE_LOC_0, 0x00},
{WCD9378_SA_UP_STAGE_LOC_1, 0x01},
{WCD9378_SA_UP_STAGE_LOC_2, 0x02},
{WCD9378_SA_UP_STAGE_LOC_3, 0x03},
{WCD9378_SA_UP_STAGE_LOC_4, 0x04},
{WCD9378_SA_UP_STAGE_LOC_5, 0x05},
{WCD9378_SA_UP_STAGE_LOC_6, 0x06},
{WCD9378_SA_UP_STAGE_LOC_7, 0x07},
{WCD9378_SA_DN_STAGE_LOC_0, 0x05},
{WCD9378_SA_DN_STAGE_LOC_1, 0x06},
{WCD9378_SA_DN_STAGE_LOC_2, 0x04},
{WCD9378_SA_DN_STAGE_LOC_3, 0x03},
{WCD9378_SA_DN_STAGE_LOC_4, 0x02},
{WCD9378_SA_DN_STAGE_LOC_5, 0x01},
{WCD9378_SA_DN_STAGE_LOC_6, 0x07},
{WCD9378_SA_DN_STAGE_LOC_7, 0x00},
{WCD9378_TX0_UP_T0, 0x02},
{WCD9378_TX0_UP_T1, 0x02},
{WCD9378_TX0_UP_T2, 0x02},
{WCD9378_TX0_UP_T3, 0x00},
{WCD9378_TX0_DN_T0, 0x02},
{WCD9378_TX0_DN_T1, 0x02},
{WCD9378_TX0_DN_T2, 0x02},
{WCD9378_TX0_DN_T3, 0x00},
{WCD9378_TX0_UP_STAGE_LOC_0, 0x00},
{WCD9378_TX0_UP_STAGE_LOC_1, 0x01},
{WCD9378_TX0_UP_STAGE_LOC_2, 0x02},
{WCD9378_TX0_UP_STAGE_LOC_3, 0x03},
{WCD9378_TX0_DN_STAGE_LOC_0, 0x02},
{WCD9378_TX0_DN_STAGE_LOC_1, 0x00},
{WCD9378_TX0_DN_STAGE_LOC_2, 0x01},
{WCD9378_TX0_DN_STAGE_LOC_3, 0x03},
{WCD9378_TX1_UP_T0, 0x02},
{WCD9378_TX1_UP_T1, 0x02},
{WCD9378_TX1_UP_T2, 0x02},
{WCD9378_TX1_UP_T3, 0x00},
{WCD9378_TX1_DN_T0, 0x02},
{WCD9378_TX1_DN_T1, 0x02},
{WCD9378_TX1_DN_T2, 0x02},
{WCD9378_TX1_DN_T3, 0x00},
{WCD9378_TX1_UP_STAGE_LOC_0, 0x00},
{WCD9378_TX1_UP_STAGE_LOC_1, 0x01},
{WCD9378_TX1_UP_STAGE_LOC_2, 0x02},
{WCD9378_TX1_UP_STAGE_LOC_3, 0x03},
{WCD9378_TX1_DN_STAGE_LOC_0, 0x02},
{WCD9378_TX1_DN_STAGE_LOC_1, 0x00},
{WCD9378_TX1_DN_STAGE_LOC_2, 0x01},
{WCD9378_TX1_DN_STAGE_LOC_3, 0x03},
{WCD9378_TX2_UP_T0, 0x02},
{WCD9378_TX2_UP_T1, 0x02},
{WCD9378_TX2_UP_T2, 0x02},
{WCD9378_TX2_UP_T3, 0x00},
{WCD9378_TX2_DN_T0, 0x02},
{WCD9378_TX2_DN_T1, 0x02},
{WCD9378_TX2_DN_T2, 0x02},
{WCD9378_TX2_DN_T3, 0x00},
{WCD9378_TX2_UP_STAGE_LOC_0, 0x00},
{WCD9378_TX2_UP_STAGE_LOC_1, 0x01},
{WCD9378_TX2_UP_STAGE_LOC_2, 0x02},
{WCD9378_TX2_UP_STAGE_LOC_3, 0x03},
{WCD9378_TX2_DN_STAGE_LOC_0, 0x02},
{WCD9378_TX2_DN_STAGE_LOC_1, 0x00},
{WCD9378_TX2_DN_STAGE_LOC_2, 0x01},
{WCD9378_TX2_DN_STAGE_LOC_3, 0x03},
{WCD9378_SEQ_HPH_STAT, 0x00},
{WCD9378_SEQ_SA_STAT, 0x00},
{WCD9378_SEQ_TX0_STAT, 0x00},
{WCD9378_SEQ_TX1_STAT, 0x00},
{WCD9378_SEQ_TX2_STAT, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_0, 0x18},
{WCD9378_MICB_REMAP_TABLE_VAL_1, 0x22},
{WCD9378_MICB_REMAP_TABLE_VAL_2, 0x24},
{WCD9378_MICB_REMAP_TABLE_VAL_3, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_4, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_5, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_6, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_7, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_8, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_9, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_10, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_11, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_12, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_13, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_14, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_15, 0x00},
{WCD9378_SM0_MB_SEL, 0x00},
{WCD9378_SM1_MB_SEL, 0x00},
{WCD9378_SM2_MB_SEL, 0x00},
{WCD9378_MB_PULLUP_EN, 0x00},
{WCD9378_BYP_EN_CTL0, 0x00},
{WCD9378_BYP_EN_CTL1, 0x00},
{WCD9378_BYP_EN_CTL2, 0x00},
{WCD9378_SEQ_OVRRIDE_CTL0, 0x00},
{WCD9378_SEQ_OVRRIDE_CTL1, 0x00},
{WCD9378_SEQ_OVRRIDE_CTL2, 0x00},
{WCD9378_HPH_SEQ_OVRRIDE_CTL0, 0x00},
{WCD9378_HPH_SEQ_OVRRIDE_CTL1, 0x00},
{WCD9378_SA_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_TX0_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_TX1_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_TX2_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_FORCE_CTL, 0x00},
{WCD9378_DEVICE_DET, 0x03},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3, 0x00},
{WCD9378_SDCA_MESSAGE_GATE, 0x00},
{WCD9378_MBHC_DATA_IN_EDGE, 0x00},
{WCD9378_MBHC_RESET, 0x00},
{WCD9378_MBHC_DEBUG, 0x00},
{WCD9378_MBHC_DEBUG_UMP_0, 0x00},
{WCD9378_MBHC_DEBUG_UMP_1, 0x00},
{WCD9378_MBHC_DEBUG_UMP_2, 0x00},
{WCD9378_HID_FUNC_EXT_ID_0, 0x00},
{WCD9378_HID_FUNC_EXT_ID_1, 0x00},
{WCD9378_HID_FUNC_EXT_VER, 0x00},
{WCD9378_HID_FUNC_STAT, 0x67},
{WCD9378_HID_CUR_OWNER, 0x01},
{WCD9378_HID_MSG_OFFSET, 0x44000001},
{WCD9378_HID_MSG_LENGTH, 0x04},
{WCD9378_HID_DEV_MANU_ID_0, 0x17},
{WCD9378_HID_DEV_MANU_ID_1, 0x02},
{WCD9378_HID_DEV_PART_ID_0, 0x10},
{WCD9378_HID_DEV_PART_ID_1, 0x01},
{WCD9378_HID_DEV_VER, 0x10},
{WCD9378_SMP_AMP_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_AMP_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_AMP_FUNC_EXT_VER, 0x00},
{WCD9378_XU22_BYP, 0x01},
{WCD9378_PDE22_REQ_PS, 0x03},
{WCD9378_FU23_MUTE, 0x01},
{WCD9378_PDE23_REQ_PS, 0x03},
{WCD9378_SMP_AMP_FUNC_STAT, 0x67},
{WCD9378_FUNC_ACT, 0x00},
{WCD9378_PDE22_ACT_PS, 0x03},
{WCD9378_SAPU29_PROT_MODE, 0x00},
{WCD9378_SAPU29_PROT_STAT, 0x00},
{WCD9378_PDE23_ACT_PS, 0x03},
{WCD9378_SMP_AMP_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_AMP_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_AMP_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_AMP_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_AMP_DEV_VER, 0x10},
{WCD9378_CMT_GRP_MASK, 0x00},
{WCD9378_SMP_JACK_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_JACK_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_JACK_FUNC_EXT_VER, 0x00},
{WCD9378_IT41_USAGE, 0x03},
{WCD9378_XU42_BYP, 0x01},
{WCD9378_PDE42_REQ_PS, 0x03},
{WCD9378_FU42_MUTE_CH1, 0x01},
{WCD9378_FU42_MUTE_CH2, 0x01},
{WCD9378_FU42_CH_VOL_CH1, 0xe200},
{WCD9378_FU42_CH_VOL_CH2, 0xe200},
{WCD9378_SU43_SELECTOR, 0x01},
{WCD9378_SU45_SELECTOR, 0x01},
{WCD9378_PDE47_REQ_PS, 0x03},
{WCD9378_GE35_SEL_MODE, 0x00},
{WCD9378_GE35_DET_MODE, 0x00},
{WCD9378_IT31_MICB, 0x00},
{WCD9378_IT31_USAGE, 0x03},
{WCD9378_PDE34_REQ_PS, 0x03},
{WCD9378_SU45_TX_SELECTOR, 0x01},
{WCD9378_XU36_BYP, 0x01},
{WCD9378_PDE36_REQ_PS, 0x03},
{WCD9378_OT36_USAGE, 0x03},
{WCD9378_SMP_JACK_FUNC_STAT, 0x67},
{WCD9378_SMP_JACK_FUNC_ACT, 0x00},
{WCD9378_PDE42_ACT_PS, 0x03},
{WCD9378_PDE47_ACT_PS, 0x03},
{WCD9378_PDE34_ACT_PS, 0x03},
{WCD9378_PDE36_ACT_PS, 0x03},
{WCD9378_SMP_JACK_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_JACK_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_JACK_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_JACK_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_JACK_DEV_VER, 0x10},
{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER, 0x00},
{WCD9378_IT11_MICB, 0x00},
{WCD9378_IT11_USAGE, 0x03},
{WCD9378_PDE11_REQ_PS, 0x03},
{WCD9378_OT10_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL0_FUNC_STAT, 0x67},
{WCD9378_SMP_MIC_CTRL0_FUNC_ACT, 0x00},
{WCD9378_PDE11_ACT_PS, 0x03},
{WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_MIC_CTRL0_DEV_VER, 0x10},
{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER, 0x00},
{WCD9378_SMP_MIC_CTRL1_IT11_MICB, 0x00},
{WCD9378_SMP_MIC_CTRL1_IT11_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS, 0x03},
{WCD9378_SMP_MIC_CTRL1_OT10_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL1_FUNC_STAT, 0x67},
{WCD9378_SMP_MIC_CTRL1_FUNC_ACT, 0x00},
{WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS, 0x03},
{WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_MIC_CTRL1_DEV_VER, 0x10},
{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER, 0x00},
{WCD9378_SMP_MIC_CTRL2_IT11_MICB, 0x00},
{WCD9378_SMP_MIC_CTRL2_IT11_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS, 0x03},
{WCD9378_SMP_MIC_CTRL2_OT10_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL2_FUNC_STAT, 0x67},
{WCD9378_SMP_MIC_CTRL2_FUNC_ACT, 0x00},
{WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS, 0x03},
{WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_MIC_CTRL2_DEV_VER, 0x10},
{WCD9378_REPORT_ID, 0x01},
{WCD9378_MESSAGE0, 0x00},
{WCD9378_MESSAGE1, 0x00},
{WCD9378_MESSAGE2, 0x00},
};
static bool wcd9378_readable_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD9378_BASE) {
switch (reg) {
case SWRS_SCP_SDCA_INTSTAT_1:
case SWRS_SCP_SDCA_INTSTAT_2:
case SWRS_SCP_SDCA_INTSTAT_3:
case SWRS_SCP_SDCA_INTMASK_1:
case SWRS_SCP_SDCA_INTMASK_2:
case SWRS_SCP_SDCA_INTMASK_3:
case SWRS_SCP_SDCA_INTRTYPE_1:
case SWRS_SCP_SDCA_INTRTYPE_2:
case SWRS_SCP_SDCA_INTRTYPE_3:
break;
default:
return false;
}
}
if (wcd9378_reg_access[WCD9378_REG(reg)] & RD_REG)
return true;
else
return false;
}
static bool wcd9378_writeable_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD9378_BASE) {
switch (reg) {
case SWRS_SCP_SDCA_INTSTAT_1:
case SWRS_SCP_SDCA_INTSTAT_2:
case SWRS_SCP_SDCA_INTSTAT_3:
case SWRS_SCP_SDCA_INTMASK_1:
case SWRS_SCP_SDCA_INTMASK_2:
case SWRS_SCP_SDCA_INTMASK_3:
case SWRS_SCP_SDCA_INTRTYPE_1:
case SWRS_SCP_SDCA_INTRTYPE_2:
case SWRS_SCP_SDCA_INTRTYPE_3:
break;
default:
return false;
}
}
if (wcd9378_reg_access[WCD9378_REG(reg)] & WR_REG)
return true;
else
return false;
}
static bool wcd9378_volatile_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD9378_BASE) {
switch (reg) {
case SWRS_SCP_SDCA_INTSTAT_1:
case SWRS_SCP_SDCA_INTSTAT_2:
case SWRS_SCP_SDCA_INTSTAT_3:
case SWRS_SCP_SDCA_INTMASK_1:
case SWRS_SCP_SDCA_INTMASK_2:
case SWRS_SCP_SDCA_INTMASK_3:
case SWRS_SCP_SDCA_INTRTYPE_1:
case SWRS_SCP_SDCA_INTRTYPE_2:
case SWRS_SCP_SDCA_INTRTYPE_3:
return true;
default:
return false;
}
}
if ((wcd9378_reg_access[WCD9378_REG(reg)] & RD_REG) &&
!(wcd9378_reg_access[WCD9378_REG(reg)] & WR_REG))
return true;
else
return false;
}
struct regmap_config wcd9378_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wcd9378_defaults,
.num_reg_defaults = ARRAY_SIZE(wcd9378_defaults),
.max_register = WCD9378_MAX_REGISTER,
.volatile_reg = wcd9378_volatile_register,
.readable_reg = wcd9378_readable_register,
.writeable_reg = wcd9378_writeable_register,
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
.can_multi_write = true,
.use_single_read = true,
};

419
asoc/codecs/wcd9378/wcd9378-slave.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/component.h>
#include <soc/soundwire.h>
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/uaccess.h>
#include <linux/fs.h>
#define SWR_SLV_MAX_REG_ADDR 0x2009
#define SWR_SLV_START_REG_ADDR 0x40
#define SWR_SLV_MAX_BUF_LEN 20
#define BYTES_PER_LINE 12
#define SWR_SLV_RD_BUF_LEN 8
#define SWR_SLV_WR_BUF_LEN 32
#define SWR_SLV_MAX_DEVICES 2
#endif /* CONFIG_DEBUG_FS */
#define SWR_MAX_RETRY 5
struct wcd9378_slave_priv {
struct swr_device *swr_slave;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_wcd9378_dent;
struct dentry *debugfs_peek;
struct dentry *debugfs_poke;
struct dentry *debugfs_reg_dump;
unsigned int read_data;
#endif
};
#ifdef CONFIG_DEBUG_FS
static int get_parameters(char *buf, u32 *param1, int num_of_par)
{
char *token = NULL;
int base = 0, cnt = 0;
token = strsep(&buf, " ");
for (cnt = 0; cnt < num_of_par; cnt++) {
if (token) {
if ((token[1] == 'x') || (token[1] == 'X'))
base = 16;
else
base = 10;
if (kstrtou32(token, base, &param1[cnt]) != 0)
return -EINVAL;
token = strsep(&buf, " ");
} else {
return -EINVAL;
}
}
return 0;
}
static bool is_swr_slv_reg_readable(int reg)
{
int ret = true;
if (((reg > 0x46) && (reg < 0x4A)) ||
((reg > 0x4A) && (reg < 0x50)) ||
((reg > 0x55) && (reg < 0xD0)) ||
((reg > 0xD0) && (reg < 0xE0)) ||
((reg > 0xE0) && (reg < 0xF0)) ||
((reg > 0xF0) && (reg < 0x100)) ||
((reg > 0x105) && (reg < 0x120)) ||
((reg > 0x205) && (reg < 0x220)) ||
((reg > 0x305) && (reg < 0x320)) ||
((reg > 0x405) && (reg < 0x420)) ||
((reg > 0x128) && (reg < 0x130)) ||
((reg > 0x228) && (reg < 0x230)) ||
((reg > 0x328) && (reg < 0x330)) ||
((reg > 0x428) && (reg < 0x430)) ||
((reg > 0x138) && (reg < 0x205)) ||
((reg > 0x238) && (reg < 0x305)) ||
((reg > 0x338) && (reg < 0x405)) ||
((reg > 0x438) && (reg < 0x2000)))
ret = false;
return ret;
}
static ssize_t wcd9378_swrslave_reg_show(struct swr_device *pdev,
char __user *ubuf,
size_t count, loff_t *ppos)
{
int i, reg_val, len;
ssize_t total = 0;
char tmp_buf[SWR_SLV_MAX_BUF_LEN];
if (!ubuf || !ppos)
return 0;
for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
i <= SWR_SLV_MAX_REG_ADDR; i++) {
if (!is_swr_slv_reg_readable(i))
continue;
swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
len = scnprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
(reg_val & 0xFF));
if (((total + len) >= count - 1) || (len < 0))
break;
if (copy_to_user((ubuf + total), tmp_buf, len)) {
pr_err("%s: fail to copy reg dump\n", __func__);
total = -EFAULT;
goto copy_err;
}
total += len;
*ppos += len;
}
copy_err:
*ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
return total;
}
static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
size_t count, loff_t *ppos)
{
struct swr_device *pdev;
if (!count || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
return wcd9378_swrslave_reg_show(pdev, ubuf, count, ppos);
}
static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
size_t count, loff_t *ppos)
{
char lbuf[SWR_SLV_RD_BUF_LEN];
struct swr_device *pdev = NULL;
struct wcd9378_slave_priv *wcd9378_slave = NULL;
if (!count || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
wcd9378_slave = swr_get_dev_data(pdev);
if (!wcd9378_slave)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
snprintf(lbuf, sizeof(lbuf), "0x%x\n",
(wcd9378_slave->read_data & 0xFF));
return simple_read_from_buffer(ubuf, count, ppos, lbuf,
strnlen(lbuf, 7));
}
static ssize_t codec_debug_peek_write(struct file *file,
const char __user *ubuf, size_t cnt, loff_t *ppos)
{
char lbuf[SWR_SLV_WR_BUF_LEN];
int rc = 0;
u32 param[5];
struct swr_device *pdev = NULL;
struct wcd9378_slave_priv *wcd9378_slave = NULL;
if (!cnt || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
wcd9378_slave = swr_get_dev_data(pdev);
if (!wcd9378_slave)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
if (cnt > sizeof(lbuf) - 1)
return -EINVAL;
rc = copy_from_user(lbuf, ubuf, cnt);
if (rc)
return -EFAULT;
lbuf[cnt] = '\0';
rc = get_parameters(lbuf, param, 1);
if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
return -EINVAL;
swr_read(pdev, pdev->dev_num, param[0], &wcd9378_slave->read_data, 1);
if (rc == 0)
rc = cnt;
else
pr_err("%s: rc = %d\n", __func__, rc);
return rc;
}
static ssize_t codec_debug_write(struct file *file,
const char __user *ubuf, size_t cnt, loff_t *ppos)
{
char lbuf[SWR_SLV_WR_BUF_LEN];
int rc = 0;
u32 param[5];
struct swr_device *pdev;
if (!file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
if (cnt > sizeof(lbuf) - 1)
return -EINVAL;
rc = copy_from_user(lbuf, ubuf, cnt);
if (rc)
return -EFAULT;
lbuf[cnt] = '\0';
rc = get_parameters(lbuf, param, 2);
if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
(param[1] <= 0xFF) && (rc == 0)))
return -EINVAL;
swr_write(pdev, pdev->dev_num, param[0], &param[1]);
if (rc == 0)
rc = cnt;
else
pr_err("%s: rc = %d\n", __func__, rc);
return rc;
}
static const struct file_operations codec_debug_write_ops = {
.open = simple_open,
.write = codec_debug_write,
};
static const struct file_operations codec_debug_read_ops = {
.open = simple_open,
.read = codec_debug_read,
.write = codec_debug_peek_write,
};
static const struct file_operations codec_debug_dump_ops = {
.open = simple_open,
.read = codec_debug_dump,
};
#endif
static int wcd9378_slave_bind(struct device *dev,
struct device *master, void *data)
{
int ret = 0;
uint8_t devnum = 0;
struct swr_device *pdev = to_swr_device(dev);
int retry = SWR_MAX_RETRY;
if (!pdev) {
pr_err("%s: invalid swr device handle\n", __func__);
return -EINVAL;
}
do {
/* Add delay for soundwire enumeration */
usleep_range(100, 110);
ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
} while (ret && --retry);
if (ret) {
dev_dbg(&pdev->dev,
"%s get devnum %d for dev addr %llx failed\n",
__func__, devnum, pdev->addr);
ret = -EPROBE_DEFER;
return ret;
}
pdev->dev_num = devnum;
return ret;
}
static void wcd9378_slave_unbind(struct device *dev,
struct device *master, void *data)
{
struct wcd9378_slave_priv *wcd9378_slave = NULL;
struct swr_device *pdev = to_swr_device(dev);
wcd9378_slave = swr_get_dev_data(pdev);
if (!wcd9378_slave) {
dev_err(&pdev->dev, "%s: wcd9378_slave is NULL\n", __func__);
return;
}
}
static const struct swr_device_id wcd9378_swr_id[] = {
{"wcd9378-slave", 0},
{}
};
static const struct of_device_id wcd9378_swr_dt_match[] = {
{
.compatible = "qcom,wcd9378-slave",
},
{}
};
static const struct component_ops wcd9378_slave_comp_ops = {
.bind = wcd9378_slave_bind,
.unbind = wcd9378_slave_unbind,
};
static int wcd9378_swr_probe(struct swr_device *pdev)
{
struct wcd9378_slave_priv *wcd9378_slave = NULL;
wcd9378_slave = devm_kzalloc(&pdev->dev,
sizeof(struct wcd9378_slave_priv), GFP_KERNEL);
if (!wcd9378_slave)
return -ENOMEM;
swr_set_dev_data(pdev, wcd9378_slave);
wcd9378_slave->swr_slave = pdev;
#ifdef CONFIG_DEBUG_FS
if (!wcd9378_slave->debugfs_wcd9378_dent) {
wcd9378_slave->debugfs_wcd9378_dent = debugfs_create_dir(
dev_name(&pdev->dev), 0);
if (!IS_ERR(wcd9378_slave->debugfs_wcd9378_dent)) {
wcd9378_slave->debugfs_peek =
debugfs_create_file("swrslave_peek",
S_IFREG | 0444,
wcd9378_slave->debugfs_wcd9378_dent,
(void *) pdev,
&codec_debug_read_ops);
wcd9378_slave->debugfs_poke =
debugfs_create_file("swrslave_poke",
S_IFREG | 0444,
wcd9378_slave->debugfs_wcd9378_dent,
(void *) pdev,
&codec_debug_write_ops);
wcd9378_slave->debugfs_reg_dump =
debugfs_create_file(
"swrslave_reg_dump",
S_IFREG | 0444,
wcd9378_slave->debugfs_wcd9378_dent,
(void *) pdev,
&codec_debug_dump_ops);
}
}
#endif
return component_add(&pdev->dev, &wcd9378_slave_comp_ops);
}
static int wcd9378_swr_remove(struct swr_device *pdev)
{
#ifdef CONFIG_DEBUG_FS
struct wcd9378_slave_priv *wcd9378_slave = swr_get_dev_data(pdev);
if (wcd9378_slave) {
debugfs_remove_recursive(wcd9378_slave->debugfs_wcd9378_dent);
wcd9378_slave->debugfs_wcd9378_dent = NULL;
}
#endif
component_del(&pdev->dev, &wcd9378_slave_comp_ops);
swr_set_dev_data(pdev, NULL);
swr_remove_device(pdev);
return 0;
}
static struct swr_driver wcd9378_slave_driver = {
.driver = {
.name = "wcd9378-slave",
.owner = THIS_MODULE,
.of_match_table = wcd9378_swr_dt_match,
},
.probe = wcd9378_swr_probe,
.remove = wcd9378_swr_remove,
.id_table = wcd9378_swr_id,
};
static int __init wcd9378_slave_init(void)
{
return swr_driver_register(&wcd9378_slave_driver);
}
static void __exit wcd9378_slave_exit(void)
{
swr_driver_unregister(&wcd9378_slave_driver);
}
module_init(wcd9378_slave_init);
module_exit(wcd9378_slave_exit);
MODULE_DESCRIPTION("WCD9378 Swr Slave driver");
MODULE_LICENSE("GPL");

845
asoc/codecs/wcd9378/wcd9378-tables.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/regmap.h>
#include <linux/device.h>
#include "wcd9378-registers.h"
const u8 wcd9378_reg_access[] = {
[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_1)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_2)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_3)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_1)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_2)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_3)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_1)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_2)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_PAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_BIAS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_RX_SUPPLIES)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_HPH)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_EAR)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_EAR_COMPANDER_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH3_HPF)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB3_DSP_EN_LOGIC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_MECH)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_ELECT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_ZDET)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_1)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_2)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_3)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB2_RAMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BIAS_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BIAS_VBG_FINE_ADJ)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOL_VDDCX_ADJUST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOL_DISABLE_LDOL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_CLK)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_ANA)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_SPARE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_BCS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_MOISTURE_DET_FSM_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_BIAS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_STB_LOADS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_SLOWRAMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB1_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB1_TEST_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB1_TEST_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB2_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB2_TEST_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB2_TEST_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB3_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB3_TEST_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB3_TEST_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_ADC_VCM)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_BIAS_ATEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_TXFE_DIV_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_TXFE_DIV_START)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TEST_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_ADC_IB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_ATEST_REFCTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TEST_BLK_EN1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TXFE1_CLKDIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_SAR2_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_1_2_SAR1_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_ADC_IB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_ATEST_REFCTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TXFE3_CLKDIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SAR4_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_3_SAR3_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TXFE2_CLKDIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SPARE1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SPARE2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SPARE3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_AUX_SW_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_PA_AUX_IN_CONN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_TIMER_DIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_OCP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_OCP_COUNT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_EAR_DAC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_EAR_AMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_LDO)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_PA)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_RDAC_LDO)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_CNP1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_LOWPOWER)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_AUX_DAC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_AUX_AMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_HPH_R_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_HPH_CNP_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_CNP_WG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_CNP_WG_TIME)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_OCP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_AUTO_CHOP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_CHOP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_PA_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_PA_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_TEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_ATEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_TEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_ATEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_CLK_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_CLK_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_LDO_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_REFBUFF_UHQA_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_REFBUFF_LP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_DAC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_DAC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_EAR_EAR_EN_REG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_PA_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_SP_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_DAC_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_CNP_FSM_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_STATUS_REG_1)] = RD_REG,
[WCD9378_REG(WCD9378_EAR_STATUS_REG_2)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_NEW_PAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_ANA_HPH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_ANA_HPH3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_WATCHDOG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_PLUG_DETECT_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ZDET_ANA_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ZDET_RAMP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_FSM_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ADC_RESULT)] = RD_REG,
[WCD9378_REG(WCD9378_AUX_AUXPA)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_DIE_CRK_DET_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_DIE_CRK_DET_OUT)] = RD_REG,
[WCD9378_REG(WCD9378_TX_NEW_TX_CH12_MUX)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_NEW_TX_CH34_MUX)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_VREF_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_MISC1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_MISC2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_11)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_12)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_13)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_14)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_15)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_16)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_17)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_18)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_19)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_CNP_VCM_CON1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_CNP_VCM_CON2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_EN_REG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_PA_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_SP_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_DAC_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_CLK_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_TEST_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_STATUS_REG)] = RD_REG,
[WCD9378_REG(WCD9378_AUX_INT_MISC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_INT_WATCHDOG_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_INT_WATCHDOG_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TAMBORA_PAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CHIP_ID0)] = RD_REG,
[WCD9378_REG(WCD9378_CHIP_ID1)] = RD_REG,
[WCD9378_REG(WCD9378_CHIP_ID2)] = RD_REG,
[WCD9378_REG(WCD9378_CHIP_ID3)] = RD_REG,
[WCD9378_REG(WCD9378_SWR_TX_CLK_RATE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TOP_CLK_CFG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_ANA_CLK_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DIG_CLK_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_RST_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_PATH_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX_RST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX0_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX1_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX2_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX_ANA_MODE_0_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX_ANA_MODE_2_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_COMP_CTL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_ANA_TX_CLK_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A1_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A1_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A2_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A2_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A3_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A3_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A4_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A4_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A5_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A5_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A6_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A7_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A1_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A1_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A2_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A2_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A3_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A3_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A4_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A4_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A5_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A5_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A6_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A7_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_RX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_RX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_PATH_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_SWR_CLG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_CLG_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX0_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX1_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX2_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX_RST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_REQ_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AMIC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC1_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC2_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC3_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_PRG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC_RATE_1_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC_RATE_3_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_EN_OVRD)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RAMP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_HOOKUP0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_HOOKUP1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_HOOKUP2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_DLY_BUF_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_MODE_DBG_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_MODE_DBG_0_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_MODE_DBG_2_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LB_IN_SEL_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LOOP_BACK_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_DAC_TEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_RX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_TX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_RX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_TX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_0)] = RD_REG,
[WCD9378_REG(WCD9378_PAD_CTL_SWR_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_SWR_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_I2C_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LEGACY_SW_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_TEST_CTL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_T_DATA_0)] = RD_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_RX0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_RX1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_TX0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_TX1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_INP_DIS_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DRIVE_STRENGTH_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DRIVE_STRENGTH_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_DATA_EDGE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_DATA_EDGE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_GPIO_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PIN_CTL_OE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PIN_CTL_DATA_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PIN_STATUS_0)] = RD_REG,
[WCD9378_REG(WCD9378_DIG_DEBUG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIG_DEBUG_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_CSR_DBG_ADD)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_CSR_DBG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SSP_DBG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MODE_STATUS_0)] = RD_REG,
[WCD9378_REG(WCD9378_MODE_STATUS_1)] = RD_REG,
[WCD9378_REG(WCD9378_SPARE_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SPARE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_0)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_1)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_2)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_3)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_4)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_5)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_6)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_7)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_8)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_9)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_10)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_11)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_12)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_13)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_14)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_15)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_16)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_17)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_18)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_19)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_20)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_21)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_22)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_23)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_24)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_25)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_26)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_27)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_28)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_29)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_30)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_31)] = RD_REG,
[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX0_PCM_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX0_DSD_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX1_PCM_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX1_DSD_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX2_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PLATFORM_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CLK_DIV_CFG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DRE_DLY_VAL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SYS_USAGE_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SURGE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_HPH_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_SA_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_TX0_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_TX1_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_TX2_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_11)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_12)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_13)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_14)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_15)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SM0_MB_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SM1_MB_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SM2_MB_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MB_PULLUP_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BYP_EN_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BYP_EN_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BYP_EN_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SEQ_OVRRIDE_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SEQ_OVRRIDE_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FORCE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEVICE_DET)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SDCA_MESSAGE_GATE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_DATA_IN_EDGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_RESET)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_0)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_1)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_2)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HID_CUR_OWNER)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HID_MSG_OFFSET)] = RD_REG,
[WCD9378_REG(WCD9378_HID_MSG_LENGTH)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_XU22_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE22_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU23_MUTE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE23_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE22_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SAPU29_PROT_MODE)] = RD_REG,
[WCD9378_REG(WCD9378_SAPU29_PROT_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_PDE23_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_CMT_GRP_MASK)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_IT41_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_XU42_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE42_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_MUTE_CH1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_MUTE_CH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_CH_VOL_CH1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_CH_VOL_CH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SU43_SELECTOR)] = RD_REG,
[WCD9378_REG(WCD9378_SU45_SELECTOR)] = RD_REG,
[WCD9378_REG(WCD9378_PDE47_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_GE35_SEL_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_GE35_DET_MODE)] = RD_REG,
[WCD9378_REG(WCD9378_IT31_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_IT31_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE34_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SU45_TX_SELECTOR)] = RD_REG,
[WCD9378_REG(WCD9378_XU36_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE36_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_OT36_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE42_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_PDE47_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_PDE34_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_PDE36_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_IT11_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_IT11_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE11_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_OT10_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE11_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_IT11_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_IT11_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_OT10_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_IT11_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_IT11_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_OT10_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_REPORT_ID)] = RD_REG,
[WCD9378_REG(WCD9378_MESSAGE0)] = RD_REG,
[WCD9378_REG(WCD9378_MESSAGE1)] = RD_REG,
[WCD9378_REG(WCD9378_MESSAGE2)] = RD_REG,
};

4490
asoc/codecs/wcd9378/wcd9378.c Normal file
View File

File diff suppressed because it is too large Load Diff

123
asoc/codecs/wcd9378/wcd9378.h Normal file
View File

@ -0,0 +1,123 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _WCD9378_H
#define _WCD9378_H
#include <bindings/audio-codec-port-types.h>
#include <sound/info.h>
#include <linux/component.h>
#define WCD9378_MAX_SLAVE_CH_TYPES 13
#define ZERO 0
#define WCD9378_DRV_NAME "wcd9378_codec"
/* from WCD to SWR DMIC events */
enum {
WCD9378_EVT_SSR_DOWN,
WCD9378_EVT_SSR_UP,
};
struct wcd9378_swr_slave_ch_map {
u8 ch_type;
u8 index;
};
static const struct wcd9378_swr_slave_ch_map wcd9378_swr_slv_tx_ch_idx[] = {
{ADC1, 0},
{ADC2, 1},
{ADC3, 2},
{ADC4, 3},
{DMIC0, 4},
{DMIC1, 5},
{MBHC, 6},
{DMIC2, 6},
{DMIC3, 7},
{DMIC4, 8},
{DMIC5, 9},
{DMIC6, 10},
{DMIC7, 11},
};
static int wcd9378_swr_master_ch_map[] = {
ZERO,
SWRM_TX1_CH1,
SWRM_TX1_CH2,
SWRM_TX1_CH3,
SWRM_TX1_CH4,
SWRM_TX2_CH1,
SWRM_TX2_CH2,
SWRM_TX2_CH3,
SWRM_TX2_CH4,
SWRM_TX3_CH1,
SWRM_TX3_CH2,
SWRM_TX3_CH3,
SWRM_TX3_CH4,
SWRM_TX_PCM_IN,
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD9378)
int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
struct snd_soc_component *component);
int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *wcd9378,
struct notifier_block *nblock,
bool enable);
int wcd9378_codec_get_dev_num(struct snd_soc_component *component);
static inline int wcd9378_slave_get_master_ch_val(int ch)
{
int i;
for (i = 0; i < WCD9378_MAX_SLAVE_CH_TYPES; i++)
if (ch == wcd9378_swr_master_ch_map[i])
return i;
return 0;
}
static inline int wcd9378_slave_get_master_ch(int idx)
{
return wcd9378_swr_master_ch_map[idx];
}
static inline int wcd9378_slave_get_slave_ch_val(int ch)
{
int i;
for (i = 0; i < WCD9378_MAX_SLAVE_CH_TYPES; i++)
if (ch == wcd9378_swr_slv_tx_ch_idx[i].ch_type)
return wcd9378_swr_slv_tx_ch_idx[i].index;
return -EINVAL;
}
#else
static inline int wcd9378_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_component *component)
{
return 0;
}
static inline int wcd9378_slave_get_master_ch_val(int ch)
{
return 0;
}
static inline int wcd9378_slave_get_master_ch(int idx)
{
return 0;
}
static inline int wcd9378_slave_get_slave_ch_val(int ch)
{
return 0;
}
static int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
{
return 0;
}
#endif /* CONFIG_SND_SOC_WCD9378 */
#endif /* _WCD9378_H */

7
audio_kernel_modules.mk
View File

@ -42,11 +42,14 @@ AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/swr_dmic_dlkm.ko \
$(KERNEL_MODULES_OUT)/lpass_cdc_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa884x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa883x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa881x_analog_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd937x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd937x_slave_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko
ifneq ($(call is-board-platform-in-list,niobe), true)
$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_slave_dlkm.ko
ifneq ($(call is-board-platform-in-list,niobe pitti), true)
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/wcd939x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd939x_slave_dlkm.ko
endif

9
audio_kernel_product_board.mk
View File

@ -29,9 +29,14 @@ PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/swr_dmic_dlkm.ko \
$(KERNEL_MODULES_OUT)/lpass_cdc_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa884x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa883x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa881x_analog_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd937x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd937x_slave_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko
ifneq ($(call is-board-platform-in-list,niobe), true)
$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_slave_dlkm.ko
ifneq ($(call is-board-platform-in-list,niobe pitti), true)
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/wcd939x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd939x_slave_dlkm.ko
endif

21
audio_modules.bzl
View File

@ -160,6 +160,9 @@ audio_modules.register(
"CONFIG_SND_SOC_PINEAPPLE": [
"pineapple.c"
],
"CONFIG_SND_SOC_PITTI": [
"pineapple.c"
],
"CONFIG_SND_SOC_NIOBE": [
"pineapple.c"
],
@ -440,3 +443,21 @@ audio_modules.register(
config_option = "CONFIG_SND_SOC_WCD939X_SLAVE",
srcs = ["wcd939x-slave.c"]
)
# >>>> WCD9378 MODULES <<<<
audio_modules.register(
name = "wcd9378_dlkm",
path = ASOC_CODECS_PATH + "/wcd9378",
config_option = "CONFIG_SND_SOC_WCD9378",
srcs = [
"wcd9378.c",
"wcd9378-regmap.c",
"wcd9378-tables.c",
"wcd9378-mbhc.c",
]
)
audio_modules.register(
name = "wcd9378_slave_dlkm",
path = ASOC_CODECS_PATH + "/wcd9378",
config_option = "CONFIG_SND_SOC_WCD9378_SLAVE",
srcs = ["wcd9378-slave.c"]
)

60
build/pitti.bzl Normal file
View File

@ -0,0 +1,60 @@
load(":audio_modules.bzl", "audio_modules")
load(":module_mgr.bzl", "define_target_modules")
def define_pitti():
define_target_modules(
target = "pitti",
variants = ["consolidate", "gki"],
registry = audio_modules,
modules = [
"q6_dlkm",
"spf_core_dlkm",
"audpkt_ion_dlkm",
"q6_notifier_dlkm",
"adsp_loader_dlkm",
"audio_prm_dlkm",
"q6_pdr_dlkm",
"gpr_dlkm",
"audio_pkt_dlkm",
"pinctrl_lpi_dlkm",
"swr_dlkm",
"swr_ctrl_dlkm",
"snd_event_dlkm",
"machine_dlkm",
"wcd_core_dlkm",
"mbhc_dlkm",
"swr_dmic_dlkm",
"wcd9xxx_dlkm",
"swr_haptics_dlkm",
"stub_dlkm",
"hdmi_dlkm",
"lpass_cdc_dlkm",
"lpass_cdc_va_macro_dlkm",
"lpass_cdc_rx_macro_dlkm",
"lpass_cdc_tx_macro_dlkm",
"lpass_cdc_wsa2_macro_dlkm",
"lpass_cdc_wsa_macro_dlkm",
"wsa881x_analog_dlkm",
"wsa883x_dlkm",
"wsa884x_dlkm",
"wcd937x_dlkm",
"wcd937x_slave_dlkm",
"wcd938x_dlkm",
"wcd938x_slave_dlkm",
"wcd9378_dlkm",
"wcd9378_slave_dlkm"
],
config_options = [
"CONFIG_SND_SOC_PITTI",
"CONFIG_SND_SOC_MSM_QDSP6V2_INTF",
"CONFIG_MSM_QDSP6_SSR",
"CONFIG_DIGITAL_CDC_RSC_MGR",
"CONFIG_SOUNDWIRE_MSTR_CTRL",
"CONFIG_WCD9XXX_CODEC_CORE_V2",
"CONFIG_MSM_CDC_PINCTRL",
"CONFIG_SND_SOC_WCD_IRQ",
"CONFIG_SND_SOC_WCD9XXX_V2",
"CONFIG_SND_SOC_WCD_MBHC_ADC",
"CONFIG_MSM_EXT_DISPLAY",
]
)

40
config/pittiauto.conf Normal file
View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
export CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m
export CONFIG_SND_SOC_PITTI=m
export CONFIG_SND_EVENT=m
export CONFIG_AUDIO_PKT_ION=m
export CONFIG_MSM_QDSP6_NOTIFIER=m
export CONFIG_MSM_QDSP6_SSR=m
export CONFIG_MSM_ADSP_LOADER=m
export CONFIG_SPF_CORE=m
export CONFIG_MSM_QDSP6_GPR_RPMSG=m
export CONFIG_MSM_QDSP6_PDR=m
export CONFIG_AUDIO_PRM=m
export CONFIG_AUDIO_PKT=m
export CONFIG_DIGITAL_CDC_RSC_MGR=m
export CONFIG_PINCTRL_LPI=m
export CONFIG_SOUNDWIRE=m
export CONFIG_SOUNDWIRE_MSTR_CTRL=m
export CONFIG_WCD9XXX_CODEC_CORE_V2=m
export CONFIG_MSM_CDC_PINCTRL=m
export CONFIG_SND_SOC_LPASS_CDC=m
export CONFIG_SND_SOC_WCD_IRQ=m
export CONFIG_LPASS_CDC_VA_MACRO=m
export CONFIG_LPASS_CDC_TX_MACRO=m
export CONFIG_LPASS_CDC_RX_MACRO=m
export CONFIG_SND_SOC_WSA881X_ANALOG=m
export CONFIG_WSA881X_TEMP_SENSOR_DISABLE=m
export CONFIG_SND_SOC_WCD9XXX_V2=m
export CONFIG_SND_SOC_WCD937X=m
export CONFIG_SND_SOC_WCD937X_SLAVE=m
export CONFIG_SND_SOC_WCD938X=m
export CONFIG_SND_SOC_WCD938X_SLAVE=m
export CONFIG_SND_SOC_WCD9378=m
export CONFIG_SND_SOC_WCD9378_SLAVE=m
export CONFIG_SND_SOC_WCD_MBHC=m
export CONFIG_SND_SOC_WCD_MBHC_ADC=m
export CONFIG_SND_SOC_MSM_STUB=m
export CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=m

43
config/pittiautoconf.h Normal file
View File

@ -0,0 +1,43 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1
#define CONFIG_SND_SOC_PITTI 1
#define CONFIG_SND_EVENT 1
#define CONFIG_AUDIO_PKT_ION 1
#define CONFIG_MSM_QDSP6_NOTIFIER 1
#define CONFIG_MSM_QDSP6_SSR 1
#define CONFIG_MSM_QDSP6_PDR 1
#define CONFIG_MSM_ADSP_LOADER 1
#define CONFIG_SPF_CORE 1
#define CONFIG_MSM_QDSP6_GPR_RPMSG 1
#define CONFIG_AUDIO_PRM 1
#define CONFIG_AUDIO_PKT 1
#define CONFIG_DIGITAL_CDC_RSC_MGR 1
#define CONFIG_PINCTRL_LPI 1
#define CONFIG_SOUNDWIRE 1
#define CONFIG_SOUNDWIRE_MSTR_CTRL 1
#define CONFIG_WCD9XXX_CODEC_CORE_V2 1
#define CONFIG_MSM_CDC_PINCTRL 1
#define CONFIG_SND_SOC_LPASS_CDC 1
#define CONFIG_SND_SOC_WCD_IRQ 1
#define CONFIG_LPASS_CDC_VA_MACRO 1
#define CONFIG_LPASS_CDC_TX_MACRO 1
#define CONFIG_LPASS_CDC_RX_MACRO 1
#define CONFIG_SND_SOC_WCD9XXX_V2 1
#define CONFIG_SND_SOC_WCD937X 1
#define CONFIG_SND_SOC_WCD937X_SLAVE 1
#define CONFIG_SND_SOC_WSA881X_ANALOG 1
#define CONFIG_WSA881X_TEMP_SENSOR_DISABLE 1
#define CONFIG_SND_SOC_WCD938X 1
#define CONFIG_SND_SOC_WCD938X_SLAVE 1
#define CONFIG_SND_SOC_WCD9378 1
#define CONFIG_SND_SOC_WCD9378_SLAVE 1
#define CONFIG_SND_SOC_WCD_MBHC 1
#define CONFIG_SND_SOC_WCD_MBHC_ADC 1
#define CONFIG_SND_SOC_MSM_STUB 1
#define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1
#define CONFIG_MSM_EXT_DISPLAY 1

4
dsp/Kbuild
View File

@ -64,8 +64,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

2
include/asoc/wcd-mbhc-v2.h
View File

@ -455,7 +455,7 @@ struct wcd_mbhc_intr {
struct wcd_mbhc_register {
const char *id;
u16 reg;
u32 reg;
u8 mask;
u8 offset;
u8 invert;

2
include/soc/soundwire.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _LINUX_SOUNDWIRE_H
@ -269,6 +270,7 @@ struct swr_device {
struct device dev;
u64 addr;
u8 group_id;
bool paging_support;
struct irq_domain *slave_irq;
bool slave_irq_pending;
};

4
ipc/Kbuild
View File

@ -65,8 +65,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

4
soc/Kbuild
View File

@ -59,8 +59,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

118
soc/regmap-swr.c
View File

@ -12,9 +12,68 @@
#include <linux/init.h>
#include <soc/soundwire.h>
#define ADDR_BYTES 2
#define VAL_BYTES 1
#define PAD_BYTES 0
#define ADDR_BYTES (2)
#define ADDR_BYTES_4 (4)
#define VAL_BYTES (1)
#define PAD_BYTES (0)
#define SCP1_ADDRESS_VAL_MASK (0x7f800000)
#define SCP2_ADDRESS_VAL_MASK (0x007f8000)
#define BIT_WIDTH_CHECK_MASK (0xffff0000)
#define SCP1_ADDRESS_VAL_SHIFT (23)
#define SCP2_ADDRESS_VAL_SHIFT (15)
#define SCP1_ADDRESS (0X48)
#define SCP2_ADDRESS (0X49)
#define SDCA_READ_WRITE_BIT (0x8000)
u8 g_scp1_val;
u8 g_scp2_val;
static DEFINE_MUTEX(swr_rw_lock);
static int regmap_swr_reg_address_get(struct swr_device *swr,
u16 *reg_addr, const void *reg, size_t reg_size)
{
u8 scp1_val = 0, scp2_val = 0;
u32 temp = 0;
int ret = 0;
if (reg_size == ADDR_BYTES_4) {
temp = (*(u32 *)reg) & SCP1_ADDRESS_VAL_MASK;
scp1_val = temp >> SCP1_ADDRESS_VAL_SHIFT;
temp = (*(u32 *)reg) & SCP2_ADDRESS_VAL_MASK;
scp2_val = temp >> SCP2_ADDRESS_VAL_SHIFT;
if (scp1_val || scp2_val) {
if (scp1_val != g_scp1_val) {
ret = swr_write(swr, swr->dev_num, SCP1_ADDRESS, &scp1_val);
if (ret < 0) {
dev_err(&swr->dev, "%s: write reg scp1_address failed, err %d\n",
__func__, ret);
return ret;
}
g_scp1_val = scp1_val;
}
if (scp2_val != g_scp2_val) {
ret = swr_write(swr, swr->dev_num, SCP2_ADDRESS, &scp2_val);
if (ret < 0) {
dev_err(&swr->dev, "%s: write reg scp2_address failed, err %d\n",
__func__, ret);
return ret;
}
g_scp2_val = scp2_val;
}
*reg_addr = (*(u16 *)reg | SDCA_READ_WRITE_BIT);
dev_dbg(&swr->dev, "%s: reg: 0x%x, scp1_val: 0x%x, scp2_val: 0x%x, reg_addr: 0x%x\n",
__func__, *(u32 *)reg, scp1_val, scp2_val, *reg_addr);
} else {
*reg_addr = *(u16 *)reg;
}
} else {
*reg_addr = *(u16 *)reg;
}
return ret;
}
static int regmap_swr_gather_write(void *context,
const void *reg, size_t reg_size,
@ -36,12 +95,20 @@ static int regmap_swr_gather_write(void *context,
dev_err_ratelimited(dev, "%s: swr device is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != ADDR_BYTES) {
if ((reg_size != ADDR_BYTES) && (reg_size != ADDR_BYTES_4)) {
dev_err_ratelimited(dev, "%s: reg size %zd bytes not supported\n",
__func__, reg_size);
return -EINVAL;
}
reg_addr = *(u16 *)reg;
mutex_lock(&swr_rw_lock);
ret = regmap_swr_reg_address_get(swr, &reg_addr, reg, reg_size);
if (ret < 0) {
mutex_unlock(&swr_rw_lock);
return ret;
}
/* val_len = VAL_BYTES * val_count */
for (i = 0; i < (val_len / VAL_BYTES); i++) {
value = (u8 *)val + (VAL_BYTES * i);
@ -51,7 +118,10 @@ static int regmap_swr_gather_write(void *context,
__func__, (reg_addr + i), ret);
break;
}
dev_dbg(dev, "%s: dev_num: 0x%x, gather write reg: 0x%x, value: 0x%x\n",
__func__, swr->dev_num, (reg_addr + i), *value);
}
mutex_unlock(&swr_rw_lock);
return ret;
}
@ -114,21 +184,30 @@ mem_fail:
static int regmap_swr_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct swr_device *swr = to_swr_device(dev);
struct regmap *map = dev_get_regmap(dev, NULL);
int addr_bytes = 0;
if (map == NULL) {
dev_err_ratelimited(dev, "%s: regmap is NULL\n", __func__);
return -EINVAL;
}
WARN_ON(count < ADDR_BYTES);
if (swr == NULL) {
dev_err_ratelimited(dev, "%s: swr is NULL\n", __func__);
return -EINVAL;
}
if (count > (ADDR_BYTES + VAL_BYTES + PAD_BYTES))
addr_bytes = (swr->paging_support ? ADDR_BYTES_4 : ADDR_BYTES);
WARN_ON(count < addr_bytes);
if (count > (addr_bytes + VAL_BYTES + PAD_BYTES))
return regmap_swr_raw_multi_reg_write(context, data, count);
else
return regmap_swr_gather_write(context, data, ADDR_BYTES,
(data + ADDR_BYTES),
(count - ADDR_BYTES));
return regmap_swr_gather_write(context, data, addr_bytes,
(data + addr_bytes),
(count - addr_bytes));
}
static int regmap_swr_read(void *context,
@ -149,16 +228,29 @@ static int regmap_swr_read(void *context,
dev_err_ratelimited(dev, "%s: swr is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != ADDR_BYTES) {
dev_err_ratelimited(dev, "%s: register size %zd bytes not supported\n",
if ((reg_size != ADDR_BYTES) && (reg_size != ADDR_BYTES_4)) {
dev_err_ratelimited(dev, "%s: reg size %zd bytes not supported\n",
__func__, reg_size);
return -EINVAL;
}
reg_addr = *(u16 *)reg;
mutex_lock(&swr_rw_lock);
ret = regmap_swr_reg_address_get(swr, &reg_addr, reg, reg_size);
if (ret < 0) {
dev_err_ratelimited(dev,
"%s: regmap_swr_reg_address_get failed, reg: 0x%x\n",
__func__, *(u32 *)reg);
mutex_unlock(&swr_rw_lock);
return ret;
}
ret = swr_read(swr, swr->dev_num, reg_addr, val, val_size);
if (ret < 0)
dev_err_ratelimited(dev, "%s: codec reg 0x%x read failed %d\n",
__func__, reg_addr, ret);
mutex_unlock(&swr_rw_lock);
return ret;
}