From 9eeb4d671b3e4e3cb6bdc8e6ca4205ab672687f3 Mon Sep 17 00:00:00 2001 From: David Wronek Date: Mon, 6 Jan 2025 17:10:44 +0100 Subject: [PATCH] Revert "DIRTY: camera-kernel: Import everything from Samsung" This reverts commit 4e6b7ad60abcb927503704686bde78669b8d08b9. --- qcom/opensource/camera-kernel/Kbuild | 26 +- qcom/opensource/camera-kernel/Kconfig | 31 +- .../camera-kernel/config/pineapple.mk | 6 + .../drivers/cam_cdm/cam_cdm_hw_core.c | 2 +- .../drivers/cam_cdm/cam_cdm_util.c | 222 +- .../drivers/cam_cdm/cam_cdm_util.h | 15 + .../drivers/cam_core/cam_context.c | 27 +- .../drivers/cam_core/cam_context.h | 52 +- .../drivers/cam_core/cam_context_utils.c | 206 +- .../drivers/cam_core/cam_hw_mgr_intf.h | 18 +- .../drivers/cam_cpas/cam_cpas_hw.c | 149 +- .../drivers/cam_cpas/cam_cpas_hw.h | 5 + .../drivers/cam_cpas/cam_cpas_hw_intf.h | 7 + .../drivers/cam_cpas/cam_cpas_intf.c | 194 + .../drivers/cam_cpas/cam_cpas_soc.c | 5 +- .../drivers/cam_cpas/cam_cpas_soc.h | 4 +- .../cam_cpas/camss_top/cam_camsstop_hw.c | 2 + .../cam_cpas/cpas_top/cam_cpastop_hw.c | 213 +- .../cam_cpas/cpas_top/cam_cpastop_hw.h | 13 + .../cam_cpas/cpas_top/cpastop_v640_200.h | 9 + .../cam_cpas/cpas_top/cpastop_v640_210.h | 583 +++ .../cam_cpas/cpas_top/cpastop_v665_100.h | 649 +++ .../cam_cpas/cpas_top/cpastop_v770_100.h | 692 +++ .../cam_cpas/cpas_top/cpastop_v860_100.h | 1347 ++++++ .../drivers/cam_cpas/include/cam_cpas_api.h | 23 +- .../drivers/cam_cre/cam_cre_context.c | 2 +- .../cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c | 229 +- .../cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.h | 31 +- .../cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c | 42 +- .../cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c | 84 +- .../cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c | 9 +- .../cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c | 19 +- .../cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw.h | 11 +- .../cam_cre_hw_mgr/cre_hw/cre_hw_100.h | 25 +- .../cam_cre_hw_mgr/cre_hw/cre_hw_110.h | 243 ++ .../cam_cre_hw_mgr/cre_hw/top/cre_top.c | 5 +- .../cam_custom_csid/cam_custom_csid_dev.c | 9 +- .../cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c | 9 +- .../drivers/cam_icp/cam_icp_subdev.c | 24 +- .../camera-kernel/drivers/cam_icp/hfi.c | 33 +- .../drivers/cam_icp/icp_hw/bps_hw/bps_core.c | 6 +- .../drivers/cam_icp/icp_hw/bps_hw/bps_dev.c | 8 +- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 342 +- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h | 2 +- .../icp_hw_mgr/include/cam_icp_hw_intf.h | 3 +- .../icp_proc/icp_common/cam_icp_proc_common.c | 8 +- .../icp_proc/icp_v1_hw/cam_icp_v1_dev.c | 8 +- .../icp_proc/icp_v2_hw/cam_icp_v2_dev.c | 15 +- .../icp_hw/include/cam_icp_hw_mgr_intf.h | 2 +- .../drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c | 6 +- .../drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c | 6 + .../drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.c | 6 + .../drivers/cam_isp/cam_isp_context.c | 490 ++- .../drivers/cam_isp/cam_isp_context.h | 27 +- .../drivers/cam_isp/cam_isp_dev.c | 44 +- .../cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 831 ++-- .../cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h | 3 +- .../cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 1788 ++++++-- .../cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 88 +- .../hw_utils/cam_isp_packet_parser.c | 113 +- .../hw_utils/include/cam_isp_packet_parser.h | 27 +- .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 26 +- .../isp_hw/ife_csid_hw/cam_ife_csid860.h | 90 + .../isp_hw/ife_csid_hw/cam_ife_csid880.h | 3 +- .../isp_hw/ife_csid_hw/cam_ife_csid_common.c | 6 + .../isp_hw/ife_csid_hw/cam_ife_csid_dev.c | 6 + .../isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c | 64 +- .../isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c | 266 +- .../isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h | 8 +- .../isp_hw/ife_csid_hw/cam_ife_csid_lite860.h | 48 + .../isp_hw/ife_csid_hw/cam_ife_csid_lite880.h | 3 +- .../ife_csid_hw/cam_ife_csid_lite_mod.c | 10 + .../isp_hw/ife_csid_hw/cam_ife_csid_mod.c | 12 +- .../isp_hw/include/cam_ife_csid_hw_intf.h | 6 +- .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 24 +- .../isp_hw/include/cam_tfe_csid_hw_intf.h | 27 +- .../isp_hw/include/cam_tfe_hw_intf.h | 26 +- .../isp_hw/ppi_hw/cam_csid_ppi_dev.c | 7 + .../isp_hw_mgr/isp_hw/sfe_hw/cam_sfe860.h | 149 + .../isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c | 7 +- .../isp_hw/sfe_hw/sfe_top/cam_sfe_top.c | 8 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid.c | 20 + .../isp_hw/tfe_csid_hw/cam_tfe_csid530.h | 2 + .../isp_hw/tfe_csid_hw/cam_tfe_csid640.h | 5 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h | 20 + .../isp_hw/tfe_csid_hw/cam_tfe_csid665.h | 373 ++ .../isp_hw/tfe_csid_hw/cam_tfe_csid770.h | 374 ++ .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 996 ++++- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 111 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c | 26 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c | 5 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h | 3 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c | 21 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h | 23 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640.h | 23 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h | 79 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe665.h | 1476 +++++++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe770.h | 1476 +++++++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 536 ++- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h | 31 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 754 +++- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h | 88 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c | 56 +- .../isp_hw/tfe_hw/cam_tfe_lite770.h | 589 +++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c | 19 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h | 3 + .../isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c | 2 +- .../isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c | 12 +- .../isp_hw/vfe_hw/vfe17x/cam_vfe780.h | 24 + .../isp_hw/vfe_hw/vfe17x/cam_vfe860.h | 141 + .../isp_hw/vfe_hw/vfe17x/cam_vfe880.h | 39 +- .../isp_hw/vfe_hw/vfe17x/cam_vfe_lite86x.h | 86 + .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c | 5 - .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c | 184 +- .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h | 3 +- .../vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c | 19 +- .../vfe_hw/vfe_top/cam_vfe_camif_ver2.c | 3 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c | 3 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c | 20 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c | 5 + .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c | 8 +- .../cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 59 +- .../jpeg_hw/include/cam_jpeg_hw_mgr_intf.h | 9 +- .../cam_jpeg_dma_770_hw_info_ver_4_2_0.h | 76 + .../jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c | 7 +- .../jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c | 8 +- .../cam_jpeg_enc_770_hw_info_ver_4_2_0.h | 103 + .../jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c | 7 +- .../jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c | 7 +- .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c | 7 +- .../cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 12 + .../drivers/cam_req_mgr/cam_mem_mgr.c | 152 +- .../drivers/cam_req_mgr/cam_mem_mgr.h | 7 +- .../drivers/cam_req_mgr/cam_req_mgr_core.c | 227 +- .../drivers/cam_req_mgr/cam_req_mgr_core.h | 28 +- .../cam_req_mgr/cam_req_mgr_interface.h | 54 +- .../drivers/cam_req_mgr/cam_req_mgr_workq.c | 4 +- .../drivers/cam_req_mgr/cam_subdev.h | 3 +- .../cam_actuator/cam_actuator_dev.c | 68 +- .../cam_sensor_module/cam_cci/cam_cci_core.c | 95 +- .../cam_sensor_module/cam_cci/cam_cci_core.h | 1 + .../cam_sensor_module/cam_cci/cam_cci_dev.c | 74 +- .../cam_sensor_module/cam_cci/cam_cci_dev.h | 4 +- .../cam_sensor_module/cam_cci/cam_cci_hwreg.h | 2 +- .../cam_sensor_module/cam_cci/cam_cci_soc.c | 11 +- .../cam_csiphy/cam_csiphy_core.c | 210 +- .../cam_csiphy/cam_csiphy_dev.c | 122 +- .../cam_csiphy/cam_csiphy_dev.h | 4 +- .../cam_csiphy/cam_csiphy_soc.c | 34 +- .../cam_csiphy/cam_csiphy_soc.h | 1 + .../include/cam_csiphy_2_2_1_hwreg.h | 2218 ++++++++++ .../cam_eeprom/cam_eeprom_core.c | 51 +- .../cam_sensor_module/cam_eeprom/hi1337_otp.h | 2 +- .../cam_sensor_module/cam_eeprom/hi847_otp.h | 2 +- .../cam_flash/cam_flash_core.c | 5 +- .../cam_flash/cam_flash_dev.c | 4 + .../cam_flash/cam_flash_dev.h | 6 +- .../cam_sensor_module/cam_ois/cam_ois_core.c | 11 +- .../cam_res_mgr/cam_res_mgr.c | 97 +- .../cam_sensor_adaptive_mipi_imx258.h | 0 .../cam_sensor_adaptive_mipi_imx374.h | 0 .../cam_sensor_adaptive_mipi_imx374_2_0.h | 0 .../cam_sensor_adaptive_mipi_imx471.h | 0 .../cam_sensor_adaptive_mipi_imx471_2_0.h | 0 .../cam_sensor_adaptive_mipi_imx564.h | 0 .../cam_sensor_adaptive_mipi_imx596_2_0.h | 0 .../cam_sensor_adaptive_mipi_imx754.h | 0 .../cam_sensor_adaptive_mipi_imx854_2_0.h | 0 .../cam_sensor_adaptive_mipi_s5k2ld.h | 0 .../cam_sensor_adaptive_mipi_s5k3j1.h | 1246 +++--- .../cam_sensor_adaptive_mipi_s5k3j1_2_0.h | 3830 ++++++++--------- .../cam_sensor_adaptive_mipi_s5k3k1.h | 0 .../cam_sensor_adaptive_mipi_s5k3lu.h | 0 .../cam_sensor_adaptive_mipi_s5k3lu_2_0_q6a.h | 0 .../cam_sensor_adaptive_mipi_s5k3lu_uw_2_0.h | 0 .../cam_sensor_adaptive_mipi_s5kgn3.h | 0 .../cam_sensor_adaptive_mipi_s5khp2.h | 0 .../cam_sensor/cam_sensor_core.c | 55 +- .../cam_sensor/cam_sensor_dev.c | 6 +- .../cam_sensor/cam_sensor_dev.h | 2 + .../cam_sensor/cam_sensor_soc.c | 4 + .../cam_sensor_io/cam_sensor_cci_i2c.c | 2 +- .../cam_sensor_io/cam_sensor_qup_i2c.c | 10 +- .../cam_sensor_io/cam_sensor_qup_i3c.c | 10 +- .../cam_sensor_utils/cam_sensor_util.c | 48 +- .../kunit_test/cam_hw_bigdata_test.h | 2 +- .../cam_sensor_module/cam_tpg/cam_tpg_core.c | 63 +- .../cam_sensor_module/cam_tpg/cam_tpg_dev.c | 22 +- .../cam_sensor_module/cam_tpg/cam_tpg_dev.h | 4 +- .../cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.c | 1 + .../tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.c | 3 +- .../drivers/cam_smmu/cam_smmu_api.c | 28 +- .../drivers/cam_sync/cam_sync_dma_fence.c | 28 +- .../drivers/cam_sync/cam_sync_synx.c | 8 +- .../drivers/cam_sync/cam_sync_util.c | 15 +- .../drivers/cam_utils/cam_common_util.c | 12 +- .../drivers/cam_utils/cam_common_util.h | 4 +- .../drivers/cam_utils/cam_compat.c | 22 +- .../drivers/cam_utils/cam_compat.h | 7 +- .../drivers/cam_utils/cam_debug_util.c | 1 - .../drivers/cam_utils/cam_soc_bus.h | 2 +- .../drivers/cam_utils/cam_soc_util.c | 156 +- .../drivers/cam_utils/cam_soc_util.h | 18 +- .../drivers/kunit_test/camera_kunit_main.c | 0 .../drivers/kunit_test/camera_kunit_main.h | 0 .../camera-kernel/dt-bindings/msm-camera.h | 3 +- .../include/uapi/camera/media/cam_cpas.h | 14 + .../include/uapi/camera/media/cam_defs.h | 15 + .../include/uapi/camera/media/cam_isp_tfe.h | 6 +- .../include/uapi/camera/media/cam_tfe.h | 119 +- .../pineapple_consolidate_defconfig | 11 - .../camera-kernel/pineapple_defconfig | 3 + .../camera-kernel/pineapple_gki_defconfig | 11 - 213 files changed, 21648 insertions(+), 5492 deletions(-) create mode 100644 qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_210.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v665_100.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v770_100.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v860_100.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_110.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid860.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite860.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe860.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid665.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid770.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe665.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe770.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_lite770.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe860.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite86x.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_770_hw_info_ver_4_2_0.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_770_hw_info_ver_4_2_0.h create mode 100644 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_2_1_hwreg.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx258.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx374.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx374_2_0.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx471.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx471_2_0.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx564.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx596_2_0.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx754.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx854_2_0.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k2ld.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1_2_0.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3k1.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu_2_0_q6a.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu_uw_2_0.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5kgn3.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5khp2.h mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/kunit_test/camera_kunit_main.c mode change 100644 => 100755 qcom/opensource/camera-kernel/drivers/kunit_test/camera_kunit_main.h delete mode 100644 qcom/opensource/camera-kernel/pineapple_consolidate_defconfig delete mode 100644 qcom/opensource/camera-kernel/pineapple_gki_defconfig diff --git a/qcom/opensource/camera-kernel/Kbuild b/qcom/opensource/camera-kernel/Kbuild index 50756a5acd..e21c7248dd 100644 --- a/qcom/opensource/camera-kernel/Kbuild +++ b/qcom/opensource/camera-kernel/Kbuild @@ -6,12 +6,8 @@ $(info "KERNEL_ROOT is: $(KERNEL_ROOT)") endif # Include Architecture configurations -ifeq ($(CONFIG_ARCH_PINEAPPLE), y) -include $(CAMERA_KERNEL_ROOT)/config/pineapple.mk -endif - -ifeq ($(CONFIG_ARCH_KALAMA), y) -include $(CAMERA_KERNEL_ROOT)/config/kalama.mk +ifeq ($(CONFIG_ARCH_CLIFFS), y) +include $(CAMERA_KERNEL_ROOT)/config/cliffs.mk endif ifeq ($(CONFIG_ARCH_WAIPIO), y) @@ -54,6 +50,24 @@ ifeq ($(CONFIG_ARCH_PARROT), y) include $(CAMERA_KERNEL_ROOT)/config/parrot.mk endif +# For some targets which have binary compatible gki kernel with another one, +# we cannot rely on CONFIG_ARCH_* symbol which is defined in Kernel defconfig +ifeq ($(BOARD_PLATFORM), kalama) +include $(CAMERA_KERNEL_ROOT)/config/kalama.mk +endif + +ifeq ($(BOARD_PLATFORM), crow) +include $(CAMERA_KERNEL_ROOT)/config/crow.mk +endif + +ifeq ($(BOARD_PLATFORM), pineapple) +include $(CAMERA_KERNEL_ROOT)/config/pineapple.mk +endif + +ifeq ($(BOARD_PLATFORM), volcano) +include $(CAMERA_KERNEL_ROOT)/config/volcano.mk +endif + ifneq ($(KBUILD_EXTRA_CONFIGS),) include $(KBUILD_EXTRA_CONFIGS) endif diff --git a/qcom/opensource/camera-kernel/Kconfig b/qcom/opensource/camera-kernel/Kconfig index 86b2e8f20f..ae59148c2c 100644 --- a/qcom/opensource/camera-kernel/Kconfig +++ b/qcom/opensource/camera-kernel/Kconfig @@ -6,6 +6,13 @@ config SPECTRA_ISP This will enable camera ISP driver to handle IFE driver. Core camera driver to handle VFE HW. +config SPECTRA_TFE + bool "enable camera tfe modele" + help + This is enabling camera tfe module. + tfe module files will be included to enable tfe based driver, + files. + config SPECTRA_ICP bool "enable camera ICP module" help @@ -21,7 +28,13 @@ config SPECTRA_JPEG camera jpeg module will be functional. This module interact with jpeg HW for snapshot processing. - +config SPECTRA_CRE + bool "enable camera jpeg module" + help + This is enabling camera CRE module. + camera cre module will be functional. + This module interact with cre HW for + format conversion. config SPECTRA_SENSOR bool "enable camera sensor module" help @@ -86,6 +99,22 @@ config DOMAIN_ID_SECURE_CAMERA domain ID based security architecture. VC based security can be achieved with this. +config CSF_2_5_SECURE_CAMERA + bool "enable CSF2.5 feature flow" + help + This is to enable Call flow for CSF2.5 + enabled platforms. this config differentiates + between csf2.0 and csf 2.5 compliant + scm calls. + +config DYNAMIC_FD_PORT_CONFIG + bool "enable dynamic FD port config feature" + help + This config enables dynamic FD port config + feature that allows the userspace to configure + the FD port to secure or non-secure based on + the FD solution in use in secure camera use cases. + config SAMSUNG_OIS_MCU_STM32 bool "enable camera mcu stm32 module" help diff --git a/qcom/opensource/camera-kernel/config/pineapple.mk b/qcom/opensource/camera-kernel/config/pineapple.mk index a4c3bac7bb..0407f8db0b 100644 --- a/qcom/opensource/camera-kernel/config/pineapple.mk +++ b/qcom/opensource/camera-kernel/config/pineapple.mk @@ -4,21 +4,27 @@ CONFIG_SPECTRA_ISP := y CONFIG_SPECTRA_ICP := y CONFIG_SPECTRA_JPEG := y +CONFIG_SPECTRA_CRE := y CONFIG_SPECTRA_SENSOR := y CONFIG_SPECTRA_LLCC_STALING := y CONFIG_SPECTRA_USE_RPMH_DRV_API := y CONFIG_SPECTRA_USE_CLK_CRM_API := y CONFIG_DOMAIN_ID_SECURE_CAMERA := y +CONFIG_DYNAMIC_FD_PORT_CONFIG := y +CONFIG_CSF_2_5_SECURE_CAMERA := y # Flags to pass into C preprocessor ccflags-y += -DCONFIG_SPECTRA_ISP=1 ccflags-y += -DCONFIG_SPECTRA_ICP=1 ccflags-y += -DCONFIG_SPECTRA_JPEG=1 +ccflags-y += -DCONFIG_SPECTRA_CRE=1 ccflags-y += -DCONFIG_SPECTRA_SENSOR=1 ccflags-y += -DCONFIG_SPECTRA_LLCC_STALING=1 ccflags-y += -DCONFIG_SPECTRA_USE_RPMH_DRV_API=1 ccflags-y += -DCONFIG_SPECTRA_USE_CLK_CRM_API=1 ccflags-y += -DCONFIG_DOMAIN_ID_SECURE_CAMERA=1 +ccflags-y += -DCONFIG_DYNAMIC_FD_PORT_CONFIG=1 +ccflags-y += -DCONFIG_CSF_2_5_SECURE_CAMERA=1 ifeq (y, $(filter y, \ $(CONFIG_SEC_PLATFORM_MU1Q) \ diff --git a/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_core.c b/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_core.c index 21bd2ccca9..4beee9d64f 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_core.c @@ -2349,7 +2349,7 @@ static int cam_hw_cdm_component_bind(struct device *dev, sizeof(work_q_name)); snprintf(work_q_name + len, sizeof(work_q_name) - len, "%d_%d", cdm_hw->soc_info.index, i); cdm_core->bl_fifo[i].work_queue = alloc_workqueue(work_q_name, - WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS | WQ_HIGHPRI, + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, CAM_CDM_INFLIGHT_WORKS); if (!cdm_core->bl_fifo[i].work_queue) { CAM_ERR(CAM_CDM, diff --git a/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.c b/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.c index b0c9956c98..31b0b9b8bd 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.c @@ -18,7 +18,6 @@ #define CAM_CDM_SW_CMD_COUNT 2 #define CAM_CMD_LENGTH_MASK 0xFFFF -#define CAM_CDM_COMMAND_OFFSET 24 #define CAM_CDM_REG_OFFSET_MASK 0x00FFFFFF #define CAM_CDM_DMI_DATA_HI_OFFSET 8 @@ -493,7 +492,7 @@ int cam_cdm_get_ioremap_from_base(uint32_t hw_base, static int cam_cdm_util_cmd_buf_validation(void __iomem *base_addr, uint32_t base_array_size, struct cam_soc_reg_map *base_table[CAM_SOC_MAX_BLOCK], - uint32_t cmd_buf_size, uint32_t *buf, + uint32_t cmd_buf_size, uint32_t *cmd_buf, void *buf, resource_size_t *size, enum cam_cdm_command cmd_type) { @@ -521,6 +520,8 @@ static int cam_cdm_util_cmd_buf_validation(void __iomem *base_addr, switch (cmd_type) { case CAM_CDM_CMD_REG_RANDOM: { struct cdm_regrandom_cmd *reg_random = (struct cdm_regrandom_cmd *)buf; + uint32_t *data, offset; + if ((!reg_random->count) || (((reg_random->count * (sizeof(uint32_t) * 2)) + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)) > cmd_buf_size)) { @@ -528,10 +529,23 @@ static int cam_cdm_util_cmd_buf_validation(void __iomem *base_addr, reg_random->count, cmd_buf_size); ret = -EINVAL; } + + data = cmd_buf + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + + for (i = 0; i < reg_random->count; i++) { + offset = data[0]; + if (offset > *size) { + CAM_ERR(CAM_CDM, "Offset out of mapped range! size:%llu offset:%u", + *size, offset); + return -EINVAL; + } + data += 2; + } } break; case CAM_CDM_CMD_REG_CONT: { struct cdm_regcontinuous_cmd *reg_cont = (struct cdm_regcontinuous_cmd *) buf; + if ((!reg_cont->count) || (((reg_cont->count * sizeof(uint32_t)) + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) > cmd_buf_size)) { @@ -539,17 +553,66 @@ static int cam_cdm_util_cmd_buf_validation(void __iomem *base_addr, cmd_buf_size, reg_cont->count); ret = -EINVAL; } + + if ((reg_cont->offset > *size) && ((reg_cont->offset + + (reg_cont->count * sizeof(uint32_t))) > *size)) { + CAM_ERR(CAM_CDM, "Offset out of mapped range! size: %lu, offset: %u", + *size, reg_cont->offset); + return -EINVAL; + } } break; - case CAM_CDM_CMD_DMI: - case CAM_CDM_CMD_SWD_DMI_32: case CAM_CDM_CMD_SWD_DMI_64: { struct cdm_dmi_cmd *swd_dmi = (struct cdm_dmi_cmd *) buf; + if (cmd_buf_size < (cam_cdm_required_size_dmi() + swd_dmi->length + 1)) { CAM_ERR(CAM_CDM, "invalid CDM_SWD_DMI length %d", swd_dmi->length + 1); ret = -EINVAL; } + + if ((swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET > *size) || + (swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_HI_OFFSET > *size)) { + CAM_ERR(CAM_CDM, + "Offset out of mapped range! size:%llu lo_offset:%u hi_offset:%u", + *size, swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET, + swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); + return -EINVAL; + } + } + break; + case CAM_CDM_CMD_SWD_DMI_32: { + struct cdm_dmi_cmd *swd_dmi = (struct cdm_dmi_cmd *) buf; + + if (cmd_buf_size < (cam_cdm_required_size_dmi() + swd_dmi->length + 1)) { + CAM_ERR(CAM_CDM, "invalid CDM_SWD_DMI length %d", + swd_dmi->length + 1); + ret = -EINVAL; + } + + if (swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET > *size) { + CAM_ERR(CAM_CDM, + "Offset out of mapped range! size:%llu lo_offset:%u", + *size, swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); + return -EINVAL; + } + } + break; + case CAM_CDM_CMD_DMI: { + struct cdm_dmi_cmd *swd_dmi = (struct cdm_dmi_cmd *) buf; + + if (cmd_buf_size < (cam_cdm_required_size_dmi() + swd_dmi->length + 1)) { + CAM_ERR(CAM_CDM, "invalid CDM_SWD_DMI length %d", + swd_dmi->length + 1); + ret = -EINVAL; + } + + if (swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_OFFSET > *size) { + CAM_ERR(CAM_CDM, + "Offset out of mapped range! size:%llu offset:%u", + *size, swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_OFFSET); + return -EINVAL; + } } break; default: @@ -572,27 +635,19 @@ static int cam_cdm_util_reg_cont_write(void __iomem *base_addr, struct cdm_regcontinuous_cmd reg_cont; resource_size_t size = 0; + memcpy(®_cont, cmd_buf, sizeof(struct cdm_regcontinuous_cmd)); rc = cam_cdm_util_cmd_buf_validation(base_addr, base_array_size, base_table, - cmd_buf_size, cmd_buf, &size, CAM_CDM_CMD_REG_CONT); + cmd_buf_size, cmd_buf, (void *)®_cont, + &size, CAM_CDM_CMD_REG_CONT); if (rc) { CAM_ERR(CAM_CDM, "Validation failed! rc=%d", rc); return rc; } - memcpy(®_cont, cmd_buf, sizeof(struct cdm_regcontinuous_cmd)); - data = cmd_buf + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT); - if ((reg_cont.offset <= size) && ((reg_cont.offset + - (reg_cont.count * sizeof(uint32_t))) <= size)) { - cam_io_memcpy(base_addr + reg_cont.offset, data, - reg_cont.count * sizeof(uint32_t)); - } else { - CAM_ERR(CAM_CDM, "Offset out of mapped range! size: %lu, offset: %u", - size, reg_cont.offset); - return -EINVAL; - } - + cam_io_memcpy(base_addr + reg_cont.offset, data, + reg_cont.count * sizeof(uint32_t)); *used_bytes = (reg_cont.count * sizeof(uint32_t)) + (4 * cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)); @@ -609,30 +664,25 @@ static int cam_cdm_util_reg_random_write(void __iomem *base_addr, uint32_t *data, offset; resource_size_t size = 0; + memcpy(®_random, cmd_buf, sizeof(struct cdm_regrandom_cmd)); + rc = cam_cdm_util_cmd_buf_validation(base_addr, base_array_size, base_table, - cmd_buf_size, cmd_buf, + cmd_buf_size, cmd_buf, (void *)®_random, &size, CAM_CDM_CMD_REG_RANDOM); if (rc) { CAM_ERR(CAM_CDM, "Validation failed! rc=%d", rc); return rc; } - memcpy(®_random, cmd_buf, sizeof(struct cdm_regrandom_cmd)); data = cmd_buf + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); for (i = 0; i < reg_random.count; i++) { offset = data[0]; - if (offset <= size) { - CAM_DBG(CAM_CDM, "reg random: offset %pK, value 0x%x", - ((void __iomem *)(base_addr + offset)), - data[1]); - cam_io_w(data[1], base_addr + offset); - data += 2; - } else { - CAM_ERR(CAM_CDM, "Offset out of mapped range! size: %llu, offset: %u", - size, offset); - return -EINVAL; - } + CAM_DBG(CAM_CDM, "reg random: offset %pK, value 0x%x", + ((void __iomem *)(base_addr + offset)), + data[1]); + cam_io_w(data[1], base_addr + offset); + data += 2; } *used_bytes = ((reg_random.count * (sizeof(uint32_t) * 2)) + @@ -651,52 +701,32 @@ static int cam_cdm_util_swd_dmi_write(uint32_t cdm_cmd_type, uint32_t *data; resource_size_t size = 0; + memcpy(&swd_dmi, cmd_buf, sizeof(struct cdm_dmi_cmd)); rc = cam_cdm_util_cmd_buf_validation(base_addr, base_array_size, base_table, - cmd_buf_size, cmd_buf, + cmd_buf_size, cmd_buf, (void *)&swd_dmi, &size, cdm_cmd_type); if (rc) { CAM_ERR(CAM_CDM, "Validation failed! rc=%d", rc); return rc; } - memcpy(&swd_dmi, cmd_buf, sizeof(struct cdm_dmi_cmd)); data = cmd_buf + cam_cdm_required_size_dmi(); if (cdm_cmd_type == CAM_CDM_CMD_SWD_DMI_64) { - if ((swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET > size) || - (swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_HI_OFFSET > size)) { - CAM_ERR(CAM_CDM, - "Offset out of mapped range! size:%llu lo_offset:%u hi_offset:%u", - size, swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET, - swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); - return -EINVAL; - } for (i = 0; i < (swd_dmi.length + 1)/8; i++) { cam_io_w_mb(data[0], base_addr + swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); cam_io_w_mb(data[1], base_addr + - swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_HI_OFFSET); + swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_HI_OFFSET); data += 2; } } else if (cdm_cmd_type == CAM_CDM_CMD_DMI) { - if (swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_OFFSET > size) { - CAM_ERR(CAM_CDM, - "Offset out of mapped range! size:%llu offset:%u", - size, swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_OFFSET); - return -EINVAL; - } for (i = 0; i < (swd_dmi.length + 1)/4; i++) { cam_io_w_mb(data[0], base_addr + swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_OFFSET); data += 1; } } else { - if (swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET > size) { - CAM_ERR(CAM_CDM, - "Offset out of mapped range! size:%llu lo_offset:%u", - size, swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); - return -EINVAL; - } for (i = 0; i < (swd_dmi.length + 1)/4; i++) { cam_io_w_mb(data[0], base_addr + swd_dmi.DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); @@ -981,6 +1011,88 @@ static long cam_cdm_util_dump_perf_ctrl_cmd(uint32_t *cmd_buf_addr) return ret; } +bool cam_cdm_util_validate_cmd_buf( + uint32_t *cmd_buf_start, uint32_t *cmd_buf_end) +{ + uint32_t *buf_now = cmd_buf_start; + uint32_t *buf_end = cmd_buf_end; + uint32_t cmd = 0; + int i = 0; + struct cdm_regcontinuous_cmd *p_regcont_cmd = NULL; + struct cdm_regrandom_cmd *p_regrand_cmd = NULL; + + if (!cmd_buf_start || !cmd_buf_end) { + CAM_ERR(CAM_CDM, "Invalid args"); + return true; + } + + do { + cmd = *buf_now; + cmd = cmd >> CAM_CDM_COMMAND_OFFSET; + + switch (cmd) { + case CAM_CDM_CMD_DMI: + case CAM_CDM_CMD_DMI_32: + case CAM_CDM_CMD_DMI_64: + if (buf_now > buf_end) + return true; + + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_DMI]; + break; + case CAM_CDM_CMD_REG_CONT: + p_regcont_cmd = (struct cdm_regcontinuous_cmd *)buf_now; + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_REG_CONT]; + for (i = 0; i < p_regcont_cmd->count; i++) { + if (buf_now > buf_end) + return true; + + buf_now++; + } + break; + case CAM_CDM_CMD_REG_RANDOM: + p_regrand_cmd = (struct cdm_regrandom_cmd *)buf_now; + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_REG_RANDOM]; + for (i = 0; i < p_regrand_cmd->count; i++) { + if (buf_now > buf_end) + return true; + + buf_now += 2; + } + break; + case CAM_CDM_CMD_BUFF_INDIRECT: + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_BUFF_INDIRECT]; + if (buf_now > buf_end) + return true; + + break; + case CAM_CDM_CMD_GEN_IRQ: + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_GEN_IRQ]; + break; + case CAM_CDM_CMD_WAIT_EVENT: + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_WAIT_EVENT]; + break; + case CAM_CDM_CMD_CHANGE_BASE: + if (buf_now > buf_end) + return true; + + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_CHANGE_BASE]; + break; + case CAM_CDM_CMD_PERF_CTRL: + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_PERF_CTRL]; + break; + case CAM_CDM_CMD_COMP_WAIT: + buf_now += CDMCmdHeaderSizes[CAM_CDM_CMD_COMP_WAIT]; + break; + default: + CAM_ERR(CAM_CDM, "Invalid CMD: 0x%x buf 0x%x", + cmd, *buf_now); + return true; + } + } while (buf_now < cmd_buf_end); + + return false; +} + void cam_cdm_util_dump_cmd_buf( uint32_t *cmd_buf_start, uint32_t *cmd_buf_end) { @@ -1039,7 +1151,7 @@ void cam_cdm_util_dump_cmd_buf( buf_now++; break; } - } while (buf_now <= cmd_buf_end); + } while (buf_now < cmd_buf_end); } static uint32_t cam_cdm_util_dump_reg_cont_cmd_v2( @@ -1210,6 +1322,6 @@ int cam_cdm_util_dump_cmd_bufs_v2( buf_now++; break; } - } while (buf_now <= dump_info->src_end); + } while (buf_now < dump_info->src_end); return rc; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.h b/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.h index d566960a9c..ecdb228e39 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.h @@ -9,6 +9,7 @@ /* Max len for tag name for header while dumping cmd buffer*/ #define CAM_CDM_CMD_TAG_MAX_LEN 128 +#define CAM_CDM_COMMAND_OFFSET 24 #include @@ -227,6 +228,20 @@ struct cam_cdm_cmd_dump_header { uint32_t word_size; }; +/** + * cam_cdm_util_validate_cmd_buf() + * + * @brief: Util function to validate cdm command buffers + * + * @cmd_buffer_start: Pointer to start of cmd buffer + * @cmd_buffer_end: Pointer to end of cmd buffer + * + * return true if invalid cmd found, otherwise false + * + */ +bool cam_cdm_util_validate_cmd_buf( + uint32_t *cmd_buffer_start, uint32_t *cmd_buffer_end); + /** * cam_cdm_util_log_cmd_bufs() * diff --git a/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.c b/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.c index 100ed22500..2f62cc8d9e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.c +++ b/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -355,6 +355,31 @@ int cam_context_dump_pf_info(void *data, void *args) return rc; } +int cam_context_handle_message(struct cam_context *ctx, + uint32_t msg_type, void *data) +{ + int rc = 0; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if ((ctx->state > CAM_CTX_AVAILABLE) && + (ctx->state < CAM_CTX_STATE_MAX)) { + if (ctx->state_machine[ctx->state].msg_cb_ops) { + rc = ctx->state_machine[ctx->state].msg_cb_ops( + ctx, msg_type, data); + } else { + CAM_WARN(CAM_CORE, + "No message handler for ctx %d, state %d msg_type :%d", + ctx->dev_hdl, ctx->state, msg_type); + } + } + + return rc; +} + int cam_context_handle_acquire_dev(struct cam_context *ctx, struct cam_acquire_dev_cmd *cmd) { diff --git a/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.h b/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.h index 1e621f7813..39d2407aff 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.h +++ b/qcom/opensource/camera-kernel/drivers/cam_core/cam_context.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CONTEXT_H_ @@ -168,7 +168,9 @@ struct cam_ctx_crm_ops { * context info * @recovery_ops: Function to be invoked to try hardware recovery * @mini_dump_ops: Function for mini dump - * @evt_inject_ops: Function for event injection + * @err_inject_ops: Function for error injection + * @msg_cb_ops: Function to be called on any message from + * other subdev notifications * */ struct cam_ctx_ops { @@ -180,6 +182,7 @@ struct cam_ctx_ops { cam_ctx_recovery_cb_func recovery_ops; cam_ctx_mini_dump_cb_func mini_dump_ops; cam_ctx_err_inject_cb_func evt_inject_ops; + cam_ctx_message_cb_func msg_cb_ops; }; @@ -273,6 +276,38 @@ struct cam_context { struct timespec64 cdm_done_ts; }; +/** + * struct cam_context_stream_dump - camera context stream information + * + * @hw_mgr_ctx_id: Hw Mgr context id returned from hw mgr + * @dev_id: ID of device associated + * @dev_hdl: Device handle + * @link_hdl: Link handle + * @sessoin_hdl: Session handle + * @refcount: Context object refcount + * @last_flush_req: Last request to flush + * @state: Current state for top level state machine + */ +struct cam_context_stream_dump { + uint32_t hw_mgr_ctx_id; + uint32_t dev_id; + uint32_t dev_hdl; + uint32_t link_hdl; + uint32_t session_hdl; + uint32_t refcount; + uint32_t last_flush_req; + enum cam_context_state state; +}; + +/** + * struct cam_context_each_req_info - camera each request information + * + * @request_id: request id + */ +struct cam_context_each_req_info { + uint64_t request_id; +}; + /** * struct cam_context_dump_header - Function for context dump header * @@ -416,6 +451,19 @@ int cam_context_mini_dump_from_hw(struct cam_context *ctx, int cam_context_dump_pf_info(void *ctx, void *pf_args); +/** + * cam_context_handle_message() + * + * @brief: Handle message callback command + * + * @ctx: Object pointer for cam_context + * @msg_type: message type sent from other subdev + * @data: data from other subdev + * + */ +int cam_context_handle_message(struct cam_context *ctx, + uint32_t msg_type, void *data); + /** * cam_context_handle_acquire_dev() * diff --git a/qcom/opensource/camera-kernel/drivers/cam_core/cam_context_utils.c b/qcom/opensource/camera-kernel/drivers/cam_core/cam_context_utils.c index 96a965d829..1c0faff812 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_core/cam_context_utils.c +++ b/qcom/opensource/camera-kernel/drivers/cam_core/cam_context_utils.c @@ -1487,6 +1487,40 @@ end: return rc; } +static int cam_context_dump_data_validaion(void *src, void *dest, + uint32_t base_len, uint32_t actual_len, uint32_t bytes_required) +{ + if (base_len + bytes_required >= actual_len) { + CAM_ERR(CAM_CTXT, "actual len %pK base len %pK", + actual_len, base_len); + return -ENOSPC; + } + memcpy(dest, src, bytes_required); + return 0; +} + +static int cam_context_stream_dump_validation(struct cam_context *ctx, + uint64_t *addr, uint32_t local_len, uint32_t buf_len) +{ + struct cam_context_stream_dump stream_dump; + + stream_dump.hw_mgr_ctx_id = ctx->hw_mgr_ctx_id; + stream_dump.dev_id = ctx->dev_id; + stream_dump.dev_hdl = ctx->dev_hdl; + stream_dump.link_hdl = ctx->link_hdl; + stream_dump.session_hdl = ctx->session_hdl; + stream_dump.refcount = refcount_read(&(ctx->refcount.refcount)); + stream_dump.last_flush_req = ctx->last_flush_req; + stream_dump.state = ctx->state; + if (cam_context_dump_data_validaion(&stream_dump, addr, + local_len, buf_len, + sizeof(struct cam_context_stream_dump))) { + CAM_WARN(CAM_CTXT, "failed to copy the stream info"); + return -ENOSPC; + } + return 0; +} + static int cam_context_user_dump(struct cam_context *ctx, struct cam_hw_dump_args *dump_args) { @@ -1495,9 +1529,9 @@ static int cam_context_user_dump(struct cam_context *ctx, struct cam_context_dump_header *hdr; uint8_t *dst; uint64_t *addr, *start; - uint32_t min_len; size_t buf_len, remain_len; uintptr_t cpu_addr; + uint32_t local_len; if (!ctx || !dump_args) { CAM_ERR(CAM_CORE, "Invalid parameters %pK %pK", @@ -1521,107 +1555,31 @@ static int cam_context_user_dump(struct cam_context *ctx, return -ENOSPC; } - spin_lock_bh(&ctx->lock); - if (!list_empty(&ctx->active_req_list)) { - req = list_first_entry(&ctx->active_req_list, - struct cam_ctx_request, list); - } else if (!list_empty(&ctx->wait_req_list)) { - req = list_first_entry(&ctx->wait_req_list, - struct cam_ctx_request, list); - } else if (!list_empty(&ctx->pending_req_list)) { - req = list_first_entry(&ctx->pending_req_list, - struct cam_ctx_request, list); - } else { - CAM_ERR(CAM_CTXT, "[%s][%d] no request to dump", - ctx->dev_name, ctx->ctx_id); - } - spin_unlock_bh(&ctx->lock); - - /* Check for min len in case of available request to dump */ - if (req != NULL) { - remain_len = buf_len - dump_args->offset; - min_len = sizeof(struct cam_context_dump_header) + - (CAM_CTXT_DUMP_NUM_WORDS + req->num_in_map_entries + - (req->num_out_map_entries * 2)) * sizeof(uint64_t); - - if (remain_len < min_len) { - CAM_WARN(CAM_CTXT, "dump buffer exhaust remain %zu min %u", - remain_len, min_len); - cam_mem_put_cpu_buf(dump_args->buf_handle); - return -ENOSPC; - } - } - /* Dump context info */ + remain_len = buf_len - dump_args->offset; + if (remain_len < sizeof(struct cam_context_dump_header)) { + CAM_WARN(CAM_CTXT, + "No sufficient space in dump buffer for headers, remain buf size: %d, header size: %d", + remain_len, sizeof(struct cam_context_dump_header)); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; hdr = (struct cam_context_dump_header *)dst; + local_len = + (dump_args->offset + sizeof(struct cam_context_dump_header)); scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, "%s_CTX_INFO:", ctx->dev_name); hdr->word_size = sizeof(uint64_t); addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); start = addr; - *addr++ = ctx->hw_mgr_ctx_id; - *addr++ = ctx->dev_id; - *addr++ = ctx->dev_hdl; - *addr++ = ctx->link_hdl; - *addr++ = ctx->session_hdl; - *addr++ = refcount_read(&(ctx->refcount.refcount)); - *addr++ = ctx->last_flush_req; - *addr++ = ctx->state; - hdr->size = hdr->word_size * (addr - start); - dump_args->offset += hdr->size + - sizeof(struct cam_context_dump_header); - - /* Dump pending request IDs */ - dst = (uint8_t *)cpu_addr + dump_args->offset; - hdr = (struct cam_context_dump_header *)dst; - scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, - "%s_OUT_FENCE_PENDING_REQUESTS:", ctx->dev_name); - hdr->word_size = sizeof(uint64_t); - addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); - start = addr; - if (!list_empty(&ctx->pending_req_list)) { - list_for_each_entry_safe(req, req_temp, &ctx->pending_req_list, list) { - *addr++ = req->request_id; - } + if (cam_context_stream_dump_validation(ctx, addr, local_len, buf_len)) { + CAM_WARN(CAM_CTXT, "%s_CTX_INFO failed to copy the stream info ", ctx->dev_name); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; } - - hdr->size = hdr->word_size * (addr - start); - dump_args->offset += hdr->size + - sizeof(struct cam_context_dump_header); - - /* Dump wait request IDs */ - dst = (uint8_t *)cpu_addr + dump_args->offset; - hdr = (struct cam_context_dump_header *)dst; - scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, - "%s_OUT_FENCE_APPLIED_REQUESTS:", ctx->dev_name); - hdr->word_size = sizeof(uint64_t); - addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); - start = addr; - if (!list_empty(&ctx->wait_req_list)) { - list_for_each_entry_safe(req, req_temp, &ctx->wait_req_list, list) { - *addr++ = req->request_id; - } - } - - hdr->size = hdr->word_size * (addr - start); - dump_args->offset += hdr->size + - sizeof(struct cam_context_dump_header); - - /* Dump active request IDs */ - dst = (uint8_t *)cpu_addr + dump_args->offset; - hdr = (struct cam_context_dump_header *)dst; - scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, - "%s_OUT_FENCE_ACTIVE_REQUESTS:", ctx->dev_name); - hdr->word_size = sizeof(uint64_t); - addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); - start = addr; - if (!list_empty(&ctx->active_req_list)) { - list_for_each_entry_safe(req, req_temp, &ctx->active_req_list, list) { - *addr++ = req->request_id; - } - } - + addr = addr + sizeof(struct cam_context_stream_dump); hdr->size = hdr->word_size * (addr - start); dump_args->offset += hdr->size + sizeof(struct cam_context_dump_header); @@ -1630,8 +1588,19 @@ static int cam_context_user_dump(struct cam_context *ctx, if (!list_empty(&ctx->wait_req_list)) { list_for_each_entry_safe(req, req_temp, &ctx->wait_req_list, list) { for (i = 0; i < req->num_out_map_entries; i++) { + remain_len = buf_len - dump_args->offset; + if (remain_len < sizeof(struct cam_context_dump_header)) { + CAM_WARN(CAM_CTXT, + "No sufficient space in dump buffer for headers, remain buf size: %d, header size: %d", + remain_len, sizeof(struct cam_context_dump_header)); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; hdr = (struct cam_context_dump_header *)dst; + local_len = dump_args->offset + + sizeof(struct cam_context_dump_header); scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, "%s_OUT_FENCE_REQUEST_APPLIED.%d.%d.%d:", ctx->dev_name, @@ -1641,7 +1610,14 @@ static int cam_context_user_dump(struct cam_context *ctx, hdr->word_size = sizeof(uint64_t); addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); start = addr; - *addr++ = req->request_id; + if (cam_context_dump_data_validaion(&req->request_id, addr, + local_len, buf_len, + sizeof(struct cam_context_each_req_info))) { + CAM_WARN(CAM_CTXT, "%s_CTX_INFO waiting_req: failed to copy the request info", + ctx->dev_name); + goto cleanup; + } + addr = addr + sizeof(struct cam_context_each_req_info); hdr->size = hdr->word_size * (addr - start); dump_args->offset += hdr->size + sizeof(struct cam_context_dump_header); @@ -1653,8 +1629,19 @@ static int cam_context_user_dump(struct cam_context *ctx, if (!list_empty(&ctx->pending_req_list)) { list_for_each_entry_safe(req, req_temp, &ctx->pending_req_list, list) { for (i = 0; i < req->num_out_map_entries; i++) { + remain_len = buf_len - dump_args->offset; + if (remain_len < sizeof(struct cam_context_dump_header)) { + CAM_WARN(CAM_CTXT, + "No sufficient space in dump buffer for headers, remain buf size: %d, header size: %d", + remain_len, sizeof(struct cam_context_dump_header)); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; hdr = (struct cam_context_dump_header *)dst; + local_len = dump_args->offset + + sizeof(struct cam_context_dump_header); scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, "%s_OUT_FENCE_REQUEST_PENDING.%d.%d.%d:", ctx->dev_name, @@ -1664,7 +1651,14 @@ static int cam_context_user_dump(struct cam_context *ctx, hdr->word_size = sizeof(uint64_t); addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); start = addr; - *addr++ = req->request_id; + if (cam_context_dump_data_validaion(&req->request_id, addr, + local_len, buf_len, + sizeof(struct cam_context_each_req_info))) { + CAM_WARN(CAM_CTXT, "%s_CTX_INFO pending_req: failed to copy the request info", + ctx->dev_name); + goto cleanup; + } + addr = addr + sizeof(struct cam_context_each_req_info); hdr->size = hdr->word_size * (addr - start); dump_args->offset += hdr->size + sizeof(struct cam_context_dump_header); @@ -1676,8 +1670,19 @@ static int cam_context_user_dump(struct cam_context *ctx, if (!list_empty(&ctx->active_req_list)) { list_for_each_entry_safe(req, req_temp, &ctx->active_req_list, list) { for (i = 0; i < req->num_out_map_entries; i++) { + remain_len = buf_len - dump_args->offset; + if (remain_len < sizeof(struct cam_context_dump_header)) { + CAM_WARN(CAM_CTXT, + "No sufficient space in dump buffer for headers, remain buf size: %d, header size: %d", + remain_len, sizeof(struct cam_context_dump_header)); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; hdr = (struct cam_context_dump_header *)dst; + local_len = dump_args->offset + + sizeof(struct cam_context_dump_header); scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, "%s_OUT_FENCE_REQUEST_ACTIVE.%d.%d.%d:", ctx->dev_name, @@ -1687,14 +1692,21 @@ static int cam_context_user_dump(struct cam_context *ctx, hdr->word_size = sizeof(uint64_t); addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); start = addr; - *addr++ = req->request_id; + if (cam_context_dump_data_validaion(&req->request_id, addr, + local_len, buf_len, + sizeof(struct cam_context_each_req_info))) { + CAM_WARN(CAM_CTXT, "%s_CTX_INFO active_req: failed to copy the request info", + ctx->dev_name); + goto cleanup; + } + addr = addr + sizeof(struct cam_context_each_req_info); hdr->size = hdr->word_size * (addr - start); dump_args->offset += hdr->size + sizeof(struct cam_context_dump_header); } } } - +cleanup: cam_mem_put_cpu_buf(dump_args->buf_handle); return 0; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_core/cam_hw_mgr_intf.h b/qcom/opensource/camera-kernel/drivers/cam_core/cam_hw_mgr_intf.h index 0735e1c7d9..a8d506d4a1 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_core/cam_hw_mgr_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_core/cam_hw_mgr_intf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_HW_MGR_INTF_H_ @@ -80,6 +80,10 @@ typedef int (*cam_ctx_mini_dump_cb_func)(void *context, typedef int (*cam_ctx_err_inject_cb_func)(void *context, void *args); +/* message callback function type */ +typedef int (*cam_ctx_message_cb_func)(void *context, + uint32_t message_type, void *data); + /** * struct cam_hw_update_entry - Entry for hardware config * @@ -165,11 +169,13 @@ struct cam_hw_acquire_stream_caps { * @hw_mgr_ctx_id HWMgr context id(returned) * @op_flags: Used as bitwise params from hw_mgr to ctx * See xxx_hw_mgr_intf.h for definitions + * @link_hdl: Link handle * @acquired_hw_id: Acquired hardware mask * @acquired_hw_path: Acquired path mask for an input * if input splits into multiple paths, * its updated per hardware * @valid_acquired_hw: Valid num of acquired hardware + * @total_ports_acq Total ports acquired ipp+ppp+rdi * @op_params: OP Params from hw_mgr to ctx * @mini_dump_cb: Mini dump callback function * @@ -185,11 +191,11 @@ struct cam_hw_acquire_args { void *ctxt_to_hw_map; uint32_t hw_mgr_ctx_id; uint32_t op_flags; - - uint32_t acquired_hw_id[CAM_MAX_ACQ_RES]; - uint32_t acquired_hw_path[CAM_MAX_ACQ_RES][CAM_MAX_HW_SPLIT]; - uint32_t valid_acquired_hw; - + int32_t link_hdl; + uint32_t acquired_hw_id[CAM_MAX_ACQ_RES]; + uint32_t acquired_hw_path[CAM_MAX_ACQ_RES][CAM_MAX_HW_SPLIT]; + uint32_t valid_acquired_hw; + uint32_t total_ports_acq; struct cam_hw_acquire_stream_caps op_params; cam_ctx_mini_dump_cb_func mini_dump_cb; }; diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.c b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.c index b442c0a3b8..0c029d39a2 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -514,7 +514,7 @@ bus_register_fail: return rc; } -static int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw, +int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw, int enable) { int rc, i = 0; @@ -983,7 +983,8 @@ static int cam_cpas_apply_smart_qos( struct cam_cpas_tree_node *niu_node; struct cam_camnoc_info *camnoc_info; uint8_t i; - int32_t reg_indx; + int32_t reg_indx, cam_qos_cnt = 0, ret = 0; + struct qcom_scm_camera_qos scm_buf[QCOM_SCM_CAMERA_MAX_QOS_CNT] = {0}; if (cpas_core->smart_qos_dump) { CAM_INFO(CAM_PERF, "Printing SmartQos values before update"); @@ -998,20 +999,44 @@ static int cam_cpas_apply_smart_qos( niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i]; if (niu_node->curr_priority_high != niu_node->applied_priority_high) { - cam_io_w_mb(niu_node->curr_priority_high, - soc_info->reg_map[reg_indx].mem_base + - niu_node->pri_lut_high_offset); + if (!soc_private->enable_secure_qos_update) { + cam_io_w_mb(niu_node->curr_priority_high, + soc_info->reg_map[reg_indx].mem_base + + niu_node->pri_lut_high_offset); + } else { + scm_buf[cam_qos_cnt].offset = niu_node->pri_lut_high_offset; + scm_buf[cam_qos_cnt].val = niu_node->curr_priority_high; + cam_qos_cnt++; + } niu_node->applied_priority_high = niu_node->curr_priority_high; } if (niu_node->curr_priority_low != niu_node->applied_priority_low) { - cam_io_w_mb(niu_node->curr_priority_low, - soc_info->reg_map[reg_indx].mem_base + - niu_node->pri_lut_low_offset); + if (!soc_private->enable_secure_qos_update) { + cam_io_w_mb(niu_node->curr_priority_low, + soc_info->reg_map[reg_indx].mem_base + + niu_node->pri_lut_low_offset); + } else { + scm_buf[cam_qos_cnt].offset = niu_node->pri_lut_low_offset; + scm_buf[cam_qos_cnt].val = niu_node->curr_priority_low; + cam_qos_cnt++; + } niu_node->applied_priority_low = niu_node->curr_priority_low; } + + if (soc_private->enable_secure_qos_update && cam_qos_cnt) { + CAM_DBG(CAM_PERF, "Updating secure camera smartOos count: %d", cam_qos_cnt); + ret = cam_update_camnoc_qos_settings(CAM_QOS_UPDATE_TYPE_SMART, + cam_qos_cnt, scm_buf); + if (ret) { + CAM_ERR(CAM_PERF, "Secure camera smartOos update failed:%d", ret); + return ret; + } + CAM_DBG(CAM_PERF, "Updated secure camera smartOos"); + cam_qos_cnt = 0; + } } if (cpas_core->smart_qos_dump) { @@ -1055,9 +1080,6 @@ static int cam_cpas_util_set_camnoc_axi_drv_clk_rate(struct cam_hw_soc_info *soc req_drv_low_camnoc_bw = 0, intermediate_drv_low_result = 0; int64_t drv_high_clk_rate = 0, drv_low_clk_rate = 0; int i, rc = 0; - void __iomem *cesta_base = - soc_info->reg_map[cpas_core->regbase_index[CAM_CPAS_REG_CESTA]].mem_base; - uint32_t cesta_vcd_curr_perfol_val; if (!soc_private->enable_cam_clk_drv) { CAM_ERR(CAM_CPAS, "Clk DRV not enabled, can't set clk rates through cesta APIs"); @@ -1160,16 +1182,6 @@ static int cam_cpas_util_set_camnoc_axi_drv_clk_rate(struct cam_hw_soc_info *soc hw_client_idx, rc); return rc; } - - cesta_vcd_curr_perfol_val = cam_io_r_mb(cesta_base + 0x400c); - CAM_DBG(CAM_ISP, "Check camnoc VCD val after set I: 0x%x", - cesta_vcd_curr_perfol_val); - cesta_vcd_curr_perfol_val = cam_io_r_mb(cesta_base + 0x400c); - CAM_DBG(CAM_ISP, "Check camnoc VCD val after set II: 0x%x", - cesta_vcd_curr_perfol_val); - cesta_vcd_curr_perfol_val = cam_io_r_mb(cesta_base + 0x400c); - CAM_DBG(CAM_ISP, "Check camnoc VCD val after set III: 0x%x", - cesta_vcd_curr_perfol_val); } return rc; @@ -1183,9 +1195,6 @@ static int cam_cpas_util_set_camnoc_axi_hlos_clk_rate(struct cam_hw_soc_info *so int64_t hlos_clk_rate = 0; int i, rc = 0; const struct camera_debug_settings *cam_debug = NULL; - void __iomem *cesta_base = - soc_info->reg_map[cpas_core->regbase_index[CAM_CPAS_REG_CESTA]].mem_base; - uint32_t cesta_vcd_curr_perfol_val; for (i = 0; i < CAM_CPAS_MAX_TREE_NODES; i++) { tree_node = soc_private->tree_node[i]; @@ -1229,7 +1238,7 @@ static int cam_cpas_util_set_camnoc_axi_hlos_clk_rate(struct cam_hw_soc_info *so do_div(intermediate_hlos_result, soc_private->camnoc_bus_width); hlos_clk_rate = intermediate_hlos_result; - CAM_INFO(CAM_PERF, "Setting camnoc axi HLOS clk rate[BW Clk] : [%llu %lld]", + CAM_DBG(CAM_PERF, "Setting camnoc axi HLOS clk rate[BW Clk] : [%llu %lld]", req_hlos_camnoc_bw, hlos_clk_rate); /* @@ -1247,19 +1256,8 @@ static int cam_cpas_util_set_camnoc_axi_hlos_clk_rate(struct cam_hw_soc_info *so req_hlos_camnoc_bw, hlos_clk_rate, rc); cpas_core->applied_camnoc_axi_rate.sw_client = hlos_clk_rate; - - cesta_vcd_curr_perfol_val = cam_io_r_mb(cesta_base + 0x400c); - CAM_DBG(CAM_ISP, "Check camnoc VCD val after set I: 0x%x", - cesta_vcd_curr_perfol_val); - cesta_vcd_curr_perfol_val = cam_io_r_mb(cesta_base + 0x400c); - CAM_DBG(CAM_ISP, "Check camnoc VCD val after set II: 0x%x", - cesta_vcd_curr_perfol_val); - cesta_vcd_curr_perfol_val = cam_io_r_mb(cesta_base + 0x400c); - CAM_DBG(CAM_ISP, "Check camnoc VCD val after set III: 0x%x", - cesta_vcd_curr_perfol_val); } - return rc; } @@ -3468,7 +3466,10 @@ static void *cam_cpas_user_dump_state_monitor_array_info( *addr++ = monitor->applied_camnoc_clk.hw_client[2].low, *addr++ = monitor->applied_ahb_level; *addr++ = cpas_core->num_valid_camnoc; - *addr++ = soc_private->smart_qos_info->num_rt_wr_nius; + + if (soc_private->enable_smart_qos) + *addr++ = soc_private->smart_qos_info->num_rt_wr_nius; + *addr++ = num_vcds; *addr++ = cpas_core->num_axi_ports; @@ -3515,14 +3516,16 @@ static void *cam_cpas_user_dump_state_monitor_array_info( } } - for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) { - niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i]; - dst = (uint8_t *)addr; - hdr = (struct cam_common_hw_dump_header *)dst; - scnprintf(hdr->tag, CAM_COMMON_HW_DUMP_TAG_MAX_LEN, "%s:", niu_node->node_name); - addr = (uint64_t *)(dst + sizeof(struct cam_common_hw_dump_header)); - *addr++ = monitor->rt_wr_niu_pri_lut_high[i]; - *addr++ = monitor->rt_wr_niu_pri_lut_low[i]; + if (soc_private->enable_smart_qos) { + for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) { + niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i]; + dst = (uint8_t *)addr; + hdr = (struct cam_common_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_COMMON_HW_DUMP_TAG_MAX_LEN, "%s:", niu_node->node_name); + addr = (uint64_t *)(dst + sizeof(struct cam_common_hw_dump_header)); + *addr++ = monitor->rt_wr_niu_pri_lut_high[i]; + *addr++ = monitor->rt_wr_niu_pri_lut_low[i]; + } } vcd_reg_debug_info = &monitor->vcd_reg_debug_info; @@ -3613,9 +3616,11 @@ static int cam_cpas_dump_state_monitor_array_info( min_len += sizeof(struct cam_common_hw_dump_header); } - for (j = 0; j < soc_private->smart_qos_info->num_rt_wr_nius; j++) - min_len += sizeof(struct cam_common_hw_dump_header) + - CAM_CPAS_DUMP_NUM_WORDS_RT_WR_NIUS * sizeof(uint64_t); + if (soc_private->enable_smart_qos) { + for (j = 0; j < soc_private->smart_qos_info->num_rt_wr_nius; j++) + min_len += sizeof(struct cam_common_hw_dump_header) + + CAM_CPAS_DUMP_NUM_WORDS_RT_WR_NIUS * sizeof(uint64_t); + } for (j = 0; j < CAM_CPAS_MAX_CESTA_VCD_NUM; j++) min_len += CAM_CPAS_DUMP_NUM_WORDS_VCD_CURR_LVL * sizeof(uint64_t); @@ -3694,6 +3699,32 @@ done: return rc; } +static int cam_cpas_hw_enable_tpg_mux_sel(struct cam_hw_info *cpas_hw, + uint32_t tpg_mux) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + int rc = 0; + + mutex_lock(&cpas_hw->hw_mutex); + + if (cpas_core->internal_ops.set_tpg_mux_sel) { + rc = cpas_core->internal_ops.set_tpg_mux_sel( + cpas_hw, tpg_mux); + if (rc) { + CAM_ERR(CAM_CPAS, + "failed in tpg mux selection rc=%d", + rc); + } + } else { + CAM_ERR(CAM_CPAS, + "CPAS tpg mux sel not enabled"); + rc = -EINVAL; + } + + mutex_unlock(&cpas_hw->hw_mutex); + return rc; +} + static int cam_cpas_activate_cache( struct cam_hw_info *cpas_hw, struct cam_sys_cache_info *cache_info) @@ -4011,10 +4042,6 @@ static int cam_cpas_hw_csid_input_core_info_update(struct cam_hw_info *cpas_hw, rc = cam_common_util_get_string_index(soc_private->client_name, soc_private->num_clients, client_name, &client_indx); - if (rc || (client_indx < 0)) { - CAM_ERR(CAM_CPAS, "Failed in getting correct client index"); - return -EINVAL; - } if (!cpas_core->cpas_client[client_indx]->is_drv_dyn) return 0; @@ -4367,6 +4394,20 @@ static int cam_cpas_hw_process_cmd(void *hw_priv, rc = cam_cpas_hw_csid_process_resume(hw_priv, *csid_idx); break; } + case CAM_CPAS_HW_CMD_TPG_MUX_SEL: { + uint32_t *tpg_mux_sel; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + tpg_mux_sel = (uint32_t *)cmd_args; + rc = cam_cpas_hw_enable_tpg_mux_sel(hw_priv, *tpg_mux_sel); + break; + + } case CAM_CPAS_HW_CMD_ENABLE_DISABLE_DOMAIN_ID_CLK: { bool *enable; @@ -4670,7 +4711,7 @@ int cam_cpas_hw_probe(struct platform_device *pdev, cpas_hw_intf->hw_ops.process_cmd = cam_cpas_hw_process_cmd; cpas_core->work_queue = alloc_workqueue(CAM_CPAS_WORKQUEUE_NAME, - WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI, CAM_CPAS_INFLIGHT_WORKS); + WQ_UNBOUND | WQ_MEM_RECLAIM, CAM_CPAS_INFLIGHT_WORKS); if (!cpas_core->work_queue) { rc = -ENOMEM; goto release_mem; diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.h index 82a320e1a8..b6be733892 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.h @@ -170,6 +170,7 @@ struct cam_cpas_kobj_map { * @print_poweron_settings: Function pointer for hw to print poweron settings * @qchannel_handshake: Function pointer for hw core specific qchannel * handshake settings + * @set_tpg_mux_sel: Set tpg mux select on CPAS TOP register * */ struct cam_cpas_internal_ops { @@ -186,6 +187,7 @@ struct cam_cpas_internal_ops { uint32_t selection_mask); int (*print_poweron_settings)(struct cam_hw_info *cpas_hw); int (*qchannel_handshake)(struct cam_hw_info *cpas_hw, bool power_on, bool force_on); + int (*set_tpg_mux_sel)(struct cam_hw_info *cpas_hw, uint32_t tpg_num); }; /** @@ -458,4 +460,7 @@ int cam_cpas_util_reg_read(struct cam_hw_info *cpas_hw, int cam_cpas_util_client_cleanup(struct cam_hw_info *cpas_hw); +int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw, + int enable); + #endif /* _CAM_CPAS_HW_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw_intf.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw_intf.h index 2d40a5601e..d8468b75dd 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw_intf.h @@ -72,6 +72,7 @@ enum cam_cpas_hw_cmd_process { CAM_CPAS_HW_CMD_CSID_INPUT_CORE_INFO_UPDATE, CAM_CPAS_HW_CMD_CSID_PROCESS_RESUME, CAM_CPAS_HW_CMD_ENABLE_DISABLE_DOMAIN_ID_CLK, + CAM_CPAS_HW_CMD_TPG_MUX_SEL, CAM_CPAS_HW_CMD_DUMP_STATE_MONITOR_INFO, CAM_CPAS_HW_CMD_INVALID, }; @@ -201,4 +202,10 @@ int cam_cpas_dev_init_module(void); * @brief : API to remove CPAS interface from platform framework. */ void cam_cpas_dev_exit_module(void); + +/** + * @brief : API to select TPG mux select. + */ +int cam_cpas_enable_tpg_mux_sel(uint32_t tpg_mux_sel); + #endif /* _CAM_CPAS_HW_INTF_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_intf.c b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_intf.c index 428594f069..f76f399418 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_intf.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_intf.c @@ -22,10 +22,18 @@ #include "cam_cpas_soc.h" #include "cam_cpastop_hw.h" #include "camera_main.h" +#include "cam_cpas_hw.h" #include #include "cam_req_mgr_interface.h" +#ifdef CONFIG_DYNAMIC_FD_PORT_CONFIG +#include +#include +#include +#define CAM_CPAS_ERROR_NOT_ALLOWED 10 +#endif + #define CAM_CPAS_DEV_NAME "cam-cpas" #define CAM_CPAS_INTF_INITIALIZED() (g_cpas_intf && g_cpas_intf->probe_done) @@ -767,6 +775,31 @@ int cam_cpas_select_qos_settings(uint32_t selection_mask) } EXPORT_SYMBOL(cam_cpas_select_qos_settings); +int cam_cpas_enable_tpg_mux_sel(uint32_t tpg_mux_sel) +{ + int rc = 0; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -EBADR; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_TPG_MUX_SEL, &tpg_mux_sel, + sizeof(tpg_mux_sel)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + rc = -EBADR; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_enable_tpg_mux_sel); + int cam_cpas_notify_event(const char *identifier_string, int32_t identifier_value) { @@ -1116,6 +1149,154 @@ int cam_cpas_dump_state_monitor_info(struct cam_req_mgr_dump_info *info) } EXPORT_SYMBOL(cam_cpas_dump_state_monitor_info); +#ifdef CONFIG_DYNAMIC_FD_PORT_CONFIG +static int cam_cpas_handle_fd_port_config(uint32_t is_secure) +{ + int rc = 0; + struct Object client_env, sc_object; + struct cam_hw_info *cpas_hw = NULL; + struct cam_cpas *cpas_core; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -EINVAL; + } + + cpas_hw = (struct cam_hw_info *) g_cpas_intf->hw_intf->hw_priv; + if (cpas_hw) { + cpas_core = (struct cam_cpas *) cpas_hw->core_info; + mutex_lock(&cpas_hw->hw_mutex); + if (cpas_core->streamon_clients > 0) { + CAM_ERR(CAM_CPAS, + "FD port config can not be updated during the session"); + mutex_unlock(&cpas_hw->hw_mutex); + return -EINVAL; + } + } else { + CAM_ERR(CAM_CPAS, "cpas_hw handle not initialized"); + return -EINVAL; + } + + /* Need to vote first before enabling clocks */ + rc = cam_cpas_util_vote_default_ahb_axi(cpas_hw, true); + if (rc) { + CAM_ERR(CAM_CPAS, + "failed to vote for the default ahb/axi clock, rc=%d", rc); + goto release_mutex; + } + + rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info, + cpas_hw->soc_info.lowest_clk_level); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in soc_enable_resources, rc=%d", rc); + goto remove_default_vote; + } + + rc = get_client_env_object(&client_env); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed getting mink env object, rc: %d", rc); + goto disable_resources; + } + + rc = IClientEnv_open(client_env, CTrustedCameraDriver_UID, &sc_object); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed getting mink sc_object, rc: %d", rc); + goto client_release; + } + + rc = ITrustedCameraDriver_dynamicConfigureFDPort(sc_object, is_secure); + if (rc) { + if (rc == CAM_CPAS_ERROR_NOT_ALLOWED) { + CAM_ERR(CAM_CPAS, "Dynamic FD port config not allowed"); + rc = -EPERM; + } else { + CAM_ERR(CAM_CPAS, "Mink secure call failed, rc: %d", rc); + rc = -EINVAL; + } + goto obj_release; + } + + rc = Object_release(sc_object); + if (rc) { + CAM_ERR(CAM_CSIPHY, "Failed releasing secure camera object, rc: %d", rc); + goto client_release; + } + + rc = Object_release(client_env); + if (rc) { + CAM_ERR(CAM_CSIPHY, "Failed releasing mink env object, rc: %d", rc); + goto disable_resources; + } + + rc = cam_cpas_soc_disable_resources(&cpas_hw->soc_info, true, true); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in soc_disable_resources, rc=%d", rc); + goto remove_default_vote; + } + + rc = cam_cpas_util_vote_default_ahb_axi(cpas_hw, false); + if (rc) + CAM_ERR(CAM_CPAS, + "failed remove the vote on ahb/axi clock, rc=%d", rc); + + mutex_unlock(&cpas_hw->hw_mutex); + return rc; + +obj_release: + Object_release(sc_object); +client_release: + Object_release(client_env); +disable_resources: + cam_cpas_soc_disable_resources(&cpas_hw->soc_info, true, true); +remove_default_vote: + cam_cpas_util_vote_default_ahb_axi(cpas_hw, false); +release_mutex: + mutex_unlock(&cpas_hw->hw_mutex); + return rc; +} +#endif + +static int cam_cpas_handle_custom_config_cmd(struct cam_cpas_intf *cpas_intf, + struct cam_custom_cmd *cmd) +{ + int32_t rc = 0; + + if (!cmd) { + CAM_ERR(CAM_CPAS, "Invalid input cmd"); + return -EINVAL; + } + + switch (cmd->cmd_type) { +#ifdef CONFIG_DYNAMIC_FD_PORT_CONFIG + case CAM_CPAS_CUSTOM_CMD_FD_PORT_CFG: { + struct cam_cpas_fd_port_config cfg; + + if (cmd->size < sizeof(cfg)) + return -EINVAL; + + rc = copy_from_user(&cfg, u64_to_user_ptr(cmd->handle), + sizeof(cfg)); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed in copy from user, rc=%d", + rc); + rc = -EINVAL; + break; + } + + rc = cam_cpas_handle_fd_port_config(cfg.is_secure); + break; + } +#endif + default: + CAM_ERR(CAM_CPAS, "Invalid custom command %d for CPAS", cmd->cmd_type); + rc = -EINVAL; + break; + + } + + return rc; +} + int cam_cpas_subdev_cmd(struct cam_cpas_intf *cpas_intf, struct cam_control *cmd) { @@ -1208,6 +1389,19 @@ int cam_cpas_subdev_cmd(struct cam_cpas_intf *cpas_intf, break; } + case CAM_CUSTOM_DEV_CONFIG: { + struct cam_custom_cmd custom_cmd; + + rc = copy_from_user(&custom_cmd, u64_to_user_ptr(cmd->handle), + sizeof(custom_cmd)); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed in copy from user, rc=%d", + rc); + break; + } + rc = cam_cpas_handle_custom_config_cmd(cpas_intf, &custom_cmd); + break; + } case CAM_SD_SHUTDOWN: break; default: diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.c b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.c index 23fd1b527b..97061e76f8 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1455,6 +1455,9 @@ int cam_cpas_get_custom_dt_info(struct cam_hw_info *cpas_hw, soc_private->num_vdd_ahb_mapping = count; } + soc_private->enable_secure_qos_update = of_property_read_bool(of_node, + "enable-secure-qos-update"); + soc_private->enable_smart_qos = of_property_read_bool(of_node, "enable-smart-qos"); diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.h index c6f1d8b420..0e39a62dad 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_soc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CPAS_SOC_H_ @@ -268,6 +268,7 @@ struct cam_cpas_sysfs_info { * @num_caches: Number of last level caches * @part_info: Camera Hw subpart info * @llcc_info: Cache info + * @enable_secure_qos_update: whether to program QoS securely on current chipset * @enable_smart_qos: Whether to enable Smart QoS mechanism on current chipset * @enable_cam_ddr_drv: Whether to enable Camera DDR DRV on current chipset * @enable_cam_clk_drv: Whether to enable Camera Clk DRV on current chipset @@ -303,6 +304,7 @@ struct cam_cpas_private_soc { bool enable_smart_qos; bool enable_cam_ddr_drv; bool enable_cam_clk_drv; + bool enable_secure_qos_update; struct cam_cpas_smart_qos_info *smart_qos_info; int32_t icp_clk_index; struct cam_cpas_domain_id_info domain_id_info; diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/camss_top/cam_camsstop_hw.c b/qcom/opensource/camera-kernel/drivers/cam_cpas/camss_top/cam_camsstop_hw.c index d8552c56d1..233de3bdac 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/camss_top/cam_camsstop_hw.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/camss_top/cam_camsstop_hw.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_cpas_hw_intf.h" @@ -80,6 +81,7 @@ int cam_camsstop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops) internal_ops->setup_qos_settings = NULL; internal_ops->print_poweron_settings = NULL; internal_ops->qchannel_handshake = NULL; + internal_ops->set_tpg_mux_sel = NULL; return 0; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index 5c933b66d4..8b3d0b46b9 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -36,13 +36,19 @@ #include "cpastop_v165_100.h" #include "cpastop_v780_100.h" #include "cpastop_v640_200.h" +#include "cpastop_v640_210.h" #include "cpastop_v880_100.h" #include "cpastop_v980_100.h" +#include "cpastop_v860_100.h" +#include "cpastop_v770_100.h" +#include "cpastop_v665_100.h" #include "cam_req_mgr_workq.h" #include "cam_common_util.h" struct cam_camnoc_info *camnoc_info[CAM_CAMNOC_HW_TYPE_MAX]; struct cam_cpas_info *cpas_info; +struct cam_cpas_camnoc_qchannel *qchannel_info; +struct cam_cpas_top_regs *cpas_top_info; #if (defined(CONFIG_CAM_TEST_IRQ_LINE) && defined(CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE)) struct completion test_irq_hw_complete[CAM_CAMNOC_HW_TYPE_MAX]; @@ -70,6 +76,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_170 */ { @@ -79,6 +86,7 @@ static const uint32_t cam_cpas_hw_version_map CAM_CPAS_TITAN_170_V120, 0, CAM_CPAS_TITAN_170_V200, + 0, }, /* for camera_175 */ { @@ -88,6 +96,7 @@ static const uint32_t cam_cpas_hw_version_map CAM_CPAS_TITAN_175_V120, CAM_CPAS_TITAN_175_V130, 0, + 0, }, /* for camera_480 */ { @@ -97,6 +106,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_580 */ { @@ -106,6 +116,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_520 */ { @@ -115,6 +126,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_540 */ @@ -125,6 +137,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_545 */ { @@ -134,6 +147,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_570 */ { @@ -143,6 +157,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, CAM_CPAS_TITAN_570_V200, + 0, }, /* for camera_680 */ { @@ -152,6 +167,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_165 */ { @@ -161,6 +177,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_780 */ { @@ -170,6 +187,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_640 */ { @@ -179,6 +197,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, CAM_CPAS_TITAN_640_V200, + CAM_CPAS_TITAN_640_V210, }, /* for camera_880 */ { @@ -188,6 +207,7 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, }, /* for camera_980 */ { @@ -197,6 +217,37 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, 0, + 0, + }, + /* for camera_860 */ + { + CAM_CPAS_TITAN_860_V100, + 0, + 0, + 0, + 0, + 0, + 0, + }, + /* for camera_770 */ + { + CAM_CPAS_TITAN_770_V100, + 0, + 0, + 0, + 0, + 0, + 0, + }, + /* for camera_665 */ + { + CAM_CPAS_TITAN_665_V100, + 0, + 0, + 0, + 0, + 0, + 0, }, }; @@ -279,6 +330,15 @@ static int cam_cpas_translate_camera_cpas_version_id( case CAM_CPAS_CAMERA_VERSION_980: *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_980; break; + case CAM_CPAS_CAMERA_VERSION_860: + *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_860; + break; + case CAM_CPAS_CAMERA_VERSION_770: + *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_770; + break; + case CAM_CPAS_CAMERA_VERSION_665: + *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_665; + break; default: CAM_ERR(CAM_CPAS, "Invalid cam version %u", cam_version); @@ -310,6 +370,10 @@ static int cam_cpas_translate_camera_cpas_version_id( *cpas_version_id = CAM_CPAS_VERSION_ID_200; break; + case CAM_CPAS_VERSION_210: + *cpas_version_id = CAM_CPAS_VERSION_ID_210; + break; + default: CAM_ERR(CAM_CPAS, "Invalid cpas version %u", cpas_version); @@ -976,59 +1040,72 @@ static int cam_cpastop_print_poweron_settings(struct cam_hw_info *cpas_hw) static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) { - int i, j; + int i, j, rc = 0; struct cam_cpas_hw_errata_wa_list *errata_wa_list; struct cam_cpas_hw_errata_wa *errata_wa; struct cam_cpas *cpas_core = cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; bool errata_enabled = false; for (i = 0; i < cpas_core->num_valid_camnoc; i++) cam_cpastop_reset_irq(0x0, cpas_hw, i); - for (i = 0; i < cpas_core->num_valid_camnoc; i++) { - CAM_DBG(CAM_CPAS, "QOS settings for %s :", - camnoc_info[i]->camnoc_name); - for (j = 0; j < camnoc_info[i]->specific_size; j++) { - if (camnoc_info[i]->specific[j].enable) { - CAM_DBG(CAM_CPAS, - "Updating QoS settings port: %d prot name: %s", - camnoc_info[i]->specific[j].port_type, - camnoc_info[i]->specific[j].port_name); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].priority_lut_low); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].priority_lut_high); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].urgency); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].danger_lut); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].safe_lut); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].ubwc_ctl); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].flag_out_set0_low); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].dynattr_mainctl); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].qosgen_mainctl); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].qosgen_shaping_low); - cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, - &camnoc_info[i]->specific[j].qosgen_shaping_high); - } - } + if (!soc_private->enable_secure_qos_update) { + for (i = 0; i < cpas_core->num_valid_camnoc; i++) { + CAM_DBG(CAM_CPAS, "QOS settings for %s :", + camnoc_info[i]->camnoc_name); + for (j = 0; j < camnoc_info[i]->specific_size; j++) { + if (camnoc_info[i]->specific[j].enable) { + CAM_DBG(CAM_CPAS, + "Updating QoS settings port: %d prot name: %s", + camnoc_info[i]->specific[j].port_type, + camnoc_info[i]->specific[j].port_name); - if (!errata_enabled) { - errata_wa_list = camnoc_info[i]->errata_wa_list; - if (errata_wa_list) { - errata_wa = &errata_wa_list->tcsr_camera_hf_sf_ares_glitch; - if (errata_wa->enable) { - cam_cpastop_scm_write(errata_wa); - errata_enabled = true; + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].priority_lut_low); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].priority_lut_high); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].urgency); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].danger_lut); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].safe_lut); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].ubwc_ctl); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].flag_out_set0_low); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].dynattr_mainctl); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].qosgen_mainctl); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].qosgen_shaping_low); + cam_cpas_util_reg_update(cpas_hw, camnoc_info[i]->reg_base, + &camnoc_info[i]->specific[j].qosgen_shaping_high); + } + } + + if (!errata_enabled) { + errata_wa_list = camnoc_info[i]->errata_wa_list; + if (errata_wa_list) { + errata_wa = &errata_wa_list->tcsr_camera_hf_sf_ares_glitch; + if (errata_wa->enable) { + cam_cpastop_scm_write(errata_wa); + errata_enabled = true; + } } } } + } else { + CAM_DBG(CAM_CPAS, "Updating secure camera static QoS settings"); + rc = cam_update_camnoc_qos_settings(CAM_QOS_UPDATE_TYPE_STATIC, 0, NULL); + if (rc) { + CAM_ERR(CAM_CPAS, "Secure camera static OoS update failed: %d", rc); + return rc; + } + CAM_DBG(CAM_CPAS, "Updated secure camera static QoS settings"); } return 0; @@ -1277,6 +1354,33 @@ static int cam_cpastop_get_hw_capability(struct cam_hw_info *cpas_hw) return 0; } +static int cam_cpastop_set_tpg_mux_sel(struct cam_hw_info *cpas_hw, + uint32_t tpg_mux) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + int reg_cpas_top; + uint32_t curr_tpg_mux = 0; + + reg_cpas_top = cpas_core->regbase_index[CAM_CPAS_REG_CPASTOP]; + + if (cpas_top_info == NULL) + return 0; + + if (!cpas_top_info->tpg_mux_sel_enabled) + return 0; + + curr_tpg_mux = cam_io_r_mb(soc_info->reg_map[reg_cpas_top].mem_base + + cpas_top_info->tpg_mux_sel); + + curr_tpg_mux = curr_tpg_mux | ((1 << tpg_mux) << cpas_top_info->tpg_mux_sel_shift); + cam_io_w_mb(curr_tpg_mux, soc_info->reg_map[reg_cpas_top].mem_base + + cpas_top_info->tpg_mux_sel); + CAM_DBG(CAM_CPAS, "SET TPG MUX to 0x%x", curr_tpg_mux); + + return 0; +} + static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, struct cam_cpas_hw_caps *hw_caps) { @@ -1286,6 +1390,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, struct cam_cpas_cesta_info *cesta_info = NULL; struct cam_camnoc_info *alloc_camnoc_info[CAM_CAMNOC_HW_TYPE_MAX] = {0}; + qchannel_info = NULL; + cpas_top_info = NULL; + CAM_DBG(CAM_CPAS, "hw_version=0x%x Camera Version %d.%d.%d, cpas version %d.%d.%d", soc_info->hw_version, @@ -1376,6 +1483,12 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, case CAM_CPAS_TITAN_640_V200: alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam640_cpas200_camnoc_info; cpas_info = &cam640_cpas200_cpas_info; + cpas_top_info = &cam640_cpas200_cpas_top_info; + break; + case CAM_CPAS_TITAN_640_V210: + alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam640_cpas210_camnoc_info; + cpas_info = &cam640_cpas210_cpas_info; + cpas_top_info = &cam640_cpas210_cpas_top_info; break; case CAM_CPAS_TITAN_880_V100: alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam880_cpas100_camnoc_info; @@ -1388,6 +1501,21 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, cpas_info = &cam980_cpas100_cpas_info; cesta_info = &cam_v980_cesta_info; break; + case CAM_CPAS_TITAN_860_V100: + alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam860_cpas100_camnoc_info; + cpas_info = &cam860_cpas100_cpas_info; + cesta_info = &cam_v860_cesta_info; + break; + case CAM_CPAS_TITAN_770_V100: + alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam770_cpas100_camnoc_info; + cpas_info = &cam770_cpas100_cpas_info; + cpas_top_info = &cam770_cpas100_cpas_top_info; + break; + case CAM_CPAS_TITAN_665_V100: + alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam665_cpas100_camnoc_info; + cpas_info = &cam665_cpas100_cpas_info; + cpas_top_info = &cam665_cpas100_cpas_top_info; + break; default: CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d", hw_caps->camera_version.major, @@ -1471,6 +1599,7 @@ int cam_cpastop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops) internal_ops->print_poweron_settings = cam_cpastop_print_poweron_settings; internal_ops->qchannel_handshake = cam_cpastop_qchannel_handshake; + internal_ops->set_tpg_mux_sel = cam_cpastop_set_tpg_mux_sel; return 0; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h index 27f47ecd01..c0be049adf 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -534,4 +534,17 @@ struct cam_cpas_info { uint8_t num_qchannel; }; +/** + * struct cam_cpas_top_regs : CPAS Top registers + * @tpg_mux_sel_shift: TPG mux select shift value + * @tpg_mux_sel: For selecting TPG + * @tpg_mux_sel_enabled: TPG mux select enabled or not + * + */ +struct cam_cpas_top_regs { + uint32_t tpg_mux_sel_shift; + uint32_t tpg_mux_sel; + bool tpg_mux_sel_enabled; +}; + #endif /* _CAM_CPASTOP_HW_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_200.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_200.h index 8bf5dcc290..8288b0bd8c 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_200.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_200.h @@ -547,6 +547,9 @@ static struct cam_camnoc_err_logger_info cam640_cpas200_err_logger_offsets = { }; static struct cam_cpas_hw_errata_wa_list cam640_cpas200_errata_wa_list = { + .enable_icp_clk_for_qchannel = { + .enable = true, + }, }; static struct cam_camnoc_info cam640_cpas200_camnoc_info = { @@ -573,5 +576,11 @@ static struct cam_cpas_info cam640_cpas200_cpas_info = { .num_qchannel = 1, }; +static struct cam_cpas_top_regs cam640_cpas200_cpas_top_info = { + .tpg_mux_sel_enabled = true, + .tpg_mux_sel_shift = 0x0, + .tpg_mux_sel = 0x1C, +}; + #endif /* _CPASTOP_V640_200_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_210.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_210.h new file mode 100644 index 0000000000..6c6772b3a8 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_210.h @@ -0,0 +1,583 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CPASTOP_V640_210_H_ +#define _CPASTOP_V640_210_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v640_210_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6840, /* CAM_NOC_SBM_FAULTINEN0_LOW */ + .value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6848, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x6880, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x5 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v640_210_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = false, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6608, /* CAM_NOC_ERL_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6610, /* CAM_NOC_ERL_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x6618, /* CAM_NOC_ERL_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5DA0, /* WR_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5D90, /* WR_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5D98, /* WR_NIU_ENCERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5F20, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */ + .value = 0xFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5F10, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5F18, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = false, + .sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6888, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6890, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v640_210_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_TFE_BAYER_STATS, + .port_name = "TFE_BAYER", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5830, /*PRIORITYLUT_LOW */ + .value = 0x55554433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5834, /* PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5838, /* URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5840, /* DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5848, /* SAFELUT_LOW */ + .value = 0x0000000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4208, /* QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4220, /* QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4224, /* QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x5820, /* UBWC_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_RAW, + .port_name = "TFE_RDI_RAW", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A30, /* PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A34, /* PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A38, /* URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A40, /* DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A48, /* SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4408, /* QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4420, /* QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4424, /* QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x5A20, /* STATS_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_WR, + .port_name = "OPE_BPS_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C30, /* PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C34, /* PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C38, /* URGENCY_LOW */ + .value = 0x00000030, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C40, /* DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C48, /* SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4608, /* QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4620, /* QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4624, /* QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x5C20, /* MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_CDM_RD, + .port_name = "OPE_BPS_CDM_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E30, /* IPE_WR_PRIORITYLUT_LOW */ + .value = 0x55554433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E34, /* IPE_WR_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E38, /* IPE_WR_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E40, /* IPE_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E48, /* IPE_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4808, /* IPE_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4820, /* IPE_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4824, /* IPE_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_CRE, + .port_name = "CRE_RD_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6030, /* BPS_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6034, /* BPS_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6038, /* BPS_WR_URGENCY_LOW */ + .value = 0x03, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6040, /* BPS_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6048, /* BPS_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4A08, /* BPS_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4A20, /* BPS_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4A24, /* BPS_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x6020, /* BPS_WR_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_ICP, + .port_name = "ICP", + .enable = false, + .flag_out_set0_low = { + .enable = false, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x6888, + .value = 0x100000, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4008, /* ICP_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4020, /* ICP_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4024, /* ICP_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam640_cpas210_err_logger_offsets = { + .mainctrl = 0x6608, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x6610, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x6620, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x6624, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x6628, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x662c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x6630, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x6634, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x6638, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x663c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam640_cpas210_errata_wa_list = { +}; + +static struct cam_camnoc_info cam640_cpas210_camnoc_info = { + .specific = &cam_cpas_v640_210_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v640_210_camnoc_specific), + .irq_sbm = &cam_cpas_v640_210_irq_sbm, + .irq_err = &cam_cpas_v640_210_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v640_210_irq_err), + .err_logger = &cam640_cpas210_err_logger_offsets, + .errata_wa_list = &cam640_cpas210_errata_wa_list, +}; + +static struct cam_cpas_camnoc_qchannel cam640_cpas210_qchannel_info = { + .qchannel_ctrl = 0x14, + .qchannel_status = 0x18, +}; + +static struct cam_cpas_info cam640_cpas210_cpas_info = { + .hw_caps_info = { + .num_caps_registers = 1, + .hw_caps_offsets = {0x8}, + }, + .qchannel_info = {&cam640_cpas210_qchannel_info}, + .num_qchannel = 1, +}; + +static struct cam_cpas_top_regs cam640_cpas210_cpas_top_info = { + .tpg_mux_sel_enabled = true, + .tpg_mux_sel_shift = 0x0, + .tpg_mux_sel = 0x1C, +}; + +#endif /* _CPASTOP_V640_210_H_ */ + diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v665_100.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v665_100.h new file mode 100644 index 0000000000..3d46ef982c --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v665_100.h @@ -0,0 +1,649 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CPASTOP_V665_100_H_ +#define _CPASTOP_V665_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v665_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */ + .value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x5 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v665_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = false, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8, /* CAM_NOC_ERL_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x10, /* CAM_NOC_ERL_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x18, /* CAM_NOC_ERL_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x89A0, /* WR_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8990, /* WR_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8998, /* WR_NIU_ENCERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8720, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */ + .value = 0xFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8710, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8718, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = false, + .sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v665_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_TFE_BAYER_STATS, + .port_name = "TFE_BAYER", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A30, /* TFE_BAYER_NIU_PRIORITYLUT_LOW */ + .value = 0x55554433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A34, /* TFE_BAYER_NIU_PRIORITYLUT_HIGH */ + .value = 0x66555555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A38, /* TFE_BAYER_NIU_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A40, /* TFE_BAYER_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A48, /* TFE_BAYER_NIU_SAFELUT_LOW */ + .value = 0x0000000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9008, /* TFE_BAYER_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9020, /* TFE_BAYER_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9024, /* TFE_BAYER_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8A20, /* TFE_BAYER_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_RAW, + .port_name = "TFE_RDI_RAW", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C30, /* TFE_RDI_NIU_PRIORITYLUT_LOW */ + .value = 0x55554433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C34, /* TFE_RDI_NIU_PRIORITYLUT_HIGH */ + .value = 0x66555555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C38, /* TFE_RDI_RAW_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C40, /* TFE_RDI_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C48, /* TFE_RDI_NIU_SAFELUT_LOW */ + .value = 0x0000000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9088, /* TFE_RDI_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x90A0, /* TFE_RDI_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x90A4, /* TFE_RDI_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8C20, /* TFE_RDI_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_WR, + .port_name = "OPE_BPS_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8830, /* OFFLINE_WR_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8834, /* OFFLINE_WR_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8838, /* OFFLINE_WR_NIU_URGENCY_LOW */ + .value = 0x030, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8840, /* OFFLINE_WR_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8848, /* OFFLINE_WR_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F88, /* OFFLINE_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8FA0, /* OFFLINE_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8FA4, /* OFFLINE_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8820, /* OFFLINE_WR_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_CDM_RD, + .port_name = "OPE_BPS_CDM_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8630, /* OFFLINE_RD_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8634, /* OFFLINE_RD_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8638, /* OFFLINE_RD_NIU_URGENCY_LOW */ + .value = 0x003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8640, /* OFFLINE_RD_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8648, /* OFFLINE_RD_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F08, /* OFFLINE_RD_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F20, /* OFFLINE_RD_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F24, /* OFFLINE_RD_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_CRE, + .port_name = "CRE_RD_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8230, /* CRE_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8234, /* CRE_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8238, /* CRE_NIU_URGENCY_LOW */ + .value = 0x033, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8240, /* CRE_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8248, /* CRE_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E88, /* CRE_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8EA0, /* CRE_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8EA4, /* CRE_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8220, /* CRE_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_CDM, + .port_name = "CDM", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8030, /* CDM_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8034, /* CDM_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8038, /* CDM_NIU_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8040, /* CDM_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8048, /* CDM_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E08, /* CDM_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E20, /* CDM_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E24, /* CDM_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_ICP, + .port_name = "ICP", + .enable = false, + .flag_out_set0_low = { + .enable = false, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x288, + .value = 0x100000, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9108, /* ICP_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9120, /* ICP_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9124, /* ICP_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam665_cpas100_err_logger_offsets = { + .mainctrl = 0x8, /* ERL_MAINCTL_LOW */ + .errvld = 0x10, /* ERl_ERRVLD_LOW */ + .errlog0_low = 0x20, /* ERL_ERRLOG0_LOW */ + .errlog0_high = 0x24, /* ERL_ERRLOG0_HIGH */ + .errlog1_low = 0x28, /* ERL_ERRLOG1_LOW */ + .errlog1_high = 0x2C, /* ERL_ERRLOG1_HIGH */ + .errlog2_low = 0x30, /* ERL_ERRLOG2_LOW */ + .errlog2_high = 0x34, /* ERL_ERRLOG2_HIGH */ + .errlog3_low = 0x38, /* ERL_ERRLOG3_LOW */ + .errlog3_high = 0x3C, /* ERL_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam665_cpas100_errata_wa_list = { + .enable_icp_clk_for_qchannel = { + .enable = true, + }, +}; + +static struct cam_camnoc_info cam665_cpas100_camnoc_info = { + .specific = &cam_cpas_v665_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v665_100_camnoc_specific), + .irq_sbm = &cam_cpas_v665_100_irq_sbm, + .irq_err = &cam_cpas_v665_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v665_100_irq_err), + .err_logger = &cam665_cpas100_err_logger_offsets, + .errata_wa_list = &cam665_cpas100_errata_wa_list, +}; + +static struct cam_cpas_camnoc_qchannel cam665_cpas100_qchannel_info = { + .qchannel_ctrl = 0x14, + .qchannel_status = 0x18, +}; + +static struct cam_cpas_info cam665_cpas100_cpas_info = { + .hw_caps_info = { + .num_caps_registers = 1, + .hw_caps_offsets = {0x8}, + }, + .qchannel_info = {&cam665_cpas100_qchannel_info}, + .num_qchannel = 1, +}; + +static struct cam_cpas_top_regs cam665_cpas100_cpas_top_info = { + .tpg_mux_sel_enabled = true, + .tpg_mux_sel_shift = 0x0, + .tpg_mux_sel = 0x1C, +}; + +#endif /* _CPASTOP_V665_100_H_ */ + diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v770_100.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v770_100.h new file mode 100644 index 0000000000..93832c94e4 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v770_100.h @@ -0,0 +1,692 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CPASTOP_V770_100_H_ +#define _CPASTOP_V770_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v770_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */ + .value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x5 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v770_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = false, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8, /* CAM_NOC_ERL_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x10, /* CAM_NOC_ERL_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x18, /* CAM_NOC_ERL_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x89A0, /* WR_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8990, /* WR_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8998, /* WR_NIU_ENCERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8720, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */ + .value = 0xFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8710, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8718, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = false, + .sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v770_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_TFE_BAYER_STATS, + .port_name = "TFE_BAYER", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A30, /* TFE_BAYER_NIU_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A34, /* TFE_BAYER_NIU_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A38, /* TFE_BAYER_NIU_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A40, /* TFE_BAYER_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A48, /* TFE_BAYER_NIU_SAFELUT_LOW */ + .value = 0x0000000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9008, /* TFE_BAYER_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9020, /* TFE_BAYER_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9024, /* TFE_BAYER_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8A20, /* TFE_BAYER_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_RAW, + .port_name = "TFE_RDI_RAW", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C30, /* TFE_RDI_NIU_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C34, /* TFE_RDI_NIU_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C38, /* TFE_RDI_RAW_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C40, /* TFE_RDI_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C48, /* TFE_RDI_NIU_SAFELUT_LOW */ + .value = 0x0000000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9088, /* TFE_RDI_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x90A0, /* TFE_RDI_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x90A4, /* TFE_RDI_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8C20, /* TFE_RDI_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_WR, + .port_name = "OPE_BPS_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8830, /* OFFLINE_WR_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8834, /* OFFLINE_WR_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8838, /* OFFLINE_WR_NIU_URGENCY_LOW */ + .value = 0x030, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8840, /* OFFLINE_WR_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8848, /* OFFLINE_WR_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F88, /* OFFLINE_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8FA0, /* OFFLINE_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8FA4, /* OFFLINE_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8820, /* OFFLINE_WR_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_CDM_RD, + .port_name = "OPE_BPS_CDM_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8630, /* OFFLINE_RD_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8634, /* OFFLINE_RD_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8638, /* OFFLINE_RD_NIU_URGENCY_LOW */ + .value = 0x003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8640, /* OFFLINE_RD_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8648, /* OFFLINE_RD_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F08, /* OFFLINE_RD_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F20, /* OFFLINE_RD_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8F24, /* OFFLINE_RD_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_CRE, + .port_name = "CRE_RD_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8230, /* CRE_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8234, /* CRE_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8238, /* CRE_NIU_URGENCY_LOW */ + .value = 0x033, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8240, /* CRE_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8248, /* CRE_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E88, /* CRE_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8EA0, /* CRE_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8EA4, /* CRE_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8220, /* CRE_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .port_name = "JPEG", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8430, /* JPEG_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8434, /* JPEG_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8438, /* JPEG_NIU_URGENCY_LOW */ + .value = 0x33, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8440, /* JPEG_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8448, /* JPEG_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_CDM, + .port_name = "CDM", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8030, /* CDM_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8034, /* CDM_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8038, /* CDM_NIU_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8040, /* CDM_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8048, /* CDM_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E08, /* CDM_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E20, /* CDM_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E24, /* CDM_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_ICP, + .port_name = "ICP", + .enable = false, + .flag_out_set0_low = { + .enable = false, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x288, + .value = 0x100000, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9108, /* ICP_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9120, /* ICP_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9124, /* ICP_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam770_cpas100_err_logger_offsets = { + .mainctrl = 0x8, /* ERL_MAINCTL_LOW */ + .errvld = 0x10, /* ERl_ERRVLD_LOW */ + .errlog0_low = 0x20, /* ERL_ERRLOG0_LOW */ + .errlog0_high = 0x24, /* ERL_ERRLOG0_HIGH */ + .errlog1_low = 0x28, /* ERL_ERRLOG1_LOW */ + .errlog1_high = 0x2C, /* ERL_ERRLOG1_HIGH */ + .errlog2_low = 0x30, /* ERL_ERRLOG2_LOW */ + .errlog2_high = 0x34, /* ERL_ERRLOG2_HIGH */ + .errlog3_low = 0x38, /* ERL_ERRLOG3_LOW */ + .errlog3_high = 0x3C, /* ERL_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam770_cpas100_errata_wa_list = { + .enable_icp_clk_for_qchannel = { + .enable = true, + }, +}; + +static struct cam_camnoc_info cam770_cpas100_camnoc_info = { + .specific = &cam_cpas_v770_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v770_100_camnoc_specific), + .irq_sbm = &cam_cpas_v770_100_irq_sbm, + .irq_err = &cam_cpas_v770_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v770_100_irq_err), + .err_logger = &cam770_cpas100_err_logger_offsets, + .errata_wa_list = &cam770_cpas100_errata_wa_list, +}; + +static struct cam_cpas_camnoc_qchannel cam770_cpas100_qchannel_info = { + .qchannel_ctrl = 0x14, + .qchannel_status = 0x18, +}; + +static struct cam_cpas_info cam770_cpas100_cpas_info = { + .hw_caps_info = { + .num_caps_registers = 1, + .hw_caps_offsets = {0x8}, + }, + .qchannel_info = {&cam770_cpas100_qchannel_info}, + .num_qchannel = 1, +}; + +static struct cam_cpas_top_regs cam770_cpas100_cpas_top_info = { + .tpg_mux_sel_enabled = true, + .tpg_mux_sel_shift = 0x0, + .tpg_mux_sel = 0x1C, +}; + +#endif /* _CPASTOP_V770_100_H_ */ + diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v860_100.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v860_100.h new file mode 100644 index 0000000000..df2232f9ce --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v860_100.h @@ -0,0 +1,1347 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CPASTOP_V860_100_H_ +#define _CPASTOP_V860_100_H_ + +static struct cam_camnoc_irq_sbm cam_cpas_v860_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */ + .value = 0x01 |/* SBM_FAULTINEN0_LOW_PORT0_MASK */ + 0x02 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20, /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + .value = 0xE, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v860_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8, /* CAM_NOC_ERL_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x10, /* CAM_NOC_ERL_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x18, /* CAM_NOC_ERL_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x93A0, /* IFE_UBWC : RT_1_NIU_ENCERREN_LOW */ + .value = 0xF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x9390, /* IFE_UBWC : RT_1_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x9398, /* IFE_UBWC : RT_1_NIU_ENCERRCLR_LOW */ + .value = 0x1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x87A0, /* BPS_WR : NRT_2_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8790, /* BPS_WR : NRT_2_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8798, /* BPS_WR : NRT_2_NIU_ENCERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8B20, /* IPE_0_RD : NRT_4_NIU_DECERREN_LOW */ + .value = 0xFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8B10, /* IPE_0_RD : NRT_4_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8B18, /* IPE_0_RD : NRT_4_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8D20, /* IPE_1_RD : NRT_5_NIU_DECERREN_LOW */ + .value = 0XFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8D10, /* IPE_1_RD : NRT_5_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8D18, /* IPE_1_RD : NRT_5_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x8FA0, /* IPE_WR : NRT_6_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x8F90, /* IPE_WR : NRT_6_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x8F98, /* IPE_WR : NRT_6_NIU_ENCERRCLR_LOW */ + .value = 0x1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = false, + .sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = false, + .sbm_port = 0x80, /* SBM_FAULTINSTATUS0_LOW_PORT7_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x3, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v860_100_camnoc_specific[] = { + /* RT ports */ + { + .port_name = "RT0-SFE_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9030, /* SFE_RD : NOC_RT_0_NIU_PRIORITYLUT_LOW */ + .value = 0x44444444, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9034, /* SFE_RD : NOC_RT_0_NIU_PRIORITYLUT_HIGH */ + .value = 0x44444444, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9038, /* SFE_RD : NOC_RT_0_NIU_URGENCY_LOW */ + .value = 0x1004, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9040, /* SFE_RD : NOC_RT_0_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9048, /* SFE_RD : NOC_RT_0_NIU_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9D88, /* SFE_RD : NOC_RT_0_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7388, /* SFE_RD : NOC_RT_0_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x73A0, /* SFE_RD : NOC_RT_0_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x73A4, /* SFE_RD : NOC_RT_0_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_name = "RT1-IFE_UBWC", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9230, /* IFE_UBWC_LINEAR : NOC_RT_1_NIU_PRIORITYLUT_LOW */ + .value = 0x65555544, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9234, /* IFE_UBWC_LINEAR : NOC_RT_1_NIU_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9238, /* IFE_UBWC_LINEAR : NOC_RT_1_NIU_URGENCY_LOW */ + .value = 0x1E40, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9240, /* IFE_UBWC_LINEAR : NOC_RT_1_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9248, /* IFE_UBWC_LINEAR : NOC_RT_1_NIU_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9E08, /* IFE_UBWC_LINEAR : NOC_RT_1_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7408, /* IFE_UBWC_LINEAR : NOC_RT_1_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7420, /* IFE_UBWC_LINEAR : NOC_RT_1_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7424, /* IFE_UBWC_LINEAR : NOC_RT_1_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x9220, /* IFE_UBWC_LINEAR : NOC_RT_1_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_name = "RT2-IFE_STATS", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9430, /* IFE_STATS : NOC_RT_2_NIU_PRIORITYLUT_LOW */ + .value = 0x65555544, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9434, /* IFE_STATS : NOC_RT_2_NIU_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9438, /* IFE_STATS : NOC_RT_2_NIU_URGENCY_LOW */ + .value = 0x1C40, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9440, /* IFE_STATS : NOC_RT_2_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9448, /* IFE_STATS : NOC_RT_2_NIU_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9E88, /* IFE_STATS : NOC_RT_2_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7488, /* IFE_STATS : NOC_RT_2_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x74A0, /* IFE_STATS : NOC_RT_2_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x74A4, /* IFE_STATS : NOC_RT_2_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x9420, /* IFE_STATS : NOC_RT_2_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_name = "RT3-IFE_PDAF_LINEAR_IFELITE", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9630, /* IFE_PDAF_IFELITE : NOC_RT_3_NIU_PRIORITYLUT_LOW */ + .value = 0x65555544, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9634, /* IFE_PDAF_IFELITE : NOC_RT_3_NIU_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9638, /* IFE_PDAF_IFELITE : NOC_RT_3_NIU_URGENCY_LOW */ + .value = 0x1C40, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9640, /* IFE_PDAF_IFELITE : NOC_RT_3_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9648, /* IFE_PDAF_IFELITE : NOC_RT_3_NIU_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9F08, /* IFE_PDAF_IFELITE : NOC_RT_3_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7508, /* IFE_PDAF_IFELITE : NOC_RT_3_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7520, /* IFE_PDAF_IFELITE : NOC_RT_3_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7524, /* IFE_PDAF_IFELITE : NOC_RT_3_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x9620, /* IFE_PDAF_IFELITE : NOC_RT_3_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_name = "RT4-IFE_RDI_SFE", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9830, /* IFE_RDI_SFE : NOC_RT_4_NIU_PRIORITYLUT_LOW */ + .value = 0x65555544, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9834, /* IFE_RDI_SFE : NOC_RT_4_NIU_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9838, /* IFE_RDI_SFE : NOC_RT_4_NIU_URGENCY_LOW */ + .value = 0x1E40, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9840, /* IFE_RDI_SFE : NOC_RT_4_NIU_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9848, /* IFE_RDI_SFE : NOC_RT_4_NIU_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9F88, /* IFE_RDI_SFE : NOC_RT_4_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7588, /* IFE_RDI_SFE : NOC_RT_4_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x75A0, /* IFE_RDI_SFE : NOC_RT_4_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x75A4, /* IFE_RDI_SFE : NOC_RT_4_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x9820, /* IFE_RDI_SFE : NOC_RT_4_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + /* NRT ports */ + { + .port_name = "NRT0-CDM", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8230, /* CDM : NOC_NRT_0_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8234, /* CDM : NOC_NRT_0_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8238, /* CDM : NOC_NRT_0_NIU_URGENCY_LOW */ + .value = 0x1003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8240, /* CDM : NOC_NRT_0_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8248, /* CDM : NOC_NRT_0_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9A08, /* CDM : NOC_NRT_0_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7008, /* CDM : NOC_NRT_0_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7020, /* CDM : NOC_NRT_0_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7024, /* CDM : NOC_NRT_0_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_name = "NRT1-JPEG_RD_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8430, /* JPEG : NOC_NRT_1_NIU_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8434, /* JPEG : NOC_NRT_1_NIU_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8438, /* JPEG : NOC_NRT_1_NIU_URGENCY_LOW */ + .value = 0x0022, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8440, /* JPEG : NOC_NRT_1_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8448, /* JPEG : NOC_NRT_1_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9A88, /* JPEG : NOC_NRT_1_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7088, /* JPEG : NOC_NRT_1_QOSGEN_MAINCTL */ + .value = 0x2, + }, + .qosgen_shaping_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x70A0, /* JPEG : NOC_NRT_1_QOSGEN_SHAPING_LOW */ + .value = 0x10101010, + }, + .qosgen_shaping_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x70A4, /* JPEG : NOC_NRT_1_QOSGEN_SHAPING_HIGH */ + .value = 0x10101010, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8420, /* JPEG : NOC_NRT_1_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_name = "NRT2-BPS_CRE_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8630, /* BPS_CRE_WR : NOC_NRT_2_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8634, /* BPS_CRE_WR : NOC_NRT_2_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8638, /* BPS_CRE_WR : NOC_NRT_2_NIU_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8640, /* BPS_CRE_WR : NOC_NRT_2_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8648, /* BPS_CRE_WR : NOC_NRT_2_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9B08, /* BPS_CRE_WR : NOC_NRT_2_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7108, /* BPS_CRE_WR : NOC_NRT_2_QOSGEN_MAINCTL */ + .value = 0x2, + }, + .qosgen_shaping_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7120, /* BPS_CRE_WR : NOC_NRT_2_QOSGEN_SHAPING_LOW */ + .value = 0x14141414, + }, + .qosgen_shaping_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7124, /* BPS_CRE_WR : NOC_NRT_2_BPS_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x14141414, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8620, /* BPS_CRE_WR : NOC_NRT_2_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_name = "NRT3-BPS_CRE_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8830, /* BPS_CRE_RD : NOC_NRT_3_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8834, /* BPS_CRE_RD : NOC_NRT_3_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8838, /* BPS_CRE_RD : NOC_NRT_3_NIU_URGENCY_LOW */ + .value = 0x1003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8840, /* BPS_CRE_RD : NOC_NRT_3_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8848, /* BPS_CRE_RD : NOC_NRT_3_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9B88, /* BPS_CRE_RD : NOC_NRT_3_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7188, /* BPS_CRE_RD : NOC_NRT_3_QOSGEN_MAINCTL */ + .value = 0x2, + }, + .qosgen_shaping_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x71A0, /* BPS_CRE_RD : NOC_NRT_3_QOSGEN_SHAPING_LOW */ + .value = 0x14141414, + }, + .qosgen_shaping_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x71A4, /* BPS_CRE_RD : NOC_NRT_3_QOSGEN_SHAPING_HIGH */ + .value = 0x14141414, + }, + }, + { + .port_name = "NRT4-IPE_0_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A30, /* IPE_0_RD : NOC_NRT_4_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A34, /* IPE_0_RD : NOC_NRT_4_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A38, /* IPE_0_RD : NOC_NRT_4_NIU_URGENCY_LOW */ + .value = 0x1003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A40, /* IPE_0_RD : NOC_NRT_4_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8A48, /* IPE_0_RD : NOC_NRT_4_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8B08, /* IPE_0_RD : NOC_NRT_4_NIU_DECCTL_LOW */ + .value = 1, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9C08, /* IPE_0_RD : NOC_NRT_4_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7208, /* IPE_0_RD : NOC_NRT_4_QOSGEN_MAINCTL */ + .value = 0x2, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7220, /* IPE_0_RD : NOC_NRT_4_QOSGEN_SHAPING_LOW */ + .value = 0x2E2E2E2E, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7224, /* IPE_0_RD : NOC_NRT_4_QOSGEN_SHAPING_HIGH */ + .value = 0x2E2E2E2E, + }, + }, + { + .port_name = "NRT5-IPE_1_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C30, /* IPE_1_RD : NOC_NRT_5_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C34, /* IPE_1_RD : NOC_NRT_5_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C38, /* IPE_1_RD : NOC_NRT_5_NIU_URGENCY_LOW */ + .value = 0x1003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C40, /* IPE_1_RD : NOC_NRT_5_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8C48, /* IPE_1_RD : NOC_NRT_5_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9C88, /* IPE_1_RD : NOC_NRT_5_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7288, /* IPE_1_RD : NOC_NRT_5_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x72A0, /* IPE_1_RD : NOC_NRT_5_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x72A4, /* IPE_1_RD : NOC_NRT_5_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_name = "NRT6-IPE_WR_0", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E30, /* IPE_WR_0 : NOC_NRT_6_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E34, /* IPE_WR_0 : NOC_NRT_6_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E38, /* IPE_WR_0 : NOC_NRT_6_NIU_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E40, /* IPE_WR_0 : NOC_NRT_6_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8E48, /* IPE_WR_0 : NOC_NRT_6_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x9D08, /* IPE_WR_0 : NOC_NRT_6_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7308, /* IPE_WR_0 : NOC_NRT_6_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7320, /* IPE_WR_0 : NOC_NRT_6_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7324, /* IPE_WR_0 : NOC_NRT_6_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x8E20, /* IPE_WR_0 : NOC_NRT_6_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_name = "NRT7-IPE_WR_1", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA430, /* IPE_WR_1 : NOC_NRT_7_NIU_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA434, /* IPE_WR_1 : NOC_NRT_7_NIU_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA438, /* IPE_WR_1 : NOC_NRT_7_NIU_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA440, /* IPE_WR_1 : NOC_NRT_7_NIU_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA448, /* IPE_WR_1 : NOC_NRT_7_NIU_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA608, /* IPE_WR_1 : NOC_NRT_7_DYNATTR_MAINCTL */ + .value = 0x0, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA688, /* IPE_WR_1 : NOC_NRT_7_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA6A0, /* IPE_WR_1 : NOC_NRT_7_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA6A4, /* IPE_WR_1 : NOC_NRT_7_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0xA420, /* IPE_WR_1 : NOC_NRT_7_NIU_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_name = "ICP_RD_WR", + .enable = false, + .dynattr_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA008, /* ICP_RD_WR : NOC_XM_ICP_DYNATTR_MAINCTL */ + .value = 0x10, + }, + .qosgen_mainctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7608, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_MAINCTL */ + .value = 0x1000040, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7620, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7624, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam860_cpas100_err_logger_offsets = { + .mainctrl = 0x08, /* NOC_ERL_MAINCTL_LOW */ + .errvld = 0x10, /* NOC_ERL_ERRVLD_LOW */ + .errlog0_low = 0x20, /* NOC_ERL_ERRLOG0_LOW */ + .errlog0_high = 0x24, /* NOC_ERL_ERRLOG0_HIGH */ + .errlog1_low = 0x28, /* NOC_ERL_ERRLOG1_LOW */ + .errlog1_high = 0x2C, /* NOC_ERL_ERRLOG1_HIGH */ + .errlog2_low = 0x30, /* NOC_ERL_ERRLOG2_LOW */ + .errlog2_high = 0x34, /* NOC_ERL_ERRLOG2_HIGH */ + .errlog3_low = 0x38, /* NOC_ERL_ERRLOG3_LOW */ + .errlog3_high = 0x3C, /* NOC_ERL_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam860_cpas100_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x300, /* sbm_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, + .enable_icp_clk_for_qchannel = { + .enable = true, + }, +}; + +static struct cam_cpas_cesta_vcd_reg_info cam_cpas_v860_100_cesta_reg_info = { + .vcd_currol = { + .reg_offset = 0x300c, + .vcd_base_inc = 0x200, + .num_vcds = 8, + }, + +}; + +static struct cam_cpas_vcd_info cam_v860_100_vcd_info[] = { + { + .index = 0, .type = CAM_CESTA_CRMC, .clk = "cam_cc_ife_0_clk_src", + }, + { + .index = 1, .type = CAM_CESTA_CRMC, .clk = "cam_cc_ife_1_clk_src", + }, + { + .index = 2, .type = CAM_CESTA_CRMC, .clk = "cam_cc_ife_2_clk_src", + }, + { + .index = 3, .type = CAM_CESTA_CRMC, .clk = "cam_cc_sfe_0_clk_src", + }, + { + .index = 4, .type = CAM_CESTA_CRMC, .clk = "cam_cc_sfe_1_clk_src", + }, + { + .index = 6, .type = CAM_CESTA_CRMC, .clk = "cam_cc_csid_clk_src", + }, + { + .index = 7, .type = CAM_CESTA_CRMC, .clk = "cam_cc_cphy_rx_clk_src", + }, + { + .index = 8, .type = CAM_CESTA_CRMB, .clk = "cam_cc_camnoc_axi_rt_clk_src", + }, +}; + +static struct cam_cpas_cesta_info cam_v860_cesta_info = { + .vcd_info = &cam_v860_100_vcd_info[0], + .num_vcds = ARRAY_SIZE(cam_v860_100_vcd_info), + .cesta_reg_info = &cam_cpas_v860_100_cesta_reg_info, +}; + +static struct cam_camnoc_info cam860_cpas100_camnoc_info = { + .specific = &cam_cpas_v860_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v860_100_camnoc_specific), + .irq_sbm = &cam_cpas_v860_100_irq_sbm, + .irq_err = &cam_cpas_v860_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v860_100_irq_err), + .err_logger = &cam860_cpas100_err_logger_offsets, + .errata_wa_list = &cam860_cpas100_errata_wa_list, + .test_irq_info = { + .sbm_enable_mask = 0x80, + .sbm_clear_mask = 0x4, + }, +}; + +static struct cam_cpas_camnoc_qchannel cam860_cpas100_qchannel_info = { + .qchannel_ctrl = 0x5C, + .qchannel_status = 0x60, +}; + +static struct cam_cpas_info cam860_cpas100_cpas_info = { + .hw_caps_info = { + .num_caps_registers = 2, + .hw_caps_offsets = {0x8, 0xDC}, + }, + .qchannel_info = {&cam860_cpas100_qchannel_info}, + .num_qchannel = 1, +}; + +#endif /* _CPASTOP_V860_100_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_cpas/include/cam_cpas_api.h b/qcom/opensource/camera-kernel/drivers/cam_cpas/include/cam_cpas_api.h index a653bc4224..7ee1e7d911 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cpas/include/cam_cpas_api.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cpas/include/cam_cpas_api.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CPAS_API_H_ @@ -32,6 +32,15 @@ #define CAM_CPAS_QOS_DEFAULT_SETTINGS_MASK 0x1 #define CAM_CPAS_QOS_CUSTOM_SETTINGS_MASK 0x2 +/** + * Secure camera QoS update id - Enum for identify QOS settings update type + */ +enum secure_camera_qos_update_type { + CAM_QOS_UPDATE_TYPE_STATIC = 0x0, + CAM_QOS_UPDATE_TYPE_SMART = 0x1, + CAM_QOS_UPDATE_TYPE_MAX, +}; + /** * enum cam_cpas_regbase_types - Enum for cpas regbase available for clients * to read/write @@ -86,6 +95,9 @@ enum cam_cpas_camera_version { CAM_CPAS_CAMERA_VERSION_640 = 0x00060400, CAM_CPAS_CAMERA_VERSION_880 = 0x00080800, CAM_CPAS_CAMERA_VERSION_980 = 0x00090800, + CAM_CPAS_CAMERA_VERSION_860 = 0x00080600, + CAM_CPAS_CAMERA_VERSION_770 = 0x00070700, + CAM_CPAS_CAMERA_VERSION_665 = 0x00060605, CAM_CPAS_CAMERA_VERSION_MAX }; @@ -100,6 +112,7 @@ enum cam_cpas_version { CAM_CPAS_VERSION_120 = 0x10020000, CAM_CPAS_VERSION_130 = 0x10030000, CAM_CPAS_VERSION_200 = 0x20000000, + CAM_CPAS_VERSION_210 = 0x20010000, CAM_CPAS_VERSION_MAX }; @@ -123,6 +136,9 @@ enum cam_cpas_camera_version_map_id { CAM_CPAS_CAMERA_VERSION_ID_640 = 0xC, CAM_CPAS_CAMERA_VERSION_ID_880 = 0xD, CAM_CPAS_CAMERA_VERSION_ID_980 = 0xE, + CAM_CPAS_CAMERA_VERSION_ID_860 = 0xF, + CAM_CPAS_CAMERA_VERSION_ID_770 = 0x10, + CAM_CPAS_CAMERA_VERSION_ID_665 = 0x11, CAM_CPAS_CAMERA_VERSION_ID_MAX }; @@ -137,6 +153,7 @@ enum cam_cpas_version_map_id { CAM_CPAS_VERSION_ID_120 = 0x3, CAM_CPAS_VERSION_ID_130 = 0x4, CAM_CPAS_VERSION_ID_200 = 0x5, + CAM_CPAS_VERSION_ID_210 = 0x6, CAM_CPAS_VERSION_ID_MAX }; @@ -166,8 +183,12 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_680_V110 = 0x680110, CAM_CPAS_TITAN_780_V100 = 0x780100, CAM_CPAS_TITAN_640_V200 = 0x640200, + CAM_CPAS_TITAN_640_V210 = 0x640210, CAM_CPAS_TITAN_880_V100 = 0x880100, CAM_CPAS_TITAN_980_V100 = 0x980100, + CAM_CPAS_TITAN_860_V100 = 0x860100, + CAM_CPAS_TITAN_770_V100 = 0x770100, + CAM_CPAS_TITAN_665_V100 = 0x665100, CAM_CPAS_TITAN_MAX }; diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_context.c b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_context.c index 32f5205e4b..801e18e012 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_context.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_context.c @@ -43,7 +43,7 @@ static int __cam_cre_ctx_flush_dev_in_ready(struct cam_context *ctx, flush_args.cmd = cmd; flush_args.flush_active_req = false; - rc = cam_context_flush_dev_to_hw(ctx, cmd, &flush_args); + rc = cam_context_flush_dev_to_hw(ctx, &flush_args); if (rc) CAM_ERR(CAM_CRE, "Failed to flush device"); diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c index 7be6214f21..0fa69f2d9a 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -210,9 +210,17 @@ static int cam_cre_mgr_process_cmd_io_buf_req(struct cam_cre_hw_mgr *hw_mgr, /* Width for WE has to be updated in number of pixels */ if (acq_io_buf->direction == CAM_BUF_OUTPUT) { - /* PLAIN 128/8 = 16 Bytes per pixel */ - plane_info->width = - io_cfg_ptr[j].planes[k].plane_stride/16; + if (plane_info->format == CAM_FORMAT_PLAIN16_10) { + plane_info->width = + io_cfg_ptr[j].planes[k].plane_stride/2; + } else if (plane_info->format == CAM_FORMAT_PLAIN128) { + /* PLAIN 128/8 = 16 Bytes per pixel */ + plane_info->width = + io_cfg_ptr[j].planes[k].plane_stride/16; + } else { + plane_info->width = + io_cfg_ptr[j].planes[k].width; + } } else { /* FE width should be in bytes */ plane_info->width = @@ -402,10 +410,6 @@ static int cam_cre_mgr_remove_bw(struct cam_cre_hw_mgr *hw_mgr, int ctx_id) ctx_data->clk_info.axi_path[i].mnoc_ab_bw; hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -= ctx_data->clk_info.axi_path[i].mnoc_ib_bw; - hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -= - ctx_data->clk_info.axi_path[i].ddr_ab_bw; - hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -= - ctx_data->clk_info.axi_path[i].ddr_ib_bw; } rc = cam_cre_update_cpas_vote(hw_mgr, ctx_data); @@ -474,10 +478,6 @@ static bool cam_cre_update_bw_v2(struct cam_cre_hw_mgr *hw_mgr, ctx_data->clk_info.axi_path[i].mnoc_ab_bw; hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -= ctx_data->clk_info.axi_path[i].mnoc_ib_bw; - hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -= - ctx_data->clk_info.axi_path[i].ddr_ab_bw; - hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -= - ctx_data->clk_info.axi_path[i].ddr_ib_bw; } ctx_data->clk_info.num_paths = @@ -515,10 +515,6 @@ static bool cam_cre_update_bw_v2(struct cam_cre_hw_mgr *hw_mgr, ctx_data->clk_info.axi_path[i].mnoc_ab_bw; hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw += ctx_data->clk_info.axi_path[i].mnoc_ib_bw; - hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw += - ctx_data->clk_info.axi_path[i].ddr_ab_bw; - hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw += - ctx_data->clk_info.axi_path[i].ddr_ib_bw; CAM_DBG(CAM_CRE, "Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]", ctx_data->cre_acquire.dev_name, @@ -764,45 +760,51 @@ static int cam_cre_mgr_process_cmd(void *priv, void *data) task_data = (struct cre_cmd_work_data *)data; mutex_lock(&hw_mgr->hw_mgr_mutex); + mutex_lock(&ctx_data->ctx_mutex); if (ctx_data->ctx_state != CRE_CTX_STATE_ACQUIRED) { - mutex_unlock(&hw_mgr->hw_mgr_mutex); CAM_ERR(CAM_CRE, "ctx id :%u is not in use", ctx_data->ctx_id); - return -EINVAL; + rc = -EINVAL; + goto err; } if (task_data->req_idx >= CAM_CTX_REQ_MAX) { - mutex_unlock(&hw_mgr->hw_mgr_mutex); CAM_ERR(CAM_CRE, "Invalid reqIdx = %llu", - task_data->req_idx); - return -EINVAL; + task_data->req_idx); + rc = -EINVAL; + goto err; + } + + if (task_data->request_id <= ctx_data->last_flush_req) { + CAM_WARN(CAM_CRE, + "request %lld has been flushed, reject packet", task_data->request_id); + rc = -EINVAL; + goto err; } cre_req = ctx_data->req_list[task_data->req_idx]; if (cre_req->request_id > ctx_data->last_flush_req) ctx_data->last_flush_req = 0; - if (cre_req->request_id <= ctx_data->last_flush_req) { - CAM_WARN(CAM_CRE, - "request %lld has been flushed, reject packet", - cre_req->request_id, ctx_data->last_flush_req); - mutex_unlock(&hw_mgr->hw_mgr_mutex); - return -EINVAL; - } - if (!cam_cre_is_pending_request(ctx_data)) { CAM_WARN(CAM_CRE, "no pending req, req %lld last flush %lld", cre_req->request_id, ctx_data->last_flush_req); - mutex_unlock(&hw_mgr->hw_mgr_mutex); - return -EINVAL; + rc = -EINVAL; + goto err; } hw_mgr = task_data->data; num_batch = cre_req->num_batch; + if (num_batch > CRE_MAX_BATCH_SIZE) { + CAM_WARN(CAM_CRE, "num_batch = %u is greater than max", + num_batch); + num_batch = CRE_MAX_BATCH_SIZE; + } + CAM_DBG(CAM_CRE, - "Going to configure cre for req %d, req_idx %d num_batch %d", - cre_req->request_id, cre_req->req_idx, num_batch); + "Ctx %d Going to configure cre for req %d, req_idx %d num_batch %d", + ctx_data->ctx_id, cre_req->request_id, cre_req->req_idx, num_batch); for (i = 0; i < num_batch; i++) { if (i != 0) { @@ -813,7 +815,8 @@ static int cam_cre_mgr_process_cmd(void *priv, void *data) cam_cre_device_timer_reset(cre_hw_mgr); CAM_ERR(CAM_CRE, "Timedout waiting for bufdone on last frame"); - return -ETIMEDOUT; + rc = -EINVAL; + goto err; } else { reinit_completion(&ctx_data->cre_top->bufdone); CAM_INFO(CAM_CRE, @@ -825,27 +828,13 @@ static int cam_cre_mgr_process_cmd(void *priv, void *data) cam_cre_mgr_update_reg_set(hw_mgr, cre_req, i); cam_cre_ctx_wait_for_idle_irq(ctx_data); } +err: + mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; } -static int cam_get_valid_ctx_id(void) -{ - struct cam_cre_hw_mgr *hw_mgr = cre_hw_mgr; - int i; - - for (i = 0; i < CRE_CTX_MAX; i++) { - if (hw_mgr->ctx[i].ctx_state == CRE_CTX_STATE_ACQUIRED) - break; - } - - if (i == CRE_CTX_MAX) - return -EINVAL; - - return i; -} - static int32_t cam_cre_mgr_process_msg(void *priv, void *data) { struct cre_msg_work_data *task_data; @@ -854,7 +843,7 @@ static int32_t cam_cre_mgr_process_msg(void *priv, void *data) struct cam_cre_ctx *ctx; struct cam_cre_request *active_req; struct cam_cre_irq_data irq_data; - int32_t ctx_id; + struct cam_cre_hw_cfg_req *cfg_req = NULL; uint32_t evt_id; uint32_t active_req_idx; int rc = 0; @@ -866,30 +855,51 @@ static int32_t cam_cre_mgr_process_msg(void *priv, void *data) task_data = data; hw_mgr = priv; - ctx_id = cam_get_valid_ctx_id(); - if (ctx_id < 0) { - CAM_ERR(CAM_CRE, "No valid context to handle error"); - return ctx_id; + + mutex_lock(&hw_mgr->hw_mgr_mutex); + cfg_req = list_first_entry(&hw_mgr->hw_config_req_list, + struct cam_cre_hw_cfg_req, list); + if (!cfg_req) { + CAM_ERR(CAM_CRE, "Hw config req list empty"); + rc = -EFAULT; + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; } + list_del_init(&cfg_req->list); - ctx = &hw_mgr->ctx[ctx_id]; - - mutex_lock(&ctx->ctx_mutex); - irq_data = task_data->irq_data; - if (ctx->ctx_state != CRE_CTX_STATE_ACQUIRED) { - CAM_DBG(CAM_CRE, "ctx id: %d not in right state: %d", - ctx_id, ctx->ctx_state); - mutex_unlock(&ctx->ctx_mutex); + if (cfg_req->ctx_id < 0) { + CAM_ERR(CAM_CRE, "No valid context to handle error"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); return -EINVAL; } + ctx = &hw_mgr->ctx[cfg_req->ctx_id]; + mutex_lock(&ctx->ctx_mutex); + + irq_data = task_data->irq_data; + if (ctx->ctx_state != CRE_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_CRE, "ctx id: %d not in right state: %d", + cfg_req->ctx_id, ctx->ctx_state); + rc = -EINVAL; + goto end; + } + active_req_idx = find_next_bit(ctx->bitmap, ctx->bits, ctx->last_done_req_idx); - CAM_DBG(CAM_CRE, "active_req_idx %d last_done_req_idx %d", + CAM_DBG(CAM_CRE, "Ctx %d active_req_idx %d last_done_req_idx %d", ctx->ctx_id, active_req_idx, ctx->last_done_req_idx); + if (active_req_idx >= CAM_CTX_REQ_MAX) { + CAM_WARN(CAM_CRE, "ctx %d not valid req idx active_req_idx %d", active_req_idx); + rc = -EINVAL; + goto end; + } + active_req = ctx->req_list[active_req_idx]; - if (!active_req) + if (!active_req) { CAM_ERR(CAM_CRE, "Active req cannot be null"); + rc = -EINVAL; + goto end; + } if (irq_data.error) { evt_id = CAM_CTX_EVT_ID_ERROR; @@ -905,14 +915,14 @@ static int32_t cam_cre_mgr_process_msg(void *priv, void *data) } else if (irq_data.wr_buf_done) { /* Signal Buf done */ active_req->frames_done++; - CAM_DBG(CAM_CRE, "Received frames_done %d num_batch %d req id %d", - active_req->frames_done, active_req->num_batch, + CAM_DBG(CAM_CRE, "Ctx %d Received frames_done %d num_batch %d req id %d", + ctx->ctx_id, active_req->frames_done, active_req->num_batch, active_req->request_id); complete(&ctx->cre_top->bufdone); if (active_req->frames_done == active_req->num_batch) { ctx->last_done_req_idx = active_req_idx; - CAM_DBG(CAM_CRE, "signaling buff done for req %d", - active_req->request_id); + CAM_DBG(CAM_CRE, "Ctx %d signaling buff done for req %d", + ctx->ctx_id, active_req->request_id); evt_id = CAM_CTX_EVT_ID_SUCCESS; buf_data.evt_param = CAM_SYNC_COMMON_EVENT_SUCCESS; buf_data.request_id = active_req->request_id; @@ -924,7 +934,10 @@ static int32_t cam_cre_mgr_process_msg(void *priv, void *data) ctx->req_list[active_req_idx] = NULL; } } +end: + list_add_tail(&cfg_req->list, &hw_mgr->free_req_list); mutex_unlock(&ctx->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; } @@ -1550,6 +1563,12 @@ static int cam_cre_validate_acquire_res_info( cre_acquire->in_res[i].format); return -EINVAL; } + + if (!cre_acquire->in_res[i].width || !cre_acquire->in_res[i].height) { + CAM_ERR(CAM_CRE, "Invalid width %d height %d for in res %d", + cre_acquire->in_res[i].width, cre_acquire->in_res[i].height, i); + return -EINVAL; + } } for (i = 0; i < cre_acquire->num_out_res; i++) { @@ -1794,8 +1813,6 @@ static int cam_cre_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) hw_mgr->clk_info.axi_path[i].camnoc_bw = 0; hw_mgr->clk_info.axi_path[i].mnoc_ab_bw = 0; hw_mgr->clk_info.axi_path[i].mnoc_ib_bw = 0; - hw_mgr->clk_info.axi_path[i].ddr_ab_bw = 0; - hw_mgr->clk_info.axi_path[i].ddr_ib_bw = 0; } } @@ -1843,8 +1860,6 @@ static int cam_cre_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) bw_update->axi_vote.axi_path[0].camnoc_bw = 600000000; bw_update->axi_vote.axi_path[0].mnoc_ab_bw = 600000000; bw_update->axi_vote.axi_path[0].mnoc_ib_bw = 600000000; - bw_update->axi_vote.axi_path[0].ddr_ab_bw = 600000000; - bw_update->axi_vote.axi_path[0].ddr_ib_bw = 600000000; bw_update->axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; bw_update->axi_vote.axi_path[0].path_data_type = @@ -2008,7 +2023,7 @@ static int cam_cre_mgr_release_hw(void *hw_priv, void *hw_release_args) mutex_lock(&hw_mgr->hw_mgr_mutex); rc = cam_cre_mgr_release_ctx(hw_mgr, ctx_id); if (!hw_mgr->cre_ctx_cnt) { - CAM_DBG(CAM_CRE, "Last Release"); + CAM_DBG(CAM_CRE, "Last Release #of CRE %d", cre_hw_mgr->num_cre); for (i = 0; i < cre_hw_mgr->num_cre; i++) { dev_intf = hw_mgr->cre_dev_intf[i]; irq_cb.cre_hw_mgr_cb = NULL; @@ -2106,20 +2121,20 @@ static int cam_cre_packet_generic_blob_handler(void *user_data, clk_info = &ctx_data->req_list[index]->clk_info; clk_info_v2 = &ctx_data->req_list[index]->clk_info_v2; - clk_info_v2.budget_ns = soc_req->budget_ns; - clk_info_v2.frame_cycles = soc_req->frame_cycles; - clk_info_v2.rt_flag = soc_req->rt_flag; - clk_info_v2.num_paths = soc_req->num_paths; + clk_info_v2->budget_ns = soc_req->budget_ns; + clk_info_v2->frame_cycles = soc_req->frame_cycles; + clk_info_v2->rt_flag = soc_req->rt_flag; + clk_info_v2->num_paths = soc_req->num_paths; for (i = 0; i < soc_req->num_paths; i++) { - clk_info_v2.axi_path[i].usage_data = soc_req->axi_path[i].usage_data; - clk_info_v2.axi_path[i].transac_type = soc_req->axi_path[i].transac_type; - clk_info_v2.axi_path[i].path_data_type = + clk_info_v2->axi_path[i].usage_data = soc_req->axi_path[i].usage_data; + clk_info_v2->axi_path[i].transac_type = soc_req->axi_path[i].transac_type; + clk_info_v2->axi_path[i].path_data_type = soc_req->axi_path[i].path_data_type; - clk_info_v2.axi_path[i].vote_level = 0; - clk_info_v2.axi_path[i].camnoc_bw = soc_req->axi_path[i].camnoc_bw; - clk_info_v2.axi_path[i].mnoc_ab_bw = soc_req->axi_path[i].mnoc_ab_bw; - clk_info_v2.axi_path[i].mnoc_ib_bw = soc_req->axi_path[i].mnoc_ib_bw; + clk_info_v2->axi_path[i].vote_level = 0; + clk_info_v2->axi_path[i].camnoc_bw = soc_req->axi_path[i].camnoc_bw; + clk_info_v2->axi_path[i].mnoc_ab_bw = soc_req->axi_path[i].mnoc_ab_bw; + clk_info_v2->axi_path[i].mnoc_ib_bw = soc_req->axi_path[i].mnoc_ib_bw; } /* Use v1 structure for clk fields */ @@ -2292,7 +2307,6 @@ static int cam_cre_mgr_prepare_hw_update(void *hw_priv, prepare_args->num_hw_update_entries = 1; prepare_args->priv = ctx_data->req_list[request_idx]; - cre_req->hang_data.packet = packet; ktime_get_boottime_ts64(&ts); ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) + ts.tv_nsec); @@ -2330,7 +2344,8 @@ static int cam_cre_mgr_enqueue_config(struct cam_cre_hw_mgr *hw_mgr, request_id = config_args->request_id; hw_update_entries = config_args->hw_update_entries; - CAM_DBG(CAM_CRE, "req_id = %lld %pK", request_id, config_args->priv); + CAM_DBG(CAM_CRE, "Ctx %d req_id = %lld %pK", ctx_data->ctx_id, + request_id, config_args->priv); task = cam_req_mgr_workq_get_task(cre_hw_mgr->cmd_work); if (!task) { @@ -2341,6 +2356,7 @@ static int cam_cre_mgr_enqueue_config(struct cam_cre_hw_mgr *hw_mgr, task_data = (struct cre_cmd_work_data *)task->payload; task_data->data = (void *)hw_mgr; task_data->req_idx = cre_req->req_idx; + task_data->request_id = cre_req->request_id; task_data->type = CRE_WORKQ_TASK_CMD_TYPE; task->process_cb = cam_cre_mgr_process_cmd; @@ -2361,8 +2377,8 @@ static int cam_cre_mgr_config_hw(void *hw_priv, void *hw_config_args) struct cam_hw_config_args *config_args = hw_config_args; struct cam_cre_ctx *ctx_data = NULL; struct cam_cre_request *cre_req = NULL; + struct cam_cre_hw_cfg_req *cfg_req = NULL; - CAM_DBG(CAM_CRE, "E"); if (!hw_mgr || !config_args) { CAM_ERR(CAM_CRE, "Invalid arguments %pK %pK", hw_mgr, config_args); @@ -2378,23 +2394,42 @@ static int cam_cre_mgr_config_hw(void *hw_priv, void *hw_config_args) mutex_lock(&hw_mgr->hw_mgr_mutex); mutex_lock(&ctx_data->ctx_mutex); if (ctx_data->ctx_state != CRE_CTX_STATE_ACQUIRED) { - mutex_unlock(&ctx_data->ctx_mutex); - mutex_unlock(&hw_mgr->hw_mgr_mutex); CAM_ERR(CAM_CRE, "ctx id :%u is not in use", ctx_data->ctx_id); - return -EINVAL; + rc= -EINVAL; + goto end; } + if (list_empty(&hw_mgr->free_req_list)) { + CAM_ERR(CAM_CRE, "No request in free list"); + rc = -ENOMEM; + goto end; + } + + cfg_req = list_first_entry(&hw_mgr->free_req_list, + struct cam_cre_hw_cfg_req, list); + list_del_init(&cfg_req->list); + cre_req = config_args->priv; cam_cre_mgr_cre_clk_update(hw_mgr, ctx_data, cre_req->req_idx); ctx_data->req_list[cre_req->req_idx]->submit_timestamp = ktime_get(); - if (cre_req->request_id <= ctx_data->last_flush_req) + CAM_DBG(CAM_CRE, "ctx id :%u req id %lld", ctx_data->ctx_id, cre_req->request_id); + + cfg_req->req_id = cre_req->request_id; + cfg_req->ctx_id = ctx_data->ctx_id; + + if (cre_req->request_id <= ctx_data->last_flush_req) { CAM_WARN(CAM_CRE, "Anomaly submitting flushed req %llu [last_flush %llu] in ctx %u", cre_req->request_id, ctx_data->last_flush_req, ctx_data->ctx_id); + rc = -EINVAL; + goto end; + } + + list_add_tail(&cfg_req->list, &hw_mgr->hw_config_req_list); rc = cam_cre_mgr_enqueue_config(hw_mgr, ctx_data, config_args); if (rc) @@ -2409,6 +2444,7 @@ static int cam_cre_mgr_config_hw(void *hw_priv, void *hw_config_args) return rc; config_err: cam_cre_mgr_handle_config_err(config_args, ctx_data); +end: mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; @@ -2417,6 +2453,7 @@ config_err: static void cam_cre_mgr_dump_pf_data(struct cam_cre_hw_mgr *hw_mgr, struct cam_hw_cmd_pf_args *pf_cmd_args) { + int rc = 0; struct cam_packet *packet; struct cam_hw_dump_pf_args *pf_args; size_t len; @@ -2970,6 +3007,14 @@ int cam_cre_hw_mgr_init(struct device_node *of_node, void *hw_mgr, if (rc) goto cre_wq_create_failed; + INIT_LIST_HEAD(&cre_hw_mgr->hw_config_req_list); + INIT_LIST_HEAD(&cre_hw_mgr->free_req_list); + for (i = 0; i < CAM_CRE_HW_CFG_Q_MAX; i++) { + INIT_LIST_HEAD(&cre_hw_mgr->req_list[i].list); + list_add_tail(&cre_hw_mgr->req_list[i].list, + &cre_hw_mgr->free_req_list); + } + cam_cre_create_debug_fs(); if (iommu_hdl) diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.h b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.h index dcaff5da1f..cd3205e0dc 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef CAM_CRE_HW_MGR_H @@ -146,14 +146,16 @@ struct cam_cre_clk_info { /** * struct cre_cmd_work_data * - * @type: Type of work data - * @data: Private data - * @req_id: Request Idx + * @type: Type of work data + * @data: Private data + * @req_idx: Request Idx + * @request_id: Request id */ struct cre_cmd_work_data { uint32_t type; void *data; int64_t req_idx; + uint64_t request_id; }; /** @@ -341,6 +343,20 @@ struct cam_cre_ctx { cam_hw_event_cb_func ctxt_event_cb; }; +/** + * struct cam_cre_hw_cfg_req + * + * @list: Requests submiited to HW + * @req_id: Request id + * ctx_id: Ctx id + * + */ +struct cam_cre_hw_cfg_req { + struct list_head list; + uint64_t req_id; + uint32_t ctx_id; +}; + /** * struct cam_cre_hw_mgr * @@ -367,6 +383,9 @@ struct cam_cre_ctx { * @clk_info: CRE clock Info for HW manager * @dentry: Pointer to CRE debugfs directory * @dump_req_data_enable: CRE hang dump enablement + * @hw_config_req_list: Requests submitted to HW + * @free_req_list: Requests that are free + * @req_list: Request list which is applied */ struct cam_cre_hw_mgr { uint32_t cre_ctx_cnt; @@ -395,6 +414,10 @@ struct cam_cre_hw_mgr { struct cam_cre_clk_info clk_info; struct dentry *dentry; bool dump_req_data_enable; + + struct list_head hw_config_req_list; + struct list_head free_req_list; + struct cam_cre_hw_cfg_req req_list[CAM_CRE_HW_CFG_Q_MAX]; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c index 69b2defb01..f77a6dd08b 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ + #include #include "cam_hw.h" #include "cam_hw_intf.h" @@ -66,7 +68,7 @@ static void cam_cre_update_read_reg_val(struct plane_info p_info, p_info.alignment); /* Fetch engine width has to be updated in number of bytes */ - rd_client_reg_val->img_width = p_info.stride; + rd_client_reg_val->img_width = p_info.width; rd_client_reg_val->stride = p_info.stride; rd_client_reg_val->img_height = p_info.height; rd_client_reg_val->alignment = p_info.alignment; @@ -137,6 +139,10 @@ static int cam_cre_bus_rd_update(struct cam_cre_hw *cam_cre_hw_info, in_port_idx = cam_cre_bus_rd_in_port_idx(io_buf->resource_type); + if (in_port_idx < 0) { + CAM_ERR(CAM_CRE, "Invalid in_port_idx for resource %d", io_buf->resource_type); + return -EINVAL; + } CAM_DBG(CAM_CRE, "in_port_idx %d", in_port_idx); for (k = 0; k < io_buf->num_planes; k++) { @@ -179,7 +185,7 @@ static int cam_cre_bus_rd_update(struct cam_cre_hw *cam_cre_hw_info, /* Buffer size */ update_cre_reg_set(cre_reg_buf, rd_reg->offset + rd_reg_client->rd_width, - rd_client_reg_val->img_width); + ctx_data->cre_acquire.in_res[in_port_idx].width); update_cre_reg_set(cre_reg_buf, rd_reg->offset + rd_reg_client->rd_height, rd_client_reg_val->img_height); @@ -223,7 +229,7 @@ static int cam_cre_bus_rd_prepare(struct cam_cre_hw *cam_cre_hw_info, struct cre_io_buf *io_buf; struct cam_cre_bus_rd_reg *rd_reg; struct cam_cre_bus_rd_reg_val *rd_reg_val; - struct cre_reg_buffer *cre_reg_buf; + struct cre_reg_buffer *cre_reg_buf = NULL; int val; @@ -267,11 +273,12 @@ static int cam_cre_bus_rd_prepare(struct cam_cre_hw *cam_cre_hw_info, rd_reg->offset + rd_reg->input_if_cmd, val); } - - for (i = 0; i < cre_reg_buf->num_rd_reg_set; i++) { - CAM_DBG(CAM_CRE, "CRE value 0x%x offset 0x%x", - cre_reg_buf->rd_reg_set[i].value, - cre_reg_buf->rd_reg_set[i].offset); + if (cre_reg_buf) { + for (i = 0; i < cre_reg_buf->num_rd_reg_set; i++) { + CAM_DBG(CAM_CRE, "CRE value 0x%x offset 0x%x", + cre_reg_buf->rd_reg_set[i].value, + cre_reg_buf->rd_reg_set[i].offset); + } } end: return 0; @@ -441,7 +448,8 @@ static int cam_cre_bus_rd_isr(struct cam_cre_hw *cam_cre_hw_info, int32_t ctx_id, void *data) { uint32_t irq_status; - uint32_t violation_status; + uint32_t const_violation_status; + uint32_t ccif_violation_status; uint32_t debug_status_0; uint32_t debug_status_1; struct cam_cre_bus_rd_reg *bus_rd_reg; @@ -464,24 +472,30 @@ static int cam_cre_bus_rd_isr(struct cam_cre_hw *cam_cre_hw_info, cam_io_w_mb(bus_rd_reg_val->irq_cmd_clear, bus_rd_reg->base + bus_rd_reg->irq_cmd); + CAM_DBG(CAM_CRE, "BUS irq_status 0x%x", irq_status); + if (irq_status & bus_rd_reg_val->rup_done) CAM_DBG(CAM_CRE, "CRE Read Bus RUP done"); if (irq_status & bus_rd_reg_val->rd_buf_done) CAM_DBG(CAM_CRE, "CRE Read Bus Buff done"); - if (irq_status & bus_rd_reg_val->cons_violation) { + if ((irq_status & bus_rd_reg_val->cons_violation) || + (irq_status & bus_rd_reg_val->ccif_violation)) { irq_data->error = 1; - violation_status = cam_io_r_mb(bus_rd_reg->base + - bus_rd_reg->rd_clients[0].cons_violation_status); + const_violation_status = cam_io_r_mb(bus_rd_reg->base + + bus_rd_reg->cons_violation); + ccif_violation_status = cam_io_r_mb(bus_rd_reg->base + + bus_rd_reg->ccif_violation); debug_status_0 = cam_io_r_mb(bus_rd_reg->base + bus_rd_reg->rd_clients[0].debug_status_0); debug_status_1 = cam_io_r_mb(bus_rd_reg->base + bus_rd_reg->rd_clients[0].debug_status_1); CAM_DBG(CAM_CRE, "CRE Read Bus Violation"); CAM_DBG(CAM_CRE, - "violation status 0x%x debug status 0/1 0x%x/0x%x", - violation_status, debug_status_0, debug_status_1); + "violation status 0x%x 0x%x debug status 0/1 0x%x/0x%x", + const_violation_status, ccif_violation_status, + debug_status_0, debug_status_1); } return 0; diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c index 0482c462b0..5ddbf36b49 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include "cam_io_util.h" @@ -22,6 +23,70 @@ static struct cre_bus_wr *wr_info; cre_reg_buf->num_wr_reg_set++; \ } while (0) +static uint32_t cam_cre_bus_wr_format_idx(uint32_t format) +{ + uint32_t format_idx = 0; + + switch(format) { + case CAM_FORMAT_PLAIN128: + format_idx = 0x0; + break; + case CAM_FORMAT_PLAIN8: + format_idx = 0x1; + break; + case CAM_FORMAT_PLAIN8_SWAP: + format_idx = 0x2; + break; + case CAM_FORMAT_PLAIN8_10: + format_idx = 0x3; + break; + case CAM_FORMAT_PLAIN8_10_SWAP: + format_idx = 0x4; + break; + case CAM_FORMAT_PLAIN16_10: + format_idx = 0x5; + break; + case CAM_FORMAT_PLAIN16_12: + format_idx = 0x6; + break; + case CAM_FORMAT_PLAIN16_14: + format_idx = 0x7; + break; + case CAM_FORMAT_PLAIN16_16: + format_idx = 0x8; + break; + case CAM_FORMAT_PLAIN32: + format_idx = 0x9; + break; + case CAM_FORMAT_PLAIN64: + format_idx = 0xA; + break; + case CAM_FORMAT_PD10: + format_idx = 0xB; + break; + case CAM_FORMAT_MIPI_RAW_10: + format_idx = 0xC; + break; + case CAM_FORMAT_MIPI_RAW_12: + format_idx = 0xD; + break; + case CAM_FORMAT_MIPI_RAW_14: + format_idx = 0xE; + break; + case CAM_FORMAT_MIPI_RAW_20: + format_idx = 0xF; + break; + case CAM_FORMAT_PLAIN32_20: + format_idx = 0x10; + break; + default: + CAM_WARN(CAM_CRE, "Invalid format %d", format); + break; + } + + return format_idx; +} + static int cam_cre_translate_write_format(struct plane_info p_info, struct cam_cre_bus_wr_client_reg_val *wr_client_reg_val) { @@ -36,12 +101,7 @@ static int cam_cre_translate_write_format(struct plane_info p_info, wr_client_reg_val->height = p_info.height; wr_client_reg_val->alignment = p_info.alignment; - /* - * Update packer format to zero irrespective of output format - * This is as per the recomendation from CRE HW team for CRE 1.0 - * This logic has to be updated for CRE 1.1 - */ - wr_client_reg_val->format = 0; + wr_client_reg_val->format = p_info.format; return 0; } @@ -101,6 +161,7 @@ static int cam_cre_bus_wr_update(struct cam_cre_hw *cam_cre_hw_info, int rc, k, out_port_idx; uint32_t req_idx; uint32_t val = 0; + uint32_t format_idx = 0; uint32_t iova_base, iova_offset; struct cam_hw_prepare_update_args *prepare_args; struct cam_cre_ctx *ctx_data; @@ -204,12 +265,13 @@ static int cam_cre_bus_wr_update(struct cam_cre_hw *cam_cre_hw_info, wr_client_reg_val->stride); val = 0; - val |= ((wr_client_reg_val->format & - wr_client_reg_val->format_mask) << + format_idx = cam_cre_bus_wr_format_idx(wr_client_reg_val->format); + val |= ((format_idx & wr_client_reg_val->format_mask) << wr_client_reg_val->format_shift); - val |= ((wr_client_reg_val->alignment & - wr_client_reg_val->alignment_mask) << - wr_client_reg_val->alignment_shift); + + /* Update alignment as LSB by default*/ + val |= (0x1 << wr_client_reg_val->alignment_shift); + /* pack cfg : Format and alignment */ update_cre_reg_set(cre_reg_buf, wr_reg->offset + wr_reg_client->packer_cfg, diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c index ed9d11202e..3aba03d8e5 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c @@ -168,10 +168,6 @@ int cam_cre_init_hw(void *device_priv, CAM_CPAS_DEFAULT_AXI_BW; cpas_vote->axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote->axi_vote.axi_path[0].ddr_ab_bw = - CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote->axi_vote.axi_path[0].ddr_ib_bw = - CAM_CPAS_DEFAULT_AXI_BW; rc = cam_cpas_start(core_info->cpas_handle, &cpas_vote->ahb_vote, &cpas_vote->axi_vote); @@ -237,6 +233,11 @@ int cam_cre_deinit_hw(void *device_priv, CAM_ERR(CAM_CRE, "soc disable is failed : %d", rc); core_info->clk_enable = false; + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_CRE, "cpas stop is failed"); + else + core_info->cpas_start = false; + return rc; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c index de2e105ccf..5a7971d1e8 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c @@ -18,6 +18,7 @@ #include "cam_cpas_api.h" #include "cam_debug_util.h" #include "cre_hw_100.h" +#include "cre_hw_110.h" #include "cre_dev_intf.h" #include "cam_smmu_api.h" #include "camera_main.h" @@ -58,6 +59,17 @@ static int cam_cre_init_hw_version(struct cam_hw_soc_info *soc_info, switch (core_info->hw_version) { case CRE_HW_VER_1_0_0: core_info->cre_hw_info->cre_hw = &cre_hw_100; + + cre_hw_100.top_reg_offset->base = core_info->cre_hw_info->cre_top_base; + cre_hw_100.bus_rd_reg_offset->base = core_info->cre_hw_info->cre_bus_rd_base; + cre_hw_100.bus_wr_reg_offset->base = core_info->cre_hw_info->cre_bus_wr_base; + break; + case CRE_HW_VER_1_1_0: + core_info->cre_hw_info->cre_hw = &cre_hw_110; + + cre_hw_110.top_reg_offset->base = core_info->cre_hw_info->cre_top_base; + cre_hw_110.bus_rd_reg_offset->base = core_info->cre_hw_info->cre_bus_rd_base; + cre_hw_110.bus_wr_reg_offset->base = core_info->cre_hw_info->cre_bus_wr_base; break; default: CAM_ERR(CAM_CRE, "Unsupported version : %u", @@ -66,9 +78,6 @@ static int cam_cre_init_hw_version(struct cam_hw_soc_info *soc_info, break; } - cre_hw_100.top_reg_offset->base = core_info->cre_hw_info->cre_top_base; - cre_hw_100.bus_rd_reg_offset->base = core_info->cre_hw_info->cre_bus_rd_base; - cre_hw_100.bus_wr_reg_offset->base = core_info->cre_hw_info->cre_bus_wr_base; return rc; } @@ -200,10 +209,6 @@ static int cam_cre_component_bind(struct device *dev, CAM_CPAS_DEFAULT_AXI_BW; cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = - CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = - CAM_CPAS_DEFAULT_AXI_BW; rc = cam_cpas_start(core_info->cpas_handle, &cpas_vote.ahb_vote, &cpas_vote.axi_vote); diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw.h b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw.h index e359edeb0c..b099180b42 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw.h @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef CAM_CRE_HW_H #define CAM_CRE_HW_H #define CRE_HW_VER_1_0_0 0x10000000 +#define CRE_HW_VER_1_1_0 0x10010000 #define CRE_DEV_CRE 0 #define CRE_DEV_MAX 1 @@ -24,6 +26,8 @@ #define CRE_WAIT_BUS_RD_DONE 0x3 #define CRE_WAIT_IDLE_IRQ 0x4 +#define CAM_CRE_HW_CFG_Q_MAX 30 + struct cam_cre_top_reg { void *base; uint32_t offset; @@ -87,6 +91,7 @@ struct cam_cre_bus_rd_client_reg { uint32_t misr_cfg_0; uint32_t misr_cfg_1; uint32_t misr_rd_val; + uint32_t system_cache_cfg; uint32_t debug_status_cfg; uint32_t debug_status_0; uint32_t debug_status_1; @@ -109,6 +114,8 @@ struct cam_cre_bus_rd_reg { uint32_t iso_cfg; uint32_t iso_seed; uint32_t test_bus_ctrl; + uint32_t cons_violation; + uint32_t ccif_violation; uint32_t num_clients; struct cam_cre_bus_rd_client_reg rd_clients[MAX_CRE_RD_CLIENTS]; @@ -161,6 +168,7 @@ struct cam_cre_bus_rd_reg_val { uint32_t rup_done; uint32_t rd_buf_done; uint32_t cons_violation; + uint32_t ccif_violation; uint32_t static_prg; uint32_t static_prg_mask; uint32_t ica_en; @@ -190,8 +198,9 @@ struct cam_cre_bus_wr_client_reg { uint32_t img_cfg_0; uint32_t img_cfg_1; uint32_t img_cfg_2; - uint32_t bw_limit; uint32_t packer_cfg; + uint32_t bw_limit; + uint32_t system_cache_cfg; uint32_t addr_cfg; uint32_t debug_status_cfg; uint32_t debug_status_0; diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_100.h b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_100.h index e1bb5e0304..edecb6a46b 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_100.h +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_100.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef CAM_CRE_HW_100_H @@ -11,7 +12,7 @@ #define CRE_BUS_RD_TYPE 0x1 #define CRE_BUS_WR_TYPE 0x2 -static struct cam_cre_top_reg top_reg = { +static struct cam_cre_top_reg cre100_top_reg = { .hw_version = 0x000, .hw_cap = 0x004, .debug_0 = 0x080, @@ -30,7 +31,7 @@ static struct cam_cre_top_reg top_reg = { .top_spare = 0x1FC, }; -struct cam_cre_top_reg_val top_reg_value = { +struct cam_cre_top_reg_val cre100_top_reg_value = { .hw_version = 0x10000000, .hw_cap = 0x4000, .irq_mask = 0xf, @@ -46,7 +47,7 @@ struct cam_cre_top_reg_val top_reg_value = { .hw_reset_cmd = 0x1, }; -struct cam_cre_bus_rd_reg bus_rd_reg = { +struct cam_cre_bus_rd_reg cre100_bus_rd_reg = { .hw_version = 0x00, .irq_mask = 0x04, .irq_clear = 0x08, @@ -82,7 +83,7 @@ struct cam_cre_bus_rd_reg bus_rd_reg = { }, }; -struct cam_cre_bus_wr_reg_val bus_wr_reg_value = { +struct cam_cre_bus_wr_reg_val cre100_bus_wr_reg_value = { .hw_version = 0x30000000, .cgc_override = 0x1, .irq_mask_0 = 0xd0000101, @@ -137,7 +138,7 @@ struct cam_cre_bus_wr_reg_val bus_wr_reg_value = { }, }; -struct cam_cre_bus_rd_reg_val bus_rd_reg_value = { +struct cam_cre_bus_rd_reg_val cre100_bus_rd_reg_value = { .hw_version = 0x30000000, .irq_mask = 0x1, /* INFO_CONS_VIOLATION */ .rd_buf_done = 0x4, @@ -183,7 +184,7 @@ struct cam_cre_bus_rd_reg_val bus_rd_reg_value = { }, }; -struct cam_cre_bus_wr_reg bus_wr_reg = { +struct cam_cre_bus_wr_reg cre100_bus_wr_reg = { .hw_version = 0x00, .cgc_override = 0x08, .irq_mask_0 = 0x18, @@ -230,11 +231,11 @@ struct cam_cre_bus_wr_reg bus_wr_reg = { }; static struct cam_cre_hw cre_hw_100 = { - .top_reg_offset = &top_reg, - .top_reg_val = &top_reg_value, - .bus_wr_reg_offset = &bus_wr_reg, - .bus_wr_reg_val = &bus_wr_reg_value, - .bus_rd_reg_offset = &bus_rd_reg, - .bus_rd_reg_val = &bus_rd_reg_value, + .top_reg_offset = &cre100_top_reg, + .top_reg_val = &cre100_top_reg_value, + .bus_wr_reg_offset = &cre100_bus_wr_reg, + .bus_wr_reg_val = &cre100_bus_wr_reg_value, + .bus_rd_reg_offset = &cre100_bus_rd_reg, + .bus_rd_reg_val = &cre100_bus_rd_reg_value, }; #endif // CAM_CRE_HW_100_H diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_110.h b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_110.h new file mode 100644 index 0000000000..b284653518 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_110.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef CAM_CRE_HW_110_H +#define CAM_CRE_HW_110_H + +#include "cre_hw.h" + +#define CRE_BUS_RD_TYPE 0x1 +#define CRE_BUS_WR_TYPE 0x2 + +static struct cam_cre_top_reg cre110_top_reg = { + .hw_version = 0x000, + .hw_cap = 0x004, + .debug_0 = 0x080, + .debug_1 = 0x084, + .debug_cfg = 0x0DC, + .testbus_ctrl = 0x1F4, + .scratch_0 = 0x1F8, + .irq_status = 0x00C, + .irq_mask = 0x010, + .irq_clear = 0x014, + .irq_set = 0x018, + .irq_cmd = 0x01C, + .reset_cmd = 0x008, + .core_clk_cfg_ctrl_0 = 0x020, + .core_clk_cfg_ctrl_1 = 0x024, + .top_spare = 0x1FC, +}; + +struct cam_cre_top_reg_val cre110_top_reg_value = { + .hw_version = 0x10010000, + .hw_cap = 0x4000, + .irq_mask = 0xf, + .irq_clear = 0xf, + .irq_set = 0xf, + .irq_cmd_set = 0xf, + .irq_cmd_clear = 0xf, + .idle = 0x8, + .fe_done = 0x4, + .we_done = 0x2, + .rst_done = 0x1, + .sw_reset_cmd = 0x2, + .hw_reset_cmd = 0x1, +}; + +struct cam_cre_bus_rd_reg cre110_bus_rd_reg = { + .hw_version = 0x00, + .irq_mask = 0x04, + .irq_clear = 0x08, + .irq_cmd = 0x0C, + .irq_status = 0x10, + .input_if_cmd = 0x14, + .irq_set = 0x18, + .misr_reset = 0x1C, + .security_cfg = 0x20, + .iso_cfg = 0x24, + .iso_seed = 0x28, + .test_bus_ctrl = 0x2C, + .cons_violation = 0x30, + .ccif_violation = 0x34, + .num_clients = 1, + .rd_clients[0] = { + .core_cfg = 0x50, + .ccif_meta_data = 0x54, + .img_addr = 0x58, + .rd_width = 0x5C, + .rd_height = 0x60, + .rd_stride = 0x64, + .unpacker_cfg = 0x68, + .latency_buf_allocation = 0x7C, + .misr_cfg_0 = 0x84, + .misr_cfg_1 = 0x88, + .misr_rd_val = 0x8C, + .system_cache_cfg = 0x90, + .read_buff_cfg = 0x94, + .addr_cfg = 0x98, + .debug_status_cfg = 0xA4, + .debug_status_0 = 0xA8, + .debug_status_1 = 0xAC, + .spare = 0x38, + }, +}; + +struct cam_cre_bus_wr_reg_val cre110_bus_wr_reg_value = { + .hw_version = 0x40000000, + .cgc_override = 0x1, + .irq_mask_0 = 0xd0000101, + .irq_set_0 = 0xd0000101, + .irq_clear_0 = 0xd0000101, + .img_size_violation = 0x80000000, + .violation = 0x40000000, + .cons_violation = 0x10000000, + .comp_buf_done = 0x100, + .comp_rup_done = 0x1, + .irq_mask_1 = 0x1, + .irq_set_1 = 0x1, + .irq_clear_1 = 0x1, + .irq_status_1 = 0x1, + .irq_cmd_set = 0x10, + .irq_cmd_clear = 0x1, + .iso_en = 0x1, + .iso_en_mask = 0x1, + .misr_0_en = 0x1, + .misr_0_en_mask = 0x1, + .misr_0_samp_mode = 0x1, + .misr_0_samp_mode_mask = 0x10000, + .misr_0_id_mask = 0xff, + .misr_rd_misr_sel_mask = 0xf, + .misr_rd_word_sel_mask = 0x70, + .num_clients = 1, + .wr_clients[0] = { + .client_en = 0x1, + .client_en_mask = 0x1, + .client_en_shift = 0x0, + .auto_recovery_en = 0x1, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xffff, + .width_shift = 0x0, + .height_mask = 0xffff, + .height_shift = 0x10, + .x_init_mask = 0xff, + .stride_mask = 0xffffff, + .format_mask = 0xf, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x5, + .bw_limit_en = 0x1, + .bw_limit_en_mask = 0x1, + .bw_limit_counter_mask = 0x1fe, + .client_buf_done = 0x1, + .output_port_id = CAM_CRE_OUTPUT_IMAGE, + .wm_port_id = 0, + }, +}; + +struct cam_cre_bus_rd_reg_val cre110_bus_rd_reg_value = { + .hw_version = 0x40000000, + .irq_mask = 0x80000001, + .rd_buf_done = 0x4, + .rup_done = 0x2, + .cons_violation = 0x1, + .ccif_violation = 0x80000000, + .irq_cmd_set = 0x10, + .irq_cmd_clear = 0x1, + .static_prg = 0x8, + .static_prg_mask = 0x8, + .ica_en = 0x1, + .ica_en_mask = 0x2, + .go_cmd = 0x1, + .go_cmd_mask = 0x1, + .irq_set = 0x7, + .irq_clear = 0x7, + .misr_reset = 0x1, + .security_cfg = 0x1, + .iso_bpp_select_mask = 0x60, + .iso_pattern_select_mask = 0x6, + .iso_en = 0x1, + .iso_en_mask = 0x1, + .num_clients = 1, + .rd_clients[0] = { + .client_en = 0x1, + .ai_en = 0x1, + .ai_en_mask = 0x1000, + .ai_en_shift = 0xc, + .pix_pattern_mask = 0xfc, + .pix_pattern_shift = 0x2, + .stripe_location_mask = 0x3, + .stripe_location_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x5, + .format_mask = 0x1f, + .format_shift = 0x0, + .latency_buf_size_mask = 0xffff, + .misr_cfg_en_mask = 0x4, + .misr_cfg_samp_mode_mask = 0x3, + .x_int_mask = 0xffff, + .byte_offset_mask = 0xff, + .input_port_id = CAM_CRE_INPUT_IMAGE, + .rm_port_id = 0x0, + }, +}; + +struct cam_cre_bus_wr_reg cre110_bus_wr_reg = { + .hw_version = 0x00, + .cgc_override = 0x08, + .irq_mask_0 = 0x18, + .irq_mask_1 = 0x1C, + .irq_clear_0 = 0x20, + .irq_clear_1 = 0x24, + .irq_status_0 = 0x28, + .irq_status_1 = 0x2C, + .irq_cmd = 0x30, + .local_frame_header_cfg_0 = 0x4C, + .irq_set_0 = 0x50, + .irq_set_1 = 0x54, + .iso_cfg = 0x5C, + .violation_status = 0x64, + .image_size_violation_status = 0x70, + .perf_count_cfg_0 = 0x74, + .perf_count_cfg_1 = 0x78, + .perf_count_cfg_2 = 0x7C, + .perf_count_cfg_3 = 0x80, + .perf_count_val_0 = 0x94, + .perf_count_val_1 = 0x98, + .perf_count_val_2 = 0x9C, + .perf_count_val_3 = 0xA0, + .perf_count_status = 0xB4, + .misr_cfg_0 = 0xB8, + .misr_cfg_1 = 0xBC, + .misr_rd_sel = 0xC8, + .misr_reset = 0xCC, + .misr_val = 0xD0, + .wr_clients[0] = { + .client_cfg = 0x200, + .img_addr = 0x204, + .img_cfg_0 = 0x20C, + .img_cfg_1 = 0x210, + .img_cfg_2 = 0x214, + .packer_cfg = 0x218, + .bw_limit = 0x21C, + .system_cache_cfg = 0x268, + .addr_cfg = 0x270, + .debug_status_cfg = 0x288, + .debug_status_0 = 0x28c, + .debug_status_1 = 0x290, + }, +}; + +static struct cam_cre_hw cre_hw_110 = { + .top_reg_offset = &cre110_top_reg, + .top_reg_val = &cre110_top_reg_value, + .bus_wr_reg_offset = &cre110_bus_wr_reg, + .bus_wr_reg_val = &cre110_bus_wr_reg_value, + .bus_rd_reg_offset = &cre110_bus_rd_reg, + .bus_rd_reg_val = &cre110_bus_rd_reg_value, +}; +#endif // CAM_CRE_HW_110_H diff --git a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top/cre_top.c b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top/cre_top.c index 4e339fa169..8c59bf923e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top/cre_top.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top/cre_top.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -46,8 +47,8 @@ static int cam_cre_top_reset(struct cam_cre_hw *cre_hw_info, cam_io_w_mb(top_reg_val->irq_mask, cre_hw_info->top_reg_offset->base + top_reg->irq_mask); - /* CRE SW RESET */ - cam_io_w_mb(top_reg_val->sw_reset_cmd, + /* CRE HW RESET */ + cam_io_w_mb(top_reg_val->hw_reset_cmd, cre_hw_info->top_reg_offset->base + top_reg->reset_cmd); rc = wait_for_completion_timeout( diff --git a/qcom/opensource/camera-kernel/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c b/qcom/opensource/camera-kernel/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c index 124be99d40..aeed9b8daf 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -107,13 +108,19 @@ err: static void cam_custom_csid_component_unbind(struct device *dev, struct device *master_dev, void *data) { - struct cam_hw_intf *csid_hw_intf; + struct cam_hw_intf *csid_hw_intf = NULL; struct cam_hw_info *csid_hw_info; struct cam_ife_csid_core_info *core_info = NULL; struct platform_device *pdev = to_platform_device(dev); const struct of_device_id *match_dev = NULL; csid_hw_intf = (struct cam_hw_intf *)platform_get_drvdata(pdev); + + if (!csid_hw_intf) { + CAM_ERR(CAM_CUSTOM, "ERROR No data in csid_hw_intf"); + return; + } + csid_hw_info = csid_hw_intf->hw_priv; core_info = csid_hw_info->core_info; diff --git a/qcom/opensource/camera-kernel/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/qcom/opensource/camera-kernel/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c index 04488f0139..9c45476486 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_fd_hw_core.h" @@ -368,6 +368,13 @@ static int cam_fd_hw_util_processcmd_prestart(struct cam_hw_info *fd_hw, ((struct cam_fd_soc_private *)soc_info->soc_private)-> regbase_index[CAM_FD_REG_CORE]); + if (mem_base == -1) { + CAM_ERR(CAM_FD, "failed to get mem_base, index: %d num_reg_map: %u", + ((struct cam_fd_soc_private *)soc_info->soc_private)-> + regbase_index[CAM_FD_REG_CORE], soc_info->num_reg_map); + return -EINVAL; + } + ctx_hw_private->cdm_ops->cdm_write_changebase(cmd_buf_addr, mem_base); cmd_buf_addr += size; available_size -= (size * 4); diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/cam_icp_subdev.c b/qcom/opensource/camera-kernel/drivers/cam_icp/cam_icp_subdev.c index 35fdad4120..aa09af8564 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/cam_icp_subdev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/cam_icp_subdev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022,2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -249,10 +249,12 @@ const struct v4l2_subdev_internal_ops cam_icp_subdev_internal_ops = { .close = cam_icp_subdev_close, }; -static inline void cam_icp_subdev_clean_up(uint32_t device_idx) +static inline int cam_icp_subdev_clean_up(uint32_t device_idx) { kfree(g_icp_dev[device_idx]); g_icp_dev[device_idx] = NULL; + + return 0; } static int cam_icp_component_bind(struct device *dev, @@ -292,6 +294,7 @@ static int cam_icp_component_bind(struct device *dev, else subdev_name = cam_icp_subdev_name_arr[device_idx]; + mutex_lock(&g_dev_lock); if (g_icp_dev[device_idx]) { CAM_ERR(CAM_ICP, @@ -303,15 +306,15 @@ static int cam_icp_component_bind(struct device *dev, } mutex_unlock(&g_dev_lock); - icp_dev = kzalloc(sizeof(struct cam_icp_subdev), GFP_KERNEL); - if (!icp_dev) { - CAM_ERR(CAM_ICP, - "Unable to allocate memory for icp device:%s size:%llu", - pdev->name, sizeof(struct cam_icp_subdev)); - return -ENOMEM; - } + icp_dev = kzalloc(sizeof(struct cam_icp_subdev), GFP_KERNEL); + if (!icp_dev) { + CAM_ERR(CAM_ICP, + "Unable to allocate memory for icp device:%s size:%llu", + pdev->name, sizeof(struct cam_icp_subdev)); + return -ENOMEM; + } - mutex_lock(&g_dev_lock); + mutex_lock(&g_dev_lock); g_icp_dev[device_idx] = icp_dev; mutex_unlock(&g_dev_lock); @@ -371,6 +374,7 @@ ctx_fail: cam_icp_context_deinit(&icp_dev->ctx_icp[i]); cam_icp_hw_mgr_deinit(device_idx); hw_init_fail: + cam_node_deinit(icp_dev->node); cam_subdev_remove(&icp_dev->sd); probe_fail: cam_icp_subdev_clean_up(device_idx); diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/hfi.c b/qcom/opensource/camera-kernel/drivers/cam_icp/hfi.c index be9d70e816..133986f51c 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/hfi.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/hfi.c @@ -76,7 +76,7 @@ static void __iomem *hfi_iface_addr(struct hfi_info *hfi) static inline int hfi_get_client_info(int client_handle, struct hfi_info **hfi) { - int idx; + uint32_t idx; idx = HFI_GET_INDEX(client_handle); if (!IS_VALID_HFI_INDEX(idx)) { @@ -310,6 +310,7 @@ int hfi_read_message(int client_handle, uint32_t *pmsg, uint8_t q_id, struct hfi_q_hdr *q; uint32_t new_read_idx, size_in_words, word_diff, temp; uint32_t *read_q, *read_ptr, *write_ptr; + uint32_t size_upper_bound = 0; struct mutex *q_lock; int rc = 0; @@ -351,6 +352,15 @@ int hfi_read_message(int client_handle, uint32_t *pmsg, uint8_t q_id, q_tbl_ptr = (struct hfi_qtbl *)hfi->map.qtbl.kva; q = &q_tbl_ptr->q_hdr[q_id]; + if (q->qhdr_read_idx == q->qhdr_write_idx) { + CAM_DBG(CAM_HFI, "[%s] hfi hdl: %d Q not ready, state:%u, r idx:%u, w idx:%u", + hfi->client_name, client_handle, hfi->hfi_state, + q->qhdr_read_idx, q->qhdr_write_idx); + rc = -EIO; + goto err; + } + + size_upper_bound = q->qhdr_q_size; if (q_id == Q_MSG) read_q = (uint32_t *)hfi->map.msg_q.kva; else @@ -359,20 +369,15 @@ int hfi_read_message(int client_handle, uint32_t *pmsg, uint8_t q_id, read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx); write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx); - if (write_ptr >= read_ptr) + if (write_ptr > read_ptr) size_in_words = write_ptr - read_ptr; else { word_diff = read_ptr - write_ptr; size_in_words = q->qhdr_q_size - word_diff; } - if (size_in_words == 0) { - CAM_DBG(CAM_HFI, "[%s] hfi hdl: %d Q is empty, state:%u, r idx:%u, w idx:%u", - hfi->client_name, client_handle, hfi->hfi_state, - q->qhdr_read_idx, q->qhdr_write_idx); - rc = -ENOMSG; - goto err; - } else if (size_in_words > q->qhdr_q_size) { + if ((size_in_words == 0) || + (size_in_words > size_upper_bound)) { CAM_ERR(CAM_HFI, "[%s] Invalid HFI message packet size - 0x%08x hfi hdl:%d", hfi->client_name, size_in_words << BYTE_WORD_SHIFT, client_handle); @@ -381,9 +386,13 @@ int hfi_read_message(int client_handle, uint32_t *pmsg, uint8_t q_id, goto err; } - /* size to read from q is bounded by size of buffer */ - if (size_in_words > buf_words_size) - size_in_words = buf_words_size; + if (size_in_words > buf_words_size) { + CAM_ERR(CAM_HFI, + "[%s] hdl: %d Size of buffer: %u is smaller than size to read from queue: %u", + hfi->client_name, client_handle, buf_words_size, size_in_words); + rc = -EIO; + goto err; + } new_read_idx = q->qhdr_read_idx + size_in_words; diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_core.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_core.c index 8780e172bf..2dc0e8e258 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -473,6 +473,10 @@ int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type, case CAM_ICP_DEV_CMD_RESET: rc = cam_bps_cmd_reset(soc_info, core_info); break; + case CAM_ICP_DEV_CMD_DUMP_CLK: { + rc = cam_soc_util_dump_clk(soc_info); + break; + } default: CAM_ERR(CAM_ICP, "Invalid Cmd Type:%u", cmd_type); rc = -EINVAL; diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_dev.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_dev.c index 8dfddd452b..18b29f3a17 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/bps_hw/bps_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -205,6 +205,12 @@ static void cam_bps_component_unbind(struct device *dev, CAM_DBG(CAM_ICP, "Unbinding component: %s", pdev->name); bps_dev_intf = platform_get_drvdata(pdev); + + if (!bps_dev_intf) { + CAM_ERR(CAM_ICP, "Error No data in pdev"); + return; + } + bps_dev = bps_dev_intf->hw_priv; core_info = (struct cam_bps_device_core_info *)bps_dev->core_info; cam_cpas_unregister_client(core_info->cpas_handle); diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 28fe8d9f2b..7f580e45d9 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2329,9 +2329,28 @@ static void cam_icp_mgr_compute_fw_avg_response_time(struct cam_icp_hw_ctx_data (perf_stats->total_resp_time / perf_stats->total_requests)); } +static int cam_icp_mgr_dump_clk(struct cam_icp_hw_ctx_data *ctx_data) +{ + uint32_t i; + struct cam_hw_intf *dev_intf = NULL; + + for (i = 0; i < ctx_data->device_info->hw_dev_cnt; i++) { + dev_intf = ctx_data->device_info->dev_intf[i]; + if (!dev_intf) { + CAM_ERR(CAM_ICP, "Device intf for %s[%u] is NULL", + ctx_data->device_info->dev_name, i); + return -EINVAL; + } + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, CAM_ICP_DEV_CMD_DUMP_CLK, + NULL, 0); + } + + return 0; +} + static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) { - int i; + int i, rc; uint32_t idx, event_id; uint64_t request_id; struct cam_icp_hw_mgr *hw_mgr = NULL; @@ -2394,6 +2413,7 @@ static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) cam_icp_error_handle_id_to_type(ioconfig_ack->err_type), request_id); event_id = CAM_CTX_EVT_ID_ERROR; + rc = cam_icp_mgr_dump_clk(ctx_data); } buf_data.evt_param = cam_icp_handle_err_type_to_evt_param(ioconfig_ack->err_type); } else { @@ -2491,8 +2511,6 @@ static int cam_icp_mgr_process_msg_frame_process(uint32_t *msg_ptr) if (ioconfig_ack->err_type != CAMERAICP_SUCCESS) { cam_icp_mgr_handle_frame_process(msg_ptr, ICP_FRAME_PROCESS_FAILURE); - if (ioconfig_ack->err_type == CAMERAICP_EABORTED) - return 0; return -EIO; } @@ -2951,90 +2969,68 @@ static int cam_icp_mgr_process_fatal_error( static void cam_icp_mgr_process_dbg_buf(struct cam_icp_hw_mgr *hw_mgr) { uint32_t *msg_ptr = NULL, *pkt_ptr = NULL; - struct hfi_msg_debug *dbg_msg = NULL; - uint32_t read_in_words, remain_len, pre_remain_len = 0; - uint32_t buf_word_size = ICP_DBG_BUF_SIZE_IN_WORDS; + struct hfi_msg_debug *dbg_msg; + uint32_t read_len, size_processed = 0, debug_lvl; uint64_t timestamp = 0; - char *msg_data; + char *dbg_buf; int rc = 0; - if (!hw_mgr) { - CAM_ERR(CAM_ICP, "Invalid data"); + rc = hfi_read_message(hw_mgr->hfi_handle, hw_mgr->dbg_buf, Q_DBG, + ICP_DBG_BUF_SIZE_IN_WORDS, &read_len); + if (rc) return; - } - do { - rc = hfi_read_message(hw_mgr->hfi_handle, - hw_mgr->dbg_buf + (pre_remain_len >> BYTE_WORD_SHIFT), - Q_DBG, buf_word_size, &read_in_words); - if (rc) - break; - - remain_len = pre_remain_len + (read_in_words << BYTE_WORD_SHIFT); - pre_remain_len = 0; - msg_ptr = (uint32_t *)hw_mgr->dbg_buf; - buf_word_size = ICP_DBG_BUF_SIZE_IN_WORDS; - - while (remain_len) { - pkt_ptr = msg_ptr; - if ((remain_len < sizeof(struct hfi_msg_debug)) || - (remain_len < pkt_ptr[ICP_PACKET_SIZE])) { - /* - * MSG is broken into two parts, need to read from dbg q again - * to complete the msg and get the remaining packets. Copy - * the remain data to start of buffer and shift buffer ptr to - * after the remaining data ends to read from queue. - */ - memcpy(hw_mgr->dbg_buf, msg_ptr, remain_len); - pre_remain_len = remain_len; - buf_word_size -= (pre_remain_len >> BYTE_WORD_SHIFT); - break; - } - - if (pkt_ptr[ICP_PACKET_TYPE] == HFI_MSG_SYS_DEBUG) { - dbg_msg = (struct hfi_msg_debug *)pkt_ptr; - msg_data = (char *)&dbg_msg->msg_data; - timestamp = ((((uint64_t)(dbg_msg->timestamp_hi) << 32) - | dbg_msg->timestamp_lo) >> 16); - trace_cam_icp_fw_dbg(msg_data, timestamp/2, - hw_mgr->hw_mgr_name); - if (!hw_mgr->icp_dbg_lvl) - CAM_INFO(CAM_ICP, "[%s]: FW_DBG:%s", - hw_mgr->hw_mgr_name, msg_data); - } - - remain_len -= pkt_ptr[ICP_PACKET_SIZE]; - if (remain_len > 0) - msg_ptr += (pkt_ptr[ICP_PACKET_SIZE] >> BYTE_WORD_SHIFT); - else - break; + msg_ptr = (uint32_t *)hw_mgr->dbg_buf; + debug_lvl = hw_mgr->icp_dbg_lvl; + while (true) { + pkt_ptr = msg_ptr; + if (pkt_ptr[ICP_PACKET_TYPE] == HFI_MSG_SYS_DEBUG) { + dbg_msg = (struct hfi_msg_debug *)pkt_ptr; + dbg_buf = (char *)&dbg_msg->msg_data; + timestamp = ((((uint64_t)(dbg_msg->timestamp_hi) << 32) + | dbg_msg->timestamp_lo) >> 16); + trace_cam_icp_fw_dbg(dbg_buf, timestamp/2, + hw_mgr->hw_mgr_name); + if (!debug_lvl) + CAM_INFO(CAM_ICP, "[%s]: FW_DBG:%s", + hw_mgr->hw_mgr_name, dbg_buf); } - - /* Repeat reading if drain buffer is insufficient to read all MSGs at once */ - } while (read_in_words >= buf_word_size); + size_processed += (pkt_ptr[ICP_PACKET_SIZE] >> + BYTE_WORD_SHIFT); + if (size_processed >= read_len) + return; + msg_ptr += (pkt_ptr[ICP_PACKET_SIZE] >> + BYTE_WORD_SHIFT); + } } static int cam_icp_process_msg_pkt_type( struct cam_icp_hw_mgr *hw_mgr, - uint32_t *msg_ptr) + uint32_t *msg_ptr, + uint32_t *msg_processed_len) { int rc = 0; + int size_processed = 0; switch (msg_ptr[ICP_PACKET_TYPE]) { case HFI_MSG_SYS_INIT_DONE: CAM_DBG(CAM_ICP, "[%s] received SYS_INIT_DONE", hw_mgr->hw_mgr_name); complete(&hw_mgr->icp_complete); + size_processed = ( + (struct hfi_msg_init_done *)msg_ptr)->size; break; case HFI_MSG_SYS_PC_PREP_DONE: CAM_DBG(CAM_ICP, "[%s] HFI_MSG_SYS_PC_PREP_DONE is received\n", hw_mgr->hw_mgr_name); complete(&hw_mgr->icp_complete); + size_processed = sizeof(struct hfi_msg_pc_prep_done); break; case HFI_MSG_SYS_PING_ACK: CAM_DBG(CAM_ICP, "[%s] received SYS_PING_ACK", hw_mgr->hw_mgr_name); rc = cam_icp_mgr_process_msg_ping_ack(msg_ptr); + size_processed = sizeof(struct hfi_msg_ping_ack); break; case HFI_MSG_IPEBPS_CREATE_HANDLE_ACK: @@ -3042,27 +3038,36 @@ static int cam_icp_process_msg_pkt_type( CAM_DBG(CAM_ICP, "[%s] received IPE/BPS/OFE CREATE_HANDLE_ACK", hw_mgr->hw_mgr_name); rc = cam_icp_mgr_process_msg_create_handle(msg_ptr); + size_processed = sizeof(struct hfi_msg_create_handle_ack); break; case HFI_MSG_IPEBPS_ASYNC_COMMAND_INDIRECT_ACK: CAM_DBG(CAM_ICP, "[%s] received IPE/BPS ASYNC_INDIRECT_ACK", hw_mgr->hw_mgr_name); rc = cam_icp_mgr_process_ipebps_indirect_ack_msg(msg_ptr); + size_processed = ( + (struct hfi_msg_dev_async_ack *)msg_ptr)->size; break; case HFI_MSG_OFE_ASYNC_COMMAND_ACK: CAM_DBG(CAM_ICP, "[%s] received OFE ASYNC COMMAND ACK", hw_mgr->hw_mgr_name); rc = cam_icp_mgr_process_ofe_indirect_ack_msg(msg_ptr); + size_processed = ( + (struct hfi_msg_dev_async_ack *)msg_ptr)->size; break; case HFI_MSG_IPEBPS_ASYNC_COMMAND_DIRECT_ACK: CAM_DBG(CAM_ICP, "[%s] received ASYNC_DIRECT_ACK", hw_mgr->hw_mgr_name); rc = cam_icp_mgr_process_direct_ack_msg(msg_ptr); + size_processed = ( + (struct hfi_msg_dev_async_ack *)msg_ptr)->size; break; case HFI_MSG_EVENT_NOTIFY: CAM_DBG(CAM_ICP, "[%s] received EVENT_NOTIFY", hw_mgr->hw_mgr_name); + size_processed = ( + (struct hfi_msg_event_notify *)msg_ptr)->size; rc = cam_icp_mgr_process_fatal_error(hw_mgr, msg_ptr); if (rc) CAM_ERR(CAM_ICP, "[%s] failed in processing evt notify", @@ -3072,133 +3077,24 @@ static int cam_icp_process_msg_pkt_type( case HFI_MSG_DBG_SYNX_TEST: CAM_DBG(CAM_ICP, "received DBG_SYNX_TEST"); + size_processed = sizeof(struct hfi_cmd_synx_test_payload); complete(&hw_mgr->icp_complete); break; - default: CAM_ERR(CAM_ICP, "[%s] invalid msg : %u", hw_mgr->hw_mgr_name, msg_ptr[ICP_PACKET_TYPE]); rc = -EINVAL; } + *msg_processed_len = size_processed; return rc; } -static int cam_icp_get_msg_pkt_size( - struct cam_icp_hw_mgr *hw_mgr, - uint32_t *msg_ptr, - uint32_t *pkt_size) +static int32_t cam_icp_mgr_process_msg(void *priv, void *data) { - switch (msg_ptr[ICP_PACKET_TYPE]) { - case HFI_MSG_SYS_INIT_DONE: - *pkt_size = ( - (struct hfi_msg_init_done *)msg_ptr)->size; - break; - case HFI_MSG_SYS_PC_PREP_DONE: - *pkt_size = sizeof(struct hfi_msg_pc_prep_done); - break; - case HFI_MSG_SYS_PING_ACK: - *pkt_size = sizeof(struct hfi_msg_ping_ack); - break; - case HFI_MSG_IPEBPS_CREATE_HANDLE_ACK: - case HFI_MSG_OFE_CREATE_HANDLE_ACK: - *pkt_size = sizeof(struct hfi_msg_create_handle_ack); - break; - case HFI_MSG_IPEBPS_ASYNC_COMMAND_INDIRECT_ACK: - *pkt_size = ( - (struct hfi_msg_dev_async_ack *)msg_ptr)->size; - break; - case HFI_MSG_OFE_ASYNC_COMMAND_ACK: - *pkt_size = ( - (struct hfi_msg_dev_async_ack *)msg_ptr)->size; - break; - case HFI_MSG_IPEBPS_ASYNC_COMMAND_DIRECT_ACK: - *pkt_size = ( - (struct hfi_msg_dev_async_ack *)msg_ptr)->size; - break; - case HFI_MSG_EVENT_NOTIFY: - *pkt_size = ( - (struct hfi_msg_event_notify *)msg_ptr)->size; - break; - case HFI_MSG_DBG_SYNX_TEST: - *pkt_size = sizeof(struct hfi_cmd_synx_test_payload); - break; - default: - CAM_ERR(CAM_ICP, "[%s] invalid msg : %u", - hw_mgr->hw_mgr_name, msg_ptr[ICP_PACKET_TYPE]); - return -EINVAL; - } - - return 0; -} - -static int cam_icp_mgr_process_msg(struct cam_icp_hw_mgr *hw_mgr) -{ - uint32_t msg_pkt_size, read_in_words; - uint32_t remain_len, pre_remain_len = 0; + uint32_t read_len, msg_processed_len; uint32_t *msg_ptr = NULL; - uint32_t buf_word_size = ICP_MSG_BUF_SIZE_IN_WORDS; - int rc = 0; - - if (!hw_mgr) { - CAM_ERR(CAM_ICP, "Invalid data"); - return -EINVAL; - } - - do { - rc = hfi_read_message(hw_mgr->hfi_handle, - hw_mgr->msg_buf + (pre_remain_len >> BYTE_WORD_SHIFT), - Q_MSG, buf_word_size, &read_in_words); - if (rc) { - if (rc != -ENOMSG) - CAM_DBG(CAM_ICP, "Unable to read msg q rc %d", rc); - break; - } - - remain_len = pre_remain_len + (read_in_words << BYTE_WORD_SHIFT); - pre_remain_len = 0; - msg_ptr = (uint32_t *)hw_mgr->msg_buf; - buf_word_size = ICP_MSG_BUF_SIZE_IN_WORDS; - - while (remain_len) { - rc = cam_icp_get_msg_pkt_size(hw_mgr, msg_ptr, &msg_pkt_size); - if (rc) { - CAM_ERR(CAM_ICP, "Failed to get pkt size"); - break; - } - - if (remain_len < msg_pkt_size) { - /* - * MSG is broken into two parts, need to read from msg q again - * to complete the msg and get the remaining packets. Copy - * the remain data to start of buffer and shift buffer ptr to - * after the remaining data ends to read from queue. - */ - memcpy(hw_mgr->msg_buf, msg_ptr, remain_len); - pre_remain_len = remain_len; - buf_word_size -= (pre_remain_len >> BYTE_WORD_SHIFT); - break; - } - - rc = cam_icp_process_msg_pkt_type(hw_mgr, msg_ptr); - if (rc) - CAM_ERR(CAM_ICP, "Failed to process MSG"); - - remain_len -= msg_pkt_size; - if (remain_len > 0) { - msg_ptr += (msg_pkt_size >> BYTE_WORD_SHIFT); - msg_pkt_size = 0; - } else - break; - } - /* Repeat reading if drain buffer is insufficient to read all MSGs at once */ - } while (read_in_words >= buf_word_size); - - return rc; -} - -static int32_t cam_icp_mgr_process_cb(void *priv, void *data) -{ struct hfi_msg_work_data *task_data; + struct hfi_msg_work_data *task_data; struct cam_icp_hw_mgr *hw_mgr; int rc = 0; @@ -3210,9 +3106,33 @@ static int32_t cam_icp_mgr_process_cb(void *priv, void *data) task_data = data; hw_mgr = priv; - rc = cam_icp_mgr_process_msg(hw_mgr); - if (rc && (rc != -ENOMSG)) - CAM_ERR(CAM_ICP, "Failed to process MSG"); + rc = hfi_read_message(hw_mgr->hfi_handle, hw_mgr->msg_buf, Q_MSG, + ICP_MSG_BUF_SIZE_IN_WORDS, &read_len); + if (rc) { + CAM_DBG(CAM_ICP, "Unable to read msg q rc %d", rc); + } else { + read_len = read_len << BYTE_WORD_SHIFT; + msg_ptr = (uint32_t *)hw_mgr->msg_buf; + while (true) { + cam_icp_process_msg_pkt_type(hw_mgr, msg_ptr, + &msg_processed_len); + + if (!msg_processed_len) { + CAM_ERR(CAM_ICP, "Failed to read"); + rc = -EINVAL; + break; + } + + read_len -= msg_processed_len; + if (read_len > 0) { + msg_ptr += (msg_processed_len >> + BYTE_WORD_SHIFT); + msg_processed_len = 0; + } else { + break; + } + } + } cam_icp_mgr_process_dbg_buf(hw_mgr); @@ -3250,7 +3170,7 @@ static int32_t cam_icp_hw_mgr_cb(void *data, bool recover) task_data->data = hw_mgr; task_data->recover = recover; task_data->type = ICP_WORKQ_TASK_MSG_TYPE; - task->process_cb = cam_icp_mgr_process_cb; + task->process_cb = cam_icp_mgr_process_msg; rc = cam_req_mgr_workq_enqueue_task(task, hw_mgr, CRM_TASK_PRIORITY_0); spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); @@ -4728,7 +4648,7 @@ static int cam_icp_mgr_device_init(struct cam_icp_hw_mgr *hw_mgr) hw_dev_deinit: for (; i >= 0; i--) { dev_info = &hw_mgr->dev_info[i]; - j = (j == -1) ? dev_info->hw_dev_cnt : (j - 1); + j = (j == -1) ? (dev_info->hw_dev_cnt - 1) : (j - 1); for (; j >= 0; j--) { dev_intf = dev_info->dev_intf[j]; dev_intf->hw_ops.deinit(dev_intf->hw_priv, NULL, 0); @@ -5473,7 +5393,8 @@ static bool cam_icp_mgr_is_valid_outconfig(struct cam_packet *packet) packet->io_configs_offset/4); for (i = 0 ; i < packet->num_io_configs; i++) - if (io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) + if ((io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) || + (io_cfg_ptr[i].direction == CAM_BUF_IN_OUT)) num_out_map_entries++; if (num_out_map_entries <= CAM_MAX_OUT_RES) { @@ -5630,13 +5551,20 @@ static int cam_icp_mgr_process_io_cfg(struct cam_icp_hw_mgr *hw_mgr, if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) { sync_in_obj[j++] = io_cfg_ptr[i].fence; prepare_args->num_in_map_entries++; - } else { + } else if ((io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) || + (io_cfg_ptr[i].direction == CAM_BUF_IN_OUT)) { prepare_args->out_map_entries[k].sync_id = io_cfg_ptr[i].fence; prepare_args->out_map_entries[k].resource_handle = io_cfg_ptr[i].resource_type; k++; prepare_args->num_out_map_entries++; + } else { + CAM_ERR(CAM_ICP, "dir: %d, max_out:%u, out %u", + io_cfg_ptr[i].direction, + prepare_args->max_out_map_entries, + prepare_args->num_out_map_entries); + return -EINVAL; } CAM_DBG(CAM_REQ, @@ -5864,6 +5792,11 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, switch (blob_type) { case CAM_ICP_CMD_GENERIC_BLOB_CLK: + if (index < 0) { + CAM_ERR(CAM_ICP, "Invalid index %d", index); + return -EINVAL; + } + CAM_WARN_RATE_LIMIT_CUSTOM(CAM_PERF, 300, 1, "Using deprecated blob type GENERIC_BLOB_CLK"); if (blob_size != sizeof(struct cam_icp_clk_bw_request)) { @@ -5895,6 +5828,11 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, break; case CAM_ICP_CMD_GENERIC_BLOB_CLK_V2: + if (index < 0) { + CAM_ERR(CAM_ICP, "Invalid index %d", index); + return -EINVAL; + } + if (blob_size < sizeof(struct cam_icp_clk_bw_request_v2)) { CAM_ERR(CAM_ICP, "%s: Mismatch blob size %d expected %lu", ctx_data->ctx_id_string, @@ -6042,6 +5980,11 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, break; case CAM_ICP_CMD_GENERIC_BLOB_PRESIL_HANGDUMP: + if (index < 0) { + CAM_ERR(CAM_ICP, "Invalid index %d", index); + return -EINVAL; + } + if (cam_presil_mode_enabled()) { cmd_mem_regions = (struct cam_cmd_mem_regions *)blob_data; if (cmd_mem_regions->num_regions <= 0) { @@ -6261,10 +6204,10 @@ static int cam_icp_mgr_prepare_hw_update(void *hw_mgr_priv, packet = prepare_args->packet; - if (cam_packet_util_validate_packet(packet, prepare_args->remain_len)) { - mutex_unlock(&ctx_data->ctx_mutex); - return -EINVAL; - } + if (cam_packet_util_validate_packet(packet, prepare_args->remain_len)) { + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } rc = cam_icp_mgr_pkt_validation(ctx_data, packet); if (rc) { @@ -6653,7 +6596,7 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) *mgr_addr++ = hw_mgr->icp_booted; *mgr_addr++ = hw_mgr->icp_resumed; *mgr_addr++ = hw_mgr->disable_ubwc_comp; - memcpy(mgr_addr, &hw_mgr->dev_info, sizeof(hw_mgr->dev_info)); + memcpy(mgr_addr, &hw_mgr->dev_info, sizeof(struct cam_icp_hw_device_info)); mgr_addr += sizeof(hw_mgr->dev_info); *mgr_addr++ = hw_mgr->icp_pc_flag; *mgr_addr++ = hw_mgr->dev_pc_flag; @@ -7686,7 +7629,7 @@ static int cam_icp_mgr_alloc_devs(struct device_node *np, struct cam_icp_hw_mgr struct cam_hw_intf **alloc_devices = NULL; int rc, i; enum cam_icp_hw_type icp_hw_type; - uint32_t num = 0, num_cpas_mask = 0, cpas_hw_mask[MAX_HW_CAPS_MASK] = {0}; + uint32_t num = 0, mask = 0, num_cpas_mask = 0, cpas_hw_mask[MAX_HW_CAPS_MASK] = {0}; rc = cam_icp_alloc_processor_devs(np, &icp_hw_type, &alloc_devices, hw_dev_cnt); if (rc) { @@ -7715,6 +7658,11 @@ static int cam_icp_mgr_alloc_devs(struct device_node *np, struct cam_icp_hw_mgr devices[icp_hw_type] = alloc_devices; hw_mgr->hw_cap_mask |= BIT(icp_hw_type); num_cpas_mask = max(num_cpas_mask, (uint32_t)(ICP_CAPS_MASK_IDX + 1)); + + rc = of_property_read_u32(np, "icp-mask", &mask); + if (!rc) + icp_cpas_mask[hw_mgr->hw_mgr_id] = mask; + cpas_hw_mask[ICP_CAPS_MASK_IDX] |= icp_cpas_mask[hw_mgr->hw_mgr_id]; rc = of_property_read_u32(np, "num-ipe", &num); @@ -7730,7 +7678,12 @@ static int cam_icp_mgr_alloc_devs(struct device_node *np, struct cam_icp_hw_mgr devices[CAM_ICP_DEV_IPE] = alloc_devices; hw_mgr->hw_cap_mask |= BIT(CAM_ICP_DEV_IPE); num_cpas_mask = max(num_cpas_mask, (uint32_t)(IPE_CAPS_MASK_IDX + 1)); - cpas_hw_mask[IPE_CAPS_MASK_IDX] |= CPAS_TITAN_IPE0_CAP_BIT; + + rc = of_property_read_u32(np, "ipe0-mask", &mask); + if (!rc) + cpas_hw_mask[IPE_CAPS_MASK_IDX] |= mask; + else + cpas_hw_mask[IPE_CAPS_MASK_IDX] |= CPAS_TITAN_IPE0_CAP_BIT; } rc = of_property_read_u32(np, "num-bps", &num); @@ -7746,7 +7699,12 @@ static int cam_icp_mgr_alloc_devs(struct device_node *np, struct cam_icp_hw_mgr devices[CAM_ICP_DEV_BPS] = alloc_devices; hw_mgr->hw_cap_mask |= BIT(CAM_ICP_DEV_BPS); num_cpas_mask = max(num_cpas_mask, (uint32_t)(BPS_CAPS_MASK_IDX + 1)); - cpas_hw_mask[BPS_CAPS_MASK_IDX] |= CPAS_BPS_BIT; + + rc = of_property_read_u32(np, "bps-mask", &mask); + if (!rc) + cpas_hw_mask[BPS_CAPS_MASK_IDX] |= mask; + else + cpas_hw_mask[BPS_CAPS_MASK_IDX] |= CPAS_BPS_BIT; } rc = of_property_read_u32(np, "num-ofe", &num); @@ -8205,7 +8163,7 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, memset(hw_mgr_intf, 0, sizeof(struct cam_hw_mgr_intf)); - hw_mgr = vzalloc(sizeof(struct cam_icp_hw_mgr)); + hw_mgr = kzalloc(sizeof(struct cam_icp_hw_mgr), GFP_KERNEL); if (!hw_mgr) return -ENOMEM; @@ -8354,7 +8312,7 @@ destroy_mutex: kfree(hw_mgr->ctx_data[i].hfi_frame_process.hangdump_mem_regions); } free_hw_mgr: - vfree(hw_mgr); + kfree(hw_mgr); return rc; } @@ -8384,6 +8342,6 @@ void cam_icp_hw_mgr_deinit(int device_idx) kfree(hw_mgr->ctx_data[i].hfi_frame_process.hangdump_mem_regions); } - vfree(hw_mgr); + kfree(hw_mgr); g_icp_hw_mgr[device_idx] = NULL; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h index b1472bfdbe..f5a5d51b8e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h @@ -44,7 +44,7 @@ /* size of buffer to drain from msg/dbq queue */ #define ICP_MSG_BUF_SIZE_IN_WORDS 512 -#define ICP_DBG_BUF_SIZE_IN_WORDS 5120 +#define ICP_DBG_BUF_SIZE_IN_WORDS 25600 #define ICP_OVER_CLK_THRESHOLD 5 #define ICP_TWO_DEV_BW_SHARE_RATIO 2 diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_icp_hw_intf.h b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_icp_hw_intf.h index aaca058511..5859733c3d 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_icp_hw_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_icp_hw_intf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef CAM_ICP_HW_INTF_H @@ -55,6 +55,7 @@ enum cam_icp_dev_cmd_type { CAM_ICP_DEV_CMD_UPDATE_CLK, CAM_ICP_DEV_CMD_DISABLE_CLK, CAM_ICP_DEV_CMD_RESET, + CAM_ICP_DEV_CMD_DUMP_CLK, CAM_ICP_DEV_CMD_MAX }; diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_proc_common.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_proc_common.c index 866c3d103c..b7728529d7 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_proc_common.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_proc_common.c @@ -195,14 +195,8 @@ int cam_icp_proc_mini_dump(struct cam_icp_hw_dump_args *args, static int cam_icp_proc_validate_ubwc_cfg(struct cam_icp_ubwc_cfg *ubwc_cfg, uint32_t ubwc_cfg_dev_mask) { - uint32_t found_ubwc_cfg_mask; + uint32_t found_ubwc_cfg_mask = ubwc_cfg->found_ubwc_cfg_mask; - if (!ubwc_cfg) { - CAM_ERR(CAM_ICP, "ubwc_cfg is NULL"); - return -ENODATA; - } - - found_ubwc_cfg_mask = ubwc_cfg->found_ubwc_cfg_mask; if ((ubwc_cfg_dev_mask & BIT(CAM_ICP_DEV_IPE)) && !(found_ubwc_cfg_mask & BIT(CAM_ICP_DEV_IPE))) { CAM_ERR(CAM_ICP, "IPE does not have UBWC cfg value"); diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_dev.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_dev.c index 579383626f..a305a2f0c7 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -212,6 +212,12 @@ static void cam_icp_v1_component_unbind(struct device *dev, struct platform_device *pdev = to_platform_device(dev); icp_v1_dev_intf = platform_get_drvdata(pdev); + + if (!icp_v1_dev_intf) { + CAM_ERR(CAM_ICP, "Error No data in pdev"); + return; + } + icp_v1_dev = icp_v1_dev_intf->hw_priv; core_info = (struct cam_icp_v1_device_core_info *)icp_v1_dev->core_info; diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_dev.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_dev.c index 483812556a..41c5ff6f36 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -165,8 +165,17 @@ static void cam_icp_v2_component_unbind(struct device *dev, struct device *mdev, void *data) { struct platform_device *pdev = to_platform_device(dev); - struct cam_hw_intf *icp_v2_intf = platform_get_drvdata(pdev); - struct cam_hw_info *icp_v2_info = icp_v2_intf->hw_priv; + struct cam_hw_intf *icp_v2_intf = NULL; + struct cam_hw_info *icp_v2_info = NULL; + + icp_v2_intf = platform_get_drvdata(pdev); + + if (!icp_v2_intf) { + CAM_ERR(CAM_ICP, "Error No data in pdev"); + return; + } + + icp_v2_info = icp_v2_intf->hw_priv; cam_icp_v2_cpas_unregister(icp_v2_intf); cam_icp_soc_resources_deinit(&icp_v2_info->soc_info); diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h index fcf0759f18..d15b5df3a3 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h @@ -21,7 +21,7 @@ #define CAM_ICP_BW_BYTES_VOTE 40000000 -#define CAM_ICP_CTX_MAX 64 +#define CAM_ICP_CTX_MAX 54 #define CPAS_IPE1_BIT 0x2000 diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c index 415e10b7b1..55ad15aec9 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -465,6 +465,10 @@ int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type, case CAM_ICP_DEV_CMD_RESET: rc = cam_ipe_cmd_reset(soc_info, core_info); break; + case CAM_ICP_DEV_CMD_DUMP_CLK: { + rc = cam_soc_util_dump_clk(soc_info); + break; + } default: CAM_ERR(CAM_ICP, "Invalid Cmd Type:%u", cmd_type); rc = -EINVAL; diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c index 99ac506dc6..f527d4f113 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c @@ -188,6 +188,12 @@ static void cam_ipe_component_unbind(struct device *dev, CAM_DBG(CAM_ICP, "Unbinding component: %s", pdev->name); ipe_dev_intf = platform_get_drvdata(pdev); + + if (!ipe_dev_intf) { + CAM_ERR(CAM_ICP, "Error No data in pdev"); + return; + } + ipe_dev = ipe_dev_intf->hw_priv; core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info; cam_cpas_unregister_client(core_info->cpas_handle); diff --git a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.c b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.c index baa5828b9f..f73046ac77 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.c @@ -184,6 +184,12 @@ static void cam_ofe_component_unbind(struct device *dev, CAM_DBG(CAM_ICP, "Unbinding component: %s", pdev->name); ofe_dev_intf = platform_get_drvdata(pdev); + + if (!ofe_dev_intf) { + CAM_ERR(CAM_ICP, "Error No data in pdev"); + return; + } + ofe_dev = ofe_dev_intf->hw_priv; core_info = (struct cam_ofe_device_core_info *)ofe_dev->core_info; cam_cpas_unregister_client(core_info->cpas_handle); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.c b/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.c index 3e2b44764c..e6b87cca98 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -23,6 +23,7 @@ #include "cam_req_mgr_debug.h" #include "cam_cpas_api.h" #include "cam_ife_hw_mgr.h" +#include "cam_subdev.h" static const char isp_dev_name[] = "cam-isp"; @@ -36,6 +37,8 @@ static int cam_isp_context_dump_requests(void *data, void *pf_args); static int cam_isp_context_hw_recovery(void *priv, void *data); +static int cam_isp_context_handle_message(void *context, + uint32_t msg_type, void *data); static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, struct cam_start_stop_dev_cmd *cmd); @@ -68,6 +71,8 @@ static const char *__cam_isp_evt_val_to_type( return "RUP"; case CAM_ISP_CTX_EVENT_BUFDONE: return "BUFDONE"; + case CAM_ISP_CTX_EVENT_SHUTTER: + return "SHUTTER_NOTIFICATION"; default: return "CAM_ISP_EVENT_INVALID"; } @@ -76,7 +81,8 @@ static const char *__cam_isp_evt_val_to_type( static void __cam_isp_ctx_update_event_record( struct cam_isp_context *ctx_isp, enum cam_isp_ctx_event event, - struct cam_ctx_request *req) + struct cam_ctx_request *req, + void *event_data) { int iterator = 0; ktime_t cur_time; @@ -90,6 +96,7 @@ static void __cam_isp_ctx_update_event_record( case CAM_ISP_CTX_EVENT_EPOCH: case CAM_ISP_CTX_EVENT_RUP: case CAM_ISP_CTX_EVENT_BUFDONE: + case CAM_ISP_CTX_EVENT_SHUTTER: break; case CAM_ISP_CTX_EVENT_SUBMIT: case CAM_ISP_CTX_EVENT_APPLY: @@ -114,6 +121,25 @@ static void __cam_isp_ctx_update_event_record( ctx_isp->dbg_monitors.event_record[event][iterator].req_id = 0; } ctx_isp->dbg_monitors.event_record[event][iterator].timestamp = cur_time; + + if (event_data == NULL) + return; + /* Update event specific data */ + ctx_isp->dbg_monitors.event_record[event][iterator].event_type = event; + if (event == CAM_ISP_CTX_EVENT_SHUTTER) { + ctx_isp->dbg_monitors.event_record[event][iterator].req_id = + ((struct shutter_event *)event_data)->req_id; + ctx_isp->dbg_monitors.event_record[event][iterator].event.shutter_event.req_id = + ((struct shutter_event *)event_data)->req_id; + ctx_isp->dbg_monitors.event_record[event][iterator].event.shutter_event.status = + ((struct shutter_event *)event_data)->status; + ctx_isp->dbg_monitors.event_record[event][iterator].event.shutter_event.frame_id = + ((struct shutter_event *)event_data)->frame_id; + ctx_isp->dbg_monitors.event_record[event][iterator].event.shutter_event.boot_ts = + ((struct shutter_event *)event_data)->boot_ts; + ctx_isp->dbg_monitors.event_record[event][iterator].event.shutter_event.sof_ts = + ((struct shutter_event *)event_data)->sof_ts; + } } static int __cam_isp_ctx_handle_sof_freeze_evt( @@ -187,12 +213,29 @@ static int __cam_isp_ctx_print_event_record(struct cam_isp_context *ctx_isp) len = 0; memset(buf, 0, CAM_ISP_CONTEXT_DBG_BUF_LEN); for (j = 0; j < num_entries; j++) { - record = &ctx_isp->dbg_monitors.event_record[i][index]; ts = ktime_to_timespec64(record->timestamp); - len += scnprintf(buf + len, CAM_ISP_CONTEXT_DBG_BUF_LEN - len, - "%llu[%lld:%06lld] ", record->req_id, ts.tv_sec, - ts.tv_nsec / NSEC_PER_USEC); + if (len >= CAM_ISP_CONTEXT_DBG_BUF_LEN) { + CAM_WARN(CAM_ISP, "Overshooting buffer length %llu", len); + break; + } + if (record->event_type != CAM_ISP_CTX_EVENT_SHUTTER) + len += scnprintf(buf + len, CAM_ISP_CONTEXT_DBG_BUF_LEN - len, + "%llu[%lld:%06lld] ", record->req_id, ts.tv_sec, + ts.tv_nsec / NSEC_PER_USEC); + else + /* + * Output format + * req Id[timestamp] status frmId softs bootts + */ + len += scnprintf(buf + len, (CAM_ISP_CONTEXT_DBG_BUF_LEN) - len, + "%llu[%lld:%06lld] [%d %lld %llu %llu] | ", + record->req_id, ts.tv_sec, + ts.tv_nsec / NSEC_PER_USEC, + record->event.shutter_event.status, + record->event.shutter_event.frame_id, + record->event.shutter_event.sof_ts, + record->event.shutter_event.boot_ts); index = (index + 1) % CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES; } @@ -243,9 +286,8 @@ static int __cam_isp_ctx_dump_event_record( return -ENOSPC; } - min_len = sizeof(struct cam_isp_context_dump_header) + - ((num_entries * CAM_ISP_CTX_DUMP_EVENT_NUM_WORDS) * - sizeof(uint64_t)); + min_len = (sizeof(struct cam_isp_context_dump_header) + + (CAM_ISP_CTX_DUMP_EVENT_NUM_WORDS * sizeof(uint64_t))) * num_entries; remain_len = dump_args->buf_len - dump_args->offset; if (remain_len < min_len) { @@ -1052,7 +1094,7 @@ static int __cam_isp_ctx_enqueue_request_in_order( } ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_SUBMIT, req); + CAM_ISP_CTX_EVENT_SUBMIT, req, NULL); if (lock) spin_unlock_bh(&ctx->lock); return 0; @@ -1281,6 +1323,9 @@ static const char *__cam_isp_tfe_resource_handle_id_to_type( case CAM_ISP_TFE_OUT_RES_DS4: return "TFE_DS_4"; case CAM_ISP_TFE_OUT_RES_DS16: return "TFE_DS_16"; case CAM_ISP_TFE_OUT_RES_AI: return "TFE_AI"; + case CAM_ISP_TFE_OUT_RES_PD_LCR_STATS: return "TFE_LCR_STATS"; + case CAM_ISP_TFE_OUT_RES_PD_PREPROCESSED: return "TFE_PD_PREPROCESSED"; + case CAM_ISP_TFE_OUT_RES_PD_PARSED: return "TFE_PD_PARSED"; /* Handle invalid type */ default: return "Invalid_Resource_Type"; } @@ -1338,24 +1383,6 @@ static uint64_t __cam_isp_ctx_get_event_ts(uint32_t evt_id, void *evt_data) return ts; } -static int __cam_isp_ctx_get_path_timestamp(struct cam_context *ctx) -{ - struct cam_hw_cmd_args hw_cmd_args; - struct cam_isp_hw_cmd_args isp_hw_cmd_args; - int rc; - - hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; - hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; - hw_cmd_args.u.internal_args = &isp_hw_cmd_args; - - isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_GET_PATH_SOF_TS; - rc = ctx->hw_mgr_intf->hw_cmd(ctx->ctxt_to_hw_map, &hw_cmd_args); - if (rc) - return rc; - - return 0; -} - static int __cam_isp_ctx_get_hw_timestamp(struct cam_context *ctx, uint64_t *prev_ts, uint64_t *curr_ts, uint64_t *boot_ts) { @@ -1465,7 +1492,7 @@ static int __cam_isp_ctx_recover_sof_timestamp(struct cam_context *ctx, uint64_t static void __cam_isp_ctx_send_sof_boot_timestamp( struct cam_isp_context *ctx_isp, uint64_t request_id, - uint32_t sof_event_status) + uint32_t sof_event_status, struct shutter_event *shutter_event) { struct cam_req_mgr_message req_msg; @@ -1481,6 +1508,10 @@ static void __cam_isp_ctx_send_sof_boot_timestamp( "request id:%lld frame number:%lld boot time stamp:0x%llx status:%u", request_id, ctx_isp->frame_id, ctx_isp->boot_timestamp, sof_event_status); + shutter_event->frame_id = ctx_isp->frame_id; + shutter_event->req_id = request_id; + shutter_event->boot_ts = ctx_isp->boot_timestamp; + shutter_event->sof_ts = ctx_isp->sof_timestamp_val; if (cam_req_mgr_notify_message(&req_msg, V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS, @@ -1488,10 +1519,14 @@ static void __cam_isp_ctx_send_sof_boot_timestamp( CAM_ERR(CAM_ISP, "Error in notifying the boot time for req id:%lld", request_id); + + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_SHUTTER, NULL, shutter_event); } static void __cam_isp_ctx_send_unified_timestamp( - struct cam_isp_context *ctx_isp, uint64_t request_id) + struct cam_isp_context *ctx_isp, uint64_t request_id, + struct shutter_event *shutter_event) { struct cam_req_mgr_message req_msg; @@ -1509,12 +1544,18 @@ static void __cam_isp_ctx_send_unified_timestamp( boot time stamp:0x%llx", ctx_isp->base->link_hdl, request_id, ctx_isp->frame_id, ctx_isp->sof_timestamp_val,ctx_isp->base->ctx_id, ctx_isp->boot_timestamp); + shutter_event->frame_id = ctx_isp->frame_id; + shutter_event->req_id = request_id; + shutter_event->boot_ts = ctx_isp->boot_timestamp; + shutter_event->sof_ts = ctx_isp->sof_timestamp_val; if (cam_req_mgr_notify_message(&req_msg, V4L_EVENT_CAM_REQ_MGR_SOF_UNIFIED_TS, V4L_EVENT_CAM_REQ_MGR_EVENT)) CAM_ERR(CAM_ISP, "Error in notifying the sof and boot time for req id:%lld", request_id); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_SHUTTER, NULL, shutter_event); } static void __cam_isp_ctx_send_sof_timestamp_frame_header( @@ -1559,6 +1600,7 @@ static void __cam_isp_ctx_send_sof_timestamp( { struct cam_req_mgr_message req_msg; struct cam_context *ctx = ctx_isp->base; + struct shutter_event shutter_event = {0}; if (ctx_isp->reported_frame_id == ctx_isp->frame_id) { if (__cam_isp_ctx_recover_sof_timestamp(ctx_isp->base, request_id)) @@ -1574,10 +1616,11 @@ static void __cam_isp_ctx_send_sof_timestamp( } ctx_isp->reported_frame_id = ctx_isp->frame_id; + shutter_event.status = sof_event_status; if ((ctx_isp->v4l2_event_sub_ids & (1 << V4L_EVENT_CAM_REQ_MGR_SOF_UNIFIED_TS)) && !ctx_isp->use_frame_header_ts) { - __cam_isp_ctx_send_unified_timestamp(ctx_isp,request_id); + __cam_isp_ctx_send_unified_timestamp(ctx_isp, request_id, &shutter_event); return; } @@ -1594,7 +1637,7 @@ static void __cam_isp_ctx_send_sof_timestamp( CAM_DBG(CAM_ISP, "request id:%lld frame number:%lld SOF time stamp:0x%llx status:%u ctx_idx: %u, link: 0x%x", - request_id, ctx_isp->frame_id, + request_id, ctx_isp->frame_id, ctx_isp->sof_timestamp_val, sof_event_status, ctx->ctx_id, ctx->link_hdl); if (cam_req_mgr_notify_message(&req_msg, @@ -1605,7 +1648,7 @@ static void __cam_isp_ctx_send_sof_timestamp( end: __cam_isp_ctx_send_sof_boot_timestamp(ctx_isp, - request_id, sof_event_status); + request_id, sof_event_status, &shutter_event); } static void __cam_isp_ctx_handle_buf_done_fail_log( @@ -1652,11 +1695,6 @@ static void __cam_isp_ctx_handle_buf_done_fail_log( if ((ctx_isp->congestion_cnt >= CAM_ISP_CONTEXT_CONGESTION_CNT_MAX) && (!ctx_isp->sof_dbg_irq_en)) __cam_isp_ctx_handle_sof_freeze_evt(ctx); - - /*Dump SOF timestamp for each path to make sure - whther SOF's are comming for each path or not - */ - __cam_isp_ctx_get_path_timestamp(ctx); } static void __cam_isp_context_reset_internal_recovery_params( @@ -1785,7 +1823,7 @@ static int __cam_isp_ctx_handle_buf_done_for_req_list( ctx_isp->last_bufdone_err_apply_req_id = 0; } else { list_add(&req->list, &ctx->pending_req_list); - CAM_INFO(CAM_REQ, + CAM_DBG(CAM_REQ, "Move active request %lld to pending list(cnt = %d) [bubble recovery], ctx %u, link: 0x%x", req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id, ctx->link_hdl); @@ -1832,7 +1870,7 @@ static int __cam_isp_ctx_handle_buf_done_for_req_list( CAM_ISP_STATE_CHANGE_TRIGGER_DONE, buf_done_req_id); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_BUFDONE, req); + CAM_ISP_CTX_EVENT_BUFDONE, req, NULL); return rc; } @@ -1892,7 +1930,7 @@ static int __cam_isp_ctx_handle_buf_done_for_request( if ((k == req_isp->num_fence_map_out) && (j != comp_grp->num_res - 1)) continue; else if (k != req_isp->num_fence_map_out) - continue; + break; else not_found = true; } @@ -1969,12 +2007,15 @@ static int __cam_isp_ctx_handle_buf_done_for_request( } if (!req_isp->bubble_detected) { + handle_type = __cam_isp_resource_handle_id_to_type( + ctx_isp->isp_device_type, + req_isp->fence_map_out[j].resource_handle); CAM_DBG(CAM_ISP, - "Sync with success: req %lld res 0x%x fd 0x%x, ctx %u link: 0x%x", + "Sync with success: req %lld res 0x%x fd 0x%x, ctx %u link: 0x%x port %s", req->request_id, req_isp->fence_map_out[j].resource_handle, req_isp->fence_map_out[j].sync_id, - ctx->ctx_id, ctx->link_hdl); + ctx->ctx_id, ctx->link_hdl, handle_type); cam_smmu_buffer_tracker_buffer_putref( req_isp->fence_map_out[j].buffer_tracker); @@ -2201,7 +2242,7 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( comp_grp = &ctx_isp->vfe_bus_comp_grp[done->comp_group_id]; if (!comp_grp) { - CAM_ERR(CAM_ISP, "comp_grp is NULL"); + CAM_ERR(CAM_ISP, "comp_grp is NULL for hw_type: %d", done->hw_type); rc = -EINVAL; return rc; } @@ -2209,7 +2250,7 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( if (i == req_isp->num_fence_map_out) { not_found = true; for (j = 0; j < comp_grp->num_res; j++) { - /* If the res is same with original res, then we don't need to read again */ + /* If the res is same with original res, we don't need to read again */ if (comp_grp->res_id[j] == done->resource_handle) continue; @@ -2258,11 +2299,15 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( CAM_36BIT_INTF_GET_IOVA_BASE( req_isp->fence_map_out[k].image_buf_addr[0]) : req_isp->fence_map_out[k].image_buf_addr[0]; - CAM_DBG(CAM_ISP, "Get res %s last_consumed_addr:0x%x cmp_addr:0x%x", + CAM_DBG(CAM_ISP, + "Get res %s comp_grp_rec_idx:%d fence_map_idx:%d last_consumed_addr:0x%x cmp_addr:0x%x", __cam_isp_resource_handle_id_to_type( - ctx_isp->isp_device_type, done->resource_handle), + ctx_isp->isp_device_type, done->resource_handle), j, k, done->last_consumed_addr, cmp_addr); if (done->last_consumed_addr == cmp_addr) { + CAM_DBG(CAM_ISP, "Consumed addr compare success for res:%s ", + __cam_isp_resource_handle_id_to_type( + ctx_isp->isp_device_type, done->resource_handle)); not_found = false; break; } @@ -2391,11 +2436,13 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( continue; } else if (!req_isp->bubble_detected) { CAM_DBG(CAM_ISP, - "Sync with success: req %lld res 0x%x fd 0x%x, ctx:%u link[0x%x]", + "Sync with success: req %lld res 0x%x fd 0x%x, ctx %u res %s", req->request_id, req_isp->fence_map_out[j].resource_handle, req_isp->fence_map_out[j].sync_id, - ctx->ctx_id, ctx->link_hdl); + ctx->ctx_id, + __cam_isp_resource_handle_id_to_type(ctx_isp->isp_device_type, + req_isp->fence_map_out[j].resource_handle)); cam_smmu_buffer_tracker_buffer_putref( req_isp->fence_map_out[j].buffer_tracker); @@ -3062,7 +3109,7 @@ static int __cam_isp_ctx_reg_upd_in_applied_state( "move request %lld to active list(cnt = %d), ctx %u, link: 0x%x", req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id, ctx->link_hdl); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_RUP, req); + CAM_ISP_CTX_EVENT_RUP, req, NULL); } else { cam_smmu_buffer_tracker_putref(&req->buf_tracker); /* no io config, so the request is completed. */ @@ -3204,7 +3251,7 @@ notify_only: (req->request_id > ctx_isp->reported_req_id)) { request_id = req->request_id; __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_EPOCH, req); + CAM_ISP_CTX_EVENT_EPOCH, req, NULL); break; } } @@ -3374,7 +3421,7 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_EPOCH, NULL); + CAM_ISP_CTX_EVENT_EPOCH, NULL, NULL); goto end; } @@ -3387,7 +3434,7 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, * The previous req is applied after SOF and there is only * one applied req, we don't need to report bubble for this case. */ - if (wait_req_cnt == 1) { + if (wait_req_cnt == 1 && !ctx_isp->is_tfe_shdr) { req = list_first_entry(&ctx->wait_req_list, struct cam_ctx_request, list); request_id = req->request_id; @@ -3433,7 +3480,7 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, list_del_init(&req->list); list_add_tail(&req->list, &ctx->active_req_list); ctx_isp->active_req_cnt++; - CAM_WARN(CAM_REQ, "move request %lld to active list for bubble recovery (cnt = %d), ctx %u, link: 0x%x", + CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d), ctx %u, link: 0x%x", req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id, ctx->link_hdl); /* @@ -3448,7 +3495,7 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, * other invalid req. */ __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_EPOCH, req); + CAM_ISP_CTX_EVENT_EPOCH, req, NULL); /* * Get the req again from active_req_list in case @@ -3622,8 +3669,7 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_EPOCH, NULL); - + CAM_ISP_CTX_EVENT_EPOCH, NULL, NULL); ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; goto end; } @@ -3685,21 +3731,20 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( request_id = req->request_id; ctx_isp->reported_req_id = request_id; __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, - CAM_REQ_MGR_SOF_EVENT_ERROR); - + CAM_REQ_MGR_SOF_EVENT_ERROR); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_EPOCH, req); + CAM_ISP_CTX_EVENT_EPOCH, req, NULL); } else { __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_EPOCH, NULL); + CAM_ISP_CTX_EVENT_EPOCH, NULL, NULL); } } else { __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_EPOCH, NULL); + CAM_ISP_CTX_EVENT_EPOCH, NULL, NULL); } ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; CAM_DBG(CAM_ISP, "next Substate[%s], ctx_idx: %u, link: 0x%x", @@ -3922,7 +3967,6 @@ static int __cam_isp_ctx_handle_recovery_req_util( { int rc = 0; struct cam_context *ctx = ctx_isp->base; - struct cam_isp_ctx_req *req_isp; struct cam_ctx_request *req_to_reapply = NULL; if (list_empty(&ctx->pending_req_list)) { @@ -3933,14 +3977,6 @@ static int __cam_isp_ctx_handle_recovery_req_util( req_to_reapply = list_first_entry(&ctx->pending_req_list, struct cam_ctx_request, list); - req_isp = (struct cam_isp_ctx_req *)req_to_reapply->req_priv; - if (req_isp->internal_recovery_attempts >= CAM_ISP_CONTEXT_MAX_INTERNAL_RECOVERY_ATTEMPTS) { - CAM_INFO(CAM_ISP, - "Max internal recovery attempts for req:%llu for ctx:%u link:0x%x", - req_to_reapply->request_id, ctx->ctx_id, ctx->link_hdl); - return -EOPNOTSUPP; - } - ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH; ctx_isp->recovery_req_id = req_to_reapply->request_id; atomic_set(&ctx_isp->internal_recovery_set, 1); @@ -4925,7 +4961,6 @@ static int __cam_isp_ctx_apply_req_in_activated_state( enum cam_isp_ctx_activated_substate next_state) { int rc = 0; - bool mode_switch = false; struct cam_ctx_request *req; struct cam_ctx_request *active_req = NULL; struct cam_isp_ctx_req *req_isp; @@ -4935,8 +4970,6 @@ static int __cam_isp_ctx_apply_req_in_activated_state( struct cam_isp_skip_frame_info *skip_info; struct cam_isp_fcg_prediction_tracker *fcg_tracker; struct cam_isp_fcg_config_info *fcg_info; - ktime_t sched_ts, curr_ts; - uint64_t diff; ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; @@ -5014,7 +5047,6 @@ static int __cam_isp_ctx_apply_req_in_activated_state( ctx->ctx_id, ctx->link_hdl); req_isp = (struct cam_isp_ctx_req *) req->req_priv; - mode_switch = req_isp->hw_update_data.mup_en; if (ctx_isp->active_req_cnt >= 2) { CAM_WARN_RATE_LIMIT(CAM_ISP, "Reject apply request (id %lld) due to congestion(cnt = %d) ctx %u, link: 0x%x", @@ -5057,7 +5089,6 @@ static int __cam_isp_ctx_apply_req_in_activated_state( req_isp->num_deferred_acks = 0; req_isp->cdm_reset_before_apply = false; req_isp->bubble_detected = false; - req_isp->internal_recovery_attempts = 0; cfg.ctxt_to_hw_map = ctx_isp->hw_ctx; cfg.request_id = req->request_id; @@ -5098,15 +5129,23 @@ static int __cam_isp_ctx_apply_req_in_activated_state( } atomic_set(&ctx_isp->apply_in_progress, 1); - sched_ts = ktime_get(); + rc = ctx->hw_mgr_intf->hw_config(ctx->hw_mgr_intf->hw_mgr_priv, &cfg); - curr_ts = ktime_get(); - diff = ktime_ms_delta(curr_ts, curr_ts); if (!rc) { spin_lock_bh(&ctx->lock); ctx_isp->substate_activated = next_state; ctx_isp->last_applied_req_id = apply->request_id; ctx_isp->last_applied_jiffies = jiffies; + + if (ctx_isp->is_tfe_shdr) { + if (ctx_isp->is_shdr_master && req_isp->hw_update_data.mup_en) + apply->dual_trigger_status = req_isp->hw_update_data.num_exp; + else + apply->dual_trigger_status = CAM_REQ_DUAL_TRIGGER_NONE; + } else { + apply->dual_trigger_status = CAM_REQ_DUAL_TRIGGER_NONE; + } + list_del_init(&req->list); if (atomic_read(&ctx_isp->internal_recovery_set)) __cam_isp_ctx_enqueue_request_in_order(ctx, req, false); @@ -5117,14 +5156,11 @@ static int __cam_isp_ctx_apply_req_in_activated_state( ctx_isp->last_applied_req_id, ctx->ctx_id, ctx->link_hdl); spin_unlock_bh(&ctx->lock); - if ((mode_switch) && (diff > 10)) - CAM_INFO(CAM_ISP, "Req %lld with mode switch moved to wait after delay %llums", apply->request_id, diff); - __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_APPLIED, req->request_id); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_APPLY, req); + CAM_ISP_CTX_EVENT_APPLY, req, NULL); } else if (rc == -EALREADY) { spin_lock_bh(&ctx->lock); req_isp->bubble_detected = true; @@ -5310,8 +5346,8 @@ static int __cam_isp_ctx_apply_default_req_settings( "Failed to apply default settings rc %d ctx %u, link: 0x%x", rc, ctx->ctx_id, ctx->link_hdl); else - CAM_INFO(CAM_ISP, "Applied default settings rc %d ctx: %u link: 0x%x rup_aup_skipped: %d", - rc, ctx->ctx_id, ctx->link_hdl, skip_rup_aup); + CAM_DBG(CAM_ISP, "Applied default settings rc %d ctx: %u link: 0x%x", + rc, ctx->ctx_id, ctx->link_hdl); } end: @@ -5561,10 +5597,10 @@ hw_dump: (CAM_ISP_CTX_DUMP_NUM_WORDS * sizeof(uint64_t)); if (remain_len < min_len) { - spin_unlock_bh(&ctx->lock); CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu min %u, ctx_idx: %u, link: 0x%x", remain_len, min_len, ctx->ctx_id, ctx->link_hdl); + spin_unlock_bh(&ctx->lock); cam_mem_put_cpu_buf(dump_info->buf_handle); return -ENOSPC; } @@ -5598,6 +5634,18 @@ hw_dump: } dump_info->offset = dump_args.offset; + min_len = sizeof(struct cam_isp_context_dump_header) + + (CAM_ISP_CTX_DUMP_NUM_WORDS * sizeof(int32_t)); + remain_len = buf_len - dump_info->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, + "Dump buffer exhaust remain %zu min %u, ctx_idx: %u, link: 0x%x", + remain_len, min_len, ctx->ctx_id, ctx->link_hdl); + spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf(dump_info->buf_handle); + return -ENOSPC; + } + /* Dump stream info */ ctx->ctxt_to_hw_map = ctx_isp->hw_ctx; if (ctx->hw_mgr_intf->hw_dump) { @@ -5612,6 +5660,17 @@ hw_dump: goto end; } + dump_info->offset = dump_args.offset; + remain_len = buf_len - dump_info->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, + "Dump buffer exhaust remain %zu min %u, ctx_idx: %u, link: 0x%x", + remain_len, min_len, ctx->ctx_id, ctx->link_hdl); + spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf(dump_info->buf_handle); + return -ENOSPC; + } + /* Dump second part of stream info from ife hw manager */ hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; @@ -6158,7 +6217,6 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied( /* Send SOF event as empty frame*/ __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); - goto end; } @@ -6194,7 +6252,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied( request_id = req->request_id; ctx_isp->reported_req_id = request_id; __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, - CAM_REQ_MGR_SOF_EVENT_ERROR); + CAM_REQ_MGR_SOF_EVENT_ERROR); } else __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); @@ -6432,14 +6490,14 @@ static int __cam_isp_ctx_rdi_only_reg_upd_in_bubble_applied_state( __cam_isp_ctx_substate_val_to_type( ctx_isp->substate_activated), ctx->ctx_id, ctx->link_hdl); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_RUP, req); + CAM_ISP_CTX_EVENT_RUP, req, NULL); return 0; error: /* Send SOF event as idle frame*/ __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); __cam_isp_ctx_update_event_record(ctx_isp, - CAM_ISP_CTX_EVENT_RUP, NULL); + CAM_ISP_CTX_EVENT_RUP, NULL, NULL); /* * There is no request in the pending list, move the sub state machine @@ -6631,6 +6689,8 @@ static int __cam_isp_ctx_flush_dev_in_top_state(struct cam_context *ctx, static void __cam_isp_ctx_free_mem_hw_entries(struct cam_context *ctx) { int i; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; if (ctx->out_map_entries) { for (i = 0; i < CAM_ISP_CTX_REQ_MAX; i++) { @@ -6662,6 +6722,13 @@ static void __cam_isp_ctx_free_mem_hw_entries(struct cam_context *ctx) ctx->hw_update_entry = NULL; } + if (ctx_isp) { + for (i = 0; i < CAM_ISP_CTX_REQ_MAX; i++) { + kfree(ctx_isp->req_isp[i].deferred_fence_map_index); + ctx_isp->req_isp[i].deferred_fence_map_index = NULL; + } + } + ctx->max_out_map_entries = 0; ctx->max_in_map_entries = 0; ctx->max_hw_update_entries = 0; @@ -6826,6 +6893,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( struct cam_packet *packet; size_t remain_len = 0; struct cam_hw_prepare_update_args cfg = {0}; + struct cam_isp_prepare_hw_update_data *hw_update_data; struct cam_req_mgr_add_request add_req; struct cam_isp_context *ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; @@ -6920,6 +6988,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( goto free_req_and_buf_tracker_list; } + hw_update_data = cfg.priv; req_isp->num_cfg = cfg.num_hw_update_entries; req_isp->num_fence_map_out = cfg.num_out_map_entries; req_isp->num_fence_map_in = cfg.num_in_map_entries; @@ -6927,8 +6996,9 @@ static int __cam_isp_ctx_config_dev_in_top_state( req_isp->num_deferred_acks = 0; req_isp->bubble_detected = false; req_isp->cdm_reset_before_apply = false; - req_isp->internal_recovery_attempts = 0; req_isp->hw_update_data.packet = packet; + req_isp->hw_update_data.num_exp = hw_update_data->num_exp; + req_isp->hw_update_data.mup_en = hw_update_data->mup_en; req->pf_data.packet_handle = cmd->packet_handle; req->pf_data.packet_offset = cmd->offset; req->pf_data.req = req; @@ -6943,7 +7013,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( } CAM_DBG(CAM_ISP, - "packet req-id:%lld, opcode:%d, num_entry:%d, num_fence_out: %d, num_fence_in: %d, ctx_idx: %u, link: 0x%x", + "packet req-id:%lld, opcode:%d, num_entry:%d, num_fence_out: %d, num_fence_in: %d, ctx: %u, link: 0x%x", packet->header.request_id, req_isp->hw_update_data.packet_opcode_type, req_isp->num_cfg, req_isp->num_fence_map_out, req_isp->num_fence_map_in, ctx->ctx_id, ctx->link_hdl); @@ -6985,6 +7055,12 @@ static int __cam_isp_ctx_config_dev_in_top_state( add_req.link_hdl = ctx->link_hdl; add_req.dev_hdl = ctx->dev_hdl; add_req.req_id = req->request_id; + add_req.num_exp = ctx_isp->last_num_exp; + + if (req_isp->hw_update_data.mup_en) { + add_req.num_exp = req_isp->hw_update_data.num_exp; + ctx_isp->last_num_exp = add_req.num_exp; + } rc = ctx->ctx_crm_intf->add_req(&add_req); if (rc) { if (rc == -EBADR) @@ -7045,6 +7121,8 @@ static int __cam_isp_ctx_allocate_mem_hw_entries( struct cam_ctx_request *req; struct cam_ctx_request *temp_req; struct cam_isp_ctx_req *req_isp; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; if (!param->op_params.param_list[0]) max_res = CAM_ISP_CTX_RES_MAX; @@ -7074,16 +7152,6 @@ static int __cam_isp_ctx_allocate_mem_hw_entries( return -ENOMEM; } - for (i = 0; i < CAM_ISP_CTX_REQ_MAX; i++) { - ctx->hw_update_entry[i] = kcalloc(ctx->max_hw_update_entries, - sizeof(struct cam_hw_update_entry), GFP_KERNEL); - if (!ctx->hw_update_entry[i]) { - CAM_ERR(CAM_CTXT, "%s[%u] no memory for hw_update_entry: %u, link: 0x%x", - ctx->dev_name, ctx->ctx_id, i, ctx->link_hdl); - return -ENOMEM; - } - } - ctx->in_map_entries = kcalloc(CAM_ISP_CTX_REQ_MAX, sizeof(struct cam_hw_fence_map_entry *), GFP_KERNEL); @@ -7094,19 +7162,6 @@ static int __cam_isp_ctx_allocate_mem_hw_entries( goto end; } - for (i = 0; i < CAM_ISP_CTX_REQ_MAX; i++) { - ctx->in_map_entries[i] = kcalloc(ctx->max_in_map_entries, - sizeof(struct cam_hw_fence_map_entry), - GFP_KERNEL); - - if (!ctx->in_map_entries[i]) { - CAM_ERR(CAM_CTXT, "%s[%u] no memory for in_map_entries: %u, link: 0x%x", - ctx->dev_name, ctx->ctx_id, i, ctx->link_hdl); - rc = -ENOMEM; - goto end; - } - } - ctx->out_map_entries = kcalloc(CAM_ISP_CTX_REQ_MAX, sizeof(struct cam_hw_fence_map_entry *), GFP_KERNEL); @@ -7117,7 +7172,29 @@ static int __cam_isp_ctx_allocate_mem_hw_entries( goto end; } + for (i = 0; i < CAM_ISP_CTX_REQ_MAX; i++) { + ctx->hw_update_entry[i] = kcalloc(ctx->max_hw_update_entries, + sizeof(struct cam_hw_update_entry), GFP_KERNEL); + + if (!ctx->hw_update_entry[i]) { + CAM_ERR(CAM_CTXT, "%s[%u] no memory for hw_update_entry: %u, link: 0x%x", + ctx->dev_name, ctx->ctx_id, i, ctx->link_hdl); + rc = -ENOMEM; + goto end; + } + + ctx->in_map_entries[i] = kcalloc(ctx->max_in_map_entries, + sizeof(struct cam_hw_fence_map_entry), + GFP_KERNEL); + + if (!ctx->in_map_entries[i]) { + CAM_ERR(CAM_CTXT, "%s[%u] no memory for in_map_entries: %u, link: 0x%x", + ctx->dev_name, ctx->ctx_id, i, ctx->link_hdl); + rc = -ENOMEM; + goto end; + } + ctx->out_map_entries[i] = kcalloc(ctx->max_out_map_entries, sizeof(struct cam_hw_fence_map_entry), GFP_KERNEL); @@ -7128,6 +7205,16 @@ static int __cam_isp_ctx_allocate_mem_hw_entries( rc = -ENOMEM; goto end; } + + ctx_isp->req_isp[i].deferred_fence_map_index = kcalloc(param->total_ports_acq, + sizeof(uint32_t), GFP_KERNEL); + + if (!ctx_isp->req_isp[i].deferred_fence_map_index) { + CAM_ERR(CAM_ISP, "%s[%d] no memory for defer fence map idx arr, ports:%u", + ctx->dev_name, ctx->ctx_id, param->total_ports_acq); + rc = -ENOMEM; + goto end; + } } list_for_each_entry_safe(req, temp_req, @@ -7220,13 +7307,6 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, param.num_acq = cmd->num_resources; param.acquire_info = (uintptr_t) isp_res; - rc = __cam_isp_ctx_allocate_mem_hw_entries(ctx, ¶m); - if (rc) { - CAM_ERR(CAM_ISP, "Ctx[%u] link: 0x%x allocate hw entry fail", - ctx->ctx_id, ctx->link_hdl); - goto free_res; - } - /* call HW manager to reserve the resource */ rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, ¶m); @@ -7236,6 +7316,13 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, goto free_res; } + rc = __cam_isp_ctx_allocate_mem_hw_entries(ctx, ¶m); + if (rc) { + CAM_ERR(CAM_ISP, "Ctx[%u] link: 0x%x allocate hw entry fail", + ctx->ctx_id, ctx->link_hdl); + goto free_res; + } + /* Query the context has rdi only resource */ hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; @@ -7357,6 +7444,7 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, struct cam_hw_cmd_args hw_cmd_args; struct cam_isp_hw_cmd_args isp_hw_cmd_args; struct cam_isp_acquire_hw_info *acquire_hw_info = NULL; + struct cam_isp_comp_record_query query_cmd; if (!ctx->hw_mgr_intf) { CAM_ERR(CAM_ISP, "HW interface is not ready, ctx %u link: 0x%x", @@ -7407,14 +7495,7 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, param.acquire_info_size = cmd->data_size; param.acquire_info = (uint64_t) acquire_hw_info; param.mini_dump_cb = __cam_isp_ctx_minidump_cb; - - rc = __cam_isp_ctx_allocate_mem_hw_entries(ctx, - ¶m); - if (rc) { - CAM_ERR(CAM_ISP, "Ctx[%u] link: 0x%x allocate hw entry fail", - ctx->ctx_id, ctx->link_hdl); - goto free_res; - } + param.link_hdl = ctx->link_hdl; /* call HW manager to reserve the resource */ rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, @@ -7425,8 +7506,43 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, goto free_res; } + rc = __cam_isp_ctx_allocate_mem_hw_entries(ctx, + ¶m); + if (rc) { + CAM_ERR(CAM_ISP, "Ctx[%u] link: 0x%x allocate hw entry fail", + ctx->ctx_id, ctx->link_hdl); + goto free_res; + } + + ctx_isp->last_num_exp = 0; ctx_isp->support_consumed_addr = (param.op_flags & CAM_IFE_CTX_CONSUME_ADDR_EN); + ctx_isp->is_tfe_shdr = (param.op_flags & CAM_IFE_CTX_SHDR_EN); + ctx_isp->is_shdr_master = (param.op_flags & CAM_IFE_CTX_SHDR_IS_MASTER); + + /* Query the context bus comp group information */ + ctx_isp->vfe_bus_comp_grp = kcalloc(CAM_IFE_BUS_COMP_NUM_MAX, + sizeof(struct cam_isp_context_comp_record), GFP_KERNEL); + if (!ctx_isp->vfe_bus_comp_grp) { + CAM_ERR(CAM_CTXT, "%s[%d] no memory for vfe_bus_comp_grp", + ctx->dev_name, ctx->ctx_id); + rc = -ENOMEM; + goto free_hw; + } + + query_cmd.vfe_bus_comp_grp = ctx_isp->vfe_bus_comp_grp; + hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_GET_BUS_COMP_GROUP; + isp_hw_cmd_args.cmd_data = &query_cmd; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "Bus Comp HW command failed, ctx_idx: %u, link: 0x%x", + ctx->ctx_id, ctx->link_hdl); + goto free_hw; + } /* Query the context has rdi only resource */ hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; @@ -7488,9 +7604,9 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, trace_cam_context_state("ISP", ctx); CAM_INFO(CAM_ISP, - "Acquire success:session_hdl 0x%xs ctx_type %d ctx %u link: 0x%x hw_mgr_ctx: %u", + "Acquire success:session_hdl 0x%xs ctx_type %d ctx %u link: 0x%x hw_mgr_ctx: %u is_shdr %d is_shdr_master %d", ctx->session_hdl, isp_hw_cmd_args.u.ctx_type, ctx->ctx_id, ctx->link_hdl, - param.hw_mgr_ctx_id); + param.hw_mgr_ctx_id, ctx_isp->is_tfe_shdr, ctx_isp->is_shdr_master); kfree(acquire_hw_info); return rc; @@ -7574,6 +7690,7 @@ static int __cam_isp_ctx_acquire_hw_v2(struct cam_context *ctx, param.acquire_info_size = cmd->data_size; param.acquire_info = (uint64_t) acquire_hw_info; param.mini_dump_cb = __cam_isp_ctx_minidump_cb; + param.link_hdl = ctx->link_hdl; /* call HW manager to reserve the resource */ rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, @@ -7595,6 +7712,7 @@ static int __cam_isp_ctx_acquire_hw_v2(struct cam_context *ctx, * Set feature flag if applicable * custom hw is supported only on v2 */ + ctx_isp->last_num_exp = 0; ctx_isp->custom_enabled = (param.op_flags & CAM_IFE_CTX_CUSTOM_EN); ctx_isp->use_frame_header_ts = @@ -7607,6 +7725,8 @@ static int __cam_isp_ctx_acquire_hw_v2(struct cam_context *ctx, (param.op_flags & CAM_IFE_CTX_AEB_EN); ctx_isp->mode_switch_en = (param.op_flags & CAM_IFE_CTX_DYNAMIC_SWITCH_EN); + ctx_isp->is_tfe_shdr = (param.op_flags & CAM_IFE_CTX_SHDR_EN); + ctx_isp->is_shdr_master = (param.op_flags & CAM_IFE_CTX_SHDR_IS_MASTER); /* Query the context bus comp group information */ ctx_isp->vfe_bus_comp_grp = kcalloc(CAM_IFE_BUS_COMP_NUM_MAX, @@ -7736,9 +7856,9 @@ static int __cam_isp_ctx_acquire_hw_v2(struct cam_context *ctx, trace_cam_context_state("ISP", ctx); CAM_INFO(CAM_ISP, - "Acquire success: session_hdl 0x%xs ctx_type %d ctx %u link: 0x%x hw_mgr_ctx: %u", + "Acquire success: session_hdl 0x%xs ctx_type %d ctx %u link 0x%x hw_mgr_ctx %u is_shdr %d is_shdr_master %d", ctx->session_hdl, isp_hw_cmd_args.u.ctx_type, ctx->ctx_id, ctx->link_hdl, - param.hw_mgr_ctx_id); + param.hw_mgr_ctx_id, ctx_isp->is_tfe_shdr, ctx_isp->is_shdr_master); kfree(acquire_hw_info); return rc; @@ -7940,10 +8060,12 @@ static int __cam_isp_ctx_unlink_in_acquired(struct cam_context *ctx, return rc; } -static int __cam_isp_ctx_get_dev_info_in_acquired(struct cam_context *ctx, +static int __cam_isp_ctx_get_dev_info(struct cam_context *ctx, struct cam_req_mgr_device_info *dev_info) { int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; dev_info->dev_hdl = ctx->dev_hdl; strlcpy(dev_info->name, CAM_ISP_DEV_NAME, sizeof(dev_info->name)); @@ -7952,6 +8074,8 @@ static int __cam_isp_ctx_get_dev_info_in_acquired(struct cam_context *ctx, dev_info->m_delay = CAM_MODESWITCH_DELAY_1; dev_info->trigger = CAM_TRIGGER_POINT_SOF; dev_info->trigger_on = true; + dev_info->is_shdr = ctx_isp->is_tfe_shdr; + dev_info->is_shdr_master = ctx_isp->is_shdr_master; return rc; } @@ -8215,10 +8339,6 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock( list_add_tail(&req->list, &ctx->free_req_list); } - CAM_INFO(CAM_ISP, - "Stop device success next state %d on ctx %u link: 0x%x last_applied: %lld", - ctx->state, ctx->ctx_id, ctx->link_hdl, ctx_isp->last_applied_req_id); - ctx_isp->frame_id = 0; ctx_isp->active_req_cnt = 0; ctx_isp->reported_req_id = 0; @@ -8240,6 +8360,9 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock( for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) atomic64_set(&ctx_isp->dbg_monitors.event_record_head[i], -1); + CAM_DBG(CAM_ISP, "Stop device success next state %d on ctx %u link: 0x%x", + ctx->state, ctx->ctx_id, ctx->link_hdl); + if (!stop_cmd) { rc = __cam_isp_ctx_unlink_in_ready(ctx, NULL); if (rc) @@ -8392,11 +8515,10 @@ static int __cam_isp_ctx_reset_and_recover( spin_unlock_bh(&ctx->lock); req_isp = (struct cam_isp_ctx_req *) req->req_priv; - req_isp->internal_recovery_attempts++; CAM_INFO(CAM_ISP, - "Trigger Halt, Reset & Resume for req: %llu ctx: %u in state: %d link: 0x%x [attempt: %u]", - req->request_id, ctx->ctx_id, ctx->state, ctx->link_hdl, req_isp->internal_recovery_attempts); + "Trigger Halt, Reset & Resume for req: %llu ctx: %u in state: %d link: 0x%x", + req->request_id, ctx->ctx_id, ctx->state, ctx->link_hdl); stop_args.ctxt_to_hw_map = ctx_isp->hw_ctx; stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY; @@ -8527,56 +8649,6 @@ error: return false; } -static void __cam_isp_ctx_dump_all_reqs( - struct cam_context *ctx) -{ - int i; - struct cam_isp_ctx_req *req_isp; - struct cam_ctx_request *req, *req_temp; - - if (list_empty(&ctx->active_req_list)) - CAM_INFO(CAM_ISP, "No active req in ctx: %u link: 0x%x", ctx->ctx_id, ctx->link_hdl); - else { - list_for_each_entry_safe(req, req_temp, &ctx->active_req_list, list) { - req_isp = (struct cam_isp_ctx_req *)req->req_priv; - CAM_INFO(CAM_ISP, "Active req:%lld ctx: %u link: 0x%x", req->request_id, ctx->ctx_id, ctx->link_hdl); - for (i = 0; i < req_isp->num_fence_map_out; i++) { - CAM_INFO(CAM_ISP, "i: %d Req: %lld fence: %d res: 0x%x", - i, req->request_id, req_isp->fence_map_out[i].sync_id, - req_isp->fence_map_out[i].resource_handle); - } - } - } - - if (list_empty(&ctx->wait_req_list)) - CAM_INFO(CAM_ISP, "No wait req in ctx: %u link: 0x%x", ctx->ctx_id, ctx->link_hdl); - else { - list_for_each_entry_safe(req, req_temp, &ctx->wait_req_list, list) { - req_isp = (struct cam_isp_ctx_req *)req->req_priv; - CAM_INFO(CAM_ISP, "Wait req:%lld ctx: %u link: 0x%x", req->request_id, ctx->ctx_id, ctx->link_hdl); - for (i = 0; i < req_isp->num_fence_map_out; i++) { - CAM_INFO(CAM_ISP, "i: %d Req: %lld fence: %d res: 0x%x", - i, req->request_id, req_isp->fence_map_out[i].sync_id, - req_isp->fence_map_out[i].resource_handle); - } - } - } - - if (list_empty(&ctx->pending_req_list)) - CAM_INFO(CAM_ISP, "No pending req in ctx: %u link: 0x%x", ctx->ctx_id, ctx->link_hdl); - else { - list_for_each_entry_safe(req, req_temp, &ctx->pending_req_list, list) { - req_isp = (struct cam_isp_ctx_req *)req->req_priv; - CAM_INFO(CAM_ISP, "pending req:%lld ctx: %u link: 0x%x", req->request_id, ctx->ctx_id, ctx->link_hdl); - for (i = 0; i < req_isp->num_fence_map_out; i++) { - CAM_INFO(CAM_ISP, "i: %d Req: %lld fence: %d res: 0x%x", - i, req->request_id, req_isp->fence_map_out[i].sync_id, - req_isp->fence_map_out[i].resource_handle); - } - } - } -} - static int __cam_isp_ctx_process_evt(struct cam_context *ctx, struct cam_req_mgr_link_evt_data *link_evt_data) { @@ -8604,7 +8676,6 @@ static int __cam_isp_ctx_process_evt(struct cam_context *ctx, rc = __cam_isp_ctx_link_resume(ctx); break; case CAM_REQ_MGR_LINK_EVT_SOF_FREEZE: - __cam_isp_ctx_dump_all_reqs(ctx); rc = __cam_isp_ctx_handle_sof_freeze_evt(ctx); break; case CAM_REQ_MGR_LINK_EVT_STALLED: { @@ -9002,7 +9073,7 @@ static struct cam_ctx_ops .crm_ops = { .link = __cam_isp_ctx_link_in_acquired, .unlink = __cam_isp_ctx_unlink_in_acquired, - .get_dev_info = __cam_isp_ctx_get_dev_info_in_acquired, + .get_dev_info = __cam_isp_ctx_get_dev_info, .process_evt = __cam_isp_ctx_process_evt, .flush_req = __cam_isp_ctx_flush_req_in_top_state, .dump_req = __cam_isp_ctx_dump_in_top_state, @@ -9023,6 +9094,7 @@ static struct cam_ctx_ops }, .crm_ops = { .unlink = __cam_isp_ctx_unlink_in_ready, + .get_dev_info = __cam_isp_ctx_get_dev_info, .flush_req = __cam_isp_ctx_flush_req_in_ready, .dump_req = __cam_isp_ctx_dump_in_top_state, }, @@ -9048,6 +9120,7 @@ static struct cam_ctx_ops .pagefault_ops = cam_isp_context_dump_requests, .dumpinfo_ops = cam_isp_context_info_dump, .evt_inject_ops = cam_isp_context_inject_evt, + .msg_cb_ops = cam_isp_context_handle_message, }, /* Activated */ { @@ -9072,6 +9145,7 @@ static struct cam_ctx_ops .dumpinfo_ops = cam_isp_context_info_dump, .recovery_ops = cam_isp_context_hw_recovery, .evt_inject_ops = cam_isp_context_inject_evt, + .msg_cb_ops = cam_isp_context_handle_message, }, }; @@ -9199,6 +9273,34 @@ end: return rc; } +static int cam_isp_context_handle_message(void *context, + uint32_t msg_type, void *data) +{ + int rc = -EINVAL; + struct cam_hw_cmd_args hw_cmd_args = {0}; + struct cam_isp_hw_cmd_args isp_hw_cmd_args = {0}; + struct cam_context *ctx = (struct cam_context *)context; + + hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + + switch (msg_type) { + case CAM_SUBDEV_MESSAGE_CLOCK_UPDATE: + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_UPDATE_CLOCK; + isp_hw_cmd_args.cmd_data = data; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + + if (rc) + CAM_ERR(CAM_ISP, "Update clock rate failed rc: %d", rc); + break; + default: + CAM_ERR(CAM_ISP, "Invalid message type %d", msg_type); + } + return rc; +} + static int cam_isp_context_debug_register(void) { int rc = 0; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.h b/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.h index 43ec69678c..63dc38eae5 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_context.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_ISP_CONTEXT_H_ @@ -105,6 +105,7 @@ enum cam_isp_ctx_event { CAM_ISP_CTX_EVENT_EPOCH, CAM_ISP_CTX_EVENT_RUP, CAM_ISP_CTX_EVENT_BUFDONE, + CAM_ISP_CTX_EVENT_SHUTTER, CAM_ISP_CTX_EVENT_MAX }; @@ -198,7 +199,7 @@ struct cam_isp_ctx_req { uint32_t num_fence_map_in; uint32_t num_acked; uint32_t num_deferred_acks; - uint32_t deferred_fence_map_index[CAM_ISP_CTX_RES_MAX]; + uint32_t *deferred_fence_map_index; int32_t bubble_report; struct cam_isp_prepare_hw_update_data hw_update_data; enum cam_hw_config_reapply_type reapply_type; @@ -241,6 +242,14 @@ struct cam_isp_context_req_id_info { int64_t last_bufdone_req_id; }; +struct shutter_event { + uint64_t frame_id; + uint64_t req_id; + uint32_t status; + ktime_t boot_ts; + ktime_t sof_ts; +}; + /** * * @@ -252,8 +261,12 @@ struct cam_isp_context_req_id_info { * */ struct cam_isp_context_event_record { - uint64_t req_id; - ktime_t timestamp; + uint64_t req_id; + ktime_t timestamp; + int event_type; + union event { + struct shutter_event shutter_event; + } event; }; /** @@ -407,6 +420,9 @@ struct cam_isp_fcg_prediction_tracker { * @hw_idx: Hardware ID * @fcg_tracker: FCG prediction tracker containing number of previously skipped * frames and indicates which prediction should be used + * @is_shdr: true, if usecase is sdhr + * @is_shdr_master: Flag to indicate master context in shdr usecase + * @last_num_exp: Last num of exposure * */ struct cam_isp_context { @@ -471,6 +487,9 @@ struct cam_isp_context { bool mode_switch_en; uint32_t hw_idx; struct cam_isp_fcg_prediction_tracker fcg_tracker; + bool is_tfe_shdr; + bool is_shdr_master; + uint32_t last_num_exp; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_dev.c b/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_dev.c index 45c73d8339..886ad4bfa3 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/cam_isp_dev.c @@ -73,6 +73,22 @@ static void cam_isp_dev_iommu_fault_handler(struct cam_smmu_pf_info *pf_smmu_inf } } +static void cam_isp_subdev_handle_message( + struct v4l2_subdev *sd, + enum cam_subdev_message_type_t message_type, + void *data) +{ + int i, rc = 0; + struct cam_node *node = v4l2_get_subdevdata(sd); + + CAM_DBG(CAM_ISP, "node name %s", node->name); + for (i = 0; i < node->ctx_size; i++) { + rc = cam_context_handle_message(&(node->ctx_list[i]), message_type, data); + if (rc) + CAM_ERR(CAM_ISP, "Failed to handle message for %s", node->name); + } +} + static const struct of_device_id cam_isp_dt_match[] = { { .compatible = "qcom,cam-isp" @@ -170,6 +186,7 @@ static int cam_isp_dev_component_bind(struct device *dev, } else if (strnstr(compat_str, "tfe", strlen(compat_str))) { rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, CAM_TFE_DEVICE_TYPE); + g_isp_dev.sd.msg_cb = cam_isp_subdev_handle_message; g_isp_dev.isp_device_type = CAM_TFE_DEVICE_TYPE; g_isp_dev.max_context = CAM_TFE_CTX_MAX; } else { @@ -185,19 +202,22 @@ static int cam_isp_dev_component_bind(struct device *dev, node = (struct cam_node *) g_isp_dev.sd.token; memset(&hw_mgr_intf, 0, sizeof(hw_mgr_intf)); - g_isp_dev.ctx = vzalloc(g_isp_dev.max_context * sizeof(struct cam_context)); + g_isp_dev.ctx = kcalloc(g_isp_dev.max_context, + sizeof(struct cam_context), + GFP_KERNEL); if (!g_isp_dev.ctx) { CAM_ERR(CAM_ISP, "Mem Allocation failed for ISP base context"); goto unregister; } - g_isp_dev.ctx_isp = vzalloc( - g_isp_dev.max_context * sizeof(struct cam_isp_context)); + g_isp_dev.ctx_isp = kcalloc(g_isp_dev.max_context, + sizeof(struct cam_isp_context), + GFP_KERNEL); if (!g_isp_dev.ctx_isp) { CAM_ERR(CAM_ISP, "Mem Allocation failed for Isp private context"); - vfree(g_isp_dev.ctx); + kfree(g_isp_dev.ctx); g_isp_dev.ctx = NULL; goto unregister; } @@ -222,8 +242,12 @@ static int cam_isp_dev_component_bind(struct device *dev, } } - cam_common_register_evt_inject_cb(cam_isp_dev_evt_inject_cb, - CAM_COMMON_EVT_INJECT_HW_ISP); + if (g_isp_dev.isp_device_type == CAM_IFE_DEVICE_TYPE) + cam_common_register_evt_inject_cb(cam_isp_dev_evt_inject_cb, + CAM_COMMON_EVT_INJECT_HW_IFE); + else + cam_common_register_evt_inject_cb(cam_isp_dev_evt_inject_cb, + CAM_COMMON_EVT_INJECT_HW_TFE); rc = cam_node_init(node, &hw_mgr_intf, g_isp_dev.ctx, g_isp_dev.max_context, CAM_ISP_DEV_NAME); @@ -244,9 +268,9 @@ static int cam_isp_dev_component_bind(struct device *dev, return 0; free_mem: - vfree(g_isp_dev.ctx); + kfree(g_isp_dev.ctx); g_isp_dev.ctx = NULL; - vfree(g_isp_dev.ctx_isp); + kfree(g_isp_dev.ctx_isp); g_isp_dev.ctx_isp = NULL; unregister: @@ -275,9 +299,9 @@ static void cam_isp_dev_component_unbind(struct device *dev, i); } - vfree(g_isp_dev.ctx); + kfree(g_isp_dev.ctx); g_isp_dev.ctx = NULL; - vfree(g_isp_dev.ctx_isp); + kfree(g_isp_dev.ctx_isp); g_isp_dev.ctx_isp = NULL; rc = cam_subdev_remove(&g_isp_dev.sd); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index e0a02c99c2..5eb17c8e96 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -22,6 +22,7 @@ #include "cam_isp_packet_parser.h" #include "cam_ife_hw_mgr.h" #include "cam_cdm_intf_api.h" +#include "cam_cdm_util.h" #include "cam_packet_util.h" #include "cam_debug_util.h" #include "cam_mem_mgr.h" @@ -42,7 +43,7 @@ #define CAM_ISP_GENERIC_BLOB_TYPE_MAX \ (CAM_ISP_GENERIC_BLOB_TYPE_CSID_QCFA_CONFIG + 1) -#define MAX_INTERNAL_RECOVERY_ATTEMPTS 7 +#define MAX_INTERNAL_RECOVERY_ATTEMPTS 1 #define MAX_PARAMS_FOR_IRQ_INJECT 5 #define IRQ_INJECT_DISPLAY_BUF_LEN 4096 @@ -156,6 +157,20 @@ static void *cam_ife_hw_mgr_get_hw_intf( return NULL; } + +static int cam_ife_mgr_get_first_valid_csid_id(void) +{ + int i = 0; + + for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) { + if (g_ife_hw_mgr.csid_devices[i]) { + CAM_DBG(CAM_ISP, "valid csid_id %d", i); + return i; + } + } + return 0; +} + static int cam_ife_mgr_update_core_info_to_cpas(struct cam_ife_hw_mgr_ctx *ctx, bool set_port) { @@ -366,7 +381,7 @@ static inline int __cam_ife_mgr_get_hw_soc_info( rc = hw_intf->hw_ops.process_cmd( hw_intf->hw_priv, CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, &soc_info, - sizeof(void *)); + (uint32_t)sizeof(void *)); if (rc) { CAM_ERR(CAM_ISP, "Failed in %d regspace data query res_id: %u split idx: %d rc : %d", @@ -483,6 +498,12 @@ static int cam_ife_mgr_handle_reg_dump(struct cam_ife_hw_mgr_ctx *ctx, { int rc = 0, i; + if (!ctx->flags.init_done) { + CAM_WARN(CAM_ISP, "Cannot dump register as HW not initialized, ctx_idx: %u", + ctx->ctx_index); + return 0; + } + if (cam_presil_mode_enabled()) { if (g_ife_hw_mgr.debug_cfg.enable_presil_reg_dump) { CAM_WARN(CAM_ISP, "regdump enabled for presil mode, ctx_idx: %u", @@ -795,8 +816,7 @@ static inline bool cam_ife_hw_mgr_is_ife_out_port(uint32_t res_id) bool is_ife_out = false; if ((res_id >= CAM_ISP_IFE_OUT_RES_BASE) && - (res_id <= (CAM_ISP_IFE_OUT_RES_BASE + - max_ife_out_res))) + (res_id < (CAM_ISP_IFE_OUT_RES_BASE + max_ife_out_res))) is_ife_out = true; return is_ife_out; @@ -940,7 +960,7 @@ static bool cam_ife_hw_mgr_is_sfe_rd_res( static int cam_ife_hw_mgr_reset_csid( struct cam_ife_hw_mgr_ctx *ctx, - int reset_type, bool power_on_rst) + int reset_type) { int i; int rc = 0; @@ -966,7 +986,6 @@ static int cam_ife_hw_mgr_reset_csid( reset_args.reset_type = reset_type; reset_args.node_res = hw_mgr_res->hw_res[i]; - reset_args.power_on_reset = power_on_rst; rc = hw_intf->hw_ops.reset(hw_intf->hw_priv, &reset_args, sizeof(reset_args)); if (rc) @@ -1081,7 +1100,7 @@ static int cam_ife_mgr_csid_start_hw( start_args.start_only = start_only; start_args.is_drv_config_en = (bool) ctx->drv_path_idle_en; hw_intf->hw_ops.start(hw_intf->hw_priv, &start_args, - sizeof(start_args)); + sizeof(start_args)); } } @@ -1189,7 +1208,7 @@ static void cam_ife_hw_mgr_deinit_hw( hw_mgr = ctx->hw_mgr; if (hw_mgr->csid_global_reset_en) - cam_ife_hw_mgr_reset_csid(ctx, CAM_IFE_CSID_RESET_GLOBAL, false); + cam_ife_hw_mgr_reset_csid(ctx, CAM_IFE_CSID_RESET_GLOBAL); /* Deinit IFE CSID */ list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { @@ -1260,7 +1279,6 @@ static int cam_ife_hw_mgr_init_hw( struct cam_ife_hw_mgr_ctx *ctx) { struct cam_isp_hw_mgr_res *hw_mgr_res; - struct cam_ife_hw_mgr *hw_mgr; int rc = 0, i; /* INIT IFE SRC */ @@ -1340,16 +1358,6 @@ static int cam_ife_hw_mgr_init_hw( } } - hw_mgr = ctx->hw_mgr; - if (hw_mgr->csid_global_reset_en) { - rc = cam_ife_hw_mgr_reset_csid(ctx, - CAM_IFE_CSID_RESET_GLOBAL, true); - if (rc) { - CAM_ERR(CAM_ISP, "CSID reset failed, ctx_idx:%u", ctx->ctx_index); - goto deinit; - } - } - /* Check if any cache needs to be activated */ for (i = CAM_LLCC_SMALL_1; i < CAM_LLCC_MAX; i++) { if (ctx->flags.sys_cache_usage[i]) { @@ -2822,51 +2830,33 @@ static int cam_convert_res_id_to_hw_path(int res_id, int csid_res_id) } static int cam_ife_hw_mgr_acquire_sfe_hw( - bool use_lower_idx, - struct cam_ife_hw_mgr_ctx *ife_ctx, - struct cam_sfe_acquire_args *sfe_acquire) + bool is_right_hw, + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_sfe_acquire_args *sfe_acquire) { - int i, rc = -EINVAL; + int rc = -EINVAL; + uint32_t hw_idx; struct cam_hw_intf *hw_intf = NULL; struct cam_ife_hw_mgr *ife_hw_mgr = ife_ctx->hw_mgr; - /* Use lower index for RDIs in case of dual */ - if ((ife_ctx->flags.is_fe_enabled) || (use_lower_idx)) { - for (i = 0; i < CAM_SFE_HW_NUM_MAX; i++) { - if (!ife_hw_mgr->sfe_devices[i]) - continue; + if (is_right_hw) + hw_idx = ife_ctx->right_hw_idx; + else + hw_idx = ife_ctx->left_hw_idx; - hw_intf = ife_hw_mgr->sfe_devices[i]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - sfe_acquire, - sizeof(struct cam_sfe_acquire_args)); - if (rc) { - CAM_DBG(CAM_ISP, - "Can not acquire SFE HW: %d for res: %d ctx_idx: %u", - i, sfe_acquire->sfe_in.res_id, ife_ctx->ctx_index); - continue; - } else { - break; - } - } - } else { - for (i = CAM_SFE_HW_NUM_MAX - 1; i >= 0; i--) { - if (!ife_hw_mgr->sfe_devices[i]) - continue; + if ((hw_idx >= CAM_SFE_HW_NUM_MAX) || !ife_hw_mgr->sfe_devices[hw_idx]) { + CAM_ERR(CAM_ISP, "the hw index:%d is wrong"); + return -EINVAL; + } - hw_intf = ife_hw_mgr->sfe_devices[i]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - sfe_acquire, - sizeof(struct cam_sfe_acquire_args)); - if (rc) { - CAM_DBG(CAM_ISP, - "Can not acquire SFE HW: %d for res: %d ctx_idx: %u", - i, sfe_acquire->sfe_in.res_id, ife_ctx->ctx_index); - continue; - } else { - break; - } - } + hw_intf = ife_hw_mgr->sfe_devices[hw_idx]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + sfe_acquire, + sizeof(struct cam_sfe_acquire_args)); + if (rc) { + CAM_DBG(CAM_ISP, + "Can not acquire SFE HW: %d for res: %d ctx_idx: %u", + hw_idx, sfe_acquire->sfe_in.res_id, ife_ctx->ctx_index); } return rc; @@ -2877,7 +2867,6 @@ static int cam_ife_hw_mgr_acquire_res_sfe_src_util( struct cam_isp_in_port_generic_info *in_port, struct cam_isp_hw_mgr_res *csid_res, struct cam_sfe_acquire_args *sfe_acquire, - bool is_rdi, uint32_t *acquired_hw_id, uint32_t *acquired_hw_path) { @@ -2909,9 +2898,7 @@ static int cam_ife_hw_mgr_acquire_res_sfe_src_util( sfe_src_res->use_wm_pack = csid_res->use_wm_pack; for (i = sfe_src_res->is_dual_isp; i >= 0; i--) { - rc = cam_ife_hw_mgr_acquire_sfe_hw( - ((is_rdi) && (!sfe_src_res->is_dual_isp) && - (ife_ctx->flags.is_dual)), + rc = cam_ife_hw_mgr_acquire_sfe_hw(i, ife_ctx, sfe_acquire); if (rc || !sfe_acquire->sfe_in.rsrc_node) { @@ -2967,12 +2954,12 @@ static int cam_ife_hw_mgr_acquire_res_sfe_src( int rc = -1; struct cam_sfe_acquire_args sfe_acquire; struct cam_isp_hw_mgr_res *csid_res; - bool is_rdi = false; long sfe_required_res = 0; uint32_t sfe_acquired_res = 0; uint32_t sfe_res_id = 0; struct cam_ife_hw_mgr *hw_mgr; struct cam_isp_hw_mgr_res *csid_res_map[CAM_ISP_HW_SFE_IN_MAX]; + int valid_id = 0; hw_mgr = ife_ctx->hw_mgr; list_for_each_entry(csid_res, &ife_ctx->res_list_ife_csid, list) { @@ -3019,9 +3006,11 @@ static int cam_ife_hw_mgr_acquire_res_sfe_src( * 1. No read count * 2. Dynamic switch from SHDR-->HDR and HDR-->SHDR is possible */ + valid_id = cam_ife_mgr_get_first_valid_csid_id(); if ((!(sfe_required_res & BIT(CAM_ISP_HW_SFE_IN_PIX))) && (!in_port->ife_rd_count || in_port->dynamic_hdr_switch_en) && - (BIT(csid_res->res_id) == hw_mgr->csid_hw_caps[0].sfe_ipp_input_rdi_res)) { + (BIT(csid_res->res_id) == + hw_mgr->csid_hw_caps[valid_id].sfe_ipp_input_rdi_res)) { sfe_required_res |= BIT(CAM_ISP_HW_SFE_IN_PIX); csid_res_map[CAM_ISP_HW_SFE_IN_PIX] = csid_res; } @@ -3034,26 +3023,9 @@ static int cam_ife_hw_mgr_acquire_res_sfe_src( sfe_res_id = ffs(sfe_required_res) - 1; clear_bit(sfe_res_id, &sfe_required_res); - switch (sfe_res_id) { - case CAM_ISP_HW_SFE_IN_PIX: - is_rdi = false; - break; - case CAM_ISP_HW_SFE_IN_RDI0: - case CAM_ISP_HW_SFE_IN_RDI1: - case CAM_ISP_HW_SFE_IN_RDI2: - case CAM_ISP_HW_SFE_IN_RDI3: - case CAM_ISP_HW_SFE_IN_RDI4: - is_rdi = true; - break; - default: - CAM_ERR(CAM_ISP, "Wrong CSID Path Resource ID: %u ctx_idx: %u", - sfe_res_id, ife_ctx->ctx_index); - goto err; - } - sfe_acquire.sfe_in.res_id = sfe_res_id; rc = cam_ife_hw_mgr_acquire_res_sfe_src_util(ife_ctx, in_port, - csid_res_map[sfe_res_id], &sfe_acquire, is_rdi, + csid_res_map[sfe_res_id], &sfe_acquire, acquired_hw_id, acquired_hw_path); if (rc) goto err; @@ -3096,6 +3068,9 @@ static bool cam_ife_mgr_check_can_use_lite( goto end; } + if (ife_ctx->flags.is_fe_enabled || ife_ctx->flags.dsp_enabled) + can_use_lite = false; + CAM_DBG(CAM_ISP, "in_port lite hint %d, rdi_only: %d can_use_lite: %d res_id: %u ctx_idx: %u", csid_acquire->in_port->can_use_lite, @@ -3110,19 +3085,23 @@ static int cam_ife_hw_mgr_acquire_res_ife_bus_rd( struct cam_ife_hw_mgr_ctx *ife_ctx, struct cam_isp_in_port_generic_info *in_port) { - int rc = -EINVAL, j; - int i = CAM_ISP_HW_SPLIT_LEFT; - struct cam_vfe_acquire_args vfe_acquire; - struct cam_isp_hw_mgr_res *ife_bus_rd_res; - struct cam_hw_intf *hw_intf; - struct cam_ife_hw_mgr *ife_hw_mgr; + int i, rc = -EINVAL; + struct cam_vfe_acquire_args vfe_acquire; + struct cam_isp_hw_mgr_res *ife_bus_rd_res; + struct cam_hw_intf *hw_intf; + struct cam_ife_hw_mgr *ife_hw_mgr; ife_hw_mgr = ife_ctx->hw_mgr; + if (!ife_hw_mgr->ife_devices[ife_ctx->left_hw_idx]) { + CAM_ERR(CAM_ISP, "ife_devices[%d] is NULL", ife_ctx->left_hw_idx); + return -ENODEV; + } + rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, &ife_bus_rd_res); if (rc) { CAM_ERR(CAM_ISP, "No more free hw mgr resource, ctx_idx: %u", ife_ctx->ctx_index); - goto end; + return -ENODEV; } vfe_acquire.rsrc_type = CAM_ISP_RESOURCE_VFE_BUS_RD; @@ -3136,64 +3115,87 @@ static int cam_ife_hw_mgr_acquire_res_ife_bus_rd( vfe_acquire.vfe_bus_rd.res_id = CAM_ISP_HW_VFE_IN_RD; vfe_acquire.vfe_bus_rd.unpacker_fmt = in_port->fe_unpacker_fmt; - for (j = 0; j < CAM_IFE_HW_NUM_MAX; j++) { - if (!ife_hw_mgr->ife_devices[j]) - continue; + if (ife_ctx->left_hw_idx >= CAM_IFE_HW_NUM_MAX) { + if (in_port->ife_rd_count) { + for (i = CAM_IFE_HW_NUM_MAX - 1; i >= 0; i--) { + if (!ife_hw_mgr->ife_devices[i]) + continue; - hw_intf = ife_hw_mgr->ife_devices[j]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &vfe_acquire, sizeof(struct cam_vfe_acquire_args)); + hw_intf = ife_hw_mgr->ife_devices[i]->hw_intf; + if (ife_hw_mgr->ife_dev_caps[hw_intf->hw_idx].is_lite) + continue; - if (!rc) { - ife_bus_rd_res->hw_res[i] = - vfe_acquire.vfe_bus_rd.rsrc_node; - - CAM_DBG(CAM_ISP, "Acquired VFE:%d BUS RD for LEFT, ctx_idx: %u", - j, ife_ctx->ctx_index); - break; + vfe_acquire.vfe_bus_rd.rsrc_node = NULL; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, sizeof(struct cam_vfe_acquire_args)); + if (!rc && vfe_acquire.vfe_bus_rd.rsrc_node) + goto acquire_successful; + else + CAM_ERR(CAM_ISP, + "IFE[%d] acquire failed (rc=%d), ctx_idx: %u", + i, rc, ife_ctx->ctx_index); + } + CAM_ERR(CAM_ISP, "Can't find free IFE for ctx_idx: %u", + ife_ctx->ctx_index); + goto put_res; + } else { + rc = -ENODEV; + CAM_ERR(CAM_ISP, + "The acquired hw idx %d is invalid and it isn't FE usecase", + ife_ctx->left_hw_idx); + goto put_res; } } - if (j == CAM_IFE_HW_NUM_MAX || !vfe_acquire.vfe_bus_rd.rsrc_node) { - CAM_ERR(CAM_ISP, "Failed to acquire VFE:%d BUS RD for LEFT, ctx_idx: %u", - j, ife_ctx->ctx_index); + if (!ife_hw_mgr->ife_devices[ife_ctx->left_hw_idx]) { + CAM_ERR(CAM_ISP, "IFE device %d is NULL.", + ife_ctx->left_hw_idx); goto put_res; } + hw_intf = ife_hw_mgr->ife_devices[ife_ctx->left_hw_idx]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, sizeof(struct cam_vfe_acquire_args)); + + if (rc || !vfe_acquire.vfe_bus_rd.rsrc_node) { + rc = -ENODEV; + CAM_ERR(CAM_ISP, "Failed to acquire VFE:%d BUS RD for LEFT, ctx_idx: %u", + ife_ctx->left_hw_idx, ife_ctx->ctx_index); + goto put_res; + } + +acquire_successful: + ife_bus_rd_res->hw_res[CAM_ISP_HW_SPLIT_LEFT] = + vfe_acquire.vfe_bus_rd.rsrc_node; + + CAM_DBG(CAM_ISP, "Acquired VFE:%d BUS RD for LEFT, ctx_idx: %u", + ife_ctx->left_hw_idx, ife_ctx->ctx_index); + + ife_ctx->left_hw_idx = hw_intf->hw_idx; ife_bus_rd_res->res_type = vfe_acquire.rsrc_type; ife_bus_rd_res->res_id = vfe_acquire.vfe_in.res_id; ife_bus_rd_res->is_dual_isp = (uint32_t)ife_ctx->flags.is_dual; cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_in_rd, &ife_bus_rd_res); if (ife_ctx->flags.is_dual) { - for (j = 0; j < CAM_IFE_HW_NUM_MAX; j++) { - if (!ife_hw_mgr->ife_devices[j]) - continue; - - if (j == ife_bus_rd_res->hw_res[i]->hw_intf->hw_idx) - continue; - - hw_intf = ife_hw_mgr->ife_devices[j]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &vfe_acquire, - sizeof(struct cam_vfe_acquire_args)); - - if (!rc) { - ife_bus_rd_res->hw_res[++i] = - vfe_acquire.vfe_bus_rd.rsrc_node; - - CAM_DBG(CAM_ISP, - "Acquired VFE:%d BUS RD for RIGHT, ctx: %u", - j, ife_ctx->ctx_index); - break; - } + if (!ife_hw_mgr->ife_devices[ife_ctx->right_hw_idx]) { + CAM_ERR(CAM_ISP, "ife_devices[%d] is NULL", ife_ctx->right_hw_idx); + goto put_res; } - if (j == CAM_IFE_HW_NUM_MAX || - !vfe_acquire.vfe_bus_rd.rsrc_node) { - CAM_ERR(CAM_ISP, "Failed to acquire VFE:%d BUS RD for RIGHT, ctx: %u", - j, ife_ctx->ctx_index); - goto end; + hw_intf = ife_hw_mgr->ife_devices[ife_ctx->right_hw_idx]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); + + if (!rc && vfe_acquire.vfe_bus_rd.rsrc_node) { + ife_bus_rd_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT] = + vfe_acquire.vfe_bus_rd.rsrc_node; + ife_ctx->right_hw_idx = hw_intf->hw_idx; + + CAM_DBG(CAM_ISP, + "Acquired VFE:%d BUS RD for RIGHT, ctx: %u", + ife_ctx->right_hw_idx, ife_ctx->ctx_index); } } @@ -3201,7 +3203,6 @@ static int cam_ife_hw_mgr_acquire_res_ife_bus_rd( put_res: cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &ife_bus_rd_res); -end: return rc; } @@ -3210,18 +3211,17 @@ static int cam_ife_hw_mgr_acquire_sfe_bus_rd( struct cam_isp_in_port_generic_info *in_port) { int rc = -1, i; - uint32_t acquired_cnt = CAM_ISP_HW_SPLIT_LEFT; struct cam_sfe_acquire_args sfe_acquire; struct cam_ife_hw_mgr *ife_hw_mgr; struct cam_hw_intf *hw_intf; - struct cam_isp_hw_mgr_res *sfe_rd_res, *sfe_res_iterator; + struct cam_isp_hw_mgr_res *sfe_rd_res; ife_hw_mgr = ife_ctx->hw_mgr; rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, &sfe_rd_res); if (rc) { CAM_ERR(CAM_ISP, "No more free hw mgr resource, ctx_idx: %u", ife_ctx->ctx_index); - goto err; + return rc; } if (!cam_ife_hw_mgr_is_sfe_rd_res(in_port->sfe_in_path_type)) { @@ -3245,73 +3245,51 @@ static int cam_ife_hw_mgr_acquire_sfe_bus_rd( sfe_acquire.sfe_rd.res_id = in_port->sfe_in_path_type; sfe_acquire.sfe_rd.secure_mode = in_port->secure_mode; - list_for_each_entry(sfe_res_iterator, &ife_ctx->res_list_ife_in_rd, - list) { - for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { - if (!sfe_res_iterator->hw_res[i]) - continue; + if (ife_ctx->left_hw_idx >= CAM_SFE_HW_NUM_MAX) { + if (in_port->ife_rd_count) { + for (i = 0; i < CAM_SFE_HW_NUM_MAX; i++) { + if (!ife_hw_mgr->sfe_devices[i]) + continue; - /* Check for secure */ - if (sfe_res_iterator->is_secure != in_port->secure_mode) - continue; - - hw_intf = sfe_res_iterator->hw_res[i]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &sfe_acquire, sizeof(sfe_acquire)); - if (rc) { - CAM_DBG(CAM_ISP, - "No SFE RD rsrc: 0x%x from hw: %u ctx_idx: %u", - in_port->sfe_in_path_type, - hw_intf->hw_idx, ife_ctx->ctx_index); - continue; + hw_intf = ife_hw_mgr->sfe_devices[i]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &sfe_acquire, sizeof(struct cam_sfe_acquire_args)); + if (rc) + continue; + else + break; } - - sfe_rd_res->hw_res[acquired_cnt++] = - sfe_acquire.sfe_rd.rsrc_node; - - CAM_DBG(CAM_ISP, - "ctx_idx: %u acquired from old SFE(%s): %u path: 0x%x successfully", - ife_ctx->ctx_index, (i == 0) ? "left" : "right", - hw_intf->hw_idx, in_port->sfe_in_path_type); - - /* With SFE the below condition should never be met */ - if ((in_port->usage_type) && (acquired_cnt == 1)) - continue; - - if (acquired_cnt) - goto acquire_successful; + } else { + rc = -ENODEV; + CAM_ERR(CAM_ISP, + "The acquired hw idx %d is invalid and it isn't FE usecase", + ife_ctx->left_hw_idx); + goto put_res; + } + } else { + if (!ife_hw_mgr->sfe_devices[ife_ctx->left_hw_idx]) { + rc = -ENODEV; + CAM_ERR(CAM_ISP, "No valid sfe devices for idx:%d", + ife_ctx->left_hw_idx); + goto put_res; } - } - /* - * SFEx can be connected to any CSID/IFE in - * single/dual use cases hence always iterating - * from 0 to HW max. IFE also will reserve from lower idx - * as well since SFE works with FULL IFEs only - */ - for (i = 0; i < CAM_SFE_HW_NUM_MAX; i++) { - if (!ife_hw_mgr->sfe_devices[i]) - continue; - - hw_intf = ife_hw_mgr->sfe_devices[i]->hw_intf; + hw_intf = ife_hw_mgr->sfe_devices[ife_ctx->left_hw_idx]->hw_intf; rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &sfe_acquire, sizeof(struct cam_sfe_acquire_args)); - if (rc) - continue; - else - break; } if (!sfe_acquire.sfe_rd.rsrc_node || rc) { + rc = -ENODEV; CAM_ERR(CAM_ISP, "Failed to acquire SFE RD: 0x%x, ctx_idx: %u", in_port->sfe_in_path_type, ife_ctx->ctx_index); goto put_res; } - sfe_rd_res->hw_res[acquired_cnt++] = sfe_acquire.sfe_rd.rsrc_node; + sfe_rd_res->hw_res[CAM_ISP_HW_SPLIT_LEFT] = sfe_acquire.sfe_rd.rsrc_node; + ife_ctx->left_hw_idx = hw_intf->hw_idx; -acquire_successful: CAM_DBG(CAM_ISP, "SFE RD left [%u] acquired success for path: %u is_dual: %d res: %s res_id: 0x%x ctx_idx: %u", sfe_rd_res->hw_res[0]->hw_intf->hw_idx, in_port->sfe_in_path_type, @@ -3324,43 +3302,9 @@ acquire_successful: sfe_rd_res->is_secure = in_port->secure_mode; cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_in_rd, &sfe_rd_res); - /* DUAL SFE for Fetch engine - unused for now */ - if (in_port->usage_type && acquired_cnt == 1) { - sfe_acquire.sfe_rd.rsrc_node = NULL; - for (i = 0; i < CAM_SFE_HW_NUM_MAX; i++) { - if (!ife_hw_mgr->sfe_devices[i]) - continue; - - if (i == sfe_rd_res->hw_res[0]->hw_intf->hw_idx) - continue; - - hw_intf = ife_hw_mgr->sfe_devices[i]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &sfe_acquire, sizeof(sfe_acquire)); - if (rc) - continue; - else - break; - } - - if (!sfe_acquire.sfe_rd.rsrc_node || rc) { - CAM_ERR(CAM_ISP, - "Can not acquire SFE RD right resource, ctx_idx: %u", - ife_ctx->ctx_index); - goto err; - } - - sfe_rd_res->hw_res[1] = sfe_acquire.sfe_rd.rsrc_node; - CAM_DBG(CAM_ISP, - "SFE right [%u] acquire success for res: 0x%x ctx_idx: %u", - sfe_rd_res->hw_res[1]->hw_intf->hw_idx, in_port->sfe_in_path_type, - ife_ctx->ctx_index); - } - return 0; put_res: cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &sfe_rd_res); -err: return rc; } @@ -3370,12 +3314,19 @@ static int cam_ife_hw_mgr_acquire_ife_src_for_sfe( bool acquire_lcr, uint32_t *acquired_hw_id, uint32_t *acquired_hw_path) { - int rc = -1, i; + int rc = -1; struct cam_vfe_acquire_args vfe_acquire; struct cam_isp_hw_mgr_res *ife_src_res; struct cam_hw_intf *hw_intf = NULL; struct cam_ife_hw_mgr *ife_hw_mgr; + if ((ife_ctx->left_hw_idx >= CAM_SFE_HW_NUM_MAX) || + (ife_ctx->flags.is_dual && (ife_ctx->right_hw_idx >= CAM_SFE_HW_NUM_MAX))) { + CAM_ERR(CAM_ISP, "the hw index:[%d - %d] is wrong", + ife_ctx->left_hw_idx, ife_ctx->right_hw_idx); + goto end; + } + ife_hw_mgr = ife_ctx->hw_mgr; rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, &ife_src_res); @@ -3417,40 +3368,29 @@ static int cam_ife_hw_mgr_acquire_ife_src_for_sfe( vfe_acquire.vfe_in.is_dual = (uint32_t)ife_ctx->flags.is_dual; - ife_src_res->res_type = vfe_acquire.rsrc_type; ife_src_res->res_id = vfe_acquire.vfe_in.res_id; ife_src_res->is_dual_isp = (uint32_t)ife_ctx->flags.is_dual; - for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { - if (!ife_hw_mgr->ife_devices[i]) - continue; - if (i != ife_ctx->left_hw_idx) - continue; + hw_intf = ife_hw_mgr->ife_devices[ife_ctx->left_hw_idx]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); - hw_intf = ife_hw_mgr->ife_devices[i]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &vfe_acquire, - sizeof(struct cam_vfe_acquire_args)); - if (rc) - continue; - else - break; - } - - if (i == CAM_IFE_HW_NUM_MAX || rc || - !vfe_acquire.vfe_in.rsrc_node) { + if (rc || !vfe_acquire.vfe_in.rsrc_node) { CAM_ERR(CAM_ISP, "Unable to acquire LEFT IFE res: %d ctx_idx: %u", vfe_acquire.vfe_in.res_id, ife_ctx->ctx_index); - return -EAGAIN; + rc = -EINVAL; + goto put_res; } - ife_src_res->hw_res[0] = vfe_acquire.vfe_in.rsrc_node; + ife_src_res->hw_res[CAM_ISP_HW_SPLIT_LEFT] = vfe_acquire.vfe_in.rsrc_node; cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_src, &ife_src_res); *acquired_hw_id |= cam_convert_hw_idx_to_ife_hw_num(hw_intf->hw_idx); - acquired_hw_path[0] |= cam_convert_res_id_to_hw_path(ife_src_res->hw_res[0]->res_id, -1); + acquired_hw_path[0] |= cam_convert_res_id_to_hw_path( + ife_src_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]->res_id, -1); CAM_DBG(CAM_ISP, "acquire success LEFT IFE: %d res type: 0x%x res: %s res id: 0x%x ctx_idx: %u", @@ -3465,39 +3405,24 @@ static int cam_ife_hw_mgr_acquire_ife_src_for_sfe( CAM_ISP_HW_SYNC_SLAVE; vfe_acquire.vfe_in.dual_hw_idx = ife_ctx->left_hw_idx; - for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { - if (!ife_hw_mgr->ife_devices[i]) - continue; - if (i == ife_src_res->hw_res[0]->hw_intf->hw_idx) - continue; + hw_intf = ife_hw_mgr->ife_devices[ife_ctx->right_hw_idx]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); - if (i != ife_ctx->right_hw_idx) - continue; - - hw_intf = ife_hw_mgr->ife_devices[i]->hw_intf; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &vfe_acquire, - sizeof(struct cam_vfe_acquire_args)); - if (rc) - continue; - else - break; - } - - if (i == CAM_IFE_HW_NUM_MAX || rc || - !vfe_acquire.vfe_in.rsrc_node) { + if (rc || !vfe_acquire.vfe_in.rsrc_node) { CAM_ERR(CAM_ISP, "Unable to acquire right IFE res: %u, ctx_idx: %u", vfe_acquire.vfe_in.res_id, ife_ctx->ctx_index); - rc = -EAGAIN; - goto end; + rc = -EINVAL; + goto put_res; } - ife_src_res->hw_res[1] = vfe_acquire.vfe_in.rsrc_node; + ife_src_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT] = vfe_acquire.vfe_in.rsrc_node; *acquired_hw_id |= cam_convert_hw_idx_to_ife_hw_num(hw_intf->hw_idx); acquired_hw_path[1] |= cam_convert_res_id_to_hw_path( - ife_src_res->hw_res[0]->res_id, -1); + ife_src_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT]->res_id, -1); CAM_DBG(CAM_ISP, "acquire success RIGHT IFE: %u res type: 0x%x res: %s res id: 0x%x ctx_idx: %u", hw_intf->hw_idx, @@ -3508,6 +3433,8 @@ static int cam_ife_hw_mgr_acquire_ife_src_for_sfe( return 0; +put_res: + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &ife_src_res); end: /* release resource at the entry function */ return rc; @@ -3710,11 +3637,11 @@ static int cam_ife_hw_mgr_acquire_csid_hw( return -EINVAL; } - if (ife_ctx->flags.is_fe_enabled || ife_ctx->flags.dsp_enabled) - is_start_lower_idx = true; - ife_hw_mgr = ife_ctx->hw_mgr; + if (ife_ctx->ctx_type == CAM_IFE_CTX_TYPE_SFE) + is_start_lower_idx = true; + if (in_port->num_out_res) out_port = &(in_port->data[0]); @@ -3754,6 +3681,14 @@ static int cam_ife_hw_mgr_acquire_csid_hw( continue; } + if (csid_caps->is_ife_sfe_mapped && + (ife_ctx->ctx_type == CAM_IFE_CTX_TYPE_SFE) && + !ife_hw_mgr->sfe_devices[hw_intf->hw_idx]) { + CAM_DBG(CAM_ISP, "No sfe_device with idx: %d, ctx_idx: %u", + hw_intf->hw_idx, ife_ctx->ctx_index); + continue; + } + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, csid_acquire, sizeof(*csid_acquire)); if (rc) { @@ -3788,6 +3723,14 @@ static int cam_ife_hw_mgr_acquire_csid_hw( compat_count++; + if (ife_hw_mgr->csid_hw_caps[hw_intf->hw_idx].is_ife_sfe_mapped && + (ife_ctx->ctx_type == CAM_IFE_CTX_TYPE_SFE) && + !ife_hw_mgr->sfe_devices[hw_intf->hw_idx]) { + CAM_DBG(CAM_ISP, "No sfe_device with idx: %d, ctx_idx: %u", + hw_intf->hw_idx, ife_ctx->ctx_index); + continue; + } + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, csid_acquire, sizeof(struct cam_csid_hw_reserve_resource_args)); if (!rc) @@ -3813,13 +3756,14 @@ static bool cam_ife_hw_mgr_is_need_csid_ipp( { struct cam_ife_hw_mgr *hw_mgr; bool need = true; - + int valid_id = 0; hw_mgr = ife_ctx->hw_mgr; + valid_id = cam_ife_mgr_get_first_valid_csid_id(); if (!(in_port->ipp_count || in_port->lcr_count)) need = false; else if (ife_ctx->ctx_type == CAM_IFE_CTX_TYPE_SFE && - ((hw_mgr->csid_hw_caps[0].sfe_ipp_input_rdi_res && !in_port->usage_type) || + ((hw_mgr->csid_hw_caps[valid_id].sfe_ipp_input_rdi_res && !in_port->usage_type) || in_port->ife_rd_count)) need = false; @@ -4094,7 +4038,8 @@ static int cam_ife_hw_mgr_acquire_csid_rdi_util( if (out_port->res_type == CAM_ISP_SFE_OUT_RES_RDI_0) { csid_acquire.sec_evt_config.en_secondary_evt = true; csid_acquire.sec_evt_config.evt_type = - CAM_IFE_CSID_EVT_EPOCH; + CAM_IFE_CSID_EVT_EPOCH | + CAM_IFE_CSID_EVT_SENSOR_SYNC_FRAME_DROP; CAM_DBG(CAM_ISP, "Secondary EPOCH & frame drop evt enabled for path: 0x%x, ctx_idx: %u", out_port->res_type, ife_ctx->ctx_index); @@ -4169,11 +4114,13 @@ static int cam_ife_hw_mgr_get_csid_rdi_for_sfe_ipp_input( struct cam_ife_hw_mgr *hw_mgr; uint32_t res_id = CAM_IFE_PIX_PATH_RES_MAX; int rc = 0; + int valid_id; hw_mgr = ife_ctx->hw_mgr; - if (hw_mgr->csid_hw_caps[0].sfe_ipp_input_rdi_res && !in_port->usage_type) - res_id = ffs(hw_mgr->csid_hw_caps[0].sfe_ipp_input_rdi_res) - 1; + valid_id = cam_ife_mgr_get_first_valid_csid_id(); + if (hw_mgr->csid_hw_caps[valid_id].sfe_ipp_input_rdi_res && !in_port->usage_type) + res_id = ffs(hw_mgr->csid_hw_caps[valid_id].sfe_ipp_input_rdi_res) - 1; if ((res_id != CAM_IFE_PIX_PATH_RES_MAX) && (!(BIT(res_id) & (*acquired_rdi_res)))) { rc = cam_ife_hw_mgr_acquire_csid_rdi_util(ife_ctx, @@ -4825,6 +4772,8 @@ static int cam_ife_hw_mgr_acquire_offline_res_csid( goto put_res; } + csid_res->hw_res[CAM_ISP_HW_SPLIT_LEFT] = csid_acquire.node_res; + if (!ife_ctx->buf_done_controller && csid_acquire.buf_done_controller) ife_ctx->buf_done_controller = csid_acquire.buf_done_controller; @@ -4834,6 +4783,7 @@ static int cam_ife_hw_mgr_acquire_offline_res_csid( csid_res->is_dual_isp = 0; csid_res->hw_res[0] = csid_acquire.node_res; csid_res->hw_res[1] = NULL; + ife_ctx->left_hw_idx = csid_acquire.node_res->hw_intf->hw_idx; cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_csid, &csid_res); return 0; @@ -5042,21 +4992,6 @@ static int cam_ife_mgr_acquire_hw_for_ctx( return -EINVAL; } - if (in_port->ife_rd_count) { - if (ife_ctx->ctx_type == CAM_IFE_CTX_TYPE_SFE) - rc = cam_ife_hw_mgr_acquire_sfe_bus_rd( - ife_ctx, in_port); - else - rc = cam_ife_hw_mgr_acquire_res_ife_bus_rd( - ife_ctx, in_port); - if (rc) { - CAM_ERR(CAM_ISP, "Acquire %s BUS RD resource Failed, ctx_idx: %u", - (ife_ctx->ctx_type == - CAM_IFE_CTX_TYPE_SFE) ? "SFE" : "IFE", ife_ctx->ctx_index); - goto err; - } - } - /* get ife csid IPP resource */ if (cam_ife_hw_mgr_is_need_csid_ipp(ife_ctx, in_port)) { rc = cam_ife_hw_mgr_acquire_res_ife_csid_pxl(ife_ctx, @@ -5102,6 +5037,25 @@ static int cam_ife_mgr_acquire_hw_for_ctx( } } + CAM_DBG(CAM_ISP, "Acquired CSID resource, is_dual:%s left_hw_idx:%d right_hw_idx:%d", + CAM_BOOL_TO_YESNO(ife_ctx->flags.is_dual), + ife_ctx->left_hw_idx, ife_ctx->right_hw_idx); + + if (in_port->ife_rd_count) { + if (ife_ctx->ctx_type == CAM_IFE_CTX_TYPE_SFE) + rc = cam_ife_hw_mgr_acquire_sfe_bus_rd( + ife_ctx, in_port); + else + rc = cam_ife_hw_mgr_acquire_res_ife_bus_rd( + ife_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, "Acquire %s BUS RD resource Failed, ctx_idx: %u", + (ife_ctx->ctx_type == + CAM_IFE_CTX_TYPE_SFE) ? "SFE" : "IFE", ife_ctx->ctx_index); + goto err; + } + } + /* try acquire RDI for SFE cases without RDI out ports, * this is specifically for targets having RDI as input * to SFE IPP @@ -5241,8 +5195,8 @@ void cam_ife_cam_cdm_callback(uint32_t handle, void *userdata, NULL, false); } else { CAM_INFO(CAM_ISP, - "CDM delay, Skip dump req: %llu, cdm_req: %llu ctx_idx: %u", - req_id, ctx->cdm_userdata.request_id, ctx->ctx_index); + "CDM delay, Skip dump req: %llu, cdm_req: %llu ctx_idx: %u", + req_id, ctx->cdm_userdata.request_id, ctx->ctx_index); } } CAM_DBG(CAM_ISP, @@ -5681,6 +5635,8 @@ static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) ife_ctx->drv_path_idle_en = 0; ife_ctx->res_list_ife_out = NULL; ife_ctx->res_list_sfe_out = NULL; + ife_ctx->left_hw_idx = CAM_IFE_CSID_HW_NUM_MAX; + ife_ctx->right_hw_idx = CAM_IFE_CSID_HW_NUM_MAX; acquire_hw_info = (struct cam_isp_acquire_hw_info *) acquire_args->acquire_info; @@ -5763,6 +5719,7 @@ static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) } total_ports = total_pix_port + total_rdi_port + total_pd_port; + acquire_args->total_ports_acq = total_ports; ife_ctx->res_list_ife_out = kcalloc(total_ports, sizeof(struct cam_isp_hw_mgr_res), GFP_KERNEL); if (!ife_ctx->res_list_ife_out) { @@ -6076,6 +6033,7 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) uint32_t total_rdi_port = 0; uint32_t in_port_length = 0; uint32_t acquired_rdi_res = 0; + uint32_t total_ports = 0; CAM_DBG(CAM_ISP, "Enter..."); @@ -6101,8 +6059,8 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) isp_resource = (struct cam_isp_resource *)acquire_args->acquire_info; gen_port_info = kcalloc(acquire_args->num_acq, - sizeof(struct cam_isp_in_port_generic_info), - GFP_KERNEL); + sizeof(struct cam_isp_in_port_generic_info), + GFP_KERNEL); if (!gen_port_info) { CAM_ERR(CAM_ISP, "No memory available, ctx_idx: %u", ife_ctx->ctx_index); @@ -6183,6 +6141,9 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) } } + total_ports = total_pix_port + total_rdi_port + total_pd_port; + acquire_args->total_ports_acq = total_ports; + /* Check whether context has only RDI resource */ if (!total_pix_port || !total_pd_port) { ife_ctx->flags.is_rdi_only_context = true; @@ -7118,6 +7079,9 @@ static int cam_ife_mgr_config_hw( struct cam_ife_hw_mgr *ife_hw_mgr; unsigned long rem_jiffies = 0; bool is_cdm_hung = false; + size_t len = 0; + uint32_t *buf_addr = NULL, *buf_start = NULL, *buf_end = NULL; + uint32_t cmd_type = 0; if (!hw_mgr_priv || !config_hw_args) { CAM_ERR(CAM_ISP, @@ -7290,14 +7254,9 @@ skip_bw_clk_update: return rc; } - if (hw_update_data->mup_en) - CAM_INFO(CAM_ISP, - "Enter ctx id:%u num_hw_upd_entries %d request id: %llu rup_aup: 0x%x", - ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id, hw_update_data->configured_rup_aup); - else - CAM_DBG(CAM_ISP, - "Enter ctx id:%u num_hw_upd_entries %d request id: %llu", - ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id); + CAM_DBG(CAM_ISP, + "Enter ctx id:%u num_hw_upd_entries %d request id: %llu", + ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id); if (cfg->num_hw_update_entries > 0) { cdm_cmd = ctx->cdm_cmd; @@ -7356,6 +7315,41 @@ skip_bw_clk_update: cdm_cmd->cmd[i - skip].offset = cmd->offset; cdm_cmd->cmd[i - skip].len = cmd->len; cdm_cmd->cmd[i - skip].arbitrate = false; + + if (g_ife_hw_mgr.debug_cfg.enable_cdm_cmd_check) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "Enter cdm cmd_buf validation"); + rc = cam_packet_util_get_cmd_mem_addr( + cdm_cmd->cmd[i - skip].bl_addr.mem_handle, + &buf_addr, &len); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed to get buf_addr and len for mem_handle: %d ctx id: %u request id: %llu", + cdm_cmd->cmd[i - skip].bl_addr.mem_handle, + ctx->ctx_index, cfg->request_id); + continue; + } + + buf_start = (uint32_t *)((uint8_t *) buf_addr + + cdm_cmd->cmd[i - skip].offset); + buf_end = (uint32_t *)((uint8_t *) buf_start + + cdm_cmd->cmd[i - skip].len - 1); + cmd_type = ((uint32_t)(*buf_start) >> CAM_CDM_COMMAND_OFFSET); + if ((i == 0) && (cmd_type != CAM_CDM_CMD_CHANGE_BASE)) { + CAM_ERR(CAM_ISP, + "first cmd in cmd_buf is not change_base, cmd_type: %u ctx id: %u request id: %llu", + cmd_type, ctx->ctx_index, cfg->request_id); + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + return -EINVAL; + } + + if (cam_cdm_util_validate_cmd_buf(buf_start, buf_end)) { + CAM_ERR(CAM_ISP, + "found invalid cmd in cmd_buf, ctx id: %u request id: %llu", + ctx->ctx_index, cfg->request_id); + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + return -EINVAL; + } + } } cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; @@ -7368,8 +7362,8 @@ skip_bw_clk_update: g_ife_hw_mgr.mgr_common.cmd_iommu_hdl); if (rc) { CAM_ERR(CAM_ISP, - "Error sending buffers for request:%llu to presil, ctx=%u", - cfg->request_id, ctx->ctx_index); + "Error sending buffers for request:%llu to presil, ctx=%u", + cfg->request_id, ctx->ctx_index); return rc; } } @@ -7402,13 +7396,9 @@ skip_bw_clk_update: ctx->cdm_handle); rc = -ETIMEDOUT; } else { - CAM_INFO(CAM_ISP, + CAM_DBG(CAM_ISP, "Wq delayed but IRQ CDM done, ctx_index %u", ctx->ctx_index); - if (hw_update_data->mup_en) { - cam_cdm_dump_debug_registers( - ctx->cdm_handle); - } } } else { CAM_DBG(CAM_ISP, @@ -7948,10 +7938,6 @@ static void cam_ife_hw_mgr_set_hw_debug_config( csid_debug_args.csid_rx_capture_debug = hw_mgr->debug_cfg.rx_capture_debug; csid_debug_args.rx_capture_debug_set = hw_mgr->debug_cfg.rx_capture_debug_set; csid_debug_args.csid_testbus_debug = hw_mgr->debug_cfg.csid_test_bus; -#if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) - csid_debug_args.csid_dbg_fps = hw_mgr->debug_cfg.csid_dbg_fps; - csid_debug_args.dbg_mode_switch = hw_mgr->debug_cfg.dbg_mode_switch; -#endif /* Set SFE debug args */ sfe_debug_args.cache_config = false; @@ -7969,9 +7955,6 @@ static void cam_ife_hw_mgr_set_hw_debug_config( for (i = 0; i < hw_mgr->isp_caps.num_ife_perf_counters; i++) vfe_debug_args.vfe_perf_counter_val[i] = hw_mgr->debug_cfg.ife_perf_counter_val[i]; -#if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) - vfe_debug_args.vfe_dbg_fps = hw_mgr->debug_cfg.vfe_dbg_fps; -#endif /* Iterate over HW acquired for this stream and update debug config */ for (i = 0; i < ctx->num_base; i++) { @@ -8037,8 +8020,6 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) uint32_t primary_rdi_csid_res; struct cam_ife_csid_top_config_args csid_top_args = {0}; struct cam_hw_intf *hw_intf; - struct cam_isp_prepare_hw_update_data *hw_update_data; - struct cam_hw_config_args *cfg; primary_rdi_src_res = CAM_ISP_HW_VFE_IN_MAX; primary_rdi_out_res = g_ife_hw_mgr.isp_caps.max_vfe_out_res_type; @@ -8178,6 +8159,7 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) "SAFE SCM call failed:Check TZ/HYP dependency, ctx_idx: %u", ctx->ctx_index); rc = -EFAULT; + mutex_unlock(&g_ife_hw_mgr.ctx_mutex); goto deinit_hw; } } @@ -8204,13 +8186,6 @@ start_only: goto cdm_streamoff; } - if (start_isp->is_internal_start) { - cfg = &start_isp->hw_config; - hw_update_data = (struct cam_isp_prepare_hw_update_data *)cfg->priv; - CAM_INFO(CAM_ISP, "Req: %lld ctx: %u rup_aup_mup: 0x%x", cfg->request_id, - ctx->ctx_index, hw_update_data->configured_rup_aup); - } - CAM_DBG(CAM_ISP, "START IFE OUT ... in ctx id:%u", ctx->ctx_index); /* start the IFE out devices */ @@ -8383,7 +8358,7 @@ static int cam_ife_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) CAM_DBG(CAM_ISP, "Reset CSID and VFE, ctx_idx: %u", ctx->ctx_index); - rc = cam_ife_hw_mgr_reset_csid(ctx, CAM_IFE_CSID_RESET_PATH, false); + rc = cam_ife_hw_mgr_reset_csid(ctx, CAM_IFE_CSID_RESET_PATH); if (rc) { CAM_ERR(CAM_ISP, "Failed to reset CSID:%d rc: %d ctx_idx: %u", @@ -8910,8 +8885,9 @@ static int cam_isp_scratch_buf_update_util( if (buffer_info->offset >= size) { CAM_ERR(CAM_ISP, - "Invalid scratch buffer offset 0x%u", - buffer_info->offset); + "Invalid scratch buffer offset:%u size:%u mmu_hdl:%u hdl:%d res_type:0x%x", + buffer_info->offset, size, mmu_hdl, buffer_info->mem_handle, + buffer_info->resource_type); rc = -EINVAL; return rc; } @@ -9588,13 +9564,12 @@ static int cam_isp_blob_csid_dynamic_switch_update( ctx = prepare->ctxt_to_hw_map; ife_hw_mgr = ctx->hw_mgr; - prepare_hw_data = (struct cam_isp_prepare_hw_update_data *)prepare->priv; CAM_INFO(CAM_ISP, - "request_id: %lld op_code: %u csid mup value=%u, ctx_idx: %u", - prepare->packet->header.request_id, prepare_hw_data->packet_opcode_type, - mup_config->mup, ctx->ctx_index); + "csid mup value=%u, ctx_idx: %u", mup_config->mup, ctx->ctx_index); + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; prepare_hw_data->mup_en = true; prepare_hw_data->mup_val = mup_config->mup; @@ -9624,11 +9599,6 @@ static int cam_isp_blob_csid_dynamic_switch_update( hw_intf = ife_hw_mgr->csid_devices[ctx->base[i].idx]; if (hw_intf && hw_intf->hw_ops.process_cmd) { -#if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_I2C) - CAM_INFO(CAM_ISP, "[SEN_DBG] CSID[%u] MUP %u reqId %lld", - hw_intf->hw_idx, prepare_hw_data->mup_val, prepare->packet->header.request_id); -#endif - rc = hw_intf->hw_ops.process_cmd( hw_intf->hw_priv, CAM_ISP_HW_CMD_CSID_DYNAMIC_SWITCH_UPDATE, @@ -9637,17 +9607,6 @@ static int cam_isp_blob_csid_dynamic_switch_update( if (rc) CAM_ERR(CAM_ISP, "Dynamic switch update failed, ctx_idx: %u", ctx->ctx_index); -#if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) - if (rc == 0 && - (g_ife_hw_mgr.debug_cfg.dbg_mode_switch == 1)) { - uint32_t sof_irq_en = 1; - rc = hw_intf->hw_ops.process_cmd( - hw_intf->hw_priv, - CAM_IFE_CSID_SOF_IRQ_DEBUG_FOR_MODESWITCH, - &sof_irq_en, - sizeof(uint32_t)); - } -#endif } } @@ -10134,7 +10093,7 @@ static int cam_isp_blob_vfe_out_update( struct cam_isp_vfe_wm_config *wm_config; struct cam_kmd_buf_info *kmd_buf_info; struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_isp_hw_mgr_res *isp_out_res = NULL; + struct cam_isp_hw_mgr_res *isp_out_res; struct cam_hw_intf *hw_intf = NULL; bool is_sfe_rd = false; uint32_t res_id_out, i; @@ -10216,27 +10175,11 @@ static int cam_isp_blob_vfe_out_update( return rc; } - if (ctx->sfe_out_map[res_id_out] == 0xFF) { - CAM_ERR(CAM_ISP, "Invalid index: %d for out_map", res_id_out); - return -EINVAL; - } - isp_out_res = &ctx->res_list_sfe_out[ctx->sfe_out_map[res_id_out]]; } else { - - if (ctx->vfe_out_map[res_id_out] == 0xFF) { - CAM_ERR(CAM_ISP, "Invalid index: %d for out_map", res_id_out); - return -EINVAL; - } - isp_out_res = &ctx->res_list_ife_out[ctx->vfe_out_map[res_id_out]]; } - if (!isp_out_res) { - CAM_ERR(CAM_ISP, "Invalid hw_mgr res, ctx_idx: %u", ctx->ctx_index); - return -EINVAL; - } - hw_intf = cam_ife_hw_mgr_get_hw_intf(blob_info->base_info); if (!hw_intf || blob_info->base_info->split_id >= CAM_ISP_HW_SPLIT_MAX) { CAM_ERR(CAM_ISP, @@ -11875,6 +11818,7 @@ static int cam_ife_mgr_util_insert_frame_header( uint32_t frame_header_iova, padded_bytes = 0; size_t len; struct cam_ife_hw_mgr *hw_mgr = &g_ife_hw_mgr; + struct cam_smmu_buffer_tracker *buf_track_entry; mmu_hdl = cam_mem_is_secure_buf( kmd_buf->handle) ? @@ -11892,8 +11836,13 @@ static int cam_ife_mgr_util_insert_frame_header( if (kmd_buf->offset >= len) { CAM_ERR(CAM_ISP, - "Invalid kmd buffer offset 0x%u", + "Invalid kmd buffer offset %u", kmd_buf->offset); + if (buf_tracker) { + buf_track_entry = list_first_entry_or_null(buf_tracker, + struct cam_smmu_buffer_tracker, list); + cam_smmu_buffer_tracker_buffer_putref(buf_track_entry); + } rc = -EINVAL; return rc; } @@ -12800,7 +12749,6 @@ static int cam_ife_mgr_csid_add_reg_update(struct cam_ife_hw_mgr_ctx *ctx, { int i; int rc = 0; - bool rup_done = false; uint32_t hw_idx; struct cam_ife_hw_mgr *hw_mgr; struct cam_isp_hw_mgr_res *hw_mgr_res; @@ -12872,11 +12820,8 @@ static int cam_ife_mgr_csid_add_reg_update(struct cam_ife_hw_mgr_ctx *ctx, break; } - CAM_DBG(CAM_ISP, "Ctx:%u Reg update added id:%d num_res %d configured val: 0x%x", - ctx->ctx_index, i, rup_args[i].num_res, rup_args[i].value); - rup_done = true; - if (rup_done && !prepare_hw_data->configured_rup_aup) - prepare_hw_data->configured_rup_aup = rup_args[i].value; + CAM_DBG(CAM_ISP, "Ctx:%u Reg update added id:%d num_res %d", + ctx->ctx_index, i, rup_args[i].num_res); } return rc; @@ -12916,7 +12861,7 @@ static int cam_ife_mgr_isp_add_reg_update(struct cam_ife_hw_mgr_ctx *ctx, rc = cam_isp_add_reg_update(prepare, &ctx->res_list_ife_src, ctx->base[i].idx, kmd_buf, - !ctx->flags.internal_cdm); + !ctx->flags.internal_cdm, NULL); if (rc) { CAM_ERR(CAM_ISP, @@ -13395,7 +13340,6 @@ static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, } prepare_hw_data = (struct cam_isp_prepare_hw_update_data *)prepare->priv; - prepare_hw_data->configured_rup_aup = 0x0; ctx = (struct cam_ife_hw_mgr_ctx *) prepare->ctxt_to_hw_map; hw_mgr = (struct cam_ife_hw_mgr *)hw_mgr_priv; @@ -13805,6 +13749,7 @@ static void cam_ife_mgr_pf_dump_mid_info( int rc = 0; get_res.mid = hw_cmd_args->u.pf_cmd_args->pf_args->pf_smmu_info->mid; + get_res.pid = hw_cmd_args->u.pf_cmd_args->pf_args->pf_smmu_info->pid; cmd_update.cmd_type = CAM_ISP_HW_CMD_GET_RES_FOR_MID; cmd_update.data = (void *) &get_res; @@ -13969,8 +13914,8 @@ int cam_isp_config_csid_rup_aup( return rc; CAM_DBG(CAM_ISP, - "Reg update for CSID: %u mup: %u ctx_idx: %u configured val: 0x%x", - res->hw_intf->hw_idx, ctx->current_mup, ctx->ctx_index, rup_args[i].value); + "Reg update for CSID: %u mup: %u ctx_idx: %u", + res->hw_intf->hw_idx, ctx->current_mup, ctx->ctx_index); } return rc; @@ -14292,42 +14237,6 @@ static void *cam_ife_mgr_user_dump_stream_info( return addr; } -static int cam_ife_mgr_cmd_get_path_sof_timestamp( - struct cam_ife_hw_mgr_ctx *ife_ctx) -{ - int rc = -EINVAL; - uint32_t i; - struct cam_isp_hw_mgr_res *hw_mgr_res; - struct cam_hw_intf *hw_intf; - uint32_t dummy_args; - - hw_mgr_res = list_first_entry(&ife_ctx->res_list_ife_csid, - struct cam_isp_hw_mgr_res, list); - - for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { - if (!hw_mgr_res->hw_res[i]) - continue; - - /* - * Get the SOF time stamp from left resource only. - */ - - hw_intf = hw_mgr_res->hw_res[i]->hw_intf; - if (hw_intf->hw_ops.process_cmd) { - rc = hw_intf->hw_ops.process_cmd( - hw_intf->hw_priv, - CAM_IFE_CSID_CMD_GET_PATH_TIME_STAMP, - &dummy_args, sizeof(dummy_args)); - } - } - - if (rc) - CAM_ERR_RATE_LIMIT(CAM_ISP, "Getting sof time stamp failed, ctx_idx: %u", - ife_ctx->ctx_index); - - return rc; -} - static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) { int rc = 0; @@ -14345,7 +14254,6 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) } ctx = (struct cam_ife_hw_mgr_ctx *)hw_cmd_args->ctxt_to_hw_map; - if (!ctx || !ctx->flags.ctx_in_use) { CAM_ERR(CAM_ISP, "Fatal: Invalid context is used"); return -EPERM; @@ -14442,9 +14350,6 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) rc = cam_ife_mgr_cmd_get_last_consumed_addr(ctx, (struct cam_isp_hw_done_event_data *)(isp_hw_cmd_args->cmd_data)); break; - case CAM_ISP_HW_MGR_GET_PATH_SOF_TS: - rc = cam_ife_mgr_cmd_get_path_sof_timestamp(ctx); - break; default: CAM_ERR(CAM_ISP, "Invalid HW mgr command:0x%x, ctx_idx: %u", hw_cmd_args->cmd_type, ctx->ctx_index); @@ -14795,7 +14700,7 @@ static int cam_ife_mgr_recover_hw(void *priv, void *data) for (i = 0; i < recovery_data->no_of_context; i++) { ctx = recovery_data->affected_ctx[i]; rc = cam_ife_hw_mgr_reset_csid(ctx, - CAM_IFE_CSID_RESET_PATH, false); + CAM_IFE_CSID_RESET_PATH); if (rc) { CAM_ERR(CAM_ISP, "Failed RESET, ctx_idx: %u", ctx->ctx_index); @@ -14957,8 +14862,7 @@ static bool cam_ife_hw_mgr_is_ctx_affected( static int cam_ife_hw_mgr_find_affected_ctx( struct cam_isp_hw_error_event_data *error_event_data, uint32_t curr_core_idx, - struct cam_ife_hw_event_recovery_data *recovery_data, - bool force_recover) + struct cam_ife_hw_event_recovery_data *recovery_data) { uint32_t affected_core[CAM_IFE_HW_NUM_MAX] = {0}; struct cam_ife_hw_mgr_ctx *ife_hwr_mgr_ctx = NULL; @@ -14985,8 +14889,7 @@ static int cam_ife_hw_mgr_find_affected_ctx( affected_core, CAM_IFE_HW_NUM_MAX)) continue; - /* Try to force recover for specific errors */ - if (!force_recover && atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) { + if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) { CAM_INFO(CAM_ISP, "CTX:%u already error reported", ife_hwr_mgr_ctx->ctx_index); continue; @@ -15064,7 +14967,7 @@ static int cam_ife_hw_mgr_handle_csid_error( struct cam_isp_hw_error_event_info *err_evt_info; struct cam_isp_hw_error_event_data error_event_data = {0}; struct cam_ife_hw_event_recovery_data recovery_data = {0}; - bool is_bus_overflow = false, force_recover = false; + bool is_bus_overflow = false; if (!event_info->event_data) { CAM_ERR(CAM_ISP, @@ -15129,13 +15032,8 @@ static int cam_ife_hw_mgr_handle_csid_error( recovery_data.error_type = err_type; } - /* If internal recovery is requested, and overflow pending is set force recovery for out of sync */ - if ((error_event_data.try_internal_recovery) && (atomic_read(&ctx->overflow_pending))) - force_recover = err_type & (CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR | - CAM_ISP_HW_ERROR_CSID_SENSOR_FRAME_DROP); - rc = cam_ife_hw_mgr_find_affected_ctx(&error_event_data, - event_info->hw_idx, &recovery_data, force_recover); + event_info->hw_idx, &recovery_data); if (rc || !recovery_data.no_of_context) goto end; @@ -15507,7 +15405,7 @@ static int cam_ife_hw_mgr_handle_sfe_hw_err( error_event_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; CAM_DBG(CAM_ISP, "Notify context for SFE error, ctx_idx: %u", ctx->ctx_index); cam_ife_hw_mgr_find_affected_ctx(&error_event_data, - event_info->hw_idx, &recovery_data, false); + event_info->hw_idx, &recovery_data); } spin_unlock(&g_ife_hw_mgr.ctx_lock); @@ -15567,7 +15465,7 @@ static int cam_ife_hw_mgr_handle_hw_err( error_event_data.enable_req_dump = true; rc = cam_ife_hw_mgr_find_affected_ctx(&error_event_data, - core_idx, &recovery_data, false); + core_idx, &recovery_data); if (rc || !recovery_data.no_of_context) goto end; @@ -16236,68 +16134,6 @@ DEFINE_SIMPLE_ATTRIBUTE(cam_ife_csid_debug, cam_ife_get_csid_debug, cam_ife_set_csid_debug, "%16llu"); -#if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) -static int cam_ife_set_csid_dbg_fps(void* data, u64 val) -{ - g_ife_hw_mgr.debug_cfg.csid_dbg_fps = val; - CAM_INFO(CAM_ISP, "Set CSID Debug Fps value :%lld", val); - return 0; -} - -static int cam_ife_get_csid_dbg_fps(void* data, u64* val) -{ - *val = g_ife_hw_mgr.debug_cfg.csid_dbg_fps; - CAM_INFO(CAM_ISP, "Get CSID Debug Fps value :%lld", - g_ife_hw_mgr.debug_cfg.csid_dbg_fps); - - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(cam_ife_csid_debug_fps, - cam_ife_get_csid_dbg_fps, - cam_ife_set_csid_dbg_fps, "%16llu"); - -static int cam_vfe_set_dbg_fps(void* data, u64 val) -{ - g_ife_hw_mgr.debug_cfg.vfe_dbg_fps = val; - CAM_INFO(CAM_ISP, "Set VFE Debug Fps value :%lld", val); - return 0; -} - -static int cam_vfe_get_dbg_fps(void* data, u64* val) -{ - *val = g_ife_hw_mgr.debug_cfg.vfe_dbg_fps; - CAM_INFO(CAM_ISP, "Get VFE Debug Fps value :%lld", - g_ife_hw_mgr.debug_cfg.vfe_dbg_fps); - - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(cam_vfe_debug_fps, - cam_vfe_get_dbg_fps, - cam_vfe_set_dbg_fps, "%16llu"); - -static int cam_ife_set_dbg_mode_switch(void* data, u64 val) -{ - g_ife_hw_mgr.debug_cfg.dbg_mode_switch = val; - CAM_INFO(CAM_ISP, "Set Debug mode switch value :%lld", val); - return 0; -} - -static int cam_ife_get_dbg_mode_switch(void* data, u64* val) -{ - *val = g_ife_hw_mgr.debug_cfg.dbg_mode_switch ; - CAM_INFO(CAM_ISP, "Get Debug mode switch value :%lld", - g_ife_hw_mgr.debug_cfg.vfe_dbg_fps); - - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(cam_debug_mode_switch, - cam_ife_get_dbg_mode_switch, - cam_ife_set_dbg_mode_switch, "%16llu"); -#endif // defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) - static int cam_ife_set_camif_debug(void *data, u64 val) { g_ife_hw_mgr.debug_cfg.camif_debug = val; @@ -17147,17 +16983,8 @@ static int cam_ife_hw_mgr_debug_register(void) &g_ife_hw_mgr.debug_cfg.enable_presil_reg_dump); debugfs_create_file("isp_irq_inject", 0644, g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_isp_irq_injection); -#if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) - debugfs_create_file("ife_csid_debug_fps", 0644, - g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_csid_debug_fps); - debugfs_create_file("vfe_debug_fps", 0644, - g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_vfe_debug_fps); - g_ife_hw_mgr.debug_cfg.vfe_dbg_fps = 100; - - debugfs_create_file("ife_debug_mode_switch", 0644, - g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_debug_mode_switch); - g_ife_hw_mgr.debug_cfg.dbg_mode_switch = 0; -#endif + debugfs_create_bool("enable_cdm_cmd_check", 0644, g_ife_hw_mgr.debug_cfg.dentry, + &g_ife_hw_mgr.debug_cfg.enable_cdm_cmd_check); end: g_ife_hw_mgr.debug_cfg.enable_csid_recovery = 1; return rc; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index 9213cb4de0..56355c6efa 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -64,7 +64,7 @@ enum cam_ife_ctx_master_type { * @rx_capture_debug_set: If rx capture debug is set by user * @disable_isp_drv: Disable ISP DRV config * @enable_presil_reg_dump: Enable per req regdump in presil - * + * @enable_cdm_cmd_check: Enable invalid command check in cmd_buf */ struct cam_ife_hw_mgr_debug { struct dentry *dentry; @@ -87,6 +87,7 @@ struct cam_ife_hw_mgr_debug { bool rx_capture_debug_set; bool disable_isp_drv; bool enable_presil_reg_dump; + bool enable_cdm_cmd_check; #if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) uint32_t csid_dbg_fps; uint32_t vfe_dbg_fps; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 5a34da277a..755ff1301b 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -16,9 +16,11 @@ #include "cam_isp_hw.h" #include "cam_tfe_csid_hw_intf.h" #include "cam_tfe_hw_intf.h" +#include "cam_tfe_soc.h" #include "cam_isp_packet_parser.h" #include "cam_tfe_hw_mgr.h" #include "cam_cdm_intf_api.h" +#include "cam_cdm_util.h" #include "cam_packet_util.h" #include "cam_debug_util.h" #include "cam_cpas_api.h" @@ -31,6 +33,7 @@ #define CAM_TFE_HW_CONFIG_TIMEOUT 60 #define CAM_TFE_HW_CONFIG_WAIT_MAX_TRY 3 +#define MAX_TFE_INTERNAL_RECOVERY_ATTEMPTS 1 #define TZ_SVC_SMMU_PROGRAM 0x15 #define TZ_SAFE_SYSCALL_ID 0x3 @@ -38,8 +41,12 @@ #define CAM_TFE_SAFE_ENABLE 1 #define SMMU_SE_TFE 0 +#define CAM_TFE_HW_MGR_STATE_INACTIVE 0 +#define CAM_TFE_HW_MGR_STATE_ACTIVE 1 static struct cam_tfe_hw_mgr g_tfe_hw_mgr; +static uint32_t g_num_tfe_available, g_num_tfe_functional; +static uint32_t g_num_tfe_lite_available, g_num_tfe_lite_functional; static int cam_tfe_hw_mgr_event_handler( void *priv, @@ -151,6 +158,12 @@ static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, return rc; } + if (!ctx->init_done) { + CAM_WARN(CAM_ISP, "regdump can't possible as HW not initialized, ctx_idx: %u", + ctx->ctx_index); + return 0; + } + if (!atomic_read(&ctx->cdm_done)) CAM_WARN_RATE_LIMIT(CAM_ISP, "Reg dump values might be from more than one request"); @@ -177,67 +190,173 @@ static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, return rc; } -static int cam_tfe_mgr_get_hw_caps(void *hw_mgr_priv, void *hw_caps_args) +static int cam_tfe_mgr_get_hw_caps_internal(void *hw_mgr_priv, + struct cam_isp_tfe_query_cap_cmd_v2 *query_isp) { - int rc = 0; - int i; + int i, rc = 0; uint32_t num_dev = 0; struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; - struct cam_query_cap_cmd *query = hw_caps_args; - struct cam_isp_tfe_query_cap_cmd query_isp; - CAM_DBG(CAM_ISP, "enter"); - - if (sizeof(struct cam_isp_tfe_query_cap_cmd) != query->size) { - CAM_ERR(CAM_ISP, - "Input query cap size:%u does not match expected query cap size: %u", - query->size, sizeof(struct cam_isp_tfe_query_cap_cmd)); - return -EFAULT; - } - - if (copy_from_user(&query_isp, - u64_to_user_ptr(query->caps_handle), - sizeof(struct cam_isp_tfe_query_cap_cmd))) { - rc = -EFAULT; - return rc; - } - - query_isp.device_iommu.non_secure = hw_mgr->mgr_common.img_iommu_hdl; - query_isp.device_iommu.secure = hw_mgr->mgr_common.img_iommu_hdl_secure; - query_isp.cdm_iommu.non_secure = hw_mgr->mgr_common.cmd_iommu_hdl; - query_isp.cdm_iommu.secure = hw_mgr->mgr_common.cmd_iommu_hdl_secure; + query_isp->device_iommu.non_secure = hw_mgr->mgr_common.img_iommu_hdl; + query_isp->device_iommu.secure = hw_mgr->mgr_common.img_iommu_hdl_secure; + query_isp->cdm_iommu.non_secure = hw_mgr->mgr_common.cmd_iommu_hdl; + query_isp->cdm_iommu.secure = hw_mgr->mgr_common.cmd_iommu_hdl_secure; for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { if (!hw_mgr->csid_devices[i]) - continue; + break; + if (i >= query_isp->num_dev) + return -EINVAL; - query_isp.dev_caps[i].hw_type = CAM_ISP_TFE_HW_TFE; - query_isp.dev_caps[i].hw_version.major = 5; - query_isp.dev_caps[i].hw_version.minor = 3; - query_isp.dev_caps[i].hw_version.incr = 0; + query_isp->dev_caps[i].hw_type = CAM_ISP_TFE_HW_TFE; + query_isp->dev_caps[i].hw_version.major = 7; + query_isp->dev_caps[i].hw_version.minor = 7; + query_isp->dev_caps[i].hw_version.incr = 0; /* * device number is based on number of full tfe * if pix is not supported, set reserve to 1 */ if (hw_mgr->tfe_csid_dev_caps[i].num_pix) { - query_isp.dev_caps[i].hw_version.reserved = 0; + query_isp->dev_caps[i].hw_version.reserved = 0; num_dev++; - } else - query_isp.dev_caps[i].hw_version.reserved = 1; + } else { + query_isp->dev_caps[i].hw_version.reserved = 1; + } } - query_isp.num_dev = num_dev; + query_isp->num_dev = num_dev; + return rc; +} + +static int cam_tfe_mgr_get_hw_caps(void *hw_mgr_priv, + void *hw_caps_args) +{ + int rc = 0; + int i, query_size; + uint32_t version = 0; + struct cam_query_cap_cmd *query = hw_caps_args; + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_isp_tfe_query_cap_cmd query_isp = {0}; + struct cam_isp_tfe_query_cap_cmd_v2 *query_isp_v2; + + query_size = sizeof(struct cam_isp_tfe_query_cap_cmd_v2) + + ((CAM_TFE_CSID_HW_NUM_MAX - 1) * sizeof(struct cam_isp_tfe_dev_cap_info)); + + query_isp_v2 = kzalloc(query_size, GFP_KERNEL); + + if (!query_isp_v2) { + CAM_ERR(CAM_ISP, "Mem alloc failed"); + return -ENOMEM; + } + + query_isp_v2->num_dev = CAM_TFE_CSID_HW_NUM_MAX; + rc = cam_tfe_mgr_get_hw_caps_internal(hw_mgr_priv, query_isp_v2); + if (rc) { + CAM_ERR(CAM_ISP, "Invalid num devs"); + kfree(query_isp_v2); + return rc; + } + + query_isp.device_iommu.non_secure = query_isp_v2->device_iommu.non_secure; + query_isp.device_iommu.secure = query_isp_v2->device_iommu.secure; + query_isp.cdm_iommu.non_secure = query_isp_v2->cdm_iommu.non_secure; + query_isp.cdm_iommu.secure = query_isp_v2->cdm_iommu.secure; + + for (i = 0; i < CAM_ISP_TFE_HW_MAX; i++) { + if (!hw_mgr->csid_devices[i]) + continue; + query_isp.dev_caps[i] = query_isp_v2->dev_caps[i]; + } + + query_isp.num_dev = query_isp_v2->num_dev; if (copy_to_user(u64_to_user_ptr(query->caps_handle), - &query_isp, sizeof(struct cam_isp_tfe_query_cap_cmd))) - rc = -EFAULT; - - CAM_DBG(CAM_ISP, "exit rc :%d", rc); + &query_isp, sizeof(struct cam_isp_tfe_query_cap_cmd))) { + CAM_ERR(CAM_ISP, "copy to user failed, query cap version %d", version); + kfree(query_isp_v2); + return -EFAULT; + } + kfree(query_isp_v2); return rc; } +static int cam_tfe_mgr_get_hw_caps_v2(void *hw_mgr_priv, + void *hw_caps_args) +{ + int query_size, rc = 0; + struct cam_query_cap_cmd *query = hw_caps_args; + struct cam_isp_tfe_query_cap_cmd_v2 tmp_query_isp_v2; + struct cam_isp_tfe_query_cap_cmd_v2 *query_isp_v2; + + if (copy_from_user(&tmp_query_isp_v2, u64_to_user_ptr(query->caps_handle), + sizeof(tmp_query_isp_v2))) { + rc = -EFAULT; + return rc; + } + + if (tmp_query_isp_v2.version != CAM_QUERY_CAP_V2) { + CAM_ERR(CAM_ISP, "Query cap Version %d invalid", tmp_query_isp_v2.version); + return -EINVAL; + } + + if (!tmp_query_isp_v2.num_dev || + tmp_query_isp_v2.num_dev > CAM_TFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid Num of dev is %d query cap version %d", + tmp_query_isp_v2.num_dev, tmp_query_isp_v2.version); + rc = -EINVAL; + return rc; + } + + query_size = sizeof(struct cam_isp_tfe_query_cap_cmd_v2) + + ((tmp_query_isp_v2.num_dev - 1) * sizeof(struct cam_isp_tfe_dev_cap_info)); + + query_isp_v2 = kzalloc(query_size, GFP_KERNEL); + + if (!query_isp_v2) { + CAM_ERR(CAM_ISP, "Mem alloc failed"); + return -ENOMEM; + } + + query_isp_v2->version = tmp_query_isp_v2.version; + query_isp_v2->num_dev = tmp_query_isp_v2.num_dev; + + rc = cam_tfe_mgr_get_hw_caps_internal(hw_mgr_priv, query_isp_v2); + if (rc) { + CAM_ERR(CAM_ISP, "Invalid Num of dev is %d query cap version %d", + tmp_query_isp_v2.num_dev, tmp_query_isp_v2.version); + kfree(query_isp_v2); + return -EINVAL; + } + + if (copy_to_user(u64_to_user_ptr(query->caps_handle), query_isp_v2, + (sizeof(struct cam_isp_tfe_query_cap_cmd_v2) + ((query_isp_v2->num_dev - 1) + * sizeof(struct cam_isp_tfe_dev_cap_info))))) { + CAM_ERR(CAM_ISP, "copy to user failed, query cap version %d", + tmp_query_isp_v2.version); + kfree(query_isp_v2); + return -EFAULT; + } + + kfree(query_isp_v2); + return rc; +} + +static inline bool cam_tfe_hw_mgr_check_path_port_compat( + uint32_t in_type, uint32_t out_type) +{ + int i; + const struct cam_isp_hw_path_port_map *map = &g_tfe_hw_mgr.path_port_map; + + for (i = 0; i < map->num_entries; i++) { + if (map->entry[i][1] == out_type) + return (map->entry[i][0] == in_type); + } + + return (in_type == CAM_ISP_HW_TFE_IN_CAMIF); +} + static int cam_tfe_hw_mgr_is_rdi_res(uint32_t res_id) { int rc = 0; @@ -440,6 +559,32 @@ static void cam_tfe_hw_mgr_deinit_hw( ctx->init_done = false; } +static inline void cam_tfe_mgr_count_functional_tfe(void) +{ + int i; + struct cam_hw_info *tfe_hw; + struct cam_tfe_soc_private *soc_private; + + g_num_tfe_functional = 0; + g_num_tfe_lite_functional = 0; + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (g_tfe_hw_mgr.tfe_devices[i]) { + tfe_hw = (struct cam_hw_info *) + g_tfe_hw_mgr.tfe_devices[i]->hw_intf->hw_priv; + soc_private = tfe_hw->soc_info.soc_private; + + if (soc_private->is_tfe_lite) + g_num_tfe_lite_functional++; + else + g_num_tfe_functional++; + } + } + + CAM_DBG(CAM_ISP, "counted functional %u TFEs and %u TFE-LITEs", g_num_tfe_functional, + g_num_tfe_lite_functional); +} + static int cam_tfe_hw_mgr_init_hw( struct cam_tfe_hw_mgr_ctx *ctx) { @@ -511,7 +656,7 @@ static int cam_tfe_hw_mgr_get_res( } static int cam_tfe_hw_mgr_free_hw_res( - struct cam_isp_hw_mgr_res *isp_hw_res) + struct cam_isp_hw_mgr_res *isp_hw_res, bool del_list) { int rc = 0; int i; @@ -534,9 +679,13 @@ static int cam_tfe_hw_mgr_free_hw_res( CAM_ERR(CAM_ISP, "Release null"); } /* caller should make sure the resource is in a list */ - list_del_init(&isp_hw_res->list); - memset(isp_hw_res, 0, sizeof(*isp_hw_res)); - INIT_LIST_HEAD(&isp_hw_res->list); + if (del_list) { + list_del_init(&isp_hw_res->list); + memset(isp_hw_res, 0, sizeof(*isp_hw_res)); + INIT_LIST_HEAD(&isp_hw_res->list); + } else { + memset(isp_hw_res, 0, sizeof(*isp_hw_res)); + } return 0; } @@ -635,24 +784,29 @@ static int cam_tfe_hw_mgr_release_hw_for_ctx( struct cam_tfe_hw_mgr_ctx *tfe_ctx) { uint32_t i; + uint32_t num_out = 0; struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_isp_hw_mgr_res *hw_mgr_res_temp; /* tfe out resource */ - for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) - cam_tfe_hw_mgr_free_hw_res(&tfe_ctx->res_list_tfe_out[i]); + num_out = tfe_ctx->num_acq_tfe_out; + for (i = 0; i < num_out; i++) { + cam_tfe_hw_mgr_free_hw_res(&tfe_ctx->res_list_tfe_out[i], + false); + tfe_ctx->num_acq_tfe_out--; + } /* tfe in resource */ list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, &tfe_ctx->res_list_tfe_in, list) { - cam_tfe_hw_mgr_free_hw_res(hw_mgr_res); + cam_tfe_hw_mgr_free_hw_res(hw_mgr_res, true); cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &hw_mgr_res); } /* tfe csid resource */ list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, &tfe_ctx->res_list_tfe_csid, list) { - cam_tfe_hw_mgr_free_hw_res(hw_mgr_res); + cam_tfe_hw_mgr_free_hw_res(hw_mgr_res, true); cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &hw_mgr_res); } @@ -754,17 +908,19 @@ static void cam_tfe_hw_mgr_dump_all_ctx(void) static void cam_tfe_mgr_add_base_info( struct cam_tfe_hw_mgr_ctx *ctx, enum cam_isp_hw_split_id split_id, - uint32_t base_idx) + uint32_t base_idx, + enum cam_isp_hw_type hw_type) { uint32_t i; if (!ctx->num_base) { ctx->base[0].split_id = split_id; ctx->base[0].idx = base_idx; + ctx->base[0].hw_type = hw_type; ctx->num_base++; CAM_DBG(CAM_ISP, - "Add split id = %d for base idx = %d num_base=%d", - split_id, base_idx, ctx->num_base); + "Add split id = %d for base idx = %d num_base=%d hw_type=%d", + split_id, base_idx, ctx->num_base, hw_type); } else { /*Check if base index already exists in the list */ for (i = 0; i < ctx->num_base; i++) { @@ -781,10 +937,11 @@ static void cam_tfe_mgr_add_base_info( if (i == ctx->num_base) { ctx->base[ctx->num_base].split_id = split_id; ctx->base[ctx->num_base].idx = base_idx; + ctx->base[ctx->num_base].hw_type = hw_type; ctx->num_base++; CAM_DBG(CAM_ISP, - "Add split_id=%d for base idx=%d num_base=%d", - split_id, base_idx, ctx->num_base); + "Add split_id=%d for base idx=%d num_base=%d hw_type=%d", + split_id, base_idx, ctx->num_base, hw_type); } } } @@ -812,12 +969,13 @@ static int cam_tfe_mgr_process_base_info( res = hw_mgr_res->hw_res[i]; cam_tfe_mgr_add_base_info(ctx, i, - res->hw_intf->hw_idx); - CAM_DBG(CAM_ISP, "add base info for hw %d", - res->hw_intf->hw_idx); + res->hw_intf->hw_idx, + CAM_ISP_HW_TYPE_TFE); + CAM_DBG(CAM_ISP, "add base info for hw %d ctx_idx: %u", + res->hw_intf->hw_idx, ctx->ctx_index); } } - CAM_DBG(CAM_ISP, "ctx base num = %d", ctx->num_base); + CAM_DBG(CAM_ISP, "ctx base num = %d, ctx_idx: %u", ctx->num_base, ctx->ctx_index); return 0; } @@ -852,18 +1010,17 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_out_rdi( CAM_ERR(CAM_ISP, "invalid resource type"); goto err; } - CAM_DBG(CAM_ISP, "tfe_in_res_id = %d, tfe_out_red_id = %d", - tfe_in_res_id, tfe_out_res_id); + CAM_DBG(CAM_ISP, "ctx: %d tfe_in_res_id = %d, tfe_out_red_id = %d", + tfe_ctx->ctx_index, tfe_in_res_id, tfe_out_res_id); tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_OUT; tfe_acquire.tasklet = tfe_ctx->common.tasklet_info; - tfe_out_res = &tfe_ctx->res_list_tfe_out[tfe_out_res_id & 0xFF]; for (i = 0; i < in_port->num_out_res; i++) { out_port = &in_port->data[i]; - CAM_DBG(CAM_ISP, "i = %d, tfe_out_res_id = %d, out_port: %d", - i, tfe_out_res_id, out_port->res_id); + CAM_DBG(CAM_ISP, "i = %d, ctx: %d tfe_out_res_id = %d, out_port: %d", + i, tfe_ctx->ctx_index, tfe_out_res_id, out_port->res_id); if (tfe_out_res_id != out_port->res_id) continue; @@ -899,11 +1056,15 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_out_rdi( goto err; } + tfe_ctx->tfe_out_map[tfe_out_res_id & 0xFF] = tfe_ctx->num_acq_tfe_out; + tfe_out_res = &tfe_ctx->res_list_tfe_out[tfe_ctx->num_acq_tfe_out]; tfe_out_res->hw_res[0] = tfe_acquire.tfe_out.rsrc_node; tfe_out_res->is_dual_isp = 0; tfe_out_res->res_id = tfe_out_res_id; tfe_out_res->res_type = CAM_ISP_RESOURCE_TFE_OUT; tfe_in_res->num_children++; + tfe_ctx->acquired_wm_mask |= (1 << out_port->res_id); + tfe_ctx->num_acq_tfe_out++; return 0; err: @@ -927,7 +1088,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_out_pixel( for (i = 0; i < in_port->num_out_res; i++) { out_port = &in_port->data[i]; k = out_port->res_id & 0xFF; - if (k >= CAM_TFE_HW_OUT_RES_MAX) { + if (k >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "invalid output resource type 0x%x", out_port->res_id); continue; @@ -936,9 +1097,14 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_out_pixel( if (cam_tfe_hw_mgr_is_rdi_res(out_port->res_id)) continue; + if (!cam_tfe_hw_mgr_check_path_port_compat(tfe_in_res->res_id, + out_port->res_id)) + continue; + CAM_DBG(CAM_ISP, "res_type 0x%x", out_port->res_id); - tfe_out_res = &tfe_ctx->res_list_tfe_out[k]; + tfe_ctx->tfe_out_map[k] = tfe_ctx->num_acq_tfe_out; + tfe_out_res = &tfe_ctx->res_list_tfe_out[tfe_ctx->num_acq_tfe_out]; tfe_out_res->is_dual_isp = in_port->usage_type; tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_OUT; @@ -997,6 +1163,8 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_out_pixel( tfe_out_res->res_type = CAM_ISP_RESOURCE_TFE_OUT; tfe_out_res->res_id = out_port->res_id; tfe_in_res->num_children++; + tfe_ctx->acquired_wm_mask |= (1 << out_port->res_id); + tfe_ctx->num_acq_tfe_out++; } return 0; @@ -1018,6 +1186,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_out( switch (tfe_in_res->res_id) { case CAM_ISP_HW_TFE_IN_CAMIF: + case CAM_ISP_HW_TFE_IN_PDLIB: rc = cam_tfe_hw_mgr_acquire_res_tfe_out_pixel(tfe_ctx, tfe_in_res, in_port); break; @@ -1045,7 +1214,8 @@ err: static int cam_tfe_hw_mgr_acquire_res_tfe_in( struct cam_tfe_hw_mgr_ctx *tfe_ctx, struct cam_isp_tfe_in_port_generic_info *in_port, - uint32_t *pdaf_enable) + uint32_t *pdaf_enable, + bool lcr_enable) { int rc = -EINVAL; int i; @@ -1079,6 +1249,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_in( tfe_acquire.tfe_in.camif_pd_enable = *pdaf_enable; tfe_acquire.priv = tfe_ctx; tfe_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + tfe_acquire.tfe_in.lcr_enable = lcr_enable; switch (csid_res->res_id) { case CAM_TFE_CSID_PATH_RES_IPP: @@ -1093,6 +1264,17 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_in( CAM_ISP_HW_SYNC_NONE; break; + case CAM_TFE_CSID_PATH_RES_PPP: + tfe_acquire.tfe_in.res_id = + CAM_ISP_HW_TFE_IN_PDLIB; + + if (csid_res->is_dual_isp) + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_MASTER; + else + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_NONE; + break; case CAM_TFE_CSID_PATH_RES_RDI_0: tfe_acquire.tfe_in.res_id = CAM_ISP_HW_TFE_IN_RDI0; tfe_acquire.tfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; @@ -1161,7 +1343,9 @@ err: static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( struct cam_tfe_hw_mgr_ctx *tfe_ctx, - struct cam_isp_tfe_in_port_generic_info *in_port) + struct cam_isp_tfe_in_port_generic_info *in_port, + bool is_ipp, + bool crop_enable) { int rc = -EINVAL; int i, j; @@ -1169,14 +1353,17 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( struct cam_tfe_hw_mgr *tfe_hw_mgr; struct cam_isp_hw_mgr_res *csid_res; struct cam_hw_intf *hw_intf; - struct cam_tfe_csid_hw_reserve_resource_args csid_acquire; + struct cam_tfe_csid_hw_reserve_resource_args csid_acquire = {0}; enum cam_tfe_csid_path_res_id path_res_id; struct cam_isp_hw_mgr_res *csid_res_temp, *csid_res_iterator; struct cam_isp_tfe_out_port_generic_info *out_port = NULL; tfe_hw_mgr = tfe_ctx->hw_mgr; /* get csid resource */ - path_res_id = CAM_TFE_CSID_PATH_RES_IPP; + if (is_ipp) + path_res_id = CAM_TFE_CSID_PATH_RES_IPP; + else + path_res_id = CAM_TFE_CSID_PATH_RES_PPP; rc = cam_tfe_hw_mgr_get_res(&tfe_ctx->free_res_list, &csid_res); if (rc) { @@ -1193,6 +1380,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( csid_acquire.node_res = NULL; csid_acquire.event_cb_prv = tfe_ctx; csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + csid_acquire.crop_enable = crop_enable; if (in_port->num_out_res) out_port = &(in_port->data[0]); @@ -1215,6 +1403,9 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( out_port->secure_mode == 1)) continue; + csid_acquire.sync_mode = ((i == CAM_ISP_HW_SPLIT_LEFT) ? + CAM_ISP_HW_SYNC_MASTER : CAM_ISP_HW_SYNC_SLAVE); + hw_intf = csid_res_iterator->hw_res[i]->hw_intf; csid_acquire.master_idx = hw_intf->hw_idx; @@ -1231,12 +1422,14 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( csid_acquire.node_res; CAM_DBG(CAM_ISP, - "acquired from old csid(%s)=%d CSID rsrc successfully", + "acquired from old csid(%s)=%d CSID rsrc %s successfully", (i == 0) ? "left" : "right", - hw_intf->hw_idx); + hw_intf->hw_idx, + (is_ipp) ? "IPP" : "PPP"); if (in_port->usage_type && acquired_cnt == 1 && - path_res_id == CAM_TFE_CSID_PATH_RES_IPP) + ((path_res_id == CAM_TFE_CSID_PATH_RES_IPP) || + (path_res_id == CAM_TFE_CSID_PATH_RES_PPP))) /* * Continue to acquire Right for IPP. * Dual TFE for RDI is not currently @@ -1263,7 +1456,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( goto acquire_successful; /* Acquire Left if not already acquired */ - if (in_port->usage_type) { + if (in_port->usage_type || in_port->is_shdr_master) { for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { if (!tfe_hw_mgr->csid_devices[i]) continue; @@ -1283,8 +1476,9 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( if (i == CAM_TFE_CSID_HW_NUM_MAX || !csid_acquire.node_res) { CAM_ERR(CAM_ISP, - "Can not acquire left tfe csid path resource %d", - path_res_id); + "Can not acquire left tfe csid path resource %d (%s)", + path_res_id, + (is_ipp) ? "IPP" : "PPP"); goto put_res; } } else { @@ -1307,14 +1501,16 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( if (i == -1 || !csid_acquire.node_res) { CAM_ERR(CAM_ISP, - "Can not acquire tfe csid path resource %d", - path_res_id); + "Can not acquire tfe csid path resource %d(%s)", + path_res_id, + (is_ipp) ? "IPP" : "PPP"); goto put_res; } } acquire_successful: - CAM_DBG(CAM_ISP, "CSID path left acquired success. is_dual %d", - in_port->usage_type); + CAM_DBG(CAM_ISP, "CSID path left acquired success. is_dual %d res %s", + in_port->usage_type, + (is_ipp) ? "IPP" : "PPP"); csid_res_temp->res_type = CAM_ISP_RESOURCE_PIX_PATH; csid_res_temp->res_id = path_res_id; @@ -1336,7 +1532,8 @@ acquire_successful: * Acquire Right if not already acquired. * Dual TFE for RDI is not currently supported. */ - if (in_port->usage_type && (path_res_id == CAM_TFE_CSID_PATH_RES_IPP) + if (in_port->usage_type && ((path_res_id == CAM_TFE_CSID_PATH_RES_IPP) + || (path_res_id == CAM_TFE_CSID_PATH_RES_PPP)) && (acquired_cnt == 1)) { memset(&csid_acquire, 0, sizeof(csid_acquire)); csid_acquire.node_res = NULL; @@ -1348,6 +1545,7 @@ acquire_successful: csid_acquire.sync_mode = CAM_ISP_HW_SYNC_SLAVE; csid_acquire.node_res = NULL; csid_acquire.out_port = in_port->data; + csid_acquire.crop_enable = crop_enable; csid_acquire.event_cb_prv = tfe_ctx; csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; @@ -1369,14 +1567,16 @@ acquire_successful: if (j == CAM_TFE_CSID_HW_NUM_MAX) { CAM_ERR(CAM_ISP, - "Can not acquire tfe csid pixel resource"); + "Can not acquire tfe csid pixel resource %s", + (is_ipp) ? "IPP" : "PPP"); goto end; } csid_res_temp->hw_res[1] = csid_acquire.node_res; tfe_ctx->slave_hw_idx = csid_res_temp->hw_res[1]->hw_intf->hw_idx; - CAM_DBG(CAM_ISP, "CSID right acquired success is_dual %d", - in_port->usage_type); + CAM_DBG(CAM_ISP, "CSID right acquired success is_dual %d res %s", + in_port->usage_type, + (is_ipp) ? "IPP" : "PPP"); } return 0; @@ -1426,7 +1626,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( struct cam_isp_hw_mgr_res *csid_res; struct cam_hw_intf *hw_intf; struct cam_isp_tfe_out_port_generic_info *out_port; - struct cam_tfe_csid_hw_reserve_resource_args csid_acquire; + struct cam_tfe_csid_hw_reserve_resource_args csid_acquire = {0}; struct cam_isp_hw_mgr_res *csid_res_iterator; enum cam_tfe_csid_path_res_id path_res_id; @@ -1472,6 +1672,13 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( hw_intf = csid_res_iterator->hw_res[i]->hw_intf; + if (tfe_hw_mgr->tfe_csid_dev_caps[hw_intf->hw_idx].is_lite + && !tfe_ctx->is_rdi_only_context) { + CAM_DBG(CAM_ISP, "Ctx id %d CSID[%u] cannot use lite", + tfe_ctx->ctx_index, hw_intf->hw_idx); + continue; + } + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &csid_acquire, sizeof(csid_acquire)); if (rc) { @@ -1504,12 +1711,20 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( } /* Acquire if not already acquired */ - if (tfe_ctx->is_dual) { + if (tfe_ctx->is_dual || in_port->is_shdr_master) { for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { if (!tfe_hw_mgr->csid_devices[i]) continue; hw_intf = tfe_hw_mgr->csid_devices[i]; + + if (tfe_hw_mgr->tfe_csid_dev_caps[hw_intf->hw_idx].is_lite && + !tfe_ctx->is_rdi_only_context) { + CAM_DBG(CAM_ISP, "Ctx id %d CSID[%u] cannot use lite", + tfe_ctx->ctx_index, hw_intf->hw_idx); + continue; + } + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &csid_acquire, sizeof(csid_acquire)); if (rc) @@ -1536,6 +1751,14 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( continue; hw_intf = tfe_hw_mgr->csid_devices[i]; + + if (tfe_hw_mgr->tfe_csid_dev_caps[hw_intf->hw_idx].is_lite && + !tfe_ctx->is_rdi_only_context) { + CAM_DBG(CAM_ISP, "Ctx id %d CSID[%u] cannot use lite", + tfe_ctx->ctx_index, hw_intf->hw_idx); + continue; + } + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &csid_acquire, sizeof(csid_acquire)); if (rc) @@ -1582,10 +1805,13 @@ static int cam_tfe_hw_mgr_preprocess_port( struct cam_isp_tfe_in_port_generic_info *in_port, int *ipp_count, int *rdi_count, - int *pdaf_enable) + int *ppp_count, + int *pdaf_enable, + bool *lcr_enable) { int ipp_num = 0; int rdi_num = 0; + int pd_num = 0; bool rdi2_enable = false; uint32_t i; struct cam_isp_tfe_out_port_generic_info *out_port; @@ -1609,6 +1835,12 @@ static int cam_tfe_hw_mgr_preprocess_port( rdi_num++; if (out_port->res_id == CAM_ISP_TFE_OUT_RES_RDI_2) rdi2_enable = true; + } else if (cam_tfe_hw_mgr_check_path_port_compat(CAM_ISP_HW_TFE_IN_PDLIB, + out_port->res_id)) { + pd_num++; + + if (out_port->res_id == CAM_ISP_TFE_OUT_RES_PD_LCR_STATS) + *lcr_enable = true; } else { ipp_num++; if (out_port->res_id == CAM_ISP_TFE_OUT_RES_PDAF) @@ -1624,9 +1856,10 @@ static int cam_tfe_hw_mgr_preprocess_port( *ipp_count = ipp_num; *rdi_count = rdi_num; + *ppp_count = pd_num; - CAM_DBG(CAM_ISP, "rdi: %d ipp: %d pdaf:%d", rdi_num, ipp_num, - *pdaf_enable); + CAM_DBG(CAM_ISP, "rdi: %d ipp: %d ppp: %d pdaf:%d", rdi_num, ipp_num, + *ppp_count, *pdaf_enable); return 0; } @@ -1635,28 +1868,52 @@ static int cam_tfe_mgr_acquire_hw_for_ctx( struct cam_tfe_hw_mgr_ctx *tfe_ctx, struct cam_isp_tfe_in_port_generic_info *in_port, uint32_t *num_pix_port, uint32_t *num_rdi_port, - uint32_t *pdaf_enable) + uint32_t *num_pd_port, uint32_t *pdaf_enable) { int rc = -EINVAL; int is_dual_isp = 0; int ipp_count = 0; int rdi_count = 0; + int ppp_count = 0; + bool lcr_enable = false; + bool crop_enable = true; is_dual_isp = in_port->usage_type; cam_tfe_hw_mgr_preprocess_port(tfe_ctx, in_port, &ipp_count, - &rdi_count, pdaf_enable); + &rdi_count, &ppp_count, pdaf_enable, &lcr_enable); - if (!ipp_count && !rdi_count) { + if (!ipp_count && !rdi_count && !ppp_count) { CAM_ERR(CAM_ISP, - "No PIX or RDI"); + "Invalid path count : Ipp %d ppp %d rdi %d", + ipp_count, ppp_count, rdi_count); return -EINVAL; } if (ipp_count) { /* get tfe csid IPP resource */ rc = cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl(tfe_ctx, - in_port); + in_port, true, crop_enable); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire TFE CSID IPP resource Failed dual:%d", + in_port->usage_type); + goto err; + } + } + + if (ppp_count || lcr_enable) { + /* get ife csid PPP resource */ + /* If both IPP and PPP paths are requested with the same vc dt + * it is implied that the sensor is a type 3 PD sensor. Crop + * must be enabled for this sensor on PPP path as well. + */ + if (!ipp_count) + crop_enable = false; + + /* get tfe csid IPP resource */ + rc = cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl(tfe_ctx, + in_port, false, crop_enable); if (rc) { CAM_ERR(CAM_ISP, "Acquire TFE CSID IPP resource Failed dual:%d", @@ -1676,7 +1933,7 @@ static int cam_tfe_mgr_acquire_hw_for_ctx( } } - rc = cam_tfe_hw_mgr_acquire_res_tfe_in(tfe_ctx, in_port, pdaf_enable); + rc = cam_tfe_hw_mgr_acquire_res_tfe_in(tfe_ctx, in_port, pdaf_enable, lcr_enable); if (rc) { CAM_ERR(CAM_ISP, "Acquire TFE IN resource Failed dual:%d", in_port->usage_type); @@ -1693,6 +1950,7 @@ static int cam_tfe_mgr_acquire_hw_for_ctx( *num_pix_port += ipp_count; *num_rdi_port += rdi_count; + *num_pd_port += ppp_count; return 0; err: @@ -1715,27 +1973,32 @@ void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, return; } + ctx = (struct cam_tfe_hw_mgr_ctx *)userdata; + hw_update_data = ctx->cdm_userdata.hw_update_data; + if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { - hw_update_data = - (struct cam_isp_prepare_hw_update_data *)userdata; - ctx = - (struct cam_tfe_hw_mgr_ctx *)hw_update_data->isp_mgr_ctx; complete_all(&ctx->config_done_complete); atomic_set(&ctx->cdm_done, 1); ctx->last_cdm_done_req = *(uint64_t *)cookie; - if (g_tfe_hw_mgr.debug_cfg.per_req_reg_dump) - cam_tfe_mgr_handle_reg_dump(ctx, - hw_update_data->reg_dump_buf_desc, - hw_update_data->num_reg_dump_buf, - CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST, - NULL, false); + if (g_tfe_hw_mgr.debug_cfg.per_req_reg_dump) { + if (ctx->cdm_userdata.request_id == *(uint64_t *)cookie) { + cam_tfe_mgr_handle_reg_dump(ctx, + hw_update_data->reg_dump_buf_desc, + hw_update_data->num_reg_dump_buf, + CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST, + NULL, false); + } else { + CAM_INFO(CAM_ISP, "CDM delay, Skip dump req: %llu, cdm_req: %llu", + *(uint64_t *)cookie, ctx->cdm_userdata.request_id); + } + } CAM_DBG(CAM_ISP, - "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d", - handle, userdata, status, *(uint64_t *)cookie, ctx->ctx_index); + "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d cdm_req=%llu", + handle, userdata, status, *(uint64_t *)cookie, ctx->ctx_index, + ctx->cdm_userdata.request_id); } else if (status == CAM_CDM_CB_STATUS_PAGEFAULT || status == CAM_CDM_CB_STATUS_INVALID_BL_CMD || status == CAM_CDM_CB_STATUS_HW_ERROR) { - ctx = userdata; CAM_INFO(CAM_ISP, "req_id =%d ctx_id =%d Bl_cmd_count =%d status=%d", ctx->applied_req_id, ctx->ctx_index, @@ -1771,8 +2034,9 @@ void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, } else { CAM_WARN(CAM_ISP, - "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", - handle, userdata, status, *(uint64_t *)cookie); + "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu cdm_req=%llu", + handle, userdata, status, *(uint64_t *)cookie, + ctx->cdm_userdata.request_id); } } @@ -1895,8 +2159,7 @@ static int cam_tfe_mgr_acquire_get_unified_structure_v2( in_port->lane_cfg = in->lane_cfg; in_port->num_valid_vc_dt = in->num_valid_vc_dt; - if (in_port->num_valid_vc_dt == 0 || - in_port->num_valid_vc_dt >= CAM_ISP_TFE_VC_DT_CFG) { + if (in_port->num_valid_vc_dt == 0) { CAM_ERR(CAM_ISP, "Invalid i/p arg invalid vc-dt: %d", in->num_valid_vc_dt); rc = -EINVAL; @@ -1932,6 +2195,15 @@ static int cam_tfe_mgr_acquire_get_unified_structure_v2( CAM_ISP_TFE_FLAG_BAYER_BIN; in_port->qcfa_bin = in->feature_flag & CAM_ISP_TFE_FLAG_QCFA_BIN; + in_port->shdr_en = in->feature_flag & + CAM_ISP_TFE_FLAG_SHDR_MASTER_EN; + in_port->shdr_en |= in->feature_flag & + CAM_ISP_TFE_FLAG_SHDR_SLAVE_EN; + in_port->is_shdr_master = in->feature_flag & + CAM_ISP_TFE_FLAG_SHDR_MASTER_EN; + in_port->epd_supported = in->feature_flag & + CAM_ISP_TFE_FLAG_EPD_SUPPORT; + if (in_port->bayer_bin && in_port->qcfa_bin) { CAM_ERR(CAM_ISP, @@ -1992,6 +2264,63 @@ static int cam_tfe_mgr_acquire_get_unified_structure( CAM_ERR(CAM_ISP, "Invalid ver of i/p port info from user"); return -EINVAL; } + return 0; +} + +int cam_tfe_hw_mgr_csiphy_clk_sync( + struct cam_tfe_hw_mgr_ctx *ctx, void *cmd_args) +{ + int rc = -EINVAL; + unsigned long phy_clock_rate = 0; + unsigned long csid_clk_rate = 0, tfe_clk_rate = 0, temp_clk_rate = 0; + struct cam_hw_intf *hw_intf; + int i; + + if (!ctx || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + phy_clock_rate = (*((unsigned long *)cmd_args)); + for (i = 0; i < ctx->num_base; i++) { + if (!ctx->hw_mgr->tfe_csid_dev_caps[ctx->base[i].idx].sync_clk) + continue; + + hw_intf = g_tfe_hw_mgr.csid_devices[ctx->base[i].idx]; + + temp_clk_rate = phy_clock_rate; + rc = hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_DYNAMIC_CLOCK_UPDATE, + &temp_clk_rate, sizeof(unsigned long)); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to set CSID Clock rate"); + return rc; + } + csid_clk_rate = temp_clk_rate; + + hw_intf = g_tfe_hw_mgr.tfe_devices[hw_intf->hw_idx]->hw_intf; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DYNAMIC_CLOCK_UPDATE, + &temp_clk_rate, sizeof(unsigned long)); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to set TFE Clock rate"); + return rc; + } + tfe_clk_rate = temp_clk_rate; + } + + CAM_DBG(CAM_ISP, "Clock rates: phy:%llu csid:%llu tfe:%llu", + phy_clock_rate, csid_clk_rate, tfe_clk_rate); + + if ((phy_clock_rate > csid_clk_rate) || (csid_clk_rate > tfe_clk_rate) || + (phy_clock_rate > tfe_clk_rate)) { + CAM_ERR(CAM_ISP, + "Invalid clock rates, phy:%llu csid:%llu tfe:%llu", + phy_clock_rate, csid_clk_rate, tfe_clk_rate); + + return -EINVAL; + } return 0; } @@ -2008,11 +2337,17 @@ static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) struct cam_cdm_acquire_data cdm_acquire; uint32_t num_pix_port_per_in = 0; uint32_t num_rdi_port_per_in = 0; + uint32_t num_pd_port_per_in = 0; uint32_t pdaf_enable = 0; uint32_t total_pix_port = 0; uint32_t total_rdi_port = 0; + uint32_t total_pd_port = 0; struct cam_isp_tfe_acquire_hw_info *acquire_hw_info = NULL; uint32_t input_size = 0; + bool lcr_enable = false; + bool is_shdr_en = false; + bool is_shdr_master = false; + uint32_t total_ports = 0; CAM_DBG(CAM_ISP, "Enter..."); @@ -2060,6 +2395,12 @@ static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) tfe_ctx->cdm_ops = cdm_acquire.ops; atomic_set(&tfe_ctx->cdm_done, 1); tfe_ctx->last_cdm_done_req = 0; + tfe_ctx->cdm_id = cdm_acquire.id; + tfe_ctx->current_mup = 0; + tfe_ctx->try_recovery_cnt = 0; + tfe_ctx->recovery_req_id = 0; + tfe_ctx->num_acq_tfe_out = 0; + tfe_ctx->res_list_tfe_out = NULL; acquire_hw_info = (struct cam_isp_tfe_acquire_hw_info *) acquire_args->acquire_info; @@ -2094,39 +2435,74 @@ static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) /* Check any inport has dual tfe usage */ tfe_ctx->is_dual = false; - for (i = 0; i < acquire_hw_info->num_inputs; i++) + for (i = 0; i < acquire_hw_info->num_inputs; i++) { if (in_port[i].usage_type) tfe_ctx->is_dual = true; - - /* acquire HW resources */ - for (i = 0; i < acquire_hw_info->num_inputs; i++) { - - if (in_port[i].num_out_res > CAM_TFE_HW_OUT_RES_MAX) { - CAM_ERR(CAM_ISP, "too many output res %d", - in_port[i].num_out_res); - rc = -EINVAL; - goto free_cdm; + if (in_port[i].shdr_en) { + is_shdr_en = true; + tfe_ctx->is_shdr = true; } + if (in_port[i].is_shdr_master) + is_shdr_master = true; + } - CAM_DBG(CAM_ISP, "in_res_id %x", in_port[i].res_id); - rc = cam_tfe_mgr_acquire_hw_for_ctx(tfe_ctx, &in_port[i], - &num_pix_port_per_in, &num_rdi_port_per_in, - &pdaf_enable); + if (is_shdr_en && !is_shdr_master) + tfe_ctx->is_shdr_slave = true; + + CAM_INFO(CAM_ISP, "ctx %d TFE index %d is_dual=%d is_shdr=%d shdr_master=%d", + tfe_ctx->ctx_index, tfe_ctx->base[0].idx, tfe_ctx->is_dual, + is_shdr_en, is_shdr_master); + + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + cam_tfe_hw_mgr_preprocess_port(tfe_ctx, &in_port[i], &num_pix_port_per_in, + &num_rdi_port_per_in, &num_pd_port_per_in, &pdaf_enable, &lcr_enable); total_pix_port += num_pix_port_per_in; total_rdi_port += num_rdi_port_per_in; + total_pd_port += num_pd_port_per_in; + } - if (rc) { - CAM_ERR(CAM_ISP, "can not acquire resource"); - goto free_res; - } + total_ports = total_pix_port + total_rdi_port + total_pd_port; + acquire_args->total_ports_acq = total_ports; + tfe_ctx->res_list_tfe_out = kcalloc(total_ports, + sizeof(struct cam_isp_hw_mgr_res), GFP_KERNEL); + if (!tfe_ctx->res_list_tfe_out) { + rc = -ENOMEM; + CAM_ERR(CAM_ISP, "Alloc failed for tfe out map"); + goto free_cdm; } /* Check whether context has only RDI resource */ if (!total_pix_port) { tfe_ctx->is_rdi_only_context = 1; CAM_DBG(CAM_ISP, "RDI only context"); - } else + } else { tfe_ctx->is_rdi_only_context = 0; + } + + /* acquire HW resources */ + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + + if (in_port[i].num_out_res > g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { + CAM_ERR(CAM_ISP, "too many output res %d", + in_port[i].num_out_res); + rc = -EINVAL; + goto free_res; + } + + num_pix_port_per_in = 0; + num_rdi_port_per_in = 0; + num_pd_port_per_in = 0; + + CAM_DBG(CAM_ISP, "in_res_id %x", in_port[i].res_id); + rc = cam_tfe_mgr_acquire_hw_for_ctx(tfe_ctx, &in_port[i], + &num_pix_port_per_in, &num_rdi_port_per_in, &num_pd_port_per_in, + &pdaf_enable); + + if (rc) { + CAM_ERR(CAM_ISP, "can not acquire resource"); + goto free_res; + } + } /* Process base info */ rc = cam_tfe_mgr_process_base_info(tfe_ctx); @@ -2149,10 +2525,22 @@ static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) in_port = NULL; } - if (g_tfe_hw_mgr.support_consumed_addr) + if (g_tfe_hw_mgr.isp_caps.support_consumed_addr) acquire_args->op_flags |= CAM_IFE_CTX_CONSUME_ADDR_EN; + if (is_shdr_en) { + acquire_args->op_flags |= CAM_IFE_CTX_SHDR_EN; + if (is_shdr_master) + acquire_args->op_flags |= CAM_IFE_CTX_SHDR_IS_MASTER; + g_tfe_hw_mgr.session_data[tfe_ctx->base[0].idx].is_shdr = true; + + CAM_DBG(CAM_ISP, "ctx %d TFE index %d link hdl %x", + tfe_ctx->ctx_index, tfe_ctx->base[0].idx, acquire_args->link_hdl); + } + + g_tfe_hw_mgr.session_data[tfe_ctx->base[0].idx].link_hdl = acquire_args->link_hdl; + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->used_ctx_list, &tfe_ctx); CAM_DBG(CAM_ISP, "Exit...(success)"); @@ -2162,13 +2550,17 @@ free_res: cam_tfe_hw_mgr_release_hw_for_ctx(tfe_ctx); tfe_ctx->ctx_in_use = 0; tfe_ctx->is_rdi_only_context = 0; - tfe_ctx->cdm_handle = 0; - tfe_ctx->cdm_ops = NULL; tfe_ctx->init_done = false; tfe_ctx->is_dual = false; + kfree(tfe_ctx->res_list_tfe_out); + tfe_ctx->res_list_tfe_out = NULL; free_cdm: cam_cdm_release(tfe_ctx->cdm_handle); + tfe_ctx->cdm_handle = 0; + tfe_ctx->cdm_ops = NULL; free_ctx: + kfree(tfe_ctx->tfe_bus_comp_grp); + tfe_ctx->tfe_bus_comp_grp = NULL; cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); if (in_port) { for (i = 0; i < acquire_hw_info->num_inputs; i++) { @@ -2179,8 +2571,6 @@ free_ctx: kfree(in_port); in_port = NULL; } - kfree(tfe_ctx->tfe_bus_comp_grp); - tfe_ctx->tfe_bus_comp_grp = NULL; err: /* Dump all the current acquired HW */ cam_tfe_hw_mgr_dump_all_ctx(); @@ -2264,10 +2654,13 @@ static int cam_tfe_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) struct cam_cdm_acquire_data cdm_acquire; uint32_t num_pix_port_per_in = 0; uint32_t num_rdi_port_per_in = 0; + uint32_t num_pd_port_per_in = 0; uint32_t pdad_enable = 0; uint32_t total_pix_port = 0; uint32_t total_rdi_port = 0; + uint32_t total_pd_port = 0; uint32_t in_port_length = 0; + uint32_t total_ports = 0; CAM_DBG(CAM_ISP, "Enter..."); @@ -2315,6 +2708,8 @@ static int cam_tfe_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) tfe_ctx->cdm_ops = cdm_acquire.ops; atomic_set(&tfe_ctx->cdm_done, 1); tfe_ctx->last_cdm_done_req = 0; + tfe_ctx->cdm_id = cdm_acquire.id; + tfe_ctx->current_mup = 0; isp_resource = (struct cam_isp_resource *)acquire_args->acquire_info; @@ -2352,7 +2747,7 @@ static int cam_tfe_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) u64_to_user_ptr(isp_resource[i].res_hdl), isp_resource[i].length); if (!IS_ERR(in_port)) { - if (in_port->num_out_res > CAM_TFE_HW_OUT_RES_MAX) { + if (in_port->num_out_res > g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "too many output res %d", in_port->num_out_res); rc = -EINVAL; @@ -2381,12 +2776,16 @@ static int cam_tfe_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) goto free_res; } + num_pix_port_per_in = 0; + num_rdi_port_per_in = 0; + rc = cam_tfe_mgr_acquire_hw_for_ctx(tfe_ctx, &gen_in_port[i], - &num_pix_port_per_in, &num_rdi_port_per_in, + &num_pix_port_per_in, &num_rdi_port_per_in, &num_pd_port_per_in, &pdad_enable); total_pix_port += num_pix_port_per_in; total_rdi_port += num_rdi_port_per_in; + total_pd_port += num_pd_port_per_in; kfree(in_port); in_port = NULL; @@ -2403,6 +2802,9 @@ static int cam_tfe_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) } } + total_ports = total_pix_port + total_rdi_port + total_pd_port; + acquire_args->total_ports_acq = total_ports; + /* Check whether context has only RDI resource */ if (!total_pix_port) { tfe_ctx->is_rdi_only_context = 1; @@ -2498,7 +2900,8 @@ static int cam_tfe_classify_vote_info( { int rc = 0, i, j = 0; - if (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + if ((hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) || + (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_PDLIB)) { if (split_idx == CAM_ISP_HW_SPLIT_LEFT) { if (*camif_l_bw_updated) return rc; @@ -2666,6 +3069,10 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, struct cam_tfe_hw_mgr_ctx *ctx; struct cam_isp_prepare_hw_update_data *hw_update_data; bool is_cdm_hung = false; + size_t len = 0; + uint32_t *buf_addr = NULL, *buf_start = NULL, *buf_end = NULL; + uint32_t cmd_type = 0; + unsigned long rem_jiffies = 0; if (!hw_mgr_priv || !config_hw_args) { CAM_ERR(CAM_ISP, "Invalid arguments"); @@ -2683,11 +3090,32 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, CAM_ERR(CAM_ISP, "Invalid context parameters"); return -EPERM; } - if (atomic_read(&ctx->overflow_pending)) + if (atomic_read(&ctx->overflow_pending)) { + CAM_DBG(CAM_ISP, + "Ctx[%pK][%d] Overflow pending, cannot apply req %llu", + ctx, ctx->ctx_index, cfg->request_id); return -EINVAL; + } + + + /* + * Assuming overflow recovery happens on req N, and we may + * haven't got all the result for req N while apply N + 1, + * so we reset try_recovery_cnt while apply N + 2. + */ + if (ctx->try_recovery_cnt && + (cfg->request_id > (ctx->recovery_req_id + 1))) { + ctx->try_recovery_cnt = 0; + ctx->recovery_req_id = 0; + CAM_DBG(CAM_ISP, + "Ctx[%pK][%d] Reset try_recovery count for req %llu", + ctx, ctx->ctx_index, cfg->request_id); + } hw_update_data = (struct cam_isp_prepare_hw_update_data *) cfg->priv; hw_update_data->isp_mgr_ctx = ctx; + ctx->cdm_userdata.request_id = cfg->request_id; + ctx->cdm_userdata.hw_update_data = hw_update_data; if (cfg->reapply_type && cfg->cdm_reset_before_apply) { if (ctx->last_cdm_done_req < cfg->request_id) { @@ -2750,7 +3178,7 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries; cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; cdm_cmd->flag = true; - cdm_cmd->userdata = hw_update_data; + cdm_cmd->userdata = ctx; cdm_cmd->cookie = cfg->request_id; cdm_cmd->gen_irq_arb = false; cdm_cmd->genirq_buff = &hw_update_data->kmd_cmd_buff_info; @@ -2769,6 +3197,40 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, cdm_cmd->cmd[i - skip].offset = cmd->offset; cdm_cmd->cmd[i - skip].len = cmd->len; cdm_cmd->cmd[i - skip].arbitrate = false; + + if (g_tfe_hw_mgr.debug_cfg.enable_cdm_cmd_check) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "Enter cdm cmd_buf validation"); + rc = cam_packet_util_get_cmd_mem_addr( + cdm_cmd->cmd[i - skip].bl_addr.mem_handle, &buf_addr, &len); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed to get buf_addr and len for mem_handle: %d ctx id: %u request id: %llu", + cdm_cmd->cmd[i - skip].bl_addr.mem_handle, + ctx->ctx_index, cfg->request_id); + continue; + } + + buf_start = (uint32_t *)((uint8_t *) buf_addr + + cdm_cmd->cmd[i - skip].offset); + buf_end = (uint32_t *)((uint8_t *) buf_start + + cdm_cmd->cmd[i - skip].len - 1); + cmd_type = ((uint32_t)(*buf_start) >> CAM_CDM_COMMAND_OFFSET); + if ((i == 0) && (cmd_type != CAM_CDM_CMD_CHANGE_BASE)) { + CAM_ERR(CAM_ISP, + "first cmd in cmd_buf is not change_base, cmd_type: %u ctx id: %u request id: %llu", + cmd_type, ctx->ctx_index, cfg->request_id); + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + return -EINVAL; + } + + if (cam_cdm_util_validate_cmd_buf(buf_start, buf_end)) { + CAM_ERR(CAM_ISP, + "found invalid cmd in cmd_buf, ctx id: %u request id: %llu", + ctx->ctx_index, cfg->request_id); + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + return -EINVAL; + } + } } cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; @@ -2821,16 +3283,17 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, ctx->last_submit_bl_cmd.cmd[i].input_len = cdm_cmd->cmd[i].len; } - if (!cfg->init_packet) + if (!cfg->init_packet && !hw_update_data->mup_en) goto end; for (i = 0; i < CAM_TFE_HW_CONFIG_WAIT_MAX_TRY; i++) { - rc = cam_common_wait_for_completion_timeout( + rem_jiffies = cam_common_wait_for_completion_timeout( &ctx->config_done_complete, msecs_to_jiffies( CAM_TFE_HW_CONFIG_TIMEOUT)); - if (rc <= 0) { - if (!cam_cdm_detect_hang_error(ctx->cdm_handle)) { + if (rem_jiffies <= 0) { + rc = cam_cdm_detect_hang_error(ctx->cdm_handle); + if (rc == 0) { CAM_ERR(CAM_ISP, "CDM workqueue delay detected, wait for some more time req_id=%llu rc=%d ctx_index %d", cfg->request_id, rc, @@ -2842,26 +3305,25 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE, rc); continue; - } + } else { + CAM_ERR(CAM_ISP, + "cfg_done completn timeout cdm_hang=%d req=%llu ctx_idx=%d", + cfg->request_id, rc, + ctx->ctx_index); + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("ISP", + "config done completion timeout", + cfg->request_id, ctx->ctx_index, + CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE, + rc); - CAM_ERR(CAM_ISP, - "config done completion timeout for req_id=%llu rc=%d ctx_index %d", - cfg->request_id, rc, - ctx->ctx_index); - - cam_req_mgr_debug_delay_detect(); - trace_cam_delay_detect("ISP", - "config done completion timeout", - cfg->request_id, ctx->ctx_index, - CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE, - rc); - - if (rc == 0) rc = -ETIMEDOUT; - - goto end; + break; + } } else { rc = 0; + if (hw_update_data->mup_en) + ctx->current_mup = hw_update_data->mup_val; CAM_DBG(CAM_ISP, "config done Success for req_id=%llu ctx_index %d", cfg->request_id, ctx->ctx_index); @@ -2870,8 +3332,7 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, } if ((i == CAM_TFE_HW_CONFIG_WAIT_MAX_TRY) && (rc == 0)) - rc = -ETIMEDOUT; - + CAM_DBG(CAM_ISP, "Wq delayed but IRQ CDM done"); end: CAM_DBG(CAM_ISP, "Exit: Config Done: %llu", cfg->request_id); @@ -2915,6 +3376,7 @@ static int cam_tfe_mgr_stop_hw_in_overflow(void *stop_hw_args) if (i == ctx->num_base) master_base_idx = ctx->base[0].idx; + ctx->ctx_state = CAM_TFE_HW_MGR_STATE_INACTIVE; /* stop the master CSID path first */ cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, @@ -2935,7 +3397,7 @@ static int cam_tfe_mgr_stop_hw_in_overflow(void *stop_hw_args) } /* TFE out resources */ - for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + for (i = 0; i < ctx->num_acq_tfe_out; i++) cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tfe_out[i]); /* Stop tasklet for context */ @@ -3043,13 +3505,13 @@ static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) if (i == ctx->num_base) master_base_idx = ctx->base[0].idx; + ctx->ctx_state = CAM_TFE_HW_MGR_STATE_INACTIVE; + /*Change slave mode*/ if (csid_halt_type == CAM_TFE_CSID_HALT_IMMEDIATELY) cam_tfe_mgr_csid_change_halt_mode(ctx, CAM_TFE_CSID_HALT_MODE_INTERNAL); - CAM_DBG(CAM_ISP, "Stopping master CSID idx %d", master_base_idx); - /* Stop the master CSID path first */ cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, master_base_idx, csid_halt_type); @@ -3068,7 +3530,7 @@ static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) CAM_DBG(CAM_ISP, "Going to stop TFE Out"); /* TFE out resources */ - for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + for (i = 0; i < ctx->num_acq_tfe_out; i++) cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tfe_out[i]); CAM_DBG(CAM_ISP, "Going to stop TFE IN"); @@ -3085,6 +3547,8 @@ static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) cam_common_wait_for_completion_timeout(&ctx->config_done_complete, msecs_to_jiffies(5)); + ctx->current_mup = 0; + if (stop_isp->stop_only) goto end; @@ -3170,7 +3634,7 @@ static int cam_tfe_mgr_restart_hw(void *start_hw_args) cam_tasklet_start(ctx->common.tasklet_info); /* start the TFE out devices */ - for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) { + for (i = 0; i < ctx->num_acq_tfe_out; i++) { rc = cam_tfe_hw_mgr_start_hw_res( &ctx->res_list_tfe_out[i], ctx); if (rc) { @@ -3193,7 +3657,7 @@ static int cam_tfe_mgr_restart_hw(void *start_hw_args) CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", ctx->ctx_index); /* Start the TFE CSID HW devices */ - list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + list_for_each_entry_reverse(hw_mgr_res, &ctx->res_list_tfe_csid, list) { rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); if (rc) { CAM_ERR(CAM_ISP, "Can not start TFE CSID (%d)", @@ -3202,6 +3666,8 @@ static int cam_tfe_mgr_restart_hw(void *start_hw_args) } } + ctx->ctx_state = CAM_TFE_HW_MGR_STATE_ACTIVE; + CAM_DBG(CAM_ISP, "Exit...(success)"); return 0; @@ -3220,14 +3686,14 @@ static int cam_tfe_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) struct cam_tfe_hw_mgr_ctx *ctx; struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; - uint32_t i; + uint32_t i, j, hw_index = 0; bool res_rdi_context_set = false; uint32_t primary_rdi_in_res; uint32_t primary_rdi_out_res; bool hw_id[CAM_TFE_HW_NUM_MAX] = {0}; primary_rdi_in_res = CAM_ISP_HW_TFE_IN_MAX; - primary_rdi_out_res = CAM_ISP_TFE_OUT_RES_MAX; + primary_rdi_out_res = g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type; if (!hw_mgr_priv || !start_isp) { CAM_ERR(CAM_ISP, "Invalid arguments"); @@ -3291,6 +3757,25 @@ static int cam_tfe_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) &g_tfe_hw_mgr.debug_cfg.camif_debug, sizeof(g_tfe_hw_mgr.debug_cfg.camif_debug)); hw_id[hw_intf->hw_idx] = true; + + if (ctx->is_shdr) { + for (j = 0; j < CAM_TFE_HW_NUM_MAX; j++) { + if (g_tfe_hw_mgr.session_data[j].link_hdl == + g_tfe_hw_mgr.session_data[ctx->base[0].idx].link_hdl + && (j != ctx->base[0].idx) && + g_tfe_hw_mgr.session_data[j].is_shdr) { + hw_index = j; + break; + } + } + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_SET_SYNC_HW_IDX, + &hw_index, + sizeof(hw_index)); + CAM_DBG(CAM_ISP, "TFE: %d sync idx %d", ctx->base[0].idx, hw_index); + } } } @@ -3326,7 +3811,7 @@ start_only: CAM_DBG(CAM_ISP, "START TFE OUT ... in ctx id:%d", ctx->ctx_index); /* start the TFE out devices */ - for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) { + for (i = 0; i < ctx->num_acq_tfe_out; i++) { hw_mgr_res = &ctx->res_list_tfe_out[i]; switch (hw_mgr_res->res_id) { case CAM_ISP_TFE_OUT_RES_RDI_0: @@ -3349,7 +3834,7 @@ start_only: } } - if (primary_rdi_out_res < CAM_ISP_TFE_OUT_RES_MAX) + if (primary_rdi_out_res < g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) primary_rdi_in_res = cam_tfe_hw_mgr_convert_rdi_out_res_id_to_in_res( primary_rdi_out_res); @@ -3377,7 +3862,7 @@ start_only: CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", ctx->ctx_index); /* Start the TFE CSID HW devices */ - list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + list_for_each_entry_reverse(hw_mgr_res, &ctx->res_list_tfe_csid, list) { rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); if (rc) { CAM_ERR(CAM_ISP, "Can not start TFE CSID (%d)", @@ -3386,6 +3871,9 @@ start_only: } } + ctx->ctx_state = CAM_TFE_HW_MGR_STATE_ACTIVE; + ctx->last_dump_flush_req_id = U64_MAX; + ctx->last_dump_err_req_id = U64_MAX; return 0; err: @@ -3514,6 +4002,7 @@ static int cam_tfe_mgr_dump(void *hw_mgr_priv, void *args) break; case CAM_TFE_CSID_PATH_RES_IPP: + case CAM_TFE_CSID_PATH_RES_PPP: if (hw_intf->hw_ops.process_cmd) { rc = hw_intf->hw_ops.process_cmd( hw_intf->hw_priv, @@ -3552,6 +4041,7 @@ static int cam_tfe_mgr_dump(void *hw_mgr_priv, void *args) break; case CAM_ISP_HW_TFE_IN_CAMIF: + case CAM_ISP_HW_TFE_IN_PDLIB: if (hw_intf->hw_ops.process_cmd) { rc = hw_intf->hw_ops.process_cmd( hw_intf->hw_priv, @@ -3640,6 +4130,11 @@ static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, CAM_DBG(CAM_ISP, "Enter...ctx id:%d", ctx->ctx_index); + if (ctx->is_shdr) { + g_tfe_hw_mgr.session_data[ctx->base[0].idx].link_hdl = 0; + g_tfe_hw_mgr.session_data[ctx->base[0].idx].is_shdr = false; + } + if (ctx->init_done) cam_tfe_hw_mgr_deinit_hw(ctx); @@ -3665,6 +4160,9 @@ static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, ctx->last_cdm_done_req = 0; kfree(ctx->tfe_bus_comp_grp); ctx->tfe_bus_comp_grp = NULL; + ctx->is_shdr = false; + ctx->is_shdr_slave = false; + ctx->acquired_wm_mask = 0; atomic_set(&ctx->overflow_pending, 0); for (i = 0; i < ctx->last_submit_bl_cmd.bl_count; i++) { @@ -3677,6 +4175,14 @@ static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, } ctx->last_submit_bl_cmd.bl_count = 0; ctx->packet = NULL; + ctx->current_mup = 0; + ctx->try_recovery_cnt = 0; + ctx->recovery_req_id = 0; + ctx->num_acq_tfe_out = 0; + kfree(ctx->res_list_tfe_out); + ctx->res_list_tfe_out = NULL; + + memset(ctx->tfe_out_map, 0, sizeof(uint8_t) * g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type); CAM_DBG(CAM_ISP, "Exit...ctx id:%d", ctx->ctx_index); @@ -3684,6 +4190,144 @@ static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, return rc; } +static int cam_isp_tfe_blob_buffer_alignment_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_alignment_resource_info *alignment_info, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_isp_tfe_alignment_offset_config *alignment_port_cfg; + struct cam_isp_resource_node *res; + struct cam_isp_hw_get_cmd_update cmd_update; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + uint32_t res_id_out, i; + int rc = 0; + + ctx = prepare->ctxt_to_hw_map; + for (i = 0; i < alignment_info->num_ports; i++) { + alignment_port_cfg = &alignment_info->port_alignment_cfg[i]; + res_id_out = alignment_port_cfg->resource_type & 0xFF; + + if (res_id_out >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { + CAM_ERR(CAM_ISP, "invalid out restype:%x ctx %d", + alignment_port_cfg->resource_type, ctx->ctx_index); + return -EINVAL; + } + + hw_mgr_res = &ctx->res_list_tfe_out[ctx->tfe_out_map[res_id_out]]; + res = hw_mgr_res->hw_res[0]; + hw_intf = res->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + cmd_update.res = res; + cmd_update.data = alignment_port_cfg; + cmd_update.cmd_type = CAM_ISP_HW_CMD_BUFFER_ALIGNMENT_UPDATE; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BUFFER_ALIGNMENT_UPDATE, + &cmd_update, + sizeof(struct cam_isp_hw_get_cmd_update)); + if (rc) + CAM_ERR(CAM_ISP, "Ctx %d Buffer alignment Update failed", + ctx->ctx_index); + } else { + CAM_ERR(CAM_ISP, "NULL hw_intf! ctx %d", ctx->ctx_index); + } + } + + return rc; +} + +static int cam_isp_tfe_blob_update_out_resource_config( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_out_resource_config *update_out_cfg, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_isp_tfe_wm_dimension_config *wm_dim_config; + struct cam_kmd_buf_info *kmd_buf_info; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + uint32_t res_id_out, i; + uint32_t total_used_bytes = 0; + uint32_t kmd_buf_remain_size; + uint32_t *cmd_buf_addr; + uint32_t bytes_used = 0; + int num_ent, rc = 0; + + ctx = prepare->ctxt_to_hw_map; + + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d", + prepare->num_hw_update_entries); + return -EINVAL; + } + + kmd_buf_info = blob_info->kmd_buf_info; + + for (i = 0; i < update_out_cfg->num_ports; i++) { + wm_dim_config = &update_out_cfg->dimension_config[i]; + + if ((kmd_buf_info->used_bytes + + total_used_bytes) < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + total_used_bytes); + } else { + CAM_ERR(CAM_ISP, "No free kmd memory for base idx: %d", + blob_info->base_info->idx); + rc = -ENOMEM; + return rc; + } + + cmd_buf_addr = kmd_buf_info->cpu_addr + + (kmd_buf_info->used_bytes / 4) + + (total_used_bytes / 4); + + res_id_out = wm_dim_config->res_id & 0xFF; + if (res_id_out >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { + CAM_ERR(CAM_ISP, "invalid out restype:%x", res_id_out); + return -EINVAL; + } + + hw_mgr_res = &ctx->res_list_tfe_out[ctx->tfe_out_map[res_id_out]]; + + hw_intf = cam_tfe_hw_mgr_get_hw_intf(blob_info->base_info, ctx); + rc = cam_isp_add_cmd_buf_update( + hw_mgr_res->hw_res[blob_info->base_info->split_id], hw_intf, + blob_type, CAM_ISP_HW_CMD_WM_CONFIG_UPDATE, + (void *)cmd_buf_addr, + kmd_buf_remain_size, + (void *)wm_dim_config, + &bytes_used); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Failed to update %s Out out_type:0x%X base_idx:%d bytes_used:%u rc:%d", + "TFE", blob_info->base_info->idx, bytes_used, rc); + return rc; + } + + total_used_bytes += bytes_used; + } + + if (total_used_bytes) { + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = total_used_bytes; + prepare->hw_update_entries[num_ent].offset = kmd_buf_info->offset; + prepare->hw_update_entries[num_ent].flags = CAM_ISP_IOCFG_BL; + num_ent++; + kmd_buf_info->used_bytes += total_used_bytes; + kmd_buf_info->offset += total_used_bytes; + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + static int cam_isp_tfe_blob_hfr_update( uint32_t blob_type, struct cam_isp_generic_blob_info *blob_info, @@ -3722,7 +4366,7 @@ static int cam_isp_tfe_blob_hfr_update( CAM_DBG(CAM_ISP, "hfr config idx %d, type=%d", i, res_id_out); - if (res_id_out >= CAM_TFE_HW_OUT_RES_MAX) { + if (res_id_out >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "invalid out restype:%x", port_hfr_config->resource_type); return -EINVAL; @@ -3744,7 +4388,7 @@ static int cam_isp_tfe_blob_hfr_update( cmd_buf_addr = kmd_buf_info->cpu_addr + kmd_buf_info->used_bytes/4 + total_used_bytes/4; - hw_mgr_res = &ctx->res_list_tfe_out[res_id_out]; + hw_mgr_res = &ctx->res_list_tfe_out[ctx->tfe_out_map[res_id_out]]; if (!hw_mgr_res->hw_res[blob_info->base_info->split_id]) return 0; @@ -3773,6 +4417,7 @@ static int cam_isp_tfe_blob_hfr_update( prepare->hw_update_entries[num_ent].handle = kmd_buf_info->handle; prepare->hw_update_entries[num_ent].len = total_used_bytes; + prepare->hw_update_entries[num_ent].flags = CAM_ISP_IQ_BL; prepare->hw_update_entries[num_ent].offset = kmd_buf_info->offset; num_ent++; @@ -3830,6 +4475,39 @@ static int cam_isp_tfe_blob_csid_clock_update( return rc; } +static int cam_isp_blob_tfe_init_config_update( + struct cam_hw_prepare_update_args *prepare, + struct cam_isp_init_config *init_config) +{ + int i, rc = 0; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_init_config_update init_cfg_update; + struct cam_hw_intf *hw_intf; + + ctx = prepare->ctxt_to_hw_map; + init_cfg_update.init_config = init_config; + + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].hw_type != CAM_ISP_HW_TYPE_TFE) + continue; + + hw_intf = g_tfe_hw_mgr.tfe_devices[ctx->base[i].idx]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + CAM_DBG(CAM_ISP, "Epoch/init config update for ctx %d", + ctx->ctx_index); + rc = hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_INIT_CONFIG_UPDATE, + &init_cfg_update, + sizeof(struct cam_isp_hw_init_config_update)); + if (rc) + CAM_ERR(CAM_ISP, "Epoch/init config failed rc %d ctx %d", + rc, ctx->ctx_index); + } + } + + return rc; +} + static int cam_isp_tfe_blob_clock_update( uint32_t blob_type, struct cam_isp_generic_blob_info *blob_info, @@ -3861,7 +4539,8 @@ static int cam_isp_tfe_blob_clock_update( if (!hw_mgr_res->hw_res[i]) continue; - if (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + if ((hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) || + (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_PDLIB)) { if (i == CAM_ISP_HW_SPLIT_LEFT) { if (camif_l_clk_updated) continue; @@ -3952,6 +4631,12 @@ static int cam_isp_tfe_blob_bw_limit_update( wm_bw_limit_cfg = &bw_limit_cfg->bw_limiter_config[i]; res_id_out = wm_bw_limit_cfg->res_type & 0xFF; + if (res_id_out >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { + CAM_DBG(CAM_ISP, "Invalid out resource id :%x", + res_id_out); + continue; + } + CAM_DBG(CAM_ISP, "%s BW limit config idx: %d port: 0x%x enable: %d [0x%x:0x%x]", "TFE", i, wm_bw_limit_cfg->res_type, wm_bw_limit_cfg->enable_limiter, wm_bw_limit_cfg->counter_limit[0], wm_bw_limit_cfg->counter_limit[1]); @@ -3973,7 +4658,9 @@ static int cam_isp_tfe_blob_bw_limit_update( (kmd_buf_info->used_bytes / 4) + (total_used_bytes / 4); - hw_mgr_res = &ctx->res_list_tfe_out[res_id_out]; + hw_mgr_res = &ctx->res_list_tfe_out[ctx->tfe_out_map[res_id_out]]; + if (!hw_mgr_res->hw_res[blob_info->base_info->split_id]) + continue; hw_intf = cam_tfe_hw_mgr_get_hw_intf(blob_info->base_info, ctx); rc = cam_isp_add_cmd_buf_update( @@ -4004,6 +4691,7 @@ static int cam_isp_tfe_blob_bw_limit_update( prepare->hw_update_entries[num_ent].handle = kmd_buf_info->handle; prepare->hw_update_entries[num_ent].len = total_used_bytes; + prepare->hw_update_entries[num_ent].flags = CAM_ISP_IOCFG_BL; prepare->hw_update_entries[num_ent].offset = kmd_buf_info->offset; num_ent++; @@ -4024,7 +4712,7 @@ static inline int cam_isp_tfe_validate_bw_limiter_blob( return -EINVAL; } /* Check for number of out ports*/ - if (bw_limit_config->num_ports > CAM_TFE_HW_OUT_RES_MAX) { + if (bw_limit_config->num_ports > g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "Invalid num_ports:%u", bw_limit_config->num_ports); return -EINVAL; } @@ -4052,6 +4740,59 @@ static inline int cam_isp_tfe_validate_bw_limiter_blob( return 0; } +static int cam_isp_tfe_blob_csid_discard_init_frame_update( + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_discard_initial_frames *discard_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_discard_init_frame_args discard_args; + int rc = 0, i; + + ctx = prepare->ctxt_to_hw_map; + discard_args.num_frames = discard_config->num_frames; + + if (discard_args.num_frames <= 0) { + CAM_DBG(CAM_ISP, "Invalid num of frames %d CSID[%u]", + discard_args.num_frames, blob_info->base_info->idx); + return rc; + } + + CAM_DBG(CAM_ISP, "Num of frame to be drop %d on CSID[%u]", discard_args.num_frames, + blob_info->base_info->idx); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + res = hw_mgr_res->hw_res[i]; + if (!(hw_intf && hw_intf->hw_ops.process_cmd)) + continue; + + if (hw_intf->hw_idx != blob_info->base_info->idx) + continue; + + discard_args.res = res; + rc = hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_CSID_DISCARD_INIT_FRAMES, + &discard_args, + sizeof(struct cam_tfe_csid_discard_init_frame_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed to update discard frame cfg for res: %s on CSID[%u]", + res->res_name, blob_info->base_info->idx); + } + } + } + + return rc; +} + static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) { @@ -4086,7 +4827,7 @@ static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, return -EINVAL; } - if (hfr_config->num_ports > CAM_ISP_TFE_OUT_RES_MAX) { + if (hfr_config->num_ports > g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "Invalid num_ports %u in hfr config", hfr_config->num_ports); return -EINVAL; @@ -4278,8 +5019,171 @@ static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, CAM_ERR(CAM_ISP, "BW limit update failed for TFE rc: %d", rc); } break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_DYNAMIC_MODE_SWITCH: { + struct cam_isp_mode_switch_info *mup_config; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + if (blob_size < sizeof(struct cam_isp_mode_switch_info)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(struct cam_isp_mode_switch_info)); + return -EINVAL; + } + + mup_config = (struct cam_isp_mode_switch_info *)blob_data; + CAM_DBG(CAM_ISP, + "Ctx id %d request id %lld csid mup value=%u num_exposures=%d", + tfe_mgr_ctx->ctx_index, prepare->packet->header.request_id, + mup_config->mup, mup_config->num_expoures); + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *)prepare->priv; + + prepare_hw_data->mup_en = true; + prepare_hw_data->mup_val = mup_config->mup; + prepare_hw_data->num_exp = mup_config->num_expoures; + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_INIT_CONFIG: { + struct cam_isp_init_config *init_config; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *)prepare->priv; + + if (prepare_hw_data->packet_opcode_type != CAM_ISP_PACKET_INIT_DEV) { + CAM_ERR(CAM_ISP, + "Epoch config blob not supported packet type: %u req: %llu Ctx %d", + prepare_hw_data->packet_opcode_type, + prepare->packet->header.request_id, + tfe_mgr_ctx->ctx_index); + return -EINVAL; + } + + if (blob_size != sizeof(struct cam_isp_init_config)) { + CAM_ERR(CAM_ISP, + "Invalid init config blob size %u expected %u ctx %d", + blob_size, sizeof(struct cam_isp_init_config), + tfe_mgr_ctx->ctx_index); + return -EINVAL; + } + + init_config = (struct cam_isp_init_config *)blob_data; + rc = cam_isp_blob_tfe_init_config_update(prepare, init_config); + if (rc) + CAM_ERR(CAM_ISP, + "Init config failed for req: %llu rc: %d ctx %d", + prepare->packet->header.request_id, rc, tfe_mgr_ctx->ctx_index); + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_ALIGNMENT_OFFSET_INFO: { + struct cam_isp_tfe_alignment_resource_info *alignment_info = + (struct cam_isp_tfe_alignment_resource_info *)blob_data; + + if (tfe_mgr_ctx->is_dual || !tfe_mgr_ctx->is_shdr) { + CAM_ERR(CAM_ISP, "Alignment blob can't be use in dual mode ctx %d", + tfe_mgr_ctx->ctx_index); + return -EINVAL; + } + + if (blob_size < sizeof(struct cam_isp_tfe_alignment_resource_info)) { + CAM_ERR(CAM_ISP, + "Invalid alignment blob size %u expected %u ctx %d", + blob_size, sizeof(struct cam_isp_tfe_alignment_resource_info), + tfe_mgr_ctx->ctx_index); + return -EINVAL; + } + + if (alignment_info->num_ports > g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { + CAM_ERR(CAM_ISP, "Invalid num_ports %u in alignment config", + alignment_info->num_ports); + return -EINVAL; + } + + if ((alignment_info->num_ports != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_alignment_resource_info) + + (alignment_info->num_ports - 1) * + sizeof(struct cam_isp_tfe_alignment_offset_config)))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(struct cam_isp_tfe_alignment_resource_info) + + (alignment_info->num_ports - 1) * + sizeof(struct cam_isp_tfe_alignment_offset_config)); + return -EINVAL; + } + + rc = cam_isp_tfe_blob_buffer_alignment_update(blob_type, blob_info, + alignment_info, prepare); + if (rc) + CAM_ERR(CAM_ISP, + "Alignment buffer update failed for req %lld rc %d ctx %d", + prepare->packet->header.request_id, rc, tfe_mgr_ctx->ctx_index); + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_UPDATE_OUT_RES: { + struct cam_isp_tfe_out_resource_config *update_out_config = + (struct cam_isp_tfe_out_resource_config *)blob_data; + + if (update_out_config->num_ports > g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { + CAM_ERR(CAM_ISP, "Invalid num_ports %u in update out config", + update_out_config->num_ports); + return -EINVAL; + } + + if (update_out_config->num_ports > 1) { + if (sizeof(struct cam_isp_tfe_out_resource_config) > + ((UINT_MAX - + sizeof(struct cam_isp_tfe_out_resource_config)) + / (update_out_config->num_ports - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in hfr config num_ports:%u size per port:%lu", + update_out_config->num_ports, + sizeof(struct cam_isp_tfe_out_resource_config)); + return -EINVAL; + } + } + + if ((update_out_config->num_ports != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_out_resource_config) + + (update_out_config->num_ports - 1) * + sizeof(struct cam_isp_tfe_wm_dimension_config)))) { + + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(struct cam_isp_tfe_out_resource_config) + + (update_out_config->num_ports - 1) * + sizeof(struct cam_isp_tfe_wm_dimension_config)); + return -EINVAL; + } + + rc = cam_isp_tfe_blob_update_out_resource_config(blob_type, blob_info, + update_out_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, + "Update out resource failed for req %lld rc %d ctx %d", + prepare->packet->header.request_id, rc, tfe_mgr_ctx->ctx_index); + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_DISCARD_INITIAL_FRAMES: { + struct cam_isp_discard_initial_frames *discard_config; + + if (blob_size < sizeof(struct cam_isp_tfe_discard_initial_frames)) { + CAM_ERR(CAM_ISP, + "Invalid discard frames blob size %u expected %u", + blob_size, sizeof(struct cam_isp_discard_initial_frames)); + return -EINVAL; + } + + discard_config = (struct cam_isp_discard_initial_frames *)blob_data; + + rc = cam_isp_tfe_blob_csid_discard_init_frame_update( + blob_info, discard_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Discard init frames update failed rc %d req %lld", + rc, prepare->packet->header.request_id); + } + break; default: - CAM_WARN(CAM_ISP, "Invalid blob type %d", blob_type); + CAM_WARN(CAM_ISP, "Invalid blob type %d ctx %d", blob_type, + tfe_mgr_ctx->ctx_index); break; } @@ -4291,6 +5195,7 @@ static int cam_tfe_update_dual_config( uint32_t split_id, uint32_t base_idx, struct cam_isp_hw_mgr_res *res_list_isp_out, + uint8_t *out_map, uint32_t size_isp_out) { int rc = -EINVAL; @@ -4363,7 +5268,7 @@ static int cam_tfe_update_dual_config( goto end; } - hw_mgr_res = &res_list_isp_out[outport_id]; + hw_mgr_res = &res_list_isp_out[out_map[outport_id & 0xFF]]; if (!hw_mgr_res->hw_res[j]) continue; @@ -4373,7 +5278,7 @@ static int cam_tfe_update_dual_config( res = hw_mgr_res->hw_res[j]; if (res->res_id < CAM_ISP_TFE_OUT_RES_BASE || - res->res_id >= CAM_ISP_TFE_OUT_RES_MAX) { + res->res_id >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_DBG(CAM_ISP, "res id :%d", res->res_id); continue; } @@ -4403,6 +5308,7 @@ int cam_tfe_add_command_buffers( struct cam_isp_ctx_base_info *base_info, cam_packet_generic_blob_handler blob_handler_cb, struct cam_isp_hw_mgr_res *res_list_isp_out, + uint8_t *out_map, uint32_t size_isp_out) { int rc = 0; @@ -4503,11 +5409,13 @@ int cam_tfe_add_command_buffers( case CAM_ISP_TFE_PACKET_META_DUAL_CONFIG: rc = cam_tfe_update_dual_config(&cmd_desc[i], split_id, - base_idx, res_list_isp_out, size_isp_out); + base_idx, res_list_isp_out, out_map, size_isp_out); if (rc) return rc; break; + case CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_LEFT: + case CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_RIGHT: case CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_COMMON: { struct cam_isp_generic_blob_info blob_info; @@ -4576,6 +5484,7 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, struct cam_isp_change_base_args change_base_info = {0}; struct cam_isp_check_io_cfg_for_scratch check_for_scratch = {0}; struct cam_isp_io_buf_info io_buf_info = {0}; + struct cam_isp_mode_switch_data mup_config; if (!hw_mgr_priv || !prepare_hw_update_args) { CAM_ERR(CAM_ISP, "Invalid args"); @@ -4622,7 +5531,7 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, i, ctx->base[i].idx); change_base_info.base_idx = ctx->base[i].idx; - change_base_info.cdm_id = CAM_CDM_MAX; + change_base_info.cdm_id = ctx->cdm_id; /* Add change base */ rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, @@ -4634,14 +5543,15 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, goto end; } - /* get command buffers */ if (ctx->base[i].split_id != CAM_ISP_HW_SPLIT_MAX) { rc = cam_tfe_add_command_buffers(prepare, &prepare_hw_data->kmd_cmd_buff_info, &ctx->base[i], cam_isp_tfe_packet_generic_blob_handler, - ctx->res_list_tfe_out, CAM_TFE_HW_OUT_RES_MAX); + ctx->res_list_tfe_out, + ctx->tfe_out_map, + g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type); if (rc) { CAM_ERR(CAM_ISP, "Failed in add cmdbuf, i=%d, split_id=%d, rc=%d", @@ -4654,6 +5564,8 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, sizeof(struct cam_isp_frame_header_info)); frame_header_info.frame_header_enable = false; + prepare_hw_data->wm_bitmask = ctx->acquired_wm_mask; + /* get IO buffers */ io_buf_info.frame_hdr = &frame_header_info; io_buf_info.scratch_check_cfg = &check_for_scratch; @@ -4665,8 +5577,9 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, io_buf_info.base = &ctx->base[i]; io_buf_info.fill_fence = fill_fence; io_buf_info.out_base = CAM_ISP_TFE_OUT_RES_BASE; - io_buf_info.out_max = CAM_TFE_HW_OUT_RES_MAX; + io_buf_info.out_max = g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type; io_buf_info.res_list_isp_out = ctx->res_list_tfe_out; + io_buf_info.out_map = ctx->tfe_out_map; rc = cam_isp_add_io_buffers(&io_buf_info); if (rc) { @@ -4727,7 +5640,7 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, /* add reg update commands */ for (i = 0; i < ctx->num_base; i++) { change_base_info.base_idx = ctx->base[i].idx; - change_base_info.cdm_id = CAM_CDM_MAX; + change_base_info.cdm_id = ctx->cdm_id; /* Add change base */ rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, &change_base_info, &prepare_hw_data->kmd_cmd_buff_info); @@ -4738,9 +5651,16 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, goto end; } + mup_config.mup = prepare_hw_data->mup_val; + mup_config.num_expoures = prepare_hw_data->num_exp; + mup_config.mup_en = prepare_hw_data->mup_en; + + if (ctx->is_shdr_slave) + continue; + /*Add reg update */ rc = cam_isp_add_reg_update(prepare, &ctx->res_list_tfe_in, - ctx->base[i].idx, &prepare_hw_data->kmd_cmd_buff_info, false); + ctx->base[i].idx, &prepare_hw_data->kmd_cmd_buff_info, false, &mup_config); if (rc) { CAM_ERR(CAM_ISP, "Add Reg_update cmd Failed i=%d, idx=%d, rc=%d", @@ -4772,18 +5692,17 @@ static int cam_tfe_mgr_cmd_get_last_consumed_addr( uint32_t res_id_out; struct cam_isp_resource_node *res; struct cam_isp_hw_mgr_res *hw_mgr_res; - struct list_head *res_list_isp_src; res_id_out = done->resource_handle & 0xFF; - if (res_id_out >= CAM_TFE_HW_OUT_RES_MAX) { + if (res_id_out >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "Invalid out resource id :%x", - res_id); - return; + res_id_out); + return rc; } hw_mgr_res = - &ctx->res_list_tfe_out[res_id_out]; + &ctx->res_list_tfe_out[ctx->tfe_out_map[res_id_out]]; for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { if (!hw_mgr_res->hw_res[i]) @@ -4889,7 +5808,7 @@ static void cam_tfe_mgr_pf_dump(uint32_t res_id, res_id_out = res_id & 0xFF; - if (res_id_out >= CAM_TFE_HW_OUT_RES_MAX) { + if (res_id_out >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "Invalid out resource id :%x", res_id); return; @@ -4914,6 +5833,58 @@ static void cam_tfe_mgr_pf_dump(uint32_t res_id, } } +static int cam_tfe_mgr_prog_default_settings(struct cam_tfe_hw_mgr_ctx *ctx) +{ + int rc = 0, i; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res; + struct list_head *res_list; + struct cam_isp_hw_get_cmd_update rup_args; + struct cam_isp_mode_switch_data mup_config; + + + res_list = &ctx->res_list_tfe_in; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + if (hw_mgr_res->res_type != CAM_ISP_RESOURCE_TFE_IN) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + rup_args.res = hw_mgr_res->hw_res[i]; + rup_args.cmd.cmd_buf_addr = NULL; + rup_args.cmd.size = 0; + rup_args.cmd_type = CAM_ISP_HW_CMD_GET_REG_UPDATE; + rup_args.reg_write = true; + + mup_config.mup = ctx->current_mup; + + rup_args.data = &mup_config; + + res = rup_args.res; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_REG_UPDATE, &rup_args, + sizeof(struct cam_isp_hw_get_cmd_update)); + + if (rc) { + CAM_ERR(CAM_ISP, "failed for TFE: %d mup: %d ctx id:%d", + res->hw_intf->hw_idx, ctx->current_mup, ctx->ctx_index); + return rc; + } + + CAM_DBG(CAM_ISP, + "Reg update for TFE: %d mup: %d ctx id:%d", + res->hw_intf->hw_idx, ctx->current_mup, ctx->ctx_index); + } + + } + + return rc; +} + static void cam_tfe_mgr_dump_pf_data( struct cam_tfe_hw_mgr *hw_mgr, struct cam_hw_cmd_args *hw_cmd_args) @@ -4982,14 +5953,14 @@ static void cam_tfe_mgr_dump_pf_data( return; } - for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) { + for (i = 0; i < ctx->num_acq_tfe_out; i++) { hw_mgr_res = &ctx->res_list_tfe_out[i]; if (!hw_mgr_res->hw_res[0]) continue; break; } - if (i >= CAM_TFE_HW_OUT_RES_MAX) { + if (i >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { CAM_ERR(CAM_ISP, "NO valid outport resources ctx id:%d req id:%lld", ctx->ctx_index, packet->header.request_id); @@ -4998,6 +5969,7 @@ static void cam_tfe_mgr_dump_pf_data( } get_res.mid = pf_cmd_args->pf_args->pf_smmu_info->mid; + get_res.pid = pf_cmd_args->pf_args->pf_smmu_info->pid; cmd_update.res = hw_mgr_res->hw_res[0]; cmd_update.cmd_type = CAM_ISP_HW_CMD_GET_RES_FOR_MID; cmd_update.data = (void *) &get_res; @@ -5028,6 +6000,38 @@ outportlog: } +static void *cam_tfe_mgr_user_dump_stream_info( + void *dump_struct, uint8_t *addr_ptr) +{ + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_isp_resource_node *hw_res = NULL; + int32_t *addr; + int i; + int hw_idx[CAM_ISP_HW_SPLIT_MAX] = { -1, -1 }; + + ctx = (struct cam_tfe_hw_mgr_ctx *)dump_struct; + + if (!list_empty(&ctx->res_list_tfe_in)) { + hw_mgr_res = list_first_entry(&ctx->res_list_tfe_in, + struct cam_isp_hw_mgr_res, list); + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + hw_res = hw_mgr_res->hw_res[i]; + if (hw_res && hw_res->hw_intf) + hw_idx[i] = hw_res->hw_intf->hw_idx; + } + } + + addr = (int32_t *)addr_ptr; + + *addr++ = ctx->is_dual; + *addr++ = hw_idx[CAM_ISP_HW_SPLIT_LEFT]; + *addr++ = hw_idx[CAM_ISP_HW_SPLIT_RIGHT]; + + return addr; +} + static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) { int rc = 0; @@ -5098,12 +6102,24 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) sizeof(struct cam_tfe_hw_comp_record) * CAM_TFE_BUS_COMP_NUM_MAX); break; + case CAM_ISP_HW_MGR_CMD_PROG_DEFAULT_CFG: + rc = cam_tfe_mgr_prog_default_settings(ctx); + break; case CAM_ISP_HW_MGR_GET_SOF_TS: rc = cam_tfe_mgr_cmd_get_sof_timestamp(ctx, &isp_hw_cmd_args->u.sof_ts.curr, &isp_hw_cmd_args->u.sof_ts.boot, &isp_hw_cmd_args->u.sof_ts.prev); - break; + break; + case CAM_ISP_HW_MGR_CMD_UPDATE_CLOCK: + rc = cam_tfe_hw_mgr_csiphy_clk_sync(ctx, isp_hw_cmd_args->cmd_data); + break; + case CAM_ISP_HW_MGR_DUMP_STREAM_INFO: + rc = cam_common_user_dump_helper( + (void *)(isp_hw_cmd_args->cmd_data), + cam_tfe_mgr_user_dump_stream_info, ctx, + sizeof(int32_t), "ISP_STREAM_INFO_FROM_TFE_HW_MGR:"); + break; case CAM_ISP_HW_MGR_GET_LAST_CONSUMED_ADDR: rc = cam_tfe_mgr_cmd_get_last_consumed_addr(ctx, (struct cam_isp_hw_done_event_data *)(isp_hw_cmd_args->cmd_data)); @@ -5538,65 +6554,136 @@ end: return 0; } -static int cam_tfe_hw_mgr_handle_csid_event( - uint32_t err_type, - struct cam_isp_hw_event_info *event_info) +static int cam_tfe_hw_mgr_handle_hw_dump_info( + void *ctx, + void *evt_info) { - struct cam_isp_hw_error_event_data error_event_data = {0}; - struct cam_tfe_hw_event_recovery_data recovery_data = {0}; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = + (struct cam_tfe_hw_mgr_ctx *)ctx; + struct cam_isp_hw_event_info *event_info = + (struct cam_isp_hw_event_info *)evt_info; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_hw_intf *hw_intf; + uint32_t i = 0, out_port_id = 0; + uint64_t dummy_args = 0; + int rc = 0; - /* this can be extended based on the types of error - * received from CSID - */ - switch (err_type) { - case CAM_ISP_HW_ERROR_CSID_FATAL: { - - if (!g_tfe_hw_mgr.debug_cfg.enable_csid_recovery) - break; - - error_event_data.error_type = err_type; - cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, - event_info->hw_idx, - &recovery_data); - break; + for (i = 0; i < tfe_hw_mgr_ctx->num_base; i++) { + hw_intf = g_tfe_hw_mgr.csid_devices[tfe_hw_mgr_ctx->base[i].idx]; + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CSID_CLOCK_DUMP, + &dummy_args, + sizeof(uint64_t)); + if (rc) + CAM_ERR(CAM_ISP, + "CSID Clock Dump failed"); + } } - default: - break; + + if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + out_port_id = event_info->res_id & 0xFF; + if (out_port_id >= g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type) { + CAM_ERR(CAM_ISP, + "Resource out of range"); + goto end; + } + hw_mgr_res = + &tfe_hw_mgr_ctx->res_list_tfe_out[tfe_hw_mgr_ctx->tfe_out_map[out_port_id]]; + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_BUS_INFO, + (void *)event_info, + sizeof(struct cam_isp_hw_event_info)); + } + } } +end: + return rc; +} + +static int cam_tfe_hw_mgr_check_and_notify_overflow( + struct cam_isp_hw_event_info *evt, + struct cam_tfe_hw_mgr_ctx *hw_mgr_ctx, + bool *is_bus_overflow) +{ + int i; + struct cam_hw_intf *hw_if = NULL; + struct cam_isp_hw_overflow_info overflow_info; + + for (i = 0; i < hw_mgr_ctx->num_base; i++) { + if (hw_mgr_ctx->base[i].idx != evt->hw_idx) + continue; + + hw_if = g_tfe_hw_mgr.tfe_devices[evt->hw_idx]->hw_intf; + if (!hw_if) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "hw_intf is null"); + return -EINVAL; + } + + if (hw_if->hw_ops.process_cmd) { + overflow_info.res_id = evt->res_id; + hw_if->hw_ops.process_cmd(hw_if->hw_priv, + CAM_ISP_HW_NOTIFY_OVERFLOW, + &overflow_info, + sizeof(struct cam_isp_hw_overflow_info)); + + CAM_DBG(CAM_ISP, + "check and notify hw idx %d type %d bus overflow happened %d", + hw_mgr_ctx->base[i].idx, hw_mgr_ctx->base[i].hw_type, + overflow_info.is_bus_overflow); + + if (overflow_info.is_bus_overflow) + *is_bus_overflow = true; + } + } + return 0; } -static int cam_tfe_hw_mgr_handle_hw_err( - void *evt_info) +static int cam_tfe_hw_mgr_handle_tfe_err( + uint32_t err_type, + struct cam_isp_hw_event_info *event_info, + struct cam_tfe_hw_mgr_ctx *ctx) { - struct cam_isp_hw_error_event_info *err_evt_info; - struct cam_isp_hw_event_info *event_info = evt_info; struct cam_isp_hw_error_event_data error_event_data = {0}; struct cam_tfe_hw_event_recovery_data recovery_data = {0}; - int rc = -EINVAL; uint32_t core_idx; + int rc = -EINVAL; - if (!event_info->event_data) { - CAM_ERR(CAM_ISP, "No error event data failed to process"); - return rc; - } - - err_evt_info = (struct cam_isp_hw_error_event_info *)event_info->event_data; - if (err_evt_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION) + switch (err_type) { + case CAM_TFE_IRQ_STATUS_VIOLATION: error_event_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; - else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_IN || - event_info->res_type == CAM_ISP_RESOURCE_PIX_PATH) - error_event_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; - else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) - error_event_data.error_type = CAM_ISP_HW_ERROR_BUSIF_OVERFLOW; + break; + case CAM_TFE_IRQ_STATUS_OUT_OF_SYNC: + error_event_data.error_type = CAM_ISP_HW_ERROR_CSID_SENSOR_FRAME_DROP; + if (ctx->try_recovery_cnt < MAX_TFE_INTERNAL_RECOVERY_ATTEMPTS) { + error_event_data.try_internal_recovery = true; + if (!atomic_read(&ctx->overflow_pending)) + ctx->try_recovery_cnt++; - spin_lock(&g_tfe_hw_mgr.ctx_lock); - if (err_evt_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) { - rc = cam_tfe_hw_mgr_handle_csid_event(err_evt_info->err_type, event_info); - spin_unlock(&g_tfe_hw_mgr.ctx_lock); - return rc; + if (!ctx->recovery_req_id) + ctx->recovery_req_id = ctx->applied_req_id; + } + CAM_INFO(CAM_ISP, + "TFE: %u error: %u current_recovery_cnt: %u recovery_req: %llu on ctx: %u", + event_info->hw_idx, error_event_data.error_type, + ctx->try_recovery_cnt, ctx->recovery_req_id, + ctx->ctx_index); + break; + default: + error_event_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + break; } + cam_tfe_hw_mgr_handle_hw_dump_info(ctx, event_info); + core_idx = event_info->hw_idx; if (g_tfe_hw_mgr.debug_cfg.enable_recovery) @@ -5606,26 +6693,146 @@ static int cam_tfe_hw_mgr_handle_hw_err( rc = cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, core_idx, &recovery_data); + if (rc || !(recovery_data.no_of_context)) - goto end; - - if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) { - spin_unlock(&g_tfe_hw_mgr.ctx_lock); return rc; - } - if (g_tfe_hw_mgr.debug_cfg.enable_recovery) { + if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) + return rc; + + if (!error_event_data.try_internal_recovery && g_tfe_hw_mgr.debug_cfg.enable_recovery) { /* Trigger for recovery */ - if (err_evt_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION) + if (err_type == CAM_TFE_IRQ_STATUS_VIOLATION) recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; else recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; cam_tfe_hw_mgr_do_error_recovery(&recovery_data); } else { - CAM_DBG(CAM_ISP, "recovery is not enabled"); + CAM_DBG(CAM_ISP, "recovery enabled: %d, internal_recovery: %d, ctx: %d", + error_event_data.try_internal_recovery, + g_tfe_hw_mgr.debug_cfg.enable_recovery, + ctx->ctx_index); rc = 0; } -end: + + return rc; +} + +static int cam_tfe_hw_mgr_handle_csid_event( + uint32_t err_type, + struct cam_isp_hw_event_info *event_info, + void *ctx) +{ + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_tfe_hw_event_recovery_data recovery_data = {0}; + bool is_bus_overflow = false; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + + /* Default error types */ + error_event_data.error_type = CAM_ISP_HW_ERROR_CSID_FATAL; + recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + + /* this can be extended based on the types of error + * received from CSID + */ + switch (err_type) { + case CAM_ISP_HW_ERROR_CSID_FRAME_SIZE: + case CAM_ISP_HW_ERROR_CSID_FATAL: { + + if (!g_tfe_hw_mgr.debug_cfg.enable_csid_recovery) { + CAM_ERR(CAM_ISP, + "CSID:%d err: %d not handled, csid_recovery_enable: %d", + event_info->hw_idx, err_type, + g_tfe_hw_mgr.debug_cfg.enable_csid_recovery); + return 0; + } + break; + } + case CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW: { + cam_tfe_hw_mgr_check_and_notify_overflow(event_info, + tfe_hw_mgr_ctx, &is_bus_overflow); + + if (is_bus_overflow) { + if (tfe_hw_mgr_ctx->try_recovery_cnt < + MAX_TFE_INTERNAL_RECOVERY_ATTEMPTS) { + + error_event_data.try_internal_recovery = true; + if (!atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + tfe_hw_mgr_ctx->try_recovery_cnt++; + + if (!tfe_hw_mgr_ctx->recovery_req_id) + tfe_hw_mgr_ctx->recovery_req_id = + tfe_hw_mgr_ctx->applied_req_id; + + error_event_data.error_type = err_type; + } + + CAM_DBG(CAM_ISP, + "CSID[%u] error: %u current_recovery_cnt: %u recovery_req: %llu", + event_info->hw_idx, err_type, tfe_hw_mgr_ctx->try_recovery_cnt, + tfe_hw_mgr_ctx->recovery_req_id); + } + break; + } + default: + CAM_ERR(CAM_ISP, "CSID:%d, unahandled error: %d", + event_info->hw_idx, err_type); + return 0; + } + + CAM_ERR(CAM_ISP, "CSID:[%u] error: %u on ctx: %u", event_info->hw_idx, + error_event_data.error_type, tfe_hw_mgr_ctx->ctx_index); + + cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, event_info->hw_idx, + &recovery_data); + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_err( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_error_event_info *err_evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx; + struct cam_isp_hw_event_info *event_info = evt_info; + int rc = -EINVAL; + + if (!event_info->event_data) { + CAM_ERR(CAM_ISP, "No error event data failed to process"); + return rc; + } + + if (ctx) + tfe_hw_mgr_ctx = (struct cam_tfe_hw_mgr_ctx *)ctx; + else { + CAM_ERR(CAM_ISP, "tfe hw mgr ctx NULL"); + return rc; + } + + if (!tfe_hw_mgr_ctx->ctx_state) { + CAM_INFO(CAM_ISP, "TFE Hw mgr ctx is not in active state ctx %d", + tfe_hw_mgr_ctx->ctx_index); + return rc; + } + + err_evt_info = (struct cam_isp_hw_error_event_info *)event_info->event_data; + + spin_lock(&g_tfe_hw_mgr.ctx_lock); + switch (event_info->hw_type) { + case CAM_ISP_HW_TYPE_TFE_CSID: + rc = cam_tfe_hw_mgr_handle_csid_event(err_evt_info->err_type, event_info, + tfe_hw_mgr_ctx); + break; + + case CAM_ISP_HW_TYPE_TFE: + rc = cam_tfe_hw_mgr_handle_tfe_err(err_evt_info->err_type, event_info, + tfe_hw_mgr_ctx); + break; + + default: + CAM_ERR(CAM_ISP, "Error unhandled for hw_type: %d", event_info->hw_type); + } spin_unlock(&g_tfe_hw_mgr.ctx_lock); return rc; } @@ -5665,6 +6872,8 @@ static int cam_tfe_hw_mgr_handle_hw_rup( CAM_ISP_HW_EVENT_REG_UPDATE, (void *)&rup_event_data); break; + case CAM_ISP_HW_TFE_IN_PDLIB: + break; default: CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", event_info->res_id); @@ -5700,6 +6909,7 @@ static int cam_tfe_hw_mgr_handle_hw_epoch( case CAM_ISP_HW_TFE_IN_RDI0: case CAM_ISP_HW_TFE_IN_RDI1: case CAM_ISP_HW_TFE_IN_RDI2: + case CAM_ISP_HW_TFE_IN_PDLIB: break; default: @@ -5752,6 +6962,8 @@ static int cam_tfe_hw_mgr_handle_hw_sof( CAM_ISP_HW_EVENT_SOF, (void *)&sof_done_event_data); break; + case CAM_ISP_HW_TFE_IN_PDLIB: + break; default: CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", event_info->res_id); @@ -5794,6 +7006,9 @@ static int cam_tfe_hw_mgr_handle_hw_eof( CAM_ISP_HW_EVENT_EOF, (void *)&eof_done_event_data); break; + case CAM_ISP_HW_TFE_IN_PDLIB: + break; + default: CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", event_info->res_id); @@ -5892,7 +7107,7 @@ static int cam_tfe_hw_mgr_event_handler( break; case CAM_ISP_HW_EVENT_ERROR: - rc = cam_tfe_hw_mgr_handle_hw_err(evt_info); + rc = cam_tfe_hw_mgr_handle_hw_err(priv, evt_info); break; default: @@ -5988,7 +7203,7 @@ static int cam_tfe_hw_mgr_debug_register(void) rc = cam_debugfs_create_subdir("tfe", &dbgfileptr); if (rc) { - CAM_ERR(CAM_ISP,"DebugFS could not create directory!"); + CAM_ERR(CAM_ISP, "DebugFS could not create directory!"); rc = -ENOENT; goto end; } @@ -6011,6 +7226,8 @@ static int cam_tfe_hw_mgr_debug_register(void) debugfs_create_u32("per_req_reg_dump", 0644, g_tfe_hw_mgr.debug_cfg.dentry, &g_tfe_hw_mgr.debug_cfg.per_req_reg_dump); + debugfs_create_bool("enable_cdm_cmd_check", 0644, g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.enable_cdm_cmd_check); if (IS_ERR(dbgfileptr)) { if (PTR_ERR(dbgfileptr) == -ENODEV) CAM_WARN(CAM_ISP, "DebugFS not enabled in kernel!"); @@ -6033,12 +7250,13 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) int i, j; struct cam_iommu_handle cdm_handles; struct cam_tfe_hw_mgr_ctx *ctx_pool; - struct cam_isp_hw_mgr_res *res_list_tfe_out; - bool support_consumed_addr = false; + struct cam_isp_hw_path_port_map path_port_map; + struct cam_isp_hw_cap isp_cap = {0}; CAM_DBG(CAM_ISP, "Enter"); memset(&g_tfe_hw_mgr, 0, sizeof(g_tfe_hw_mgr)); + memset(&path_port_map, 0, sizeof(path_port_map)); mutex_init(&g_tfe_hw_mgr.ctx_mutex); spin_lock_init(&g_tfe_hw_mgr.ctx_lock); @@ -6058,16 +7276,30 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) g_tfe_hw_mgr.tfe_devices[i]->hw_intf->hw_priv; struct cam_hw_soc_info *soc_info = &tfe_hw->soc_info; - if (j == 0) + if (j == 0) { tfe_device->hw_ops.process_cmd( tfe_hw, - CAM_ISP_HW_CMD_IS_CONSUMED_ADDR_SUPPORT, - &support_consumed_addr, - sizeof(support_consumed_addr)); + CAM_ISP_HW_CMD_QUERY_CAP, + &isp_cap, + sizeof(struct cam_isp_hw_cap)); + CAM_DBG(CAM_ISP, + "max TFE out resources: 0x%x supported consume add: 0x%x", + isp_cap.max_out_res_type, isp_cap.support_consumed_addr); + + tfe_device->hw_ops.process_cmd( + tfe_hw, + CAM_ISP_HW_CMD_GET_PATH_PORT_MAP, + &path_port_map, + sizeof(struct cam_isp_hw_path_port_map)); + CAM_DBG(CAM_ISP, "received %d path-port mappings", + path_port_map.num_entries); + } j++; g_tfe_hw_mgr.cdm_reg_map[i] = &soc_info->reg_map[0]; + g_tfe_hw_mgr.session_data[i].link_hdl = 0; + g_tfe_hw_mgr.session_data[i].is_shdr = false; CAM_DBG(CAM_ISP, "reg_map: mem base = %pK cam_base = 0x%llx", (void __iomem *)soc_info->reg_map[0].mem_base, @@ -6081,7 +7313,18 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) return -EINVAL; } - g_tfe_hw_mgr.support_consumed_addr = support_consumed_addr; + g_tfe_hw_mgr.isp_caps.support_consumed_addr = + isp_cap.support_consumed_addr; + g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type = + isp_cap.max_out_res_type; + memset(&isp_cap, 0x0, sizeof(struct cam_isp_hw_cap)); + + for (i = 0; i < path_port_map.num_entries; i++) { + g_tfe_hw_mgr.path_port_map.entry[i][0] = path_port_map.entry[i][0]; + g_tfe_hw_mgr.path_port_map.entry[i][1] = path_port_map.entry[i][1]; + } + g_tfe_hw_mgr.path_port_map.num_entries = path_port_map.num_entries; + /* fill csid hw intf information */ for (i = 0, j = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { rc = cam_tfe_csid_hw_init(&g_tfe_hw_mgr.csid_devices[i], i); @@ -6141,9 +7384,15 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].res_list_tfe_csid); INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].res_list_tfe_in); ctx_pool = &g_tfe_hw_mgr.ctx_pool[i]; - for (j = 0; j < CAM_TFE_HW_OUT_RES_MAX; j++) { - res_list_tfe_out = &ctx_pool->res_list_tfe_out[j]; - INIT_LIST_HEAD(&res_list_tfe_out->list); + + g_tfe_hw_mgr.ctx_pool[i].tfe_out_map = + kzalloc((g_tfe_hw_mgr.isp_caps.max_tfe_out_res_type * sizeof(uint8_t)), + GFP_KERNEL); + if (!g_tfe_hw_mgr.ctx_pool[i].tfe_out_map) { + rc = -ENOMEM; + CAM_ERR(CAM_ISP, "Alloc failed for tfe_out_map, ctx_idx: %u", + g_tfe_hw_mgr.ctx_pool[i].ctx_index); + goto end; } /* init context pool */ @@ -6192,6 +7441,7 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) /* fill return structure */ hw_mgr_intf->hw_mgr_priv = &g_tfe_hw_mgr; hw_mgr_intf->hw_get_caps = cam_tfe_mgr_get_hw_caps; + hw_mgr_intf->hw_get_caps_v2 = cam_tfe_mgr_get_hw_caps_v2; hw_mgr_intf->hw_acquire = cam_tfe_mgr_acquire; hw_mgr_intf->hw_start = cam_tfe_mgr_start_hw; hw_mgr_intf->hw_stop = cam_tfe_mgr_stop_hw; @@ -6208,6 +7458,20 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) *iommu_hdl = g_tfe_hw_mgr.mgr_common.img_iommu_hdl; cam_tfe_hw_mgr_debug_register(); + cam_tfe_mgr_count_functional_tfe(); + + cam_tfe_get_num_tfe_hws(&g_num_tfe_available); + rc = cam_cpas_prepare_subpart_info(CAM_IFE_HW_IDX, g_num_tfe_available, + g_num_tfe_functional); + if (rc) + CAM_ERR(CAM_ISP, "Failed to populate num_ifes, rc: %d", rc); + + cam_tfe_get_num_tfe_lite_hws(&g_num_tfe_lite_available); + rc = cam_cpas_prepare_subpart_info(CAM_IFE_LITE_HW_IDX, g_num_tfe_lite_available, + g_num_tfe_lite_functional); + if (rc) + CAM_ERR(CAM_ISP, "Failed to populate num_ife_lites, rc: %d", rc); + CAM_DBG(CAM_ISP, "Exit"); return 0; @@ -6218,6 +7482,8 @@ end: &g_tfe_hw_mgr.mgr_common.tasklet_pool[i]); kfree(g_tfe_hw_mgr.ctx_pool[i].cdm_cmd); g_tfe_hw_mgr.ctx_pool[i].cdm_cmd = NULL; + kfree(g_tfe_hw_mgr.ctx_pool[i].tfe_out_map); + g_tfe_hw_mgr.ctx_pool[i].tfe_out_map = NULL; g_tfe_hw_mgr.ctx_pool[i].common.tasklet_info = NULL; } } @@ -6242,6 +7508,8 @@ void cam_tfe_hw_mgr_deinit(void) &g_tfe_hw_mgr.mgr_common.tasklet_pool[i]); kfree(g_tfe_hw_mgr.ctx_pool[i].cdm_cmd); g_tfe_hw_mgr.ctx_pool[i].cdm_cmd = NULL; + kfree(g_tfe_hw_mgr.ctx_pool[i].tfe_out_map); + g_tfe_hw_mgr.ctx_pool[i].tfe_out_map = NULL; g_tfe_hw_mgr.ctx_pool[i].common.tasklet_info = NULL; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index 37801fb91c..d8be7490cb 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_TFE_HW_MGR_H_ @@ -19,7 +19,6 @@ /* TFE resource constants */ #define CAM_TFE_HW_IN_RES_MAX (CAM_ISP_TFE_IN_RES_MAX & 0xFF) -#define CAM_TFE_HW_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_MAX & 0xFF) #define CAM_TFE_HW_RES_POOL_MAX 64 /** @@ -32,7 +31,7 @@ * @camif_debug: enable sensor diagnosis status * @enable_reg_dump: enable reg dump on error; * @per_req_reg_dump: Enable per request reg dump - * + * @enable_cdm_cmd_check: Enable invalid command check in cmd_buf */ struct cam_tfe_hw_mgr_debug { struct dentry *dentry; @@ -42,6 +41,7 @@ struct cam_tfe_hw_mgr_debug { uint32_t camif_debug; uint32_t enable_reg_dump; uint32_t per_req_reg_dump; + bool enable_cdm_cmd_check; }; /** @@ -71,6 +71,28 @@ struct cam_tfe_comp_record_query { void *reserved; }; +/** + * struct cam_tfe_cdm_user_data - TFE HW user data with CDM + * + * @prepare: hw_update_data + * @request_id: Request id + */ +struct cam_tfe_cdm_user_data { + struct cam_isp_prepare_hw_update_data *hw_update_data; + uint64_t request_id; +}; + +/** + * struct cam_isp_tfe_hw_caps - BUS capabilities + * + * @max_tfe_out_res_type : max tfe out res type value from hw + * @support_consumed_addr : indicate whether hw supports last consumed address + */ +struct cam_isp_tfe_hw_caps { + uint32_t max_tfe_out_res_type; + bool support_consumed_addr; +}; + /** * struct cam_tfe_hw_mgr_ctx - TFE HW manager Context object * @@ -82,7 +104,9 @@ struct cam_tfe_comp_record_query { * @res_list_csid: csid resource list * @res_list_tfe_in: tfe input resource list * @res_list_tfe_out: tfe output resoruces array + * @num_acq_tfe_out: Number of acquired TFE out resources * @free_res_list: free resources list for the branch node + * @tfe_out_map: Map for TFE out ports * @res_pool: memory storage for the free resource list * @base device base index array contain the all TFE HW * instance associated with this context. @@ -113,6 +137,14 @@ struct cam_tfe_comp_record_query { * @packet CSL packet from user mode driver * @bw_config_version BW Config version * @tfe_bus_comp_grp pointer to tfe comp group info + * @cdm_userdata CDM user data + * @try_recovery_cnt Retry count for overflow recovery + * @current_mup Current MUP val + * @recovery_req_id The request id on which overflow recovery happens + * @acquired_wm_mask Bitmask of acquired out resource + * @is_shdr Indicate if the usecase is SHDR + * @is_shdr_slave Indicate whether context is slave in shdr usecase + * @ctx_state Indicate if ctx is active or paused */ struct cam_tfe_hw_mgr_ctx { struct list_head list; @@ -124,10 +156,11 @@ struct cam_tfe_hw_mgr_ctx { struct list_head res_list_tfe_csid; struct list_head res_list_tfe_in; - struct cam_isp_hw_mgr_res - res_list_tfe_out[CAM_TFE_HW_OUT_RES_MAX]; + struct cam_isp_hw_mgr_res *res_list_tfe_out; + uint32_t num_acq_tfe_out; struct list_head free_res_list; + uint8_t *tfe_out_map; struct cam_isp_hw_mgr_res res_pool[CAM_TFE_HW_RES_POOL_MAX]; struct cam_isp_ctx_base_info base[CAM_TFE_HW_NUM_MAX]; @@ -156,6 +189,15 @@ struct cam_tfe_hw_mgr_ctx { struct cam_packet *packet; uint32_t bw_config_version; struct cam_tfe_hw_comp_record *tfe_bus_comp_grp; + struct cam_tfe_cdm_user_data cdm_userdata; + uint32_t current_mup; + uint32_t try_recovery_cnt; + uint64_t recovery_req_id; + uint64_t acquired_wm_mask; + enum cam_cdm_id cdm_id; + bool is_shdr; + bool is_shdr_slave; + uint32_t ctx_state; }; /** @@ -172,31 +214,35 @@ struct cam_tfe_hw_mgr_ctx { * @free_ctx_list: free hw context list * @used_ctx_list: used hw context list * @ctx_pool: context storage + * @session_data: Data related to current session * @tfe_csid_dev_caps csid device capability stored per core * @tfe_dev_caps tfe device capability per core * @work q work queue for TFE hw manager * @debug_cfg debug configuration - * @support_consumed_addr indicate whether hw supports last consumed address + * @path_port_map Mapping of outport to TFE mux * @ctx_lock Spinlock for HW manager + * @isp_caps Capability of underlying TFE HW */ struct cam_tfe_hw_mgr { - struct cam_isp_hw_mgr mgr_common; - struct cam_hw_intf *csid_devices[CAM_TFE_CSID_HW_NUM_MAX]; - struct cam_isp_hw_intf_data *tfe_devices[CAM_TFE_HW_NUM_MAX]; - struct cam_soc_reg_map *cdm_reg_map[CAM_TFE_HW_NUM_MAX]; - struct mutex ctx_mutex; - atomic_t active_ctx_cnt; - struct list_head free_ctx_list; - struct list_head used_ctx_list; - struct cam_tfe_hw_mgr_ctx ctx_pool[CAM_TFE_CTX_MAX]; + struct cam_isp_hw_mgr mgr_common; + struct cam_hw_intf *csid_devices[CAM_TFE_CSID_HW_NUM_MAX]; + struct cam_isp_hw_intf_data *tfe_devices[CAM_TFE_HW_NUM_MAX]; + struct cam_soc_reg_map *cdm_reg_map[CAM_TFE_HW_NUM_MAX]; + struct mutex ctx_mutex; + atomic_t active_ctx_cnt; + struct list_head free_ctx_list; + struct list_head used_ctx_list; + struct cam_tfe_hw_mgr_ctx ctx_pool[CAM_TFE_CTX_MAX]; + struct cam_isp_session_data session_data[CAM_TFE_HW_NUM_MAX]; - struct cam_tfe_csid_hw_caps tfe_csid_dev_caps[ + struct cam_tfe_csid_hw_caps tfe_csid_dev_caps[ CAM_TFE_CSID_HW_NUM_MAX]; - struct cam_tfe_hw_get_hw_cap tfe_dev_caps[CAM_TFE_HW_NUM_MAX]; - struct cam_req_mgr_core_workq *workq; - struct cam_tfe_hw_mgr_debug debug_cfg; - bool support_consumed_addr; - spinlock_t ctx_lock; + struct cam_tfe_hw_get_hw_cap tfe_dev_caps[CAM_TFE_HW_NUM_MAX]; + struct cam_req_mgr_core_workq *workq; + struct cam_tfe_hw_mgr_debug debug_cfg; + struct cam_isp_hw_path_port_map path_port_map; + spinlock_t ctx_lock; + struct cam_isp_tfe_hw_caps isp_caps; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index 3c5e695208..6410798377 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -767,8 +767,8 @@ static int cam_isp_io_buf_get_entries_util( &buf_info->scratch_check_cfg->ife_scratch_res_info, io_cfg->resource_type); } - *hw_mgr_res = &buf_info->res_list_isp_out[buf_info->out_map[res_id]]; + if ((*hw_mgr_res)->res_type == CAM_ISP_RESOURCE_UNINT) { CAM_ERR(CAM_ISP, "io res id:%d not valid", io_cfg->resource_type); @@ -852,9 +852,8 @@ static int cam_isp_add_io_buffers_util( struct cam_hw_fence_map_entry *out_map_entry = NULL; struct cam_smmu_buffer_tracker *old_head_entry, *new_head_entry; uint32_t kmd_buf_remain_size; - uint32_t plane_id; - uint32_t num_entries; - + uint32_t plane_id; + int num_entries; dma_addr_t *image_buf_addr; uint32_t *image_buf_offset; size_t size; @@ -1014,7 +1013,6 @@ static int cam_isp_add_io_buffers_util( num_entries = buf_info->prepare->num_out_map_entries - 1; out_map_entry = &buf_info->prepare->out_map_entries[num_entries]; - if (!out_map_entry) { CAM_ERR(CAM_ISP, "out_map_entry is NULL"); rc = -EINVAL; @@ -1126,7 +1124,7 @@ int cam_isp_add_io_buffers(struct cam_isp_io_buf_info *io_info) int rc = 0; struct cam_buf_io_cfg *io_cfg = NULL; struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; - uint32_t i; + uint32_t i, j; uint32_t curr_used_bytes = 0; uint32_t bytes_updated = 0; struct cam_isp_resource_node *res = NULL; @@ -1135,6 +1133,8 @@ int cam_isp_add_io_buffers(struct cam_isp_io_buf_info *io_info) uint8_t max_out_res = 0; uint64_t *mc_cfg = NULL; uint32_t major_version = 0; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + uint64_t cfg_io_mask = 0, disabled_wm_mask = 0; io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) &io_info->prepare->packet->payload + @@ -1161,6 +1161,7 @@ int cam_isp_add_io_buffers(struct cam_isp_io_buf_info *io_info) } } + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) io_info->prepare->priv; for (i = 0; i < io_info->prepare->packet->num_io_configs; i++) { if (major_version == 3) { @@ -1195,6 +1196,8 @@ int cam_isp_add_io_buffers(struct cam_isp_io_buf_info *io_info) if (!res) continue; + cfg_io_mask |= (1 << (res->res_id & 0xFF)); + rc = cam_isp_add_io_buffers_util(io_info, &io_cfg[i], res); if (rc) { CAM_ERR(CAM_ISP, "io_cfg[%d] add buf failed rc %d", i, rc); @@ -1217,9 +1220,26 @@ int cam_isp_add_io_buffers(struct cam_isp_io_buf_info *io_info) vfree(mc_cfg); } + disabled_wm_mask = (prepare_hw_data->wm_bitmask ^ cfg_io_mask); + + if ((io_info->base->hw_type == CAM_ISP_HW_TYPE_TFE) && disabled_wm_mask) { + for (j = 0; j < io_info->out_max; j++) { + rc = cam_isp_add_disable_wm_update(io_info->prepare, + &io_info->res_list_isp_out[io_info->out_map[j]], + io_info->base->idx, io_info->kmd_buf_info, + &disabled_wm_mask, + io_info); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Disable out res %d failed", + j, rc); + return rc; + } + } + } + bytes_updated = io_info->kmd_buf_info->used_bytes - curr_used_bytes; - CAM_DBG(CAM_ISP, "io_cfg_used_bytes %d, fill_fence %d", - bytes_updated, io_info->fill_fence); + CAM_DBG(CAM_ISP, "io_cfg_used_bytes %d, fill_fence %d acuired mask %x cfg mask %x", + bytes_updated, io_info->fill_fence, prepare_hw_data->wm_bitmask, cfg_io_mask); if (bytes_updated) { /** @@ -1240,17 +1260,82 @@ err: return rc; } +int cam_isp_add_disable_wm_update( + struct cam_hw_prepare_update_args *prepare, + struct cam_isp_hw_mgr_res *isp_hw_res, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info, + uint64_t *wm_mask, + struct cam_isp_io_buf_info *io_info) +{ + int rc = 0; + struct cam_hw_intf *hw_intf; + struct cam_isp_resource_node *res; + struct cam_isp_hw_get_cmd_update wm_update; + uint32_t kmd_buf_remain_size, i; + + if (prepare->packet->header.request_id == 0) + return 0; + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + res = isp_hw_res->hw_res[i]; + if (res->hw_intf->hw_idx != base_idx) + continue; + if (!(*wm_mask & (1 << res->res_id))) { + CAM_DBG(CAM_ISP, "No need to disable out res %d", res->res_id); + continue; + } + + *wm_mask &= ~BIT(res->res_id); + + if (kmd_buf_info->used_bytes < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - kmd_buf_info->used_bytes; + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base=%d bytes_used=%u buf_size=%u", + base_idx, kmd_buf_info->used_bytes, kmd_buf_info->size); + rc = -EINVAL; + return rc; + } + + wm_update.cmd.cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4; + wm_update.cmd.size = kmd_buf_remain_size; + wm_update.cmd_type = CAM_ISP_HW_CMD_BUS_WM_DISABLE; + wm_update.res = res; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_BUS_WM_DISABLE, &wm_update, + sizeof(struct cam_isp_hw_get_cmd_update)); + if (rc) { + CAM_ERR(CAM_ISP, "Diaable res %d failed split %d", + res->res_id, i); + return rc; + } + CAM_DBG(CAM_ISP, + "Out res %d disable update added hw_id %d cdm_idx %d split id: %d", + res->res_id, res->hw_intf->hw_idx, base_idx, i); + + io_info->kmd_buf_info->used_bytes += wm_update.cmd.used_bytes; + io_info->kmd_buf_info->offset += wm_update.cmd.used_bytes; + } + return rc; +} + int cam_isp_add_reg_update( struct cam_hw_prepare_update_args *prepare, struct list_head *res_list_isp_src, uint32_t base_idx, struct cam_kmd_buf_info *kmd_buf_info, - bool combine) + bool combine, + void *priv_data) { int rc = -EINVAL; - struct cam_isp_resource_node *res; - struct cam_isp_hw_mgr_res *hw_mgr_res; - struct cam_isp_hw_get_cmd_update get_regup; + struct cam_isp_resource_node *res; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_get_cmd_update get_regup; uint32_t kmd_buf_remain_size, i, reg_update_size; /* Max one hw entries required for each base */ @@ -1296,6 +1381,8 @@ int cam_isp_add_reg_update( get_regup.cmd_type = CAM_ISP_HW_CMD_GET_REG_UPDATE; get_regup.res = res; + get_regup.data = priv_data; + rc = res->hw_intf->hw_ops.process_cmd( res->hw_intf->hw_priv, CAM_ISP_HW_CMD_GET_REG_UPDATE, &get_regup, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h index 8fdf7148c8..3b41508f29 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_ISP_HW_PARSER_H_ @@ -278,6 +278,27 @@ int cam_isp_add_command_buffers( */ int cam_isp_add_io_buffers(struct cam_isp_io_buf_info *io_info); +/* + * cam_isp_add_disable_wm_update() + * + * @brief Add disable wm command + * + * @prepare: Contain the packet and HW update variables + * @isp_hw_res: Resource list for IFE/VFE out resource + * @base_idx: Base or dev index of the IFE/VFE HW instance + * @kmd_buf_info: Kmd buffer to store the change base command + * @wm_mask Bit mask of unconfigured resource + * @io_info IO buf info + * + */ +int cam_isp_add_disable_wm_update( + struct cam_hw_prepare_update_args *prepare, + struct cam_isp_hw_mgr_res *isp_hw_res, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info, + uint64_t *wm_mask, + struct cam_isp_io_buf_info *io_info); + /* * cam_isp_add_reg_update() * @@ -290,6 +311,7 @@ int cam_isp_add_io_buffers(struct cam_isp_io_buf_info *io_info); * @base_idx: Base or dev index of the IFE/VFE HW instance * @kmd_buf_info: Kmd buffer to store the change base command * @combine: Indicate whether combine with prev update entry + * @priv_data: private data for HW driver * @return: 0 for success * -EINVAL for Fail */ @@ -298,7 +320,8 @@ int cam_isp_add_reg_update( struct list_head *res_list_isp_src, uint32_t base_idx, struct cam_kmd_buf_info *kmd_buf_info, - bool combine); + bool combine, + void *priv_data); /* * cam_isp_add_comp_wait() diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index a3c5fd987b..ec9dbbaaf0 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -24,7 +24,7 @@ #define CAM_ISP_BW_CONFIG_V1 1 #define CAM_ISP_BW_CONFIG_V2 2 #define CAM_ISP_BW_CONFIG_V3 3 -#define CAM_TFE_HW_NUM_MAX 3 +#define CAM_TFE_HW_NUM_MAX 4 #define CAM_TFE_RDI_NUM_MAX 3 #define CAM_IFE_SCRATCH_NUM_MAX 2 #define CAM_IFE_BUS_COMP_NUM_MAX 18 @@ -33,7 +33,7 @@ #define CAM_TFE_BUS_COMP_NUM_MAX 18 /* maximum context numbers for TFE */ -#define CAM_TFE_CTX_MAX 4 +#define CAM_TFE_CTX_MAX 6 /* maximum context numbers for IFE */ #define CAM_IFE_CTX_MAX 8 @@ -49,6 +49,8 @@ #define CAM_IFE_CTX_SFE_EN BIT(4) #define CAM_IFE_CTX_AEB_EN BIT(5) #define CAM_IFE_CTX_DYNAMIC_SWITCH_EN BIT(6) +#define CAM_IFE_CTX_SHDR_EN BIT(7) +#define CAM_IFE_CTX_SHDR_IS_MASTER BIT(8) /* * Maximum configuration entry size - This is based on the @@ -346,6 +348,7 @@ struct cam_isp_fcg_config_info { * @packet: CSL packet from user mode driver * @mup_val: MUP value if configured * @num_exp: Num of exposures + * @wm_bitmask: Bitmask of acquired out resource * @mup_en: Flag if dynamic sensor switch is enabled * @fcg_info: Track FCG config for further usage in config stage * @@ -368,7 +371,7 @@ struct cam_isp_prepare_hw_update_data { struct cam_kmd_buf_info kmd_cmd_buff_info; uint32_t mup_val; uint32_t num_exp; - uint32_t configured_rup_aup; + uint64_t wm_bitmask; bool mup_en; struct cam_isp_fcg_config_info fcg_info; }; @@ -477,8 +480,8 @@ enum cam_isp_hw_mgr_command { CAM_ISP_HW_MGR_GET_SOF_TS, CAM_ISP_HW_MGR_DUMP_STREAM_INFO, CAM_ISP_HW_MGR_GET_BUS_COMP_GROUP, + CAM_ISP_HW_MGR_CMD_UPDATE_CLOCK, CAM_ISP_HW_MGR_GET_LAST_CONSUMED_ADDR, - CAM_ISP_HW_MGR_GET_PATH_SOF_TS, CAM_ISP_HW_MGR_CMD_MAX, }; @@ -547,6 +550,21 @@ struct cam_isp_lcr_rdi_cfg_args { bool is_init; }; + +/** + * struct cam_isp_mode_switch_data - isp hardware mode update arguments + * + * @mup Mup value + * @num_expoures Number of exposures + * @mup_en Flag to indicate if mup is enable + * + */ +struct cam_isp_mode_switch_data { + uint32_t mup; + uint32_t num_expoures; + bool mup_en; +}; + /** * cam_isp_hw_mgr_init() * diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid860.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid860.h new file mode 100644 index 0000000000..e839f87b38 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid860.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_860_H_ +#define _CAM_IFE_CSID_860_H_ + +#include +#include "cam_ife_csid_dev.h" +#include "camera_main.h" +#include "cam_ife_csid_common.h" +#include "cam_ife_csid_hw_ver2.h" +#include "cam_irq_controller.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_ife_csid880.h" + +#define CAM_CSID_VERSION_V860 0x80060000 + +static struct cam_ife_csid_ver2_reg_info cam_ife_csid_860_reg_info = { + .top_irq_reg_info = cam_ife_csid_880_top_irq_reg_info, + .rx_irq_reg_info = cam_ife_csid_880_rx_irq_reg_info, + .path_irq_reg_info = { + &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0], + &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1], + &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2], + &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3], + &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_4], + &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP], + &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_PPP], + }, + .buf_done_irq_reg_info = &cam_ife_csid_880_buf_done_irq_reg_info, + .cmn_reg = &cam_ife_csid_880_cmn_reg_info, + .csi2_reg = &cam_ife_csid_880_csi2_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_IPP] = &cam_ife_csid_880_ipp_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_PPP] = &cam_ife_csid_880_ppp_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_880_rdi_0_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_1] = &cam_ife_csid_880_rdi_1_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_880_rdi_2_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_880_rdi_3_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_4] = &cam_ife_csid_880_rdi_4_reg_info, + .top_reg = &cam_ife_csid_880_top_reg_info, + .input_core_sel = { + { + 0x0, + 0x1, + 0x2, + 0x3, + -1, + -1, + -1, + -1, + }, + { + 0x0, + 0x1, + 0x2, + 0x3, + -1, + -1, + -1, + -1, + }, + { + 0x0, + 0x1, + 0x2, + 0x3, + -1, + -1, + -1, + -1, + }, + }, + .need_top_cfg = 0x1, + .top_irq_desc = &cam_ife_csid_880_top_irq_desc, + .rx_irq_desc = &cam_ife_csid_880_rx_irq_desc, + .path_irq_desc = cam_ife_csid_880_path_irq_desc, + .num_top_err_irqs = cam_ife_csid_880_num_top_irq_desc, + .num_rx_err_irqs = cam_ife_csid_880_num_rx_irq_desc, + .num_path_err_irqs = ARRAY_SIZE(cam_ife_csid_880_path_irq_desc), + .num_top_regs = 1, + .num_rx_regs = 1, + .width_fuse_max_val = 1, + .fused_max_dualife_width = {7296, 5344, UINT_MAX}, + .fused_max_width = {7296, 7296, UINT_MAX}, + .is_ife_sfe_mapped = true, +}; + +#endif /*_CAM_IFE_CSID_860_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid880.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid880.h index f5b9caaf69..8dc23631fb 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid880.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid880.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_IFE_CSID_880_H_ @@ -1508,5 +1508,6 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_880_reg_info = { .num_path_err_irqs = ARRAY_SIZE(cam_ife_csid_880_path_irq_desc), .num_top_regs = 1, .num_rx_regs = 1, + .is_ife_sfe_mapped = true, }; #endif /*_CAM_IFE_CSID_880_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c index 64628375bb..10ef60059c 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c @@ -684,6 +684,12 @@ int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info, } mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(soc_info, base_id); + if (mem_base == -1) { + CAM_ERR(CAM_ISP, "failed to get mem_base, index: %d num_reg_map: %u", + base_id, soc_info->num_reg_map); + return -EINVAL; + } + if (cdm_args->cdm_id == CAM_CDM_RT) { if (!soc_private->rt_wrapper_base) { CAM_ERR(CAM_ISP, "rt_wrapper_base_addr is null"); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c index 8a3dfa1546..f5c7eeebf0 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c @@ -116,6 +116,12 @@ static void cam_ife_csid_component_unbind(struct device *dev, const struct of_device_id *match_dev = NULL; hw_intf = (struct cam_hw_intf *)platform_get_drvdata(pdev); + + if (!hw_intf) { + CAM_ERR(CAM_ISP, "Error No data in hw_intf"); + return; + } + hw_info = hw_intf->hw_priv; CAM_DBG(CAM_ISP, "CSID:%d component unbind", diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c index 3433f635f8..e6f731b384 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -721,9 +721,8 @@ static int cam_ife_csid_ver1_deinit_rdi_path( if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || res->res_id > CAM_IFE_PIX_PATH_RES_RDI_4) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -782,9 +781,8 @@ static int cam_ife_csid_ver1_deinit_udi_path( (res->res_id < CAM_IFE_PIX_PATH_RES_UDI_0 || res->res_id > CAM_IFE_PIX_PATH_RES_UDI_2)) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -841,9 +839,8 @@ static int cam_ife_csid_ver1_deinit_pxl_path( if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -903,9 +900,8 @@ static int cam_ife_csid_ver1_stop_pxl_path( if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -987,9 +983,8 @@ static int cam_ife_csid_ver1_stop_rdi_path( if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -1045,9 +1040,8 @@ static int cam_ife_csid_ver1_stop_udi_path( if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -1827,6 +1821,14 @@ int cam_ife_csid_ver1_release(void *hw_priv, csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); path_cfg = (struct cam_ife_csid_ver1_path_cfg *)res->res_priv; + + if (path_cfg->cid >= CAM_IFE_CSID_CID_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid cid:%d", + csid_hw->hw_intf->hw_idx, path_cfg->cid); + rc = -EINVAL; + goto end; + } + cam_ife_csid_cid_release(&csid_hw->cid_data[path_cfg->cid], csid_hw->hw_intf->hw_idx, path_cfg->cid); @@ -1869,9 +1871,8 @@ static int cam_ife_csid_ver1_start_rdi_path( if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || res->res_id > CAM_IFE_PIX_PATH_RES_RDI_4) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -1921,9 +1922,8 @@ static int cam_ife_csid_ver1_start_udi_path( (res->res_id < CAM_IFE_PIX_PATH_RES_UDI_0 || res->res_id > CAM_IFE_PIX_PATH_RES_UDI_2)) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -1974,9 +1974,8 @@ static int cam_ife_csid_ver1_start_pix_path( if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { CAM_ERR(CAM_ISP, - "CSID:%d %s path res type:%d res_id:%d Invalid state%d", - csid_hw->hw_intf->hw_idx, - res->res_name, + "CSID:%d %s path res_type:%d res_id:%d Invalid state:%d", + csid_hw->hw_intf->hw_idx, res->res_name, res->res_type, res->res_id, res->res_state); return -EINVAL; } @@ -2720,7 +2719,6 @@ static int cam_ife_csid_ver1_enable_hw(struct cam_ife_csid_ver1_hw *csid_hw) csid_hw->flags.fatal_err_detected = false; csid_hw->flags.device_enabled = true; spin_unlock_irqrestore(&csid_hw->lock_state, flags); - cam_tasklet_start(csid_hw->tasklet); return rc; @@ -2742,8 +2740,6 @@ int cam_ife_csid_ver1_init_hw(void *hw_priv, struct cam_hw_info *hw_info; int rc = 0; - - if (!hw_priv || !init_args || (arg_size != sizeof(struct cam_isp_resource_node))) { CAM_ERR(CAM_ISP, "CSID: Invalid args"); @@ -2752,7 +2748,7 @@ int cam_ife_csid_ver1_init_hw(void *hw_priv, hw_info = (struct cam_hw_info *)hw_priv; csid_hw = (struct cam_ife_csid_ver1_hw *)hw_info->core_info; - + rc = cam_ife_csid_ver1_enable_hw(csid_hw); if (rc) { @@ -2901,7 +2897,6 @@ static int cam_ife_csid_ver1_disable_hw( cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->top_irq_mask_addr); - cam_tasklet_stop(csid_hw->tasklet); rc = cam_ife_csid_disable_soc_resources(soc_info); if (rc) CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", @@ -3802,9 +3797,6 @@ static int cam_ife_csid_ver1_process_cmd(void *hw_priv, case CAM_ISP_HW_CMD_CSID_DUMP_CROP_REG: /* Not supported in V1*/ break; - case CAM_IFE_CSID_CMD_GET_PATH_TIME_STAMP: - /* Not supported in V1*/ - break; default: CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", csid_hw->hw_intf->hw_idx, cmd_type); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c index f430569e81..c6e0d28f05 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1327,9 +1327,6 @@ static inline uint32_t cam_ife_csid_ver2_input_core_to_hw_idx(int core_sel) } } -static int cam_ife_csid_ver2_dump_frame_stats( - struct cam_ife_csid_ver2_hw *csid_hw); - static int cam_ife_csid_ver2_handle_event_err( struct cam_ife_csid_ver2_hw *csid_hw, uint32_t irq_status, @@ -1382,7 +1379,6 @@ static int cam_ife_csid_ver2_handle_event_err( cam_ife_csid_ver2_input_core_to_hw_idx(csid_hw->top_cfg.input_core_type); cam_ife_csid_ver2_print_camif_timestamps(csid_hw); - cam_ife_csid_ver2_dump_frame_stats(csid_hw); csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_ERROR, (void *)&evt); @@ -1667,7 +1663,7 @@ void cam_ife_csid_hw_ver2_drv_err_handler(void *csid) void cam_ife_csid_hw_ver2_mup_mismatch_handler( void *csid, void *resource) { - uint32_t idx = 0, val; + uint32_t idx = 0; struct timespec64 current_ts; struct cam_ife_csid_ver2_hw *csid_hw = csid; struct cam_isp_resource_node *res = resource; @@ -1694,16 +1690,16 @@ void cam_ife_csid_hw_ver2_mup_mismatch_handler( if (path_cfg->ts_comb_vcdt_en) { ktime_get_boottime_ts64(¤t_ts); - val = cam_io_r_mb(soc_info->reg_map[0].mem_base + - path_reg->timestamp_curr0_sof_addr); - idx = val & csid_reg->cmn_reg->ts_comb_vcdt_mask; + idx = cam_io_r_mb(soc_info->reg_map[0].mem_base + + path_reg->timestamp_curr0_sof_addr) & + csid_reg->cmn_reg->ts_comb_vcdt_mask; if (idx < CAM_IFE_CSID_MULTI_VC_DT_GRP_MAX) CAM_INFO(CAM_ISP, - "CSID:%d Received frame with vc:%d on [id: %d name: %s] timestamp: %lld.%09lld register value: 0x%x", + "CSID:%d Received frame with vc:%d on [id: %d name: %s] timestamp: %lld.%09lld", csid_hw->hw_intf->hw_idx, cid_data->vc_dt[idx].vc, res->res_id, res->res_name, current_ts.tv_sec, - current_ts.tv_nsec, val); + current_ts.tv_nsec); else CAM_ERR(CAM_ISP, "CSID:%d Get invalid vc index: %d on [id: %d name: %s] timestamp: %lld.%09lld", @@ -1749,7 +1745,8 @@ void cam_ife_csid_ver2_print_illegal_programming_irq_status( cfg1 = cam_io_r_mb(base + path_reg->cfg1_addr); vcdt_cfg0 = cam_io_r_mb(base + path_reg->multi_vcdt_cfg0_addr); - CAM_INFO(CAM_ISP, "cfg0 = %x cfg1 = %x vcdt_cfg0 = %x ", cfg0, cfg1, vcdt_cfg0); + CAM_INFO(CAM_ISP, "cfg0 = %x cfg1 = %x vcdt_cfg0 = %x vcrop %x", cfg0, cfg1, vcdt_cfg0, + cam_io_r_mb(base + path_reg->vcrop_addr)); if (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid) { decode_fmt = ((cfg0 >> @@ -1962,7 +1959,6 @@ static int cam_ife_csid_ver2_parse_path_irq_status( if ((irq_status & IFE_CSID_VER2_PATH_INFO_INPUT_SOF)) csid_hw->counters.irq_debug_cnt++; - if (csid_hw->counters.irq_debug_cnt >= CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX) { cam_ife_csid_ver2_sof_irq_debug(csid_hw, @@ -2474,9 +2470,8 @@ static int cam_ife_csid_ver2_rdi_bottom_half( /* Only notify if secondary event is subscribed for */ if ((path_cfg->sec_evt_config.en_secondary_evt) && (path_cfg->sec_evt_config.evt_type & - CAM_IFE_CSID_EVT_SENSOR_SYNC_FRAME_DROP)) { - do_notify = true; - } + CAM_IFE_CSID_EVT_SENSOR_SYNC_FRAME_DROP)) + do_notify = true; /* Validate error threshold for primary RDI (master) */ if (res->is_rdi_primary_res) { @@ -2561,6 +2556,7 @@ int cam_ife_csid_ver2_get_hw_caps(void *hw_priv, hw_caps->is_lite = soc_private->is_ife_csid_lite; hw_caps->sfe_ipp_input_rdi_res = csid_reg->cmn_reg->sfe_ipp_input_rdi_res; hw_caps->camif_irq_support = csid_reg->cmn_reg->camif_irq_support; + hw_caps->is_ife_sfe_mapped = csid_reg->is_ife_sfe_mapped; CAM_DBG(CAM_ISP, "CSID:%u num-rdis:%d, num-pix:%d, major:%d minor:%d ver:%d", @@ -2678,7 +2674,7 @@ static int cam_ife_csid_ver2_reset_irq_top_half(uint32_t evt_id, } static int cam_ife_csid_ver2_internal_reset( - struct cam_ife_csid_ver2_hw *csid_hw, bool power_on_rst, + struct cam_ife_csid_ver2_hw *csid_hw, uint32_t rst_cmd, uint32_t rst_location, uint32_t rst_mode) { uint32_t val = 0; @@ -2707,18 +2703,9 @@ static int cam_ife_csid_ver2_internal_reset( cam_io_w_mb(0x0, mem_base + csi2_reg->cfg1_addr); } - /* - * After power on once the connection has been established - * between master and slave CSIDs, issuing a reset to master - * will also reset the slave. Reset to the slave is only needed - * when powering on the cores since at this point the master-slave - * connection is not established yet - */ - if ((csid_hw->sync_mode == CAM_ISP_HW_SYNC_SLAVE) && (!power_on_rst)) + if (csid_hw->sync_mode == CAM_ISP_HW_SYNC_SLAVE) goto wait_only; - CAM_DBG(CAM_ISP, "CSID[%u] issuing reset", csid_hw->hw_intf->hw_idx); - reinit_completion(&csid_hw->hw_info->hw_complete); /* Program the reset location */ @@ -2779,16 +2766,14 @@ int cam_ife_csid_ver2_reset(void *hw_priv, switch (reset->reset_type) { case CAM_IFE_CSID_RESET_GLOBAL: - rc = cam_ife_csid_ver2_internal_reset( - csid_hw, reset->power_on_reset, + rc = cam_ife_csid_ver2_internal_reset(csid_hw, CAM_IFE_CSID_RESET_CMD_SW_RST, CAM_IFE_CSID_RESET_LOC_COMPLETE, CAM_CSID_HALT_IMMEDIATELY); break; case CAM_IFE_CSID_RESET_PATH: - rc = cam_ife_csid_ver2_internal_reset( - csid_hw, reset->power_on_reset, + rc = cam_ife_csid_ver2_internal_reset(csid_hw, CAM_IFE_CSID_RESET_CMD_HW_RST, CAM_IFE_CSID_RESET_LOC_PATH_ONLY, CAM_CSID_HALT_IMMEDIATELY); @@ -3362,6 +3347,82 @@ end: return rc; } +static bool cam_ife_csid_ver2_is_width_valid_by_fuse( + struct cam_csid_hw_reserve_resource_args *reserve, + struct cam_ife_csid_ver2_hw *csid_hw, + uint32_t width) +{ + struct cam_ife_csid_ver2_reg_info *csid_reg; + uint32_t fuse_val = UINT_MAX; + + csid_reg = (struct cam_ife_csid_ver2_reg_info *) + csid_hw->core_info->csid_reg; + + cam_cpas_is_feature_supported(CAM_CPAS_MP_LIMIT_FUSE, CAM_CPAS_HW_IDX_ANY, &fuse_val); + if (fuse_val == UINT_MAX) { + CAM_DBG(CAM_ISP, "CSID[%u] MP limit fuse not present", + csid_hw->hw_intf->hw_idx); + return true; + } + + if ((fuse_val > csid_reg->width_fuse_max_val) || + (fuse_val >= CAM_IFE_CSID_WIDTH_FUSE_VAL_MAX)) { + CAM_ERR(CAM_ISP, "Invalid fuse value %u", fuse_val); + return false; + } + + if (((reserve->sync_mode == CAM_ISP_HW_SYNC_SLAVE) || + (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER)) && + (width > csid_reg->fused_max_dualife_width[fuse_val])) { + CAM_ERR(CAM_ISP, + "CSID[%u] Resolution not supported required_width dualife: %d max_supported_width: %d", + csid_hw->hw_intf->hw_idx, + width, csid_reg->fused_max_dualife_width[fuse_val]); + return false; + + } else if (width > csid_reg->fused_max_width[fuse_val]) { + CAM_ERR(CAM_ISP, + "CSID[%u] Resolution not supported required_width: %d max_supported_width: %d", + csid_hw->hw_intf->hw_idx, + width, csid_reg->fused_max_width[fuse_val]); + return false; + } + + return true; +} + +bool cam_ife_csid_ver2_is_width_valid( + struct cam_csid_hw_reserve_resource_args *reserve, + struct cam_ife_csid_ver2_hw *csid_hw) +{ + uint32_t width = 0; + struct cam_csid_soc_private *soc_private; + + soc_private = (struct cam_csid_soc_private *)csid_hw->hw_info->soc_info.soc_private; + + if ((reserve->res_id != CAM_IFE_PIX_PATH_RES_IPP) || soc_private->is_ife_csid_lite) + return true; + + if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER || + reserve->sync_mode == CAM_ISP_HW_SYNC_NONE) + width = reserve->in_port->left_stop - + reserve->in_port->left_start + 1; + else if (reserve->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + width = reserve->in_port->right_stop - + reserve->in_port->right_start + 1; + + if (reserve->in_port->horizontal_bin || reserve->in_port->qcfa_bin) + width /= 2; + + if (!cam_ife_csid_ver2_is_width_valid_by_fuse(reserve, csid_hw, width)) { + CAM_ERR(CAM_ISP, "CSID[%u] width limited by fuse", + csid_hw->hw_intf->hw_idx); + return false; + } + + return true; +} + static int cam_ife_csid_ver2_in_port_validate( struct cam_csid_hw_reserve_resource_args *reserve, struct cam_ife_csid_ver2_hw *csid_hw) @@ -3376,6 +3437,9 @@ static int cam_ife_csid_ver2_in_port_validate( goto err; } + if (!cam_ife_csid_ver2_is_width_valid(reserve, csid_hw)) + goto err; + if (csid_hw->counters.csi2_reserve_cnt) { if (csid_hw->token != reserve->cb_priv) { @@ -3573,6 +3637,13 @@ int cam_ife_csid_ver2_release(void *hw_priv, path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv; + if (path_cfg->cid >= CAM_IFE_CSID_CID_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid cid:%d", + csid_hw->hw_intf->hw_idx, path_cfg->cid); + rc = -EINVAL; + goto end; + } + cam_ife_csid_cid_release(&csid_hw->cid_data[path_cfg->cid], csid_hw->hw_intf->hw_idx, path_cfg->cid); @@ -3813,7 +3884,8 @@ static int cam_ife_csid_ver2_init_config_rdi_path( res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0)) cam_ife_csid_ver2_res_master_slave_cfg(csid_hw, res->res_id); - if (1) { + if (csid_hw->debug_info.debug_val & + CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO) { val = cam_io_r_mb(mem_base + path_reg->format_measure_cfg0_addr); val |= cmn_reg->measure_en_hbi_vbi_cnt_mask; @@ -3986,7 +4058,8 @@ static int cam_ife_csid_ver2_init_config_pxl_path( cam_io_w_mb(val, mem_base + path_reg->err_recovery_cfg0_addr); } - if (1) { + if (csid_hw->debug_info.debug_val & + CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO) { val = cam_io_r_mb(mem_base + path_reg->format_measure_cfg0_addr); val |= csid_reg->cmn_reg->measure_en_hbi_vbi_cnt_mask; @@ -4095,7 +4168,8 @@ static int cam_ife_csid_ver2_path_irq_subscribe( struct cam_isp_resource_node *res, uint32_t irq_mask, uint32_t err_irq_mask) { - uint32_t top_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0}; + uint32_t num_register = 0; + uint32_t *top_irq_mask = NULL; struct cam_ife_csid_ver2_path_cfg *path_cfg = res->res_priv; struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg; int i, rc; @@ -4114,8 +4188,14 @@ static int cam_ife_csid_ver2_path_irq_subscribe( return -EINVAL; } - top_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] = - csid_reg->path_reg[res->res_id]->top_irq_mask[top_index]; + num_register = csid_reg->top_irq_reg_info[top_index].num_registers; + top_irq_mask = vmalloc(sizeof(uint32_t) * num_register); + if (!top_irq_mask) { + CAM_ERR(CAM_ISP, "csid top_irq_mask allocation failed"); + return -ENOMEM; + } + + top_irq_mask[0] = csid_reg->path_reg[res->res_id]->top_irq_mask[top_index]; if (csid_reg->path_reg[res->res_id]->capabilities & CAM_IFE_CSID_CAP_MULTI_CTXT) { rc = cam_ife_csid_ver2_mc_irq_subscribe(csid_hw, res, top_index); @@ -4182,7 +4262,7 @@ static int cam_ife_csid_ver2_path_irq_subscribe( rc = -EINVAL; goto unsub_path; } - + vfree(top_irq_mask); return 0; unsub_path: @@ -4201,6 +4281,7 @@ unsub_mc: csid_hw->top_mc_irq_handle); csid_hw->top_mc_irq_handle = 0; end: + vfree(top_irq_mask); return rc; } @@ -4643,7 +4724,8 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi uint32_t irq_mask, uint32_t err_irq_mask) { struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg; - uint32_t top_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0}; + uint32_t num_register = 0; + uint32_t *top_irq_mask = NULL; int top_index = -1; int i, rc; @@ -4661,8 +4743,14 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi return rc; } - top_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] = - csid_reg->csi2_reg->top_irq_mask[top_index]; + num_register = csid_reg->top_irq_reg_info[top_index].num_registers; + top_irq_mask = vmalloc(sizeof(uint32_t) * num_register); + if (!top_irq_mask) { + CAM_ERR(CAM_ISP, "csid top_irq_mask allocation failed"); + return -ENOMEM; + } + + top_irq_mask[0] = csid_reg->csi2_reg->top_irq_mask[top_index]; csid_hw->rx_cfg.top_irq_handle = cam_irq_controller_subscribe_irq( csid_hw->top_irq_controller[top_index], @@ -4726,7 +4814,7 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi rc = -EINVAL; goto unsub_rx; } - + vfree(top_irq_mask); return 0; unsub_rx: @@ -4743,6 +4831,7 @@ unsub_top: csid_hw->rx_cfg.top_irq_handle); csid_hw->rx_cfg.top_irq_handle = 0; err: + vfree(top_irq_mask); return rc; } @@ -5055,8 +5144,9 @@ static int cam_ife_csid_ver2_enable_hw( int i, rc; void __iomem *mem_base; const struct cam_ife_csid_ver2_path_reg_info *path_reg = NULL; + uint32_t num_register = 0; uint32_t top_err_irq_mask = 0; - uint32_t buf_done_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0}; + uint32_t *buf_done_irq_mask = NULL; uint32_t top_info_irq_mask = 0; if (csid_hw->flags.device_enabled) { @@ -5097,12 +5187,16 @@ static int cam_ife_csid_ver2_enable_hw( /* Read hw version */ val = cam_io_r_mb(mem_base + csid_reg->cmn_reg->hw_version_addr); - buf_done_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] = - csid_reg->cmn_reg->top_buf_done_irq_mask; + num_register = csid_reg->top_irq_reg_info[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0].num_registers; + buf_done_irq_mask = vmalloc(sizeof(uint32_t) * num_register); + if (!buf_done_irq_mask) { + CAM_ERR(CAM_ISP, "csid buf_done_irq_mask allocation failed"); + return -ENOMEM; + } + buf_done_irq_mask[0] = csid_reg->cmn_reg->top_buf_done_irq_mask; if (csid_reg->ipp_mc_reg) - buf_done_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] |= - csid_reg->ipp_mc_reg->comp_subgrp0_mask | + buf_done_irq_mask[0] |= csid_reg->ipp_mc_reg->comp_subgrp0_mask | csid_reg->ipp_mc_reg->comp_subgrp2_mask; csid_hw->buf_done_irq_handle = cam_irq_controller_subscribe_irq( @@ -5120,7 +5214,8 @@ static int cam_ife_csid_ver2_enable_hw( if (csid_hw->buf_done_irq_handle < 1) { CAM_ERR(CAM_ISP, "CSID[%u] buf done irq subscribe fail", csid_hw->hw_intf->hw_idx); - return -EINVAL; + rc = -EINVAL; + goto free_buf_done_mask; } top_err_irq_mask = csid_reg->cmn_reg->top_err_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]; @@ -5182,6 +5277,7 @@ static int cam_ife_csid_ver2_enable_hw( csid_hw->flags.fatal_err_detected = false; CAM_DBG(CAM_ISP, "CSID:%u CSID HW version: 0x%x", csid_hw->hw_intf->hw_idx, val); + vfree(buf_done_irq_mask); return 0; @@ -5196,6 +5292,8 @@ unsubscribe_buf_done: csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0], csid_hw->buf_done_irq_handle); csid_hw->buf_done_irq_handle = 0; +free_buf_done_mask: + vfree(buf_done_irq_mask); return rc; } @@ -5649,7 +5747,7 @@ int cam_ife_csid_ver2_start(void *hw_priv, void *args, } } - CAM_INFO(CAM_ISP, "CSID:%u RUP:0x%x AUP: 0x%x MUP:0x%x at start updated: %s", + CAM_DBG(CAM_ISP, "CSID:%u RUP:0x%x AUP: 0x%x MUP:0x%x at start updated: %s", csid_hw->hw_intf->hw_idx, rup_aup_mask.rup_mask, rup_aup_mask.aup_mask, rup_aup_mask.rup_aup_set_mask, CAM_BOOL_TO_YESNO(!start_args->is_internal_start)); @@ -5831,7 +5929,6 @@ int cam_ife_csid_ver2_stop(void *hw_priv, /* Issue a halt & reset to ensure there is no HW activity post the halt block */ reset.reset_type = CAM_IFE_CSID_RESET_PATH; - reset.power_on_reset = false; cam_ife_csid_ver2_reset(hw_priv, &reset, sizeof(struct cam_csid_reset_cfg_args)); @@ -6182,7 +6279,7 @@ static int cam_ife_csid_ver2_reg_update( if (rup_args->mup_en) { csid_hw->rx_cfg.mup = rup_args->mup_val; - CAM_INFO(CAM_ISP, "CSID[%u] MUP %u", + CAM_DBG(CAM_ISP, "CSID[%u] MUP %u", csid_hw->hw_intf->hw_idx, csid_hw->rx_cfg.mup); } @@ -6191,7 +6288,6 @@ static int cam_ife_csid_ver2_reg_update( else cam_ife_csid_ver2_get_sc_reg_val_pair(csid_hw, reg_val_pair, rup_args); - rup_args->value = reg_val_pair[1]; if (rup_args->reg_write) { for (i = 0; i < (2 * num_reg_val_pairs); i = i + 2) cam_io_w_mb(reg_val_pair[i + 1], csid_clc_membase + reg_val_pair[i]); @@ -6547,72 +6643,6 @@ static int cam_ife_csid_ver2_update_frame_stats( return 0; } -static int cam_ife_csid_ver2_dump_frame_stats( - struct cam_ife_csid_ver2_hw *csid_hw) -{ - int i, j; - uint32_t index, num_entries, oldest_entry, val0, val1; - struct cam_isp_resource_node *res; - const struct cam_ife_csid_ver2_reg_info *csid_reg; - const struct cam_ife_csid_ver2_path_reg_info *path_reg; - struct cam_ife_csid_ver2_path_cfg *path_cfg; - struct cam_hw_soc_info *soc_info; - struct cam_ife_csid_cid_data *cid_data; - int64_t state_head = 0; - - csid_reg = (struct cam_ife_csid_ver2_reg_info *) - csid_hw->core_info->csid_reg; - soc_info = &csid_hw->hw_info->soc_info; - for (i = 0; i < CAM_IFE_PIX_PATH_RES_MAX; i++) { - res = &csid_hw->path_res[i]; - if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) - continue; - - path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv; - cid_data = &csid_hw->cid_data[path_cfg->cid]; - path_reg = csid_reg->path_reg[res->res_id]; - state_head = atomic64_read(&path_cfg->frame_stats_cntr); - val0 = cam_io_r_mb(soc_info->reg_map[0].mem_base + - path_reg->format_measure1_addr); - val1 = cam_io_r_mb(soc_info->reg_map[0].mem_base + - path_reg->format_measure2_addr); - CAM_INFO(CAM_ISP, - "PATH: %s current hbi_min: %u hbi_max: %u vblank: %u", - res->res_name, (val0 & 0xFFF), ((val0 >> 0x10) & 0xFFF), val1); - CAM_INFO(CAM_ISP, "vc0: %u dt0: %u vc1: %u dt1: %u vc1_valid: %u", - cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].vc, - cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].dt, - cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].vc, - cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].dt, - cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid); - - if (state_head == -1) - continue; - - if (state_head < CAM_CSID_MAX_FRAME_STATS_CNTR) { - num_entries = state_head + 1; - oldest_entry = 0; - } else { - num_entries = CAM_CSID_MAX_FRAME_STATS_CNTR; - div_u64_rem(state_head + 1, CAM_CSID_MAX_FRAME_STATS_CNTR, - &oldest_entry); - } - - index = oldest_entry; - for (j = 0; j < num_entries; j++) { - CAM_INFO(CAM_ISP, - "PATH: %s Index: %u hbi_min: %u hbi_max: %u vblank: %u", - res->res_name, index, (path_cfg->frame_stats[index].hbi & 0xFFF), - ((path_cfg->frame_stats[index].hbi >> 0x10) & 0xFFF), - path_cfg->frame_stats[index].vbi); - - index = (index + 1) % CAM_CSID_MAX_FRAME_STATS_CNTR; - } - } - - return 0; -} - static int cam_ife_csid_ver2_set_dynamic_switch_config( struct cam_ife_csid_ver2_hw *csid_hw, void *cmd_args) @@ -6631,7 +6661,7 @@ static int cam_ife_csid_ver2_set_dynamic_switch_config( if (switch_update->mup_args.use_mup) { csid_hw->rx_cfg.mup = switch_update->mup_args.mup_val; - CAM_INFO(CAM_ISP, "CSID[%u] MUP %u", + CAM_DBG(CAM_ISP, "CSID[%u] MUP %u", csid_hw->hw_intf->hw_idx, csid_hw->rx_cfg.mup); } diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h index de3780a9c3..7211989379 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_IFE_CSID_HW_VER2_H_ @@ -752,6 +752,12 @@ struct cam_ife_csid_ver2_reg_info { const uint32_t num_path_err_irqs; const uint32_t num_top_regs; const uint32_t num_rx_regs; + const uint32_t fused_max_dualife_width[ + CAM_IFE_CSID_WIDTH_FUSE_VAL_MAX]; + const uint32_t fused_max_width[ + CAM_IFE_CSID_WIDTH_FUSE_VAL_MAX]; + const uint32_t width_fuse_max_val; + bool is_ife_sfe_mapped; }; /* diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite860.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite860.h new file mode 100644 index 0000000000..291211ec81 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite860.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_LITE_860_H_ +#define _CAM_IFE_CSID_LITE_860_H_ + +#include "cam_ife_csid_common.h" +#include "cam_ife_csid_dev.h" +#include "cam_ife_csid_hw_ver2.h" +#include "cam_irq_controller.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_ife_csid_lite880.h" + +static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_860_reg_info = { + .top_irq_reg_info = &cam_ife_csid_lite_880_top_irq_reg_info, + .rx_irq_reg_info = &cam_ife_csid_lite_880_rx_irq_reg_info, + .path_irq_reg_info = { + &cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0], + &cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1], + &cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2], + &cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3], + NULL, + &cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP], + }, + .buf_done_irq_reg_info = &cam_ife_csid_lite_880_buf_done_irq_reg_info, + .cmn_reg = &cam_ife_csid_lite_880_cmn_reg_info, + .csi2_reg = &cam_ife_csid_lite_880_csi2_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_IPP] = &cam_ife_csid_lite_880_ipp_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_PPP] = NULL, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_lite_880_rdi_0_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_1] = &cam_ife_csid_lite_880_rdi_1_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_lite_880_rdi_2_reg_info, + .path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_lite_880_rdi_3_reg_info, + .need_top_cfg = 0, + .top_irq_desc = &cam_ife_csid_lite_880_top_irq_desc, + .rx_irq_desc = &cam_ife_csid_lite_880_rx_irq_desc, + .path_irq_desc = cam_ife_csid_lite_880_path_irq_desc, + .num_top_err_irqs = cam_ife_csid_lite_880_num_top_irq_desc, + .num_rx_err_irqs = cam_ife_csid_lite_880_num_rx_irq_desc, + .num_path_err_irqs = ARRAY_SIZE(cam_ife_csid_lite_880_path_irq_desc), + .num_top_regs = 1, + .num_rx_regs = 1, + .is_ife_sfe_mapped = true, +}; + +#endif /* _CAM_IFE_CSID_LITE_860_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite880.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite880.h index 5540868ab3..2a9ba84876 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite880.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite880.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_IFE_CSID_LITE_880_H_ @@ -1067,5 +1067,6 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_880_reg_info = { .num_path_err_irqs = ARRAY_SIZE(cam_ife_csid_lite_880_path_irq_desc), .num_top_regs = 1, .num_rx_regs = 1, + .is_ife_sfe_mapped = true, }; #endif /* _CAM_IFE_CSID_LITE_780_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c index a3dd21c1ef..fbb1806ba2 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c @@ -13,6 +13,7 @@ #include "cam_ife_csid_lite480.h" #include "cam_ife_csid_lite680.h" #include "cam_ife_csid_lite780.h" +#include "cam_ife_csid_lite860.h" #include "cam_ife_csid_lite880.h" #define CAM_CSID_LITE_DRV_NAME "csid_lite" @@ -37,6 +38,11 @@ static struct cam_ife_csid_core_info cam_ife_csid_lite_780_hw_info = { .sw_version = CAM_IFE_CSID_VER_2_0, }; +static struct cam_ife_csid_core_info cam_ife_csid_lite_860_hw_info = { + .csid_reg = &cam_ife_csid_lite_860_reg_info, + .sw_version = CAM_IFE_CSID_VER_2_0, +}; + static struct cam_ife_csid_core_info cam_ife_csid_lite_880_hw_info = { .csid_reg = &cam_ife_csid_lite_880_reg_info, .sw_version = CAM_IFE_CSID_VER_2_0, @@ -79,6 +85,10 @@ static const struct of_device_id cam_ife_csid_lite_dt_match[] = { .compatible = "qcom,csid-lite780", .data = &cam_ife_csid_lite_780_hw_info, }, + { + .compatible = "qcom,csid-lite860", + .data = &cam_ife_csid_lite_860_hw_info, + }, { .compatible = "qcom,csid-lite880", .data = &cam_ife_csid_lite_880_hw_info, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c index fd167f225d..2d10d08cb8 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -20,6 +20,7 @@ #include "cam_ife_csid680.h" #include "cam_ife_csid680_110.h" #include "cam_ife_csid780.h" +#include "cam_ife_csid860.h" #include "cam_ife_csid880.h" #include "cam_ife_csid980.h" @@ -80,6 +81,11 @@ static struct cam_ife_csid_core_info cam_ife_csid780_hw_info = { .sw_version = CAM_IFE_CSID_VER_2_0, }; +static struct cam_ife_csid_core_info cam_ife_csid860_hw_info = { + .csid_reg = &cam_ife_csid_860_reg_info, + .sw_version = CAM_IFE_CSID_VER_2_0, +}; + static struct cam_ife_csid_core_info cam_ife_csid880_hw_info = { .csid_reg = &cam_ife_csid_880_reg_info, .sw_version = CAM_IFE_CSID_VER_2_0, @@ -136,6 +142,10 @@ static const struct of_device_id cam_ife_csid_dt_match[] = { .compatible = "qcom,csid780", .data = &cam_ife_csid780_hw_info, }, + { + .compatible = "qcom,csid860", + .data = &cam_ife_csid860_hw_info, + }, { .compatible = "qcom,csid880", .data = &cam_ife_csid880_hw_info, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h index f49e27fdc3..14308e95bd 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CSID_HW_INTF_H_ @@ -16,7 +16,6 @@ #define RT_BASE_IDX 2 #define CAM_ISP_MAX_PATHS 8 - /** * enum cam_ife_csid_hw_irq_regs - Specify the top irq reg */ @@ -109,6 +108,7 @@ enum cam_ife_csid_secondary_evt_type { * @rup_en: flag to indicate if rup is on csid side * @only_master_rup: flag to indicate if only master RUP * @camif_irq_support: flag to indicate if CSID supports CAMIF irq + * @is_ife_sfe_mapped: flag to indicate if IFE & SFE are one-one mapped */ struct cam_ife_csid_hw_caps { uint32_t num_rdis; @@ -123,6 +123,7 @@ struct cam_ife_csid_hw_caps { bool rup_en; bool only_master_rup; bool camif_irq_support; + bool is_ife_sfe_mapped; }; struct cam_isp_out_port_generic_info { @@ -482,7 +483,6 @@ struct cam_isp_csid_reg_update_args { bool reg_write; uint32_t mup_val; uint32_t mup_en; - uint32_t value; }; /* diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index b879a91762..76d7d589de 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -214,6 +214,7 @@ enum cam_isp_hw_cmd_type { CAM_ISP_HW_CMD_FE_TRIGGER_CMD, CAM_ISP_HW_CMD_UNMASK_BUS_WR_IRQ, CAM_ISP_HW_CMD_IS_CONSUMED_ADDR_SUPPORT, + CAM_ISP_HW_CMD_GET_LAST_CONSUMED_ADDR, CAM_ISP_HW_CMD_GET_RES_FOR_MID, CAM_ISP_HW_CMD_BLANKING_UPDATE, CAM_ISP_HW_CMD_CSID_CLOCK_DUMP, @@ -258,7 +259,10 @@ enum cam_isp_hw_cmd_type { #if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) CAM_IFE_CSID_SOF_IRQ_DEBUG_FOR_MODESWITCH, #endif - CAM_ISP_HW_CMD_GET_LAST_CONSUMED_ADDR, + CAM_ISP_HW_CMD_DYNAMIC_CLOCK_UPDATE, + CAM_ISP_HW_CMD_SET_SYNC_HW_IDX, + CAM_ISP_HW_CMD_BUS_WM_DISABLE, + CAM_ISP_HW_CMD_BUFFER_ALIGNMENT_UPDATE, CAM_IFE_CSID_CMD_GET_PATH_TIME_STAMP, CAM_ISP_HW_CMD_MAX, }; @@ -441,11 +445,13 @@ struct cam_isp_hw_get_wm_update { * @Brief: Get the out resource id for given mid * * @mid: Mid number of hw outport numb + * @pid: Pid number associated with mid * @out_res_id: Out resource id * */ struct cam_isp_hw_get_res_for_mid { uint32_t mid; + uint32_t pid; uint32_t out_res_id; }; @@ -518,6 +524,7 @@ struct cam_isp_hw_fcg_cmd { * @cmd: Command buffer information * @use_scratch_cfg: To indicate if it's scratch buffer config * @trigger_cdm_en: Flag to indicate if cdm is trigger + * @reg_write: if set use AHB to config rup/aup * */ struct cam_isp_hw_get_cmd_update { @@ -532,6 +539,7 @@ struct cam_isp_hw_get_cmd_update { struct cam_isp_hw_get_wm_update *rm_update; }; bool trigger_cdm_en; + bool reg_write; }; /* @@ -587,6 +595,20 @@ struct cam_isp_hw_dump_header { uint32_t word_size; }; +/** + * struct cam_isp_session_data - Session data + * + * @Brief: ISP session or usecase data + * + * @link_hdl: Link handle + * @is_shdr: Indicate is usecase is shdr + * + */ +struct cam_isp_session_data { + int32_t link_hdl; + bool is_shdr; +}; + /** * struct cam_isp_hw_intf_data - ISP hw intf data * diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h index 3952818899..b5ccbe8b08 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_TFE_CSID_HW_INTF_H_ @@ -12,7 +12,7 @@ #include "cam_tfe.h" /* MAX TFE CSID instance */ -#define CAM_TFE_CSID_HW_NUM_MAX 3 +#define CAM_TFE_CSID_HW_NUM_MAX 4 #define CAM_TFE_CSID_RDI_MAX 3 /** @@ -23,6 +23,7 @@ enum cam_tfe_csid_path_res_id { CAM_TFE_CSID_PATH_RES_RDI_1, CAM_TFE_CSID_PATH_RES_RDI_2, CAM_TFE_CSID_PATH_RES_IPP, + CAM_TFE_CSID_PATH_RES_PPP, CAM_TFE_CSID_PATH_RES_MAX, }; @@ -36,6 +37,7 @@ enum cam_tfe_csid_irq_reg { TFE_CSID_IRQ_REG_TOP, TFE_CSID_IRQ_REG_RX, TFE_CSID_IRQ_REG_IPP, + TFE_CSID_IRQ_REG_PPP, TFE_CSID_IRQ_REG_MAX, }; @@ -89,6 +91,9 @@ struct cam_isp_tfe_in_port_generic_info { uint32_t ipp_count; uint32_t rdi_count; uint32_t secure_mode; + bool shdr_en; + bool is_shdr_master; + bool epd_supported; struct cam_isp_tfe_out_port_generic_info *data; }; @@ -96,17 +101,23 @@ struct cam_isp_tfe_in_port_generic_info { * struct cam_tfe_csid_hw_caps- get the CSID hw capability * @num_rdis: number of rdis supported by CSID HW device * @num_pix: number of pxl paths supported by CSID HW device + * @num_ppp: number of ppp paths supported by CSID HW device * @major_version : major version * @minor_version: minor version * @version_incr: version increment + * @sync_clk: sync clocks such that freq(TFE)>freq(CSID)>freq(CSIPHY) + * @is_lite: Indicate if it is CSID Lite * */ struct cam_tfe_csid_hw_caps { uint32_t num_rdis; uint32_t num_pix; + uint32_t num_ppp; uint32_t major_version; uint32_t minor_version; uint32_t version_incr; + bool sync_clk; + bool is_lite; }; /** @@ -124,6 +135,7 @@ struct cam_tfe_csid_hw_caps { * @event_cb_prv: Context data * @event_cb: Callback function to hw mgr in case of hw events * @node_res : Reserved resource structure pointer + * @crop_enable : Flag to indicate CSID crop enable * */ struct cam_tfe_csid_hw_reserve_resource_args { @@ -137,6 +149,7 @@ struct cam_tfe_csid_hw_reserve_resource_args { void *event_cb_prv; cam_hw_mgr_event_cb_func event_cb; struct cam_isp_resource_node *node_res; + bool crop_enable; }; /** @@ -261,5 +274,15 @@ struct cam_tfe_csid_clock_update_args { uint64_t clk_rate; }; +/* + * struct cam_tfe_csid_discard_init_frame_args: + * + * @num_frames: Num frames to discard + * @res: Node res for this path + */ +struct cam_tfe_csid_discard_init_frame_args { + uint32_t num_frames; + struct cam_isp_resource_node *res; +}; #endif /* _CAM_TFE_CSID_HW_INTF_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h index b8fd2c1afd..9a6635d7ae 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_TFE_HW_INTF_H_ @@ -10,7 +10,7 @@ #include "cam_isp_hw.h" #include "cam_cpas_api.h" -#define CAM_TFE_HW_NUM_MAX 3 +#define CAM_TFE_HW_NUM_MAX 4 #define TFE_CORE_BASE_IDX 0 @@ -19,6 +19,7 @@ enum cam_isp_hw_tfe_in { CAM_ISP_HW_TFE_IN_RDI0 = 1, CAM_ISP_HW_TFE_IN_RDI1 = 2, CAM_ISP_HW_TFE_IN_RDI2 = 3, + CAM_ISP_HW_TFE_IN_PDLIB = 4, CAM_ISP_HW_TFE_IN_MAX, }; @@ -35,6 +36,7 @@ enum cam_tfe_hw_irq_status { CAM_TFE_IRQ_STATUS_OVERFLOW, CAM_TFE_IRQ_STATUS_P2I_ERROR, CAM_TFE_IRQ_STATUS_VIOLATION, + CAM_TFE_IRQ_STATUS_OUT_OF_SYNC, CAM_TFE_IRQ_STATUS_MAX, }; @@ -120,6 +122,7 @@ struct cam_tfe_hw_tfe_out_acquire_args { * @in_port: Input port details to acquire * @camif_pd_enable Camif pd enable or disable * @dual_tfe_sync_sel_idx Dual tfe master hardware index + * @lcr_enable LCR enable field */ struct cam_tfe_hw_tfe_in_acquire_args { struct cam_isp_resource_node *rsrc_node; @@ -129,6 +132,7 @@ struct cam_tfe_hw_tfe_in_acquire_args { enum cam_isp_hw_sync_mode sync_mode; bool camif_pd_enable; uint32_t dual_tfe_sync_sel_idx; + bool lcr_enable; }; /* @@ -244,6 +248,24 @@ struct cam_tfe_irq_evt_payload { uint32_t last_consumed_addr; }; +/* + * cam_tfe_get_num_tfe_hws() + * + * @brief: Gets number of TFEs + * + * @num_tfes: Fills number of TFES in the address passed + */ +void cam_tfe_get_num_tfe_hws(uint32_t *num_tfes); + +/* + * cam_tfe_get_num_tfe_lite_hws() + * + * @brief: Gets number of TFE-LITEs + * + * @num_tfe_lites: Fills number of TFE-LITEs in the address passed + */ +void cam_tfe_get_num_tfe_lite_hws(uint32_t *num_tfe_lites); + /* * cam_tfe_hw_init() * diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c index d1fb5b7dd6..99a17b9957 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -108,6 +109,12 @@ static void cam_ppi_component_unbind(struct device *dev, struct platform_device *pdev = to_platform_device(dev); ppi_dev = (struct cam_csid_ppi_hw *)platform_get_drvdata(pdev); + + if (!ppi_dev) { + CAM_ERR(CAM_ISP, "Error No data in ppi_dev"); + return; + } + ppi_hw_intf = ppi_dev->hw_intf; ppi_hw_info = ppi_dev->hw_info; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe860.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe860.h new file mode 100644 index 0000000000..fe22704860 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe860.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_SFE860_H_ +#define _CAM_SFE860_H_ +#include "cam_sfe_core.h" +#include "cam_sfe_bus.h" +#include "cam_sfe_bus_rd.h" +#include "cam_sfe_bus_wr.h" +#include "cam_sfe880.h" + +static struct cam_sfe_top_common_reg_offset sfe860_top_commong_reg = { + .hw_version = 0x00000000, + .hw_capability = 0x00000004, + .stats_feature = 0x00000008, + .core_cgc_ctrl = 0x00000010, + .ahb_clk_ovd = 0x00000014, + .core_cfg = 0x000000CC, + .ipp_violation_status = 0x00000030, + .diag_config = 0x00000034, + .diag_sensor_status_0 = 0x00000038, + .diag_sensor_status_1 = 0x0000003C, + .diag_sensor_frame_cnt_status0 = 0x00000040, + .diag_sensor_frame_cnt_status1 = 0x00000044, + .stats_ch2_throttle_cfg = 0x000000B0, + .stats_ch1_throttle_cfg = 0x000000B4, + .stats_ch0_throttle_cfg = 0x000000B8, + .hdr_throttle_cfg = 0x000000C0, + .sfe_op_throttle_cfg = 0x000000C4, + .irc_throttle_cfg = 0x000000C8, + .sfe_single_dual_cfg = 0x000000D0, + .bus_overflow_status = 0x00000868, + .num_perf_counters = 2, + .perf_count_reg = { + { + .perf_count_cfg = 0x00000080, + .perf_pix_count = 0x00000084, + .perf_line_count = 0x00000088, + .perf_stall_count = 0x0000008C, + .perf_always_count = 0x00000090, + .perf_count_status = 0x00000094, + }, + { + .perf_count_cfg = 0x00000098, + .perf_pix_count = 0x0000009C, + .perf_line_count = 0x000000A0, + .perf_stall_count = 0x000000A4, + .perf_always_count = 0x000000A8, + .perf_count_status = 0x000000AC, + }, + }, + .top_debug_cfg = 0x0000007C, + .top_cc_test_bus_ctrl = 0x000001F0, + .lcr_supported = false, + .ir_supported = true, + .qcfa_only = false, + .num_sfe_mode = ARRAY_SIZE(sfe_880_mode), + .sfe_mode = sfe_880_mode, + .ipp_violation_mask = 0x4000, + .top_debug_testbus_reg = 13, + .top_debug_nonccif_regstart_idx = 12, + .top_cc_test_bus_supported = true, + .num_debug_registers = 20, + .top_debug = { + 0x0000004C, + 0x00000050, + 0x00000054, + 0x00000058, + 0x0000005C, + 0x00000060, + 0x00000064, + 0x00000068, + 0x0000006C, + 0x00000070, + 0x00000074, + 0x00000078, + 0x000000EC, + 0x000000F0, + 0x000000F4, + 0x000000F8, + 0x000000FC, + 0x00000100, + 0x00000104, + 0x00000108, + }, +}; + +static struct cam_sfe_top_hw_info sfe860_top_hw_info = { + .common_reg = &sfe860_top_commong_reg, + .modules_hw_info = &sfe880_modules_common_reg, + .common_reg_data = &sfe_880_top_common_reg_data, + .ipp_module_desc = sfe_880_mod_desc, + .wr_client_desc = sfe_880_wr_client_desc, + .pix_reg_data = &sfe_880_pix_reg_data, + .rdi_reg_data[0] = &sfe_880_rdi0_reg_data, + .rdi_reg_data[1] = &sfe_880_rdi1_reg_data, + .rdi_reg_data[2] = &sfe_880_rdi2_reg_data, + .rdi_reg_data[3] = &sfe_880_rdi3_reg_data, + .rdi_reg_data[4] = &sfe_880_rdi4_reg_data, + .num_inputs = 6, + .input_type = { + CAM_SFE_PIX_VER_1_0, + CAM_SFE_RDI_VER_1_0, + CAM_SFE_RDI_VER_1_0, + CAM_SFE_RDI_VER_1_0, + CAM_SFE_RDI_VER_1_0, + CAM_SFE_RDI_VER_1_0, + }, + .num_top_errors = ARRAY_SIZE(sfe_880_top_irq_err_desc), + .top_err_desc = sfe_880_top_irq_err_desc, + .num_clc_module = 12, + .clc_dbg_mod_info = &sfe880_clc_dbg_module_info, + .num_of_testbus = 2, + .test_bus_info = { + /* TEST BUS 1 INFO */ + { + .debugfs_val = SFE_DEBUG_ENABLE_TESTBUS1, + .enable = false, + .value = 0x1, + .size = ARRAY_SIZE(sfe880_testbus1_info), + .testbus = sfe880_testbus1_info, + }, + /* TEST BUS 2 INFO */ + { + .debugfs_val = SFE_DEBUG_ENABLE_TESTBUS2, + .enable = false, + .value = 0x3, + .size = ARRAY_SIZE(sfe880_testbus2_info), + .testbus = sfe880_testbus2_info, + }, + }, +}; + +struct cam_sfe_hw_info cam_sfe860_hw_info = { + .irq_reg_info = &sfe880_top_irq_reg_info, + + .bus_wr_version = CAM_SFE_BUS_WR_VER_1_0, + .bus_wr_hw_info = &sfe880_bus_wr_hw_info, + + .bus_rd_version = CAM_SFE_BUS_RD_VER_1_0, + .bus_rd_hw_info = &sfe880_bus_rd_hw_info, + + .top_version = CAM_SFE_TOP_VER_1_0, + .top_hw_info = &sfe860_top_hw_info, +}; + +#endif /* _CAM_SFE860_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c index 645e73cdec..0da2706500 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -14,6 +14,7 @@ #include "cam_sfe_soc.h" #include "cam_sfe680.h" #include "cam_sfe780.h" +#include "cam_sfe860.h" #include "cam_sfe880.h" #include "cam_debug_util.h" #include "camera_main.h" @@ -261,6 +262,10 @@ static const struct of_device_id cam_sfe_dt_match[] = { .compatible = "qcom,sfe780", .data = &cam_sfe780_hw_info, }, + { + .compatible = "qcom,sfe860", + .data = &cam_sfe860_hw_info, + }, { .compatible = "qcom,sfe880", .data = &cam_sfe880_hw_info, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c index c2dda97d3a..3bd0248551 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c @@ -780,6 +780,11 @@ static int cam_sfe_top_get_base( mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( top_priv->common_data.soc_info, SFE_CORE_BASE_IDX); + if (mem_base == -1) { + CAM_ERR(CAM_SFE, "failed to get mem_base, index: %d num_reg_map: %u", + SFE_CORE_BASE_IDX, top_priv->common_data.soc_info->num_reg_map); + return -EINVAL; + } if (cdm_args->cdm_id == CAM_CDM_RT) { if (!soc_private->rt_wrapper_base) { @@ -1190,6 +1195,7 @@ static int cam_sfe_top_apply_fcg_update( } fcg_index_shift = fcg_module_info->fcg_index_shift; + for (i = 0, j = 0; i < fcg_config->num_ch_ctx; i++) { if (j >= fcg_module_info->max_reg_val_pair_size) { CAM_ERR(CAM_SFE, "reg_val_pair %d exceeds the array limit %u", @@ -1836,7 +1842,7 @@ static int cam_sfe_top_handle_irq_bottom_half( void *handler_priv, void *evt_payload_priv) { int i; - uint32_t val0, val1, frame_cnt = 0, offset0, offset1; + uint32_t val0, val1, frame_cnt, offset0, offset1; uint32_t irq_status[CAM_SFE_IRQ_REGISTERS_MAX] = {0}; enum cam_sfe_hw_irq_status ret = CAM_SFE_IRQ_STATUS_MAX; struct cam_isp_resource_node *res = handler_priv; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid.c index 61c9e60acd..ca02633e09 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -8,6 +9,9 @@ #include "cam_tfe_csid_core.h" #include "cam_tfe_csid530.h" #include "cam_tfe_csid640.h" +#include "cam_tfe_csid640_210.h" +#include "cam_tfe_csid770.h" +#include "cam_tfe_csid665.h" #include "cam_tfe_csid_dev.h" #include "camera_main.h" @@ -22,6 +26,22 @@ static const struct of_device_id cam_tfe_csid_dt_match[] = { .compatible = "qcom,csid640", .data = &cam_tfe_csid640_hw_info, }, + { + .compatible = "qcom,csid640_210", + .data = &cam_tfe_csid640_210_hw_info, + }, + { + .compatible = "qcom,csid770", + .data = &cam_tfe_csid770_hw_info, + }, + { + .compatible = "qcom,csid-lite770", + .data = &cam_tfe_csid770_hw_info, + }, + { + .compatible = "qcom,csid665", + .data = &cam_tfe_csid665_hw_info, + }, {} }; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h index 5faa1f7314..89bd203746 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_TFE_CSID_530_H_ @@ -178,6 +179,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset .csi2_rx_long_pkt_hdr_rst_stb_shift = 0x1, .csi2_rx_short_pkt_hdr_rst_stb_shift = 0x2, .csi2_rx_cphy_pkt_hdr_rst_stb_shift = 0x3, + .need_to_sel_tpg_mux = false, }; static struct cam_tfe_csid_common_reg_offset diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640.h index a647bd596c..582a998417 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_TFE_CSID_640_H_ @@ -199,7 +200,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset .csid_csi2_rx_stats_ecc_addr = 0x164, .csid_csi2_rx_total_crc_err_addr = 0x168, - .phy_tpg_base_id = 0, + .phy_tpg_base_id = 1, .csi2_rst_srb_all = 0x3FFF, .csi2_rst_done_shift_val = 27, .csi2_irq_mask_all = 0xFFFFFFF, @@ -216,6 +217,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset .csi2_rx_long_pkt_hdr_rst_stb_shift = 0x1, .csi2_rx_short_pkt_hdr_rst_stb_shift = 0x2, .csi2_rx_cphy_pkt_hdr_rst_stb_shift = 0x3, + .need_to_sel_tpg_mux = true, }; static struct cam_tfe_csid_common_reg_offset @@ -264,6 +266,7 @@ static struct cam_tfe_csid_common_reg_offset .format_measure_height_shift_val = 16, .format_measure_height_mask_val = 0xe, .format_measure_width_mask_val = 0x10, + .sync_clk = true, }; static struct cam_tfe_csid_reg_offset cam_tfe_csid_640_reg_offset = { diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h new file mode 100644 index 0000000000..0dd72fd1dc --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_640_210_H_ +#define _CAM_TFE_CSID_640_210_H_ + +#include "cam_tfe_csid_core.h" +#include "cam_tfe_csid640.h" + +#define CAM_TFE_CSID_VERSION_V640_210 0x60040000 + +static struct cam_tfe_csid_hw_info cam_tfe_csid640_210_hw_info = { + .csid_reg = &cam_tfe_csid_640_reg_offset, + .hw_dts_version = CAM_TFE_CSID_VERSION_V640_210, +}; + +#endif /*_CAM_TFE_CSID_640_210_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid665.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid665.h new file mode 100644 index 0000000000..b39d26ee3f --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid665.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_665_H_ +#define _CAM_TFE_CSID_665_H_ + +#include "cam_tfe_csid_core.h" + +#define CAM_TFE_CSID_VERSION_V665 0x70065000 + +static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_665_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_frame_drop_pattern = 0x20c, + .csid_pxl_frame_drop_period = 0x210, + .csid_pxl_irq_subsample_pattern = 0x214, + .csid_pxl_irq_subsample_period = 0x218, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_format_measure_cfg0_addr = 0x270, + .csid_pxl_format_measure_cfg1_addr = 0x274, + .csid_pxl_format_measure0_addr = 0x278, + .csid_pxl_format_measure1_addr = 0x27c, + .csid_pxl_format_measure2_addr = 0x280, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + .csid_pxl_err_recovery_cfg0_addr = 0x2d0, + .csid_pxl_err_recovery_cfg1_addr = 0x2d4, + .csid_pxl_err_recovery_cfg2_addr = 0x2d8, + .csid_pxl_multi_vcdt_cfg0_addr = 0x2dc, + + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .halt_master_sel_shift = 4, + .halt_mode_shift = 2, + .halt_mode_mask = 3, + .halt_master_sel_master_val = 1, + .halt_master_sel_slave_val = 0, + .binning_supported = 3, + .bin_qcfa_en_shift_val = 30, + .bin_en_shift_val = 2, + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 9, +}; + +static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_665_ppp_reg_offset = { + .csid_pxl_irq_status_addr = 0xA0, + .csid_pxl_irq_mask_addr = 0xA4, + .csid_pxl_irq_clear_addr = 0xA8, + .csid_pxl_irq_set_addr = 0xAc, + + .csid_pxl_cfg0_addr = 0x700, + .csid_pxl_cfg1_addr = 0x704, + .csid_pxl_ctrl_addr = 0x708, + .csid_pxl_frame_drop_pattern = 0x70c, + .csid_pxl_frame_drop_period = 0x710, + .csid_pxl_irq_subsample_pattern = 0x714, + .csid_pxl_irq_subsample_period = 0x718, + .csid_pxl_hcrop_addr = 0x71c, + .csid_pxl_vcrop_addr = 0x720, + .csid_pxl_rst_strobes_addr = 0x740, + .csid_pxl_status_addr = 0x754, + .csid_pxl_misr_val_addr = 0x758, + .csid_pxl_format_measure_cfg0_addr = 0x770, + .csid_pxl_format_measure_cfg1_addr = 0x774, + .csid_pxl_format_measure0_addr = 0x778, + .csid_pxl_format_measure1_addr = 0x77c, + .csid_pxl_format_measure2_addr = 0x780, + .csid_pxl_timestamp_curr0_sof_addr = 0x790, + .csid_pxl_timestamp_curr1_sof_addr = 0x794, + .csid_pxl_timestamp_perv0_sof_addr = 0x798, + .csid_pxl_timestamp_perv1_sof_addr = 0x79c, + .csid_pxl_timestamp_curr0_eof_addr = 0x7a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x7a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x7a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x7ac, + .csid_pxl_ppp_sparse_pd_ext_cfg0 = 0x7c0, + .csid_pxl_err_recovery_cfg0_addr = 0x7d0, + .csid_pxl_err_recovery_cfg1_addr = 0x7d4, + .csid_pxl_err_recovery_cfg2_addr = 0x7d8, + .csid_pxl_multi_vcdt_cfg0_addr = 0x7dc, + + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .halt_master_sel_shift = 4, + .halt_mode_shift = 2, + .halt_mode_mask = 3, + .halt_master_sel_master_val = 3, + .halt_master_sel_slave_val = 2, + .binning_supported = 0, + .bin_qcfa_en_shift_val = 30, + .bin_en_shift_val = 2, + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 9, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_665_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frame_drop_pattern = 0x30c, + .csid_rdi_frame_drop_period = 0x310, + .csid_rdi_irq_subsample_pattern = 0x314, + .csid_rdi_irq_subsample_period = 0x318, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_err_recovery_cfg0_addr = 0x3b0, + .csid_rdi_err_recovery_cfg1_addr = 0x3b4, + .csid_rdi_err_recovery_cfg2_addr = 0x3b8, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, + .csid_rdi_multi_vcdt_cfg0_addr = 0x3bc, + + /* configurations */ + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 8, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_665_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frame_drop_pattern = 0x40c, + .csid_rdi_frame_drop_period = 0x410, + .csid_rdi_irq_subsample_pattern = 0x414, + .csid_rdi_irq_subsample_period = 0x418, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_err_recovery_cfg0_addr = 0x4b0, + .csid_rdi_err_recovery_cfg1_addr = 0x4b4, + .csid_rdi_err_recovery_cfg2_addr = 0x4b8, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, + .csid_rdi_multi_vcdt_cfg0_addr = 0x4bc, + + /* configurations */ + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 8, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_665_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frame_drop_pattern = 0x50c, + .csid_rdi_frame_drop_period = 0x510, + .csid_rdi_irq_subsample_pattern = 0x514, + .csid_rdi_irq_subsample_period = 0x518, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_err_recovery_cfg0_addr = 0x5b0, + .csid_rdi_err_recovery_cfg1_addr = 0x5b4, + .csid_rdi_err_recovery_cfg2_addr = 0x5b8, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, + .csid_rdi_multi_vcdt_cfg0_addr = 0x5bc, + + /* configurations */ + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 8, +}; + +static struct cam_tfe_csid_csi2_rx_reg_offset + cam_tfe_csid_665_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .phy_sel_base = 1, + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .phy_tpg_base_id = 3, + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 12, + .csi2_capture_cphy_pkt_dt_shift = 14, + .csi2_capture_cphy_pkt_vc_shift = 20, + .csi2_rx_phy_num_mask = 0x7, + .csi2_rx_long_pkt_hdr_rst_stb_shift = 0x1, + .csi2_rx_short_pkt_hdr_rst_stb_shift = 0x2, + .csi2_rx_cphy_pkt_hdr_rst_stb_shift = 0x3, + .need_to_sel_tpg_mux = true, +}; + +static struct cam_tfe_csid_common_reg_offset + cam_tfe_csid_665_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 5, + .minor_version = 3, + .version_incr = 0, + .num_rdis = 3, + .num_pix = 1, + .num_ppp = 1, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .ipp_path_rst_stb_all = 0x17, + .ppp_path_rst_stb_all = 0x17, + .rdi_path_rst_stb_all = 0x97, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .vc1_shift_val = 2, + .dt1_shift_val = 7, + .multi_vc_dt_en_shift_val = 0, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0x3FFFF, + .ppp_irq_mask_all = 0x3FFFF, + .rdi_irq_mask_all = 0x3FFFF, + .top_tfe2_pix_pipe_fuse_reg = 0xFE4, + .top_tfe2_fuse_reg = 0xFE8, + .format_measure_support = true, + .format_measure_height_shift_val = 16, + .format_measure_height_mask_val = 0xFFFF, + .format_measure_width_mask_val = 0xFFFF, + .sync_clk = true, +}; + +static struct cam_tfe_csid_reg_offset cam_tfe_csid_665_reg_offset = { + .cmn_reg = &cam_tfe_csid_665_cmn_reg_offset, + .csi2_reg = &cam_tfe_csid_665_csi2_reg_offset, + .ipp_reg = &cam_tfe_csid_665_ipp_reg_offset, + .ppp_reg = &cam_tfe_csid_665_ppp_reg_offset, + .rdi_reg = { + &cam_tfe_csid_665_rdi_0_reg_offset, + &cam_tfe_csid_665_rdi_1_reg_offset, + &cam_tfe_csid_665_rdi_2_reg_offset, + }, +}; + +static struct cam_tfe_csid_hw_info cam_tfe_csid665_hw_info = { + .csid_reg = &cam_tfe_csid_665_reg_offset, + .hw_dts_version = CAM_TFE_CSID_VERSION_V665, +}; + +#endif /*_CAM_TFE_CSID_665_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid770.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid770.h new file mode 100644 index 0000000000..6f18f38b79 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid770.h @@ -0,0 +1,374 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_770_H_ +#define _CAM_TFE_CSID_770_H_ + +#include "cam_tfe_csid_core.h" + +#define CAM_TFE_CSID_VERSION_V770 0x70070000 + +static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_770_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_frame_drop_pattern = 0x20c, + .csid_pxl_frame_drop_period = 0x210, + .csid_pxl_irq_subsample_pattern = 0x214, + .csid_pxl_irq_subsample_period = 0x218, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_format_measure_cfg0_addr = 0x270, + .csid_pxl_format_measure_cfg1_addr = 0x274, + .csid_pxl_format_measure0_addr = 0x278, + .csid_pxl_format_measure1_addr = 0x27c, + .csid_pxl_format_measure2_addr = 0x280, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + .csid_pxl_err_recovery_cfg0_addr = 0x2d0, + .csid_pxl_err_recovery_cfg1_addr = 0x2d4, + .csid_pxl_err_recovery_cfg2_addr = 0x2d8, + .csid_pxl_multi_vcdt_cfg0_addr = 0x2dc, + + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .halt_master_sel_shift = 4, + .halt_mode_shift = 2, + .halt_mode_mask = 3, + .halt_master_sel_master_val = 1, + .halt_master_sel_slave_val = 0, + .binning_supported = 3, + .bin_qcfa_en_shift_val = 30, + .bin_en_shift_val = 2, + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 9, +}; + +static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_770_ppp_reg_offset = { + .csid_pxl_irq_status_addr = 0xA0, + .csid_pxl_irq_mask_addr = 0xA4, + .csid_pxl_irq_clear_addr = 0xA8, + .csid_pxl_irq_set_addr = 0xAc, + + .csid_pxl_cfg0_addr = 0x700, + .csid_pxl_cfg1_addr = 0x704, + .csid_pxl_ctrl_addr = 0x708, + .csid_pxl_frame_drop_pattern = 0x70c, + .csid_pxl_frame_drop_period = 0x710, + .csid_pxl_irq_subsample_pattern = 0x714, + .csid_pxl_irq_subsample_period = 0x718, + .csid_pxl_hcrop_addr = 0x71c, + .csid_pxl_vcrop_addr = 0x720, + .csid_pxl_rst_strobes_addr = 0x740, + .csid_pxl_status_addr = 0x754, + .csid_pxl_misr_val_addr = 0x758, + .csid_pxl_format_measure_cfg0_addr = 0x770, + .csid_pxl_format_measure_cfg1_addr = 0x774, + .csid_pxl_format_measure0_addr = 0x778, + .csid_pxl_format_measure1_addr = 0x77c, + .csid_pxl_format_measure2_addr = 0x780, + .csid_pxl_timestamp_curr0_sof_addr = 0x790, + .csid_pxl_timestamp_curr1_sof_addr = 0x794, + .csid_pxl_timestamp_perv0_sof_addr = 0x798, + .csid_pxl_timestamp_perv1_sof_addr = 0x79c, + .csid_pxl_timestamp_curr0_eof_addr = 0x7a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x7a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x7a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x7ac, + .csid_pxl_ppp_sparse_pd_ext_cfg0 = 0x7c0, + .csid_pxl_err_recovery_cfg0_addr = 0x7d0, + .csid_pxl_err_recovery_cfg1_addr = 0x7d4, + .csid_pxl_err_recovery_cfg2_addr = 0x7d8, + .csid_pxl_multi_vcdt_cfg0_addr = 0x7dc, + + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .halt_master_sel_shift = 4, + .halt_mode_shift = 2, + .halt_mode_mask = 3, + .halt_master_sel_master_val = 3, + .halt_master_sel_slave_val = 2, + .binning_supported = 0, + .bin_qcfa_en_shift_val = 30, + .bin_en_shift_val = 2, + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 9, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_770_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frame_drop_pattern = 0x30c, + .csid_rdi_frame_drop_period = 0x310, + .csid_rdi_irq_subsample_pattern = 0x314, + .csid_rdi_irq_subsample_period = 0x318, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_err_recovery_cfg0_addr = 0x3b0, + .csid_rdi_err_recovery_cfg1_addr = 0x3b4, + .csid_rdi_err_recovery_cfg2_addr = 0x3b8, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, + .csid_rdi_multi_vcdt_cfg0_addr = 0x3bc, + + /* configurations */ + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 8, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_770_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frame_drop_pattern = 0x40c, + .csid_rdi_frame_drop_period = 0x410, + .csid_rdi_irq_subsample_pattern = 0x414, + .csid_rdi_irq_subsample_period = 0x418, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_err_recovery_cfg0_addr = 0x4b0, + .csid_rdi_err_recovery_cfg1_addr = 0x4b4, + .csid_rdi_err_recovery_cfg2_addr = 0x4b8, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, + .csid_rdi_multi_vcdt_cfg0_addr = 0x4bc, + + /* configurations */ + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 8, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_770_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frame_drop_pattern = 0x50c, + .csid_rdi_frame_drop_period = 0x510, + .csid_rdi_irq_subsample_pattern = 0x514, + .csid_rdi_irq_subsample_period = 0x518, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_err_recovery_cfg0_addr = 0x5b0, + .csid_rdi_err_recovery_cfg1_addr = 0x5b4, + .csid_rdi_err_recovery_cfg2_addr = 0x5b8, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, + .csid_rdi_multi_vcdt_cfg0_addr = 0x5bc, + + /* configurations */ + .is_multi_vc_dt_supported = true, + .format_measure_en_shift_val = 0, + .measure_en_hbi_vbi_cnt_val = 0xc, + .cgc_mode_en_shift_val = 8, +}; + +static struct cam_tfe_csid_csi2_rx_reg_offset + cam_tfe_csid_770_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .phy_sel_base = 1, + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .phy_tpg_base_id = 3, + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_rx_epd_mode_shift_en = 8, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 12, + .csi2_capture_cphy_pkt_dt_shift = 14, + .csi2_capture_cphy_pkt_vc_shift = 20, + .csi2_rx_phy_num_mask = 0x7, + .csi2_rx_long_pkt_hdr_rst_stb_shift = 0x1, + .csi2_rx_short_pkt_hdr_rst_stb_shift = 0x2, + .csi2_rx_cphy_pkt_hdr_rst_stb_shift = 0x3, + .need_to_sel_tpg_mux = true, +}; + +static struct cam_tfe_csid_common_reg_offset + cam_tfe_csid_770_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 5, + .minor_version = 3, + .version_incr = 0, + .num_rdis = 3, + .num_pix = 1, + .num_ppp = 1, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .ipp_path_rst_stb_all = 0x17, + .ppp_path_rst_stb_all = 0x17, + .rdi_path_rst_stb_all = 0x97, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .vc1_shift_val = 2, + .dt1_shift_val = 7, + .multi_vc_dt_en_shift_val = 0, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0x3FFFF, + .ppp_irq_mask_all = 0x3FFFF, + .rdi_irq_mask_all = 0x3FFFF, + .top_tfe2_pix_pipe_fuse_reg = 0xFE4, + .top_tfe2_fuse_reg = 0xFE8, + .format_measure_support = true, + .format_measure_height_shift_val = 16, + .format_measure_height_mask_val = 0xFFFF, + .format_measure_width_mask_val = 0xFFFF, + .sync_clk = true, +}; + +static struct cam_tfe_csid_reg_offset cam_tfe_csid_770_reg_offset = { + .cmn_reg = &cam_tfe_csid_770_cmn_reg_offset, + .csi2_reg = &cam_tfe_csid_770_csi2_reg_offset, + .ipp_reg = &cam_tfe_csid_770_ipp_reg_offset, + .ppp_reg = &cam_tfe_csid_770_ppp_reg_offset, + .rdi_reg = { + &cam_tfe_csid_770_rdi_0_reg_offset, + &cam_tfe_csid_770_rdi_1_reg_offset, + &cam_tfe_csid_770_rdi_2_reg_offset, + }, +}; + +static struct cam_tfe_csid_hw_info cam_tfe_csid770_hw_info = { + .csid_reg = &cam_tfe_csid_770_reg_offset, + .hw_dts_version = CAM_TFE_CSID_VERSION_V770, +}; + +#endif /*_CAM_TFE_CSID_770_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index e045465ef0..4e6bcef39c 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -23,6 +23,7 @@ #include "cam_common_util.h" #include "cam_tfe_csid_hw_intf.h" #include +#include "cam_cpas_hw_intf.h" /* Timeout value in msec */ #define TFE_CSID_TIMEOUT 1000 @@ -46,7 +47,7 @@ /* Max CSI Rx irq error count threshold value */ #define CAM_TFE_CSID_MAX_IRQ_ERROR_COUNT 5 -static int cam_tfe_csid_is_ipp_format_supported( +static int cam_tfe_csid_is_ipp_ppp_format_supported( uint32_t in_format) { int rc = -EINVAL; @@ -169,7 +170,7 @@ static int cam_tfe_csid_get_format_rdi( return rc; } -static int cam_tfe_csid_get_format_ipp( +static int cam_tfe_csid_get_format_ipp_ppp( uint32_t in_format, uint32_t *decode_fmt, uint32_t *plain_fmt) { @@ -250,6 +251,9 @@ static void cam_tfe_csid_enable_path_for_init_frame_drop( if (res_id == CAM_TFE_CSID_PATH_RES_IPP) { res = &csid_hw->ipp_res; pxl_reg = csid_reg->ipp_reg; + } else if (res_id == CAM_TFE_CSID_PATH_RES_PPP) { + res = &csid_hw->ppp_res; + pxl_reg = csid_reg->ppp_reg; } else if (res_id >= CAM_TFE_CSID_PATH_RES_RDI_0 && res_id <= CAM_TFE_CSID_PATH_RES_RDI_2) { res = &csid_hw->rdi_res[res_id]; @@ -281,8 +285,9 @@ static void cam_tfe_csid_enable_path_for_init_frame_drop( if ((path_data->res_sof_cnt == path_data->init_frame_drop) && pxl_reg) { - CAM_DBG(CAM_ISP, "CSID:%d Enabling pixel IPP Path", - csid_hw->hw_intf->hw_idx); + CAM_DBG(CAM_ISP, "CSID:%d Enabling pixel %s Path", + csid_hw->hw_intf->hw_idx, + (res_id == CAM_TFE_CSID_PATH_RES_IPP) ? "IPP" : "PPP"); if (path_data->sync_mode != CAM_ISP_HW_SYNC_SLAVE) { val = cam_io_r_mb(soc_info->reg_map[0].mem_base + @@ -340,6 +345,17 @@ static bool cam_tfe_csid_check_path_active(struct cam_tfe_csid_hw *csid_hw) goto end; } + /* check the PPP path status */ + if (csid_reg->cmn_reg->num_ppp) { + path_status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_status_addr); + CAM_DBG(CAM_ISP, "CSID:%d PPP path status:%d", + csid_hw->hw_intf->hw_idx, path_status); + /* if status is 0 then it is active */ + if (!path_status) + goto end; + } + /* Check the RDI path status */ for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { path_status = cam_io_r_mb(soc_info->reg_map[0].mem_base + @@ -460,6 +476,10 @@ static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); @@ -477,6 +497,11 @@ static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(csid_reg->cmn_reg->ppp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_clear_addr); + for (i = 0 ; i < csid_reg->cmn_reg->num_rdis; i++) cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, soc_info->reg_map[0].mem_base + @@ -525,7 +550,6 @@ static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) } else rc = 0; - usleep_range(3000, 3010); val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); if (val != 0) @@ -540,6 +564,12 @@ static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) path_data->res_sof_cnt = 0; } + if (csid_reg->cmn_reg->num_ppp) { + path_data = (struct cam_tfe_csid_path_cfg *) + csid_hw->ppp_res.res_priv; + path_data->res_sof_cnt = 0; + } + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { path_data = (struct cam_tfe_csid_path_cfg *) csid_hw->rdi_res[i].res_priv; @@ -598,6 +628,24 @@ static int cam_tfe_csid_path_reset(struct cam_tfe_csid_hw *csid_hw, val |= TFE_CSID_PATH_INFO_RST_DONE; cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + } else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) { + if (!csid_reg->ppp_reg) { + CAM_ERR(CAM_ISP, "CSID:%d PPP not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = csid_reg->ppp_reg->csid_pxl_rst_strobes_addr; + complete = &csid_hw->csid_ppp_complete; + reset_strb_val = csid_reg->cmn_reg->ppp_path_rst_stb_all; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); + val |= TFE_CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); } else { id = res->res_id; if (!csid_reg->rdi_reg[id]) { @@ -649,13 +697,14 @@ static int cam_tfe_csid_cid_reserve(struct cam_tfe_csid_hw *csid_hw, const struct cam_tfe_csid_reg_offset *csid_reg; CAM_DBG(CAM_ISP, - "CSID:%d res_id:0x%x Lane type:%d lane_num:%d dt:%d vc:%d", + "CSID:%d res_id:0x%x Lane type:%d lane_num:%d dt:%d vc:%d, is_EPD: %d", csid_hw->hw_intf->hw_idx, cid_reserv->in_port->res_id, cid_reserv->in_port->lane_type, cid_reserv->in_port->lane_num, cid_reserv->in_port->dt[0], - cid_reserv->in_port->vc[0]); + cid_reserv->in_port->vc[0], + cid_reserv->in_port->epd_supported); if (cid_reserv->in_port->res_id >= CAM_ISP_TFE_IN_RES_MAX) { CAM_ERR(CAM_ISP, "CSID:%d Invalid phy sel %d", @@ -691,11 +740,10 @@ static int cam_tfe_csid_cid_reserve(struct cam_tfe_csid_hw *csid_hw, rc = -EINVAL; goto end; } - /* CSID CSI2 v1.1 supports 4 vc */ for (i = 0; i < cid_reserv->in_port->num_valid_vc_dt; i++) { if (cid_reserv->in_port->dt[i] > 0x3f || - cid_reserv->in_port->vc[i] > 0x3) { + cid_reserv->in_port->vc[i] > 0x1f) { CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d", csid_hw->hw_intf->hw_idx, cid_reserv->in_port->vc[i], @@ -754,6 +802,8 @@ static int cam_tfe_csid_cid_reserve(struct cam_tfe_csid_hw *csid_hw, cid_reserv->in_port->lane_type; csid_hw->csi2_rx_cfg.lane_num = cid_reserv->in_port->lane_num; + if (cid_reserv->in_port->epd_supported) + csid_hw->csi2_rx_cfg.epd_supported = 1; switch (cid_reserv->in_port->res_id) { case CAM_ISP_TFE_IN_RES_TPG: @@ -776,9 +826,11 @@ static int cam_tfe_csid_cid_reserve(struct cam_tfe_csid_hw *csid_hw, } csid_hw->csi2_reserve_cnt++; - CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired reserv cnt:%d", + CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired reserv cnt:%d phy_sel: %d res_id: %d", csid_hw->hw_intf->hw_idx, *cid_value, - csid_hw->csi2_reserve_cnt); + csid_hw->csi2_reserve_cnt, + csid_hw->csi2_rx_cfg.phy_sel, + cid_reserv->in_port->res_id); end: return rc; @@ -792,10 +844,19 @@ static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw, struct cam_isp_resource_node *res; uint32_t cid_value; + if (reserve->in_port->num_valid_vc_dt == 0 || + reserve->in_port->num_valid_vc_dt > CAM_ISP_TFE_VC_DT_CFG) { + CAM_ERR(CAM_ISP, "CSID:%d invalid num_valid_vc_dt: %d", + csid_hw->hw_intf->hw_idx, + reserve->in_port->num_valid_vc_dt); + rc = -EINVAL; + goto end; + } + /* CSID CSI2 v2.0 supports 4 vc */ for (i = 0; i < reserve->in_port->num_valid_vc_dt; i++) { if (reserve->in_port->dt[i] > 0x3f || - reserve->in_port->vc[i] > 0x3 || + reserve->in_port->vc[i] > 0x1f || (reserve->sync_mode >= CAM_ISP_HW_SYNC_MAX)) { CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d mode:%d", csid_hw->hw_intf->hw_idx, @@ -819,7 +880,7 @@ static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw, goto end; } - if (cam_tfe_csid_is_ipp_format_supported( + if (cam_tfe_csid_is_ipp_ppp_format_supported( reserve->in_port->format)) { CAM_ERR(CAM_ISP, "CSID:%d res id:%d un support format %d", @@ -840,6 +901,43 @@ static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw, break; + case CAM_TFE_CSID_PATH_RES_PPP: + if (csid_hw->ppp_res.res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_DBG(CAM_ISP, + "CSID:%d PPP resource not available %d", + csid_hw->hw_intf->hw_idx, + csid_hw->ppp_res.res_state); + rc = -EINVAL; + goto end; + } + + if (cam_tfe_csid_is_ipp_ppp_format_supported( + reserve->in_port->format)) { + CAM_ERR(CAM_ISP, + "CSID:%d res id:%d un support format %d", + csid_hw->hw_intf->hw_idx, reserve->res_id, + reserve->in_port->format); + rc = -EINVAL; + goto end; + } + + rc = cam_tfe_csid_cid_reserve(csid_hw, reserve, &cid_value); + if (rc) { + CAM_ERR(CAM_ISP, + "CSID:%d res id:%d invalid cid %d", + csid_hw->hw_intf->hw_idx, reserve->res_id, cid_value); + goto end; + } + + /* assign the PPP resource */ + res = &csid_hw->ppp_res; + CAM_DBG(CAM_ISP, + "CSID:%d PPP resource:%d acquired successfully", + csid_hw->hw_intf->hw_idx, res->res_id); + + break; + case CAM_TFE_CSID_PATH_RES_RDI_0: case CAM_TFE_CSID_PATH_RES_RDI_1: case CAM_TFE_CSID_PATH_RES_RDI_2: @@ -898,6 +996,9 @@ static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw, path_data->bayer_bin = reserve->in_port->bayer_bin; path_data->qcfa_bin = reserve->in_port->qcfa_bin; + path_data->crop_enable = reserve->crop_enable; + path_data->is_shdr_master = reserve->in_port->is_shdr_master; + path_data->is_shdr = reserve->in_port->shdr_en; csid_hw->event_cb = reserve->event_cb; csid_hw->event_cb_priv = reserve->event_cb_prv; @@ -911,10 +1012,6 @@ static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw, } } - /* Enable crop only for ipp */ - if (reserve->res_id == CAM_TFE_CSID_PATH_RES_IPP) - path_data->crop_enable = true; - CAM_DBG(CAM_ISP, "Res id: %d height:%d line_start %d line_end %d crop_en %d", reserve->res_id, reserve->in_port->height, @@ -970,6 +1067,38 @@ end: return rc; } +static void cam_tfe_csid_send_secure_info( + struct cam_tfe_csid_hw *csid_hw) +{ + struct cam_tfe_csid_secure_info secure_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + int phy_sel = 0; + + csid_reg = csid_hw->csid_info->csid_reg; + + secure_info.lane_cfg = csid_hw->csi2_rx_cfg.lane_cfg; + secure_info.cdm_hw_idx_mask = 0; + secure_info.vc_mask = 0; + secure_info.csid_hw_idx_mask = BIT(csid_hw->hw_intf->hw_idx); + + CAM_DBG(CAM_ISP, + "PHY secure info for CSID[%u], lane_cfg: 0x%x, tfe: 0x%x, cdm: 0x%x, vc_mask: 0x%llx", + csid_hw->hw_intf->hw_idx, secure_info.lane_cfg, secure_info.csid_hw_idx_mask, + secure_info.cdm_hw_idx_mask, secure_info.vc_mask); + + phy_sel = (int)(csid_hw->csi2_rx_cfg.phy_sel - csid_reg->csi2_reg->phy_sel_base); + if (phy_sel < 0) { + CAM_WARN(CAM_ISP, "Can't notify csiphy, incorrect phy selected=%d", + phy_sel); + } else { + secure_info.phy_sel = (uint32_t)phy_sel; + CAM_DBG(CAM_ISP, "Notify CSIPHY: %d", phy_sel); + cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_DOMAIN_ID_SECURE_PARAMS, (void *)&secure_info); + } + +} + static int cam_tfe_csid_enable_csi2( struct cam_tfe_csid_hw *csid_hw) { @@ -994,11 +1123,25 @@ static int cam_tfe_csid_enable_csi2( cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + if (csid_hw->in_res_id >= CAM_ISP_TFE_IN_RES_CPHY_TPG_0 && + csid_hw->in_res_id <= CAM_ISP_TFE_IN_RES_CPHY_TPG_2 && + csid_reg->csi2_reg->need_to_sel_tpg_mux) { + cam_cpas_enable_tpg_mux_sel(csid_hw->in_res_id - + CAM_ISP_TFE_IN_RES_CPHY_TPG_0); + } + /* rx cfg1 */ val = (1 << csid_reg->csi2_reg->csi2_misr_enable_shift_val); + /* enable vc mode to configure vc with value more than 3 */ + val |= (1 << csid_reg->csi2_reg->csi2_vc_mode_shift_val); + /* enable packet ecc correction */ val |= 1; + /* enable epd mode */ + if (csid_hw->csi2_rx_cfg.epd_supported) + val |= (csid_hw->csi2_rx_cfg.epd_supported << + csid_reg->csi2_reg->csi2_rx_epd_mode_shift_en); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); @@ -1017,6 +1160,10 @@ static int cam_tfe_csid_enable_csi2( TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME | TFE_CSID_CSI2_RX_ERROR_CPHY_PH_CRC; + if (csid_hw->csi2_rx_cfg.epd_supported && + (csid_hw->csi2_rx_cfg.lane_type == CAM_ISP_LANE_TYPE_DPHY)) + val &= ~TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION; + /* Enable the interrupt based on csid debug info set */ if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOT_IRQ) val |= TFE_CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED | @@ -1048,7 +1195,7 @@ static int cam_tfe_csid_enable_csi2( */ ppi_index = csid_hw->csi2_rx_cfg.phy_sel - csid_reg->csi2_reg->phy_sel_base; - if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { + if (csid_hw->ppi_enable && csid_hw->ppi_hw_intf[ppi_index]) { ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type; ppi_lane_cfg.lane_num = csid_hw->csi2_rx_cfg.lane_num; ppi_lane_cfg.lane_cfg = csid_hw->csi2_rx_cfg.lane_cfg; @@ -1092,7 +1239,7 @@ static int cam_tfe_csid_disable_csi2( csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); ppi_index = csid_hw->csi2_rx_cfg.phy_sel - csid_reg->csi2_reg->phy_sel_base; - if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { + if (csid_hw->ppi_enable && csid_hw->ppi_hw_intf[ppi_index]) { /* De-Initialize the PPI bridge */ CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index); rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.deinit( @@ -1133,8 +1280,8 @@ static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) return rc; } - CAM_DBG(CAM_ISP, "CSID:%d init CSID HW", - csid_hw->hw_intf->hw_idx); + CAM_DBG(CAM_ISP, "CSID:%d init CSID HW is_secure: %d", + csid_hw->hw_intf->hw_idx, csid_hw->is_secure); rc = cam_soc_util_get_clk_level(soc_info, csid_hw->clk_rate, soc_info->src_clk_idx, &clk_lvl); @@ -1169,6 +1316,11 @@ static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_clear_addr); + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, soc_info->reg_map[0].mem_base + @@ -1191,7 +1343,6 @@ static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) csid_hw->fatal_err_detected = false; csid_hw->device_enabled = 1; spin_unlock_irqrestore(&csid_hw->spin_lock, flags); - cam_tasklet_start(csid_hw->tasklet); if (csid_hw->pxl_pipe_enable ) { path_data = (struct cam_tfe_csid_path_cfg *) @@ -1199,12 +1350,21 @@ static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) path_data->res_sof_cnt = 0; } + if (csid_reg->cmn_reg->num_ppp) { + path_data = (struct cam_tfe_csid_path_cfg *) + csid_hw->ppp_res.res_priv; + path_data->res_sof_cnt = 0; + } + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { path_data = (struct cam_tfe_csid_path_cfg *) csid_hw->rdi_res[i].res_priv; path_data->res_sof_cnt = 0; } + if (csid_hw->is_secure) + cam_tfe_csid_send_secure_info(csid_hw); + return rc; @@ -1254,8 +1414,6 @@ static int cam_tfe_csid_disable_hw(struct cam_tfe_csid_hw *csid_hw) cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_mask_addr); - cam_tasklet_stop(csid_hw->tasklet); - rc = cam_tfe_csid_disable_soc_resources(soc_info); if (rc) CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", @@ -1286,15 +1444,22 @@ static int cam_tfe_csid_init_config_pxl_path( csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; - pxl_reg = csid_reg->ipp_reg; + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + pxl_reg = csid_reg->ipp_reg; + else + pxl_reg = csid_reg->ppp_reg; + if (!pxl_reg) { - CAM_ERR(CAM_ISP, "CSID:%d IPP :%d is not supported on HW", - csid_hw->hw_intf->hw_idx, res->res_id); + CAM_ERR(CAM_ISP, "CSID:%d %s :%d is not supported on HW", + csid_hw->hw_intf->hw_idx, + (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) ? "IPP" : "PPP", + res->res_id); return -EINVAL; } - CAM_DBG(CAM_ISP, "Config IPP Path"); - rc = cam_tfe_csid_get_format_ipp(path_data->in_format, + CAM_DBG(CAM_ISP, "Config %s Path", + (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) ? "IPP" : "PPP"); + rc = cam_tfe_csid_get_format_ipp_ppp(path_data->in_format, &decode_format, &plain_format); if (rc) return rc; @@ -1352,8 +1517,8 @@ static int cam_tfe_csid_init_config_pxl_path( } } - if (csid_reg->cmn_reg->format_measure_support && - (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO)) + if ((csid_reg->cmn_reg->format_measure_support && res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + || (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO)) val |= (1 << pxl_reg->format_measure_en_shift_val); val |= (1 << pxl_reg->pix_store_en_shift_val); @@ -1473,18 +1638,25 @@ static int cam_tfe_csid_deinit_pxl_path( csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; - pxl_reg = csid_reg->ipp_reg; + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + pxl_reg = csid_reg->ipp_reg; + else + pxl_reg = csid_reg->ppp_reg; + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { CAM_ERR(CAM_ISP, - "CSID:%d IPP Res type %d res_id:%d in wrong state %d", + "CSID:%d %s Res type %d res_id:%d in wrong state %d", csid_hw->hw_intf->hw_idx, + (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) ? "IPP" : "PPP", res->res_type, res->res_id, res->res_state); rc = -EINVAL; } if (!pxl_reg) { - CAM_ERR(CAM_ISP, "CSID:%d IPP %d is not supported on HW", - csid_hw->hw_intf->hw_idx, res->res_id); + CAM_ERR(CAM_ISP, "CSID:%d %s %d is not supported on HW", + csid_hw->hw_intf->hw_idx, + (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) ? "IPP" : "PPP", + res->res_id); rc = -EINVAL; goto end; } @@ -1529,33 +1701,31 @@ static int cam_tfe_csid_enable_pxl_path( CAM_DBG(CAM_ISP, "Enable IPP path"); - /* Set master or slave path */ - if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) - /* Set halt mode as master */ - val = (TFE_CSID_HALT_MODE_MASTER << - pxl_reg->halt_mode_shift) | - (pxl_reg->halt_master_sel_master_val << - pxl_reg->halt_master_sel_shift); - else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) - /* Set halt mode as slave and set master idx */ - val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift); + if ((path_data->is_shdr && path_data->is_shdr_master) || + (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)) + /* Set halt mode for master */ + val = (TFE_CSID_HALT_MODE_MASTER << pxl_reg->halt_mode_shift) | + (TFE_CSID_HALT_CMD_SOURCE_NONE << pxl_reg->halt_master_sel_shift) | + (CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift); + else if ((path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) || + (path_data->is_shdr)) + /* Set halt mode for slave */ + val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift) | + (TFE_CSID_HALT_CMD_SOURCE_EXTERNAL << pxl_reg->halt_master_sel_shift) | + (CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift); else - /* Default is internal halt mode */ - val = 0; - - /* - * Resume at frame boundary if Master or No Sync. - * Slave will get resume command from Master. - */ - if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || - path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) - val |= CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY; + /* Set halt mode for default */ + val = (TFE_CSID_HALT_MODE_INTERNAL << pxl_reg->halt_mode_shift) | + (TFE_CSID_HALT_CMD_SOURCE_NONE << pxl_reg->halt_master_sel_shift) | + (CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_ctrl_addr); - CAM_DBG(CAM_ISP, "CSID:%d IPP Ctrl val: 0x%x", - csid_hw->hw_intf->hw_idx, val); + CAM_DBG(CAM_ISP, "CSID:%d sync_mode=%d IPP_Ctrl:0x%x is_shdr=%d shdr_master=%d", + csid_hw->hw_intf->hw_idx, path_data->sync_mode, + cam_io_r_mb(soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_ctrl_addr), + path_data->is_shdr, path_data->is_shdr_master); /* Enable the required pxl path interrupts */ val = TFE_CSID_PATH_INFO_RST_DONE | @@ -1568,7 +1738,7 @@ static int cam_tfe_csid_enable_pxl_path( TFE_CSID_PATH_ERROR_LINE_COUNT; } - if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ) + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ || path_data->init_frame_drop) val |= TFE_CSID_PATH_INFO_INPUT_SOF; if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ) val |= TFE_CSID_PATH_INFO_INPUT_EOF; @@ -1634,7 +1804,6 @@ static int cam_tfe_csid_disable_pxl_path( enum cam_tfe_csid_halt_cmd stop_cmd) { int rc = 0; - uint32_t val = 0; const struct cam_tfe_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; struct cam_tfe_csid_path_cfg *path_data; @@ -1658,6 +1827,7 @@ static int cam_tfe_csid_disable_pxl_path( } pxl_reg = csid_reg->ipp_reg; + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { CAM_DBG(CAM_ISP, "CSID:%d IPP path Res:%d Invalid state%d", csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); @@ -1684,29 +1854,157 @@ static int cam_tfe_csid_disable_pxl_path( cam_io_w_mb(0, soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_irq_mask_addr); - if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || - path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) { - /* configure Halt */ - val = cam_io_r_mb(soc_info->reg_map[0].mem_base + - pxl_reg->csid_pxl_ctrl_addr); - val &= ~0x3; - val |= stop_cmd; - cam_io_w_mb(val, soc_info->reg_map[0].mem_base + - pxl_reg->csid_pxl_ctrl_addr); + path_data->init_frame_drop = 0; + path_data->res_sof_cnt = 0; + + CAM_DBG(CAM_ISP, "halt CSID:%d sync_mode:%d res_id:%d IPP path pxl_ctrl=0x%x", + csid_hw->hw_intf->hw_idx, path_data->sync_mode, res->res_id, + cam_io_r_mb(soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_ctrl_addr)); + + return rc; +} + +static int cam_tfe_csid_enable_ppp_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_pxl_reg_offset *ppp_reg = NULL; + uint32_t val = 0; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + ppp_reg = csid_reg->ppp_reg; + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { + CAM_ERR(CAM_ISP, + "CSID:%d PPP path res type:%d res_id:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + return -EINVAL; } - if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE && - stop_cmd == CAM_TFE_CSID_HALT_IMMEDIATELY) { - /* configure Halt for slave */ - val = cam_io_r_mb(soc_info->reg_map[0].mem_base + - pxl_reg->csid_pxl_ctrl_addr); - val &= ~0xF; - val |= stop_cmd; - val |= (TFE_CSID_HALT_MODE_MASTER << 2); - cam_io_w_mb(val, soc_info->reg_map[0].mem_base + - pxl_reg->csid_pxl_ctrl_addr); + if (!ppp_reg) { + CAM_ERR(CAM_ISP, "CSID:%d PPP resid: %d not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; } + CAM_DBG(CAM_ISP, "CSID:%d Enable PPP path", csid_hw->hw_intf->hw_idx); + + if ((path_data->is_shdr && path_data->is_shdr_master) || + (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)) + /* Set halt mode for master shdr/dual */ + val = (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift) | + (TFE_CSID_HALT_CMD_SOURCE_INTERNAL1 << ppp_reg->halt_master_sel_shift) | + (CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << ppp_reg->halt_cmd_shift); + else if ((path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) || + (path_data->is_shdr)) + /* Set halt mode for slave shdr/dual*/ + val = (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift) | + (TFE_CSID_HALT_CMD_SOURCE_INTERNAL2 << ppp_reg->halt_master_sel_shift) | + (CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << ppp_reg->halt_cmd_shift); + else + /* Set halt mode for default */ + val = (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift) | + (TFE_CSID_HALT_CMD_SOURCE_INTERNAL1 << ppp_reg->halt_master_sel_shift) | + (CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << ppp_reg->halt_cmd_shift); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr); + + CAM_DBG(CAM_ISP, "CSID:%d sync_mode:%d PPP Ctrl val: 0x%x", + csid_hw->hw_intf->hw_idx, path_data->sync_mode, + cam_io_r_mb(soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr)); + + /* Enable the required ppp path interrupts */ + val = TFE_CSID_PATH_INFO_RST_DONE | TFE_CSID_PATH_ERROR_FIFO_OVERFLOW | + TFE_CSID_PATH_PPP_ERROR_CCIF_VIOLATION | TFE_CSID_PATH_PPP_OVERFLOW_IRQ; + + if (csid_reg->cmn_reg->format_measure_support) + val |= TFE_CSID_PATH_ERROR_PIX_COUNT | TFE_CSID_PATH_ERROR_LINE_COUNT; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ || path_data->init_frame_drop) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_irq_mask_addr); + + CAM_DBG(CAM_ISP, "CSID:%d Enable PPP IRQ mask 0x%x", csid_hw->hw_intf->hw_idx, val); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_tfe_csid_disable_ppp_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_tfe_csid_halt_cmd stop_cmd) +{ + int rc = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_pxl_reg_offset *ppp_reg; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); + return rc; + } + + ppp_reg = csid_reg->ppp_reg; + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_DBG(CAM_ISP, "CSID:%d IPP path Res:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); + return -EINVAL; + } + + if (!ppp_reg) { + CAM_ERR(CAM_ISP, "CSID:%d PPP %d is not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (stop_cmd != CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_TFE_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, + "CSID:%d PPP path un supported stop command:%d", + csid_hw->hw_intf->hw_idx, stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d PPP path", + csid_hw->hw_intf->hw_idx, res->res_id); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + ppp_reg->csid_pxl_irq_mask_addr); + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d Skip prgramming halt mode for PPP path", + csid_hw->hw_intf->hw_idx, res->res_id); + + CAM_DBG(CAM_ISP, "CSID:%d sync_mode:%d res_id:%d PPP path halt_ctrl_reg=0x%x", + csid_hw->hw_intf->hw_idx, path_data->sync_mode, res->res_id, + cam_io_r_mb(soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr)); + + path_data->init_frame_drop = 0; + path_data->res_sof_cnt = 0; + return rc; } @@ -1749,8 +2047,7 @@ static int cam_tfe_csid_init_config_rdi_path( (plain_fmt << csid_reg->cmn_reg->plain_fmt_shit_val) | (1 << 2) | 1; - if (csid_reg->cmn_reg->format_measure_support && - (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO)) + if (csid_reg->cmn_reg->format_measure_support) val |= (1 << rdi_reg->format_measure_en_shift_val); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + @@ -2007,6 +2304,9 @@ static int cam_tfe_csid_poll_stop_status( uint32_t csid_status_addr = 0, val = 0, res_id = 0; const struct cam_tfe_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; + uint32_t csid_ctrl_reg = 0; + uint32_t csid_cfg0_reg = 0; + uint32_t csid_cfg1_reg = 0; csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; @@ -2020,13 +2320,31 @@ static int cam_tfe_csid_poll_stop_status( csid_status_addr = csid_reg->ipp_reg->csid_pxl_status_addr; + csid_ctrl_reg = csid_reg->ipp_reg->csid_pxl_ctrl_addr; + csid_cfg0_reg = csid_reg->ipp_reg->csid_pxl_cfg0_addr; + csid_cfg1_reg = csid_reg->ipp_reg->csid_pxl_cfg1_addr; + if (csid_hw->ipp_res.res_state != CAM_ISP_RESOURCE_STATE_STREAMING) continue; + } else if (res_id == CAM_TFE_CSID_PATH_RES_PPP) { + csid_status_addr = + csid_reg->ppp_reg->csid_pxl_status_addr; + csid_ctrl_reg = csid_reg->ppp_reg->csid_pxl_ctrl_addr; + csid_cfg0_reg = csid_reg->ppp_reg->csid_pxl_cfg0_addr; + csid_cfg1_reg = csid_reg->ppp_reg->csid_pxl_cfg1_addr; + + if (csid_hw->ppp_res.res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + } else { csid_status_addr = csid_reg->rdi_reg[res_id]->csid_rdi_status_addr; + csid_ctrl_reg = csid_reg->rdi_reg[res_id]->csid_rdi_ctrl_addr; + csid_cfg0_reg = csid_reg->rdi_reg[res_id]->csid_rdi_cfg0_addr; + csid_cfg1_reg = csid_reg->rdi_reg[res_id]->csid_rdi_cfg1_addr; if (csid_hw->rdi_res[res_id].res_state != CAM_ISP_RESOURCE_STATE_STREAMING) @@ -2047,6 +2365,13 @@ static int cam_tfe_csid_poll_stop_status( if (rc < 0) { CAM_ERR(CAM_ISP, "CSID:%d res:%d halt failed rc %d", csid_hw->hw_intf->hw_idx, res_id, rc); + + CAM_ERR(CAM_ISP, "CSID:%d status:0x%x ctrl_reg:0x%x cfg0:0x%x cfg1:0x%x", + csid_hw->hw_intf->hw_idx, + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_status_addr), + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_ctrl_reg), + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_cfg0_reg), + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_cfg1_reg)); rc = -ETIMEDOUT; break; } @@ -2121,6 +2446,19 @@ static int cam_tfe_csid_get_time_stamp( csid_reg->ipp_reg->csid_pxl_timestamp_perv0_sof_addr, &time_stamp->prev_time_stamp_val); } + } else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) { + torn = __cam_tfe_csid_read_timestamp( + soc_info->reg_map[0].mem_base, + csid_reg->ppp_reg->csid_pxl_timestamp_curr1_sof_addr, + csid_reg->ppp_reg->csid_pxl_timestamp_curr0_sof_addr, + &time_stamp->time_stamp_val); + if (time_stamp->get_prev_timestamp) { + prev_torn = __cam_tfe_csid_read_timestamp( + soc_info->reg_map[0].mem_base, + csid_reg->ppp_reg->csid_pxl_timestamp_perv1_sof_addr, + csid_reg->ppp_reg->csid_pxl_timestamp_perv0_sof_addr, + &time_stamp->prev_time_stamp_val); + } } else { id = res->res_id; rdi_reg = csid_reg->rdi_reg[id]; @@ -2221,6 +2559,11 @@ static int cam_tfe_csid_print_hbi_vbi( csid_reg->ipp_reg->csid_pxl_format_measure1_addr); vbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_format_measure2_addr); + } else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) { + hbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_format_measure1_addr); + vbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_format_measure2_addr); } else if ((res->res_id >= CAM_TFE_CSID_PATH_RES_RDI_0) && (res->res_id <= CAM_TFE_CSID_PATH_RES_RDI_2)) { rdi_reg = csid_reg->rdi_reg[res->res_id]; @@ -2263,6 +2606,7 @@ static int cam_tfe_csid_get_hw_caps(void *hw_priv, struct cam_tfe_csid_hw *csid_hw; struct cam_hw_info *csid_hw_info; const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_tfe_csid_soc_private *soc_private; if (!hw_priv || !get_hw_cap_args) { CAM_ERR(CAM_ISP, "CSID: Invalid args"); @@ -2273,12 +2617,16 @@ static int cam_tfe_csid_get_hw_caps(void *hw_priv, csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; csid_reg = csid_hw->csid_info->csid_reg; hw_caps = (struct cam_tfe_csid_hw_caps *) get_hw_cap_args; + soc_private = (struct cam_tfe_csid_soc_private *) csid_hw_info->soc_info.soc_private; hw_caps->num_rdis = csid_reg->cmn_reg->num_rdis; hw_caps->num_pix = csid_hw->pxl_pipe_enable; + hw_caps->num_ppp = csid_reg->cmn_reg->num_ppp; hw_caps->major_version = csid_reg->cmn_reg->major_version; hw_caps->minor_version = csid_reg->cmn_reg->minor_version; hw_caps->version_incr = csid_reg->cmn_reg->version_incr; + hw_caps->sync_clk = csid_reg->cmn_reg->sync_clk; + hw_caps->is_lite = soc_private->is_tfe_csid_lite; CAM_DBG(CAM_ISP, "CSID:%d No rdis:%d, no pix:%d, major:%d minor:%d ver :%d", @@ -2348,8 +2696,10 @@ static int cam_tfe_csid_reserve(void *hw_priv, return -EINVAL; } - CAM_DBG(CAM_ISP, "res_type %d, CSID: %u", - reserv->res_type, csid_hw->hw_intf->hw_idx); + csid_hw->is_secure = reserv->out_port->secure_mode; + + CAM_DBG(CAM_ISP, "res_type %d, CSID: %u is_secure: %d", + reserv->res_type, csid_hw->hw_intf->hw_idx, csid_hw->is_secure); mutex_lock(&csid_hw->hw_info->hw_mutex); rc = cam_tfe_csid_path_reserve(csid_hw, reserv); @@ -2395,6 +2745,7 @@ static int cam_tfe_csid_release(void *hw_priv, csid_hw->event_cb = NULL; csid_hw->event_cb_priv = NULL; + csid_hw->is_secure = false; if ((res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE) || (res->res_state >= CAM_ISP_RESOURCE_STATE_STREAMING)) { @@ -2539,7 +2890,8 @@ static int cam_tfe_csid_init_hw(void *hw_priv, if (rc) goto end; - if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + if ((res->res_id == CAM_TFE_CSID_PATH_RES_IPP) || + (res->res_id == CAM_TFE_CSID_PATH_RES_PPP)) rc = cam_tfe_csid_init_config_pxl_path(csid_hw, res); else rc = cam_tfe_csid_init_config_rdi_path(csid_hw, res); @@ -2548,9 +2900,6 @@ static int cam_tfe_csid_init_hw(void *hw_priv, if (rc < 0) CAM_ERR(CAM_ISP, "CSID: Failed in SW reset"); - if (rc) - cam_tfe_csid_disable_hw(csid_hw); - spin_lock_irqsave(&csid_hw->spin_lock, flags); csid_hw->device_enabled = 1; spin_unlock_irqrestore(&csid_hw->spin_lock, flags); @@ -2595,7 +2944,8 @@ static int cam_tfe_csid_deinit_hw(void *hw_priv, CAM_DBG(CAM_ISP, "De-Init IPP Path: %d", res->res_id); - if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + if ((res->res_id == CAM_TFE_CSID_PATH_RES_IPP) || + (res->res_id == CAM_TFE_CSID_PATH_RES_PPP)) rc = cam_tfe_csid_deinit_pxl_path(csid_hw, res); else rc = cam_tfe_csid_deinit_rdi_path(csid_hw, res); @@ -2650,6 +3000,8 @@ static int cam_tfe_csid_start(void *hw_priv, void *start_args, case CAM_ISP_RESOURCE_PIX_PATH: if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) rc = cam_tfe_csid_enable_pxl_path(csid_hw, res); + else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) + rc = cam_tfe_csid_enable_ppp_path(csid_hw, res); else rc = cam_tfe_csid_enable_rdi_path(csid_hw, res); break; @@ -2707,12 +3059,16 @@ static int cam_tfe_csid_stop(void *hw_priv, void *stop_args, uint32_t arg_size) { int rc = 0; - struct cam_tfe_csid_hw *csid_hw; - struct cam_hw_info *csid_hw_info; - struct cam_isp_resource_node *res; - struct cam_tfe_csid_hw_stop_args *csid_stop; - uint32_t i; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_hw_stop_args *csid_stop; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg; + uint32_t i, val = 0; uint32_t res_mask = 0; + void __iomem *mem_base; if (!hw_priv || !stop_args || (arg_size != sizeof(struct cam_tfe_csid_hw_stop_args))) { @@ -2728,9 +3084,74 @@ static int cam_tfe_csid_stop(void *hw_priv, csid_hw_info = (struct cam_hw_info *)hw_priv; csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; - CAM_DBG(CAM_ISP, "CSID:%d num_res %d", - csid_hw->hw_intf->hw_idx, - csid_stop->num_res); + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + mem_base = soc_info->reg_map[0].mem_base; + + /* Disalbe cgc for all the path */ + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + switch (res->res_type) { + case CAM_ISP_RESOURCE_PIX_PATH: + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + pxl_reg = csid_reg->ipp_reg; + val = cam_io_r_mb(mem_base + pxl_reg->csid_pxl_cfg0_addr); + val = val | (1 << pxl_reg->cgc_mode_en_shift_val); + cam_io_w_mb(val, mem_base + pxl_reg->csid_pxl_cfg0_addr); + } else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) { + pxl_reg = csid_reg->ppp_reg; + val = cam_io_r_mb(mem_base + pxl_reg->csid_pxl_cfg0_addr); + val = val | (1 << pxl_reg->cgc_mode_en_shift_val); + cam_io_w_mb(val, mem_base + pxl_reg->csid_pxl_cfg0_addr); + } + CAM_DBG(CAM_ISP, "CSID:%d cgc change res_type %d res_id %d val:0x%x", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, val); + break; + default: + CAM_DBG(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, res->res_type); + break; + } + } + + /* csid ctrl to resume at frame boundary */ + cam_io_w_mb(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY, + mem_base + csid_reg->cmn_reg->csid_ctrl_addr); + + /* halt to global */ + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + switch (res->res_type) { + case CAM_ISP_RESOURCE_PIX_PATH: + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + pxl_reg = csid_reg->ipp_reg; + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~(pxl_reg->halt_mode_mask << pxl_reg->halt_mode_shift); + val |= (TFE_CSID_HALT_MODE_GLOBAL << pxl_reg->halt_mode_shift); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) { + pxl_reg = csid_reg->ppp_reg; + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~(pxl_reg->halt_mode_mask << pxl_reg->halt_mode_shift); + val |= (TFE_CSID_HALT_MODE_GLOBAL << pxl_reg->halt_mode_shift); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + CAM_DBG(CAM_ISP, "CSID:%d global change res_type %d res_id %d val:0x%x", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, val); + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, + res->res_type); + break; + } + } /* Stop the resource first */ for (i = 0; i < csid_stop->num_res; i++) { @@ -2744,10 +3165,12 @@ static int cam_tfe_csid_stop(void *hw_priv, if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) rc = cam_tfe_csid_disable_pxl_path(csid_hw, res, csid_stop->stop_cmd); + else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) + rc = cam_tfe_csid_disable_ppp_path(csid_hw, + res, csid_stop->stop_cmd); else rc = cam_tfe_csid_disable_rdi_path(csid_hw, res, csid_stop->stop_cmd); - break; default: CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", @@ -2757,9 +3180,40 @@ static int cam_tfe_csid_stop(void *hw_priv, } } + /* issue global cmd */ + cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, + mem_base + csid_reg->cmn_reg->csid_ctrl_addr); + if (res_mask) rc = cam_tfe_csid_poll_stop_status(csid_hw, res_mask); + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + CAM_DBG(CAM_ISP, "CSID:%d cgc change to dynamic res_type %d res_id %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id); + switch (res->res_type) { + case CAM_ISP_RESOURCE_PIX_PATH: + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + pxl_reg = csid_reg->ipp_reg; + val = cam_io_r_mb(mem_base + pxl_reg->csid_pxl_cfg0_addr); + val &= ~(1 << pxl_reg->cgc_mode_en_shift_val); + cam_io_w_mb(val, mem_base + pxl_reg->csid_pxl_cfg0_addr); + } else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) { + pxl_reg = csid_reg->ipp_reg; + val = cam_io_r_mb(mem_base + pxl_reg->csid_pxl_cfg0_addr); + val &= ~(1 << pxl_reg->cgc_mode_en_shift_val); + cam_io_w_mb(val, mem_base + pxl_reg->csid_pxl_cfg0_addr); + } else + continue; + default: + CAM_DBG(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, + res->res_type); + break; + } + } + for (i = 0; i < csid_stop->num_res; i++) { res = csid_stop->node_res[i]; res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; @@ -2823,6 +3277,22 @@ static int cam_tfe_csid_sof_irq_debug( } } + if (csid_reg->ppp_reg) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); + + if (val) { + if (sof_irq_enable) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + else + val &= ~TFE_CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); + val = 0; + } + } + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); @@ -2871,6 +3341,85 @@ static int cam_tfe_csid_set_csid_clock( return 0; } +static int cam_tfe_csid_dump_csid_clock( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_hw_soc_info *soc_info; + + if (!csid_hw) + return -EINVAL; + + soc_info = &csid_hw->hw_info->soc_info; + + CAM_INFO(CAM_ISP, "CSID:%d sw_client clk rate:%lu ", + csid_hw->hw_intf->hw_idx, + soc_info->applied_src_clk_rates.sw_client); + + return 0; +} + +static int cam_tfe_csid_set_csid_clock_dynamically( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_hw_soc_info *soc_info; + unsigned long *clk_rate; + int rc = 0; + + soc_info = &csid_hw->hw_info->soc_info; + clk_rate = (unsigned long *)cmd_args; + + CAM_DBG(CAM_ISP, "CSID[%u] clock rate requested: %llu curr: %llu", + csid_hw->hw_intf->hw_idx, *clk_rate, soc_info->applied_src_clk_rates.sw_client); + + if (*clk_rate <= soc_info->applied_src_clk_rates.sw_client) + goto end; + + rc = cam_soc_util_set_src_clk_rate(soc_info, CAM_CLK_SW_CLIENT_IDX, *clk_rate, 0); + if (rc) { + CAM_ERR(CAM_ISP, + "unable to set clock dynamically rate:%llu", *clk_rate); + return rc; + } +end: + *clk_rate = soc_info->applied_src_clk_rates.sw_client; + CAM_DBG(CAM_ISP, "CSID[%u] new clock rate %llu", + csid_hw->hw_intf->hw_idx, soc_info->applied_src_clk_rates.sw_client); + + return rc; +} + +static int cam_tfe_csid_set_discard_frame_cfg( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_isp_resource_node *res; + struct cam_tfe_csid_path_cfg *path_cfg; + struct cam_tfe_csid_discard_init_frame_args *discard_config = NULL; + + if (!csid_hw) + return -EINVAL; + + discard_config = (struct cam_tfe_csid_discard_init_frame_args *)cmd_args; + + res = discard_config->res; + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_ERR(CAM_ISP, "CSID[%u] Invalid res_type: %d res id: %d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + return -EINVAL; + } + + if ((res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW)) { + + path_cfg = (struct cam_tfe_csid_path_cfg *)res->res_priv; + + path_cfg->init_frame_drop = discard_config->num_frames; + path_cfg->res_sof_cnt = 0; + } + + return 0; +} + static int cam_tfe_csid_get_regdump(struct cam_tfe_csid_hw *csid_hw, void *cmd_args) { @@ -2925,6 +3474,29 @@ static int cam_tfe_csid_get_regdump(struct cam_tfe_csid_hw *csid_hw, csid_reg->ipp_reg->csid_pxl_vcrop_addr); CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", csid_reg->ipp_reg->csid_pxl_vcrop_addr, val); + } else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP) { + CAM_INFO(CAM_ISP, "Dumping CSID:%d PPP registers ", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_cfg0_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ppp_reg->csid_pxl_cfg0_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_cfg1_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ppp_reg->csid_pxl_cfg1_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_ctrl_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ppp_reg->csid_pxl_ctrl_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_hcrop_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ppp_reg->csid_pxl_hcrop_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_vcrop_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ppp_reg->csid_pxl_vcrop_addr, val); } else { id = res->res_id; CAM_INFO(CAM_ISP, "Dumping CSID:%d RDI:%d registers ", @@ -3141,6 +3713,9 @@ static int cam_tfe_csid_process_cmd(void *hw_priv, case CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE: rc = cam_tfe_csid_set_csid_clock(csid_hw, cmd_args); break; + case CAM_ISP_HW_CMD_CSID_CLOCK_DUMP: + rc = cam_tfe_csid_dump_csid_clock(csid_hw, cmd_args); + break; case CAM_TFE_CSID_CMD_GET_REG_DUMP: rc = cam_tfe_csid_get_regdump(csid_hw, cmd_args); break; @@ -3153,6 +3728,12 @@ static int cam_tfe_csid_process_cmd(void *hw_priv, case CAM_TFE_CSID_LOG_ACQUIRE_DATA: rc = cam_tfe_csid_log_acquire_data(csid_hw, cmd_args); break; + case CAM_ISP_HW_CMD_DYNAMIC_CLOCK_UPDATE: + rc = cam_tfe_csid_set_csid_clock_dynamically(csid_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_CSID_DISCARD_INIT_FRAMES: + rc = cam_tfe_csid_set_discard_frame_cfg(csid_hw, cmd_args); + break; default: CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", csid_hw->hw_intf->hw_idx, cmd_type); @@ -3217,6 +3798,7 @@ static int cam_tfe_csid_evt_bottom_half_handler( struct cam_isp_hw_event_info event_info; int i; int rc = 0; + uint32_t data_idx; if (!handler_priv || !evt_payload_priv) { CAM_ERR(CAM_ISP, @@ -3228,6 +3810,7 @@ static int cam_tfe_csid_evt_bottom_half_handler( csid_hw = (struct cam_tfe_csid_hw *)handler_priv; evt_payload = (struct cam_csid_evt_payload *)evt_payload_priv; csid_reg = csid_hw->csid_info->csid_reg; + data_idx = csid_hw->csi2_rx_cfg.phy_sel - 1; if (!csid_hw->event_cb || !csid_hw->event_cb_priv) { CAM_ERR_RATE_LIMIT(CAM_ISP, @@ -3256,6 +3839,13 @@ static int cam_tfe_csid_evt_bottom_half_handler( csid_hw->hw_intf->hw_idx); } + if (evt_payload->irq_status[TFE_CSID_IRQ_REG_PPP] & + TFE_CSID_PATH_INFO_INPUT_SOF) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PPP SOF received", + csid_hw->hw_intf->hw_idx); + } + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { if (evt_payload->irq_status[i] & TFE_CSID_PATH_INFO_INPUT_SOF) @@ -3265,13 +3855,14 @@ static int cam_tfe_csid_evt_bottom_half_handler( } } else { CAM_ERR_RATE_LIMIT(CAM_ISP, - "CSID %d err %d phy %d irq status TOP: 0x%x RX: 0x%x IPP: 0x%x RDI0: 0x%x RDI1: 0x%x RDI2: 0x%x", + "CSID %d err %d phy %d irq status TOP: 0x%x RX: 0x%x IPP: 0x%x PPP: 0x%x RDI0: 0x%x RDI1: 0x%x RDI2: 0x%x", csid_hw->hw_intf->hw_idx, evt_payload->evt_type, csid_hw->csi2_rx_cfg.phy_sel, evt_payload->irq_status[TFE_CSID_IRQ_REG_TOP], evt_payload->irq_status[TFE_CSID_IRQ_REG_RX], evt_payload->irq_status[TFE_CSID_IRQ_REG_IPP], + evt_payload->irq_status[TFE_CSID_IRQ_REG_PPP], evt_payload->irq_status[TFE_CSID_IRQ_REG_RDI0], evt_payload->irq_status[TFE_CSID_IRQ_REG_RDI1], evt_payload->irq_status[TFE_CSID_IRQ_REG_RDI2]); @@ -3282,14 +3873,23 @@ static int cam_tfe_csid_evt_bottom_half_handler( */ err_evt_info.err_type = evt_payload->evt_type; event_info.hw_idx = evt_payload->hw_idx; + event_info.res_type = CAM_ISP_RESOURCE_PIX_PATH; + event_info.hw_type = CAM_ISP_HW_TYPE_TFE_CSID; switch (evt_payload->evt_type) { - case CAM_ISP_HW_ERROR_CSID_FATAL: - if (csid_hw->fatal_err_detected) + case CAM_ISP_HW_ERROR_CSID_FRAME_SIZE: break; - event_info.event_data = (void *)&err_evt_info; + case CAM_ISP_HW_ERROR_CSID_FATAL: + /* phy_sel starts from 1 and should never be zero*/ + if (csid_hw->csi2_rx_cfg.phy_sel > 0) { + cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_REG_DUMP, (void *)&data_idx); + } csid_hw->fatal_err_detected = true; - rc = csid_hw->event_cb(NULL, + break; + case CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW: + event_info.event_data = (void *)&err_evt_info; + rc = csid_hw->event_cb(csid_hw->event_cb_priv, CAM_ISP_HW_EVENT_ERROR, (void *)&event_info); break; @@ -3356,15 +3956,17 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) struct cam_hw_soc_info *soc_info; const struct cam_tfe_csid_reg_offset *csid_reg; const struct cam_tfe_csid_pxl_reg_offset *ipp_reg; + const struct cam_tfe_csid_pxl_reg_offset *ppp_reg; const struct cam_tfe_csid_rdi_reg_offset *rdi_reg; const struct cam_tfe_csid_common_reg_offset *cmn_reg; const struct cam_tfe_csid_csi2_rx_reg_offset *csi2_reg; - uint32_t irq_status[TFE_CSID_IRQ_REG_MAX]; + uint32_t irq_status[TFE_CSID_IRQ_REG_MAX] = {0}; bool fatal_err_detected = false, is_error_irq = false; uint32_t sof_irq_debug_en = 0, log_en = 0; unsigned long flags; uint32_t i, val, val1; uint32_t data_idx; + uint32_t report_err_type = CAM_ISP_HW_ERROR_NONE; if (!data) { CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); @@ -3393,6 +3995,11 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_status_addr); + if (csid_reg->cmn_reg->num_ppp) + irq_status[TFE_CSID_IRQ_REG_PPP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_status_addr); + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) irq_status[i] = cam_io_r_mb(soc_info->reg_map[0].mem_base + @@ -3412,6 +4019,11 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(irq_status[TFE_CSID_IRQ_REG_PPP], + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_clear_addr); + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { cam_io_w_mb(irq_status[i], soc_info->reg_map[0].mem_base + @@ -3420,7 +4032,6 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); - /* Software register reset complete*/ if (irq_status[TFE_CSID_IRQ_REG_TOP]) complete(&csid_hw->csid_top_complete); @@ -3455,8 +4066,16 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) } if (irq_status[TFE_CSID_IRQ_REG_RX] & - TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) - csid_hw->error_irq_count++; + TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) { + if (csid_hw->csi2_rx_cfg.epd_supported) + CAM_DBG(CAM_ISP, + "CSID[%u] Rcvd Only ERROR_EOT for EPD sensor PHY type: %s(%u)", + csid_hw->hw_intf->hw_idx, + (csid_hw->csi2_rx_cfg.lane_type) ? "cphy" : "dphy", + csid_hw->csi2_rx_cfg.lane_type); + else + csid_hw->error_irq_count++; + } if (irq_status[TFE_CSID_IRQ_REG_RX] & TFE_CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) @@ -3481,6 +4100,7 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) if (irq_status[TFE_CSID_IRQ_REG_RX] & TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) is_error_irq = true; + } handle_fatal_error: spin_unlock_irqrestore(&csid_hw->spin_lock, flags); @@ -3502,13 +4122,10 @@ handle_fatal_error: csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); - /* phy_sel starts from 1 and should never be zero*/ - if (csid_hw->csi2_rx_cfg.phy_sel > 0) { - cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE, - CAM_SUBDEV_MESSAGE_REG_DUMP, (void *)&data_idx); - } + + report_err_type = CAM_ISP_HW_ERROR_CSID_FATAL; cam_tfe_csid_handle_hw_err_irq(csid_hw, - CAM_ISP_HW_ERROR_CSID_FATAL, irq_status); + report_err_type, irq_status); } if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOT_IRQ) { @@ -3635,6 +4252,11 @@ handle_fatal_error: CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID IPP reset complete"); + if (irq_status[TFE_CSID_IRQ_REG_PPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID PPP reset complete"); + if (irq_status[TFE_CSID_IRQ_REG_TOP]) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID TOP reset complete"); @@ -3654,6 +4276,12 @@ handle_fatal_error: complete(&csid_hw->csid_ipp_complete); } + if (irq_status[TFE_CSID_IRQ_REG_IPP] & TFE_CSID_PATH_INFO_INPUT_SOF) { + CAM_DBG(CAM_ISP, "CSID:%d IPP SOF received", csid_hw->hw_intf->hw_idx); + cam_tfe_csid_enable_path_for_init_frame_drop(csid_hw, + CAM_TFE_CSID_PATH_RES_IPP); + } + if ((irq_status[TFE_CSID_IRQ_REG_IPP] & TFE_CSID_PATH_INFO_INPUT_SOF) && (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ)) { @@ -3682,16 +4310,15 @@ handle_fatal_error: soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_ctrl_addr); is_error_irq = true; + report_err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW; } if (irq_status[TFE_CSID_IRQ_REG_IPP] & TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION) is_error_irq = true; - if ((irq_status[TFE_CSID_IRQ_REG_IPP] & - TFE_CSID_PATH_ERROR_PIX_COUNT) || - (irq_status[TFE_CSID_IRQ_REG_IPP] & - TFE_CSID_PATH_ERROR_LINE_COUNT)) { + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + (TFE_CSID_PATH_ERROR_PIX_COUNT | TFE_CSID_PATH_ERROR_LINE_COUNT)) { ipp_reg = csid_reg->ipp_reg; cmn_reg = csid_reg->cmn_reg; val = cam_io_r_mb(soc_info->reg_map[0].mem_base + @@ -3712,6 +4339,86 @@ handle_fatal_error: cmn_reg->format_measure_height_mask_val), val & cmn_reg->format_measure_width_mask_val); + is_error_irq = true; + report_err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE; + } + + } + + /* read the PPP errors */ + if (csid_reg->cmn_reg->num_ppp) { + /* PPP reset done bit */ + if (irq_status[TFE_CSID_IRQ_REG_PPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID PPP reset complete"); + complete(&csid_hw->csid_ppp_complete); + } + + if (irq_status[TFE_CSID_IRQ_REG_PPP] & TFE_CSID_PATH_INFO_INPUT_SOF) { + CAM_DBG(CAM_ISP, "CSID:%d PPP SOF received", csid_hw->hw_intf->hw_idx); + cam_tfe_csid_enable_path_for_init_frame_drop(csid_hw, + CAM_TFE_CSID_PATH_RES_PPP); + } + + if ((irq_status[TFE_CSID_IRQ_REG_PPP] & + TFE_CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ)) { + if (!csid_hw->sof_irq_triggered) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PPP SOF received", + csid_hw->hw_intf->hw_idx); + else + log_en = 1; + + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[TFE_CSID_IRQ_REG_PPP] & + TFE_CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP EOF received", + csid_hw->hw_intf->hw_idx); + } + + if (irq_status[TFE_CSID_IRQ_REG_PPP] & + TFE_CSID_PATH_ERROR_FIFO_OVERFLOW) { + /* Stop PPP path immediately */ + cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_ctrl_addr); + is_error_irq = true; + report_err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW; + } + + if (irq_status[TFE_CSID_IRQ_REG_PPP] & + TFE_CSID_PATH_PPP_ERROR_CCIF_VIOLATION) + is_error_irq = true; + + if (irq_status[TFE_CSID_IRQ_REG_PPP] & + (TFE_CSID_PATH_ERROR_PIX_COUNT | TFE_CSID_PATH_ERROR_LINE_COUNT)) { + ppp_reg = csid_reg->ppp_reg; + cmn_reg = csid_reg->cmn_reg; + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppp_reg->csid_pxl_format_measure0_addr); + val1 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppp_reg->csid_pxl_format_measure_cfg1_addr); + + CAM_ERR(CAM_ISP, + "Pix/Line count error for CSID: %d PPP path, Expected:: height: %d, width: %d and Actual:: height: %d width %d", + csid_hw->hw_intf->hw_idx, + ((val1 >> + cmn_reg->format_measure_height_shift_val) & + cmn_reg->format_measure_height_mask_val), + val1 & + cmn_reg->format_measure_width_mask_val, + ((val >> + cmn_reg->format_measure_height_shift_val) & + cmn_reg->format_measure_height_mask_val), + val & + cmn_reg->format_measure_width_mask_val); + is_error_irq = true; + report_err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE; } } @@ -3733,8 +4440,11 @@ handle_fatal_error: complete(&csid_hw->csid_rdin_complete[i]); } - if (irq_status[i] & TFE_CSID_PATH_INFO_INPUT_SOF) + if (irq_status[i] & TFE_CSID_PATH_INFO_INPUT_SOF) { + CAM_DBG(CAM_ISP, "CSID:%d RDI:%d SOF received", + csid_hw->hw_intf->hw_idx); cam_tfe_csid_enable_path_for_init_frame_drop(csid_hw, i); + } if ((irq_status[i] & TFE_CSID_PATH_INFO_INPUT_SOF) && (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ)) { @@ -3762,6 +4472,7 @@ handle_fatal_error: cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr); + report_err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW; } if ((irq_status[i] & TFE_CSID_PATH_RDI_OVERFLOW_IRQ) || @@ -3791,12 +4502,30 @@ handle_fatal_error: cmn_reg->format_measure_height_mask_val), val & cmn_reg->format_measure_width_mask_val); + + is_error_irq = true; + report_err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE; } } - if (is_error_irq || log_en) + if (is_error_irq || log_en) { + CAM_ERR(CAM_ISP, + "CSID %d irq status TOP: 0x%x RX: 0x%x IPP: 0x%x PPP: 0x%x", + csid_hw->hw_intf->hw_idx, + irq_status[TFE_CSID_IRQ_REG_TOP], + irq_status[TFE_CSID_IRQ_REG_RX], + irq_status[TFE_CSID_IRQ_REG_IPP], + irq_status[TFE_CSID_IRQ_REG_PPP]); + CAM_ERR(CAM_ISP, + "RDI0: 0x%x RDI1: 0x%x RDI2: 0x%x CSID clk:%d", + irq_status[TFE_CSID_IRQ_REG_RDI0], + irq_status[TFE_CSID_IRQ_REG_RDI1], + irq_status[TFE_CSID_IRQ_REG_RDI2], + soc_info->applied_src_clk_rates.sw_client); + cam_tfe_csid_handle_hw_err_irq(csid_hw, - CAM_ISP_HW_ERROR_NONE, irq_status); + report_err_type, irq_status); + } if (csid_hw->irq_debug_cnt >= CAM_TFE_CSID_IRQ_SOF_DEBUG_CNT_MAX) { cam_tfe_csid_sof_irq_debug(csid_hw, &sof_irq_debug_en); @@ -3815,6 +4544,7 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, struct cam_tfe_csid_path_cfg *path_data; struct cam_hw_info *csid_hw_info; struct cam_tfe_csid_hw *tfe_csid_hw = NULL; + struct cam_tfe_csid_soc_private *soc_private = NULL; const struct cam_tfe_csid_reg_offset *csid_reg; if (csid_idx >= CAM_TFE_CSID_HW_NUM_MAX) { @@ -3842,6 +4572,7 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, init_completion(&tfe_csid_hw->csid_top_complete); init_completion(&tfe_csid_hw->csid_csi2_complete); init_completion(&tfe_csid_hw->csid_ipp_complete); + init_completion(&tfe_csid_hw->csid_ppp_complete); for (i = 0; i < CAM_TFE_CSID_RDI_MAX; i++) init_completion(&tfe_csid_hw->csid_rdin_complete[i]); @@ -3864,6 +4595,8 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, goto err; } + soc_private = (struct cam_tfe_csid_soc_private *) csid_hw_info->soc_info.soc_private; + tfe_csid_hw->hw_intf->hw_ops.get_hw_caps = cam_tfe_csid_get_hw_caps; tfe_csid_hw->hw_intf->hw_ops.init = cam_tfe_csid_init_hw; tfe_csid_hw->hw_intf->hw_ops.deinit = cam_tfe_csid_deinit_hw; @@ -3910,7 +4643,7 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, csid_reg->cmn_reg->top_tfe2_pix_pipe_fuse_reg); /* Initialize the IPP resources */ - if (!(val && (tfe_csid_hw->hw_intf->hw_idx == 2))) { + if (!soc_private->is_tfe_csid_lite && !(val && (tfe_csid_hw->hw_intf->hw_idx == 2))) { CAM_DBG(CAM_ISP, "initializing the pix path"); tfe_csid_hw->ipp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; @@ -3928,6 +4661,24 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, tfe_csid_hw->pxl_pipe_enable = 1; } + /* Initialize the PPP resources */ + if (tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_ppp) { + CAM_DBG(CAM_ISP, "initializing the ppp path"); + + tfe_csid_hw->ppp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; + tfe_csid_hw->ppp_res.res_id = CAM_TFE_CSID_PATH_RES_PPP; + tfe_csid_hw->ppp_res.res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + tfe_csid_hw->ppp_res.hw_intf = tfe_csid_hw->hw_intf; + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + tfe_csid_hw->ppp_res.res_priv = path_data; + } + /* Initialize the RDI resource */ for (i = 0; i < tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; i++) { @@ -3995,6 +4746,8 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, err: if (rc) { kfree(tfe_csid_hw->ipp_res.res_priv); + if (tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_ppp) + kfree(tfe_csid_hw->ppp_res.res_priv); for (i = 0; i < tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; i++) @@ -4018,6 +4771,9 @@ int cam_tfe_csid_hw_deinit(struct cam_tfe_csid_hw *tfe_csid_hw) /* release the privdate data memory from resources */ kfree(tfe_csid_hw->ipp_res.res_priv); + if (tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_ppp) + kfree(tfe_csid_hw->ppp_res.res_priv); + for (i = 0; i < tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; i++) { diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index eef95c19a3..5d4ce961f4 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_TFE_CSID_HW_H_ @@ -55,11 +56,14 @@ #define TFE_CSID_PATH_ERROR_PIX_COUNT BIT(13) #define TFE_CSID_PATH_ERROR_LINE_COUNT BIT(14) #define TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION BIT(15) -#define TFE_CSID_PATH_IPP_OVERFLOW_IRQ BIT(16) -#define TFE_CSID_PATH_IPP_FRAME_DROP BIT(17) +#define TFE_CSID_PATH_IPP_FRAME_DROP BIT(16) +#define TFE_CSID_PATH_IPP_OVERFLOW_IRQ BIT(17) +#define TFE_CSID_PATH_PPP_ERROR_CCIF_VIOLATION BIT(15) +#define TFE_CSID_PATH_PPP_FRAME_DROP BIT(16) +#define TFE_CSID_PATH_PPP_OVERFLOW_IRQ BIT(17) +#define TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION BIT(15) #define TFE_CSID_PATH_RDI_FRAME_DROP BIT(16) #define TFE_CSID_PATH_RDI_OVERFLOW_IRQ BIT(17) -#define TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION BIT(18) /* * Debug values enable the corresponding interrupts and debug logs provide @@ -94,6 +98,14 @@ enum cam_tfe_csid_path_halt_mode { TFE_CSID_HALT_MODE_SLAVE, }; +/* enum cam_csid_path_halt_master select the path halt master control */ +enum cam_tfe_csid_path_halt_master_sel { + TFE_CSID_HALT_CMD_SOURCE_EXTERNAL, + TFE_CSID_HALT_CMD_SOURCE_NONE, + TFE_CSID_HALT_CMD_SOURCE_INTERNAL2, + TFE_CSID_HALT_CMD_SOURCE_INTERNAL1, +}; + /** *enum cam_csid_path_timestamp_stb_sel - select the sof/eof strobes used to * capture the timestamp @@ -115,11 +127,20 @@ struct cam_tfe_csid_pxl_reg_offset { uint32_t csid_pxl_cfg0_addr; uint32_t csid_pxl_cfg1_addr; uint32_t csid_pxl_ctrl_addr; + uint32_t csid_pxl_frame_drop_pattern; + uint32_t csid_pxl_frame_drop_period; + uint32_t csid_pxl_irq_subsample_pattern; + uint32_t csid_pxl_irq_subsample_period; uint32_t csid_pxl_hcrop_addr; uint32_t csid_pxl_vcrop_addr; uint32_t csid_pxl_rst_strobes_addr; uint32_t csid_pxl_status_addr; uint32_t csid_pxl_misr_val_addr; + uint32_t csid_pxl_format_measure_cfg0_addr; + uint32_t csid_pxl_format_measure_cfg1_addr; + uint32_t csid_pxl_format_measure0_addr; + uint32_t csid_pxl_format_measure1_addr; + uint32_t csid_pxl_format_measure2_addr; uint32_t csid_pxl_timestamp_curr0_sof_addr; uint32_t csid_pxl_timestamp_curr1_sof_addr; uint32_t csid_pxl_timestamp_perv0_sof_addr; @@ -128,21 +149,19 @@ struct cam_tfe_csid_pxl_reg_offset { uint32_t csid_pxl_timestamp_curr1_eof_addr; uint32_t csid_pxl_timestamp_perv0_eof_addr; uint32_t csid_pxl_timestamp_perv1_eof_addr; + uint32_t csid_pxl_ppp_sparse_pd_ext_cfg0; uint32_t csid_pxl_err_recovery_cfg0_addr; uint32_t csid_pxl_err_recovery_cfg1_addr; uint32_t csid_pxl_err_recovery_cfg2_addr; uint32_t csid_pxl_multi_vcdt_cfg0_addr; - uint32_t csid_pxl_format_measure_cfg0_addr; - uint32_t csid_pxl_format_measure_cfg1_addr; - uint32_t csid_pxl_format_measure0_addr; - uint32_t csid_pxl_format_measure1_addr; - uint32_t csid_pxl_format_measure2_addr; /* configuration */ uint32_t pix_store_en_shift_val; uint32_t early_eof_en_shift_val; uint32_t halt_master_sel_shift; uint32_t halt_mode_shift; + uint32_t halt_mode_mask; + uint32_t halt_cmd_shift; uint32_t halt_master_sel_master_val; uint32_t halt_master_sel_slave_val; uint32_t binning_supported; @@ -151,6 +170,7 @@ struct cam_tfe_csid_pxl_reg_offset { uint32_t format_measure_en_shift_val; uint32_t measure_en_hbi_vbi_cnt_val; bool is_multi_vc_dt_supported; + uint32_t cgc_mode_en_shift_val; }; struct cam_tfe_csid_rdi_reg_offset { @@ -163,10 +183,21 @@ struct cam_tfe_csid_rdi_reg_offset { uint32_t csid_rdi_cfg0_addr; uint32_t csid_rdi_cfg1_addr; uint32_t csid_rdi_ctrl_addr; + uint32_t csid_rdi_frame_drop_pattern; + uint32_t csid_rdi_frame_drop_period; + uint32_t csid_rdi_irq_subsample_pattern; + uint32_t csid_rdi_irq_subsample_period; uint32_t csid_rdi_rst_strobes_addr; uint32_t csid_rdi_status_addr; uint32_t csid_rdi_misr_val0_addr; uint32_t csid_rdi_misr_val1_addr; + uint32_t csid_rdi_misr_val2_addr; + uint32_t csid_rdi_misr_val3_addr; + uint32_t csid_rdi_format_measure_cfg0_addr; + uint32_t csid_rdi_format_measure_cfg1_addr; + uint32_t csid_rdi_format_measure0_addr; + uint32_t csid_rdi_format_measure1_addr; + uint32_t csid_rdi_format_measure2_addr; uint32_t csid_rdi_timestamp_curr0_sof_addr; uint32_t csid_rdi_timestamp_curr1_sof_addr; uint32_t csid_rdi_timestamp_prev0_sof_addr; @@ -181,17 +212,13 @@ struct cam_tfe_csid_rdi_reg_offset { uint32_t csid_rdi_byte_cntr_ping_addr; uint32_t csid_rdi_byte_cntr_pong_addr; uint32_t csid_rdi_multi_vcdt_cfg0_addr; - uint32_t csid_rdi_format_measure_cfg0_addr; - uint32_t csid_rdi_format_measure_cfg1_addr; - uint32_t csid_rdi_format_measure0_addr; - uint32_t csid_rdi_format_measure1_addr; - uint32_t csid_rdi_format_measure2_addr; /* configuration */ uint32_t packing_format; uint32_t format_measure_en_shift_val; uint32_t measure_en_hbi_vbi_cnt_val; bool is_multi_vc_dt_supported; + uint32_t cgc_mode_en_shift_val; }; struct cam_tfe_csid_csi2_rx_reg_offset { @@ -223,6 +250,7 @@ struct cam_tfe_csid_csi2_rx_reg_offset { uint32_t csi2_irq_mask_all; uint32_t csi2_misr_enable_shift_val; uint32_t csi2_vc_mode_shift_val; + uint32_t csi2_rx_epd_mode_shift_en; uint32_t csi2_capture_long_pkt_en_shift; uint32_t csi2_capture_short_pkt_en_shift; uint32_t csi2_capture_cphy_pkt_en_shift; @@ -235,6 +263,7 @@ struct cam_tfe_csid_csi2_rx_reg_offset { uint32_t csi2_rx_long_pkt_hdr_rst_stb_shift; uint32_t csi2_rx_short_pkt_hdr_rst_stb_shift; uint32_t csi2_rx_cphy_pkt_hdr_rst_stb_shift; + bool need_to_sel_tpg_mux; }; struct cam_tfe_csid_common_reg_offset { @@ -257,10 +286,12 @@ struct cam_tfe_csid_common_reg_offset { uint32_t version_incr; uint32_t num_rdis; uint32_t num_pix; + uint32_t num_ppp; uint32_t csid_reg_rst_stb; uint32_t csid_rst_stb; uint32_t csid_rst_stb_sw_all; uint32_t ipp_path_rst_stb_all; + uint32_t ppp_path_rst_stb_all; uint32_t rdi_path_rst_stb_all; uint32_t path_rst_done_shift_val; uint32_t path_en_shift_val; @@ -276,6 +307,7 @@ struct cam_tfe_csid_common_reg_offset { uint32_t crop_h_en_shift_val; uint32_t crop_shift; uint32_t ipp_irq_mask_all; + uint32_t ppp_irq_mask_all; uint32_t rdi_irq_mask_all; uint32_t top_tfe2_pix_pipe_fuse_reg; uint32_t top_tfe2_fuse_reg; @@ -283,6 +315,7 @@ struct cam_tfe_csid_common_reg_offset { uint32_t format_measure_height_mask_val; uint32_t format_measure_width_mask_val; bool format_measure_support; + bool sync_clk; }; /** @@ -298,9 +331,37 @@ struct cam_tfe_csid_reg_offset { const struct cam_tfe_csid_common_reg_offset *cmn_reg; const struct cam_tfe_csid_csi2_rx_reg_offset *csi2_reg; const struct cam_tfe_csid_pxl_reg_offset *ipp_reg; + const struct cam_tfe_csid_pxl_reg_offset *ppp_reg; const struct cam_tfe_csid_rdi_reg_offset *rdi_reg[CAM_TFE_CSID_RDI_MAX]; }; +/** + * struct cam_tfe_csid_secure_info: Contains all relevant info to be + * programmed for targets supporting + * this feature + * @phy_sel: Intermediate value for this mask. CSID passes + * phy_sel.This variable's position at the top is to + * be left unchanged, to have it be used correctly + * in the cam_subdev_notify_message callback for + * csiphy + * @lane_cfg: This value is similar to lane_assign in the PHY + * driver, and is used to identify the particular + * PHY instance with which this IFE session is + * connected to. + * @vc_mask: Virtual channel masks (Unused for mobile usecase) + * @csid_hw_idx_mask: Bit position denoting CSID(s) in use for secure + * session + * @cdm_hw_idx_mask: Bit position denoting CDM in use for secure + * session + */ +struct cam_tfe_csid_secure_info { + uint32_t phy_sel; + uint32_t lane_cfg; + uint64_t vc_mask; + uint32_t csid_hw_idx_mask; + uint32_t cdm_hw_idx_mask; +}; + /** * struct cam_tfe_csid_hw_info- CSID HW info * @@ -317,10 +378,11 @@ struct cam_tfe_csid_hw_info { /** * struct cam_tfe_csid_csi2_rx_cfg- csid csi2 rx configuration data - * @phy_sel: input resource type for sensor only - * @lane_type: lane type: c-phy or d-phy - * @lane_num : active lane number - * @lane_cfg: lane configurations: 4 bits per lane + * @phy_sel: input resource type for sensor only + * @lane_type: lane type: c-phy or d-phy + * @lane_num : active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * @epd_supported: Flag to check if epd supported * */ struct cam_tfe_csid_csi2_rx_cfg { @@ -328,6 +390,7 @@ struct cam_tfe_csid_csi2_rx_cfg { uint32_t lane_type; uint32_t lane_num; uint32_t lane_cfg; + uint32_t epd_supported; }; /** @@ -392,7 +455,8 @@ struct cam_tfe_csid_cid_data { * one more frame than pix. * @res_sof_cnt path resource sof count value. it used for initial * frame drop - * + * @is_shdr_master flag to indicate path to be shdr master + * @is_shdr flag to indicate if shdr mode is enabled */ struct cam_tfe_csid_path_cfg { struct vc_dt_data vc_dt[CAM_ISP_TFE_VC_DT_CFG]; @@ -420,6 +484,8 @@ struct cam_tfe_csid_path_cfg { uint32_t usage_type; uint32_t init_frame_drop; uint32_t res_sof_cnt; + bool is_shdr_master; + bool is_shdr; }; /** @@ -450,13 +516,14 @@ struct cam_csid_evt_payload { * @in_res_id: csid in resource type * @csi2_rx_cfg: csi2 rx decoder configuration for csid * @csi2_rx_reserve_cnt: csi2 reservations count value + * pxl_pipe_enable: flag to specify if the hardware has IPP * @ipp_res: image pixel path resource + * @ppp_res: PD pixel path resource * @rdi_res: raw dump image path resources * @cid_res: cid resources values * @csid_top_reset_complete: csid top reset completion * @csid_csi2_reset_complete: csi2 reset completion * @csid_ipp_reset_complete: ipp reset completion - * @csid_ppp_complete: ppp reset completion * @csid_rdin_reset_complete: rdi n completion * @csid_debug: csid debug information to enable the SOT, EOT, * SOF, EOF, measure etc in the csid hw @@ -477,6 +544,8 @@ struct cam_csid_evt_payload { * or not * @prev_boot_timestamp previous frame bootime stamp * @prev_qtimer_ts previous frame qtimer csid timestamp + * @sync_clk sync clocks such that freq(TFE)>freq(CSID)>freq(CSIPHY) + * @is_secure Flag to denote secure operation * */ struct cam_tfe_csid_hw { @@ -491,11 +560,13 @@ struct cam_tfe_csid_hw { uint32_t csi2_reserve_cnt; uint32_t pxl_pipe_enable; struct cam_isp_resource_node ipp_res; + struct cam_isp_resource_node ppp_res; struct cam_isp_resource_node rdi_res[CAM_TFE_CSID_RDI_MAX]; struct cam_tfe_csid_cid_data cid_res[CAM_TFE_CSID_CID_MAX]; struct completion csid_top_complete; struct completion csid_csi2_complete; struct completion csid_ipp_complete; + struct completion csid_ppp_complete; struct completion csid_rdin_complete[CAM_TFE_CSID_RDI_MAX]; uint64_t csid_debug; uint64_t clk_rate; @@ -511,6 +582,8 @@ struct cam_tfe_csid_hw { bool ppi_enable; uint64_t prev_boot_timestamp; uint64_t prev_qtimer_ts; + bool sync_clk; + bool is_secure; }; int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c index d4dde1a8fd..662ccfe61d 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c @@ -1,16 +1,19 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include #include +#include #include "cam_tfe_csid_core.h" #include "cam_tfe_csid_dev.h" #include "cam_tfe_csid_hw_intf.h" #include "cam_debug_util.h" #include "camera_main.h" +#include "cam_cpas_api.h" static struct cam_hw_intf *cam_tfe_csid_hw_list[CAM_TFE_CSID_HW_NUM_MAX] = { 0, 0, 0}; @@ -24,12 +27,25 @@ static int cam_tfe_csid_component_bind(struct device *dev, struct cam_tfe_csid_hw *csid_dev = NULL; const struct of_device_id *match_dev = NULL; struct cam_tfe_csid_hw_info *csid_hw_data = NULL; - uint32_t csid_dev_idx; + uint32_t csid_dev_idx = 0; int rc = 0; struct platform_device *pdev = to_platform_device(dev); CAM_DBG(CAM_ISP, "probe called"); + /* get tfe csid hw index */ + rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to read cell-index of TFE CSID HW, rc: %d", rc); + goto err; + } + + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_FUSE, BIT(csid_dev_idx), NULL) || + !cam_cpas_is_feature_supported(CAM_CPAS_ISP_LITE_FUSE, BIT(csid_dev_idx), NULL)) { + CAM_DBG(CAM_ISP, "CSID[%d] not supported based on fuse", csid_dev_idx); + goto err; + } + csid_hw_intf = kzalloc(sizeof(*csid_hw_intf), GFP_KERNEL); if (!csid_hw_intf) { rc = -ENOMEM; @@ -48,8 +64,6 @@ static int cam_tfe_csid_component_bind(struct device *dev, goto free_hw_info; } - /* get tfe csid hw index */ - of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); /* get tfe csid hw information */ match_dev = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev); @@ -107,6 +121,12 @@ void cam_tfe_csid_component_unbind(struct device *dev, struct platform_device *pdev = to_platform_device(dev); csid_dev = (struct cam_tfe_csid_hw *)platform_get_drvdata(pdev); + + if (!csid_dev) { + CAM_ERR(CAM_ISP, "Error No data in csid_dev"); + return; + } + csid_hw_intf = csid_dev->hw_intf; csid_hw_info = csid_dev->hw_info; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c index 22da4054ae..515f492537 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c @@ -24,7 +24,6 @@ int cam_tfe_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, soc_info->soc_private = soc_private; - rc = cam_soc_util_get_dt_properties(soc_info); if (rc < 0) return rc; @@ -32,6 +31,10 @@ int cam_tfe_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, for (i = 0; i < soc_info->irq_count; i++) irq_data[i] = data; + soc_private->is_tfe_csid_lite = false; + if (strnstr(soc_info->compatible, "lite", strlen(soc_info->compatible)) != NULL) + soc_private->is_tfe_csid_lite = true; + /* Need to see if we want post process the clock list */ rc = cam_soc_util_request_platform_resource(soc_info, csid_irq_handler, &(irq_data[0])); if (rc < 0) { diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h index 98f7a909ee..77182a0c2a 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_TFE_CSID_SOC_H_ @@ -16,9 +17,11 @@ * @cpas_handle: Handle returned on registering with CPAS driver. * This handle is used for all further interface * with CPAS. + * @is_tfe_csid_lite: Flag to indicate if it is CSID lite HW */ struct cam_tfe_csid_soc_private { uint32_t cpas_handle; + bool is_tfe_csid_lite; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c index 33999c4b95..b92417b1db 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c @@ -1,11 +1,16 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include "cam_tfe530.h" #include "cam_tfe640.h" +#include "cam_tfe640_210.h" +#include "cam_tfe770.h" +#include "cam_tfe_lite770.h" +#include "cam_tfe665.h" #include "cam_tfe_hw_intf.h" #include "cam_tfe_core.h" #include "cam_tfe_dev.h" @@ -20,6 +25,22 @@ static const struct of_device_id cam_tfe_dt_match[] = { .compatible = "qcom,tfe640", .data = &cam_tfe640, }, + { + .compatible = "qcom,tfe640_210", + .data = &cam_tfe640_210, + }, + { + .compatible = "qcom,tfe770", + .data = &cam_tfe770, + }, + { + .compatible = "qcom,tfe-lite770", + .data = &cam_tfe_lite770, + }, + { + .compatible = "qcom,tfe665", + .data = &cam_tfe665, + }, {} }; MODULE_DEVICE_TABLE(of, cam_tfe_dt_match); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h index 19982cb03e..c0ac558c6e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h @@ -18,7 +18,7 @@ static struct cam_tfe_top_reg_offset_common tfe530_top_commong_reg = { .stats_feature = 0x0000100C, .zoom_feature = 0x00001010, .global_reset_cmd = 0x00001014, - .core_cgc_ctrl = 0x00001018, + .core_cgc_ctrl_0 = 0x00001018, .ahb_cgc_ctrl = 0x0000101C, .core_cfg_0 = 0x00001024, .core_cfg_1 = 0x00001028, @@ -53,6 +53,24 @@ static struct cam_tfe_top_reg_offset_common tfe530_top_commong_reg = { .diag_neq_hbi_shift = 14, .diag_sensor_hbi_mask = 0x3FFF, .serializer_supported = false, + .pp_camif_violation_bit = BIT(0), + .pp_violation_bit = BIT(1), + .rdi0_camif_violation_bit = BIT(2), + .rdi1_camif_violation_bit = BIT(3), + .rdi2_camif_violation_bit = BIT(4), + .diag_violation_bit = BIT(5), + .pp_frame_drop_bit = BIT(8), + .rdi0_frame_drop_bit = BIT(9), + .rdi1_frame_drop_bit = BIT(10), + .rdi2_frame_drop_bit = BIT(11), + .pp_overflow_bit = BIT(16), + .rdi0_overflow_bit = BIT(17), + .rdi1_overflow_bit = BIT(18), + .rdi2_overflow_bit = BIT(19), + .mup_shift_val = 0, + .mup_supported = false, + .height_shift = 16, + .epoch_shift_val = 16, }; static struct cam_tfe_camif_reg tfe530_camif_reg = { @@ -220,7 +238,6 @@ static struct cam_tfe_rdi_reg_data tfe530_rdi2_reg_data = { .enable_diagnostic_hw = 0x1, .diag_sensor_sel = 0x3, .diag_sensor_shift = 0x1, - }; static struct cam_tfe_clc_hw_status tfe530_clc_hw_info[CAM_TFE_MAX_CLC] = { @@ -859,6 +876,8 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .max_bw_counter_limit = 0xFF, .counter_limit_shift = 1, .counter_limit_mask = 0xF, + .mode_cfg_shift = 16, + .height_shift = 16, }; struct cam_tfe_hw_info cam_tfe530 = { diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640.h index 9b60c47491..1f85637a72 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640.h @@ -18,7 +18,7 @@ static struct cam_tfe_top_reg_offset_common tfe640_top_commong_reg = { .stats_feature = 0x0000180C, .zoom_feature = 0x00001810, .global_reset_cmd = 0x00001814, - .core_cgc_ctrl = 0x00001818, + .core_cgc_ctrl_0 = 0x00001818, .ahb_cgc_ctrl = 0x0000181C, .core_cfg_0 = 0x00001824, .reg_update_cmd = 0x0000182C, @@ -66,6 +66,24 @@ static struct cam_tfe_top_reg_offset_common tfe640_top_commong_reg = { .diag_neq_hbi_shift = 14, .diag_sensor_hbi_mask = 0x3FFF, .serializer_supported = true, + .pp_camif_violation_bit = BIT(0), + .pp_violation_bit = BIT(1), + .rdi0_camif_violation_bit = BIT(2), + .rdi1_camif_violation_bit = BIT(3), + .rdi2_camif_violation_bit = BIT(4), + .diag_violation_bit = BIT(5), + .pp_frame_drop_bit = BIT(8), + .rdi0_frame_drop_bit = BIT(9), + .rdi1_frame_drop_bit = BIT(10), + .rdi2_frame_drop_bit = BIT(11), + .pp_overflow_bit = BIT(16), + .rdi0_overflow_bit = BIT(17), + .rdi1_overflow_bit = BIT(18), + .rdi2_overflow_bit = BIT(19), + .mup_shift_val = 0, + .mup_supported = false, + .height_shift = 16, + .epoch_shift_val = 16, }; static struct cam_tfe_camif_reg tfe640_camif_reg = { @@ -235,7 +253,6 @@ static struct cam_tfe_rdi_reg_data tfe640_rdi2_reg_data = { .enable_diagnostic_hw = 0x1, .diag_sensor_sel = 0x3, .diag_sensor_shift = 0x1, - }; static struct cam_tfe_clc_hw_status tfe640_clc_hw_info[CAM_TFE_MAX_CLC] = { @@ -1175,6 +1192,8 @@ static struct cam_tfe_bus_hw_info tfe640_bus_hw_info = { .max_bw_counter_limit = 0xFF, .counter_limit_shift = 1, .counter_limit_mask = 0xF, + .mode_cfg_shift = 16, + .height_shift = 16, }; struct cam_tfe_hw_info cam_tfe640 = { diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h new file mode 100644 index 0000000000..e2fa7b3836 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#ifndef _CAM_TFE640_210_H_ +#define _CAM_TFE640_210_H_ +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" +#include "cam_tfe640.h" + +struct cam_tfe_hw_info cam_tfe640_210 = { + .top_irq_mask = { + 0x00001834, + 0x00001838, + 0x0000183C, + }, + .top_irq_clear = { + 0x00001840, + 0x00001844, + 0x00001848, + }, + .top_irq_status = { + 0x0000184C, + 0x00001850, + 0x00001854, + }, + .top_irq_cmd = 0x00001830, + .global_clear_bitmask = 0x00000001, + .bus_irq_mask = { + 0x00003018, + 0x0000301C, + }, + .bus_irq_clear = { + 0x00003020, + 0x00003024, + }, + .bus_irq_status = { + 0x00003028, + 0x0000302C, + }, + .bus_irq_cmd = 0x00003030, + .bus_violation_reg = 0x00003064, + .bus_overflow_reg = 0x00003068, + .bus_image_size_vilation_reg = 0x3070, + .bus_overflow_clear_cmd = 0x3060, + .debug_status_top = 0x30D8, + + .reset_irq_mask = { + 0x00000001, + 0x00000000, + 0x00000000, + }, + .error_irq_mask = { + 0x000F0F00, + 0x00000000, + 0x0000003F, + }, + .bus_reg_irq_mask = { + 0x00000002, + 0x00000000, + }, + .bus_error_irq_mask = { + 0xC0000000, + 0x00000000, + }, + + .num_clc = 39, + .clc_hw_status_info = tfe640_clc_hw_info, + .bus_version = CAM_TFE_BUS_1_0, + .bus_hw_info = &tfe640_bus_hw_info, + + .top_version = CAM_TFE_TOP_1_0, + .top_hw_info = &tfe640_top_hw_info, +}; + +#endif /* _CAM_TFE640_210_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe665.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe665.h new file mode 100644 index 0000000000..ff0e96b6ce --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe665.h @@ -0,0 +1,1476 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#ifndef _CAM_TFE665_H_ +#define _CAM_TFE665_H_ +#include +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" + + +static struct cam_tfe_top_reg_offset_common tfe665_top_commong_reg = { + .hw_version = 0x00001800, + .hw_capability = 0x00001804, + .lens_feature = 0x00001808, + .stats_feature = 0x0000180C, + .zoom_feature = 0x00001810, + .global_reset_cmd = 0x00001814, + .core_cgc_ctrl_0 = 0x00001818, + .core_cgc_ctrl_1 = 0x0000181C, + .ahb_cgc_ctrl = 0x0000181C, + .core_cfg_0 = 0x00001824, + .reg_update_cmd = 0x0000182C, + .diag_config = 0x00001860, + .diag_sensor_status_0 = 0x00001864, + .diag_sensor_status_1 = 0x00001868, + .diag_sensor_frame_cnt_status = 0x0000186C, + .violation_status = 0x00001870, + .stats_throttle_cnt_cfg_0 = 0x00001874, + .stats_throttle_cnt_cfg_1 = 0x00001878, + .num_debug_reg = 12, + .debug_reg = { + 0x000018A0, + 0x000018A4, + 0x000018A8, + 0x000018AC, + 0x000018B0, + 0x000018B4, + 0x000018B8, + 0x000018BC, + 0x000018C0, + 0x000018C4, + 0x000018C8, + 0x000018CC, + }, + .debug_cfg = 0x000018DC, + .num_perf_cfg = 2, + .perf_cfg = { + { + .perf_cnt_cfg = 0x000018E0, + .perf_pixel_count = 0x000018E4, + .perf_line_count = 0x000018E8, + .perf_stall_count = 0x000018EC, + .perf_always_count = 0x000018F0, + .perf_count_status = 0x000018F4, + }, + { + .perf_cnt_cfg = 0x000018F8, + .perf_pixel_count = 0x000018FC, + .perf_line_count = 0x00001900, + .perf_stall_count = 0x00001904, + .perf_always_count = 0x00001908, + .perf_count_status = 0x0000190C, + }, + }, + .diag_sensor_frame_cnt_status_1 = 0x00001920, + .diag_min_hbi_error_shift = 15, + .diag_neq_hbi_shift = 14, + .diag_sensor_hbi_mask = 0x3FFF, + .serializer_supported = true, + .pp_camif_violation_bit = BIT(0), + .pp_violation_bit = BIT(1), + .rdi0_camif_violation_bit = BIT(2), + .rdi1_camif_violation_bit = BIT(3), + .rdi2_camif_violation_bit = BIT(4), + .diag_violation_bit = BIT(5), + .ppp_camif_violation_bit = BIT(6), + .ppp_violation_bit = BIT(7), + .lcr_pd_timing_protocol_violation_bit = BIT(8), + .dyamanic_switch_violation_bit = BIT(9), + .pp_frame_drop_bit = BIT(8), + .rdi0_frame_drop_bit = BIT(9), + .rdi1_frame_drop_bit = BIT(10), + .rdi2_frame_drop_bit = BIT(11), + .ppp_frame_drop_bit = BIT(12), + .pp_overflow_bit = BIT(16), + .rdi0_overflow_bit = BIT(17), + .rdi1_overflow_bit = BIT(18), + .rdi2_overflow_bit = BIT(19), + .ppp_overflow_bit = BIT(20), + .out_of_sync_frame_drop_bit = BIT(21), + .mup_shift_val = 8, + .mup_supported = true, + .height_shift = 16, + .epoch_shift_val = 16, +}; + +static struct cam_tfe_camif_reg tfe665_camif_reg = { + .hw_version = 0x00001C00, + .hw_status = 0x00001C04, + .module_cfg = 0x00001C60, + .pdaf_raw_crop_width_cfg = 0x00001C68, + .pdaf_raw_crop_height_cfg = 0x00001C6C, + .line_skip_pattern = 0x00001C70, + .pixel_skip_pattern = 0x00001C74, + .period_cfg = 0x00001C78, + .irq_subsample_pattern = 0x00001C7C, + .epoch_irq_cfg = 0x00001C80, + .debug_1 = 0x00001DF0, + .debug_0 = 0x00001DF4, + .test_bus_ctrl = 0x00001DF8, + .spare = 0x00001DFC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_camif_reg_data tfe665_camif_reg_data = { + .extern_reg_update_mask = 0x00000001, + .dual_tfe_pix_en_shift = 0x00000001, + .extern_reg_update_shift = 0x0, + .dual_tfe_sync_sel_shift = 18, + .delay_line_en_shift = 8, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x7000000, + .module_enable_shift = 0, + .pix_out_enable_shift = 8, + .pdaf_output_enable_shift = 9, + .dsp_mode_shift = 0, + .dsp_mode_mask = 0, + .dsp_en_shift = 0, + .dsp_en_mask = 0, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .epoch1_irq_mask = 0x00000008, + .eof_irq_mask = 0x00000002, + .reg_update_irq_mask = 0x00000001, + .error_irq_mask0 = 0x00210100, + .error_irq_mask2 = 0x00000223, + .subscribe_irq_mask = { + 0x00000000, + 0x00000007, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .perf_cnt_start_cmd_shift = 0, + .perf_cnt_continuous_shift = 2, + .perf_client_sel_shift = 8, + .perf_window_start_shift = 16, + .perf_window_end_shift = 20, + .ai_c_srl_en_shift = 11, + .ds16_c_srl_en_shift = 10, + .ds4_c_srl_en_shift = 9, + .shdr_mode_shift = 21, + .extern_mup_shift = 22, +}; + +static struct cam_tfe_rdi_reg tfe665_rdi0_reg = { + .rdi_hw_version = 0x00001E00, + .rdi_hw_status = 0x00001E04, + .rdi_module_config = 0x00001E60, + .rdi_skip_period = 0x00001E68, + .rdi_irq_subsample_pattern = 0x00001E6C, + .rdi_epoch_irq = 0x00001E70, + .rdi_debug_1 = 0x00001FF0, + .rdi_debug_0 = 0x00001FF4, + .rdi_test_bus_ctrl = 0x00001FF8, + .rdi_spare = 0x00001FFC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe665_rdi0_reg_data = { + .reg_update_cmd_data = 0x2, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000010, + .epoch0_irq_mask = 0x00000040, + .epoch1_irq_mask = 0x00000080, + .eof_irq_mask = 0x00000020, + .error_irq_mask0 = 0x00020200, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00000030, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x1, + .diag_sensor_shift = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe665_rdi1_reg = { + .rdi_hw_version = 0x00002000, + .rdi_hw_status = 0x00002004, + .rdi_module_config = 0x00002060, + .rdi_skip_period = 0x00002068, + .rdi_irq_subsample_pattern = 0x0000206C, + .rdi_epoch_irq = 0x00002070, + .rdi_debug_1 = 0x000021F0, + .rdi_debug_0 = 0x000021F4, + .rdi_test_bus_ctrl = 0x000021F8, + .rdi_spare = 0x000021FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe665_rdi1_reg_data = { + .reg_update_cmd_data = 0x4, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000100, + .epoch0_irq_mask = 0x00000400, + .epoch1_irq_mask = 0x00000800, + .eof_irq_mask = 0x00000200, + .error_irq_mask0 = 0x00040400, + .error_irq_mask2 = 0x00000008, + .subscribe_irq_mask = { + 0x00000000, + 0x00000300, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x2, + .diag_sensor_shift = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe665_rdi2_reg = { + .rdi_hw_version = 0x00002200, + .rdi_hw_status = 0x00002204, + .rdi_module_config = 0x00002260, + .rdi_skip_period = 0x00002268, + .rdi_irq_subsample_pattern = 0x0000226C, + .rdi_epoch_irq = 0x00002270, + .rdi_debug_1 = 0x000023F0, + .rdi_debug_0 = 0x000023F4, + .rdi_test_bus_ctrl = 0x000023F8, + .rdi_spare = 0x000023FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe665_rdi2_reg_data = { + .reg_update_cmd_data = 0x8, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00001000, + .epoch0_irq_mask = 0x00004000, + .epoch1_irq_mask = 0x00008000, + .eof_irq_mask = 0x00002000, + .error_irq_mask0 = 0x00080800, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00003000, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x3, + .diag_sensor_shift = 0x1, + +}; + +static struct cam_tfe_ppp_reg tfe665_ppp_reg = { + .ppp_hw_version = 0x00002400, + .ppp_hw_status = 0x00002404, + .ppp_module_config = 0x00002460, + .ppp_skip_period = 0x00002468, + .ppp_irq_subsample_pattern = 0x0000246C, + .ppp_epoch_irq = 0x00002470, + .ppp_debug_1 = 0x000025F0, + .ppp_debug_0 = 0x000025F4, + .ppp_test_bus_ctrl = 0x000025F8, + .ppp_spare = 0x000025FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_ppp_reg_data tfe665_ppp_reg_data = { + .sof_irq_mask = 0x00000000, + .epoch0_irq_mask = 0x00000000, + .epoch1_irq_mask = 0x00000000, + .eof_irq_mask = 0x00000000, + .subscribe_irq_mask = { + 0x00000000, + 0x00000000, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x4, + .diag_sensor_shift = 0x1, + .pdaf_path_en_shift = 24, + .lcr_dis_en_shift = 23, +}; + +static struct cam_tfe_clc_hw_status tfe665_clc_hw_info[CAM_TFE_MAX_CLC] = { + { + .name = "CLC_CAMIF", + .hw_status_reg = 0x1C04, + }, + { + .name = "CLC_RDI0_CAMIF", + .hw_status_reg = 0x1E04, + }, + { + .name = "CLC_RDI1_CAMIF", + .hw_status_reg = 0x2004, + }, + { + .name = "CLC_RDI2_CAMIF", + .hw_status_reg = 0x2204, + }, + { + .name = "CLC_PD_CAMIF", + .hw_status_reg = 0x2404, + }, + { + .name = "CLC_PDAF_LITE", + .hw_status_reg = 0x2A04, + }, + { + .name = "CLC_CHANNEL_GAIN", + .hw_status_reg = 0x6004, + }, + { + .name = "CLC_BPC_PDPC", + .hw_status_reg = 0x6204, + }, + { + .name = "CLC_LCS", + .hw_status_reg = 0x6404, + }, + { + .name = "CLC_SHARED_LB", + .hw_status_reg = 0x6604, + }, + { + .name = "CLC_WB_BDS", + .hw_status_reg = 0x6804, + }, + { + .name = "CLC_CROP_RND_CLAMP_POST_BDS", + .hw_status_reg = 0x6A04, + }, + { + .name = "CLC_BLS", + .hw_status_reg = 0x6C04, + }, + { + .name = "CLC_BAYER_GLUT", + .hw_status_reg = 0x6E04, + }, + { + .name = "CLC_BAYER_DS4", + .hw_status_reg = 0x7004, + }, + { + .name = "CLC_COLOR_XFORM_DS4", + .hw_status_reg = 0x7204, + }, + { + .name = "CLC_CHROMA_DS2", + .hw_status_reg = 0x7404, + }, + { + .name = "CLC_CROP_RND_CLAMP_Y_DS4", + .hw_status_reg = 0x7604, + }, + { + .name = "CLC_CROP_RND_CLAMP_C_DS4", + .hw_status_reg = 0x7804, + }, + { + .name = "CLC_R2PD_DS4", + .hw_status_reg = 0x7A04, + }, + { + .name = "CLC_DOWNSCALE_4TO1_Y", + .hw_status_reg = 0x7C04, + }, + { + .name = "CLC_DOWNSCALE_4TO1_C", + .hw_status_reg = 0x7E04, + }, + { + .name = "CLC_CROP_RND_CLAMP_Y_DS16", + .hw_status_reg = 0x8004, + }, + { + .name = "CLC_CROP_RND_CLAMP_C_DS16", + .hw_status_reg = 0x8204, + }, + { + .name = "CLC_R2PD_DS16", + .hw_status_reg = 0x8404, + }, + { + .name = "CLC_WB_GAIN", + .hw_status_reg = 0x8604, + }, + { + .name = "CLC_BAYER_DS2", + .hw_status_reg = 0x8804, + }, + { + .name = "CLC_GTM", + .hw_status_reg = 0x8A04, + }, + { + .name = "CLC_COLOR_XFORM_AI_DS", + .hw_status_reg = 0x8C04, + }, + { + .name = "CLC_DOWNSCALE_MN_Y", + .hw_status_reg = 0x8E04, + }, + { + .name = "CLC_DOWNSCALE_MN_C", + .hw_status_reg = 0x9004, + }, + { + .name = "CLC_CROP_RND_CLAMP_Y_AI_DS", + .hw_status_reg = 0x9204, + }, + { + .name = "CLC_CROP_RND_CLAMP_C_AI_DS", + .hw_status_reg = 0x9404, + }, + { + .name = "CLC_CROP_RND_CLAMP_IDEAL_RAW", + .hw_status_reg = 0x9604, + }, + { + .name = "CLC_ABF", + .hw_status_reg = 0x9804, + }, + { + .name = "CLC_STATS_BG", + .hw_status_reg = 0x9A04, + }, + { + .name = "CLC_STATS_BHIST", + .hw_status_reg = 0x9C04, + }, + { + .name = "CLC_STATS_AWB_BG", + .hw_status_reg = 0x9E04, + }, + { + .name = "CLC_STATS_AEC_BG", + .hw_status_reg = 0xA004, + }, + { + .name = "CLC_STATS_BAF", + .hw_status_reg = 0xA204, + }, + { + .name = "CLC_STATS_RS", + .hw_status_reg = 0xA404, + }, +}; + +static struct cam_tfe_top_hw_info tfe665_top_hw_info = { + .common_reg = &tfe665_top_commong_reg, + .camif_hw_info = { + .camif_reg = &tfe665_camif_reg, + .reg_data = &tfe665_camif_reg_data, + }, + .rdi_hw_info = { + { + .rdi_reg = &tfe665_rdi0_reg, + .reg_data = &tfe665_rdi0_reg_data, + }, + { + .rdi_reg = &tfe665_rdi1_reg, + .reg_data = &tfe665_rdi1_reg_data, + }, + { + .rdi_reg = &tfe665_rdi2_reg, + .reg_data = &tfe665_rdi2_reg_data, + }, + }, + .ppp_hw_info = { + .ppp_reg = &tfe665_ppp_reg, + .reg_data = &tfe665_ppp_reg_data, + }, + .in_port = { + CAM_TFE_CAMIF_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_PDLIB_VER_1_0 + }, + .reg_dump_data = { + .num_reg_dump_entries = 19, + .num_lut_dump_entries = 0, + .bus_start_addr = 0x2000, + .bus_write_top_end_addr = 0x2120, + .bus_client_start_addr = 0x2200, + .bus_client_offset = 0x100, + .num_bus_clients = 10, + .reg_entry = { + { + .start_offset = 0x1000, + .end_offset = 0x10F4, + }, + { + .start_offset = 0x1260, + .end_offset = 0x1280, + }, + { + .start_offset = 0x13F0, + .end_offset = 0x13FC, + }, + { + .start_offset = 0x1460, + .end_offset = 0x1470, + }, + { + .start_offset = 0x15F0, + .end_offset = 0x15FC, + }, + { + .start_offset = 0x1660, + .end_offset = 0x1670, + }, + { + .start_offset = 0x17F0, + .end_offset = 0x17FC, + }, + { + .start_offset = 0x1860, + .end_offset = 0x1870, + }, + { + .start_offset = 0x19F0, + .end_offset = 0x19FC, + }, + { + .start_offset = 0x2660, + .end_offset = 0x2694, + }, + { + .start_offset = 0x2860, + .end_offset = 0x2884, + }, + { + .start_offset = 0x2A60, + .end_offset = 0X2B34, + }, + { + .start_offset = 0x2C60, + .end_offset = 0X2C80, + }, + { + .start_offset = 0x2E60, + .end_offset = 0X2E7C, + }, + { + .start_offset = 0x3060, + .end_offset = 0X3110, + }, + { + .start_offset = 0x3260, + .end_offset = 0X3278, + }, + { + .start_offset = 0x3460, + .end_offset = 0X3478, + }, + { + .start_offset = 0x3660, + .end_offset = 0X3684, + }, + { + .start_offset = 0x3860, + .end_offset = 0X3884, + }, + }, + .lut_entry = { + { + .lut_word_size = 1, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + .dmi_reg_offset = 0x2800, + }, + { + .lut_word_size = 1, + .lut_bank_sel = 0x41, + .lut_addr_size = 180, + .dmi_reg_offset = 0x3000, + }, + }, + }, + .num_path_port_map = 3, + .path_port_map = { + {CAM_ISP_HW_TFE_IN_PDLIB, CAM_ISP_TFE_OUT_RES_PD_LCR_STATS}, + {CAM_ISP_HW_TFE_IN_PDLIB, CAM_ISP_TFE_OUT_RES_PD_PREPROCESSED}, + {CAM_ISP_HW_TFE_IN_PDLIB, CAM_ISP_TFE_OUT_RES_PD_PARSED}, + }, +}; + +static struct cam_tfe_bus_hw_info tfe665_bus_hw_info = { + .common_reg = { + .hw_version = 0x00003000, + .cgc_ovd = 0x00003008, + .comp_cfg_0 = 0x0000300C, + .comp_cfg_1 = 0x00003010, + .frameheader_cfg = { + 0x00003034, + 0x00003038, + 0x0000303C, + 0x00003040, + }, + .pwr_iso_cfg = 0x0000305C, + .overflow_status_clear = 0x00003060, + .ccif_violation_status = 0x00003064, + .overflow_status = 0x00003068, + .image_size_violation_status = 0x00003070, + .perf_count_cfg = { + 0x00003074, + 0x00003078, + 0x0000307C, + 0x00003080, + 0x00003084, + 0x00003088, + 0x0000308C, + 0x00003090, + }, + .perf_count_val = { + 0x00003094, + 0x00003098, + 0x0000309C, + 0x000030A0, + 0x000030A4, + 0x000030A8, + 0x000030AC, + 0x000030B0, + }, + .perf_count_status = 0x000030B4, + .debug_status_top_cfg = 0x000030D4, + .debug_status_top = 0x000030D8, + .test_bus_ctrl = 0x000030DC, + .irq_mask = { + 0x00003018, + 0x0000301C, + }, + .irq_clear = { + 0x00003020, + 0x00003024, + }, + .irq_status = { + 0x00003028, + 0x0000302C, + }, + .irq_cmd = 0x00003030, + .cons_violation_shift = 28, + .violation_shift = 30, + .image_size_violation = 31, + }, + .num_client = 19, + .bus_client_reg = { + /* BUS Client 0 BAYER */ + { + .cfg = 0x00003200, + .image_addr = 0x00003204, + .frame_incr = 0x00003208, + .image_cfg_0 = 0x0000320C, + .image_cfg_1 = 0x00003210, + .image_cfg_2 = 0x00003214, + .packer_cfg = 0x00003218, + .bw_limit = 0x0000321C, + .frame_header_addr = 0x00003220, + .frame_header_incr = 0x00003224, + .frame_header_cfg = 0x00003228, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003230, + .irq_subsample_pattern = 0x00003234, + .framedrop_period = 0x00003238, + .framedrop_pattern = 0x0000323C, + .system_cache_cfg = 0x00003260, + .addr_status_0 = 0x00003268, + .addr_status_1 = 0x0000326C, + .addr_status_2 = 0x00003270, + .addr_status_3 = 0x00003274, + .debug_status_cfg = 0x00003278, + .debug_status_0 = 0x0000327C, + .debug_status_1 = 0x00003280, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "BAYER", + }, + /* BUS Client 1 IDEAL RAW*/ + { + .cfg = 0x00003300, + .image_addr = 0x00003304, + .frame_incr = 0x00003308, + .image_cfg_0 = 0x0000330C, + .image_cfg_1 = 0x00003310, + .image_cfg_2 = 0x00003314, + .packer_cfg = 0x00003318, + .bw_limit = 0x0000331C, + .frame_header_addr = 0x00003320, + .frame_header_incr = 0x00003324, + .frame_header_cfg = 0x00003328, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003330, + .irq_subsample_pattern = 0x00003334, + .framedrop_period = 0x00003338, + .framedrop_pattern = 0x0000333C, + .system_cache_cfg = 0x00003360, + .addr_status_0 = 0x00003368, + .addr_status_1 = 0x0000336C, + .addr_status_2 = 0x00003370, + .addr_status_3 = 0x00003374, + .debug_status_cfg = 0x00003378, + .debug_status_0 = 0x0000337C, + .debug_status_1 = 0x00003380, + .comp_group = CAM_TFE_BUS_COMP_GRP_1, + .client_name = "IDEAL_RAW", + }, + /* BUS Client 2 Stats BE Tintless */ + { + .cfg = 0x00003400, + .image_addr = 0x00003404, + .frame_incr = 0x00003408, + .image_cfg_0 = 0x0000340C, + .image_cfg_1 = 0x00003410, + .image_cfg_2 = 0x00003414, + .packer_cfg = 0x00003418, + .bw_limit = 0x0000341C, + .frame_header_addr = 0x00003420, + .frame_header_incr = 0x00003424, + .frame_header_cfg = 0x00003428, + .line_done_cfg = 0x00003400, + .irq_subsample_period = 0x00003430, + .irq_subsample_pattern = 0x00003434, + .framedrop_period = 0x00003438, + .framedrop_pattern = 0x0000343C, + .system_cache_cfg = 0x00003460, + .addr_status_0 = 0x00003468, + .addr_status_1 = 0x0000346C, + .addr_status_2 = 0x00003470, + .addr_status_3 = 0x00003474, + .debug_status_cfg = 0x00003478, + .debug_status_0 = 0x0000347C, + .debug_status_1 = 0x00003480, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BE TINTLESS", + }, + /* BUS Client 3 Stats Bhist */ + { + .cfg = 0x00003500, + .image_addr = 0x00003504, + .frame_incr = 0x00003508, + .image_cfg_0 = 0x0000350C, + .image_cfg_1 = 0x00003510, + .image_cfg_2 = 0x00003514, + .packer_cfg = 0x00003518, + .bw_limit = 0x0000351C, + .frame_header_addr = 0x00003520, + .frame_header_incr = 0x00003524, + .frame_header_cfg = 0x00003528, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003530, + .irq_subsample_pattern = 0x00003534, + .framedrop_period = 0x00003538, + .framedrop_pattern = 0x0000353C, + .system_cache_cfg = 0x00003560, + .addr_status_0 = 0x00003568, + .addr_status_1 = 0x0000356C, + .addr_status_2 = 0x00003570, + .addr_status_3 = 0x00003574, + .debug_status_cfg = 0x00003578, + .debug_status_0 = 0x0000357C, + .debug_status_1 = 0x00003580, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BHIST", + }, + /* BUS Client 4 Stats AWB BG */ + { + .cfg = 0x00003600, + .image_addr = 0x00003604, + .frame_incr = 0x00003608, + .image_cfg_0 = 0x0000360C, + .image_cfg_1 = 0x00003610, + .image_cfg_2 = 0x00003614, + .packer_cfg = 0x00003618, + .bw_limit = 0x0000361C, + .frame_header_addr = 0x00003620, + .frame_header_incr = 0x00003624, + .frame_header_cfg = 0x00003628, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003630, + .irq_subsample_pattern = 0x00003634, + .framedrop_period = 0x00003638, + .framedrop_pattern = 0x0000363C, + .system_cache_cfg = 0x00003660, + .addr_status_0 = 0x00003668, + .addr_status_1 = 0x0000366C, + .addr_status_2 = 0x00003670, + .addr_status_3 = 0x00003674, + .debug_status_cfg = 0x00003678, + .debug_status_0 = 0x0000367C, + .debug_status_1 = 0x00003680, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AWB BG", + }, + /* BUS Client 5 Stats AEC BG */ + { + .cfg = 0x00003700, + .image_addr = 0x00003704, + .frame_incr = 0x00003708, + .image_cfg_0 = 0x0000370C, + .image_cfg_1 = 0x00003710, + .image_cfg_2 = 0x00003714, + .packer_cfg = 0x00003718, + .bw_limit = 0x0000371C, + .frame_header_addr = 0x00003720, + .frame_header_incr = 0x00003724, + .frame_header_cfg = 0x00003728, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003730, + .irq_subsample_pattern = 0x00003734, + .framedrop_period = 0x00003738, + .framedrop_pattern = 0x0000373C, + .system_cache_cfg = 0x00003760, + .addr_status_0 = 0x00003768, + .addr_status_1 = 0x0000376C, + .addr_status_2 = 0x00003770, + .addr_status_3 = 0x00003774, + .debug_status_cfg = 0x00003778, + .debug_status_0 = 0x0000377C, + .debug_status_1 = 0x00003780, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AEC BG", + }, + /* BUS Client 6 Stats BAF */ + { + .cfg = 0x00003800, + .image_addr = 0x00003804, + .frame_incr = 0x00003808, + .image_cfg_0 = 0x0000380C, + .image_cfg_1 = 0x00003810, + .image_cfg_2 = 0x00003814, + .packer_cfg = 0x00003818, + .bw_limit = 0x0000381C, + .frame_header_addr = 0x00003820, + .frame_header_incr = 0x00003824, + .frame_header_cfg = 0x00003828, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003830, + .irq_subsample_pattern = 0x00003834, + .framedrop_period = 0x00003838, + .framedrop_pattern = 0x0000383C, + .system_cache_cfg = 0x00003860, + .addr_status_0 = 0x00003868, + .addr_status_1 = 0x0000386C, + .addr_status_2 = 0x00003870, + .addr_status_3 = 0x00003874, + .debug_status_cfg = 0x00003878, + .debug_status_0 = 0x0000387C, + .debug_status_1 = 0x00003880, + .comp_group = CAM_TFE_BUS_COMP_GRP_4, + .client_name = "STATS BAF", + }, + /* BUS Client 7 RDI0 */ + { + .cfg = 0x00003900, + .image_addr = 0x00003904, + .frame_incr = 0x00003908, + .image_cfg_0 = 0x0000390C, + .image_cfg_1 = 0x00003910, + .image_cfg_2 = 0x00003914, + .packer_cfg = 0x00003918, + .bw_limit = 0x0000391C, + .frame_header_addr = 0x00003920, + .frame_header_incr = 0x00003924, + .frame_header_cfg = 0x00003928, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003930, + .irq_subsample_pattern = 0x00003934, + .framedrop_period = 0x00003938, + .framedrop_pattern = 0x0000393C, + .system_cache_cfg = 0x00003960, + .addr_status_0 = 0x00003968, + .addr_status_1 = 0x0000396C, + .addr_status_2 = 0x00003970, + .addr_status_3 = 0x00003974, + .debug_status_cfg = 0x00003978, + .debug_status_0 = 0x0000397C, + .debug_status_1 = 0x00003980, + .comp_group = CAM_TFE_BUS_COMP_GRP_5, + .client_name = "RDI0", + }, + /* BUS Client 8 RDI1 */ + { + .cfg = 0x00003A00, + .image_addr = 0x00003A04, + .frame_incr = 0x00003A08, + .image_cfg_0 = 0x00003A0C, + .image_cfg_1 = 0x00003A10, + .image_cfg_2 = 0x00003A14, + .packer_cfg = 0x00003A18, + .bw_limit = 0x00003A1C, + .frame_header_addr = 0x00003A20, + .frame_header_incr = 0x00003A24, + .frame_header_cfg = 0x00003A28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003A30, + .irq_subsample_pattern = 0x00003A34, + .framedrop_period = 0x00003A38, + .framedrop_pattern = 0x00003A3C, + .system_cache_cfg = 0x00003A60, + .addr_status_0 = 0x00003A68, + .addr_status_1 = 0x00003A6C, + .addr_status_2 = 0x00003A70, + .addr_status_3 = 0x00003A74, + .debug_status_cfg = 0x00003A78, + .debug_status_0 = 0x00003A7C, + .debug_status_1 = 0x00003A80, + .comp_group = CAM_TFE_BUS_COMP_GRP_6, + .client_name = "RDI1", + }, + /* BUS Client 9 RDI2 */ + { + .cfg = 0x00003B00, + .image_addr = 0x00003B04, + .frame_incr = 0x00003B08, + .image_cfg_0 = 0x00003B0C, + .image_cfg_1 = 0x00003B10, + .image_cfg_2 = 0x00003B14, + .packer_cfg = 0x00003B18, + .bw_limit = 0x00003B1C, + .frame_header_addr = 0x00003B20, + .frame_header_incr = 0x00003B24, + .frame_header_cfg = 0x00003B28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003B30, + .irq_subsample_pattern = 0x00003B34, + .framedrop_period = 0x00003B38, + .framedrop_pattern = 0x00003B3C, + .system_cache_cfg = 0x00003B60, + .addr_status_0 = 0x00003B68, + .addr_status_1 = 0x00003B6C, + .addr_status_2 = 0x00003B70, + .addr_status_3 = 0x00003B74, + .debug_status_cfg = 0x00003B78, + .debug_status_0 = 0x00003B7C, + .debug_status_1 = 0x00003B80, + .comp_group = CAM_TFE_BUS_COMP_GRP_7, + .client_name = "RDI2", + }, + /* BUS Client 10 PDAF */ + { + .cfg = 0x00003C00, + .image_addr = 0x00003C04, + .frame_incr = 0x00003C08, + .image_cfg_0 = 0x00003C0C, + .image_cfg_1 = 0x00003C10, + .image_cfg_2 = 0x00003C14, + .packer_cfg = 0x00003C18, + .bw_limit = 0x00003C1C, + .frame_header_addr = 0x00003C20, + .frame_header_incr = 0x00003C24, + .frame_header_cfg = 0x00003C28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003C30, + .irq_subsample_pattern = 0x00003C34, + .framedrop_period = 0x00003C38, + .framedrop_pattern = 0x00003C3C, + .system_cache_cfg = 0x00003C60, + .addr_status_0 = 0x00003C68, + .addr_status_1 = 0x00003C6C, + .addr_status_2 = 0x00003C70, + .addr_status_3 = 0x00003C74, + .debug_status_cfg = 0x00003C78, + .debug_status_0 = 0x00003C7C, + .debug_status_1 = 0x00003C80, + .comp_group = CAM_TFE_BUS_COMP_GRP_8, + .client_name = "PDAF", + }, + /* BUS Client 11 DS4 */ + { + .cfg = 0x00003D00, + .image_addr = 0x00003D04, + .frame_incr = 0x00003D08, + .image_cfg_0 = 0x00003D0C, + .image_cfg_1 = 0x00003D10, + .image_cfg_2 = 0x00003D14, + .packer_cfg = 0x00003D18, + .bw_limit = 0x00003D1C, + .frame_header_addr = 0x00003D20, + .frame_header_incr = 0x00003D24, + .frame_header_cfg = 0x00003D28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003D30, + .irq_subsample_pattern = 0x00003D34, + .framedrop_period = 0x00003D38, + .framedrop_pattern = 0x00003D3C, + .system_cache_cfg = 0x00003D60, + .addr_status_0 = 0x00003D68, + .addr_status_1 = 0x00003D6C, + .addr_status_2 = 0x00003D70, + .addr_status_3 = 0x00003D74, + .debug_status_cfg = 0x00003D78, + .debug_status_0 = 0x00003D7C, + .debug_status_1 = 0x00003D80, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "DS4", + }, + /* BUS Client 12 DS16 */ + { + .cfg = 0x00003E00, + .image_addr = 0x00003E04, + .frame_incr = 0x00003E08, + .image_cfg_0 = 0x00003E0C, + .image_cfg_1 = 0x00003E10, + .image_cfg_2 = 0x00003E14, + .packer_cfg = 0x00003E18, + .bw_limit = 0x00003E1C, + .frame_header_addr = 0x00003E20, + .frame_header_incr = 0x00003E24, + .frame_header_cfg = 0x00003E28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003E30, + .irq_subsample_pattern = 0x00003E34, + .framedrop_period = 0x00003E38, + .framedrop_pattern = 0x00003E3C, + .system_cache_cfg = 0x00003E60, + .addr_status_0 = 0x00003E68, + .addr_status_1 = 0x00003E6C, + .addr_status_2 = 0x00003E70, + .addr_status_3 = 0x00003E74, + .debug_status_cfg = 0x00003E78, + .debug_status_0 = 0x00003E7C, + .debug_status_1 = 0x00003E80, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "DS16", + }, + /* BUS Client 13 AI-Y */ + { + .cfg = 0x00003F00, + .image_addr = 0x00003F04, + .frame_incr = 0x00003F08, + .image_cfg_0 = 0x00003F0C, + .image_cfg_1 = 0x00003F10, + .image_cfg_2 = 0x00003F14, + .packer_cfg = 0x00003F18, + .bw_limit = 0x00003F1C, + .frame_header_addr = 0x00003F20, + .frame_header_incr = 0x00003F24, + .frame_header_cfg = 0x00003F28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003F30, + .irq_subsample_pattern = 0x00003F34, + .framedrop_period = 0x00003F38, + .framedrop_pattern = 0x00003F3C, + .system_cache_cfg = 0x00003F60, + .addr_status_0 = 0x00003F68, + .addr_status_1 = 0x00003F6C, + .addr_status_2 = 0x00003F70, + .addr_status_3 = 0x00003F74, + .debug_status_cfg = 0x00003F78, + .debug_status_0 = 0x00003F7C, + .debug_status_1 = 0x00003F80, + .comp_group = CAM_TFE_BUS_COMP_GRP_9, + .client_name = "AI-Y", + }, + /* BUS Client 14 AI-C */ + { + .cfg = 0x00004000, + .image_addr = 0x00004004, + .frame_incr = 0x00004008, + .image_cfg_0 = 0x0000400C, + .image_cfg_1 = 0x00004010, + .image_cfg_2 = 0x00004014, + .packer_cfg = 0x00004018, + .bw_limit = 0x0000401C, + .frame_header_addr = 0x00004020, + .frame_header_incr = 0x00004024, + .frame_header_cfg = 0x00004028, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004030, + .irq_subsample_pattern = 0x00004034, + .framedrop_period = 0x00004038, + .framedrop_pattern = 0x0000403C, + .system_cache_cfg = 0x00004060, + .addr_status_0 = 0x00004068, + .addr_status_1 = 0x0000406C, + .addr_status_2 = 0x00004070, + .addr_status_3 = 0x00004074, + .debug_status_cfg = 0x00004078, + .debug_status_0 = 0x0000407C, + .debug_status_1 = 0x00004080, + .comp_group = CAM_TFE_BUS_COMP_GRP_9, + .client_name = "AI-C", + }, + /* BUS Client 15 Stats RS */ + { + .cfg = 0x00004100, + .image_addr = 0x00004104, + .frame_incr = 0x00004108, + .image_cfg_0 = 0x0000410C, + .image_cfg_1 = 0x00004110, + .image_cfg_2 = 0x00004114, + .packer_cfg = 0x00004118, + .bw_limit = 0x0000411C, + .frame_header_addr = 0x00004120, + .frame_header_incr = 0x00004124, + .frame_header_cfg = 0x00004128, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004130, + .irq_subsample_pattern = 0x00004134, + .framedrop_period = 0x00004138, + .framedrop_pattern = 0x0000413C, + .system_cache_cfg = 0x00004160, + .addr_status_0 = 0x00004168, + .addr_status_1 = 0x0000416C, + .addr_status_2 = 0x00004170, + .addr_status_3 = 0x00004174, + .debug_status_cfg = 0x00004178, + .debug_status_0 = 0x0000417C, + .debug_status_1 = 0x00004180, + .comp_group = CAM_TFE_BUS_COMP_GRP_10, + .client_name = "STATS RS", + }, + /* BUS Client 16 PDAF 0 STAT LCR */ + { + .cfg = 0x00004200, + .image_addr = 0x00004204, + .frame_incr = 0x00004208, + .image_cfg_0 = 0x0000420C, + .image_cfg_1 = 0x00004210, + .image_cfg_2 = 0x00004214, + .packer_cfg = 0x00004218, + .bw_limit = 0x0000421C, + .frame_header_addr = 0x00004220, + .frame_header_incr = 0x00004224, + .frame_header_cfg = 0x00004228, + .line_done_cfg = 0x0000422C, + .irq_subsample_period = 0x00004230, + .irq_subsample_pattern = 0x00004234, + .framedrop_period = 0x00004238, + .framedrop_pattern = 0x0000423C, + .system_cache_cfg = 0x00004260, + .addr_status_0 = 0x00004268, + .addr_status_1 = 0x0000426C, + .addr_status_2 = 0x00004270, + .addr_status_3 = 0x00004274, + .debug_status_cfg = 0x00004278, + .debug_status_0 = 0x0000427C, + .debug_status_1 = 0x00004280, + .comp_group = CAM_TFE_BUS_COMP_GRP_11, + .client_name = "STAT LCR", + }, + /* BUS Client 17 PDAF 1 PD PREPROCESSED*/ + { + .cfg = 0x00004300, + .image_addr = 0x00004304, + .frame_incr = 0x00004308, + .image_cfg_0 = 0x0000430C, + .image_cfg_1 = 0x00004310, + .image_cfg_2 = 0x00004314, + .packer_cfg = 0x00004318, + .bw_limit = 0x0000431C, + .frame_header_addr = 0x00004320, + .frame_header_incr = 0x00004324, + .frame_header_cfg = 0x00004328, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004330, + .irq_subsample_pattern = 0x00004334, + .framedrop_period = 0x00004338, + .framedrop_pattern = 0x0000433C, + .system_cache_cfg = 0x00004360, + .addr_status_0 = 0x00004368, + .addr_status_1 = 0x0000436C, + .addr_status_2 = 0x00004370, + .addr_status_3 = 0x00004374, + .debug_status_cfg = 0x00004378, + .debug_status_0 = 0x0000437C, + .debug_status_1 = 0x00004380, + .comp_group = CAM_TFE_BUS_COMP_GRP_11, + .client_name = "PD PREPROCESSED", + }, + /* BUS Client 18 PDAF 2 PD PARSED*/ + { + .cfg = 0x00004400, + .image_addr = 0x00004404, + .frame_incr = 0x00004408, + .image_cfg_0 = 0x0000440C, + .image_cfg_1 = 0x00004410, + .image_cfg_2 = 0x00004414, + .packer_cfg = 0x00004418, + .bw_limit = 0x0000441C, + .frame_header_addr = 0x00004420, + .frame_header_incr = 0x00004424, + .frame_header_cfg = 0x00004428, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004430, + .irq_subsample_pattern = 0x00004434, + .framedrop_period = 0x00004438, + .framedrop_pattern = 0x0000443C, + .system_cache_cfg = 0x00004460, + .addr_status_0 = 0x00004468, + .addr_status_1 = 0x0000446C, + .addr_status_2 = 0x00004470, + .addr_status_3 = 0x00004474, + .debug_status_cfg = 0x00004478, + .debug_status_0 = 0x0000447C, + .debug_status_1 = 0x00004480, + .comp_group = CAM_TFE_BUS_COMP_GRP_11, + .client_name = "PD PARSED", + }, + }, + .num_out = 18, + .tfe_out_hw_info = { + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_5, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_1, + .mid[0] = 16, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_6, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_2, + .mid[0] = 17, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_7, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_3, + .mid[0] = 18, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 16, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RAW_DUMP, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_1, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 19, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PDAF, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_8, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 26, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 20, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 18, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 17, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 19, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_4, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 21, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_RS, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_10, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 27, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_DS4, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 22, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_DS16, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 23, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_AI, + .max_width = 1920, + .max_height = 1920, + .composite_group = CAM_TFE_BUS_COMP_GRP_9, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 24, + .mid[1] = 25, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PD_LCR_STATS, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_11, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_4, + .mid[0] = 21, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PD_PREPROCESSED, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_11, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_4, + .mid[0] = 20, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PD_PARSED, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_11, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_4, + .mid[0] = 22, + .pid_mask = 0x70, + }, + }, + .num_comp_grp = 12, + .max_wm_per_comp_grp = 3, + .comp_done_shift = 8, + .top_bus_wr_irq_shift = 1, + .comp_buf_done_mask = 0xFFF00, + .comp_rup_done_mask = 0xF, + .bus_irq_error_mask = { + 0xD0000000, + 0x00000000, + }, + .support_consumed_addr = true, + .pdaf_rdi2_mux_en = false, + .rdi_width = 128, + .mode_cfg_shift = 16, + .height_shift = 16, + .max_out_res = CAM_ISP_TFE_OUT_RES_MAX & 0xFF, +}; + +struct cam_tfe_hw_info cam_tfe665 = { + .top_irq_mask = { + 0x00001834, + 0x00001838, + 0x0000183C, + }, + .top_irq_clear = { + 0x00001840, + 0x00001844, + 0x00001848, + }, + .top_irq_status = { + 0x0000184C, + 0x00001850, + 0x00001854, + }, + .top_irq_cmd = 0x00001830, + .global_clear_bitmask = 0x00000001, + .bus_irq_mask = { + 0x00003018, + 0x0000301C, + }, + .bus_irq_clear = { + 0x00003020, + 0x00003024, + }, + .bus_irq_status = { + 0x00003028, + 0x0000302C, + }, + .bus_irq_cmd = 0x00003030, + .bus_violation_reg = 0x00003064, + .bus_overflow_reg = 0x00003068, + .bus_image_size_vilation_reg = 0x3070, + .bus_overflow_clear_cmd = 0x3060, + .debug_status_top = 0x30D8, + + .reset_irq_mask = { + 0x00000001, + 0x00000000, + 0x00000000, + }, + .error_irq_mask = { + 0x001F1F00, + 0x00000000, + 0x000002FF, + }, + .non_fatal_error_irq_mask = { + 0x00200000, + 0x00000000, + 0x00000000, + }, + .bus_reg_irq_mask = { + 0x00000002, + 0x00000000, + }, + .bus_error_irq_mask = { + 0xC0000000, + 0x00000000, + }, + + .num_clc = 39, + .clc_hw_status_info = tfe665_clc_hw_info, + .bus_version = CAM_TFE_BUS_1_0, + .bus_hw_info = &tfe665_bus_hw_info, + + .top_version = CAM_TFE_TOP_1_0, + .top_hw_info = &tfe665_top_hw_info, +}; + +#endif /* _CAM_TFE665__H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe770.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe770.h new file mode 100644 index 0000000000..d7a17ae5fc --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe770.h @@ -0,0 +1,1476 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#ifndef _CAM_TFE770_H_ +#define _CAM_TFE770_H_ +#include +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" + + +static struct cam_tfe_top_reg_offset_common tfe770_top_commong_reg = { + .hw_version = 0x00001800, + .hw_capability = 0x00001804, + .lens_feature = 0x00001808, + .stats_feature = 0x0000180C, + .zoom_feature = 0x00001810, + .global_reset_cmd = 0x00001814, + .core_cgc_ctrl_0 = 0x00001818, + .core_cgc_ctrl_1 = 0x0000181C, + .ahb_cgc_ctrl = 0x0000181C, + .core_cfg_0 = 0x00001824, + .reg_update_cmd = 0x0000182C, + .diag_config = 0x00001860, + .diag_sensor_status_0 = 0x00001864, + .diag_sensor_status_1 = 0x00001868, + .diag_sensor_frame_cnt_status = 0x0000186C, + .violation_status = 0x00001870, + .stats_throttle_cnt_cfg_0 = 0x00001874, + .stats_throttle_cnt_cfg_1 = 0x00001878, + .num_debug_reg = 12, + .debug_reg = { + 0x000018A0, + 0x000018A4, + 0x000018A8, + 0x000018AC, + 0x000018B0, + 0x000018B4, + 0x000018B8, + 0x000018BC, + 0x000018C0, + 0x000018C4, + 0x000018C8, + 0x000018CC, + }, + .debug_cfg = 0x000018DC, + .num_perf_cfg = 2, + .perf_cfg = { + { + .perf_cnt_cfg = 0x000018E0, + .perf_pixel_count = 0x000018E4, + .perf_line_count = 0x000018E8, + .perf_stall_count = 0x000018EC, + .perf_always_count = 0x000018F0, + .perf_count_status = 0x000018F4, + }, + { + .perf_cnt_cfg = 0x000018F8, + .perf_pixel_count = 0x000018FC, + .perf_line_count = 0x00001900, + .perf_stall_count = 0x00001904, + .perf_always_count = 0x00001908, + .perf_count_status = 0x0000190C, + }, + }, + .diag_sensor_frame_cnt_status_1 = 0x00001920, + .diag_min_hbi_error_shift = 15, + .diag_neq_hbi_shift = 14, + .diag_sensor_hbi_mask = 0x3FFF, + .serializer_supported = true, + .pp_camif_violation_bit = BIT(0), + .pp_violation_bit = BIT(1), + .rdi0_camif_violation_bit = BIT(2), + .rdi1_camif_violation_bit = BIT(3), + .rdi2_camif_violation_bit = BIT(4), + .diag_violation_bit = BIT(5), + .ppp_camif_violation_bit = BIT(6), + .ppp_violation_bit = BIT(7), + .lcr_pd_timing_protocol_violation_bit = BIT(8), + .dyamanic_switch_violation_bit = BIT(9), + .pp_frame_drop_bit = BIT(8), + .rdi0_frame_drop_bit = BIT(9), + .rdi1_frame_drop_bit = BIT(10), + .rdi2_frame_drop_bit = BIT(11), + .ppp_frame_drop_bit = BIT(12), + .pp_overflow_bit = BIT(16), + .rdi0_overflow_bit = BIT(17), + .rdi1_overflow_bit = BIT(18), + .rdi2_overflow_bit = BIT(19), + .ppp_overflow_bit = BIT(20), + .out_of_sync_frame_drop_bit = BIT(21), + .mup_shift_val = 8, + .mup_supported = true, + .height_shift = 16, + .epoch_shift_val = 16, +}; + +static struct cam_tfe_camif_reg tfe770_camif_reg = { + .hw_version = 0x00001C00, + .hw_status = 0x00001C04, + .module_cfg = 0x00001C60, + .pdaf_raw_crop_width_cfg = 0x00001C68, + .pdaf_raw_crop_height_cfg = 0x00001C6C, + .line_skip_pattern = 0x00001C70, + .pixel_skip_pattern = 0x00001C74, + .period_cfg = 0x00001C78, + .irq_subsample_pattern = 0x00001C7C, + .epoch_irq_cfg = 0x00001C80, + .debug_1 = 0x00001DF0, + .debug_0 = 0x00001DF4, + .test_bus_ctrl = 0x00001DF8, + .spare = 0x00001DFC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_camif_reg_data tfe770_camif_reg_data = { + .extern_reg_update_mask = 0x00000001, + .dual_tfe_pix_en_shift = 0x00000001, + .extern_reg_update_shift = 0x0, + .dual_tfe_sync_sel_shift = 18, + .delay_line_en_shift = 8, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x7000000, + .module_enable_shift = 0, + .pix_out_enable_shift = 8, + .pdaf_output_enable_shift = 9, + .dsp_mode_shift = 0, + .dsp_mode_mask = 0, + .dsp_en_shift = 0, + .dsp_en_mask = 0, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .epoch1_irq_mask = 0x00000008, + .eof_irq_mask = 0x00000002, + .reg_update_irq_mask = 0x00000001, + .error_irq_mask0 = 0x00210100, + .error_irq_mask2 = 0x00000223, + .subscribe_irq_mask = { + 0x00000000, + 0x00000007, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .perf_cnt_start_cmd_shift = 0, + .perf_cnt_continuous_shift = 2, + .perf_client_sel_shift = 8, + .perf_window_start_shift = 16, + .perf_window_end_shift = 20, + .ai_c_srl_en_shift = 11, + .ds16_c_srl_en_shift = 10, + .ds4_c_srl_en_shift = 9, + .shdr_mode_shift = 21, + .extern_mup_shift = 22, +}; + +static struct cam_tfe_rdi_reg tfe770_rdi0_reg = { + .rdi_hw_version = 0x00001E00, + .rdi_hw_status = 0x00001E04, + .rdi_module_config = 0x00001E60, + .rdi_skip_period = 0x00001E68, + .rdi_irq_subsample_pattern = 0x00001E6C, + .rdi_epoch_irq = 0x00001E70, + .rdi_debug_1 = 0x00001FF0, + .rdi_debug_0 = 0x00001FF4, + .rdi_test_bus_ctrl = 0x00001FF8, + .rdi_spare = 0x00001FFC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe770_rdi0_reg_data = { + .reg_update_cmd_data = 0x2, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000010, + .epoch0_irq_mask = 0x00000040, + .epoch1_irq_mask = 0x00000080, + .eof_irq_mask = 0x00000020, + .error_irq_mask0 = 0x00020200, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00000030, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x1, + .diag_sensor_shift = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe770_rdi1_reg = { + .rdi_hw_version = 0x00002000, + .rdi_hw_status = 0x00002004, + .rdi_module_config = 0x00002060, + .rdi_skip_period = 0x00002068, + .rdi_irq_subsample_pattern = 0x0000206C, + .rdi_epoch_irq = 0x00002070, + .rdi_debug_1 = 0x000021F0, + .rdi_debug_0 = 0x000021F4, + .rdi_test_bus_ctrl = 0x000021F8, + .rdi_spare = 0x000021FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe770_rdi1_reg_data = { + .reg_update_cmd_data = 0x4, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000100, + .epoch0_irq_mask = 0x00000400, + .epoch1_irq_mask = 0x00000800, + .eof_irq_mask = 0x00000200, + .error_irq_mask0 = 0x00040400, + .error_irq_mask2 = 0x00000008, + .subscribe_irq_mask = { + 0x00000000, + 0x00000300, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x2, + .diag_sensor_shift = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe770_rdi2_reg = { + .rdi_hw_version = 0x00002200, + .rdi_hw_status = 0x00002204, + .rdi_module_config = 0x00002260, + .rdi_skip_period = 0x00002268, + .rdi_irq_subsample_pattern = 0x0000226C, + .rdi_epoch_irq = 0x00002270, + .rdi_debug_1 = 0x000023F0, + .rdi_debug_0 = 0x000023F4, + .rdi_test_bus_ctrl = 0x000023F8, + .rdi_spare = 0x000023FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe770_rdi2_reg_data = { + .reg_update_cmd_data = 0x8, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00001000, + .epoch0_irq_mask = 0x00004000, + .epoch1_irq_mask = 0x00008000, + .eof_irq_mask = 0x00002000, + .error_irq_mask0 = 0x00080800, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00003000, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x3, + .diag_sensor_shift = 0x1, + +}; + +static struct cam_tfe_ppp_reg tfe770_ppp_reg = { + .ppp_hw_version = 0x00002400, + .ppp_hw_status = 0x00002404, + .ppp_module_config = 0x00002460, + .ppp_skip_period = 0x00002468, + .ppp_irq_subsample_pattern = 0x0000246C, + .ppp_epoch_irq = 0x00002470, + .ppp_debug_1 = 0x000025F0, + .ppp_debug_0 = 0x000025F4, + .ppp_test_bus_ctrl = 0x000025F8, + .ppp_spare = 0x000025FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_ppp_reg_data tfe770_ppp_reg_data = { + .sof_irq_mask = 0x00000000, + .epoch0_irq_mask = 0x00000000, + .epoch1_irq_mask = 0x00000000, + .eof_irq_mask = 0x00000000, + .subscribe_irq_mask = { + 0x00000000, + 0x00000000, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x4, + .diag_sensor_shift = 0x1, + .pdaf_path_en_shift = 24, + .lcr_dis_en_shift = 23, +}; + +static struct cam_tfe_clc_hw_status tfe770_clc_hw_info[CAM_TFE_MAX_CLC] = { + { + .name = "CLC_CAMIF", + .hw_status_reg = 0x1C04, + }, + { + .name = "CLC_RDI0_CAMIF", + .hw_status_reg = 0x1E04, + }, + { + .name = "CLC_RDI1_CAMIF", + .hw_status_reg = 0x2004, + }, + { + .name = "CLC_RDI2_CAMIF", + .hw_status_reg = 0x2204, + }, + { + .name = "CLC_PD_CAMIF", + .hw_status_reg = 0x2404, + }, + { + .name = "CLC_PDAF_LITE", + .hw_status_reg = 0x2A04, + }, + { + .name = "CLC_CHANNEL_GAIN", + .hw_status_reg = 0x6004, + }, + { + .name = "CLC_BPC_PDPC", + .hw_status_reg = 0x6204, + }, + { + .name = "CLC_LCS", + .hw_status_reg = 0x6404, + }, + { + .name = "CLC_SHARED_LB", + .hw_status_reg = 0x6604, + }, + { + .name = "CLC_WB_BDS", + .hw_status_reg = 0x6804, + }, + { + .name = "CLC_CROP_RND_CLAMP_POST_BDS", + .hw_status_reg = 0x6A04, + }, + { + .name = "CLC_BLS", + .hw_status_reg = 0x6C04, + }, + { + .name = "CLC_BAYER_GLUT", + .hw_status_reg = 0x6E04, + }, + { + .name = "CLC_BAYER_DS4", + .hw_status_reg = 0x7004, + }, + { + .name = "CLC_COLOR_XFORM_DS4", + .hw_status_reg = 0x7204, + }, + { + .name = "CLC_CHROMA_DS2", + .hw_status_reg = 0x7404, + }, + { + .name = "CLC_CROP_RND_CLAMP_Y_DS4", + .hw_status_reg = 0x7604, + }, + { + .name = "CLC_CROP_RND_CLAMP_C_DS4", + .hw_status_reg = 0x7804, + }, + { + .name = "CLC_R2PD_DS4", + .hw_status_reg = 0x7A04, + }, + { + .name = "CLC_DOWNSCALE_4TO1_Y", + .hw_status_reg = 0x7C04, + }, + { + .name = "CLC_DOWNSCALE_4TO1_C", + .hw_status_reg = 0x7E04, + }, + { + .name = "CLC_CROP_RND_CLAMP_Y_DS16", + .hw_status_reg = 0x8004, + }, + { + .name = "CLC_CROP_RND_CLAMP_C_DS16", + .hw_status_reg = 0x8204, + }, + { + .name = "CLC_R2PD_DS16", + .hw_status_reg = 0x8404, + }, + { + .name = "CLC_WB_GAIN", + .hw_status_reg = 0x8604, + }, + { + .name = "CLC_BAYER_DS2", + .hw_status_reg = 0x8804, + }, + { + .name = "CLC_GTM", + .hw_status_reg = 0x8A04, + }, + { + .name = "CLC_COLOR_XFORM_AI_DS", + .hw_status_reg = 0x8C04, + }, + { + .name = "CLC_DOWNSCALE_MN_Y", + .hw_status_reg = 0x8E04, + }, + { + .name = "CLC_DOWNSCALE_MN_C", + .hw_status_reg = 0x9004, + }, + { + .name = "CLC_CROP_RND_CLAMP_Y_AI_DS", + .hw_status_reg = 0x9204, + }, + { + .name = "CLC_CROP_RND_CLAMP_C_AI_DS", + .hw_status_reg = 0x9404, + }, + { + .name = "CLC_CROP_RND_CLAMP_IDEAL_RAW", + .hw_status_reg = 0x9604, + }, + { + .name = "CLC_ABF", + .hw_status_reg = 0x9804, + }, + { + .name = "CLC_STATS_BG", + .hw_status_reg = 0x9A04, + }, + { + .name = "CLC_STATS_BHIST", + .hw_status_reg = 0x9C04, + }, + { + .name = "CLC_STATS_AWB_BG", + .hw_status_reg = 0x9E04, + }, + { + .name = "CLC_STATS_AEC_BG", + .hw_status_reg = 0xA004, + }, + { + .name = "CLC_STATS_BAF", + .hw_status_reg = 0xA204, + }, + { + .name = "CLC_STATS_RS", + .hw_status_reg = 0xA404, + }, +}; + +static struct cam_tfe_top_hw_info tfe770_top_hw_info = { + .common_reg = &tfe770_top_commong_reg, + .camif_hw_info = { + .camif_reg = &tfe770_camif_reg, + .reg_data = &tfe770_camif_reg_data, + }, + .rdi_hw_info = { + { + .rdi_reg = &tfe770_rdi0_reg, + .reg_data = &tfe770_rdi0_reg_data, + }, + { + .rdi_reg = &tfe770_rdi1_reg, + .reg_data = &tfe770_rdi1_reg_data, + }, + { + .rdi_reg = &tfe770_rdi2_reg, + .reg_data = &tfe770_rdi2_reg_data, + }, + }, + .ppp_hw_info = { + .ppp_reg = &tfe770_ppp_reg, + .reg_data = &tfe770_ppp_reg_data, + }, + .in_port = { + CAM_TFE_CAMIF_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_PDLIB_VER_1_0 + }, + .reg_dump_data = { + .num_reg_dump_entries = 19, + .num_lut_dump_entries = 0, + .bus_start_addr = 0x2000, + .bus_write_top_end_addr = 0x2120, + .bus_client_start_addr = 0x2200, + .bus_client_offset = 0x100, + .num_bus_clients = 10, + .reg_entry = { + { + .start_offset = 0x1000, + .end_offset = 0x10F4, + }, + { + .start_offset = 0x1260, + .end_offset = 0x1280, + }, + { + .start_offset = 0x13F0, + .end_offset = 0x13FC, + }, + { + .start_offset = 0x1460, + .end_offset = 0x1470, + }, + { + .start_offset = 0x15F0, + .end_offset = 0x15FC, + }, + { + .start_offset = 0x1660, + .end_offset = 0x1670, + }, + { + .start_offset = 0x17F0, + .end_offset = 0x17FC, + }, + { + .start_offset = 0x1860, + .end_offset = 0x1870, + }, + { + .start_offset = 0x19F0, + .end_offset = 0x19FC, + }, + { + .start_offset = 0x2660, + .end_offset = 0x2694, + }, + { + .start_offset = 0x2860, + .end_offset = 0x2884, + }, + { + .start_offset = 0x2A60, + .end_offset = 0X2B34, + }, + { + .start_offset = 0x2C60, + .end_offset = 0X2C80, + }, + { + .start_offset = 0x2E60, + .end_offset = 0X2E7C, + }, + { + .start_offset = 0x3060, + .end_offset = 0X3110, + }, + { + .start_offset = 0x3260, + .end_offset = 0X3278, + }, + { + .start_offset = 0x3460, + .end_offset = 0X3478, + }, + { + .start_offset = 0x3660, + .end_offset = 0X3684, + }, + { + .start_offset = 0x3860, + .end_offset = 0X3884, + }, + }, + .lut_entry = { + { + .lut_word_size = 1, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + .dmi_reg_offset = 0x2800, + }, + { + .lut_word_size = 1, + .lut_bank_sel = 0x41, + .lut_addr_size = 180, + .dmi_reg_offset = 0x3000, + }, + }, + }, + .num_path_port_map = 3, + .path_port_map = { + {CAM_ISP_HW_TFE_IN_PDLIB, CAM_ISP_TFE_OUT_RES_PD_LCR_STATS}, + {CAM_ISP_HW_TFE_IN_PDLIB, CAM_ISP_TFE_OUT_RES_PD_PREPROCESSED}, + {CAM_ISP_HW_TFE_IN_PDLIB, CAM_ISP_TFE_OUT_RES_PD_PARSED}, + }, +}; + +static struct cam_tfe_bus_hw_info tfe770_bus_hw_info = { + .common_reg = { + .hw_version = 0x00003000, + .cgc_ovd = 0x00003008, + .comp_cfg_0 = 0x0000300C, + .comp_cfg_1 = 0x00003010, + .frameheader_cfg = { + 0x00003034, + 0x00003038, + 0x0000303C, + 0x00003040, + }, + .pwr_iso_cfg = 0x0000305C, + .overflow_status_clear = 0x00003060, + .ccif_violation_status = 0x00003064, + .overflow_status = 0x00003068, + .image_size_violation_status = 0x00003070, + .perf_count_cfg = { + 0x00003074, + 0x00003078, + 0x0000307C, + 0x00003080, + 0x00003084, + 0x00003088, + 0x0000308C, + 0x00003090, + }, + .perf_count_val = { + 0x00003094, + 0x00003098, + 0x0000309C, + 0x000030A0, + 0x000030A4, + 0x000030A8, + 0x000030AC, + 0x000030B0, + }, + .perf_count_status = 0x000030B4, + .debug_status_top_cfg = 0x000030D4, + .debug_status_top = 0x000030D8, + .test_bus_ctrl = 0x000030DC, + .irq_mask = { + 0x00003018, + 0x0000301C, + }, + .irq_clear = { + 0x00003020, + 0x00003024, + }, + .irq_status = { + 0x00003028, + 0x0000302C, + }, + .irq_cmd = 0x00003030, + .cons_violation_shift = 28, + .violation_shift = 30, + .image_size_violation = 31, + }, + .num_client = 19, + .bus_client_reg = { + /* BUS Client 0 BAYER */ + { + .cfg = 0x00003200, + .image_addr = 0x00003204, + .frame_incr = 0x00003208, + .image_cfg_0 = 0x0000320C, + .image_cfg_1 = 0x00003210, + .image_cfg_2 = 0x00003214, + .packer_cfg = 0x00003218, + .bw_limit = 0x0000321C, + .frame_header_addr = 0x00003220, + .frame_header_incr = 0x00003224, + .frame_header_cfg = 0x00003228, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003230, + .irq_subsample_pattern = 0x00003234, + .framedrop_period = 0x00003238, + .framedrop_pattern = 0x0000323C, + .system_cache_cfg = 0x00003260, + .addr_status_0 = 0x00003268, + .addr_status_1 = 0x0000326C, + .addr_status_2 = 0x00003270, + .addr_status_3 = 0x00003274, + .debug_status_cfg = 0x00003278, + .debug_status_0 = 0x0000327C, + .debug_status_1 = 0x00003280, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "BAYER", + }, + /* BUS Client 1 IDEAL RAW*/ + { + .cfg = 0x00003300, + .image_addr = 0x00003304, + .frame_incr = 0x00003308, + .image_cfg_0 = 0x0000330C, + .image_cfg_1 = 0x00003310, + .image_cfg_2 = 0x00003314, + .packer_cfg = 0x00003318, + .bw_limit = 0x0000331C, + .frame_header_addr = 0x00003320, + .frame_header_incr = 0x00003324, + .frame_header_cfg = 0x00003328, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003330, + .irq_subsample_pattern = 0x00003334, + .framedrop_period = 0x00003338, + .framedrop_pattern = 0x0000333C, + .system_cache_cfg = 0x00003360, + .addr_status_0 = 0x00003368, + .addr_status_1 = 0x0000336C, + .addr_status_2 = 0x00003370, + .addr_status_3 = 0x00003374, + .debug_status_cfg = 0x00003378, + .debug_status_0 = 0x0000337C, + .debug_status_1 = 0x00003380, + .comp_group = CAM_TFE_BUS_COMP_GRP_1, + .client_name = "IDEAL_RAW", + }, + /* BUS Client 2 Stats BE Tintless */ + { + .cfg = 0x00003400, + .image_addr = 0x00003404, + .frame_incr = 0x00003408, + .image_cfg_0 = 0x0000340C, + .image_cfg_1 = 0x00003410, + .image_cfg_2 = 0x00003414, + .packer_cfg = 0x00003418, + .bw_limit = 0x0000341C, + .frame_header_addr = 0x00003420, + .frame_header_incr = 0x00003424, + .frame_header_cfg = 0x00003428, + .line_done_cfg = 0x00003400, + .irq_subsample_period = 0x00003430, + .irq_subsample_pattern = 0x00003434, + .framedrop_period = 0x00003438, + .framedrop_pattern = 0x0000343C, + .system_cache_cfg = 0x00003460, + .addr_status_0 = 0x00003468, + .addr_status_1 = 0x0000346C, + .addr_status_2 = 0x00003470, + .addr_status_3 = 0x00003474, + .debug_status_cfg = 0x00003478, + .debug_status_0 = 0x0000347C, + .debug_status_1 = 0x00003480, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BE TINTLESS", + }, + /* BUS Client 3 Stats Bhist */ + { + .cfg = 0x00003500, + .image_addr = 0x00003504, + .frame_incr = 0x00003508, + .image_cfg_0 = 0x0000350C, + .image_cfg_1 = 0x00003510, + .image_cfg_2 = 0x00003514, + .packer_cfg = 0x00003518, + .bw_limit = 0x0000351C, + .frame_header_addr = 0x00003520, + .frame_header_incr = 0x00003524, + .frame_header_cfg = 0x00003528, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003530, + .irq_subsample_pattern = 0x00003534, + .framedrop_period = 0x00003538, + .framedrop_pattern = 0x0000353C, + .system_cache_cfg = 0x00003560, + .addr_status_0 = 0x00003568, + .addr_status_1 = 0x0000356C, + .addr_status_2 = 0x00003570, + .addr_status_3 = 0x00003574, + .debug_status_cfg = 0x00003578, + .debug_status_0 = 0x0000357C, + .debug_status_1 = 0x00003580, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BHIST", + }, + /* BUS Client 4 Stats AWB BG */ + { + .cfg = 0x00003600, + .image_addr = 0x00003604, + .frame_incr = 0x00003608, + .image_cfg_0 = 0x0000360C, + .image_cfg_1 = 0x00003610, + .image_cfg_2 = 0x00003614, + .packer_cfg = 0x00003618, + .bw_limit = 0x0000361C, + .frame_header_addr = 0x00003620, + .frame_header_incr = 0x00003624, + .frame_header_cfg = 0x00003628, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003630, + .irq_subsample_pattern = 0x00003634, + .framedrop_period = 0x00003638, + .framedrop_pattern = 0x0000363C, + .system_cache_cfg = 0x00003660, + .addr_status_0 = 0x00003668, + .addr_status_1 = 0x0000366C, + .addr_status_2 = 0x00003670, + .addr_status_3 = 0x00003674, + .debug_status_cfg = 0x00003678, + .debug_status_0 = 0x0000367C, + .debug_status_1 = 0x00003680, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AWB BG", + }, + /* BUS Client 5 Stats AEC BG */ + { + .cfg = 0x00003700, + .image_addr = 0x00003704, + .frame_incr = 0x00003708, + .image_cfg_0 = 0x0000370C, + .image_cfg_1 = 0x00003710, + .image_cfg_2 = 0x00003714, + .packer_cfg = 0x00003718, + .bw_limit = 0x0000371C, + .frame_header_addr = 0x00003720, + .frame_header_incr = 0x00003724, + .frame_header_cfg = 0x00003728, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003730, + .irq_subsample_pattern = 0x00003734, + .framedrop_period = 0x00003738, + .framedrop_pattern = 0x0000373C, + .system_cache_cfg = 0x00003760, + .addr_status_0 = 0x00003768, + .addr_status_1 = 0x0000376C, + .addr_status_2 = 0x00003770, + .addr_status_3 = 0x00003774, + .debug_status_cfg = 0x00003778, + .debug_status_0 = 0x0000377C, + .debug_status_1 = 0x00003780, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AEC BG", + }, + /* BUS Client 6 Stats BAF */ + { + .cfg = 0x00003800, + .image_addr = 0x00003804, + .frame_incr = 0x00003808, + .image_cfg_0 = 0x0000380C, + .image_cfg_1 = 0x00003810, + .image_cfg_2 = 0x00003814, + .packer_cfg = 0x00003818, + .bw_limit = 0x0000381C, + .frame_header_addr = 0x00003820, + .frame_header_incr = 0x00003824, + .frame_header_cfg = 0x00003828, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003830, + .irq_subsample_pattern = 0x00003834, + .framedrop_period = 0x00003838, + .framedrop_pattern = 0x0000383C, + .system_cache_cfg = 0x00003860, + .addr_status_0 = 0x00003868, + .addr_status_1 = 0x0000386C, + .addr_status_2 = 0x00003870, + .addr_status_3 = 0x00003874, + .debug_status_cfg = 0x00003878, + .debug_status_0 = 0x0000387C, + .debug_status_1 = 0x00003880, + .comp_group = CAM_TFE_BUS_COMP_GRP_4, + .client_name = "STATS BAF", + }, + /* BUS Client 7 RDI0 */ + { + .cfg = 0x00003900, + .image_addr = 0x00003904, + .frame_incr = 0x00003908, + .image_cfg_0 = 0x0000390C, + .image_cfg_1 = 0x00003910, + .image_cfg_2 = 0x00003914, + .packer_cfg = 0x00003918, + .bw_limit = 0x0000391C, + .frame_header_addr = 0x00003920, + .frame_header_incr = 0x00003924, + .frame_header_cfg = 0x00003928, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003930, + .irq_subsample_pattern = 0x00003934, + .framedrop_period = 0x00003938, + .framedrop_pattern = 0x0000393C, + .system_cache_cfg = 0x00003960, + .addr_status_0 = 0x00003968, + .addr_status_1 = 0x0000396C, + .addr_status_2 = 0x00003970, + .addr_status_3 = 0x00003974, + .debug_status_cfg = 0x00003978, + .debug_status_0 = 0x0000397C, + .debug_status_1 = 0x00003980, + .comp_group = CAM_TFE_BUS_COMP_GRP_5, + .client_name = "RDI0", + }, + /* BUS Client 8 RDI1 */ + { + .cfg = 0x00003A00, + .image_addr = 0x00003A04, + .frame_incr = 0x00003A08, + .image_cfg_0 = 0x00003A0C, + .image_cfg_1 = 0x00003A10, + .image_cfg_2 = 0x00003A14, + .packer_cfg = 0x00003A18, + .bw_limit = 0x00003A1C, + .frame_header_addr = 0x00003A20, + .frame_header_incr = 0x00003A24, + .frame_header_cfg = 0x00003A28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003A30, + .irq_subsample_pattern = 0x00003A34, + .framedrop_period = 0x00003A38, + .framedrop_pattern = 0x00003A3C, + .system_cache_cfg = 0x00003A60, + .addr_status_0 = 0x00003A68, + .addr_status_1 = 0x00003A6C, + .addr_status_2 = 0x00003A70, + .addr_status_3 = 0x00003A74, + .debug_status_cfg = 0x00003A78, + .debug_status_0 = 0x00003A7C, + .debug_status_1 = 0x00003A80, + .comp_group = CAM_TFE_BUS_COMP_GRP_6, + .client_name = "RDI1", + }, + /* BUS Client 9 RDI2 */ + { + .cfg = 0x00003B00, + .image_addr = 0x00003B04, + .frame_incr = 0x00003B08, + .image_cfg_0 = 0x00003B0C, + .image_cfg_1 = 0x00003B10, + .image_cfg_2 = 0x00003B14, + .packer_cfg = 0x00003B18, + .bw_limit = 0x00003B1C, + .frame_header_addr = 0x00003B20, + .frame_header_incr = 0x00003B24, + .frame_header_cfg = 0x00003B28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003B30, + .irq_subsample_pattern = 0x00003B34, + .framedrop_period = 0x00003B38, + .framedrop_pattern = 0x00003B3C, + .system_cache_cfg = 0x00003B60, + .addr_status_0 = 0x00003B68, + .addr_status_1 = 0x00003B6C, + .addr_status_2 = 0x00003B70, + .addr_status_3 = 0x00003B74, + .debug_status_cfg = 0x00003B78, + .debug_status_0 = 0x00003B7C, + .debug_status_1 = 0x00003B80, + .comp_group = CAM_TFE_BUS_COMP_GRP_7, + .client_name = "RDI2", + }, + /* BUS Client 10 PDAF */ + { + .cfg = 0x00003C00, + .image_addr = 0x00003C04, + .frame_incr = 0x00003C08, + .image_cfg_0 = 0x00003C0C, + .image_cfg_1 = 0x00003C10, + .image_cfg_2 = 0x00003C14, + .packer_cfg = 0x00003C18, + .bw_limit = 0x00003C1C, + .frame_header_addr = 0x00003C20, + .frame_header_incr = 0x00003C24, + .frame_header_cfg = 0x00003C28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003C30, + .irq_subsample_pattern = 0x00003C34, + .framedrop_period = 0x00003C38, + .framedrop_pattern = 0x00003C3C, + .system_cache_cfg = 0x00003C60, + .addr_status_0 = 0x00003C68, + .addr_status_1 = 0x00003C6C, + .addr_status_2 = 0x00003C70, + .addr_status_3 = 0x00003C74, + .debug_status_cfg = 0x00003C78, + .debug_status_0 = 0x00003C7C, + .debug_status_1 = 0x00003C80, + .comp_group = CAM_TFE_BUS_COMP_GRP_8, + .client_name = "PDAF", + }, + /* BUS Client 11 DS4 */ + { + .cfg = 0x00003D00, + .image_addr = 0x00003D04, + .frame_incr = 0x00003D08, + .image_cfg_0 = 0x00003D0C, + .image_cfg_1 = 0x00003D10, + .image_cfg_2 = 0x00003D14, + .packer_cfg = 0x00003D18, + .bw_limit = 0x00003D1C, + .frame_header_addr = 0x00003D20, + .frame_header_incr = 0x00003D24, + .frame_header_cfg = 0x00003D28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003D30, + .irq_subsample_pattern = 0x00003D34, + .framedrop_period = 0x00003D38, + .framedrop_pattern = 0x00003D3C, + .system_cache_cfg = 0x00003D60, + .addr_status_0 = 0x00003D68, + .addr_status_1 = 0x00003D6C, + .addr_status_2 = 0x00003D70, + .addr_status_3 = 0x00003D74, + .debug_status_cfg = 0x00003D78, + .debug_status_0 = 0x00003D7C, + .debug_status_1 = 0x00003D80, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "DS4", + }, + /* BUS Client 12 DS16 */ + { + .cfg = 0x00003E00, + .image_addr = 0x00003E04, + .frame_incr = 0x00003E08, + .image_cfg_0 = 0x00003E0C, + .image_cfg_1 = 0x00003E10, + .image_cfg_2 = 0x00003E14, + .packer_cfg = 0x00003E18, + .bw_limit = 0x00003E1C, + .frame_header_addr = 0x00003E20, + .frame_header_incr = 0x00003E24, + .frame_header_cfg = 0x00003E28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003E30, + .irq_subsample_pattern = 0x00003E34, + .framedrop_period = 0x00003E38, + .framedrop_pattern = 0x00003E3C, + .system_cache_cfg = 0x00003E60, + .addr_status_0 = 0x00003E68, + .addr_status_1 = 0x00003E6C, + .addr_status_2 = 0x00003E70, + .addr_status_3 = 0x00003E74, + .debug_status_cfg = 0x00003E78, + .debug_status_0 = 0x00003E7C, + .debug_status_1 = 0x00003E80, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "DS16", + }, + /* BUS Client 13 AI-Y */ + { + .cfg = 0x00003F00, + .image_addr = 0x00003F04, + .frame_incr = 0x00003F08, + .image_cfg_0 = 0x00003F0C, + .image_cfg_1 = 0x00003F10, + .image_cfg_2 = 0x00003F14, + .packer_cfg = 0x00003F18, + .bw_limit = 0x00003F1C, + .frame_header_addr = 0x00003F20, + .frame_header_incr = 0x00003F24, + .frame_header_cfg = 0x00003F28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003F30, + .irq_subsample_pattern = 0x00003F34, + .framedrop_period = 0x00003F38, + .framedrop_pattern = 0x00003F3C, + .system_cache_cfg = 0x00003F60, + .addr_status_0 = 0x00003F68, + .addr_status_1 = 0x00003F6C, + .addr_status_2 = 0x00003F70, + .addr_status_3 = 0x00003F74, + .debug_status_cfg = 0x00003F78, + .debug_status_0 = 0x00003F7C, + .debug_status_1 = 0x00003F80, + .comp_group = CAM_TFE_BUS_COMP_GRP_9, + .client_name = "AI-Y", + }, + /* BUS Client 14 AI-C */ + { + .cfg = 0x00004000, + .image_addr = 0x00004004, + .frame_incr = 0x00004008, + .image_cfg_0 = 0x0000400C, + .image_cfg_1 = 0x00004010, + .image_cfg_2 = 0x00004014, + .packer_cfg = 0x00004018, + .bw_limit = 0x0000401C, + .frame_header_addr = 0x00004020, + .frame_header_incr = 0x00004024, + .frame_header_cfg = 0x00004028, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004030, + .irq_subsample_pattern = 0x00004034, + .framedrop_period = 0x00004038, + .framedrop_pattern = 0x0000403C, + .system_cache_cfg = 0x00004060, + .addr_status_0 = 0x00004068, + .addr_status_1 = 0x0000406C, + .addr_status_2 = 0x00004070, + .addr_status_3 = 0x00004074, + .debug_status_cfg = 0x00004078, + .debug_status_0 = 0x0000407C, + .debug_status_1 = 0x00004080, + .comp_group = CAM_TFE_BUS_COMP_GRP_9, + .client_name = "AI-C", + }, + /* BUS Client 15 Stats RS */ + { + .cfg = 0x00004100, + .image_addr = 0x00004104, + .frame_incr = 0x00004108, + .image_cfg_0 = 0x0000410C, + .image_cfg_1 = 0x00004110, + .image_cfg_2 = 0x00004114, + .packer_cfg = 0x00004118, + .bw_limit = 0x0000411C, + .frame_header_addr = 0x00004120, + .frame_header_incr = 0x00004124, + .frame_header_cfg = 0x00004128, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004130, + .irq_subsample_pattern = 0x00004134, + .framedrop_period = 0x00004138, + .framedrop_pattern = 0x0000413C, + .system_cache_cfg = 0x00004160, + .addr_status_0 = 0x00004168, + .addr_status_1 = 0x0000416C, + .addr_status_2 = 0x00004170, + .addr_status_3 = 0x00004174, + .debug_status_cfg = 0x00004178, + .debug_status_0 = 0x0000417C, + .debug_status_1 = 0x00004180, + .comp_group = CAM_TFE_BUS_COMP_GRP_10, + .client_name = "STATS RS", + }, + /* BUS Client 16 PDAF 0 STAT LCR */ + { + .cfg = 0x00004200, + .image_addr = 0x00004204, + .frame_incr = 0x00004208, + .image_cfg_0 = 0x0000420C, + .image_cfg_1 = 0x00004210, + .image_cfg_2 = 0x00004214, + .packer_cfg = 0x00004218, + .bw_limit = 0x0000421C, + .frame_header_addr = 0x00004220, + .frame_header_incr = 0x00004224, + .frame_header_cfg = 0x00004228, + .line_done_cfg = 0x0000422C, + .irq_subsample_period = 0x00004230, + .irq_subsample_pattern = 0x00004234, + .framedrop_period = 0x00004238, + .framedrop_pattern = 0x0000423C, + .system_cache_cfg = 0x00004260, + .addr_status_0 = 0x00004268, + .addr_status_1 = 0x0000426C, + .addr_status_2 = 0x00004270, + .addr_status_3 = 0x00004274, + .debug_status_cfg = 0x00004278, + .debug_status_0 = 0x0000427C, + .debug_status_1 = 0x00004280, + .comp_group = CAM_TFE_BUS_COMP_GRP_11, + .client_name = "STAT LCR", + }, + /* BUS Client 17 PDAF 1 PD PREPROCESSED*/ + { + .cfg = 0x00004300, + .image_addr = 0x00004304, + .frame_incr = 0x00004308, + .image_cfg_0 = 0x0000430C, + .image_cfg_1 = 0x00004310, + .image_cfg_2 = 0x00004314, + .packer_cfg = 0x00004318, + .bw_limit = 0x0000431C, + .frame_header_addr = 0x00004320, + .frame_header_incr = 0x00004324, + .frame_header_cfg = 0x00004328, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004330, + .irq_subsample_pattern = 0x00004334, + .framedrop_period = 0x00004338, + .framedrop_pattern = 0x0000433C, + .system_cache_cfg = 0x00004360, + .addr_status_0 = 0x00004368, + .addr_status_1 = 0x0000436C, + .addr_status_2 = 0x00004370, + .addr_status_3 = 0x00004374, + .debug_status_cfg = 0x00004378, + .debug_status_0 = 0x0000437C, + .debug_status_1 = 0x00004380, + .comp_group = CAM_TFE_BUS_COMP_GRP_11, + .client_name = "PD PREPROCESSED", + }, + /* BUS Client 18 PDAF 2 PD PARSED*/ + { + .cfg = 0x00004400, + .image_addr = 0x00004404, + .frame_incr = 0x00004408, + .image_cfg_0 = 0x0000440C, + .image_cfg_1 = 0x00004410, + .image_cfg_2 = 0x00004414, + .packer_cfg = 0x00004418, + .bw_limit = 0x0000441C, + .frame_header_addr = 0x00004420, + .frame_header_incr = 0x00004424, + .frame_header_cfg = 0x00004428, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00004430, + .irq_subsample_pattern = 0x00004434, + .framedrop_period = 0x00004438, + .framedrop_pattern = 0x0000443C, + .system_cache_cfg = 0x00004460, + .addr_status_0 = 0x00004468, + .addr_status_1 = 0x0000446C, + .addr_status_2 = 0x00004470, + .addr_status_3 = 0x00004474, + .debug_status_cfg = 0x00004478, + .debug_status_0 = 0x0000447C, + .debug_status_1 = 0x00004480, + .comp_group = CAM_TFE_BUS_COMP_GRP_11, + .client_name = "PD PARSED", + }, + }, + .num_out = 18, + .tfe_out_hw_info = { + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_5, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_1, + .mid[0] = 16, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_6, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_2, + .mid[0] = 17, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_7, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_3, + .mid[0] = 18, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 16, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RAW_DUMP, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_1, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 19, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PDAF, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_8, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 26, + .pid_mask = 0x700, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 20, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 18, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 17, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 19, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_4, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 21, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_RS, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_10, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 27, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_DS4, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 22, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_DS16, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 23, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_AI, + .max_width = 1920, + .max_height = 1920, + .composite_group = CAM_TFE_BUS_COMP_GRP_9, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + .mid[0] = 24, + .mid[1] = 25, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PD_LCR_STATS, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_11, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_4, + .mid[0] = 21, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PD_PREPROCESSED, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_11, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_4, + .mid[0] = 20, + .pid_mask = 0x70, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PD_PARSED, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_11, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_4, + .mid[0] = 22, + .pid_mask = 0x70, + }, + }, + .num_comp_grp = 12, + .max_wm_per_comp_grp = 3, + .comp_done_shift = 8, + .top_bus_wr_irq_shift = 1, + .comp_buf_done_mask = 0xFFF00, + .comp_rup_done_mask = 0xF, + .bus_irq_error_mask = { + 0xD0000000, + 0x00000000, + }, + .support_consumed_addr = true, + .pdaf_rdi2_mux_en = false, + .rdi_width = 128, + .mode_cfg_shift = 16, + .height_shift = 16, + .max_out_res = CAM_ISP_TFE_OUT_RES_MAX & 0xFF, +}; + +struct cam_tfe_hw_info cam_tfe770 = { + .top_irq_mask = { + 0x00001834, + 0x00001838, + 0x0000183C, + }, + .top_irq_clear = { + 0x00001840, + 0x00001844, + 0x00001848, + }, + .top_irq_status = { + 0x0000184C, + 0x00001850, + 0x00001854, + }, + .top_irq_cmd = 0x00001830, + .global_clear_bitmask = 0x00000001, + .bus_irq_mask = { + 0x00003018, + 0x0000301C, + }, + .bus_irq_clear = { + 0x00003020, + 0x00003024, + }, + .bus_irq_status = { + 0x00003028, + 0x0000302C, + }, + .bus_irq_cmd = 0x00003030, + .bus_violation_reg = 0x00003064, + .bus_overflow_reg = 0x00003068, + .bus_image_size_vilation_reg = 0x3070, + .bus_overflow_clear_cmd = 0x3060, + .debug_status_top = 0x30D8, + + .reset_irq_mask = { + 0x00000001, + 0x00000000, + 0x00000000, + }, + .error_irq_mask = { + 0x001F1F00, + 0x00000000, + 0x000002FF, + }, + .non_fatal_error_irq_mask = { + 0x00200000, + 0x00000000, + 0x00000000, + }, + .bus_reg_irq_mask = { + 0x00000002, + 0x00000000, + }, + .bus_error_irq_mask = { + 0xC0000000, + 0x00000000, + }, + + .num_clc = 39, + .clc_hw_status_info = tfe770_clc_hw_info, + .bus_version = CAM_TFE_BUS_1_0, + .bus_hw_info = &tfe770_bus_hw_info, + + .top_version = CAM_TFE_TOP_1_0, + .top_hw_info = &tfe770_top_hw_info, +}; + +#endif /* _CAM_TFE770__H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 5bb3ba9558..072b0f1b76 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -71,6 +71,8 @@ struct cam_tfe_bus_common_data { uint32_t num_sec_out; uint32_t comp_done_shift; uint32_t rdi_width; + uint32_t mode_cfg_shift; + uint32_t height_shift; bool is_lite; bool support_consumed_addr; cam_hw_mgr_event_cb_func event_cb; @@ -79,6 +81,7 @@ struct cam_tfe_bus_common_data { uint32_t max_bw_counter_limit; uint32_t counter_limit_shift; uint32_t counter_limit_mask; + uint32_t pack_align_shift; }; struct cam_tfe_bus_wm_resource_data { @@ -108,7 +111,12 @@ struct cam_tfe_bus_wm_resource_data { uint32_t acquired_width; uint32_t acquired_height; uint32_t acquired_stride; + + uint32_t buffer_offset; + bool is_buffer_aligned; bool limiter_blob_status; + + bool is_dim_update; }; struct cam_tfe_bus_comp_grp_data { @@ -152,6 +160,7 @@ struct cam_tfe_bus_tfe_out_data { void *priv; cam_hw_mgr_event_cb_func event_cb; uint32_t mid[CAM_TFE_BUS_MAX_MID_PER_PORT]; + uint64_t pid_mask; }; struct cam_tfe_bus_priv { @@ -173,6 +182,7 @@ struct cam_tfe_bus_priv { uint32_t comp_buf_done_mask; uint32_t comp_rup_done_mask; uint32_t bus_irq_error_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t max_out_res; }; static bool cam_tfe_bus_can_be_secure(uint32_t out_id) @@ -186,6 +196,9 @@ static bool cam_tfe_bus_can_be_secure(uint32_t out_id) case CAM_TFE_BUS_TFE_OUT_DS4: case CAM_TFE_BUS_TFE_OUT_DS16: case CAM_TFE_BUS_TFE_OUT_AI: + case CAM_TFE_BUS_TFE_OUT_PD_LCR_STATS: + case CAM_TFE_BUS_TFE_OUT_PD_PREPROCESSED: + case CAM_TFE_BUS_TFE_OUT_PD_PARSED: return true; case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE: @@ -233,6 +246,12 @@ static enum cam_tfe_bus_tfe_out_id return CAM_TFE_BUS_TFE_OUT_DS16; case CAM_ISP_TFE_OUT_RES_AI: return CAM_TFE_BUS_TFE_OUT_AI; + case CAM_ISP_TFE_OUT_RES_PD_LCR_STATS: + return CAM_TFE_BUS_TFE_OUT_PD_LCR_STATS; + case CAM_ISP_TFE_OUT_RES_PD_PREPROCESSED: + return CAM_TFE_BUS_TFE_OUT_PD_PREPROCESSED; + case CAM_ISP_TFE_OUT_RES_PD_PARSED: + return CAM_TFE_BUS_TFE_OUT_PD_PARSED; default: return CAM_TFE_BUS_TFE_OUT_MAX; } @@ -323,7 +342,7 @@ static int cam_tfe_bus_get_num_wm( switch (format) { case CAM_FORMAT_NV12: case CAM_FORMAT_TP10: - case CAM_FORMAT_PD10: + case CAM_FORMAT_PLAIN16_10: return 2; default: break; @@ -350,6 +369,17 @@ static int cam_tfe_bus_get_num_wm( break; } break; + case CAM_TFE_BUS_TFE_OUT_PD_LCR_STATS: + case CAM_TFE_BUS_TFE_OUT_PD_PREPROCESSED: + case CAM_TFE_BUS_TFE_OUT_PD_PARSED: + switch (format) { + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN64: + return 1; + default: + break; + } + break; default: break; } @@ -360,6 +390,47 @@ static int cam_tfe_bus_get_num_wm( return -EINVAL; } +static int cam_tfe_lite_bus_get_wm_idx( + enum cam_tfe_bus_tfe_out_id tfe_out_res_id, + enum cam_tfe_bus_plane_type plane) +{ + int wm_idx = -1; + + switch (tfe_out_res_id) { + case CAM_TFE_BUS_TFE_OUT_RDI0: + switch (plane) { + case PLANE_Y: + wm_idx = 0; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RDI1: + switch (plane) { + case PLANE_Y: + wm_idx = 1; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RDI2: + switch (plane) { + case PLANE_Y: + wm_idx = 2; + break; + default: + break; + } + break; + default: + break; + } + + return wm_idx; +} + static int cam_tfe_bus_get_wm_idx( enum cam_tfe_bus_tfe_out_id tfe_out_res_id, enum cam_tfe_bus_plane_type plane, @@ -510,6 +581,33 @@ static int cam_tfe_bus_get_wm_idx( break; } break; + case CAM_TFE_BUS_TFE_OUT_PD_LCR_STATS: + switch (plane) { + case PLANE_Y: + wm_idx = 16; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_PD_PREPROCESSED: + switch (plane) { + case PLANE_Y: + wm_idx = 17; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_PD_PARSED: + switch (plane) { + case PLANE_Y: + wm_idx = 18; + break; + default: + break; + } + break; default: break; } @@ -561,6 +659,7 @@ static int cam_tfe_bus_acquire_rdi_wm( { int pack_fmt = 0; int rdi_width = rsrc_data->common_data->rdi_width; + int mode_cfg_shift = rsrc_data->common_data->mode_cfg_shift; if (rdi_width == 64) pack_fmt = 0xa; @@ -581,7 +680,7 @@ static int cam_tfe_bus_acquire_rdi_wm( rsrc_data->height = 0; rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << mode_cfg_shift) | 0x1; } break; case CAM_FORMAT_MIPI_RAW_8: @@ -598,7 +697,7 @@ static int cam_tfe_bus_acquire_rdi_wm( rsrc_data->height = 0; rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << mode_cfg_shift) | 0x1; } break; case CAM_FORMAT_MIPI_RAW_10: @@ -614,7 +713,7 @@ static int cam_tfe_bus_acquire_rdi_wm( rsrc_data->height = 0; rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << mode_cfg_shift) | 0x1; } break; case CAM_FORMAT_MIPI_RAW_12: @@ -630,7 +729,7 @@ static int cam_tfe_bus_acquire_rdi_wm( rsrc_data->height = 0; rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << mode_cfg_shift) | 0x1; } break; case CAM_FORMAT_MIPI_RAW_14: @@ -646,7 +745,7 @@ static int cam_tfe_bus_acquire_rdi_wm( rsrc_data->height = 0; rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << mode_cfg_shift) | 0x1; } break; case CAM_FORMAT_PLAIN16_10: @@ -666,7 +765,7 @@ static int cam_tfe_bus_acquire_rdi_wm( rsrc_data->height = 0; rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << mode_cfg_shift) | 0x1; } break; @@ -684,7 +783,7 @@ static int cam_tfe_bus_acquire_rdi_wm( rsrc_data->height = 0; rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << mode_cfg_shift) | 0x1; } break; default: @@ -711,14 +810,16 @@ static int cam_tfe_bus_acquire_wm( struct cam_tfe_bus_wm_resource_data *rsrc_data = NULL; uint32_t wm_idx = 0; int rc = 0; - *wm_res = NULL; /* No need to allocate for BUS TFE OUT to WM is fixed. */ - wm_idx = cam_tfe_bus_get_wm_idx(tfe_out_res_id, plane, - bus_priv->common_data.pdaf_rdi2_mux_en); + if (bus_priv->common_data.is_lite) + wm_idx = cam_tfe_lite_bus_get_wm_idx(tfe_out_res_id, plane); + else + wm_idx = cam_tfe_bus_get_wm_idx(tfe_out_res_id, plane, + bus_priv->common_data.pdaf_rdi2_mux_en); if (wm_idx < 0 || wm_idx >= bus_priv->num_client) { - CAM_ERR(CAM_ISP, "Unsupported TFE out %d plane %d", - tfe_out_res_id, plane); + CAM_ERR(CAM_ISP, "Unsupported TFE out %d plane %d wm id %d num client %d", + tfe_out_res_id, plane, wm_idx, bus_priv->num_client); return -EINVAL; } @@ -754,8 +855,8 @@ static int cam_tfe_bus_acquire_wm( /* Set WM offset value to default */ rsrc_data->offset = 0; - if (((rsrc_data->index >= 7) && (rsrc_data->index <= 9)) && - (tfe_out_res_id != CAM_TFE_BUS_TFE_OUT_PDAF)) { + if (bus_priv->common_data.is_lite || (((rsrc_data->index >= 7) && + (rsrc_data->index <= 9)) && (tfe_out_res_id != CAM_TFE_BUS_TFE_OUT_PDAF))) { /* WM 7-9 refers to RDI 0/ RDI 1/RDI 2 */ rc = cam_tfe_bus_acquire_rdi_wm(rsrc_data); if (rc) @@ -781,6 +882,21 @@ static int cam_tfe_bus_acquire_wm( case CAM_FORMAT_PLAIN16_10: rsrc_data->pack_fmt = 0x5; rsrc_data->pack_fmt |= 0x10; + + /* AI port */ + if (rsrc_data->index == 13 || rsrc_data->index == 14) { + rsrc_data->pack_fmt = 0x5; + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + } break; case CAM_FORMAT_PLAIN16_12: rsrc_data->pack_fmt = 0x6; @@ -818,11 +934,52 @@ static int cam_tfe_bus_acquire_wm( rsrc_data->width = 0; rsrc_data->height = 0; rsrc_data->stride = 1; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; + rsrc_data->en_cfg = (0x1 << rsrc_data->common_data->mode_cfg_shift) | 0x1; /*RS state packet format*/ if (rsrc_data->index == 15) rsrc_data->pack_fmt = 0x9; + } else if (rsrc_data->index == 16) { + /* LCR */ + switch (rsrc_data->format) { + case CAM_FORMAT_PLAIN64: + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 1; + rsrc_data->en_cfg = (0x1 << rsrc_data->common_data->mode_cfg_shift) | 0x1; + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d out_type:%d index: %d", + rsrc_data->format, tfe_out_res_id, rsrc_data->index); + return -EINVAL; + } + } else if (rsrc_data->index == 17) { + /* PD_PREPROCESSED */ + switch (rsrc_data->format) { + case CAM_FORMAT_PLAIN16_10: + rsrc_data->stride = ALIGNUP(rsrc_data->width * 2, 8); + rsrc_data->en_cfg = 0x1; + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d out_type:%d index: %d", + rsrc_data->format, tfe_out_res_id, rsrc_data->index); + return -EINVAL; + } + } else if (rsrc_data->index == 18) { + /* PD PARSED */ + switch (rsrc_data->format) { + case CAM_FORMAT_PLAIN16_10: + rsrc_data->stride = ALIGNUP(rsrc_data->width * 2, 8); + rsrc_data->en_cfg = 0x1; + /* LSB aligned */ + rsrc_data->pack_fmt |= (1 << + bus_priv->common_data.pack_align_shift); + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d out_type:%d index: %d", + rsrc_data->format, tfe_out_res_id, rsrc_data->index); + return -EINVAL; + } } else { CAM_ERR(CAM_ISP, "Invalid WM:%d requested", rsrc_data->index); return -EINVAL; @@ -859,6 +1016,8 @@ static int cam_tfe_bus_release_wm(void *bus_priv, rsrc_data->en_cfg = 0; rsrc_data->is_dual = 0; rsrc_data->limiter_blob_status = false; + rsrc_data->is_buffer_aligned = false; + rsrc_data->buffer_offset = 0; wm_res->tasklet_info = NULL; wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; @@ -875,13 +1034,14 @@ static int cam_tfe_bus_start_wm(struct cam_isp_resource_node *wm_res) wm_res->res_priv; struct cam_tfe_bus_common_data *common_data = rsrc_data->common_data; + int height_shift = rsrc_data->common_data->height_shift; /* Skip to overwrite if wm bandwidth limiter blob already sent */ if (!rsrc_data->limiter_blob_status) cam_io_w(rsrc_data->common_data->counter_limit_mask, common_data->mem_base + rsrc_data->hw_regs->bw_limit); - cam_io_w((rsrc_data->height << 16) | rsrc_data->width, + cam_io_w((rsrc_data->height << height_shift) | rsrc_data->width, common_data->mem_base + rsrc_data->hw_regs->image_cfg_0); cam_io_w(rsrc_data->pack_fmt, common_data->mem_base + rsrc_data->hw_regs->packer_cfg); @@ -897,10 +1057,6 @@ static int cam_tfe_bus_start_wm(struct cam_isp_resource_node *wm_res) rsrc_data->stride); } - /* Enable WM */ - cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base + - rsrc_data->hw_regs->cfg); - CAM_DBG(CAM_ISP, "TFE:%d WM:%d width = %d, height = %d", common_data->core_index, rsrc_data->index, rsrc_data->width, rsrc_data->height); @@ -1271,7 +1427,10 @@ static int cam_tfe_bus_init_comp_grp(uint32_t index, INIT_LIST_HEAD(&comp_grp->list); comp_grp->res_id = index; - rsrc_data->comp_grp_id = index; + if (bus_priv->common_data.is_lite) + rsrc_data->comp_grp_id = hw_info->bus_client_reg[index].comp_group; + else + rsrc_data->comp_grp_id = index; rsrc_data->common_data = &bus_priv->common_data; rsrc_data->max_wm_per_comp_grp = bus_priv->max_wm_per_comp_grp; @@ -1697,6 +1856,8 @@ static int cam_tfe_bus_init_tfe_out_resource(uint32_t index, for (i = 0; i < CAM_TFE_BUS_MAX_MID_PER_PORT; i++) rsrc_data->mid[i] = hw_info->tfe_out_hw_info[index].mid[i]; + rsrc_data->pid_mask = hw_info->tfe_out_hw_info[index].pid_mask; + tfe_out->hw_intf = bus_priv->common_data.hw_intf; return 0; @@ -1745,6 +1906,8 @@ static const char *cam_tfe_bus_rup_type( return "RDI1 RUP"; case CAM_ISP_HW_TFE_IN_RDI2: return "RDI2 RUP"; + case CAM_ISP_HW_TFE_IN_PDLIB: + return "PDLIB RUP"; default: return "invalid rup group"; } @@ -1753,12 +1916,10 @@ static int cam_tfe_bus_rup_bottom_half( struct cam_tfe_bus_priv *bus_priv, struct cam_tfe_irq_evt_payload *evt_payload) { - struct cam_tfe_bus_common_data *common_data; - struct cam_tfe_bus_tfe_out_data *out_rsrc_data; + struct cam_tfe_bus_tfe_out_data *out_rsrc_data = NULL; struct cam_isp_hw_event_info evt_info; uint32_t i, j; - common_data = &bus_priv->common_data; evt_info.hw_idx = bus_priv->common_data.core_index; evt_info.res_type = CAM_ISP_RESOURCE_TFE_OUT; @@ -1768,17 +1929,20 @@ static int cam_tfe_bus_rup_bottom_half( break; if (evt_payload->bus_irq_val[0] & BIT(i)) { - for (j = 0; j < CAM_TFE_BUS_TFE_OUT_MAX; j++) { + for (j = 0; j < bus_priv->num_out; j++) { out_rsrc_data = (struct cam_tfe_bus_tfe_out_data *) bus_priv->tfe_out[j].res_priv; + if (!out_rsrc_data) + break; + if ((out_rsrc_data->rup_group_id == i) && (bus_priv->tfe_out[j].res_state == CAM_ISP_RESOURCE_STATE_STREAMING)) break; } - if (j == CAM_TFE_BUS_TFE_OUT_MAX) { + if (j == bus_priv->num_out) { CAM_ERR(CAM_ISP, "TFE:%d out rsc active status[0]:0x%x", bus_priv->common_data.core_index, @@ -1790,6 +1954,13 @@ static int cam_tfe_bus_rup_bottom_half( bus_priv->common_data.core_index, cam_tfe_bus_rup_type(i)); evt_info.res_id = i; + + if (!out_rsrc_data) { + CAM_ERR(CAM_ISP, + "out_rsrc_data null for out_res: %d, RUP_group: %d", + j, i); + break; + } if (out_rsrc_data->event_cb) { out_rsrc_data->event_cb( out_rsrc_data->priv, @@ -1816,13 +1987,15 @@ static uint32_t cam_tfe_bus_get_last_consumed_addr( struct cam_isp_resource_node *rsrc_node = NULL; struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; struct cam_tfe_bus_wm_resource_data *wm_rsrc_data = NULL; + enum cam_tfe_bus_tfe_out_id tfe_out_res_id; - if (out_id >= CAM_TFE_BUS_TFE_OUT_MAX) { + tfe_out_res_id = cam_tfe_bus_get_out_res_id(out_id); + if (tfe_out_res_id >= CAM_TFE_BUS_TFE_OUT_MAX) { CAM_ERR(CAM_ISP, "invalid out_id:%u", out_id); return 0; } - rsrc_node = &bus_priv->tfe_out[out_id]; + rsrc_node = &bus_priv->tfe_out[tfe_out_res_id]; rsrc_data = rsrc_node->res_priv; wm_rsrc_data = rsrc_data->wm_res[PLANE_Y]->res_priv; @@ -1830,6 +2003,9 @@ static uint32_t cam_tfe_bus_get_last_consumed_addr( wm_rsrc_data->common_data->mem_base + wm_rsrc_data->hw_regs->addr_status_0); + CAM_DBG(CAM_ISP, "TFE:%u res_type:0x%x res_id:0x%x last_consumed_addr:0x%x", + bus_priv->common_data.core_index, out_id, tfe_out_res_id, val); + return val; } @@ -1844,6 +2020,7 @@ static int cam_tfe_bus_bufdone_bottom_half( struct cam_tfe_bus_comp_grp_data *comp_rsrc_data; struct cam_isp_hw_bufdone_event_info bufdone_evt_info = {0}; uint32_t i; + struct cam_tfe_bus_wm_resource_data *wm_rsrc_data = NULL; common_data = &bus_priv->common_data; @@ -1855,31 +2032,31 @@ static int cam_tfe_bus_bufdone_bottom_half( comp_rsrc_data = (struct cam_tfe_bus_comp_grp_data *) bus_priv->comp_grp[i].res_priv; + CAM_DBG(CAM_ISP, "i: %d irq: 0x%x comm_done: 0x%x com_grp: %d", + i, evt_payload->bus_irq_val[0], bus_priv->common_data.comp_done_shift, + comp_rsrc_data->comp_grp_id); + if (evt_payload->bus_irq_val[0] & BIT(comp_rsrc_data->comp_grp_id + bus_priv->common_data.comp_done_shift)) { - out_rsrc = comp_rsrc_data->out_rsrc[0]; - out_rsrc_data = out_rsrc->res_priv; - evt_info.res_type = out_rsrc->res_type; - evt_info.hw_idx = out_rsrc->hw_intf->hw_idx; - evt_info.res_id = out_rsrc->res_id; - bufdone_evt_info.res_id = out_rsrc->res_id; - bufdone_evt_info.comp_grp_id = comp_rsrc_data->comp_grp_id; - bufdone_evt_info.last_consumed_addr = - cam_tfe_bus_get_last_consumed_addr( - out_rsrc_data->bus_priv, - out_rsrc_data->out_id); - evt_info.event_data = (void *)&bufdone_evt_info; + out_rsrc = comp_rsrc_data->out_rsrc[0]; + out_rsrc_data = out_rsrc->res_priv; + evt_info.res_type = out_rsrc->res_type; + evt_info.hw_idx = out_rsrc->hw_intf->hw_idx; + evt_info.res_id = out_rsrc->res_id; + bufdone_evt_info.res_id = out_rsrc->res_id; + bufdone_evt_info.comp_grp_id = comp_rsrc_data->comp_grp_id; + wm_rsrc_data = out_rsrc_data->wm_res[PLANE_Y]->res_priv; + bufdone_evt_info.last_consumed_addr = cam_io_r_mb( + wm_rsrc_data->common_data->mem_base + + wm_rsrc_data->hw_regs->addr_status_0); + evt_info.event_data = (void *)&bufdone_evt_info; - if (out_rsrc_data->event_cb) - out_rsrc_data->event_cb(out_rsrc_data->priv, - CAM_ISP_HW_EVENT_DONE, - (void *)&evt_info); + if (out_rsrc_data->event_cb) + out_rsrc_data->event_cb(out_rsrc_data->priv, + CAM_ISP_HW_EVENT_DONE, + (void *)&evt_info); } - - evt_payload->bus_irq_val[0] &= - BIT(comp_rsrc_data->comp_grp_id + - bus_priv->common_data.comp_done_shift); } return 0; @@ -2027,6 +2204,103 @@ end: } +static int cam_tfe_bus_update_wm_config(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_wm_cmd; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + struct cam_isp_tfe_wm_dimension_config *update_out_cfg; + uint32_t i, rc = 0; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + update_wm_cmd = (struct cam_isp_hw_get_cmd_update *) cmd_args; + update_out_cfg = (struct cam_isp_tfe_wm_dimension_config *) update_wm_cmd->data; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) update_wm_cmd->res->res_priv; + + if (!tfe_out_data) { + CAM_ERR(CAM_ISP, "Failed! invalid data"); + return -EINVAL; + } + + for (i = 0; i < tfe_out_data->num_wm; i++) { + wm_data = tfe_out_data->wm_res[i]->res_priv; + wm_data->is_dim_update = true; + wm_data->width = update_out_cfg->width; + wm_data->height = update_out_cfg->height; + CAM_DBG(CAM_ISP, "WM %d width %lld height %lld", wm_data->index, + wm_data->width, wm_data->height); + } + + return rc; +} + +static int cam_tfe_bus_diable_wm(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_buf; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + uint32_t *reg_val_pair; + uint32_t num_regval_pairs = 0; + uint32_t i, j, size = 0; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args; + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) update_buf->res->res_priv; + + if (!tfe_out_data || !(tfe_out_data->cdm_util_ops)) { + CAM_ERR(CAM_ISP, "Failed! invalid data"); + return -EINVAL; + } + + cdm_util_ops = tfe_out_data->cdm_util_ops; + + reg_val_pair = &tfe_out_data->common_data->io_buf_update[0]; + for (i = 0, j = 0; i < tfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + wm_data = tfe_out_data->wm_res[i]->res_priv; + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->cfg, 0); + CAM_DBG(CAM_ISP, "WM:%d disabled cfg %x", wm_data->index, wm_data->hw_regs->cfg); + } + + num_regval_pairs = j / 2; + + if (num_regval_pairs) { + size = cdm_util_ops->cdm_required_size_reg_random(num_regval_pairs); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_buf->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_buf->cmd.size, size); + return -ENOMEM; + } + + cdm_util_ops->cdm_write_regrandom( + update_buf->cmd.cmd_buf_addr, + num_regval_pairs, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_buf->cmd.used_bytes = size * 4; + } else { + update_buf->cmd.used_bytes = 0; + CAM_DBG(CAM_ISP, "No reg val pairs. num_wms: %u", tfe_out_data->num_wm); + } + + return 0; +} + static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, uint32_t arg_size) { @@ -2035,7 +2309,7 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, struct cam_buf_io_cfg *io_cfg; struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; struct cam_tfe_bus_wm_resource_data *wm_data = NULL; - struct cam_cdm_utils_ops *cdm_util_ops; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; uint32_t *reg_val_pair; uint32_t num_regval_pairs = 0; uint32_t i, j, size = 0; @@ -2047,13 +2321,13 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) update_buf->res->res_priv; - cdm_util_ops = tfe_out_data->cdm_util_ops; - - if (!tfe_out_data || !cdm_util_ops) { - CAM_ERR(CAM_ISP, "Failed! Invalid data"); + if (!tfe_out_data || !(tfe_out_data->cdm_util_ops)) { + CAM_ERR(CAM_ISP, "Failed! invalid data"); return -EINVAL; } + cdm_util_ops = tfe_out_data->cdm_util_ops; + if (update_buf->wm_update->num_buf != tfe_out_data->num_wm) { CAM_ERR(CAM_ISP, "Failed! Invalid number buffers:%d required:%d", @@ -2074,7 +2348,8 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, wm_data = tfe_out_data->wm_res[i]->res_priv; /* update width register */ - val = ((wm_data->height << 16) | (wm_data->width & 0xFFFF)); + val = ((wm_data->height << wm_data->common_data->height_shift) | + (wm_data->width & 0xFFFF)); CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_cfg_0, val); CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%x", @@ -2089,7 +2364,9 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, if ((wm_data->index < 7) || ((wm_data->index >= 7) && (wm_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE)) || (wm_data->out_id == CAM_TFE_BUS_TFE_OUT_PDAF) || - (wm_data->index >= 11 && wm_data->index <= 15)) { + (wm_data->index >= 11 && wm_data->index <= 15) || + (wm_data->index >= 17)) { + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_cfg_2, io_cfg->planes[i].plane_stride); @@ -2101,6 +2378,9 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, frame_inc = io_cfg->planes[i].plane_stride * io_cfg->planes[i].slice_height; + if (wm_data->is_buffer_aligned) + update_buf->wm_update->image_buf[i] += wm_data->buffer_offset; + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_addr, update_buf->wm_update->image_buf[i]); @@ -2148,6 +2428,38 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, return 0; } +static int cam_tfe_buffer_alignment_update(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *alignment_cmd; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + struct cam_isp_tfe_alignment_offset_config *alignment_port_cfg = NULL; + uint32_t i, rc = 0; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + alignment_cmd = (struct cam_isp_hw_get_cmd_update *) cmd_args; + alignment_port_cfg = (struct cam_isp_tfe_alignment_offset_config *) alignment_cmd->data; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) alignment_cmd->res->res_priv; + + if (!tfe_out_data) { + CAM_ERR(CAM_ISP, "Failed! invalid data"); + return -EINVAL; + } + + for (i = 0; i < tfe_out_data->num_wm; i++) { + wm_data = tfe_out_data->wm_res[i]->res_priv; + wm_data->is_buffer_aligned = true; + wm_data->offset = alignment_port_cfg->x_offset; + wm_data->buffer_offset = alignment_port_cfg->y_offset; + CAM_DBG(CAM_ISP, "wm %d X-Offset %x Y-Offset %x", wm_data->index, + wm_data->offset, wm_data->buffer_offset); + } + + return rc; +} static int cam_tfe_bus_update_hfr(void *priv, void *cmd_args, uint32_t arg_size) @@ -2156,7 +2468,7 @@ static int cam_tfe_bus_update_hfr(void *priv, void *cmd_args, struct cam_isp_hw_get_cmd_update *update_hfr; struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; struct cam_tfe_bus_wm_resource_data *wm_data = NULL; - struct cam_cdm_utils_ops *cdm_util_ops; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; struct cam_isp_tfe_port_hfr_config *hfr_cfg = NULL; uint32_t *reg_val_pair; uint32_t num_regval_pairs = 0; @@ -2168,13 +2480,12 @@ static int cam_tfe_bus_update_hfr(void *priv, void *cmd_args, tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) update_hfr->res->res_priv; - cdm_util_ops = tfe_out_data->cdm_util_ops; - - if (!tfe_out_data || !cdm_util_ops) { - CAM_ERR(CAM_ISP, "Failed! Invalid data"); + if (!tfe_out_data || !(tfe_out_data->cdm_util_ops)) { + CAM_ERR(CAM_ISP, "Failed! invalid data"); return -EINVAL; } + cdm_util_ops = tfe_out_data->cdm_util_ops; reg_val_pair = &tfe_out_data->common_data->io_buf_update[0]; hfr_cfg = (struct cam_isp_tfe_port_hfr_config *)update_hfr->data; @@ -2295,7 +2606,9 @@ static int cam_tfe_bus_get_res_id_for_mid( struct cam_isp_hw_get_cmd_update *cmd_update = (struct cam_isp_hw_get_cmd_update *)cmd_args; struct cam_isp_hw_get_res_for_mid *get_res = NULL; + uint32_t num_mid = 0, port_mid[CAM_TFE_BUS_TFE_OUT_MAX] = {0}; int i, j; + bool pid_found = false; get_res = (struct cam_isp_hw_get_res_for_mid *)cmd_update->data; if (!get_res) { @@ -2313,11 +2626,23 @@ static int cam_tfe_bus_get_res_id_for_mid( for (j = 0; j < CAM_TFE_BUS_MAX_MID_PER_PORT; j++) { if (tfe_out_data->mid[j] == get_res->mid) - goto end; + port_mid[num_mid++] = i; + } } - if (i == bus_priv->num_out) { + for (i = 0; i < num_mid; i++) { + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) + bus_priv->tfe_out[port_mid[i]].res_priv; + get_res->out_res_id = bus_priv->tfe_out[port_mid[i]].res_id; + if (tfe_out_data->pid_mask & (1 << get_res->pid)) { + get_res->out_res_id = bus_priv->tfe_out[port_mid[i]].res_id; + pid_found = true; + goto end; + } + } + + if (!num_mid) { CAM_ERR(CAM_ISP, "mid:%d does not match with any out resource", get_res->mid); @@ -2326,9 +2651,8 @@ static int cam_tfe_bus_get_res_id_for_mid( } end: - CAM_INFO(CAM_ISP, "match mid :%d out resource:%d found", - get_res->mid, bus_priv->tfe_out[i].res_id); - get_res->out_res_id = bus_priv->tfe_out[i].res_id; + CAM_INFO(CAM_ISP, "match mid :%d out resource:%d found, is pid found %d", + get_res->mid, get_res->out_res_id, pid_found); return 0; } @@ -2549,15 +2873,49 @@ static int cam_tfe_bus_deinit_hw(void *hw_priv, return rc; } +static int cam_tfe_bus_check_overflow( + struct cam_tfe_bus_priv *bus_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data; + struct cam_isp_hw_overflow_info *overflow_info = NULL; + uint32_t bus_overflow_status = 0, i = 0, tmp = 0; + + overflow_info = (struct cam_isp_hw_overflow_info *)cmd_args; + + bus_overflow_status = cam_io_r(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->overflow_status); + + if (bus_overflow_status) { + overflow_info->is_bus_overflow = true; + CAM_INFO(CAM_ISP, "TFE[%d] Bus overflow status: 0x%x", + bus_priv->common_data.core_index, bus_overflow_status); + } + + tmp = bus_overflow_status; + while (tmp) { + if (tmp & 0x1) { + rsrc_data = bus_priv->bus_client[i].res_priv; + CAM_ERR(CAM_ISP, "TFE[%d] WM : %d %s overflow", + bus_priv->common_data.core_index, i, + rsrc_data->hw_regs->client_name); + } + tmp = tmp >> 1; + i++; + } + + return 0; +} + static int cam_tfe_bus_process_cmd(void *priv, uint32_t cmd_type, void *cmd_args, uint32_t arg_size) { struct cam_tfe_bus_priv *bus_priv; - int rc = -EINVAL; + int rc = 0; uint32_t i, val; - bool *support_consumed_addr; bool *pdaf_rdi2_mux_en; struct cam_isp_hw_done_event_data *done; + struct cam_isp_hw_cap *tfe_bus_cap; if (!priv || !cmd_args) { CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid input arguments"); @@ -2589,10 +2947,11 @@ static int cam_tfe_bus_process_cmd(void *priv, bus_priv->common_data.common_reg->irq_mask[i]); } break; - case CAM_ISP_HW_CMD_IS_CONSUMED_ADDR_SUPPORT: + case CAM_ISP_HW_CMD_QUERY_CAP: bus_priv = (struct cam_tfe_bus_priv *) priv; - support_consumed_addr = (bool *)cmd_args; - *support_consumed_addr = + tfe_bus_cap = (struct cam_isp_hw_cap *) cmd_args; + tfe_bus_cap->max_out_res_type = bus_priv->max_out_res; + tfe_bus_cap->support_consumed_addr = bus_priv->common_data.support_consumed_addr; break; case CAM_ISP_HW_CMD_GET_RES_FOR_MID: @@ -2615,9 +2974,22 @@ static int cam_tfe_bus_process_cmd(void *priv, done->last_consumed_addr = cam_tfe_bus_get_last_consumed_addr( bus_priv, done->resource_handle); break; + case CAM_ISP_HW_CMD_BUS_WM_DISABLE: + rc = cam_tfe_bus_diable_wm(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_NOTIFY_OVERFLOW: + rc = cam_tfe_bus_check_overflow(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_BUFFER_ALIGNMENT_UPDATE: + rc = cam_tfe_buffer_alignment_update(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_WM_CONFIG_UPDATE: + rc = cam_tfe_bus_update_wm_config(priv, cmd_args, arg_size); + break; default: CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d", cmd_type); + rc = -EINVAL; break; } @@ -2635,6 +3007,7 @@ int cam_tfe_bus_init( struct cam_tfe_bus_priv *bus_priv = NULL; struct cam_tfe_bus *tfe_bus_local; struct cam_tfe_bus_hw_info *hw_info = bus_hw_info; + struct cam_tfe_soc_private *soc_private = NULL; if (!soc_info || !hw_intf || !bus_hw_info) { CAM_ERR(CAM_ISP, @@ -2644,6 +3017,13 @@ int cam_tfe_bus_init( goto end; } + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + rc = -ENODEV; + goto end; + } + tfe_bus_local = kzalloc(sizeof(struct cam_tfe_bus), GFP_KERNEL); if (!tfe_bus_local) { CAM_DBG(CAM_ISP, "Failed to alloc for tfe_bus"); @@ -2665,6 +3045,7 @@ int cam_tfe_bus_init( bus_priv->num_comp_grp = hw_info->num_comp_grp; bus_priv->max_wm_per_comp_grp = hw_info->max_wm_per_comp_grp; bus_priv->top_bus_wr_irq_shift = hw_info->top_bus_wr_irq_shift; + bus_priv->max_out_res = hw_info->max_out_res; bus_priv->common_data.comp_done_shift = hw_info->comp_done_shift; bus_priv->common_data.num_sec_out = 0; @@ -2684,16 +3065,15 @@ int cam_tfe_bus_init( bus_priv->common_data.max_bw_counter_limit = hw_info->max_bw_counter_limit; bus_priv->common_data.counter_limit_shift = hw_info->counter_limit_shift; bus_priv->common_data.counter_limit_mask = hw_info->counter_limit_mask; + bus_priv->common_data.mode_cfg_shift = hw_info->mode_cfg_shift; + bus_priv->common_data.height_shift = hw_info->height_shift; + bus_priv->common_data.pack_align_shift = hw_info->pack_align_shift; for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++) bus_priv->bus_irq_error_mask[i] = hw_info->bus_irq_error_mask[i]; - if (strnstr(soc_info->compatible, "lite", - strlen(soc_info->compatible)) != NULL) - bus_priv->common_data.is_lite = true; - else - bus_priv->common_data.is_lite = false; + bus_priv->common_data.is_lite = soc_private->is_tfe_lite; for (i = 0; i < CAM_TFE_BUS_RUP_GRP_MAX; i++) bus_priv->common_data.rup_irq_enable[i] = false; @@ -2808,7 +3188,7 @@ int cam_tfe_bus_deinit( "Deinit Comp Grp failed rc=%d", rc); } - for (i = 0; i < CAM_TFE_BUS_TFE_OUT_MAX; i++) { + for (i = 0; i < bus_priv->num_out; i++) { rc = cam_tfe_bus_deinit_tfe_out_resource( &bus_priv->tfe_out[i]); if (rc < 0) diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h index 218952fe73..441136dff9 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -12,7 +12,7 @@ #include "cam_isp_hw.h" #include "cam_tfe_hw_intf.h" -#define CAM_TFE_BUS_MAX_CLIENTS 16 +#define CAM_TFE_BUS_MAX_CLIENTS 19 #define CAM_TFE_BUS_MAX_SUB_GRPS 4 #define CAM_TFE_BUS_MAX_PERF_CNT_REG 8 #define CAM_TFE_BUS_MAX_IRQ_REGISTERS 2 @@ -61,6 +61,7 @@ enum cam_tfe_bus_comp_grp_id { CAM_TFE_BUS_COMP_GRP_8, CAM_TFE_BUS_COMP_GRP_9, CAM_TFE_BUS_COMP_GRP_10, + CAM_TFE_BUS_COMP_GRP_11, CAM_TFE_BUS_COMP_GRP_MAX, }; @@ -69,6 +70,7 @@ enum cam_tfe_bus_rup_grp_id { CAM_TFE_BUS_RUP_GRP_1, CAM_TFE_BUS_RUP_GRP_2, CAM_TFE_BUS_RUP_GRP_3, + CAM_TFE_BUS_RUP_GRP_4, CAM_TFE_BUS_RUP_GRP_MAX, }; @@ -88,6 +90,9 @@ enum cam_tfe_bus_tfe_out_id { CAM_TFE_BUS_TFE_OUT_DS4, CAM_TFE_BUS_TFE_OUT_DS16, CAM_TFE_BUS_TFE_OUT_AI, + CAM_TFE_BUS_TFE_OUT_PD_LCR_STATS, + CAM_TFE_BUS_TFE_OUT_PD_PREPROCESSED, + CAM_TFE_BUS_TFE_OUT_PD_PARSED, CAM_TFE_BUS_TFE_OUT_MAX, }; @@ -145,6 +150,7 @@ struct cam_tfe_bus_reg_offset_bus_client { uint32_t irq_subsample_pattern; uint32_t framedrop_period; uint32_t framedrop_pattern; + uint32_t system_cache_cfg; uint32_t addr_status_0; uint32_t addr_status_1; uint32_t addr_status_2; @@ -161,12 +167,13 @@ struct cam_tfe_bus_reg_offset_bus_client { * struct cam_tfe_bus_tfe_out_hw_info: * * @Brief: HW capability of TFE Bus Client - * tfe_out_id Tfe out port id - * max_width Max width supported by the outport - * max_height Max height supported by outport - * composite_group Out port composite group id - * rup_group_id Reg update group of outport id + * tfe_out_id: Tfe out port id + * max_width: Max width supported by the outport + * max_height: Max height supported by outport + * composite_group: Out port composite group id + * rup_group_id: Reg update group of outport id * mid: ouport mid value + * pid: pid associated with mid */ struct cam_tfe_bus_tfe_out_hw_info { enum cam_tfe_bus_tfe_out_id tfe_out_id; @@ -175,6 +182,7 @@ struct cam_tfe_bus_tfe_out_hw_info { uint32_t composite_group; uint32_t rup_group_id; uint32_t mid[CAM_TFE_BUS_MAX_MID_PER_PORT]; + uint64_t pid_mask; }; /* @@ -189,6 +197,8 @@ struct cam_tfe_bus_tfe_out_hw_info { * @num_comp_grp: Number of composite group * @max_wm_per_comp_grp: Max number of wm associated with one composite group * @comp_done_shift: Mask shift for comp done mask + * @mode_cfg_shift: Mask shift for mode config + * @height_shift: Mask shift for height shift * @top_bus_wr_irq_shift: Mask shift for top level BUS WR irq * @comp_buf_done_mask: Composite buf done bits mask * @comp_rup_done_mask: Reg update done mask @@ -199,6 +209,9 @@ struct cam_tfe_bus_tfe_out_hw_info { * @max_bw_counter_limit: Max BW counter limit * @counter_limit_shift: Mask shift for BW counter limit * @counter_limit_mask: Default Mask of BW limit counter + * @en_cfg_shift: bus client frame based enable bit + * @pack_align_shift: pack alignment shift + * @max_out_res: Max tfe out resource value supported for hw */ struct cam_tfe_bus_hw_info { struct cam_tfe_bus_reg_offset_common common_reg; @@ -211,6 +224,8 @@ struct cam_tfe_bus_hw_info { uint32_t num_comp_grp; uint32_t max_wm_per_comp_grp; uint32_t comp_done_shift; + uint32_t mode_cfg_shift; + uint32_t height_shift; uint32_t top_bus_wr_irq_shift; uint32_t comp_buf_done_mask; uint32_t comp_rup_done_mask; @@ -221,6 +236,8 @@ struct cam_tfe_bus_hw_info { uint32_t max_bw_counter_limit; uint32_t counter_limit_shift; uint32_t counter_limit_mask; + uint32_t pack_align_shift; + uint32_t max_out_res; }; /* diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index 572937f092..ceb3d3781b 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -30,6 +30,8 @@ static const char drv_name[] = "tfe"; #define CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES 3 #define CAM_TFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2 #define CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES 3 +#define CAM_TFE_MAX_OUT_OF_SYNC_ERR_COUNT 3 +#define CAM_TFE_DUAL_TFE_SYNC_SEL_IDX_FACTOR 1 struct cam_tfe_top_common_data { struct cam_hw_soc_info *soc_info; @@ -58,6 +60,9 @@ struct cam_tfe_top_priv { struct timespec64 eof_ts; struct timespec64 error_ts; uint32_t top_debug; + uint32_t last_mup_val; + uint32_t sync_hw_id; + atomic_t switch_out_of_sync_cnt; }; struct cam_tfe_camif_data { @@ -90,6 +95,9 @@ struct cam_tfe_camif_data { uint32_t qcfa_bin; uint32_t bayer_bin; uint32_t core_cfg; + bool shdr_en; + bool is_shdr_master; + uint32_t epoch_factor; }; struct cam_tfe_rdi_data { @@ -106,6 +114,27 @@ struct cam_tfe_rdi_data { uint32_t left_last_pixel; uint32_t first_line; uint32_t last_line; + bool shdr_en; + bool is_shdr_master; + uint32_t epoch_factor; +}; + +struct cam_tfe_ppp_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_ppp_reg *ppp_reg; + struct cam_tfe_ppp_reg_data *reg_data; + cam_hw_mgr_event_cb_func event_cb; + void *priv; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t pix_pattern; + uint32_t left_first_pixel; + uint32_t left_last_pixel; + uint32_t first_line; + uint32_t last_line; + uint32_t core_cfg; + bool lcr_enable; }; static int cam_tfe_validate_pix_pattern(uint32_t pattern) @@ -238,9 +267,12 @@ static void cam_tfe_log_tfe_in_debug_status( void __iomem *mem_base; struct cam_tfe_camif_data *camif_data; struct cam_tfe_rdi_data *rdi_data; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_ppp_data *ppp_data; uint32_t i, val_0, val_1; mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + common_reg = top_priv->common_data.common_reg; for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { if ((top_priv->in_rsrc[i].res_state != @@ -257,7 +289,7 @@ static void cam_tfe_log_tfe_in_debug_status( CAM_INFO(CAM_ISP, "camif debug1:0x%x Height:0x%x, width:0x%x", val_1, - ((val_0 >> 16) & 0x1FFF), + ((val_0 >> common_reg->height_shift) & 0x1FFF), (val_0 & 0x1FFF)); CAM_INFO(CAM_ISP, "Acquired sync mode:%d left start pxl:0x%x end_pixel:0x%x", @@ -280,6 +312,28 @@ static void cam_tfe_log_tfe_in_debug_status( camif_data->vbi_value, camif_data->hbi_value); + } else if (top_priv->in_rsrc[i].res_id == CAM_ISP_HW_TFE_IN_PDLIB) { + ppp_data = (struct cam_tfe_ppp_data *) + top_priv->in_rsrc[i].res_priv; + val_0 = cam_io_r(mem_base + + ppp_data->ppp_reg->ppp_debug_0); + val_1 = cam_io_r(mem_base + + ppp_data->ppp_reg->ppp_debug_1); + CAM_INFO(CAM_ISP, + "PDLIB res id:%d debug1:0x%x Height:0x%x, width:0x%x", + top_priv->in_rsrc[i].res_id, + val_1, ((val_0 >> 16) & 0x1FFF), + (val_0 & 0x1FFF)); + CAM_INFO(CAM_ISP, + "sync mode:%d left start pxl:0x%x end_pixel:0x%x", + ppp_data->sync_mode, + ppp_data->left_first_pixel, + ppp_data->left_last_pixel); + CAM_INFO(CAM_ISP, + "sync mode:%d line start:0x%x line end:0x%x", + ppp_data->sync_mode, + ppp_data->first_line, + ppp_data->last_line); } else if ((top_priv->in_rsrc[i].res_id >= CAM_ISP_HW_TFE_IN_RDI0) || (top_priv->in_rsrc[i].res_id <= @@ -293,7 +347,7 @@ static void cam_tfe_log_tfe_in_debug_status( CAM_INFO(CAM_ISP, "RDI res id:%d debug1:0x%x Height:0x%x, width:0x%x", top_priv->in_rsrc[i].res_id, - val_1, ((val_0 >> 16) & 0x1FFF), + val_1, ((val_0 >> common_reg->height_shift) & 0x1FFF), (val_0 & 0x1FFF)); CAM_INFO(CAM_ISP, "sync mode:%d left start pxl:0x%x end_pixel:0x%x", @@ -311,7 +365,8 @@ static void cam_tfe_log_tfe_in_debug_status( static void cam_tfe_log_error_irq_status( struct cam_tfe_hw_core_info *core_info, struct cam_tfe_top_priv *top_priv, - struct cam_tfe_irq_evt_payload *evt_payload) + struct cam_tfe_irq_evt_payload *evt_payload, + struct cam_isp_hw_error_event_info *err_evt_info) { struct cam_tfe_hw_info *hw_info; void __iomem *mem_base; @@ -319,20 +374,21 @@ static void cam_tfe_log_error_irq_status( struct cam_tfe_soc_private *soc_private; struct cam_tfe_clc_hw_status *clc_hw_status; + struct cam_tfe_top_reg_offset_common *common_reg; struct timespec64 ts; uint32_t i, val_0, val_1, val_2, val_3; - ktime_get_boottime_ts64(&ts); hw_info = core_info->tfe_hw_info; mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; soc_info = top_priv->common_data.soc_info; soc_private = top_priv->common_data.soc_info->soc_private; + common_reg = top_priv->common_data.common_reg; - CAM_INFO(CAM_ISP, "current monotonic timestamp:[%lld.%06lld]", + CAM_INFO(CAM_ISP, "current monotonic time stamp seconds %lld:%lld", ts.tv_sec, ts.tv_nsec/1000); CAM_INFO(CAM_ISP, - "ERROR timestamp:[%lld.%06lld] SOF timestamp:[%lld.%06lld] EPOCH timestamp:[%lld.%06lld] EOF timestamp:[%lld.%06lld]", + "ERROR time %lld:%lld SOF %lld:%lld EPOCH %lld:%lld EOF %lld:%lld", top_priv->error_ts.tv_sec, top_priv->error_ts.tv_nsec/1000, top_priv->sof_ts.tv_sec, @@ -346,26 +402,22 @@ static void cam_tfe_log_error_irq_status( evt_payload->irq_reg_val[0], evt_payload->irq_reg_val[1], evt_payload->irq_reg_val[2]); - for (i = 0; i < top_priv->common_data.common_reg->num_debug_reg; i++) { + for (i = 0; i < common_reg->num_debug_reg; i++) { val_0 = cam_io_r(mem_base + - top_priv->common_data.common_reg->debug_reg[i]); - CAM_INFO(CAM_ISP, "Top debug [i]:0x%x", i, val_0); + common_reg->debug_reg[i]); + CAM_INFO(CAM_ISP, "Top debug [%d]:0x%x", i, val_0); } cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle); - for (i = 0; i < top_priv->common_data.common_reg->num_perf_cfg; i++) { - val_0 = cam_io_r(mem_base + - top_priv->common_data.common_reg->perf_cfg[i].perf_pixel_count); + for (i = 0; i < common_reg->num_perf_cfg; i++) { + val_0 = cam_io_r(mem_base + common_reg->perf_cfg[i].perf_pixel_count); - val_1 = cam_io_r(mem_base + - top_priv->common_data.common_reg->perf_cfg[i].perf_line_count); + val_1 = cam_io_r(mem_base + common_reg->perf_cfg[i].perf_line_count); - val_2 = cam_io_r(mem_base + - top_priv->common_data.common_reg->perf_cfg[i].perf_stall_count); + val_2 = cam_io_r(mem_base + common_reg->perf_cfg[i].perf_stall_count); - val_3 = cam_io_r(mem_base + - top_priv->common_data.common_reg->perf_cfg[i].perf_always_count); + val_3 = cam_io_r(mem_base + common_reg->perf_cfg[i].perf_always_count); CAM_INFO(CAM_ISP, "Top perf cnt [%d] pix:0x%x line:0x%x stall:0x%x always:0x%x", @@ -388,54 +440,74 @@ static void cam_tfe_log_error_irq_status( /* Check the overflow errors */ if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { - if (evt_payload->irq_reg_val[0] & BIT(8)) - CAM_INFO(CAM_ISP, "PP_FRAME_DROP"); + if (evt_payload->irq_reg_val[0] & common_reg->pp_frame_drop_bit) + CAM_INFO(CAM_ISP, "TFE %d PP_FRAME_DROP", core_info->core_index); - if (evt_payload->irq_reg_val[0] & BIT(9)) - CAM_INFO(CAM_ISP, "RDI0_FRAME_DROP"); + if (evt_payload->irq_reg_val[0] & common_reg->rdi0_frame_drop_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI0_FRAME_DROP", core_info->core_index); - if (evt_payload->irq_reg_val[0] & BIT(10)) - CAM_INFO(CAM_ISP, "RDI1_FRAME_DROP"); + if (evt_payload->irq_reg_val[0] & common_reg->rdi1_frame_drop_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI1_FRAME_DROP", core_info->core_index); - if (evt_payload->irq_reg_val[0] & BIT(11)) - CAM_INFO(CAM_ISP, "RDI2_FRAME_DROP"); + if (evt_payload->irq_reg_val[0] & common_reg->rdi2_frame_drop_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI2_FRAME_DROP", core_info->core_index); - if (evt_payload->irq_reg_val[0] & BIT(16)) - CAM_INFO(CAM_ISP, "PP_OVERFLOW"); + if (evt_payload->irq_reg_val[0] & common_reg->ppp_frame_drop_bit) + CAM_INFO(CAM_ISP, "TFE %d PDAF_FRAME_DROP", core_info->core_index); - if (evt_payload->irq_reg_val[0] & BIT(17)) - CAM_INFO(CAM_ISP, "RDI0_OVERFLOW"); + if (evt_payload->irq_reg_val[0] & common_reg->pp_overflow_bit) + CAM_INFO(CAM_ISP, "TFE %d PP_OVERFLOW", core_info->core_index); - if (evt_payload->irq_reg_val[0] & BIT(18)) - CAM_INFO(CAM_ISP, "RDI1_OVERFLOW"); + if (evt_payload->irq_reg_val[0] & common_reg->rdi0_overflow_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI0_OVERFLOW", core_info->core_index); - if (evt_payload->irq_reg_val[0] & BIT(19)) - CAM_INFO(CAM_ISP, "RDI2_OVERFLOW"); + if (evt_payload->irq_reg_val[0] & common_reg->rdi1_overflow_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI1_OVERFLOW", core_info->core_index); + + if (evt_payload->irq_reg_val[0] & common_reg->rdi2_overflow_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI2_OVERFLOW", core_info->core_index); + + if (evt_payload->irq_reg_val[0] & common_reg->ppp_overflow_bit) + CAM_INFO(CAM_ISP, "TFE %d PDAF_OVERFLOW", core_info->core_index); } /* Check the violation errors */ if (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2]) { - if (evt_payload->irq_reg_val[2] & BIT(0)) - CAM_INFO(CAM_ISP, "PP_CAMIF_VIOLATION"); + if (evt_payload->irq_reg_val[2] & common_reg->pp_camif_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d PP_CAMIF_VIOLATION", core_info->core_index); - if (evt_payload->irq_reg_val[2] & BIT(1)) - CAM_INFO(CAM_ISP, "PP_VIOLATION"); + if (evt_payload->irq_reg_val[2] & common_reg->pp_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d PP_VIOLATION", core_info->core_index); - if (evt_payload->irq_reg_val[2] & BIT(2)) - CAM_INFO(CAM_ISP, "RDI0_CAMIF_VIOLATION"); + if (evt_payload->irq_reg_val[2] & common_reg->rdi0_camif_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI0_CAMIF_VIOLATION", core_info->core_index); - if (evt_payload->irq_reg_val[2] & BIT(3)) - CAM_INFO(CAM_ISP, "RDI1_CAMIF_VIOLATION"); + if (evt_payload->irq_reg_val[2] & common_reg->rdi1_camif_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI1_CAMIF_VIOLATION", core_info->core_index); - if (evt_payload->irq_reg_val[2] & BIT(4)) - CAM_INFO(CAM_ISP, "RDI2_CAMIF_VIOLATION"); + if (evt_payload->irq_reg_val[2] & common_reg->rdi2_camif_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d RDI2_CAMIF_VIOLATION", core_info->core_index); - if (evt_payload->irq_reg_val[2] & BIT(5)) - CAM_INFO(CAM_ISP, "DIAG_VIOLATION"); + if (evt_payload->irq_reg_val[2] & common_reg->diag_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d DIAG_VIOLATION", core_info->core_index); - val_0 = cam_io_r(mem_base + - top_priv->common_data.common_reg->violation_status); - CAM_INFO(CAM_ISP, "TOP Violation status:0x%x", val_0); + if (evt_payload->irq_reg_val[2] & common_reg->ppp_camif_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d PDAF_CAMIF_VIOLATION", core_info->core_index); + + if (evt_payload->irq_reg_val[2] & common_reg->ppp_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d PDAF_VIOLATION", core_info->core_index); + + if (evt_payload->irq_reg_val[2] & common_reg->lcr_pd_timing_protocol_violation_bit) + CAM_INFO(CAM_ISP, "TFE %d LCR_PD_INPUT_TIMING_PROTOCOL_VIOLATION", + core_info->core_index); + + if (evt_payload->irq_reg_val[2] & common_reg->dyamanic_switch_violation_bit) + CAM_INFO(CAM_ISP, + "TFE %d DYNAMIC_SHDR_MODE_SWITCH_VIOLATION mup val %d", + core_info->core_index, top_priv->last_mup_val); + + val_0 = cam_io_r(mem_base + common_reg->violation_status); + CAM_INFO(CAM_ISP, "TFE %d TOP Violation status:0x%x", core_info->core_index, val_0); } core_info->tfe_bus->bottom_half_handler( @@ -446,6 +518,37 @@ static void cam_tfe_log_error_irq_status( top_priv->hw_clk_rate, top_priv->total_bw_applied); + cam_cpas_log_votes(false); +} + +static void cam_tfe_check_out_of_sync( + struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_top_priv *top_priv, + struct cam_tfe_irq_evt_payload *evt_payload, + struct cam_isp_hw_error_event_info *err_evt_info, + uint32_t *report_err) +{ + struct cam_tfe_top_reg_offset_common *common_reg; + void __iomem *mem_base; + + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + common_reg = top_priv->common_data.common_reg; + + if (evt_payload->irq_reg_val[0] & common_reg->out_of_sync_frame_drop_bit) { + CAM_INFO(CAM_ISP, + "TFE %d SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP mup: last %d curr %d", + core_info->core_index, top_priv->last_mup_val, + ((cam_io_r(mem_base + common_reg->reg_update_cmd) >> + common_reg->mup_shift_val) & 1)); + atomic_inc(&top_priv->switch_out_of_sync_cnt); + if (atomic_read(&top_priv->switch_out_of_sync_cnt) >= + CAM_TFE_MAX_OUT_OF_SYNC_ERR_COUNT) { + *report_err = 1; + err_evt_info->err_type = CAM_TFE_IRQ_STATUS_OUT_OF_SYNC; + CAM_ERR(CAM_ISP, "TFE %d out of sync frame count: %d", + core_info->core_index, top_priv->switch_out_of_sync_cnt); + } + } } static int cam_tfe_error_irq_bottom_half( @@ -463,12 +566,18 @@ static int cam_tfe_error_irq_bottom_half( hw_info = core_info->tfe_hw_info; evt_info.hw_idx = core_info->core_index; evt_info.res_type = CAM_ISP_RESOURCE_TFE_IN; + evt_info.hw_type = CAM_ISP_HW_TYPE_TFE; if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { err_evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW; error_detected = 1; } + if (evt_payload->irq_reg_val[0] & hw_info->non_fatal_error_irq_mask[0]) { + cam_tfe_check_out_of_sync(core_info, top_priv, evt_payload, + &err_evt_info, &error_detected); + } + if ((evt_payload->bus_irq_val[0] & hw_info->bus_error_irq_mask[0]) || (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2])) { err_evt_info.err_type = CAM_TFE_IRQ_STATUS_VIOLATION; @@ -482,10 +591,11 @@ static int cam_tfe_error_irq_bottom_half( top_priv->error_ts.tv_nsec = evt_payload->ts.mono_time.tv_nsec; - cam_tfe_log_error_irq_status(core_info, top_priv, evt_payload); + cam_tfe_log_error_irq_status(core_info, top_priv, + evt_payload, &err_evt_info); if (event_cb) - event_cb(event_cb_priv, - CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + event_cb(event_cb_priv, CAM_ISP_HW_EVENT_ERROR, + (void *)&evt_info); else CAM_ERR(CAM_ISP, "TFE:%d invalid eventcb:", core_info->core_index); @@ -538,6 +648,8 @@ static int cam_tfe_rdi_irq_bottom_half( rdi_priv->event_cb(rdi_priv->priv, CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + atomic_set(&top_priv->switch_out_of_sync_cnt, 0); + if (top_priv->top_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { common_reg = rdi_priv->common_reg; @@ -572,6 +684,84 @@ static int cam_tfe_rdi_irq_bottom_half( return 0; } +static int cam_tfe_ppp_irq_bottom_half( + struct cam_tfe_top_priv *top_priv, + struct cam_isp_resource_node *ppp_node, + bool epoch_process, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_ppp_data *ppp_priv; + struct cam_isp_hw_event_info evt_info; + struct cam_hw_info *hw_info; + struct cam_tfe_top_reg_offset_common *common_reg; + uint32_t val, val2; + + ppp_priv = (struct cam_tfe_ppp_data *)ppp_node->res_priv; + hw_info = ppp_node->hw_intf->hw_priv; + + evt_info.hw_idx = ppp_node->hw_intf->hw_idx; + evt_info.res_id = ppp_node->res_id; + evt_info.res_type = ppp_node->res_type; + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + ppp_priv->reg_data->eof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EOF"); + top_priv->eof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->eof_ts.tv_nsec = + evt_payload->ts.mono_time.tv_nsec; + + if (ppp_priv->event_cb) + ppp_priv->event_cb(ppp_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + } + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + ppp_priv->reg_data->sof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received SOF"); + top_priv->sof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->sof_ts.tv_nsec = + evt_payload->ts.mono_time.tv_nsec; + + if (ppp_priv->event_cb) + ppp_priv->event_cb(ppp_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + + if (top_priv->top_debug & + CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + common_reg = ppp_priv->common_reg; + val = cam_io_r(ppp_priv->mem_base + + common_reg->diag_sensor_status_0); + val2 = cam_io_r(ppp_priv->mem_base + + common_reg->diag_sensor_status_1); + CAM_INFO(CAM_ISP, + "TFE:%d diag sensor hbi min error:%d neq hbi:%d HBI:%d VBI:%d", + ppp_node->hw_intf->hw_idx, + ((val >> common_reg->diag_min_hbi_error_shift) + & 0x1), + ((val >> common_reg->diag_neq_hbi_shift) & 0x1), + (val & common_reg->diag_sensor_hbi_mask), + val2); + } + } + + if (epoch_process && (evt_payload->irq_reg_val[1] & + ppp_priv->reg_data->epoch0_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EPOCH0"); + top_priv->epoch_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->epoch_ts.tv_nsec = + evt_payload->ts.mono_time.tv_nsec; + + if (ppp_priv->event_cb) + ppp_priv->event_cb(ppp_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + } + + return 0; +} + static int cam_tfe_camif_irq_bottom_half( struct cam_tfe_top_priv *top_priv, struct cam_isp_resource_node *camif_node, @@ -630,6 +820,8 @@ static int cam_tfe_camif_irq_bottom_half( camif_priv->event_cb(camif_priv->priv, CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + atomic_set(&top_priv->switch_out_of_sync_cnt, 0); + if (top_priv->top_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { common_reg = camif_priv->common_reg; @@ -673,6 +865,7 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, struct cam_tfe_irq_evt_payload *evt_payload; struct cam_tfe_camif_data *camif_priv; struct cam_tfe_rdi_data *rdi_priv; + struct cam_tfe_ppp_data *ppp_priv; cam_hw_mgr_event_cb_func event_cb = NULL; void *event_cb_priv = NULL; uint32_t i; @@ -705,6 +898,20 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, &top_priv->in_rsrc[i], false, evt_payload); + } else if ((top_priv->in_rsrc[i].res_id == + CAM_ISP_HW_TFE_IN_PDLIB) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + ppp_priv = (struct cam_tfe_ppp_data *) + top_priv->in_rsrc[i].res_priv; + event_cb = ppp_priv->event_cb; + event_cb_priv = ppp_priv->priv; + + if (ppp_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_ppp_irq_bottom_half(top_priv, + &top_priv->in_rsrc[i], false, + evt_payload); } else if ((top_priv->in_rsrc[i].res_id >= CAM_ISP_HW_TFE_IN_RDI0) && (top_priv->in_rsrc[i].res_id <= @@ -749,6 +956,17 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, cam_tfe_camif_irq_bottom_half(top_priv, &top_priv->in_rsrc[i], true, evt_payload); + } else if ((top_priv->in_rsrc[i].res_id == + CAM_ISP_HW_TFE_IN_PDLIB) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + ppp_priv = (struct cam_tfe_ppp_data *) + top_priv->in_rsrc[i].res_priv; + if (ppp_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_ppp_irq_bottom_half(top_priv, + &top_priv->in_rsrc[i], true, + evt_payload); } else if ((top_priv->in_rsrc[i].res_id >= CAM_ISP_HW_TFE_IN_RDI0) && (top_priv->in_rsrc[i].res_id <= @@ -971,6 +1189,41 @@ static int cam_tfe_top_set_hw_clk_rate( return rc; } +static int cam_tfe_top_dynamic_clock_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, + uint32_t arg_size) +{ + struct cam_hw_soc_info *soc_info; + unsigned long *clk_rate; + int rc = 0; + + soc_info = top_priv->common_data.soc_info; + clk_rate = (unsigned long *)cmd_args; + CAM_DBG(CAM_ISP, "TFE[%u] clock rate requested: %llu curr: %llu", + top_priv->common_data.hw_intf->hw_idx, *clk_rate, + soc_info->applied_src_clk_rates.sw_client); + + if (*clk_rate <= top_priv->hw_clk_rate) + goto end; + + rc = cam_soc_util_set_src_clk_rate(soc_info, CAM_CLK_SW_CLIENT_IDX, *clk_rate, 0); + if (!rc) { + top_priv->hw_clk_rate = *clk_rate; + } else { + CAM_ERR(CAM_ISP, + "unable to set clock dynamically rate: %llu", + *clk_rate); + return rc; + } +end: + *clk_rate = soc_info->applied_src_clk_rates.sw_client; + CAM_DBG(CAM_ISP, "TFE[%u] new clock rate %llu", + top_priv->common_data.hw_intf->hw_idx, soc_info->applied_src_clk_rates.sw_client); + + return rc; +} + static struct cam_axi_vote *cam_tfe_top_delay_bw_reduction( struct cam_tfe_top_priv *top_priv, uint64_t *to_be_applied_bw) @@ -1177,6 +1430,7 @@ static int cam_tfe_top_get_base(struct cam_tfe_top_priv *top_priv, uint32_t mem_base = 0; struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_tfe_soc_private *soc_private; if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { CAM_ERR(CAM_ISP, "Error Invalid cmd size"); @@ -1189,6 +1443,12 @@ static int cam_tfe_top_get_base(struct cam_tfe_top_priv *top_priv, return -EINVAL; } + soc_private = top_priv->common_data.soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "soc_private is null"); + return -EINVAL; + } + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; @@ -1207,54 +1467,103 @@ static int cam_tfe_top_get_base(struct cam_tfe_top_priv *top_priv, mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( top_priv->common_data.soc_info, TFE_CORE_BASE_IDX); + if (mem_base == -1) { + CAM_ERR(CAM_ISP, "failed to get mem_base, index: %d num_reg_map: %u", + TFE_CORE_BASE_IDX, top_priv->common_data.soc_info->num_reg_map); + return -EINVAL; + } - cdm_util_ops->cdm_write_changebase( - cdm_args->cmd.cmd_buf_addr, mem_base); + if (cdm_args->cdm_id == CAM_CDM_RT) { + if (!soc_private->rt_wrapper_base) { + CAM_ERR(CAM_ISP, "rt_wrapper_base_addr is null"); + return -EINVAL; + } + + mem_base -= soc_private->rt_wrapper_base; + } + + cdm_util_ops->cdm_write_changebase(cdm_args->cmd.cmd_buf_addr, mem_base); cdm_args->cmd.used_bytes = (size * 4); return 0; } +static int cam_tfe_top_update_mup( + struct cam_tfe_top_priv *top_priv, + struct cam_isp_mode_switch_data *mup_config) +{ + uint32_t mup_val = 0, final_mup = 0; + struct cam_tfe_top_reg_offset_common *common_reg; + + mup_val = mup_config->mup; + common_reg = top_priv->common_data.common_reg; + + CAM_DBG(CAM_ISP, "TFE: %d mup_val: %d, mup_en: %d", + top_priv->common_data.hw_intf->hw_idx, mup_val, mup_config->mup_en); + + if (mup_config->mup_en) { + final_mup = (mup_val << common_reg->mup_shift_val); + top_priv->last_mup_val = mup_val; + } else { + final_mup = (top_priv->last_mup_val << common_reg->mup_shift_val); + } + + return final_mup; +} + static int cam_tfe_top_get_reg_update( struct cam_tfe_top_priv *top_priv, void *cmd_args, uint32_t arg_size) { + int rc = 0; uint32_t size = 0; - uint32_t reg_val_pair[2]; + uint32_t reg_val_pair[2] = {0}; struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; struct cam_cdm_utils_ops *cdm_util_ops = NULL; struct cam_tfe_camif_data *camif_rsrc_data = NULL; struct cam_tfe_rdi_data *rdi_rsrc_data = NULL; struct cam_isp_resource_node *in_res; + struct cam_isp_mode_switch_data *mup_config = NULL; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_top_reg_offset_common *common_reg; if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { CAM_ERR(CAM_ISP, "Invalid cmd size"); - return -EINVAL; + rc = -EINVAL; + goto end; } - if (!cdm_args || !cdm_args->res) { + if (!cdm_args || !cdm_args->res || !top_priv) { CAM_ERR(CAM_ISP, "Invalid args"); - return -EINVAL; + rc = -EINVAL; + goto end; } cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; if (!cdm_util_ops) { CAM_ERR(CAM_ISP, "Invalid CDM ops"); - return -EINVAL; + rc = -EINVAL; + goto end; } + soc_info = top_priv->common_data.soc_info; in_res = cdm_args->res; size = cdm_util_ops->cdm_required_size_reg_random(1); /* since cdm returns dwords, we need to convert it into bytes */ - if ((size * 4) > cdm_args->cmd.size) { + if ((!cdm_args->reg_write) && ((size * 4) > cdm_args->cmd.size)) { CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", cdm_args->cmd.size, size); - return -EINVAL; + rc = -EINVAL; + goto end; } if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { camif_rsrc_data = in_res->res_priv; + if (camif_rsrc_data->shdr_en && !camif_rsrc_data->is_shdr_master) { + CAM_DBG(CAM_ISP, "Skip reg update cmd for slave camif"); + goto end; + } reg_val_pair[0] = camif_rsrc_data->camif_reg->reg_update_cmd; reg_val_pair[1] = camif_rsrc_data->reg_data->reg_update_cmd_data; @@ -1263,12 +1572,88 @@ static int cam_tfe_top_get_reg_update( rdi_rsrc_data = in_res->res_priv; reg_val_pair[0] = rdi_rsrc_data->rdi_reg->reg_update_cmd; reg_val_pair[1] = rdi_rsrc_data->reg_data->reg_update_cmd_data; + } else if (in_res->res_id == CAM_ISP_HW_TFE_IN_PDLIB) { + /*REG CMD is not supported in PDLIB. PD CAMIF takes RUP from IPP CAMIF */ + CAM_DBG(CAM_ISP, "Reg update not supported for res %d", + in_res->res_id); + cdm_args->cmd.used_bytes = 0; + goto end; + } else { + CAM_ERR(CAM_ISP, "Unknown resource with res_id = %d", in_res->res_id); + rc = -EINVAL; + goto end; } - cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, - 1, reg_val_pair); + common_reg = top_priv->common_data.common_reg; + if (common_reg->mup_supported) { + if (!cdm_args->data) { + CAM_ERR(CAM_ISP, "invalid data (NULL), TFE: %d mup_supported :%d", + top_priv->common_data.hw_intf->hw_idx , cdm_args->data); + return -EINVAL; + } + mup_config = (struct cam_isp_mode_switch_data *) cdm_args->data; + reg_val_pair[1] |= cam_tfe_top_update_mup(top_priv, mup_config); + CAM_DBG(CAM_ISP, "MUP supported, TFE: %d final reg_up cmd: 0x%x", + top_priv->common_data.hw_intf->hw_idx, reg_val_pair[1]); + } - cdm_args->cmd.used_bytes = size * 4; + if (cdm_args->reg_write) { + cam_io_w_mb(reg_val_pair[1], + soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base + reg_val_pair[0]); + } else { + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + cdm_args->cmd.used_bytes = size * 4; + } + +end: + return rc; +} + +static int cam_tfe_top_init_config_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + int i = 0; + struct cam_isp_hw_init_config_update *init_cfg = NULL; + struct cam_isp_resource_node *rsrc_node = NULL; + struct cam_tfe_camif_data *camif_data; + + init_cfg = (struct cam_isp_hw_init_config_update *)cmd_args; + + if (arg_size != sizeof(struct cam_isp_hw_init_config_update)) { + CAM_ERR(CAM_ISP, "Invalid args size expected: %zu actual: %zu", + sizeof(struct cam_isp_hw_init_config_update), arg_size); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + rsrc_node = &top_priv->in_rsrc[i]; + break; + } + } + + if (!rsrc_node) { + CAM_ERR(CAM_ISP, "TFE %d null input res node", + top_priv->common_data.hw_intf->hw_idx); + return -EINVAL; + } + + if (rsrc_node->res_type != CAM_ISP_RESOURCE_TFE_IN) { + CAM_ERR(CAM_ISP, "TFE %d Invalid res_type %d res id %d ", + rsrc_node->hw_intf->hw_idx, rsrc_node->res_type, + rsrc_node->res_id); + return -EINVAL; + } + + camif_data = (struct cam_tfe_camif_data *)rsrc_node->res_priv; + camif_data->epoch_factor = init_cfg->init_config->epoch_cfg.epoch_factor; + + CAM_DBG(CAM_ISP, + "Init Update TFE %d res type: %d res id %d epoch_factor: %u", + rsrc_node->hw_intf->hw_idx, rsrc_node->res_type, + rsrc_node->res_id, camif_data->epoch_factor); return 0; } @@ -1412,6 +1797,27 @@ static int cam_tfe_top_bw_control( return rc; } +static int cam_tfe_set_sync_hw_idx( + struct cam_tfe_hw_core_info *core_info, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + uint32_t *hw_idx; + + if (!cmd_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + hw_idx = (uint32_t *)cmd_args; + top_priv->sync_hw_id = *hw_idx; + + CAM_DBG(CAM_ISP, "TFE:%d top sync hw idx %d", core_info->core_index, + top_priv->sync_hw_id); + return 0; +} + static int cam_tfe_top_get_reg_dump( struct cam_tfe_top_priv *top_priv, void *cmd_args, uint32_t arg_size) @@ -1819,6 +2225,22 @@ int cam_tfe_set_top_debug(struct cam_tfe_hw_core_info *core_info, return 0; } +static int cam_tfe_bus_get_path_port_map(void *top_hw_info, + void *cmd_args, uint32_t arg_size) +{ + struct cam_isp_hw_path_port_map *arg = cmd_args; + struct cam_tfe_top_hw_info *hw_info = + (struct cam_tfe_top_hw_info *)top_hw_info; + int i; + + for (i = 0; i < hw_info->num_path_port_map; i++) { + arg->entry[i][0] = hw_info->path_port_map[i][0]; + arg->entry[i][1] = hw_info->path_port_map[i][1]; + } + arg->num_entries = hw_info->num_path_port_map; + + return 0; +} int cam_tfe_top_reserve(void *device_priv, void *reserve_args, uint32_t arg_size) @@ -1827,6 +2249,7 @@ int cam_tfe_top_reserve(void *device_priv, struct cam_tfe_acquire_args *args; struct cam_tfe_hw_tfe_in_acquire_args *acquire_args; struct cam_tfe_camif_data *camif_data; + struct cam_tfe_ppp_data *ppp_data; struct cam_tfe_rdi_data *rdi_data; uint32_t i; int rc = -EINVAL; @@ -1839,6 +2262,7 @@ int cam_tfe_top_reserve(void *device_priv, top_priv = (struct cam_tfe_top_priv *)device_priv; args = (struct cam_tfe_acquire_args *)reserve_args; acquire_args = &args->tfe_in; + top_priv->last_mup_val = 0; for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { CAM_DBG(CAM_ISP, "i :%d res_id:%d state:%d", i, @@ -1891,12 +2315,33 @@ int cam_tfe_top_reserve(void *device_priv, acquire_args->in_port->bayer_bin; camif_data->core_cfg = acquire_args->in_port->core_cfg; + camif_data->shdr_en = acquire_args->in_port->shdr_en; + camif_data->is_shdr_master = acquire_args->in_port->is_shdr_master; CAM_DBG(CAM_ISP, "TFE:%d pix_pattern:%d dsp_mode=%d", top_priv->in_rsrc[i].hw_intf->hw_idx, camif_data->pix_pattern, camif_data->dsp_mode); + } else if (acquire_args->res_id == CAM_ISP_HW_TFE_IN_PDLIB) { + ppp_data = (struct cam_tfe_ppp_data *) + top_priv->in_rsrc[i].res_priv; + ppp_data->pix_pattern = + acquire_args->in_port->pix_pattern; + ppp_data->sync_mode = acquire_args->sync_mode; + ppp_data->event_cb = args->event_cb; + ppp_data->priv = args->priv; + ppp_data->left_first_pixel = + acquire_args->in_port->left_start; + ppp_data->left_last_pixel = + acquire_args->in_port->left_end; + ppp_data->first_line = + acquire_args->in_port->line_start; + ppp_data->last_line = + acquire_args->in_port->line_end; + ppp_data->lcr_enable = + acquire_args->lcr_enable; + ppp_data->core_cfg = acquire_args->in_port->core_cfg; } else { rdi_data = (struct cam_tfe_rdi_data *) top_priv->in_rsrc[i].res_priv; @@ -1913,6 +2358,8 @@ int cam_tfe_top_reserve(void *device_priv, acquire_args->in_port->line_start; rdi_data->last_line = acquire_args->in_port->line_end; + rdi_data->shdr_en = acquire_args->in_port->shdr_en; + rdi_data->is_shdr_master = acquire_args->in_port->is_shdr_master; } top_priv->in_rsrc[i].cdm_ops = acquire_args->cdm_ops; @@ -1967,13 +2414,14 @@ static int cam_tfe_camif_resource_start( struct cam_tfe_camif_data *rsrc_data; struct cam_tfe_soc_private *soc_private; struct cam_tfe_top_priv *top_priv; - uint32_t val = 0; + uint32_t val = 0, epoch_factor = 50; uint32_t epoch0_irq_mask; uint32_t epoch1_irq_mask; uint32_t computed_epoch_line_cfg; uint32_t camera_hw_version = 0; struct cam_hw_intf *tfe_device; bool pdaf_rdi2_mux_en = false; + struct cam_tfe_top_reg_offset_common *common_reg; if (!camif_res || !core_info) { CAM_ERR(CAM_ISP, "Error Invalid input arguments"); @@ -1995,7 +2443,7 @@ static int cam_tfe_camif_resource_start( core_info->core_index); return -ENODEV; } - + common_reg = top_priv->common_data.common_reg; /* Config tfe core*/ val = 0; if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) @@ -2004,7 +2452,7 @@ static int cam_tfe_camif_resource_start( if ((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) || (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)) { val |= (1 << rsrc_data->reg_data->dual_tfe_pix_en_shift); - val |= ((rsrc_data->dual_tfe_sync_sel + 1) << + val |= ((rsrc_data->dual_tfe_sync_sel + CAM_TFE_DUAL_TFE_SYNC_SEL_IDX_FACTOR) << rsrc_data->reg_data->dual_tfe_sync_sel_shift); } @@ -2032,12 +2480,22 @@ static int cam_tfe_camif_resource_start( (1 << rsrc_data->reg_data->ds4_c_srl_en_shift); } + if (rsrc_data->shdr_en) { + val |= (1 << rsrc_data->reg_data->shdr_mode_shift); + val |= (1 << rsrc_data->reg_data->dual_tfe_pix_en_shift); + val |= ((top_priv->sync_hw_id + CAM_TFE_DUAL_TFE_SYNC_SEL_IDX_FACTOR) << + rsrc_data->reg_data->dual_tfe_sync_sel_shift); + if (!rsrc_data->is_shdr_master) { + val |= (1 << rsrc_data->reg_data->extern_mup_shift); + val |= (1 << rsrc_data->reg_data->extern_reg_update_shift); + } + } cam_io_w_mb(val, rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0); - CAM_DBG(CAM_ISP, "TFE:%d core_cfg 0 val:0x%x", core_info->core_index, - val); + CAM_DBG(CAM_ISP, "TFE:%d core_cfg_0 val:0x%x", core_info->core_index, + cam_io_r_mb(rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0)); if (cam_cpas_get_cpas_hw_version(&camera_hw_version)) CAM_ERR(CAM_ISP, "Failed to get HW version"); @@ -2053,8 +2511,12 @@ static int cam_tfe_camif_resource_start( } /* Epoch config */ + if ((rsrc_data->epoch_factor) && (rsrc_data->epoch_factor <= 100)) + epoch_factor = rsrc_data->epoch_factor; + epoch0_irq_mask = (((rsrc_data->last_line + rsrc_data->vbi_value) - - rsrc_data->first_line) / 2); + rsrc_data->first_line) * epoch_factor / 100); + if (epoch0_irq_mask > (rsrc_data->last_line - rsrc_data->first_line)) epoch0_irq_mask = (rsrc_data->last_line - rsrc_data->first_line); @@ -2064,26 +2526,29 @@ static int cam_tfe_camif_resource_start( epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & 0xFFFF; - computed_epoch_line_cfg = (epoch0_irq_mask << 16) | + computed_epoch_line_cfg = (epoch0_irq_mask << common_reg->epoch_shift_val) | epoch1_irq_mask; cam_io_w_mb(computed_epoch_line_cfg, rsrc_data->mem_base + rsrc_data->camif_reg->epoch_irq_cfg); CAM_DBG(CAM_ISP, "TFE:%d first_line: %u\n" "last_line: %u\n" - "epoch_line_cfg: 0x%x", + "epoch_line_cfg: 0x%x epoch factor %d", core_info->core_index, rsrc_data->first_line, rsrc_data->last_line, - computed_epoch_line_cfg); + computed_epoch_line_cfg, epoch_factor); camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; /* Reg Update */ - cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data | + (top_priv->last_mup_val << common_reg->mup_shift_val), rsrc_data->mem_base + rsrc_data->camif_reg->reg_update_cmd); - CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d", camif_res->hw_intf->hw_idx, - rsrc_data->reg_data->reg_update_cmd_data); + CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d MUP val: %d", + camif_res->hw_intf->hw_idx, + rsrc_data->reg_data->reg_update_cmd_data, + top_priv->last_mup_val); /* Disable sof irq debug flag */ rsrc_data->enable_sof_irq_debug = false; @@ -2122,6 +2587,44 @@ static int cam_tfe_camif_resource_start( return 0; } +static int cam_tfe_ppp_resource_start( + struct cam_tfe_hw_core_info *core_info, + struct cam_isp_resource_node *ppp_res) +{ + struct cam_tfe_ppp_data *rsrc_data; + uint32_t val = 0; + + if (!ppp_res || !core_info) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + if (ppp_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "TFE:%d Error Invalid camif res res_state:%d", + core_info->core_index, ppp_res->res_state); + return -EINVAL; + } + + rsrc_data = (struct cam_tfe_ppp_data *)ppp_res->res_priv; + + val = cam_io_r_mb(rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0); + + /* Config tfe core */ + val |= (1 << rsrc_data->reg_data->pdaf_path_en_shift); + + val |= (rsrc_data->core_cfg & (1 << rsrc_data->reg_data->lcr_dis_en_shift)); + + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_0); + + ppp_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + CAM_DBG(CAM_ISP, "TFE: %d Start PPP Done, core_cfg 0 val:0x%x", + core_info->core_index, + cam_io_r_mb(rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0)); + return 0; +} + int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, void *start_args, uint32_t arg_size) { @@ -2141,6 +2644,7 @@ int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; in_res = (struct cam_isp_resource_node *)start_args; hw_info = (struct cam_hw_info *)in_res->hw_intf->hw_priv; + atomic_set(&top_priv->switch_out_of_sync_cnt, 0); if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { CAM_ERR(CAM_ISP, "TFE:%d HW not powered up", @@ -2165,6 +2669,8 @@ int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { cam_tfe_camif_resource_start(core_info, in_res); + } else if (in_res->res_id == CAM_ISP_HW_TFE_IN_PDLIB) { + cam_tfe_ppp_resource_start(core_info, in_res); } else if (in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0 && in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2) { rsrc_rdi_data = (struct cam_tfe_rdi_data *) in_res->res_priv; @@ -2181,11 +2687,17 @@ int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, rsrc_rdi_data->rdi_reg->rdi_epoch_irq); /* Reg Update */ - cam_io_w_mb(rsrc_rdi_data->reg_data->reg_update_cmd_data, - rsrc_rdi_data->mem_base + + val = cam_io_r_mb(rsrc_rdi_data->mem_base + rsrc_rdi_data->rdi_reg->reg_update_cmd); + val |= rsrc_rdi_data->reg_data->reg_update_cmd_data; + cam_io_w_mb(val, rsrc_rdi_data->mem_base + rsrc_rdi_data->rdi_reg->reg_update_cmd); in_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d MUP val: %d", + in_res->hw_intf->hw_idx, + rsrc_rdi_data->reg_data->reg_update_cmd_data, + top_priv->last_mup_val); + /* Enable the irq */ if (in_res->is_rdi_primary_res) cam_tfe_irq_config(core_info, @@ -2212,6 +2724,9 @@ int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, cam_tfe_irq_config(core_info, core_info->tfe_hw_info->error_irq_mask, CAM_TFE_TOP_IRQ_REG_NUM, true); + cam_tfe_irq_config(core_info, + core_info->tfe_hw_info->non_fatal_error_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); top_priv->error_ts.tv_sec = 0; top_priv->error_ts.tv_nsec = 0; top_priv->sof_ts.tv_sec = 0; @@ -2234,6 +2749,7 @@ int cam_tfe_top_stop(struct cam_tfe_hw_core_info *core_info, struct cam_hw_info *hw_info = NULL; struct cam_tfe_camif_data *camif_data; struct cam_tfe_rdi_data *rsrc_rdi_data; + struct cam_tfe_ppp_data *ppp_data; uint32_t val = 0; int i, rc = 0; @@ -2271,7 +2787,15 @@ int cam_tfe_top_stop(struct cam_tfe_hw_core_info *core_info, cam_io_w_mb(val, camif_data->mem_base + camif_data->common_reg->diag_config); } - } else if ((in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) && + } else if (in_res->res_id == CAM_ISP_HW_TFE_IN_PDLIB) { + ppp_data = (struct cam_tfe_ppp_data *)in_res->res_priv; + + cam_io_w_mb(0, ppp_data->mem_base + + ppp_data->ppp_reg->ppp_module_config); + + if (in_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + in_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + } else if ((in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) && (in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2)) { rsrc_rdi_data = (struct cam_tfe_rdi_data *) in_res->res_priv; cam_io_w_mb(0x0, rsrc_rdi_data->mem_base + @@ -2304,11 +2828,16 @@ int cam_tfe_top_stop(struct cam_tfe_hw_core_info *core_info, } } + atomic_set(&top_priv->switch_out_of_sync_cnt, 0); core_info->irq_err_config_cnt--; - if (!core_info->irq_err_config_cnt) + if (!core_info->irq_err_config_cnt) { cam_tfe_irq_config(core_info, core_info->tfe_hw_info->error_irq_mask, CAM_TFE_TOP_IRQ_REG_NUM, false); + cam_tfe_irq_config(core_info, + core_info->tfe_hw_info->non_fatal_error_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + } return rc; } @@ -2324,6 +2853,7 @@ int cam_tfe_top_init( struct cam_tfe_soc_private *soc_private = NULL; struct cam_tfe_camif_data *camif_priv = NULL; struct cam_tfe_rdi_data *rdi_priv = NULL; + struct cam_tfe_ppp_data *ppp_priv = NULL; int i, j, rc = 0; top_priv = kzalloc(sizeof(struct cam_tfe_top_priv), @@ -2386,8 +2916,31 @@ int cam_tfe_top_init( camif_priv->hw_intf = hw_intf; camif_priv->soc_info = soc_info; - } else if (hw_info->in_port[i] == - CAM_TFE_RDI_VER_1_0) { + } else if (hw_info->in_port[i] == CAM_TFE_PDLIB_VER_1_0) { + top_priv->in_rsrc[i].res_id = + CAM_ISP_HW_TFE_IN_PDLIB; + + ppp_priv = kzalloc(sizeof(struct cam_tfe_ppp_data), + GFP_KERNEL); + if (!ppp_priv) { + CAM_DBG(CAM_ISP, + "TFE:%d Error Failed to alloc for ppp_priv", + core_info->core_index); + goto deinit_resources; + } + + top_priv->in_rsrc[i].res_priv = ppp_priv; + + ppp_priv->mem_base = + soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + ppp_priv->hw_intf = hw_intf; + ppp_priv->common_reg = hw_info->common_reg; + ppp_priv->ppp_reg = + hw_info->ppp_hw_info.ppp_reg; + ppp_priv->reg_data = + hw_info->ppp_hw_info.reg_data; + } else if (hw_info->in_port[i] == CAM_TFE_RDI_VER_1_0 && + (j < CAM_TFE_RDI_MAX)) { top_priv->in_rsrc[i].res_id = CAM_ISP_HW_TFE_IN_RDI0 + j; @@ -2411,8 +2964,8 @@ int cam_tfe_top_init( rdi_priv->reg_data = hw_info->rdi_hw_info[j++].reg_data; } else { - CAM_WARN(CAM_ISP, "TFE:%d Invalid inport type: %u", - core_info->core_index, hw_info->in_port[i]); + CAM_WARN(CAM_ISP, "TFE:%d Invalid inport type: %u at i = %d. j = %d", + core_info->core_index, hw_info->in_port[i], i, j); } } @@ -2868,7 +3421,8 @@ int cam_tfe_process_cmd(void *hw_priv, uint32_t cmd_type, if (!hw_priv) { CAM_ERR(CAM_ISP, "Invalid arguments"); - return -EINVAL; + rc = -EINVAL; + goto end; } soc_info = &tfe_hw->soc_info; @@ -2915,27 +3469,53 @@ int cam_tfe_process_cmd(void *hw_priv, uint32_t cmd_type, rc = cam_tfe_set_top_debug(core_info, cmd_args, arg_size); break; + case CAM_ISP_HW_CMD_DYNAMIC_CLOCK_UPDATE: + rc = cam_tfe_top_dynamic_clock_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_INIT_CONFIG_UPDATE: + rc = cam_tfe_top_init_config_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_NOTIFY_OVERFLOW: case CAM_ISP_HW_CMD_GET_BUF_UPDATE: case CAM_ISP_HW_CMD_GET_HFR_UPDATE: case CAM_ISP_HW_CMD_STRIPE_UPDATE: case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: case CAM_ISP_HW_CMD_GET_WM_SECURE_MODE: - case CAM_ISP_HW_CMD_IS_CONSUMED_ADDR_SUPPORT: + case CAM_ISP_HW_CMD_QUERY_CAP: case CAM_ISP_HW_CMD_GET_RES_FOR_MID: case CAM_ISP_HW_CMD_DUMP_BUS_INFO: case CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN: case CAM_ISP_HW_CMD_WM_BW_LIMIT_CONFIG: case CAM_ISP_HW_CMD_GET_LAST_CONSUMED_ADDR: + case CAM_ISP_HW_CMD_BUS_WM_DISABLE: + case CAM_ISP_HW_CMD_BUFFER_ALIGNMENT_UPDATE: + case CAM_ISP_HW_CMD_WM_CONFIG_UPDATE: rc = core_info->tfe_bus->hw_ops.process_cmd( core_info->tfe_bus->bus_priv, cmd_type, cmd_args, arg_size); break; + case CAM_ISP_HW_CMD_GET_PATH_PORT_MAP: + rc = cam_tfe_bus_get_path_port_map(hw_info->top_hw_info, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_SET_SYNC_HW_IDX: + rc = cam_tfe_set_sync_hw_idx(core_info, cmd_args, arg_size); + break; default: CAM_ERR(CAM_ISP, "TFE:%d Invalid cmd type:%d", core_info->core_index, cmd_type); rc = -EINVAL; break; } + +end: + if (rc) { + CAM_ERR(CAM_ISP, "TFE: %d error with cmd type: %d", + core_info->core_index, cmd_type); + } + return rc; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h index 0ef9aa7e27..7e95f25025 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -15,20 +16,22 @@ #define CAM_TFE_CAMIF_VER_1_0 0x10 #define CAM_TFE_RDI_VER_1_0 0x1000 +#define CAM_TFE_PDLIB_VER_1_0 0x10000 #define CAM_TFE_TOP_1_0 0x1000 -#define CAM_TFE_TOP_IN_PORT_MAX 4 +#define CAM_TFE_TOP_IN_PORT_MAX 5 #define CAM_TFE_RDI_MAX 4 #define CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS BIT(0) #define CAM_TFE_EVT_MAX 256 -#define CAM_TFE_MAX_REG_DUMP_ENTRIES 20 -#define CAM_TFE_MAX_LUT_DUMP_ENTRIES 10 +#define CAM_TFE_MAX_REG_DUMP_ENTRIES 20 +#define CAM_TFE_MAX_LUT_DUMP_ENTRIES 10 -#define CAM_TFE_MAX_CLC 40 -#define CAM_TFE_CLC_NAME_LENGTH_MAX 32 -#define CAM_TFE_MAX_DEBUG_REG 10 -#define CAM_TFE_MAX_PERF_CNT 2 +#define CAM_TFE_MAX_CLC 42 +#define CAM_TFE_CLC_NAME_LENGTH_MAX 32 +#define CAM_TFE_LITE_MAX_CLC 4 +#define CAM_TFE_MAX_DEBUG_REG 12 +#define CAM_TFE_MAX_PERF_CNT 2 /*we take each word as uint32_t, for dumping uint64_t count as 2 words * soc index @@ -85,7 +88,8 @@ struct cam_tfe_top_reg_offset_common { uint32_t stats_feature; uint32_t zoom_feature; uint32_t global_reset_cmd; - uint32_t core_cgc_ctrl; + uint32_t core_cgc_ctrl_0; + uint32_t core_cgc_ctrl_1; uint32_t ahb_cgc_ctrl; uint32_t core_cfg_0; uint32_t core_cfg_1; @@ -102,14 +106,42 @@ struct cam_tfe_top_reg_offset_common { uint32_t debug_cfg; uint32_t num_perf_cfg; struct cam_tfe_top_reg_perf_cfg perf_cfg[CAM_TFE_MAX_PERF_CNT]; + uint32_t diag_sensor_frame_cnt_status_1; /*reg data */ uint32_t diag_min_hbi_error_shift; uint32_t diag_neq_hbi_shift; uint32_t diag_sensor_hbi_mask; + uint32_t mup_shift_val; + + /* error bit data */ + uint32_t pp_camif_violation_bit; + uint32_t pp_violation_bit; + uint32_t ppp_camif_violation_bit; + uint32_t ppp_violation_bit; + uint32_t rdi0_camif_violation_bit; + uint32_t rdi1_camif_violation_bit; + uint32_t rdi2_camif_violation_bit; + uint32_t diag_violation_bit; + uint32_t dyamanic_switch_violation_bit; + uint32_t pp_frame_drop_bit; + uint32_t ppp_frame_drop_bit; + uint32_t rdi0_frame_drop_bit; + uint32_t rdi1_frame_drop_bit; + uint32_t rdi2_frame_drop_bit; + uint32_t pp_overflow_bit; + uint32_t ppp_overflow_bit; + uint32_t rdi0_overflow_bit; + uint32_t rdi1_overflow_bit; + uint32_t rdi2_overflow_bit; + uint32_t out_of_sync_frame_drop_bit; + uint32_t lcr_pd_timing_protocol_violation_bit; + uint32_t height_shift; + uint32_t epoch_shift_val; /* configuration */ bool serializer_supported; + bool mup_supported; }; struct cam_tfe_camif_reg { @@ -170,6 +202,9 @@ struct cam_tfe_camif_reg_data { uint32_t ai_c_srl_en_shift; uint32_t ds16_c_srl_en_shift; uint32_t ds4_c_srl_en_shift; + + uint32_t shdr_mode_shift; + uint32_t extern_mup_shift; }; struct cam_tfe_camif_hw_info { @@ -211,6 +246,34 @@ struct cam_tfe_rdi_reg_data { uint32_t diag_sensor_shift; }; +struct cam_tfe_ppp_reg { + uint32_t ppp_hw_version; + uint32_t ppp_hw_status; + uint32_t ppp_module_config; + uint32_t ppp_skip_period; + uint32_t ppp_irq_subsample_pattern; + uint32_t ppp_epoch_irq; + uint32_t ppp_debug_1; + uint32_t ppp_debug_0; + uint32_t ppp_test_bus_ctrl; + uint32_t ppp_spare; + uint32_t reg_update_cmd; +}; + +struct cam_tfe_ppp_reg_data { + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t eof_irq_mask; + uint32_t subscribe_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t enable_diagnostic_hw; + uint32_t diag_sensor_sel; + uint32_t diag_sensor_shift; + + uint32_t pdaf_path_en_shift; + uint32_t lcr_dis_en_shift; +}; + struct cam_tfe_clc_hw_status { uint8_t name[CAM_TFE_CLC_NAME_LENGTH_MAX]; uint32_t hw_status_reg; @@ -221,12 +284,20 @@ struct cam_tfe_rdi_hw_info { struct cam_tfe_rdi_reg_data *reg_data; }; +struct cam_tfe_ppp_hw_info { + struct cam_tfe_ppp_reg *ppp_reg; + struct cam_tfe_ppp_reg_data *reg_data; +}; + struct cam_tfe_top_hw_info { struct cam_tfe_top_reg_offset_common *common_reg; struct cam_tfe_camif_hw_info camif_hw_info; struct cam_tfe_rdi_hw_info rdi_hw_info[CAM_TFE_RDI_MAX]; + struct cam_tfe_ppp_hw_info ppp_hw_info; uint32_t in_port[CAM_TFE_TOP_IN_PORT_MAX]; struct cam_tfe_reg_dump_data reg_dump_data; + uint32_t num_path_port_map; + uint32_t path_port_map[CAM_ISP_HW_PATH_PORT_MAP_MAX][2]; }; struct cam_tfe_hw_info { @@ -249,6 +320,7 @@ struct cam_tfe_hw_info { uint32_t reset_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; uint32_t error_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t non_fatal_error_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; uint32_t bus_reg_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; uint32_t bus_error_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c index e8190bb813..63b0d6bbd5 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c @@ -1,18 +1,22 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include #include +#include #include "cam_tfe_dev.h" #include "cam_tfe_core.h" #include "cam_tfe_soc.h" #include "cam_debug_util.h" #include "camera_main.h" +#include "cam_cpas_api.h" static struct cam_isp_hw_intf_data cam_tfe_hw_list[CAM_TFE_HW_NUM_MAX]; +static uint32_t g_num_tfe_hws, g_num_tfe_lite_hws; static int cam_tfe_component_bind(struct device *dev, struct device *master_dev, void *data) @@ -25,17 +29,29 @@ static int cam_tfe_component_bind(struct device *dev, struct cam_tfe_soc_private *tfe_soc_priv; int rc = 0; struct platform_device *pdev = to_platform_device(dev); + uint32_t tfe_hw_idx = 0; uint32_t i; + CAM_DBG(CAM_ISP, "probe called"); + + rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &tfe_hw_idx); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to read cell-index of TFE HW, rc: %d", rc); + goto end; + } + + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_FUSE, BIT(tfe_hw_idx), NULL) || + !cam_cpas_is_feature_supported(CAM_CPAS_ISP_LITE_FUSE, BIT(tfe_hw_idx), NULL)) { + CAM_DBG(CAM_ISP, "TFE[%d] not supported based on fuse", tfe_hw_idx); + goto end; + } + tfe_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); if (!tfe_hw_intf) { rc = -ENOMEM; goto end; } - of_property_read_u32(pdev->dev.of_node, - "cell-index", &tfe_hw_intf->hw_idx); - tfe_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); if (!tfe_hw) { rc = -ENOMEM; @@ -46,6 +62,7 @@ static int cam_tfe_component_bind(struct device *dev, tfe_hw->soc_info.dev = &pdev->dev; tfe_hw->soc_info.dev_name = pdev->name; tfe_hw_intf->hw_priv = tfe_hw; + tfe_hw_intf->hw_idx = tfe_hw_idx; tfe_hw_intf->hw_ops.get_hw_caps = cam_tfe_get_hw_caps; tfe_hw_intf->hw_ops.init = cam_tfe_init_hw; tfe_hw_intf->hw_ops.deinit = cam_tfe_deinit_hw; @@ -195,11 +212,44 @@ const static struct component_ops cam_tfe_component_ops = { .unbind = cam_tfe_component_unbind, }; +void cam_tfe_get_num_tfe_hws(uint32_t *num_tfes) +{ + if (num_tfes) + *num_tfes = g_num_tfe_hws; + else + CAM_ERR(CAM_ISP, "Invalid argument, g_num_tfe_hws: %u", g_num_tfe_hws); +} + +void cam_tfe_get_num_tfe_lite_hws(uint32_t *num_tfe_lites) +{ + if (num_tfe_lites) + *num_tfe_lites = g_num_tfe_lite_hws; + else + CAM_ERR(CAM_ISP, "Invalid argument, g_num_tfe_lite_hws: %u", g_num_tfe_lite_hws); +} + int cam_tfe_probe(struct platform_device *pdev) { int rc = 0; + const char *compatible_name; + struct device_node *of_node = NULL; CAM_DBG(CAM_ISP, "Adding TFE component"); + + of_node = pdev->dev.of_node; + + rc = of_property_read_string_index(of_node, "compatible", 0, + (const char **)&compatible_name); + if (rc) + CAM_ERR(CAM_ISP, "No compatible string present for: %s, rc: %d", pdev->name, rc); + + if (strnstr(compatible_name, "lite", strlen(compatible_name)) != NULL) + g_num_tfe_lite_hws++; + else if (strnstr(compatible_name, "tfe", strlen(compatible_name)) != NULL) + g_num_tfe_hws++; + else + CAM_ERR(CAM_ISP, "Failed to increement number of TFEs/TFE-LITEs"); + rc = component_add(&pdev->dev, &cam_tfe_component_ops); if (rc) CAM_ERR(CAM_ISP, "failed to add component rc: %d", rc); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_lite770.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_lite770.h new file mode 100644 index 0000000000..b879a36032 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_lite770.h @@ -0,0 +1,589 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#ifndef _CAM_TFE_LITE770_H_ +#define _CAM_TFE_LITE770_H_ +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" + + +/* throtle cfg register not used, diag sensor frame cnt status1 */ +static struct cam_tfe_top_reg_offset_common tfe_lite770_top_commong_reg = { + .hw_version = 0x00001800, + .hw_capability = 0x00001804, + .lens_feature = 0x00001808, + .stats_feature = 0x0000180C, + .zoom_feature = 0x00001810, + .global_reset_cmd = 0x00001814, + .core_cgc_ctrl_0 = 0x00001818, + .core_cgc_ctrl_1 = 0x0000181C, + .ahb_cgc_ctrl = 0x00001820, + .core_cfg_0 = 0x00001824, + .reg_update_cmd = 0x0000182C, + .diag_config = 0x00001860, + .diag_sensor_status_0 = 0x00001864, + .diag_sensor_status_1 = 0x00001868, + .diag_sensor_frame_cnt_status = 0x0000186C, + .violation_status = 0x00001870, + .stats_throttle_cnt_cfg_0 = 0x00001874, + .stats_throttle_cnt_cfg_1 = 0x00001878, + .num_debug_reg = 12, + .debug_reg = { + 0x000018A0, + 0x000018A4, + 0x000018A8, + 0x000018AC, + 0x000018B0, + 0x000018B4, + 0x000018B8, + 0x000018BC, + 0x000018C0, + 0x000018C4, + 0x000018C8, + 0x000018CC, + }, + .debug_cfg = 0x000018DC, + .num_perf_cfg = 2, + .perf_cfg = { + { + .perf_cnt_cfg = 0x000018E0, + .perf_pixel_count = 0x000018E4, + .perf_line_count = 0x000018E8, + .perf_stall_count = 0x000018EC, + .perf_always_count = 0x000018F0, + .perf_count_status = 0x000018F4, + }, + { + .perf_cnt_cfg = 0x000018F8, + .perf_pixel_count = 0x000018FC, + .perf_line_count = 0x00001900, + .perf_stall_count = 0x00001904, + .perf_always_count = 0x00001908, + .perf_count_status = 0x0000190C, + }, + }, + .diag_sensor_frame_cnt_status_1 = 0x00001920, + .diag_min_hbi_error_shift = 15, + .diag_neq_hbi_shift = 14, + .diag_sensor_hbi_mask = 0x3FFF, + .serializer_supported = true, + .height_shift = 16, + .epoch_shift_val = 16, +}; + +static struct cam_tfe_rdi_reg tfe_lite770_rdi0_reg = { + .rdi_hw_version = 0x00001E00, + .rdi_hw_status = 0x00001E04, + .rdi_module_config = 0x00001E60, + .rdi_skip_period = 0x00001E68, + .rdi_irq_subsample_pattern = 0x00001E6C, + .rdi_epoch_irq = 0x00001E70, + .rdi_debug_1 = 0x00001FF0, + .rdi_debug_0 = 0x00001FF4, + .rdi_test_bus_ctrl = 0x00001FF8, + .rdi_spare = 0x00001FFC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe_lite770_rdi0_reg_data = { + .reg_update_cmd_data = 0x2, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000010, + .epoch0_irq_mask = 0x00000040, + .epoch1_irq_mask = 0x00000080, + .eof_irq_mask = 0x00000020, + .error_irq_mask0 = 0x00020200, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00000030, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x1, + .diag_sensor_shift = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe_lite770_rdi1_reg = { + .rdi_hw_version = 0x00002000, + .rdi_hw_status = 0x00002004, + .rdi_module_config = 0x00002060, + .rdi_skip_period = 0x00002068, + .rdi_irq_subsample_pattern = 0x0000206C, + .rdi_epoch_irq = 0x00002070, + .rdi_debug_1 = 0x000021F0, + .rdi_debug_0 = 0x000021F4, + .rdi_test_bus_ctrl = 0x000021F8, + .rdi_spare = 0x000021FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe_lite770_rdi1_reg_data = { + .reg_update_cmd_data = 0x4, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000100, + .epoch0_irq_mask = 0x00000400, + .epoch1_irq_mask = 0x00000800, + .eof_irq_mask = 0x00000200, + .error_irq_mask0 = 0x00040400, + .error_irq_mask2 = 0x00000008, + .subscribe_irq_mask = { + 0x00000000, + 0x00000300, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x2, + .diag_sensor_shift = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe_lite770_rdi2_reg = { + .rdi_hw_version = 0x00002200, + .rdi_hw_status = 0x00002204, + .rdi_module_config = 0x00002260, + .rdi_skip_period = 0x00002268, + .rdi_irq_subsample_pattern = 0x0000226C, + .rdi_epoch_irq = 0x00002270, + .rdi_debug_1 = 0x000023F0, + .rdi_debug_0 = 0x000023F4, + .rdi_test_bus_ctrl = 0x000023F8, + .rdi_spare = 0x000023FC, + .reg_update_cmd = 0x0000182C, +}; + +static struct cam_tfe_rdi_reg_data tfe_lite770_rdi2_reg_data = { + .reg_update_cmd_data = 0x8, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00001000, + .epoch0_irq_mask = 0x00004000, + .epoch1_irq_mask = 0x00008000, + .eof_irq_mask = 0x00002000, + .error_irq_mask0 = 0x00080800, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00003000, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .diag_sensor_sel = 0x3, + .diag_sensor_shift = 0x1, + +}; + +static struct cam_tfe_clc_hw_status tfe_lite770_clc_hw_info[CAM_TFE_LITE_MAX_CLC] = { + { + .name = "CLC_RDI0_CAMIF", + .hw_status_reg = 0x1E04, + }, + { + .name = "CLC_RDI1_CAMIF", + .hw_status_reg = 0x2004, + }, + { + .name = "CLC_RDI2_CAMIF", + .hw_status_reg = 0x2204, + }, +}; + +static struct cam_tfe_top_hw_info tfe_lite770_top_hw_info = { + .common_reg = &tfe_lite770_top_commong_reg, + .rdi_hw_info = { + { + .rdi_reg = &tfe_lite770_rdi0_reg, + .reg_data = &tfe_lite770_rdi0_reg_data, + }, + { + .rdi_reg = &tfe_lite770_rdi1_reg, + .reg_data = &tfe_lite770_rdi1_reg_data, + }, + { + .rdi_reg = &tfe_lite770_rdi2_reg, + .reg_data = &tfe_lite770_rdi2_reg_data, + }, + }, + .in_port = { + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0 + }, + .reg_dump_data = { + .num_reg_dump_entries = 19, + .num_lut_dump_entries = 0, + .bus_start_addr = 0x2000, + .bus_write_top_end_addr = 0x2120, + .bus_client_start_addr = 0x2200, + .bus_client_offset = 0x100, + .num_bus_clients = 10, + .reg_entry = { + { + .start_offset = 0x1000, + .end_offset = 0x10F4, + }, + { + .start_offset = 0x1260, + .end_offset = 0x1280, + }, + { + .start_offset = 0x13F0, + .end_offset = 0x13FC, + }, + { + .start_offset = 0x1460, + .end_offset = 0x1470, + }, + { + .start_offset = 0x15F0, + .end_offset = 0x15FC, + }, + { + .start_offset = 0x1660, + .end_offset = 0x1670, + }, + { + .start_offset = 0x17F0, + .end_offset = 0x17FC, + }, + { + .start_offset = 0x1860, + .end_offset = 0x1870, + }, + { + .start_offset = 0x19F0, + .end_offset = 0x19FC, + }, + { + .start_offset = 0x2660, + .end_offset = 0x2694, + }, + { + .start_offset = 0x2860, + .end_offset = 0x2884, + }, + { + .start_offset = 0x2A60, + .end_offset = 0X2B34, + }, + { + .start_offset = 0x2C60, + .end_offset = 0X2C80, + }, + { + .start_offset = 0x2E60, + .end_offset = 0X2E7C, + }, + { + .start_offset = 0x3060, + .end_offset = 0X3110, + }, + { + .start_offset = 0x3260, + .end_offset = 0X3278, + }, + { + .start_offset = 0x3460, + .end_offset = 0X3478, + }, + { + .start_offset = 0x3660, + .end_offset = 0X3684, + }, + { + .start_offset = 0x3860, + .end_offset = 0X3884, + }, + }, + .lut_entry = { + { + .lut_word_size = 1, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + .dmi_reg_offset = 0x2800, + }, + { + .lut_word_size = 1, + .lut_bank_sel = 0x41, + .lut_addr_size = 180, + .dmi_reg_offset = 0x3000, + }, + }, + }, +}; + +static struct cam_tfe_bus_hw_info tfe_lite770_bus_hw_info = { + .common_reg = { + .hw_version = 0x00003000, + .cgc_ovd = 0x00003008, + .comp_cfg_0 = 0x0000300C, + .comp_cfg_1 = 0x00003010, + .frameheader_cfg = { + 0x00003034, + 0x00003038, + 0x0000303C, + 0x00003040, + }, + .pwr_iso_cfg = 0x0000305C, + .overflow_status_clear = 0x00003060, + .ccif_violation_status = 0x00003064, + .overflow_status = 0x00003068, + .image_size_violation_status = 0x00003070, + .perf_count_cfg = { + 0x00003074, + 0x00003078, + 0x0000307C, + 0x00003080, + 0x00003084, + 0x00003088, + 0x0000308C, + 0x00003090, + }, + .perf_count_val = { + 0x00003094, + 0x00003098, + 0x0000309C, + 0x000030A0, + 0x000030A4, + 0x000030A8, + 0x000030AC, + 0x000030B0, + }, + .perf_count_status = 0x000030B4, + .debug_status_top_cfg = 0x000030D4, + .debug_status_top = 0x000030D8, + .test_bus_ctrl = 0x000030DC, + .irq_mask = { + 0x00003018, + 0x0000301C, + }, + .irq_clear = { + 0x00003020, + 0x00003024, + }, + .irq_status = { + 0x00003028, + 0x0000302C, + }, + .irq_cmd = 0x00003030, + .cons_violation_shift = 28, + .violation_shift = 30, + .image_size_violation = 31, + }, + .num_client = 3, + .bus_client_reg = { + { + .cfg = 0x00003900, + .image_addr = 0x00003904, + .frame_incr = 0x00003908, + .image_cfg_0 = 0x0000390C, + .image_cfg_1 = 0x00003910, + .image_cfg_2 = 0x00003914, + .packer_cfg = 0x00003918, + .bw_limit = 0x0000391C, + .frame_header_addr = 0x00003920, + .frame_header_incr = 0x00003924, + .frame_header_cfg = 0x00003928, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003930, + .irq_subsample_pattern = 0x00003934, + .framedrop_period = 0x00003938, + .framedrop_pattern = 0x0000393C, + .system_cache_cfg = 0x00003960, + .addr_status_0 = 0x00003968, + .addr_status_1 = 0x0000396C, + .addr_status_2 = 0x00003970, + .addr_status_3 = 0x00003974, + .debug_status_cfg = 0x00003978, + .debug_status_0 = 0x0000397C, + .debug_status_1 = 0x00003980, + .comp_group = CAM_TFE_BUS_COMP_GRP_5, + .client_name = "RDI0", + }, + /* BUS Client 8 RDI1 */ + { + .cfg = 0x00003A00, + .image_addr = 0x00003A04, + .frame_incr = 0x00003A08, + .image_cfg_0 = 0x00003A0C, + .image_cfg_1 = 0x00003A10, + .image_cfg_2 = 0x00003A14, + .packer_cfg = 0x00003A18, + .bw_limit = 0x00003A1C, + .frame_header_addr = 0x00003A20, + .frame_header_incr = 0x00003A24, + .frame_header_cfg = 0x00003A28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003A30, + .irq_subsample_pattern = 0x00003A34, + .framedrop_period = 0x00003A38, + .framedrop_pattern = 0x00003A3C, + .system_cache_cfg = 0x00003A60, + .addr_status_0 = 0x00003A68, + .addr_status_1 = 0x00003A6C, + .addr_status_2 = 0x00003A70, + .addr_status_3 = 0x00003A74, + .debug_status_cfg = 0x00003A78, + .debug_status_0 = 0x00003A7C, + .debug_status_1 = 0x00003A80, + .comp_group = CAM_TFE_BUS_COMP_GRP_6, + .client_name = "RDI1", + }, + /* BUS Client 9 RDI2 */ + { + .cfg = 0x00003B00, + .image_addr = 0x00003B04, + .frame_incr = 0x00003B08, + .image_cfg_0 = 0x00003B0C, + .image_cfg_1 = 0x00003B10, + .image_cfg_2 = 0x00003B14, + .packer_cfg = 0x00003B18, + .bw_limit = 0x00003B1C, + .frame_header_addr = 0x00003B20, + .frame_header_incr = 0x00003B24, + .frame_header_cfg = 0x00003B28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00003B30, + .irq_subsample_pattern = 0x00003B34, + .framedrop_period = 0x00003B38, + .framedrop_pattern = 0x00003B3C, + .system_cache_cfg = 0x00003B60, + .addr_status_0 = 0x00003B68, + .addr_status_1 = 0x00003B6C, + .addr_status_2 = 0x00003B70, + .addr_status_3 = 0x00003B74, + .debug_status_cfg = 0x00003B78, + .debug_status_0 = 0x00003B7C, + .debug_status_1 = 0x00003B80, + .comp_group = CAM_TFE_BUS_COMP_GRP_7, + .client_name = "RDI2", + }, + }, + .num_out = 3, + .tfe_out_hw_info = { + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_1, + .mid[0] = 4, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_1, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_2, + .mid[0] = 5, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_3, + .mid[0] = 6, + }, + }, + .num_comp_grp = 3, + .max_wm_per_comp_grp = 3, + .comp_done_shift = 8, + .top_bus_wr_irq_shift = 1, + .comp_buf_done_mask = 0xE000, + .comp_rup_done_mask = 0xF, + .bus_irq_error_mask = { + 0xD0000000, + 0x00000000, + }, + .support_consumed_addr = true, + .pdaf_rdi2_mux_en = false, + .rdi_width = 128, + .mode_cfg_shift = 16, + .height_shift = 16, +}; + +struct cam_tfe_hw_info cam_tfe_lite770 = { + .top_irq_mask = { + 0x00001834, + 0x00001838, + 0x0000183C, + }, + .top_irq_clear = { + 0x00001840, + 0x00001844, + 0x00001848, + }, + .top_irq_status = { + 0x0000184C, + 0x00001850, + 0x00001854, + }, + .top_irq_cmd = 0x00001830, + .global_clear_bitmask = 0x00000001, + .bus_irq_mask = { + 0x00003018, + 0x0000301C, + }, + .bus_irq_clear = { + 0x00003020, + 0x00003024, + }, + .bus_irq_status = { + 0x00003028, + 0x0000302C, + }, + .bus_irq_cmd = 0x00003030, + .bus_violation_reg = 0x00003064, + .bus_overflow_reg = 0x00003068, + .bus_image_size_vilation_reg = 0x3070, + .bus_overflow_clear_cmd = 0x3060, + .debug_status_top = 0x30D8, + + .reset_irq_mask = { + 0x00000001, + 0x00000000, + 0x00000000, + }, + .error_irq_mask = { + 0x001F1F00, + 0x00000000, + 0x0000003F, + }, + .non_fatal_error_irq_mask = { + 0x00200000, + 0x00000000, + 0x00000000, + }, + .bus_reg_irq_mask = { + 0x00000002, + 0x00000000, + }, + .bus_error_irq_mask = { + 0xC0000000, + 0x00000000, + }, + + .num_clc = 3, + .clc_hw_status_info = tfe_lite770_clc_hw_info, + .bus_version = CAM_TFE_BUS_1_0, + .bus_hw_info = &tfe_lite770_bus_hw_info, + + .top_version = CAM_TFE_TOP_1_0, + .top_hw_info = &tfe_lite770_top_hw_info, +}; + +#endif /* _CAM_TFE_LITE770__H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c index f846160aae..17a706230f 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c @@ -45,6 +45,20 @@ int cam_tfe_init_soc_resources(struct cam_hw_soc_info *soc_info, goto free_soc_private; } + soc_private->is_tfe_lite = false; + if (strnstr(soc_info->compatible, "lite", + strlen(soc_info->compatible)) != NULL) + soc_private->is_tfe_lite = true; + + rc = of_property_read_u32(soc_info->pdev->dev.of_node, "rt-wrapper-base", + &soc_private->rt_wrapper_base); + if (rc) { + soc_private->rt_wrapper_base = 0; + CAM_DBG(CAM_ISP, "rc: %d Error reading rt_wrapper_base for core_idx: %u", + rc, soc_info->index); + rc = 0; + } + /* set some default values */ soc_private->num_pid = 0; @@ -164,7 +178,10 @@ int cam_tfe_enable_soc_resources( ahb_vote.type = CAM_VOTE_ABSOLUTE; ahb_vote.vote.level = CAM_LOWSVS_D1_VOTE; axi_vote.num_paths = 1; - axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_IFE_VID; + if (soc_private->is_tfe_lite) + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_IFE_RDI1; + else + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_IFE_VID; axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_RT_AXI_BW; axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_RT_AXI_BW; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h index 11ae1591cb..0894d58c03 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h @@ -30,13 +30,16 @@ enum cam_cpas_handle_id { * @dsp_clk_index: DSP clk index in optional clocks * @num_pid: number of pids of tfe * @pid: TFE pid value list + * @is_tfe_lite: Flag to indicate if it is TFE Lite HW */ struct cam_tfe_soc_private { uint32_t cpas_handle; uint32_t cpas_version; + uint32_t rt_wrapper_base; int32_t dsp_clk_index; uint32_t num_pid; uint32_t pid[CAM_ISP_HW_MAX_PID_VAL]; + bool is_tfe_lite; }; /* diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c index 4a8c7b2351..0fbd8e4044 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -529,6 +529,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type, case CAM_ISP_HW_CMD_UBWC_UPDATE_V2: case CAM_ISP_HW_CMD_WM_CONFIG_UPDATE: case CAM_ISP_HW_CMD_GET_WM_SECURE_MODE: + case CAM_ISP_HW_CMD_GET_LAST_CONSUMED_ADDR: case CAM_ISP_HW_CMD_UNMASK_BUS_WR_IRQ: case CAM_ISP_HW_CMD_DUMP_BUS_INFO: case CAM_ISP_HW_CMD_GET_RES_FOR_MID: @@ -539,7 +540,6 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type, case CAM_ISP_HW_CMD_MC_CTXT_SEL: case CAM_ISP_HW_CMD_IRQ_INJECTION: case CAM_ISP_HW_CMD_DUMP_IRQ_DESCRIPTION: - case CAM_ISP_HW_CMD_GET_LAST_CONSUMED_ADDR: rc = core_info->vfe_bus->hw_ops.process_cmd( core_info->vfe_bus->bus_priv, cmd_type, cmd_args, arg_size); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c index b5027fc044..73d03bd527 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -15,12 +15,14 @@ #include "cam_vfe680.h" #include "cam_vfe680_110.h" #include "cam_vfe780.h" +#include "cam_vfe860.h" #include "cam_vfe880.h" #include "cam_tfe980.h" #include "cam_vfe_lite17x.h" #include "cam_vfe_lite48x.h" #include "cam_vfe_lite68x.h" #include "cam_vfe_lite78x.h" +#include "cam_vfe_lite86x.h" #include "cam_vfe_lite88x.h" #include "cam_vfe_lite98x.h" #include "cam_vfe_hw_intf.h" @@ -69,6 +71,10 @@ static const struct of_device_id cam_vfe_dt_match[] = { .compatible = "qcom,vfe780", .data = &cam_vfe780_hw_info, }, + { + .compatible = "qcom,vfe860", + .data = &cam_vfe860_hw_info, + }, { .compatible = "qcom,vfe880", .data = &cam_vfe880_hw_info, @@ -109,6 +115,10 @@ static const struct of_device_id cam_vfe_dt_match[] = { .compatible = "qcom,vfe-lite780", .data = &cam_vfe_lite78x_hw_info, }, + { + .compatible = "qcom,vfe-lite860", + .data = &cam_vfe_lite86x_hw_info, + }, { .compatible = "qcom,vfe-lite880", .data = &cam_vfe_lite88x_hw_info, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h index 2370f490c8..daaa66d0b6 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h @@ -1876,6 +1876,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "RDI_0", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI1, @@ -1892,6 +1893,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "RDI_1", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI2, @@ -1908,6 +1910,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "RDI_2", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FULL, @@ -1925,6 +1928,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { "FULL_Y", "FULL_C", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS4, @@ -1940,6 +1944,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "DS_4", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS16, @@ -1955,6 +1960,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "DS_16", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP, @@ -1970,6 +1976,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "PIXEL_RAW", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FD, @@ -1987,6 +1994,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { "FD_Y", "FD_C", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_2PD, @@ -2002,6 +2010,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "PDAF_0_2PD", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = @@ -2018,6 +2027,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "STATS_TL_BG", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_CAF, @@ -2033,6 +2043,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "STATS_BF", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG, @@ -2048,6 +2059,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "STATS_AWB_BGB", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST, @@ -2063,6 +2075,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "STATS_BHIST", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BAYER_RS, @@ -2078,6 +2091,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "STATS_RS", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST, @@ -2093,6 +2107,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "STATS_IHIST", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP, @@ -2110,6 +2125,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { "FULL_DISP_Y", "FULL_DISP_C", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP, @@ -2125,6 +2141,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "DISP_DS_4", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP, @@ -2140,6 +2157,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "DISP_DS_16", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_PREPROCESS_2PD, @@ -2155,6 +2173,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "PDAF_1_PREPROCESS_2PD", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_AWB_BFW, @@ -2170,6 +2189,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "AWB_BFW", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_PDAF_PARSED, @@ -2185,6 +2205,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "PDAF_2_PARSED_DATA", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AEC_BE, @@ -2200,6 +2221,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "AEC_BE", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_LTM_STATS, @@ -2215,6 +2237,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "LTM", }, + .pid_mask = 0x700000, }, { .vfe_out_type = @@ -2231,6 +2254,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = { .name = { "GTM_BHIST", }, + .pid_mask = 0x700000, }, }, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe860.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe860.h new file mode 100644 index 0000000000..fb5ec82f13 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe860.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_VFE860_H_ +#define _CAM_VFE860_H_ +#include "cam_vfe_top_ver4.h" +#include "cam_vfe_core.h" +#include "cam_vfe_bus_ver3.h" +#include "cam_irq_controller.h" +#include "cam_vfe880.h" + +static struct cam_vfe_top_ver4_reg_offset_common vfe860_top_common_reg = { + .hw_version = 0x00000000, + .hw_capability = 0x00000004, + .lens_feature = 0x00000008, + .stats_feature = 0x0000000C, + .color_feature = 0x00000010, + .zoom_feature = 0x00000014, + .core_cfg_0 = 0x00000024, + .core_cfg_1 = 0x00000028, + .core_cfg_2 = 0x0000002C, + .global_reset_cmd = 0x00000030, + .diag_config = 0x00000050, + .diag_sensor_status_0 = 0x00000054, + .diag_sensor_status_1 = 0x00000058, + .diag_frm_cnt_status_0 = 0x0000005C, + .diag_frm_cnt_status_1 = 0x00000060, + .ipp_violation_status = 0x00000064, + .pdaf_violation_status = 0x00000404, + .core_cgc_ovd_0 = 0x00000018, + .core_cgc_ovd_1 = 0x0000001C, + .ahb_cgc_ovd = 0x00000020, + .dsp_status = 0x0000006C, + .stats_throttle_cfg_0 = 0x00000070, + .stats_throttle_cfg_1 = 0x00000074, + .stats_throttle_cfg_2 = 0x00000078, + .core_cfg_4 = 0x00000080, + .core_cfg_5 = 0x00000084, + .core_cfg_6 = 0x00000088, + .period_cfg = 0x0000008C, + .irq_sub_pattern_cfg = 0x00000090, + .epoch0_pattern_cfg = 0x00000094, + .epoch1_pattern_cfg = 0x00000098, + .epoch_height_cfg = 0x0000009C, + .bus_violation_status = 0x00000C64, + .bus_overflow_status = 0x00000C68, + .num_perf_counters = 2, + .perf_count_reg = { + { + .perf_count_cfg = 0x00000100, + .perf_pix_count = 0x00000104, + .perf_line_count = 0x00000108, + .perf_stall_count = 0x0000010C, + .perf_always_count = 0x00000110, + .perf_count_status = 0x00000114, + }, + { + .perf_count_cfg = 0x00000118, + .perf_pix_count = 0x0000011C, + .perf_line_count = 0x00000120, + .perf_stall_count = 0x00000124, + .perf_always_count = 0x00000128, + .perf_count_status = 0x0000012C, + }, + }, + .top_debug_cfg = 0x000000FC, + .num_top_debug_reg = CAM_VFE_880_NUM_DBG_REG, + .pdaf_input_cfg_0 = 0x00000130, + .pdaf_input_cfg_1 = 0x00000134, + .top_debug = vfe880_top_debug_reg, + .frame_timing_irq_reg_idx = CAM_IFE_IRQ_CAMIF_REG_STATUS1, +}; + +struct cam_vfe_ver4_path_hw_info + vfe860_rdi_hw_info_arr[] = { + { + .common_reg = &vfe860_top_common_reg, + .reg_data = &vfe880_vfe_full_rdi_reg_data[0], + }, + { + .common_reg = &vfe860_top_common_reg, + .reg_data = &vfe880_vfe_full_rdi_reg_data[1], + }, + { + .common_reg = &vfe860_top_common_reg, + .reg_data = &vfe880_vfe_full_rdi_reg_data[2], + }, +}; + +static struct cam_vfe_top_ver4_hw_info vfe860_top_hw_info = { + .common_reg = &vfe860_top_common_reg, + .vfe_full_hw_info = { + .common_reg = &vfe860_top_common_reg, + .reg_data = &vfe880_pp_common_reg_data, + }, + .pdlib_hw_info = { + .common_reg = &vfe860_top_common_reg, + .reg_data = &vfe880_pdlib_reg_data, + }, + .rdi_hw_info = vfe860_rdi_hw_info_arr, + .wr_client_desc = vfe880_wr_client_desc, + .ipp_module_desc = vfe880_ipp_mod_desc, + .num_mux = 5, + .mux_type = { + CAM_VFE_CAMIF_VER_4_0, + CAM_VFE_PDLIB_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + }, + .num_path_port_map = 3, + .path_port_map = { + {CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_2PD}, + {CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PREPROCESS_2PD}, + {CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PDAF_PARSED_DATA}, + }, + .num_rdi = ARRAY_SIZE(vfe860_rdi_hw_info_arr), + .num_top_errors = ARRAY_SIZE(vfe880_top_irq_err_desc), + .top_err_desc = vfe880_top_irq_err_desc, + .num_pdaf_violation_errors = ARRAY_SIZE(vfe880_pdaf_violation_desc), + .pdaf_violation_desc = vfe880_pdaf_violation_desc, + .debug_reg_info = &vfe880_dbg_reg_info, + .pdaf_lcr_res_mask = vfe880_pdaf_lcr_res_mask, + .num_pdaf_lcr_res = ARRAY_SIZE(vfe880_pdaf_lcr_res_mask), + .fcg_module_info = &vfe880_fcg_module_info, + .fcg_supported = true, +}; + +static struct cam_vfe_hw_info cam_vfe860_hw_info = { + .irq_hw_info = &vfe880_irq_hw_info, + + .bus_version = CAM_VFE_BUS_VER_3_0, + .bus_hw_info = &vfe880_bus_hw_info, + + .top_version = CAM_VFE_TOP_VER_4_0, + .top_hw_info = &vfe860_top_hw_info, +}; + +#endif /* _CAM_VFE860_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe880.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe880.h index e884e48565..7913b7d537 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe880.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe880.h @@ -994,11 +994,11 @@ static uint32_t vfe880_out_port_mid[][4] = { {34, 0, 0, 0}, {35, 0, 0, 0}, {36, 0, 0, 0}, - {16, 17, 18, 19}, - {20, 0, 0, 0}, - {21, 0, 0, 0}, + {8, 9, 10, 11}, + {11, 0, 0, 0}, + {12, 0, 0, 0}, {32, 33, 0, 0}, - {28, 29, 30, 0}, + {27, 28, 29, 0}, {8, 0, 0, 0}, {18, 0, 0, 0}, {21, 0, 0, 0}, @@ -1006,9 +1006,9 @@ static uint32_t vfe880_out_port_mid[][4] = { {17, 0, 0, 0}, {23, 0, 0, 0}, {24, 0, 0, 0}, - {22, 23, 24, 25}, - {26, 0, 0, 0}, - {27, 0, 0, 0}, + {12, 13, 14, 15}, + {13, 0, 0, 0}, + {14, 0, 0, 0}, {9, 0, 0, 0}, {20, 0, 0, 0}, {10, 0, 0, 0}, @@ -1962,6 +1962,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "RDI_0", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI1, @@ -1978,6 +1979,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "RDI_1", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI2, @@ -1994,6 +1996,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "RDI_2", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FULL, @@ -2011,6 +2014,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { "FULL_Y", "FULL_C", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS4, @@ -2026,6 +2030,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "DS_4", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS16, @@ -2041,6 +2046,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "DS_16", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP, @@ -2056,6 +2062,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "PIXEL_RAW", }, + .pid_mask = 0x700, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FD, @@ -2073,6 +2080,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { "FD_Y", "FD_C", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_2PD, @@ -2088,6 +2096,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "PDAF_0_2PD", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = @@ -2104,6 +2113,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "STATS_TL_BG", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_CAF, @@ -2119,6 +2129,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "STATS_BF", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG, @@ -2134,6 +2145,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "STATS_AWB_BGB", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST, @@ -2149,6 +2161,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "STATS_BHIST", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BAYER_RS, @@ -2164,6 +2177,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "STATS_RS", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST, @@ -2179,6 +2193,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "STATS_IHIST", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP, @@ -2196,6 +2211,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { "FULL_DISP_Y", "FULL_DISP_C", }, + .pid_mask = 0x70000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP, @@ -2211,6 +2227,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "DISP_DS_4", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP, @@ -2226,6 +2243,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "DISP_DS_16", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_PREPROCESS_2PD, @@ -2241,6 +2259,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "PDAF_1_PREPROCESS_2PD", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_AWB_BFW, @@ -2256,6 +2275,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "AWB_BFW", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_PDAF_PARSED, @@ -2271,6 +2291,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "PDAF_2_PARSED_DATA", }, + .pid_mask = 0x7000000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AEC_BE, @@ -2286,6 +2307,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "AEC_BE", }, + .pid_mask = 0x700000, }, { .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_LTM_STATS, @@ -2301,6 +2323,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "LTM", }, + .pid_mask = 0x700000, }, { .vfe_out_type = @@ -2317,6 +2340,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "GTM_BHIST", }, + .pid_mask = 0x700000, }, { .vfe_out_type = @@ -2333,6 +2357,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = { .name = { "STATS_ALSC", }, + .pid_mask = 0x700000, }, }, diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite86x.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite86x.h new file mode 100644 index 0000000000..6b7305249c --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite86x.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#ifndef _CAM_VFE_LITE86X_H_ +#define _CAM_VFE_LITE86X_H_ +#include "cam_vfe_camif_ver3.h" +#include "cam_vfe_top_ver4.h" +#include "cam_vfe_core.h" +#include "cam_vfe_bus_ver3.h" +#include "cam_irq_controller.h" +#include "cam_vfe_lite78x.h" +#include "cam_vfe_lite88x.h" + +static struct cam_vfe_top_ver4_reg_offset_common vfe_lite86x_top_common_reg = { + .hw_version = 0x00001000, + .hw_capability = 0x00001004, + .core_cgc_ovd_0 = 0x00001014, + .ahb_cgc_ovd = 0x00001018, + .core_cfg_0 = 0x0000103C, + .diag_config = 0x00001040, + .diag_sensor_status_0 = 0x00001044, + .diag_sensor_status_1 = 0x00001048, + .ipp_violation_status = 0x00001054, + .bus_violation_status = 0x00001264, + .bus_overflow_status = 0x00001268, + .top_debug_cfg = 0x00001074, + .num_top_debug_reg = CAM_VFE_88X_NUM_DBG_REG, + .top_debug = vfe_lite88x_top_debug_reg, + .frame_timing_irq_reg_idx = CAM_IFE_IRQ_CAMIF_REG_STATUS1, +}; + +static struct cam_vfe_ver4_path_hw_info + vfe_lite86x_rdi_hw_info[] = { + { + .common_reg = &vfe_lite86x_top_common_reg, + .reg_data = &vfe_lite88x_rdi_reg_data[0], + }, + { + .common_reg = &vfe_lite86x_top_common_reg, + .reg_data = &vfe_lite88x_rdi_reg_data[1], + }, + { + .common_reg = &vfe_lite86x_top_common_reg, + .reg_data = &vfe_lite88x_rdi_reg_data[2], + }, + { + .common_reg = &vfe_lite86x_top_common_reg, + .reg_data = &vfe_lite88x_rdi_reg_data[3], + }, +}; + +static struct cam_vfe_top_ver4_hw_info vfe_lite86x_top_hw_info = { + .common_reg = &vfe_lite86x_top_common_reg, + .rdi_hw_info = vfe_lite86x_rdi_hw_info, + .vfe_full_hw_info = { + .common_reg = &vfe_lite86x_top_common_reg, + .reg_data = &vfe_lite88x_ipp_reg_data, + }, + .ipp_module_desc = vfe_lite78x_ipp_mod_desc, + .wr_client_desc = vfe_lite78x_wr_client_desc, + .num_mux = 5, + .mux_type = { + CAM_VFE_CAMIF_VER_4_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + }, + .debug_reg_info = &vfe78x_dbg_reg_info, + .num_rdi = ARRAY_SIZE(vfe_lite88x_rdi_hw_info), +}; + +static struct cam_vfe_hw_info cam_vfe_lite86x_hw_info = { + .irq_hw_info = &vfe_lite88x_irq_hw_info, + + .bus_version = CAM_VFE_BUS_VER_3_0, + .bus_hw_info = &vfe_lite88x_bus_hw_info, + + .top_version = CAM_VFE_TOP_VER_4_0, + .top_hw_info = &vfe_lite86x_top_hw_info, +}; + +#endif /* _CAM_VFE_LITE86X_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c index 74dde7a469..65c6bd4f54 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c @@ -3637,11 +3637,6 @@ int cam_vfe_bus_dump_wm_data(void *priv, void *cmd_args, uint32_t arg_size) enum cam_vfe_bus_ver2_vfe_out_type vfe_out_res_id; vfe_out_res_id = cam_vfe_bus_get_out_res_id(event_info->res_id); - if (vfe_out_res_id >= CAM_VFE_BUS_VER2_VFE_OUT_MAX) { - CAM_ERR(CAM_ISP, "Unsupported res_id: %u", vfe_out_res_id); - return -EINVAL; - } - rsrc_node = &bus_priv->vfe_out[vfe_out_res_id]; rsrc_data = rsrc_node->res_priv; for (i = 0; i < rsrc_data->num_wm; i++) { diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c index d8915ba4bc..25ad1dd1fc 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -50,6 +50,13 @@ static uint32_t bus_error_irq_mask[2] = { 0x00000000, }; +enum cam_vfe_bus_wr_wm_mode { + CAM_VFE_WM_LINE_BASED_MODE, + CAM_VFE_WM_FRAME_BASED_MODE, + CAM_VFE_WM_INDEX_BASED_MODE, + CAM_VFE_WM_MODE_MAX, +}; + enum cam_vfe_bus_ver3_packer_format { PACKER_FMT_VER3_PLAIN_128, PACKER_FMT_VER3_PLAIN_8, @@ -160,6 +167,7 @@ struct cam_vfe_bus_ver3_wm_resource_data { uint32_t default_line_based; bool use_wm_pack; bool update_wm_format; + enum cam_vfe_bus_wr_wm_mode wm_mode; }; struct cam_vfe_bus_ver3_comp_grp_data { @@ -207,6 +215,7 @@ struct cam_vfe_bus_ver3_vfe_out_data { bool mc_based; bool cntxt_cfg_except; uint32_t dst_hw_ctxt_id_mask; + uint64_t pid_mask; }; struct cam_vfe_bus_ver3_priv { @@ -765,141 +774,99 @@ static int cam_vfe_bus_ver3_handle_rup_bottom_half(void *handler_priv, return ret; } +static inline void cam_vfe_bus_ver3_config_frame_based_rdi_wm( + struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data) +{ + rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; +} + static int cam_vfe_bus_ver3_config_rdi_wm( struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data) { rsrc_data->pack_fmt = PACKER_FMT_VER3_PLAIN_128; + + if (rsrc_data->wm_mode == CAM_VFE_WM_FRAME_BASED_MODE) + cam_vfe_bus_ver3_config_frame_based_rdi_wm(rsrc_data); + else if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) + rsrc_data->en_cfg = 0x1; + else { + CAM_WARN(CAM_ISP, "No index mode %d is supported for VFE: %u WM: %u", + rsrc_data->wm_mode, + rsrc_data->common_data->core_index, + rsrc_data->index); + return 0; + } + switch (rsrc_data->format) { case CAM_FORMAT_MIPI_RAW_10: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; - rsrc_data->width = - ALIGNUP((rsrc_data->width * 5) / 4, 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) + rsrc_data->width = ALIGNUP((rsrc_data->width * 5) / 4, 16) / 16; if (rsrc_data->use_wm_pack) { rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI10; - if (rsrc_data->default_line_based) + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 8); } break; case CAM_FORMAT_MIPI_RAW_6: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 3) / 4, 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } break; case CAM_FORMAT_MIPI_RAW_8: case CAM_FORMAT_YUV422: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP(rsrc_data->width, 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } break; case CAM_FORMAT_MIPI_RAW_12: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 3) / 2, 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } if (rsrc_data->use_wm_pack) { rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI12; - if (rsrc_data->default_line_based) + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 8); } break; case CAM_FORMAT_MIPI_RAW_14: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 7) / 2, 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } if (rsrc_data->use_wm_pack) { rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI14; - if (rsrc_data->default_line_based) + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 8); } break; case CAM_FORMAT_MIPI_RAW_16: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 2), 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } break; case CAM_FORMAT_MIPI_RAW_20: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 5) / 2, 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } if (rsrc_data->use_wm_pack) rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI20; break; case CAM_FORMAT_PLAIN128: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 16), 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } break; case CAM_FORMAT_PLAIN32_20: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 4), 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } break; case CAM_FORMAT_PLAIN8: rsrc_data->en_cfg = 0x1; @@ -920,7 +887,7 @@ static int cam_vfe_bus_ver3_config_rdi_wm( rsrc_data->pack_fmt |= (1 << rsrc_data->common_data->pack_align_shift); - if (rsrc_data->default_line_based) + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 8); } break; @@ -930,16 +897,9 @@ static int cam_vfe_bus_ver3_config_rdi_wm( rsrc_data->en_cfg = 0x1; break; case CAM_FORMAT_YUV422_10: - if (rsrc_data->default_line_based) { - rsrc_data->en_cfg = 0x1; + if (rsrc_data->wm_mode == CAM_VFE_WM_LINE_BASED_MODE) rsrc_data->width = ALIGNUP((rsrc_data->width * 5) / 4, 16) / 16; - } else { - rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } break; default: CAM_ERR(CAM_ISP, "VFE:%u Unsupported RDI format %d", @@ -989,6 +949,11 @@ static int cam_vfe_bus_ver3_acquire_wm( if ((vfe_out_res_id >= CAM_VFE_BUS_VER3_VFE_OUT_RDI0) && (vfe_out_res_id <= CAM_VFE_BUS_VER3_VFE_OUT_RDI3)) { + if (rsrc_data->default_line_based) + rsrc_data->wm_mode = CAM_VFE_WM_LINE_BASED_MODE; + else + rsrc_data->wm_mode = CAM_VFE_WM_FRAME_BASED_MODE; + rc = cam_vfe_bus_ver3_config_rdi_wm(rsrc_data); if (rc) return rc; @@ -1703,9 +1668,10 @@ static int cam_vfe_bus_ver3_handle_comp_done_bottom_half( uint32_t *cam_ife_irq_regs; uint32_t status_0; - if (!evt_payload) + if (!evt_payload || !rsrc_data) { + CAM_ERR(CAM_ISP, "Either evt_payload or rsrc_data is invalid"); return rc; - + } if (rsrc_data->is_dual && (!rsrc_data->is_master)) { CAM_ERR(CAM_ISP, "VFE:%u Invalid comp_grp:%u is_master:%u", rsrc_data->common_data->core_index, rsrc_data->comp_grp_type, @@ -2305,6 +2271,11 @@ static int cam_vfe_bus_ver3_handle_vfe_out_done_bottom_half( uint32_t evt_id = 0; uint32_t comp_grp_id = 0; + if (!rsrc_data) { + CAM_ERR(CAM_ISP, "Invalid rsrc data pointer, returning from bottom half"); + return rc; + } + rc = cam_vfe_bus_ver3_handle_comp_done_bottom_half( rsrc_data, evt_payload_priv, &comp_grp_id); CAM_DBG(CAM_ISP, "VFE:%u out_type:0x%x comp_grp_id:%d rc:%d", @@ -2414,6 +2385,8 @@ static int cam_vfe_bus_ver3_init_vfe_out_resource(uint32_t index, } } + rsrc_data->pid_mask = ver3_hw_info->vfe_out_hw_info[index].pid_mask; + vfe_out->start = cam_vfe_bus_ver3_start_vfe_out; vfe_out->stop = cam_vfe_bus_ver3_stop_vfe_out; vfe_out->top_half_handler = @@ -3949,7 +3922,7 @@ static int cam_vfe_bus_ver3_update_wm_config( for (i = 0; i < vfe_out_data->num_wm; i++) { wm_data = vfe_out_data->wm_res[i].res_priv; - if (wm_config->wm_mode > 0x2) { + if (wm_config->wm_mode >= CAM_VFE_WM_MODE_MAX) { CAM_ERR(CAM_ISP, "VFE:%u Invalid wm_mode: 0x%X WM:%d", vfe_out_data->common_data->core_index, wm_config->wm_mode, wm_data->index); @@ -3980,8 +3953,12 @@ static int cam_vfe_bus_ver3_update_wm_config( /* Reconfigure only for valid packer fmt */ if (packer_fmt != PACKER_FMT_VER3_MAX) { if ((vfe_out_data->out_type >= CAM_VFE_BUS_VER3_VFE_OUT_RDI0) && - (vfe_out_data->out_type <= CAM_VFE_BUS_VER3_VFE_OUT_RDI3)) - cam_vfe_bus_ver3_config_rdi_wm(wm_data); + (vfe_out_data->out_type <= CAM_VFE_BUS_VER3_VFE_OUT_RDI3)) { + if (wm_config->wm_mode != wm_data->wm_mode) { + wm_data->wm_mode = wm_config->wm_mode; + cam_vfe_bus_ver3_config_rdi_wm(wm_data); + } + } /* LSB aligned for plain type format */ switch (wm_config->packer_format) { @@ -4346,7 +4323,9 @@ static int cam_vfe_bus_get_res_for_mid( struct cam_vfe_bus_ver3_vfe_out_data *out_data = NULL; struct cam_isp_hw_get_cmd_update *cmd_update = cmd_args; struct cam_isp_hw_get_res_for_mid *get_res = NULL; + uint32_t num_mid = 0, port_mid[CAM_VFE_BUS_VER3_VFE_OUT_MAX] = {0}; int i, j; + bool pid_found = false; get_res = (struct cam_isp_hw_get_res_for_mid *)cmd_update->data; if (!get_res) { @@ -4364,11 +4343,22 @@ static int cam_vfe_bus_get_res_for_mid( for (j = 0; j < out_data->num_mid; j++) { if (out_data->mid[j] == get_res->mid) - goto end; + port_mid[num_mid++] = i; } } - if (i == bus_priv->num_out) { + for (i = 0; i < num_mid; i++) { + out_data = (struct cam_vfe_bus_ver3_vfe_out_data *) + bus_priv->vfe_out[i].res_priv; + get_res->out_res_id = bus_priv->vfe_out[port_mid[i]].res_id; + if (out_data->pid_mask & (1 << get_res->pid)) { + get_res->out_res_id = bus_priv->vfe_out[port_mid[i]].res_id; + pid_found = true; + goto end; + } + } + + if (!num_mid) { CAM_ERR(CAM_ISP, "VFE:%u mid:%d does not match with any out resource", bus_priv->common_data.core_index, get_res->mid); @@ -4377,9 +4367,9 @@ static int cam_vfe_bus_get_res_for_mid( } end: - CAM_INFO(CAM_ISP, "VFE:%u match mid :%d out resource:0x%x found", - bus_priv->common_data.core_index, get_res->mid, bus_priv->vfe_out[i].res_id); - get_res->out_res_id = bus_priv->vfe_out[i].res_id; + CAM_INFO(CAM_ISP, "VFE:%u match mid :%d out resource:0x%x found, is pid found %d", + bus_priv->common_data.core_index, get_res->mid, bus_priv->vfe_out[i].res_id, + pid_found); return 0; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h index 6c91f4b4f2..d953120221 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h @@ -224,8 +224,9 @@ struct cam_vfe_bus_ver3_vfe_out_hw_info { uint32_t wm_idx[PLANE_MAX]; uint32_t mc_grp_shift; uint8_t *name[PLANE_MAX]; + uint64_t pid_mask; bool mc_based; - bool cntxt_cfg_except; + bool cntxt_cfg_except; }; /* diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c index 29c91a1f04..d7a25d16b7 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -572,13 +572,14 @@ int cam_vfe_camif_lite_ver2_deinit( camif_lite_node->res_priv; int i = 0; - if (camif_lite_priv) { - CAM_INFO(CAM_ISP, "camif_priv is not NULL"); - INIT_LIST_HEAD(&camif_lite_priv->free_payload_list); - for (i = 0; i < CAM_VFE_CAMIF_LITE_EVT_MAX; i++) - INIT_LIST_HEAD(&camif_lite_priv->evt_payload[i].list); - kfree(camif_lite_priv); - } + if (!camif_lite_priv) { + CAM_WARN(CAM_ISP, "Error! camif_priv is NULL"); + return -ENODEV; + } + + INIT_LIST_HEAD(&camif_lite_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_LITE_EVT_MAX; i++) + INIT_LIST_HEAD(&camif_lite_priv->evt_payload[i].list); camif_lite_node->start = NULL; camif_lite_node->stop = NULL; @@ -587,5 +588,7 @@ int cam_vfe_camif_lite_ver2_deinit( camif_lite_node->bottom_half_handler = NULL; camif_lite_node->res_priv = NULL; + kfree(camif_lite_priv); + return 0; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c index ab9622267b..885e102f90 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -991,7 +991,6 @@ int cam_vfe_camif_ver2_deinit( camif_node->res_priv = NULL; - kfree(camif_priv); return 0; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c index 21c98e7898..bdf035c543 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -609,7 +609,6 @@ int cam_vfe_rdi_ver2_deinit( rdi_node->res_priv = NULL; - kfree(rdi_priv); return 0; diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c index a572465987..a67bb4f2e6 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c @@ -64,6 +64,12 @@ static int cam_vfe_top_mux_get_base(struct cam_vfe_top_ver2_priv *top_priv, mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( top_priv->top_common.soc_info, VFE_CORE_BASE_IDX); + if (mem_base == -1) { + CAM_ERR(CAM_ISP, "failed to get mem_base, index: %d num_reg_map: %u", + VFE_CORE_BASE_IDX, top_priv->top_common.soc_info->num_reg_map); + return -EINVAL; + } + CAM_DBG(CAM_ISP, "core %d mem_base 0x%x", top_priv->top_common.soc_info->index, mem_base); @@ -288,7 +294,7 @@ static int cam_vfe_hw_dump( void *cmd_args, uint32_t arg_size) { - int size, i, j; + int i, j; uint8_t *dst; uint32_t reg_start_offset; uint32_t reg_dump_size = 0; @@ -331,17 +337,9 @@ static int cam_vfe_hw_dump( soc_info = top_priv->top_common.soc_info; /*Dump registers */ - for (i = 0; i < dump_data->num_reg_dump_entries; i++) { - size = (dump_data->reg_entry[i].reg_dump_end - + for (i = 0; i < dump_data->num_reg_dump_entries; i++) + reg_dump_size += (dump_data->reg_entry[i].reg_dump_end - dump_data->reg_entry[i].reg_dump_start); - if (size >= 0) { - reg_dump_size += size; - } else { - CAM_WARN(CAM_ISP, "Invalid size %d", size); - return -EINVAL; - } - } - /* * We dump the offset as well, so the total size dumped becomes * multiplied by 2 diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c index 8d9193826d..6666fed253 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c @@ -83,6 +83,11 @@ static int cam_vfe_top_ver3_mux_get_base(struct cam_vfe_top_ver3_priv *top_priv, mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( top_priv->top_common.soc_info, VFE_CORE_BASE_IDX); + if (mem_base == -1) { + CAM_ERR(CAM_ISP, "failed to get mem_base, index: %d num_reg_map: %u", + VFE_CORE_BASE_IDX, top_priv->top_common.soc_info->num_reg_map); + return -EINVAL; + } CAM_DBG(CAM_ISP, "core %d mem_base 0x%x", top_priv->top_common.soc_info->index, mem_base); diff --git a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c index f32480c337..6824c3c153 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c +++ b/qcom/opensource/camera-kernel/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c @@ -261,6 +261,12 @@ static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv, mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( top_priv->top_common.soc_info, VFE_CORE_BASE_IDX); + if (mem_base == -1) { + CAM_ERR(CAM_ISP, "failed to get mem_base, index: %d num_reg_map: %u", + VFE_CORE_BASE_IDX, top_priv->top_common.soc_info->num_reg_map); + return -EINVAL; + } + if (cdm_args->cdm_id == CAM_CDM_RT) { if (!soc_private->rt_wrapper_base) { CAM_ERR(CAM_ISP, "VFE:%u rt_wrapper_base_addr is null", @@ -1146,7 +1152,7 @@ static int cam_vfe_top_apply_fcg_update( } fcg_index_shift = fcg_module_info->fcg_index_shift; - + for (i = 0, j = 0; i < fcg_config->num_ch_ctx; i++) { if (j >= fcg_module_info->max_reg_val_pair_size) { CAM_ERR(CAM_ISP, "reg_val_pair %d exceeds the array limit %u", diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 1bc61c6e06..2592ce3629 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -106,10 +106,6 @@ static int cam_jpeg_add_command_buffers(struct cam_packet *packet, struct cam_cmd_buf_desc *cmd_desc = NULL; struct cam_jpeg_request_data *jpeg_request_data; struct cam_kmd_buf_info kmd_buf; - struct cam_jpeg_config_inout_param_info *inout_params; - uint32_t *cmd_buf_kaddr; - uintptr_t kaddr; - size_t len; unsigned int num_entry = 0; unsigned int i; int rc; @@ -157,9 +153,10 @@ static int cam_jpeg_add_command_buffers(struct cam_packet *packet, num_entry++; jpeg_request_data->dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; - jpeg_request_data->encode_size_buffer_ptr = NULL; jpeg_request_data->request_id = packet->header.request_id; jpeg_request_data->thumbnail_threshold_size = 0; + jpeg_request_data->out_size_mem_handle = 0; + jpeg_request_data->out_size_offset = 0; CAM_DBG(CAM_JPEG, "Change_Base HW_Entry. Offset: 0x%x Length: %u mem_handle: 0x%x num_entry: %d", @@ -193,29 +190,8 @@ static int cam_jpeg_add_command_buffers(struct cam_packet *packet, num_entry++; break; case CAM_JPEG_PACKET_INOUT_PARAM: - rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, - (uintptr_t *)&kaddr, &len); - if (rc) { - CAM_ERR(CAM_JPEG, "unable to get info for cmd buf: %x %d"); - return rc; - } - - cmd_buf_kaddr = (uint32_t *)kaddr; - - if ((cmd_desc[i].offset / sizeof(uint32_t)) >= len) { - CAM_ERR(CAM_JPEG, "Invalid offset: %u cmd buf len: %zu", - cmd_desc[i].offset, len); - cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); - return -EINVAL; - } - - cmd_buf_kaddr += (cmd_desc[i].offset / sizeof(uint32_t)); - - inout_params = (struct cam_jpeg_config_inout_param_info *)cmd_buf_kaddr; - jpeg_request_data->encode_size_buffer_ptr = &inout_params->output_size; - CAM_DBG(CAM_JPEG, "encode_size_buf_ptr: 0x%p", - jpeg_request_data->encode_size_buffer_ptr); - cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + jpeg_request_data->out_size_mem_handle = cmd_desc[i].mem_handle; + jpeg_request_data->out_size_offset = cmd_desc[i].offset; break; case CAM_JPEG_PACKET_GENERIC_BLOB: rc = cam_packet_util_process_generic_cmd_buffer(&cmd_desc[i], @@ -391,6 +367,11 @@ static int cam_jpeg_mgr_bottom_half_irq(void *priv, void *data) struct cam_ctx_request *req; struct cam_jpeg_misr_dump_args misr_args; struct cam_jpeg_hw_buf_done_evt_data jpeg_done_evt; + struct cam_jpeg_config_inout_param_info *inout_params; + uint32_t *cmd_buf_kaddr; + uintptr_t kaddr; + size_t len; + size_t inout_param_size; if (!data || !priv) { CAM_ERR(CAM_JPEG, "Invalid data"); @@ -467,10 +448,26 @@ static int cam_jpeg_mgr_bottom_half_irq(void *priv, void *data) } jpeg_req = irq_cb_data->jpeg_req; + inout_param_size = sizeof(struct cam_jpeg_config_inout_param_info); if (jpeg_req->dev_type == CAM_JPEG_RES_TYPE_ENC) { - if (jpeg_req->encode_size_buffer_ptr) - *jpeg_req->encode_size_buffer_ptr = task_data->u.output_encode_size; + rc = cam_mem_get_cpu_buf(jpeg_req->out_size_mem_handle, + (uintptr_t *)&kaddr, &len); + if (!rc) { + if ((inout_param_size > len) || + (jpeg_req->out_size_offset >= (len - inout_param_size))) + CAM_ERR(CAM_JPEG, + "Inval off = %u cmd buf len = %zu inout_param_size = %d", + jpeg_req->out_size_offset, len, inout_param_size); + else { + cmd_buf_kaddr = (uint32_t *)kaddr; + cmd_buf_kaddr += (jpeg_req->out_size_offset / sizeof(uint32_t)); + inout_params = + (struct cam_jpeg_config_inout_param_info *)cmd_buf_kaddr; + inout_params->output_size = task_data->u.output_encode_size; + } + cam_mem_put_cpu_buf(jpeg_req->out_size_mem_handle); + } else CAM_ERR(CAM_JPEG, "Buffer pointer for inout param is null"); @@ -817,7 +814,7 @@ static int cam_jpeg_mgr_process_hw_update_entries(void *priv, void *data) rc = hw_mgr->devices[dev_type][0]->hw_ops.init( hw_mgr->devices[dev_type][0]->hw_priv, ctx_data, - sizeof(struct cam_jpeg_hw_ctx_data)); + sizeof(ctx_data)); if (rc) { CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type); goto end; diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h index 7bb24728b3..c6168f62f5 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022,2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef CAM_JPEG_HW_MGR_INTF_H @@ -23,15 +23,16 @@ enum cam_jpeg_hw_type { * struct cam_jpeg_request_data - Jpeg request data received from command buffers * @dev_type : Jpeg device type(ENC vs DMA) * @request_id : Request ID - * @encode_size_buffer_ptr : Pointer to the buffer location for storing the encode - size of the result * @thumbnail_threshold_size : Threshold size for thumbnail image + * @out_size_mem_handle : handle to the buffer to share encoded output size with userspace + * @out_size_offset : offset to memory where out_size_mem_handle is stored */ struct cam_jpeg_request_data { uint32_t dev_type; uint64_t request_id; - uint32_t *encode_size_buffer_ptr; uint32_t thumbnail_threshold_size; + __s32 out_size_mem_handle; + uint32_t out_size_offset; }; typedef void (*cam_jpeg_mini_dump_cb)(void *priv, void *dst); diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_770_hw_info_ver_4_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_770_hw_info_ver_4_2_0.h new file mode 100644 index 0000000000..4025fd1cf2 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_770_hw_info_ver_4_2_0.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef CAM_JPEG_DMA_770_HW_INFO_VER_4_2_0_H +#define CAM_JPEG_DMA_770_HW_INFO_VER_4_2_0_H + +#define CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE (1 << 0) +#define CAM_JPEGDMA_HW_IRQ_STATUS_RD_BUF_DONE (1 << 1) +#define CAM_JPEGDMA_HW_IRQ_STATUS_WR_BUF_DONE (1 << 5) +#define CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT (1 << 9) +#define CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE (1 << 10) + +#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1 + +#define CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE \ + CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE +#define CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK \ + CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE + +static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_770_hw_info = { + .reg_offset = { + .hw_version = 0x0, + .int_clr = 0x14, + .int_status = 0x10, + .int_mask = 0x0C, + .hw_cmd = 0x1C, + .reset_cmd = 0x08, + .encode_size = 0x180, + .core_cfg = 0x18, + .misr_cfg0 = 0x160, + .misr_cfg1 = 0x164, + }, + .reg_val = { + .int_clr_clearall = 0xFFFFFFFF, + .int_mask_disable_all = 0x00000000, + .int_mask_enable_all = 0xFFFFFFFF, + .hw_cmd_start = 0x00000001, + .reset_cmd = 0x32083, + .hw_cmd_stop = 0x00000004, + .misr_cfg0 = 0x506, + }, + .int_status = { + .framedone = CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE, + .resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK, + .iserror = 0x0, + .stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT, + .scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE, + .scale_enable_shift = 0x4, + }, + .camnoc_misr_reg_offset = { + .main_ctl = 0x8108, + .id_mask_low = 0x8120, + .id_value_low = 0x8118, + .misc_ctl = 0x8110, + .sigdata0 = 0x8150, + }, + .camnoc_misr_reg_val = { + .main_ctl = 0x7, + .id_mask_low = 0xFC0, + .id_value_low_rd = 0xD00, + .id_value_low_wr = 0xD42, + .misc_ctl_start = 0x1, + .misc_ctl_stop = 0x2, + }, + .max_misr = 3, + .max_misr_rd = 4, + .max_misr_wr = 4, + .camnoc_misr_sigdata = 4, + .master_we_sel = 2, + .misr_rd_word_sel = 4, + .camnoc_misr_support = 1, +}; + +#endif /* CAM_JPEG_DMA_770_HW_INFO_VER_4_2_0_H */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c index 99b6a8eb2c..b4815f0d41 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -693,6 +693,7 @@ int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type, uint32_t *num_pid = NULL; struct cam_hw_soc_info *soc_info = NULL; int i, rc = 0; + unsigned long flags = 0; if (!device_priv) { CAM_ERR(CAM_JPEG, "Invalid arguments"); @@ -723,7 +724,7 @@ int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type, } irq_cb_data = &irq_cb->irq_cb_data; - spin_lock(&jpeg_dma_dev->hw_lock); + spin_lock_irqsave(&jpeg_dma_dev->hw_lock, flags); if (irq_cb->b_set_cb) { core_info->irq_cb.jpeg_hw_mgr_cb = irq_cb->jpeg_hw_mgr_cb; @@ -734,7 +735,7 @@ int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type, core_info->irq_cb.irq_cb_data.jpeg_req = NULL; core_info->irq_cb.irq_cb_data.private_data = NULL; } - spin_unlock(&jpeg_dma_dev->hw_lock); + spin_unlock_irqrestore(&jpeg_dma_dev->hw_lock, flags); rc = 0; break; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c index 38d9bed6a2..bb9438c8d1 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -24,6 +24,7 @@ #include "cam_jpeg_dma_580_hw_info_ver_4_2_0.h" #include "cam_jpeg_dma_680_hw_info_ver_4_2_0.h" #include "cam_jpeg_dma_780_hw_info_ver_4_2_0.h" +#include "cam_jpeg_dma_770_hw_info_ver_4_2_0.h" #include "camera_main.h" static int cam_jpeg_dma_register_cpas(struct cam_hw_soc_info *soc_info, @@ -260,6 +261,11 @@ static const struct of_device_id cam_jpeg_dma_dt_match[] = { .compatible = "qcom,cam_jpeg_dma_780", .data = &cam_jpeg_dma_780_hw_info, }, + { + .compatible = "qcom,cam_jpeg_dma_770", + .data = &cam_jpeg_dma_770_hw_info, + + }, {} }; MODULE_DEVICE_TABLE(of, cam_jpeg_dma_dt_match); diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_770_hw_info_ver_4_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_770_hw_info_ver_4_2_0.h new file mode 100644 index 0000000000..d47c860379 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_770_hw_info_ver_4_2_0.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef CAM_JPEG_ENC_770_HW_INFO_TITAN170_H +#define CAM_JPEG_ENC_770_HW_INFO_TITAN170_H + +#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001 +#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000 + +#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000 +#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a + +#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK 0x8000000 +#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_SHIFT 0x0000001b + +#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800 +#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b + +#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1 + +#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF (0x1<<19) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR (0x1<<20) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR (0x1<<21) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW (0x1<<23) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM (0x1<<24) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ (0x1<<25) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM (0x1<<26) +#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK (0x1<<29) + +#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \ + CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK +#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \ + CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK +#define CAM_JPEG_HW_MASK_COMP_ERR \ + (CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \ + CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK) + +static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_770_hw_info = { + .reg_offset = { + .hw_version = 0x0, + .int_clr = 0x1c, + .int_status = 0x20, + .int_mask = 0x18, + .hw_cmd = 0x10, + .reset_cmd = 0x8, + .encode_size = 0x180, + .core_cfg = 0xc, + .misr_cfg = 0x2B4, + .misr_rd0 = 0x2B8, + }, + .reg_val = { + .int_clr_clearall = 0xFFFFFFFF, + .int_mask_disable_all = 0x00000000, + .int_mask_enable_all = 0xFFFFFFFF, + .hw_cmd_start = 0x00000001, + .reset_cmd = 0x200320D3, + .hw_cmd_stop = 0x00000002, + .misr_cfg = 0x7, + }, + .int_status = { + .framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE, + .resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK, + .iserror = CAM_JPEG_HW_MASK_COMP_ERR, + .stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK, + .scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE, + .scale_enable_shift = 0x7, + }, + .reg_dump = { + .start_offset = 0x0, + .end_offset = 0x33C, + }, + .camnoc_misr_reg_offset = { + .main_ctl = 0x8108, + .id_mask_low = 0x8120, + .id_value_low = 0x8118, + .misc_ctl = 0x8110, + .sigdata0 = 0x8150, + }, + .camnoc_misr_reg_val = { + .main_ctl = 0x7, + .id_mask_low = 0xFC0, + .id_value_low_rd = 0xD80, + .id_value_low_wr = 0xDC2, + .misc_ctl_start = 0x1, + .misc_ctl_stop = 0x2, + }, + .max_misr = 3, + .max_misr_rd = 4, + .camnoc_misr_sigdata = 4, + .camnoc_misr_support = 1, +}; + +#endif /* CAM_JPEG_ENC_770_HW_INFO_TITAN170_H */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c index 369ca4dead..2b291d4c5e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -784,6 +784,7 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type, uint32_t *num_pid = NULL; struct cam_hw_soc_info *soc_info = NULL; int i, rc = 0; + unsigned long flags = 0; if (!device_priv) { CAM_ERR(CAM_JPEG, "Invalid arguments"); @@ -813,7 +814,7 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type, } irq_cb_data = &irq_cb->irq_cb_data; - spin_lock(&jpeg_enc_dev->hw_lock); + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); if (irq_cb->b_set_cb) { core_info->irq_cb.jpeg_hw_mgr_cb = irq_cb->jpeg_hw_mgr_cb; @@ -824,7 +825,7 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type, core_info->irq_cb.irq_cb_data.private_data = NULL; core_info->irq_cb.irq_cb_data.jpeg_req = NULL; } - spin_unlock(&jpeg_enc_dev->hw_lock); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); rc = 0; break; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c index a238253315..93830658f0 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -24,6 +24,7 @@ #include "cam_jpeg_enc_580_hw_info_ver_4_2_0.h" #include "cam_jpeg_enc_680_hw_info_ver_4_2_0.h" #include "cam_jpeg_enc_780_hw_info_ver_4_2_0.h" +#include "cam_jpeg_enc_770_hw_info_ver_4_2_0.h" #include "camera_main.h" static int cam_jpeg_enc_register_cpas(struct cam_hw_soc_info *soc_info, @@ -261,6 +262,10 @@ static const struct of_device_id cam_jpeg_enc_dt_match[] = { .compatible = "qcom,cam_jpeg_enc_780", .data = &cam_jpeg_enc_780_hw_info, }, + { + .compatible = "qcom,cam_jpeg_enc_770", + .data = &cam_jpeg_enc_770_hw_info, + }, {} }; MODULE_DEVICE_TABLE(of, cam_jpeg_enc_dt_match); diff --git a/qcom/opensource/camera-kernel/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c b/qcom/opensource/camera-kernel/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c index 3147119908..5230c51406 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -408,6 +408,11 @@ static int cam_lrme_hw_util_process_config_hw(struct cam_hw_info *lrme_hw, } mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(soc_info, CAM_LRME_BASE_IDX); + if (mem_base == -1) { + CAM_ERR(CAM_LRME, "failed to get mem_base, index: %d num_reg_map: %u", + CAM_LRME_BASE_IDX, soc_info->num_reg_map); + return -EINVAL; + } hw_cdm_info->cdm_ops->cdm_write_changebase(cmd_buf_addr, mem_base); cmd_buf_addr += size; diff --git a/qcom/opensource/camera-kernel/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 7c5af792e1..412154536a 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2212,6 +2212,14 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, hw_mgr->iommu_hdl); goto end; } + if ((len <= frame_process->cmd_buf[i][j].offset) || + (frame_process->cmd_buf[i][j].size < + frame_process->cmd_buf[i][j].length) || + ((len - frame_process->cmd_buf[i][j].offset) < + frame_process->cmd_buf[i][j].length)) { + CAM_ERR(CAM_OPE, "Invalid offset."); + return -EINVAL; + } cpu_addr = cpu_addr + frame_process->cmd_buf[i][j].offset; CAM_DBG(CAM_OPE, "Hdl %x size %d len %d off %d", @@ -2260,6 +2268,10 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, uint32_t s_idx = 0; s_idx = cmd_buf->stripe_idx; + if (s_idx < 0 || s_idx >= OPE_MAX_STRIPES) { + CAM_ERR(CAM_OPE, "Invalid index."); + return -EINVAL; + } num_cmd_bufs = ope_request->num_stripe_cmd_bufs[i][s_idx]; diff --git a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.c index e9dbe0e06f..f46cfca473 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -100,10 +100,11 @@ static void cam_mem_mgr_print_tbl(void) for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) { CAM_CONVERT_TIMESTAMP_FORMAT((tbl.bufq[i].timestamp), hrs, min, sec, ms); CAM_INFO(CAM_MEM, - "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu active %d buf_handle %d refCount %d bu f_name %s", + "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu active %d buf_handle %d krefCount %d urefCount %d buf_name %s", hrs, min, sec, ms, i, tbl.bufq[i].fd, tbl.bufq[i].i_ino, tbl.bufq[i].len, tbl.bufq[i].active, tbl.bufq[i].buf_handle, - kref_read(&tbl.bufq[i].krefcount), tbl.bufq[i].buf_name); + kref_read(&tbl.bufq[i].krefcount), kref_read(&tbl.bufq[i].urefcount), + tbl.bufq[i].buf_name); } } @@ -315,7 +316,7 @@ clean_bitmap_and_mutex: kfree(tbl.bitmap); tbl.bitmap = NULL; mutex_destroy(&tbl.m_lock); - + atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED); put_heaps: #if IS_REACHABLE(CONFIG_DMABUF_HEAPS) cam_mem_mgr_put_dma_heaps(); @@ -352,6 +353,8 @@ static void cam_mem_put_slot(int32_t idx) tbl.bufq[idx].release_deferred = false; tbl.bufq[idx].is_internal = false; memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64)); + kref_init(&tbl.bufq[idx].krefcount); + kref_init(&tbl.bufq[idx].urefcount); mutex_unlock(&tbl.bufq[idx].q_lock); mutex_destroy(&tbl.bufq[idx].q_lock); clear_bit(idx, tbl.bitmap); @@ -500,7 +503,6 @@ EXPORT_SYMBOL(cam_mem_get_io_buf); int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) { int idx; - int ret = 0; if (!atomic_read(&cam_mem_mgr_state)) { CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); @@ -515,27 +517,22 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) return -EINVAL; - mutex_lock(&tbl.bufq[idx].q_lock); - if (!tbl.bufq[idx].active) { CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,", idx); - ret = -EPERM; - goto end; + return -EPERM; } if (buf_handle != tbl.bufq[idx].buf_handle) { CAM_ERR(CAM_MEM, "idx: %d Invalid buf handle %d", idx, buf_handle); - ret = -EINVAL; - goto end; + return -EINVAL; } if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) { CAM_ERR(CAM_MEM, "idx: %d Invalid flag 0x%x", idx, tbl.bufq[idx].flags); - ret = -EINVAL; - goto end; + return -EINVAL; } if (tbl.bufq[idx].kmdvaddr && kref_get_unless_zero(&tbl.bufq[idx].krefcount)) { @@ -544,13 +541,10 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) } else { CAM_ERR(CAM_MEM, "No KMD access requested, kmdvddr= %p, idx= %d, buf_handle= %d", tbl.bufq[idx].kmdvaddr, idx, buf_handle); - ret = -EINVAL; - goto end; + return -EINVAL; } -end: - mutex_unlock(&tbl.bufq[idx].q_lock); - return ret; + return 0; } EXPORT_SYMBOL(cam_mem_get_cpu_buf); @@ -945,15 +939,8 @@ static int cam_mem_util_get_dma_buf(size_t len, * */ if (!(cam_flags & CAM_MEM_FLAG_USE_SYS_HEAP_ONLY)) - { try_heap = tbl.camera_heap; - if (tbl.system_movable_heap && (alloc_type == CAM_MEMMGR_ALLOC_USER)) - heap = tbl.system_movable_heap; - else - heap = tbl.system_heap; - } - if (!(cam_flags & CAM_MEM_FLAG_USE_CAMERA_HEAP_ONLY)) { if (tbl.system_movable_heap && (alloc_type == CAM_MEMMGR_ALLOC_USER)) heap = tbl.system_movable_heap; @@ -982,7 +969,7 @@ static int cam_mem_util_get_dma_buf(size_t len, if (try_heap) { *buf = dma_heap_buffer_alloc(try_heap, len, O_RDWR, 0); if (IS_ERR(*buf)) { - CAM_DBG(CAM_MEM, + CAM_WARN(CAM_MEM, "Failed in allocating from try heap, heap=%pK, len=%zu, err=%d", try_heap, len, PTR_ERR(*buf)); *buf = NULL; @@ -990,8 +977,7 @@ static int cam_mem_util_get_dma_buf(size_t len, } if (*buf == NULL) { - if (heap) - *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0); + *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0); if (IS_ERR(*buf)) { rc = PTR_ERR(*buf); CAM_ERR(CAM_MEM, @@ -1363,7 +1349,7 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd_v2 *cmd) } if (cam_dma_buf_set_name(dmabuf, cmd->buf_name)) - CAM_DBG(CAM_MEM, "set dma buffer name(%s) failed", cmd->buf_name); + CAM_ERR(CAM_MEM, "set dma buffer name(%s) failed", cmd->buf_name); if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) || (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) || @@ -1433,9 +1419,14 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd_v2 *cmd) tbl.bufq[idx].num_hdls = cmd->num_hdl; cam_mem_mgr_reset_presil_params(idx); tbl.bufq[idx].is_imported = false; - kref_init(&tbl.bufq[idx].krefcount); + + if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) + kref_init(&tbl.bufq[idx].krefcount); + + kref_init(&tbl.bufq[idx].urefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; - strlcpy(tbl.bufq[idx].buf_name, cmd->buf_name, sizeof(tbl.bufq[idx].buf_name)); + strscpy(tbl.bufq[idx].buf_name, cmd->buf_name, sizeof(tbl.bufq[idx].buf_name)); mutex_unlock(&tbl.bufq[idx].q_lock); cmd->out.buf_handle = tbl.bufq[idx].buf_handle; @@ -1568,9 +1559,11 @@ int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd_v2 *cmd) tbl.bufq[idx].num_hdls = cmd->num_hdl; tbl.bufq[idx].is_imported = true; tbl.bufq[idx].is_internal = is_internal; - kref_init(&tbl.bufq[idx].krefcount); + if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) + kref_init(&tbl.bufq[idx].krefcount); + kref_init(&tbl.bufq[idx].urefcount); tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; - strlcpy(tbl.bufq[idx].buf_name, cmd->buf_name, sizeof(tbl.bufq[idx].buf_name)); + strscpy(tbl.bufq[idx].buf_name, cmd->buf_name, sizeof(tbl.bufq[idx].buf_name)); mutex_unlock(&tbl.bufq[idx].q_lock); cmd->out.buf_handle = tbl.bufq[idx].buf_handle; @@ -1713,6 +1706,8 @@ static int cam_mem_mgr_cleanup_table(void) tbl.bufq[i].is_internal = false; memset(tbl.bufq[i].hdls_info, 0x0, tbl.max_hdls_info_size); cam_mem_mgr_reset_presil_params(i); + kref_init(&tbl.bufq[i].krefcount); + kref_init(&tbl.bufq[i].urefcount); mutex_unlock(&tbl.bufq[i].q_lock); mutex_destroy(&tbl.bufq[i].q_lock); } @@ -1751,16 +1746,17 @@ void cam_mem_mgr_deinit(void) mutex_destroy(&tbl.m_lock); } -static void cam_mem_util_unmap(struct kref *kref) +static void cam_mem_util_unmap_dummy(struct kref *kref) +{ + CAM_DBG(CAM_MEM, "Cam mem util unmap dummy"); +} + +static void cam_mem_util_unmap(int32_t idx) { int rc = 0; - int32_t idx; enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; enum cam_smmu_mapping_client client; - struct cam_mem_buf_queue *bufq = - container_of(kref, typeof(*bufq), krefcount); - idx = CAM_MEM_MGR_GET_HDL_IDX(bufq->buf_handle); if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { CAM_ERR(CAM_MEM, "Incorrect index"); return; @@ -1836,6 +1832,8 @@ static void cam_mem_util_unmap(struct kref *kref) memset(tbl.bufq[idx].hdls_info, 0x0, tbl.max_hdls_info_size); cam_mem_mgr_reset_presil_params(idx); memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64)); + memset(&tbl.bufq[idx].krefcount, 0, sizeof(struct kref)); + memset(&tbl.bufq[idx].urefcount, 0, sizeof(struct kref)); mutex_unlock(&tbl.bufq[idx].q_lock); mutex_destroy(&tbl.bufq[idx].q_lock); clear_bit(idx, tbl.bitmap); @@ -1843,11 +1841,27 @@ static void cam_mem_util_unmap(struct kref *kref) } +static void cam_mem_util_unmap_wrapper(struct kref *kref) +{ + int32_t idx; + struct cam_mem_buf_queue *bufq = container_of(kref, typeof(*bufq), krefcount); + + idx = CAM_MEM_MGR_GET_HDL_IDX(bufq->buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "idx: %d not valid", idx); + return; + } + + cam_mem_util_unmap(idx); +} + void cam_mem_put_cpu_buf(int32_t buf_handle) { int idx; uint64_t ms, hrs, min, sec; struct timespec64 current_ts; + uint32_t krefcount = 0, urefcount = 0; + bool unmap = false; if (!buf_handle) { CAM_ERR(CAM_MEM, "Invalid buf_handle"); @@ -1871,26 +1885,38 @@ void cam_mem_put_cpu_buf(int32_t buf_handle) return; } - if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) { + kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap_dummy); + + krefcount = kref_read(&tbl.bufq[idx].krefcount); + urefcount = kref_read(&tbl.bufq[idx].urefcount); + + if ((krefcount == 1) && (urefcount == 0)) + unmap = true; + + if (unmap) { + cam_mem_util_unmap(idx); CAM_GET_TIMESTAMP(current_ts); CAM_CONVERT_TIMESTAMP_FORMAT(current_ts, hrs, min, sec, ms); - CAM_INFO(CAM_MEM, + CAM_DBG(CAM_MEM, "%llu:%llu:%llu:%llu Called unmap from here, buf_handle: %u, idx: %d", hrs, min, sec, ms, buf_handle, idx); } else if (tbl.bufq[idx].release_deferred) { CAM_CONVERT_TIMESTAMP_FORMAT((tbl.bufq[idx].timestamp), hrs, min, sec, ms); CAM_ERR(CAM_MEM, - "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu active %d buf_handle %d refCount %d buf_name %s", + "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu active %d buf_handle %d krefCount %d urefCount %d buf_name %s", hrs, min, sec, ms, idx, tbl.bufq[idx].fd, tbl.bufq[idx].i_ino, tbl.bufq[idx].len, tbl.bufq[idx].active, tbl.bufq[idx].buf_handle, - kref_read(&tbl.bufq[idx].krefcount), tbl.bufq[idx].buf_name); + krefcount, urefcount, tbl.bufq[idx].buf_name); CAM_GET_TIMESTAMP(current_ts); CAM_CONVERT_TIMESTAMP_FORMAT(current_ts, hrs, min, sec, ms); CAM_ERR(CAM_MEM, "%llu:%llu:%llu:%llu Not unmapping even after defer, buf_handle: %u, idx: %d", hrs, min, sec, ms, buf_handle, idx); + } else if (krefcount == 0) { + CAM_ERR(CAM_MEM, + "Unbalanced release Called buf_handle: %u, idx: %d", + tbl.bufq[idx].buf_handle, idx); } - } EXPORT_SYMBOL(cam_mem_put_cpu_buf); @@ -1901,6 +1927,8 @@ int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) int rc = 0; uint64_t ms, hrs, min, sec; struct timespec64 current_ts; + uint32_t krefcount = 0, urefcount = 0; + bool unmap = false; if (!atomic_read(&cam_mem_mgr_state)) { CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); @@ -1932,26 +1960,40 @@ int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) } CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx); - if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) { - CAM_DBG(CAM_MEM, - "Called unmap from here, buf_handle: %u, idx: %d", - cmd->buf_handle, idx); + + kref_put(&tbl.bufq[idx].urefcount, cam_mem_util_unmap_dummy); + + urefcount = kref_read(&tbl.bufq[idx].urefcount); + + if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) { + krefcount = kref_read(&tbl.bufq[idx].krefcount); + if ((krefcount == 1) && (urefcount == 0)) + unmap = true; } else { + if (urefcount == 0) + unmap = true; + } + + if (unmap) { + cam_mem_util_unmap(idx); + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", cmd->buf_handle, idx); + } else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) { rc = -EINVAL; CAM_GET_TIMESTAMP(current_ts); CAM_CONVERT_TIMESTAMP_FORMAT(current_ts, hrs, min, sec, ms); - CAM_ERR(CAM_MEM, - "%llu:%llu:%llu:%llu Unbalanced release Called buf_handle: %u, idx: %d", - hrs, min, sec, ms, cmd->buf_handle, idx); CAM_CONVERT_TIMESTAMP_FORMAT((tbl.bufq[idx].timestamp), hrs, min, sec, ms); CAM_ERR(CAM_MEM, - "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu active %d buf_handle %d refCount %d buf_name %s", + "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu active %d buf_handle %d krefCount %d urefCount %d buf_name %s", hrs, min, sec, ms, idx, tbl.bufq[idx].fd, tbl.bufq[idx].i_ino, tbl.bufq[idx].len, tbl.bufq[idx].active, tbl.bufq[idx].buf_handle, - kref_read(&tbl.bufq[idx].krefcount), tbl.bufq[idx].buf_name); + krefcount, urefcount, tbl.bufq[idx].buf_name); + if (tbl.bufq[idx].release_deferred) + CAM_ERR(CAM_MEM, "Unbalanced release Called buf_handle: %u, idx: %d", + tbl.bufq[idx].buf_handle, idx); tbl.bufq[idx].release_deferred = true; - } + return rc; } @@ -2121,7 +2163,7 @@ int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) } CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); - if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap_wrapper)) CAM_DBG(CAM_MEM, "Called unmap from here, buf_handle: %u, idx: %d", tbl.bufq[idx].buf_handle, idx); @@ -2415,7 +2457,7 @@ int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp) } CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); - if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap_wrapper)) CAM_DBG(CAM_MEM, "Called unmap from here, buf_handle: %u, idx: %d", inp->mem_handle, idx); diff --git a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.h b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.h index a29c941c4e..d0ecd53122 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.h +++ b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_mem_mgr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_MEM_MGR_H_ @@ -82,10 +82,12 @@ struct cam_mem_buf_hw_hdl_info { * @is_internal: Flag indicating kernel allocated buffer * @timestamp: Timestamp at which this entry in tbl was made * @krefcount: Reference counter to track whether the buffer is - * mapped and in use + * mapped and in use by kmd * @smmu_mapping_client: Client buffer (User or kernel) * @buf_name: Name associated with buffer. * @presil_params: Parameters specific to presil environment + * @urefcount: Reference counter to track whether the buffer is + * mapped and in use by umd */ struct cam_mem_buf_queue { struct dma_buf *dma_buf; @@ -111,6 +113,7 @@ struct cam_mem_buf_queue { #ifdef CONFIG_CAM_PRESIL struct cam_presil_dmabuf_params presil_params; #endif + struct kref urefcount; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.c b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.c index 3182f0ef89..bdd915b9d8 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -96,6 +96,8 @@ void cam_req_mgr_core_link_reset(struct cam_req_mgr_core_link *link) link->is_sending_req = false; atomic_set(&link->eof_event_cnt, 0); link->cont_empty_slots = 0; + link->is_shdr = false; + link->wait_for_dual_trigger = false; __cam_req_mgr_reset_apply_data(link); __cam_req_mgr_reset_state_monitor_array(link); @@ -317,7 +319,7 @@ static void __cam_req_mgr_find_dev_name( if (masked_val & BIT(dev->dev_bit)) continue; if (link->wq_congestion) - CAM_INFO(CAM_CRM, + CAM_INFO_RATE_LIMIT(CAM_CRM, "WQ congestion, Skip Frame: req: %lld not ready on link: 0x%x for pd: %d dev: %s open_req count: %u", req_id, link->link_hdl, pd, dev->dev_info.name, link->open_req_cnt); @@ -1012,8 +1014,6 @@ static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link, slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; slot->status = CRM_SLOT_STATUS_NO_REQ; slot->num_sync_links = 0; - slot->ts = 0; - slot->apply_ts = 0; for (i = 0; i < MAXIMUM_LINKS_PER_SESSION - 1; i++) slot->sync_link_hdls[i] = 0; @@ -1219,6 +1219,30 @@ static int __cam_req_mgr_move_to_next_req_slot( return rc; } +static void cam_req_mgr_reconfigure_link(struct cam_req_mgr_core_link *link, + struct cam_req_mgr_connected_device *device, bool is_active) +{ + int i = 0; + struct cam_req_mgr_connected_device *dev = NULL; + struct cam_req_mgr_req_tbl *tbl = NULL; + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + + if (dev->dev_info.trigger_on && !dev->dev_info.is_shdr_master) { + dev->is_active = is_active; + tbl = dev->pd_tbl; + if (is_active) { + tbl->dev_mask |= (1 << dev->dev_bit); + } else { + tbl->dev_mask &= ~(1 << dev->dev_bit); + dev->dev_info.mode_switch_req = 0; + } + } + + } +} + /** * __cam_req_mgr_send_req() * @@ -1243,6 +1267,7 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, struct cam_req_mgr_tbl_slot *slot = NULL; struct cam_req_mgr_apply *apply_data = NULL; struct cam_req_mgr_state_monitor state; + bool prev_dual_trigger_status = false; apply_req.link_hdl = link->link_hdl; apply_req.report_if_bubble = 0; @@ -1289,6 +1314,12 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, continue; } + if (!dev->is_active) { + CAM_DBG(CAM_CRM, "Device %x linked with link %x is not active", + dev->dev_hdl, link->link_hdl); + continue; + } + for (j = 0; j < slot->ops.num_dev; j++) { if (dev->dev_hdl == slot->ops.dev_hdl[j]) { found = true; @@ -1393,6 +1424,16 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, if (!(dev->dev_info.trigger & trigger)) continue; + idx = apply_data[pd].idx; + slot = &dev->pd_tbl->slot[idx]; + + if (dev->dev_info.trigger_on && !dev->dev_info.is_shdr_master && + slot->ops.skip_isp_apply) { + CAM_DBG(CAM_CRM, "Skip slave switch req %d apply %lld", + dev->dev_info.mode_switch_req, apply_data[pd].req_id); + continue; + } + if (apply_data[pd].skip_idx || (apply_data[pd].req_id < 0)) { CAM_DBG(CAM_CRM, @@ -1417,8 +1458,6 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, apply_req.dev_hdl = dev->dev_hdl; apply_req.request_id = apply_data[pd].req_id; - idx = apply_data[pd].idx; - slot = &dev->pd_tbl->slot[idx]; apply_req.report_if_bubble = in_q->slot[idx].recover; @@ -1458,6 +1497,7 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, continue; apply_req.trigger_point = trigger; + apply_req.dual_trigger_status = CAM_REQ_DUAL_TRIGGER_NONE; CAM_DBG(CAM_REQ, "SEND: link_hdl %x dev %s pd %d req_id %lld", link->link_hdl, dev->dev_info.name, @@ -1477,6 +1517,20 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, state.frame_id = -1; __cam_req_mgr_update_state_monitor_array(link, &state); + if (link->is_shdr && dev->dev_info.is_shdr_master) { + prev_dual_trigger_status = link->wait_for_dual_trigger; + if (apply_req.dual_trigger_status == + CAM_REQ_DUAL_TRIGGER_TWO_EXPOSURE) + link->wait_for_dual_trigger = true; + else if (apply_req.dual_trigger_status == + CAM_REQ_DUAL_TRIGGER_ONE_EXPOSURE) + link->wait_for_dual_trigger = false; + + if (prev_dual_trigger_status != link->wait_for_dual_trigger) + cam_req_mgr_reconfigure_link( + link, dev, link->wait_for_dual_trigger); + } + if (pd == link->min_delay) req_applied_to_min_pd = apply_req.request_id; @@ -2418,7 +2472,8 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, tbl_slot = &dev->pd_tbl->slot[idx]; if ((apply_data[pd].req_id != -1) && - (tbl_slot->req_apply_map != dev->pd_tbl->dev_mask)) { + !(tbl_slot->req_apply_map & BIT(dev->dev_bit)) && + (dev->is_active)) { is_applied = false; break; } @@ -2426,7 +2481,6 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, if (is_applied) { slot->status = CRM_SLOT_STATUS_REQ_APPLIED; - slot->apply_ts = ktime_get(); CAM_DBG(CAM_CRM, "req %d is applied on link %x success", slot->req_id, @@ -2630,13 +2684,8 @@ static int __cam_req_mgr_process_sof_freeze(void *priv, void *data) struct cam_req_mgr_req_queue *in_q = NULL; struct cam_req_mgr_core_session *session = NULL; struct cam_req_mgr_message msg = {0}; - struct cam_req_mgr_slot *slot; - int rc = 0, i, diff; - uint32_t wr_idx, iterator; + int rc = 0; int64_t last_applied_req_id = -EINVAL; - struct cam_req_mgr_apply *apply_data; - struct timespec64 apply_time; - struct timespec64 sched_time; if (!data || !priv) { CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); @@ -2651,18 +2700,14 @@ static int __cam_req_mgr_process_sof_freeze(void *priv, void *data) } in_q = link->req.in_q; - if (link->state == CAM_CRM_LINK_STATE_AVAILABLE || !in_q) { - CAM_WARN(CAM_CRM, "Link %x not available state %d in_q %x", - link->link_hdl, link->state, in_q); - return -EINVAL; + if (in_q) { + mutex_lock(&link->req.lock); + if (in_q->last_applied_idx >= 0) + last_applied_req_id = + in_q->slot[in_q->last_applied_idx].req_id; + mutex_unlock(&link->req.lock); } - mutex_lock(&link->req.lock); - if (in_q->last_applied_idx >= 0) - last_applied_req_id = - in_q->slot[in_q->last_applied_idx].req_id; - mutex_unlock(&link->req.lock); - spin_lock_bh(&link->link_state_spin_lock); if ((link->watchdog) && (link->watchdog->pause_timer)) { CAM_INFO(CAM_CRM, @@ -2673,28 +2718,10 @@ static int __cam_req_mgr_process_sof_freeze(void *priv, void *data) } spin_unlock_bh(&link->link_state_spin_lock); - wr_idx = in_q->wr_idx; - if (in_q->wr_idx > in_q->rd_idx) - diff = in_q->wr_idx - in_q->rd_idx; - else - diff = in_q->rd_idx - in_q->wr_idx; - - iterator = in_q->rd_idx; - apply_data = link->req.apply_data; - for (i = 0; i < diff; i++) { - slot = &in_q->slot[iterator]; - sched_time = ktime_to_timespec64(slot->ts); - apply_time = ktime_to_timespec64(slot->apply_ts); - CAM_INFO(CAM_CRM, "Open req for %llu sched_ts[%lld:%06ld] apply_ts[%lld:%06ld]", - slot->req_id, sched_time.tv_sec, sched_time.tv_nsec / NSEC_PER_USEC, - apply_time.tv_sec, apply_time.tv_nsec / NSEC_PER_USEC); - __cam_req_mgr_inc_idx(&iterator, 1, in_q->num_slots); - } - CAM_ERR(CAM_CRM, - "SOF freeze for session: %d link: 0x%x max_pd: %d last_req_id:%d apply[%lld][%lld][%lld]", + "SOF freeze for session: %d link: 0x%x max_pd: %d last_req_id:%d", session->session_hdl, link->link_hdl, link->max_delay, - last_applied_req_id, apply_data[2].req_id, apply_data[1].req_id, apply_data[0].req_id); + last_applied_req_id); __cam_req_mgr_send_evt(0, CAM_REQ_MGR_LINK_EVT_SOF_FREEZE, CRM_KMD_ERR_FATAL, link); @@ -3110,10 +3137,8 @@ static int __cam_req_mgr_try_cancel_req(struct cam_req_mgr_core_link *link, return -EINVAL; } - CAM_INFO(CAM_CRM, - "canceling request %lld [last_applied %lld] on link 0x%x for devices with pd less than %d", - flush_info->req_id, link->req.prev_apply_data[link->max_delay].req_id, - flush_info->link_hdl, pd); + CAM_DBG(CAM_CRM, "cancelling request %lld on link 0x%x for devices with pd less than %d", + flush_info->req_id, flush_info->link_hdl, pd); __cam_req_mgr_flush_dev_with_max_pd(link, flush_info, pd); link->open_req_cnt--; return 0; @@ -3155,9 +3180,8 @@ int cam_req_mgr_process_flush_req(void *priv, void *data) switch (flush_info->flush_type) { case CAM_REQ_MGR_FLUSH_TYPE_ALL: link->last_flush_id = flush_info->req_id; - CAM_INFO(CAM_CRM, "Last request id to flush is %lld on link 0x%x last_applied %lld", - flush_info->req_id, link->link_hdl, - link->req.prev_apply_data[link->max_delay].req_id); + CAM_INFO(CAM_CRM, "Last request id to flush is %lld on link 0x%x", + flush_info->req_id, link->link_hdl); __cam_req_mgr_flush_req_slot(link); __cam_req_mgr_reset_apply_data(link); __cam_req_mgr_flush_dev_with_max_pd(link, flush_info, link->max_delay); @@ -3232,7 +3256,6 @@ int cam_req_mgr_process_sched_req(void *priv, void *data) slot->sync_mode = sched_req->sync_mode; slot->skip_idx = 0; slot->recover = sched_req->bubble_enable; - slot->ts = ktime_get(); if (sched_req->additional_timeout < 0) { CAM_WARN(CAM_CRM, @@ -3393,6 +3416,7 @@ int cam_req_mgr_process_add_req(void *priv, void *data) struct cam_req_mgr_add_request *add_req = NULL; struct cam_req_mgr_core_link *link = NULL; struct cam_req_mgr_connected_device *device = NULL; + struct cam_req_mgr_connected_device *dev_l = NULL; struct cam_req_mgr_req_tbl *tbl = NULL; struct cam_req_mgr_tbl_slot *slot = NULL; struct crm_task_payload *task_data = NULL; @@ -3445,6 +3469,7 @@ int cam_req_mgr_process_add_req(void *priv, void *data) link_slot = &link->req.in_q->slot[idx]; slot = &tbl->slot[idx]; + slot->ops.skip_isp_apply = false; if ((add_req->skip_at_sof & 0xFF) > slot->inject_delay_at_sof) { slot->inject_delay_at_sof = (add_req->skip_at_sof & 0xFF); @@ -3549,9 +3574,9 @@ int cam_req_mgr_process_add_req(void *priv, void *data) slot->state = CRM_REQ_STATE_PENDING; slot->req_ready_map |= BIT(device->dev_bit); - CAM_DBG(CAM_CRM, "idx %d dev_hdl %x req_id %lld pd %d ready_map %x", + CAM_DBG(CAM_CRM, "idx %d dev_hdl %x req_id %lld pd %d ready_map %x tbl mask %x", idx, add_req->dev_hdl, add_req->req_id, tbl->pd, - slot->req_ready_map); + slot->req_ready_map, tbl->dev_mask); trace_cam_req_mgr_add_req(link, idx, add_req, tbl, device); @@ -3567,8 +3592,43 @@ int cam_req_mgr_process_add_req(void *priv, void *data) state.frame_id = -1; __cam_req_mgr_update_state_monitor_array(link, &state); } - mutex_unlock(&link->req.lock); + if (!link->is_shdr && !device->dev_info.trigger_on) { + mutex_unlock(&link->req.lock); + return rc; + } + + if (device->dev_info.trigger_on && + add_req->num_exp == CAM_REQ_DUAL_TRIGGER_ONE_EXPOSURE) { + for (i = 0; i < link->num_devs; i++) { + dev_l = &link->l_dev[i]; + if (dev_l->dev_info.trigger_on && dev_l->dev_hdl != add_req->dev_hdl) { + slot->ops.skip_isp_apply = true; + slot->req_ready_map |= (1 << dev_l->dev_bit); + if (slot->req_ready_map == tbl->dev_mask) { + slot->state = CRM_REQ_STATE_READY; + CAM_DBG(CAM_REQ, + "SHDR link %x idx %d req_id %lld pd %d SLOT READY", + link->link_hdl, idx, add_req->req_id, tbl->pd); + } + break; + } + } + } + + if (device->dev_info.trigger_on && + add_req->num_exp == CAM_REQ_DUAL_TRIGGER_TWO_EXPOSURE && + !device->dev_info.is_shdr_master) { + tbl->dev_mask |= (1 << device->dev_bit); + if (slot->req_ready_map == tbl->dev_mask) { + slot->state = CRM_REQ_STATE_READY; + CAM_DBG(CAM_REQ, + "SHDR link 0x%x idx %d req_id %lld pd %d SLOT READY", + link->link_hdl, idx, add_req->req_id, tbl->pd); + } + } + + mutex_unlock(&link->req.lock); end: return rc; } @@ -3656,7 +3716,7 @@ int cam_req_mgr_process_error(void *priv, void *data) "req_id %lld not found in input queue", err_info->req_id); } else { - CAM_INFO(CAM_CRM, "req_id %lld found at idx %d last_applied %d", + CAM_DBG(CAM_CRM, "req_id %lld found at idx %d last_applied %d", err_info->req_id, idx, in_q->last_applied_idx); slot = &in_q->slot[idx]; if (!slot->recover) { @@ -4039,6 +4099,8 @@ static int cam_req_mgr_cb_add_req(struct cam_req_mgr_add_request *add_req) dev_req->trigger_eof = add_req->trigger_eof; dev_req->skip_at_sof = add_req->skip_at_sof; dev_req->skip_at_eof = add_req->skip_at_eof; + dev_req->num_exp = add_req->num_exp; + if (dev_req->trigger_eof) { atomic_inc(&link->eof_event_cnt); CAM_DBG(CAM_REQ, "Req_id: %llu, eof_event_cnt: %d", @@ -4282,8 +4344,6 @@ end: return rc; } - - /** * cam_req_mgr_cb_notify_trigger() * @@ -4313,7 +4373,7 @@ static int cam_req_mgr_cb_notify_trigger( link = cam_get_link_priv(trigger_data->link_hdl); if (!link) { - CAM_DBG(CAM_CRM, "link ptr NULL %x", trigger_data->link_hdl); + CAM_WARN_RATE_LIMIT(CAM_CRM, "link ptr NULL %x", trigger_data->link_hdl); rc = -EINVAL; goto end; } @@ -4366,7 +4426,7 @@ static int cam_req_mgr_cb_notify_trigger( (trigger == CAM_TRIGGER_POINT_SOF)) link->watchdog->pause_timer = false; - if (link->dual_trigger) { + if (link->dual_trigger && link->wait_for_dual_trigger) { if ((trigger_id >= 0) && (trigger_id < CAM_REQ_MGR_MAX_TRIGGERS)) { link->trigger_cnt[trigger_id][trigger]++; @@ -4445,6 +4505,7 @@ static int __cam_req_mgr_setup_link_info(struct cam_req_mgr_core_link *link, enum cam_pipeline_delay max_delay; enum cam_modeswitch_delay max_modeswitch; uint32_t num_trigger_devices = 0; + if (link_info->version == VERSION_1) { if (link_info->u.link_info_v1.num_devices > CAM_REQ_MGR_MAX_HANDLES) @@ -4545,6 +4606,8 @@ static int __cam_req_mgr_setup_link_info(struct cam_req_mgr_core_link *link, if (dev->dev_info.trigger_on) num_trigger_devices++; + + dev->is_active = true; } if (num_trigger_devices > CAM_REQ_MGR_MAX_TRIGGERS) { @@ -5205,7 +5268,7 @@ int cam_req_mgr_schedule_request_v2( } if (sched_req->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) { - if ((sched_req->num_links <= 0) && + if ((sched_req->num_links <= 0) || (sched_req->num_links > MAXIMUM_LINKS_PER_SESSION)) { CAM_ERR(CAM_CRM, "link:0x%x req:%lld invalid num_links:%d", link->link_hdl, sched_req->req_id, sched_req->num_links); @@ -5436,6 +5499,45 @@ end: return rc; } +int cam_req_mgr_rearrange_devs( + struct cam_req_mgr_core_link *link) +{ + int i, rc = 0; + uint32_t master_dev_idx = 0, slave_dev_idx = 0; + struct cam_req_mgr_connected_device *dev, tmp_dev; + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + + if (!dev->dev_info.trigger_on) + continue; + rc = dev->ops->get_dev_info(&dev->dev_info); + if (rc) { + CAM_ERR(CAM_CRM, "Get dev info failed link %x dev %x", + link->link_hdl, dev->dev_hdl); + continue; + } + + if (dev->dev_info.is_shdr_master) + master_dev_idx = i; + else + slave_dev_idx = i; + } + + if (master_dev_idx < slave_dev_idx) { + tmp_dev = link->l_dev[master_dev_idx]; + link->l_dev[master_dev_idx] = link->l_dev[slave_dev_idx]; + link->l_dev[slave_dev_idx] = tmp_dev; + } + + link->is_shdr = true; + link->wait_for_dual_trigger = true; + CAM_DBG(CAM_CRM, "link hdl %x wait for dual triger %d", + link->link_hdl, link->wait_for_dual_trigger); + + return rc; +} + int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) { int rc = 0, i; @@ -5492,6 +5594,9 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) link->link_hdl); rc = -EFAULT; } + + if (link->dual_trigger) + rc = cam_req_mgr_rearrange_devs(link); /* Wait for the streaming of sync link */ link->initial_skip = true; /* Pause the timer before sensor stream on */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.h b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.h index 8880e201e0..762296c5fb 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ + #ifndef _CAM_REQ_MGR_CORE_H_ #define _CAM_REQ_MGR_CORE_H_ @@ -245,11 +246,16 @@ struct cam_req_mgr_apply { * @num_dev : Number of devices need to be applied at this trigger point * @dev_hdl : Device handle who requested for special ops * @apply_at_eof : Boolean Identifier for request to be applied at EOF + * @is_applied : Flag to identify if request is already applied to device + * in previous frame + * @skip_isp_apply : Flag to indicate skip apply req for ISP */ struct crm_tbl_slot_special_ops { uint32_t num_dev; int32_t dev_hdl[MAX_DEV_FOR_SPECIAL_OPS]; bool apply_at_eof; + bool is_applied; + bool skip_isp_apply; }; /** @@ -332,8 +338,6 @@ struct cam_req_mgr_slot { int32_t num_sync_links; int32_t sync_link_hdls[MAXIMUM_LINKS_PER_SESSION - 1]; uint32_t bubble_times; - ktime_t ts; - ktime_t apply_ts; bool internal_recovered; }; @@ -402,13 +406,14 @@ struct cam_req_mgr_req_data { /** * struct cam_req_mgr_connected_device * - Device Properties - * @dev_hdl : device handle - * @dev_bit : unique bit assigned to device in link + * @dev_hdl : device handle + * @dev_bit : unique bit assigned to device in link * - Device characteristics - * @pd_tbl : tracks latest available req id at this device - * @dev_info : holds dev characteristics such as pipeline delay, dev name - * @ops : holds func pointer to call methods on this device - * @parent : pvt data - like link which this dev hdl belongs to + * @pd_tbl : tracks latest available req id at this device + * @dev_info : holds dev characteristics such as pipeline delay, dev name + * @ops : holds func pointer to call methods on this device + * @parent : pvt data - like link which this dev hdl belongs to + * @is_active : indicate whether device is active in auto shdr usecase */ struct cam_req_mgr_connected_device { int32_t dev_hdl; @@ -417,6 +422,7 @@ struct cam_req_mgr_connected_device { struct cam_req_mgr_device_info dev_info; struct cam_req_mgr_kmd_ops *ops; void *parent; + bool is_active; }; /** @@ -477,6 +483,8 @@ struct cam_req_mgr_connected_device { * @try_for_internal_recovery : If the link stalls try for RT internal recovery * @properties_mask : Indicates if current link enables some special properties * @cont_empty_slots : Continuous empty slots + * @is_shdr : flag to indicate auto shdr usecase without SFE + * @wait_for_dual_trigger: Flag to indicate whether to wait for second epoch in dual trigger */ struct cam_req_mgr_core_link { int32_t link_hdl; @@ -521,6 +529,8 @@ struct cam_req_mgr_core_link { bool is_sending_req; uint32_t properties_mask; uint32_t cont_empty_slots; + bool is_shdr; + bool wait_for_dual_trigger; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_interface.h b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_interface.h index f41655c619..96e4c8b3b4 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_interface.h +++ b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_interface.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_REQ_MGR_INTERFACE_H @@ -141,6 +141,14 @@ enum cam_modeswitch_delay { #define CAM_TRIGGER_POINT_EOF (1 << 1) #define CAM_TRIGGER_MAX_POINTS 2 + +enum cam_req_mgr_dual_trigger { + CAM_REQ_DUAL_TRIGGER_NONE, + CAM_REQ_DUAL_TRIGGER_ONE_EXPOSURE, + CAM_REQ_DUAL_TRIGGER_TWO_EXPOSURE, + CAM_REQ_DUAL_TRIGGER_MAX, +}; + /** * enum cam_req_status * @brief : enumerator for request status @@ -304,6 +312,7 @@ struct cam_req_mgr_error_notify { * by not sending request to devices. ex: IFE and Flash * @trigger_eof : to identify that one of the device at this slot needs * to be apply at EOF + * @num_exp : num of exposure associated with the request */ struct cam_req_mgr_add_request { int32_t link_hdl; @@ -311,6 +320,7 @@ struct cam_req_mgr_add_request { uint64_t req_id; uint32_t skip_at_sof; uint32_t skip_at_eof; + uint32_t num_exp; bool trigger_eof; }; @@ -333,7 +343,10 @@ struct cam_req_mgr_notify_stop { * @p_delay : delay between time settings applied and take effect * @m_delay : delay between time modeswitch settings applied and take effect * @trigger : Trigger point for the client + * @mode_switch_req : Request id on which sensor mode switch observed on the device * @trigger_on : This device provides trigger + * @is_shdr : Flag to indicate auto shdr usecase without SFE + * @is_shdr_master : Flag to indicate master dev in auto shdr usecase without SFE */ struct cam_req_mgr_device_info { int32_t dev_hdl; @@ -342,7 +355,10 @@ struct cam_req_mgr_device_info { enum cam_pipeline_delay p_delay; enum cam_modeswitch_delay m_delay; uint32_t trigger; + uint64_t mode_switch_req; bool trigger_on; + bool is_shdr; + bool is_shdr_master; }; /** @@ -367,26 +383,26 @@ struct cam_req_mgr_core_dev_link_setup { /** * struct cam_req_mgr_apply_request - * @link_hdl : link identifier - * @dev_hdl : device handle for cross check - * @request_id : request id settings to apply - * @last_applied_max_pd_req : Last applied request on highest pd device - * -1 is considered invalid - * @report_if_bubble : report to crm if failure in applying - * @trigger_point : the trigger point of this apply - * @re_apply : to skip re_apply for buf_done request - * @recovery : Indicate if it is recovery req - * + * @link_hdl : link identifier + * @dev_hdl : device handle for cross check + * @request_id : request id settings to apply + * @last_applied_max_pd_req : Last applied req on highest pd dev -1 is considered invalid + * @report_if_bubble : report to crm if failure in applying + * @trigger_point : the trigger point of this apply + * @re_apply : to skip re_apply for buf_done request + * @recovery : Indicate if it is recovery req + * @dual_trigger_status : Enum to indicate status of dual trigger */ struct cam_req_mgr_apply_request { - int32_t link_hdl; - int32_t dev_hdl; - uint64_t request_id; - int64_t last_applied_max_pd_req; - int32_t report_if_bubble; - uint32_t trigger_point; - bool re_apply; - bool recovery; + int32_t link_hdl; + int32_t dev_hdl; + uint64_t request_id; + int64_t last_applied_max_pd_req; + int32_t report_if_bubble; + uint32_t trigger_point; + bool re_apply; + bool recovery; + enum cam_req_mgr_dual_trigger dual_trigger_status; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_workq.c b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_workq.c index 9313ebd63e..aa155ae3f8 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_workq.c +++ b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_req_mgr_workq.c @@ -157,7 +157,7 @@ int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task, } workq = (struct cam_req_mgr_core_workq *)task->parent; if (!workq) { - CAM_DBG(CAM_CRM, "NULL workq pointer suspect mem corruption"); + CAM_WARN_RATE_LIMIT(CAM_CRM, "NULL workq pointer suspect mem corruption"); return -EINVAL; } @@ -211,8 +211,6 @@ int cam_req_mgr_workq_create(char *name, int32_t num_tasks, return -ENOMEM; wq_flags |= WQ_UNBOUND; - wq_flags |= WQ_HIGHPRI; - if (flags & CAM_WORKQ_FLAG_HIGH_PRIORITY) wq_flags |= WQ_HIGHPRI; diff --git a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_subdev.h b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_subdev.h index 6af89c75bc..12c944ad1b 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_subdev.h +++ b/qcom/opensource/camera-kernel/drivers/cam_req_mgr/cam_subdev.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_SUBDEV_H_ @@ -82,6 +82,7 @@ enum cam_subdev_message_type_t { CAM_SUBDEV_MESSAGE_CONN_CSID_INFO, CAM_SUBDEV_MESSAGE_DRV_INFO, CAM_SUBDEV_MESSAGE_NOTIFY_HALT_RESUME, + CAM_SUBDEV_MESSAGE_CLOCK_UPDATE }; /* Enum for close sequence priority */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c index 84918e7f18..5deea98b4e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c @@ -16,30 +16,30 @@ struct cam_actuator_ctrl_t *g_a_ctrls[SEC_SENSOR_ID_MAX]; #endif -#if defined(CONFIG_SAMSUNG_OIS_MCU_STM32) -static int32_t cam_actuator_update_i2c_info(struct cam_actuator_ctrl_t *a_ctrl, - struct cam_actuator_i2c_info_t *i2c_info) -{ - struct cam_sensor_cci_client *cci_client = NULL; - - if (a_ctrl->io_master_info.master_type == CCI_MASTER) { - cci_client = a_ctrl->io_master_info.cci_client; - if (!cci_client) { - CAM_ERR(CAM_ACTUATOR, "failed: cci_client %pK", - cci_client); - return -EINVAL; - } - cci_client->cci_i2c_master = a_ctrl->cci_i2c_master; - cci_client->sid = (i2c_info->slave_addr) >> 1; - cci_client->retries = 3; - cci_client->id_map = 0; - cci_client->i2c_freq_mode = i2c_info->i2c_freq_mode; - } - - return 0; -} - -#endif +//#if defined(CONFIG_SAMSUNG_OIS_MCU_STM32) +//static int32_t cam_actuator_update_i2c_info(struct cam_actuator_ctrl_t *a_ctrl, +// struct cam_actuator_i2c_info_t *i2c_info) +//{ +// struct cam_sensor_cci_client *cci_client = NULL; +// +// if (a_ctrl->io_master_info.master_type == CCI_MASTER) { +// cci_client = a_ctrl->io_master_info.cci_client; +// if (!cci_client) { +// CAM_ERR(CAM_ACTUATOR, "failed: cci_client %pK", +// cci_client); +// return -EINVAL; +// } +// cci_client->cci_i2c_master = a_ctrl->cci_i2c_master; +// cci_client->sid = (i2c_info->slave_addr) >> 1; +// cci_client->retries = 3; +// cci_client->id_map = 0; +// cci_client->i2c_freq_mode = i2c_info->i2c_freq_mode; +// } +// +// return 0; +//} +// +//#endif static struct cam_i3c_actuator_data { struct cam_actuator_ctrl_t *a_ctrl; @@ -200,7 +200,7 @@ static int cam_actuator_init_subdev(struct cam_actuator_ctrl_t *a_ctrl) CAM_SD_CLOSE_MEDIUM_PRIORITY; rc = cam_register_subdev(&(a_ctrl->v4l2_dev_str)); - if (rc < 0) + if (rc) CAM_ERR(CAM_ACTUATOR, "Fail with cam_register_subdev rc: %d", rc); @@ -285,11 +285,6 @@ static int cam_actuator_i2c_component_bind(struct device *dev, a_ctrl->last_flush_req = 0; a_ctrl->cam_act_state = CAM_ACTUATOR_INIT; -#if defined(CONFIG_SAMSUNG_OIS_MCU_STM32) || defined(CONFIG_SAMSUNG_ACTUATOR_PREVENT_SHAKING) - if (a_ctrl->soc_info.index < SEC_SENSOR_ID_MAX) - g_a_ctrls[a_ctrl->soc_info.index] = a_ctrl; -#endif - return rc; unreg_subdev: @@ -444,14 +439,6 @@ static int cam_actuator_platform_component_bind(struct device *dev, goto free_mem; } -#if defined(CONFIG_SAMSUNG_OIS_MCU_STM32) - rc = cam_actuator_update_i2c_info(a_ctrl, &soc_private->i2c_info); - if (rc) { - CAM_ERR(CAM_ACTUATOR, "failed: to update i2c info rc %d", rc); - goto free_mem; - } -#endif - /* Fill platform device id*/ pdev->id = a_ctrl->soc_info.index; @@ -479,11 +466,6 @@ static int cam_actuator_platform_component_bind(struct device *dev, g_i3c_actuator_data[a_ctrl->soc_info.index].a_ctrl = a_ctrl; init_completion(&g_i3c_actuator_data[a_ctrl->soc_info.index].probe_complete); -#if defined(CONFIG_SAMSUNG_OIS_MCU_STM32) || defined(CONFIG_SAMSUNG_ACTUATOR_PREVENT_SHAKING) - if (a_ctrl->soc_info.index < SEC_SENSOR_ID_MAX) - g_a_ctrls[a_ctrl->soc_info.index] = a_ctrl; -#endif - return rc; free_mem: diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 96fc7c33c6..9b07351751 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -218,7 +218,7 @@ static void cam_cci_lock_queue(struct cci_device *cci_dev, cam_io_w_mb(val, base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + reg_offset); - if (cci_dev->cci_master_info[master].isBurstEnable[queue] == true) { + if (cci_dev->cci_master_info[master].is_burst_enable[queue] == true) { cci_dev->cci_master_info[master].num_words_exec[queue]++; read_val = cci_dev->cci_master_info[master].num_words_exec[queue]; } else { @@ -358,7 +358,7 @@ static void cam_cci_load_report_cmd(struct cci_device *cci_dev, cam_io_w_mb(report_val, base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + reg_offset); - if (cci_dev->cci_master_info[master].isBurstEnable[queue] == true) { + if (cci_dev->cci_master_info[master].is_burst_enable[queue] == true) { cci_dev->cci_master_info[master].num_words_exec[queue]++; read_val = cci_dev->cci_master_info[master].num_words_exec[queue]; } else { @@ -846,7 +846,6 @@ int32_t cam_cci_data_queue_burst_apply(struct cci_device *cci_dev, cci_dev->cci_master_info[master].data_queue_start_index[queue] = index; iterate--; } - CAM_DBG(CAM_CCI,"*******************************************************************"); } } @@ -889,8 +888,8 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, uint8_t data_len = 0, addr_len = 0; uint32_t index = 0; uint8_t *buf = NULL; - uint32_t lastI2cFullPayload = 0; - uint32_t triggerHalfQueue = 0, queueStartThreshold = 0; + uint32_t last_i2c_full_payload = 0; + uint32_t trigger_half_queue = 0, queue_start_threshold = 0; uint32_t en_threshold_irq = 0, cci_enable_th_irq = 0; if (i2c_cmd == NULL) { @@ -925,15 +924,17 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d : START for sid: 0x%x size: %d", cci_dev->soc_info.index, master, queue, c_ctrl->cci_info->sid, i2c_msg->size); - cci_dev->cci_master_info[master].isBurstEnable[queue] = false; + cci_dev->cci_master_info[master].is_burst_enable[queue] = false; cci_dev->cci_master_info[master].num_words_exec[queue] = 0; addr_len = cam_cci_convert_type_to_num_bytes(i2c_msg->addr_type); data_len = cam_cci_convert_type_to_num_bytes(i2c_msg->data_type); len = (cmd_size * data_len + addr_len); - lastI2cFullPayload = len/MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11; - /* For every 11 Bytes of Data 1 Byte of data is Control cmd: 0xF9 or 0xE9 or {0x19 to 0xB9} * - * Hence compute will account for "len/PAYLOAD_SIZE_11" */ + last_i2c_full_payload = len/MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11; + /* + * For every 11 Bytes of Data 1 Byte of data is Control cmd: 0xF9 or 0xE9 or {0x19 to 0xB9} + * Hence compute will account for "len/PAYLOAD_SIZE_11" + */ len = len + len/MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11 + (((len % MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11) == 0) ? 0 : 1); if (len % 4) { @@ -941,9 +942,10 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, } else { len = len/4; } - - /* Its possible that 8 number of CCI cmds, each 32-bit * - * can co-exisist in QUEUE along with I2C Data*/ + /* + * Its possible that 8 number of CCI cmds, each 32-bit + * can co-exisist in QUEUE along with I2C Data + */ len = len + 8; data_queue = kzalloc((len * sizeof(uint32_t)), @@ -963,9 +965,11 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, /* Retry count is not supported in BURST MODE */ c_ctrl->cci_info->retries = 0; - /* 1. Configure Slave ID through SET_PARAM_CMD + /* + * 1. Configure Slave ID through SET_PARAM_CMD * For Burst Mode retries are not supported. - * Record the number of words written to QUEUE*/ + * Record the number of words written to QUEUE + */ val = CCI_I2C_SET_PARAM_CMD | c_ctrl->cci_info->sid << 4 | c_ctrl->cci_info->retries << 16 | c_ctrl->cci_info->id_map << 18; @@ -977,8 +981,10 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, reg_offset); index++; - /* 2. Initialize the variables used for synchronizing between - * process context and CCI IRQ Context*/ + /* + * 2. Initialize the variables used for synchronizing between + * process context and CCI IRQ Context + */ spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue], flags); atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 0); @@ -1022,18 +1028,22 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, cam_cci_lock_queue(cci_dev, master, queue, 1); index++; - /* 4. Need to place 0xE0 marker in middle and end of the QUEUE to trigger - * Thresold Interrupt*/ + /* + * 4. Need to place 0xE0 marker in middle and end of the QUEUE to trigger + * Thresold Interrupt + */ full_queue_mark = (queue_size - index - 1) / MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_WORDS; half_queue_mark = full_queue_mark / 2; CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d queue_size: %d full_queue_mark: %d half_queue_mark: %d", cci_dev->soc_info.index, master, queue, queue_size, full_queue_mark, half_queue_mark); - /* 5. Iterate through entire size of settings ==> {reg_addr, reg_data} + /* + * 5. Iterate through entire size of settings ==> {reg_addr, reg_data} * and formulate in QUEUE0 like below * D2 A1 A2 F9 ==> 0xF9: Hold the BUS for I2C WRITE; {0xA2A1, 0xD2D1, * D6 D3 D4 D1 ==> 0xD4D3, 0xD6D5, 0xD8D7, 0xD10D9.......} - * D10 D7 D8 D5*/ + * D10 D7 D8 D5 + */ index = 0; buf = (uint8_t *) &data_queue[index]; @@ -1105,12 +1115,12 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, --cmd_size; } } while ((cmd_size > 0) && (i <= cci_dev->payload_size)); - /**/ + num_payload++; en_threshold_irq = cci_enable_th_irq && - (((num_payload % half_queue_mark) == 0) || (num_payload == lastI2cFullPayload)); + (((num_payload % half_queue_mark) == 0) || (num_payload == last_i2c_full_payload)); if (cmd_size > 0) { - if (en_threshold_irq){ + if (en_threshold_irq) { buf[0] |= 0xE0; cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]++; CAM_DBG(CAM_CCI, @@ -1127,7 +1137,7 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, } en_seq_write = 1; len = ((i-1)/4) + 1; - // increment pointer to next multiple of 4; which is a word in CCI QUEUE + /* increment pointer to next multiple of 4; which is a word in CCI QUEUE */ buf = buf + ((i+3) & ~0x03); num_word_written_to_queue += len; } @@ -1141,14 +1151,14 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]); index = 0; - queueStartThreshold = half_queue_mark * MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_WORDS; + queue_start_threshold = half_queue_mark * MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_WORDS; cci_dev->cci_master_info[master].data_queue[queue] = data_queue; cci_dev->cci_master_info[master].num_words_in_data_queue[queue] = num_word_written_to_queue; cci_dev->cci_master_info[master].data_queue_start_index[queue] = index; - cci_dev->cci_master_info[master].half_queue_mark[queue] = queueStartThreshold; + cci_dev->cci_master_info[master].half_queue_mark[queue] = queue_start_threshold; - cam_cci_data_queue_burst_apply(cci_dev, master, queue, triggerHalfQueue); + cam_cci_data_queue_burst_apply(cci_dev, master, queue, trigger_half_queue); while ((cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]) > 0) { if (!cam_common_wait_for_completion_timeout( @@ -1168,14 +1178,14 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev, goto ERROR; } cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]--; - CAM_INFO(CAM_CCI, + CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d Threshold IRQ Raised, BufferLevel: %d", cci_dev->soc_info.index, master, queue, cam_io_r_mb(base + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset)); } if (cci_dev->cci_master_info[master].th_irq_ref_cnt[queue] > 0) { - cci_dev->cci_master_info[master].isBurstEnable[queue] = true; + cci_dev->cci_master_info[master].is_burst_enable[queue] = true; cci_dev->cci_master_info[master].num_words_exec[queue] = 0; } @@ -1244,7 +1254,7 @@ static int32_t cam_cci_data_queue(struct cci_device *cci_dev, } reg_offset = master * 0x200 + queue * 0x100; - cci_dev->cci_master_info[master].isBurstEnable[queue] = false; + cci_dev->cci_master_info[master].is_burst_enable[queue] = false; cci_dev->cci_master_info[master].num_words_exec[queue] = 0; cam_io_w_mb(cci_dev->cci_wait_sync_cfg.cid, base + CCI_SET_CID_SYNC_TIMER_ADDR + @@ -1485,6 +1495,10 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd, void __iomem *base = NULL; cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } master = c_ctrl->cci_info->cci_i2c_master; read_cfg = &c_ctrl->cfg.cci_i2c_read_cfg; @@ -1776,6 +1790,10 @@ static int32_t cam_cci_read(struct v4l2_subdev *sd, void __iomem *base = NULL; cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } master = c_ctrl->cci_info->cci_i2c_master; read_cfg = &c_ctrl->cfg.cci_i2c_read_cfg; @@ -1994,6 +2012,10 @@ static int32_t cam_cci_i2c_write(struct v4l2_subdev *sd, enum cci_i2c_master_t master; cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } if (cci_dev->cci_state != CCI_STATE_ENABLED) { CAM_ERR(CAM_CCI, "invalid cci: %d state: %d", @@ -2106,6 +2128,10 @@ static int32_t cam_cci_i2c_write_async(struct v4l2_subdev *sd, struct cam_sensor_i2c_reg_setting *cci_i2c_write_cfg_w; cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } write_async = kzalloc(sizeof(*write_async), GFP_KERNEL); if (!write_async) { @@ -2356,6 +2382,10 @@ static int32_t cam_cci_release(struct v4l2_subdev *sd, struct cci_device *cci_dev; cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } rc = cam_cci_soc_release(cci_dev, master); if (rc < 0) { @@ -2452,8 +2482,9 @@ int32_t cam_cci_core_cfg(struct v4l2_subdev *sd, return -EINVAL; } - if (!cci_ctrl) { - CAM_ERR(CAM_CCI, "CCI%d_I2C_M%d CCI_CTRL IS NULL", cci_dev->soc_info.index, master); + if (!cci_ctrl || !cci_ctrl->cci_info) { + CAM_ERR(CAM_CCI, "CCI%d_I2C_M%d CCI_CTRL OR CCI_INFO IS NULL", + cci_dev->soc_info.index, master); return -EINVAL; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.h index 182e500a50..50298625de 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_core.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CCI_CORE_H_ #define _CAM_CCI_CORE_H_ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c index ad6f89a185..1d80fc11f3 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -27,8 +27,8 @@ struct cci_irq_data { static struct v4l2_subdev *g_cci_subdev[MAX_CCI] = { 0 }; static struct dentry *debugfs_root; static struct cci_irq_data cci_irq_queue[QUEUE_SIZE] = { 0 }; -static int32_t head = 0; -static int32_t tail = 0; +static int32_t head; +static int32_t tail; #if defined(CONFIG_CAMERA_SYSFS_V2) struct device *is_dev = NULL; @@ -214,7 +214,7 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) spin_lock_irqsave(&cci_dev->lock_status, flags); trace_cam_cci_burst(cci_dev->soc_info.index, 1, 0, "th_irq honoured irq1", irq_status1); - CAM_INFO(CAM_CCI, "CCI%d_M1_Q0: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", + CAM_DBG(CAM_CCI, "CCI%d_M1_Q0: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", cci_dev->soc_info.index, irq_status1, cci_master_info->th_irq_ref_cnt[QUEUE_0]); if (cci_master_info->th_irq_ref_cnt[QUEUE_0] == 1) { @@ -248,7 +248,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) spin_lock_irqsave(&cci_dev->lock_status, flags); trace_cam_cci_burst(cci_dev->soc_info.index, 1, 1, "th_irq honoured irq1", irq_status1); - CAM_INFO(CAM_CCI, "CCI%d_M1_Q1: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", + CAM_DBG(CAM_CCI, + "CCI%d_M1_Q1: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", cci_dev->soc_info.index, irq_status1, cci_master_info->th_irq_ref_cnt[QUEUE_1]); if (cci_master_info->th_irq_ref_cnt[QUEUE_1] == 1) { @@ -282,7 +283,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) spin_lock_irqsave(&cci_dev->lock_status, flags); trace_cam_cci_burst(cci_dev->soc_info.index, 0, 0, "th_irq honoured irq1", irq_status1); - CAM_INFO(CAM_CCI, "CCI%d_M0_Q0: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", + CAM_DBG(CAM_CCI, + "CCI%d_M0_Q0: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", cci_dev->soc_info.index, irq_status1, cci_master_info->th_irq_ref_cnt[QUEUE_0]); if (cci_master_info->th_irq_ref_cnt[QUEUE_0] == 1) { @@ -316,7 +318,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) spin_lock_irqsave(&cci_dev->lock_status, flags); trace_cam_cci_burst(cci_dev->soc_info.index, 0, 1, "th_irq honoured irq1", irq_status1); - CAM_INFO(CAM_CCI, "CCI%d_M0_Q1: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", + CAM_DBG(CAM_CCI, + "CCI%d_M0_Q1: th_irq honoured irq1: 0x%x th_irq_ref_cnt: %d", cci_dev->soc_info.index, irq_status1, cci_master_info->th_irq_ref_cnt[QUEUE_1]); if (cci_master_info->th_irq_ref_cnt[QUEUE_1] == 1) { @@ -579,12 +582,14 @@ irqreturn_t cam_cci_threaded_irq(int irq_num, void *data) CAM_INFO(CAM_CCI, "CCI%d: nice: %d rt-Priority: %d cci_dev: %p", soc_info->index, task_nice(current), task->rt_priority, cci_dev); spin_lock_irqsave(&cci_dev->lock_status, flags); - if(tail != head) { + if (tail != head) { cci_data = cci_irq_queue[tail]; tail = increment_index(tail); - /* "head" and "tail" variables are shared across + /* + * "head" and "tail" variables are shared across * Top half and Bottom Half routines, Hence place a - * lock while accessing these variables.*/ + * lock while accessing these variables. + */ spin_unlock_irqrestore(&cci_dev->lock_status, flags); cam_cci_data_queue_burst_apply(cci_dev, cci_data.master, cci_data.queue, triggerHalfQueue); @@ -597,10 +602,22 @@ irqreturn_t cam_cci_threaded_irq(int irq_num, void *data) static int cam_cci_irq_routine(struct v4l2_subdev *sd, u32 status, bool *handled) { - struct cci_device *cci_dev = v4l2_get_subdevdata(sd); + struct cci_device *cci_dev = NULL; irqreturn_t ret; - struct cam_hw_soc_info *soc_info = - &cci_dev->soc_info; + struct cam_hw_soc_info *soc_info = NULL; + + if (!sd) { + CAM_ERR(CAM_CCI, "Error No data in subdev"); + return -EINVAL; + } + + cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } + + soc_info = &cci_dev->soc_info; ret = cam_cci_irq(soc_info->irq_num[0], cci_dev); if (ret == IRQ_NONE) @@ -747,7 +764,7 @@ static int cam_cci_component_bind(struct device *dev, goto cci_unregister_subdev; } - CAM_INFO(CAM_CCI, "CPAS registration successful handle=%d", + CAM_DBG(CAM_CCI, "CPAS registration successful handle=%d", cpas_parms.client_handle); new_cci_dev->cpas_handle = cpas_parms.client_handle; @@ -756,8 +773,9 @@ static int cam_cci_component_bind(struct device *dev, CAM_WARN(CAM_CCI, "debugfs creation failed"); rc = 0; } - CAM_ERR(CAM_CCI, "CCI Component bound successfully: %s", - pdev->name); + head = 0; + tail = 0; + CAM_DBG(CAM_CCI, "Component bound successfully"); return rc; cci_unregister_subdev: @@ -774,8 +792,23 @@ static void cam_cci_component_unbind(struct device *dev, struct platform_device *pdev = to_platform_device(dev); struct v4l2_subdev *subdev = platform_get_drvdata(pdev); - struct cci_device *cci_dev = - v4l2_get_subdevdata(subdev); + struct cci_device *cci_dev = NULL; + + if (!subdev) { + CAM_ERR(CAM_CCI, "Error No data in subdev"); + return; + } + + cci_dev = v4l2_get_subdevdata(subdev); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "Error No data in cci_dev"); + return; + } + + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return; + } cam_cpas_unregister_client(cci_dev->cpas_handle); debugfs_root = NULL; @@ -796,13 +829,10 @@ static int cam_cci_platform_probe(struct platform_device *pdev) { int rc = 0; - CAM_ERR(CAM_CCI, "Adding CCI component: %s", pdev->name); + CAM_DBG(CAM_CCI, "Adding CCI component"); rc = component_add(&pdev->dev, &cam_cci_component_ops); if (rc) - CAM_ERR(CAM_CCI, "failed to add component rc:%d ::%s", rc, pdev->name); - - CAM_ERR(CAM_CCI, "CCI platform probe successful. rc:%d ::%s", - rc, pdev->name); + CAM_ERR(CAM_CCI, "failed to add component rc: %d", rc); #if defined(CONFIG_CAMERA_SYSFS_V2) is_dev = &pdev->dev; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index cd378c3d09..fed1e20b5f 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CCI_DEV_H_ @@ -145,7 +145,7 @@ struct cam_cci_master_info { bool is_initilized; struct completion th_burst_complete[NUM_QUEUES]; uint32_t th_irq_ref_cnt[NUM_QUEUES]; - bool isBurstEnable[NUM_QUEUES]; + bool is_burst_enable[NUM_QUEUES]; uint32_t num_words_exec[NUM_QUEUES]; uint32_t *data_queue[NUM_QUEUES]; uint32_t num_words_in_data_queue[NUM_QUEUES]; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h index e2aa351fad..c9f8e8410a 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2012-2015, 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CCI_HWREG_ @@ -39,7 +40,6 @@ #define CCI_IRQ_MASK_0_ADDR 0x00000c04 #define CCI_IRQ_MASK_0_RMSK 0x7fff7ff7 #define CCI_IRQ_MASK_1_ADDR 0x00000c10 -//#define CCI_IRQ_MASK_1_RMSK 0x00110000 #define CCI_IRQ_MASK_1_RMSK 0x00DD0000 #define CCI_IRQ_CLEAR_0_ADDR 0x00000c08 #define CCI_IRQ_CLEAR_1_ADDR 0x00000c14 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c index 1fa6a769a3..e670980c65 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c @@ -405,8 +405,8 @@ int cam_cci_parse_dt_info(struct platform_device *pdev, &new_cci_dev->soc_info; void *irq_data[CAM_SOC_MAX_IRQ_LINES_PER_DEV] = {0}; int32_t num_irq = 0; - struct task_struct* task = NULL; - struct irq_desc * desc = NULL; + struct task_struct *task = NULL; + struct irq_desc *desc = NULL; struct sched_param param = {0}; @@ -420,9 +420,10 @@ int cam_cci_parse_dt_info(struct platform_device *pdev, for (i = 0; i < soc_info->irq_count; i++) irq_data[i] = new_cci_dev; - - // Lokesh: Bypass devm_request_irq() and induce - // devm_request_threaded_irq() externally. + /* + * Bypass devm_request_irq() and induce + * devm_request_threaded_irq() externally. + */ num_irq = soc_info->irq_count; soc_info->irq_count = 0; rc = cam_soc_util_request_platform_resource(soc_info, diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 0a66a3b639..714e67e406 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -39,14 +39,12 @@ */ #define CAM_MAX_PHYS_PER_CP_CTRL_REG 4 -static DEFINE_MUTEX(active_csiphy_cnt_mutex); -static DEFINE_MUTEX(main_aon_selection); +/* + * PHY ON-The-Go Buffer Size + */ +#define CSIPHY_ONTHEGO_BUFSIZE 30 -static int csiphy_onthego_reg_count; -static unsigned int csiphy_onthego_regs[150]; -module_param_array(csiphy_onthego_regs, uint, &csiphy_onthego_reg_count, 0644); -MODULE_PARM_DESC(csiphy_onthego_regs, "Functionality to let csiphy registers program on the fly"); struct g_csiphy_data { void __iomem *base_address; @@ -58,8 +56,125 @@ struct g_csiphy_data { struct cam_csiphy_aon_sel_params_t *aon_sel_param; }; +static DEFINE_MUTEX(active_csiphy_cnt_mutex); +static DEFINE_MUTEX(main_aon_selection); static struct g_csiphy_data g_phy_data[MAX_CSIPHY] = {0}; static int active_csiphy_hw_cnt; +static char csiphy_onthego_regs[20]; +static int csiphy_onthego_reg_count[MAX_CSIPHY]; +static unsigned int csiphy_onthego_regvals[MAX_CSIPHY][CSIPHY_ONTHEGO_BUFSIZE]; + + +typedef int (*csiphy_onthego_func)(int *inp, int n_inp, int phy_idx, char *outp); +static int csiphy_onthego_get_set(int *inp, int n_inp, int phy_idx, char *outp); + +static int csiphy_set_onthego_values(const char *val, const struct kernel_param *kp) +{ + /** + * Expected format string: ":n1,n2,..:val1,val2,..."" + * Values between the colons, specify the PHY(s) with + * which these settings apply to + * The actual onthego values should have comma-delimited + * entries with total a multiple of 3 (reg_addr, val, delay) + */ + csiphy_onthego_func fn = (csiphy_onthego_func) kp->arg; + int i, idx, onthego_val, onthego_idx = 0; + int onthego_values[CSIPHY_ONTHEGO_BUFSIZE] = {0}; + char *p1, *p2, *token; + bool phy_target[MAX_CSIPHY] = {false}; + + p1 = strnchr(val, 1, ':'); p2 = strrchr(val, ':'); + if (!p1 || !p2 || p2 - p1 < 2) { + CAM_ERR(CAM_CSIPHY, "Invalid csiphy onthego input string: %s", val); + return -EINVAL; + } + + strscpy(csiphy_onthego_regs, p1, 20); + while ((token = strsep(&p1, ":")) != NULL) { + if (!kstrtoint(token, 0, &idx) && idx >= 0 && idx < MAX_CSIPHY) + phy_target[idx] = true; + } + + p1 = p2 + 1; + + if (!strncasecmp(p1, "X", 1)) { + for (i = 0; i < MAX_CSIPHY; i++) { + if (phy_target[i]) + csiphy_onthego_reg_count[i] = 0; + } + return 0; + } + + while ((token = strsep(&p1, ",")) != NULL) { + if (!kstrtoint(token, 0, &onthego_val)) + onthego_values[onthego_idx++] = onthego_val; + } + + if (!onthego_idx || (onthego_idx % 3)) { + CAM_ERR(CAM_CSIPHY, "Invalid multiple of onthego entries: %d,", onthego_idx); + return -EINVAL; + } + + for (i = 0; i < MAX_CSIPHY && onthego_idx; i++) { + if (phy_target[i]) + fn(onthego_values, onthego_idx, i, NULL); + } + + return 0; +} + +static int csiphy_get_onthego_values(char *buffer, const struct kernel_param *kp) +{ + csiphy_onthego_func fn = (csiphy_onthego_func) kp->arg; + int rc = 0, i; + char *p = buffer; + + for (i = 0; i < MAX_CSIPHY; i++) + rc += fn(NULL, 0, i, p + rc); + + return rc; +} + +static const struct kernel_param_ops csiphy_onthego_ops = { + .set = csiphy_set_onthego_values, + .get = csiphy_get_onthego_values, +}; + +module_param_cb(csiphy_onthego_regs, &csiphy_onthego_ops, csiphy_onthego_get_set, 0644); +MODULE_PARM_DESC(csiphy_onthego_regs, "Functionality to let csiphy registers program on the fly"); + +static int csiphy_onthego_get_set(int *inp, int n_inp, int phy_idx, char *outp) +{ + int i, idx, rc = 0; + char *p; + + idx = csiphy_onthego_reg_count[phy_idx]; + + if (inp && n_inp) { + for (i = 0; i < n_inp; i++) { + csiphy_onthego_regvals[phy_idx][idx] = (unsigned int) inp[i]; + if (++idx == CSIPHY_ONTHEGO_BUFSIZE) { + CAM_WARN(CAM_CSIPHY, + "Onthego input for PHY %d reached end of circular buffer, circling back", + phy_idx); + idx = idx % CSIPHY_ONTHEGO_BUFSIZE; + } + } + } + + csiphy_onthego_reg_count[phy_idx] = idx; + + if (outp) { + p = outp; + rc += scnprintf(p, PAGE_SIZE, "PHY idx %d: ", phy_idx); + for (i = 0; i < idx; i++) + rc += scnprintf(p + rc, PAGE_SIZE - rc, "0x%x,", + csiphy_onthego_regvals[phy_idx][i]); + rc += scnprintf(p + rc, PAGE_SIZE - rc, "\n"); + } + + return rc; +} void cam_csiphy_update_auxiliary_mask(struct csiphy_device *csiphy_dev) { @@ -73,7 +188,7 @@ void cam_csiphy_update_auxiliary_mask(struct csiphy_device *csiphy_dev) return; } - g_phy_data[csiphy_dev->soc_info.index].data_rate_aux_mask ^= + g_phy_data[csiphy_dev->soc_info.index].data_rate_aux_mask |= BIT_ULL(csiphy_dev->curr_data_rate_idx); /* check if userland has provided a buffer for data rate aux mask */ @@ -179,23 +294,23 @@ static inline void cam_csiphy_apply_onthego_reg_values(void __iomem *csiphybase, CAM_DBG(CAM_CSIPHY, "csiphy: %d, onthego_reg_count: %d", csiphy_idx, - csiphy_onthego_reg_count); + csiphy_onthego_reg_count[csiphy_idx]); - if (csiphy_onthego_reg_count % 3) - csiphy_onthego_reg_count -= (csiphy_onthego_reg_count % 3); + for (i = 0; i < csiphy_onthego_reg_count[csiphy_idx]; i += 3) { + cam_io_w_mb(csiphy_onthego_regvals[csiphy_idx][i+1], + csiphybase + csiphy_onthego_regvals[csiphy_idx][i]); - for (i = 0; i < csiphy_onthego_reg_count; i += 3) { - cam_io_w_mb(csiphy_onthego_regs[i+1], - csiphybase + csiphy_onthego_regs[i]); - - if (csiphy_onthego_regs[i+2]) - usleep_range(csiphy_onthego_regs[i+2], csiphy_onthego_regs[i+2] + 5); + if (csiphy_onthego_regvals[csiphy_idx][i+2]) + usleep_range(csiphy_onthego_regvals[csiphy_idx][i+2], + csiphy_onthego_regvals[csiphy_idx][i+2] + 5); CAM_INFO(CAM_CSIPHY, "Offset: 0x%x, Val: 0x%x Delay(us): %u", - csiphy_onthego_regs[i], - cam_io_r_mb(csiphybase + csiphy_onthego_regs[i]), - csiphy_onthego_regs[i+2]); + csiphy_onthego_regvals[csiphy_idx][i], + cam_io_r_mb(csiphybase + csiphy_onthego_regvals[csiphy_idx][i]), + csiphy_onthego_regvals[csiphy_idx][i+2]); } + + csiphy_onthego_reg_count[csiphy_idx] = 0; } static inline int cam_csiphy_release_from_reset_state(struct csiphy_device *csiphy_dev, @@ -485,6 +600,7 @@ static void cam_csiphy_program_common_registers( } } +#ifndef CONFIG_CSF_2_5_SECURE_CAMERA static int cam_csiphy_update_secure_info(struct csiphy_device *csiphy_dev, int32_t index) { uint64_t lane_assign_bitmask = 0; @@ -514,6 +630,12 @@ static int cam_csiphy_update_secure_info(struct csiphy_device *csiphy_dev, int32 } switch (cpas_version) { + case CAM_CPAS_TITAN_640_V200: + case CAM_CPAS_TITAN_665_V100: + case CAM_CPAS_TITAN_770_V100: + bit_offset_bet_phys_in_cp_ctrl = + CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES + 1; + break; case CAM_CPAS_TITAN_580_V100: case CAM_CPAS_TITAN_680_V100: case CAM_CPAS_TITAN_780_V100: @@ -549,6 +671,7 @@ static int cam_csiphy_update_secure_info(struct csiphy_device *csiphy_dev, int32 return 0; } +#endif static int cam_csiphy_get_lane_enable( struct csiphy_device *csiphy, int index, @@ -798,7 +921,7 @@ static int __cam_csiphy_parse_lane_info_cmd_buf( csiphy_dev->csiphy_info[index].lane_enable |= lane_enable; lane_assign >>= 4; } - +#ifndef CONFIG_CSF_2_5_SECURE_CAMERA if (csiphy_dev->csiphy_info[index].secure_mode == 1) { rc = cam_csiphy_update_secure_info(csiphy_dev, index); if (rc) { @@ -807,7 +930,7 @@ static int __cam_csiphy_parse_lane_info_cmd_buf( goto reset_settings; } } - +#endif CAM_DBG(CAM_CSIPHY, "phy version:%d, phy_idx: %d, preamble_en: %u", csiphy_dev->hw_version, @@ -1187,12 +1310,10 @@ static int cam_csiphy_cphy_data_rate_config(struct csiphy_device *csiphy_device, reg_data = config_params[i].reg_data; reg_param_type = config_params[i].csiphy_param_type; delay = config_params[i].delay; -#if defined(CONFIG_CAMERA_ADAPTIVE_MIPI) && defined(CONFIG_CAMERA_RF_MIPI) CAM_DBG(CAM_CSIPHY, - "[RF_MIPI_DBG] param_type: %02d writing reg : %04X val : %02X delay: %dus", + "param_type: %d writing reg : %x val : %x delay: %dus", reg_param_type, reg_addr, reg_data, delay); -#endif switch (reg_param_type) { case CSIPHY_DEFAULT_PARAMS: cam_io_w_mb(reg_data, @@ -2101,7 +2222,6 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, uint32_t cphy_trio_status; void __iomem *csiphybase; int32_t rc = 0; - uint32_t i; if (!csiphy_dev || !cmd) { CAM_ERR(CAM_CSIPHY, "Invalid input args"); @@ -2130,6 +2250,12 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, csiphy_reg = csiphy_dev->ctrl_reg->csiphy_reg; status_reg_ptr = csiphy_reg->status_reg_params; + if (!status_reg_ptr) { + CAM_ERR(CAM_CSIPHY, "CSIPHY %d status reg is NULL: %s", + soc_info->index, CAM_IS_NULL_TO_STR(status_reg_ptr)); + return -EINVAL; + } + CAM_DBG(CAM_CSIPHY, "Opcode received: %d", cmd->op_code); mutex_lock(&csiphy_dev->mutex); switch (cmd->op_code) { @@ -2512,10 +2638,11 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, case CAM_START_DEV: { struct cam_csiphy_param *param; struct cam_start_stop_dev_cmd config; - int32_t offset; + int32_t i, offset; int clk_vote_level_high = -1; int clk_vote_level_low = -1; uint8_t data_rate_variant_idx = 0; + unsigned long clk_rate = 0; #if defined(CONFIG_CAMERA_ADAPTIVE_MIPI) && defined(CONFIG_CAMERA_RF_MIPI) data_rate_variant_idx = cam_csiphy_core_check_rf_condition(); @@ -2605,6 +2732,29 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, goto release_mutex; } + + for (i = 0; i < csiphy_dev->soc_info.num_clk; + i++) { + if (i == + csiphy_dev->soc_info.src_clk_idx) { + CAM_DBG(CAM_CSIPHY, + "Skipping call back for src" + " clk %s", + csiphy_dev->soc_info.clk_name[ + i]); + continue; + } + clk_rate = + cam_soc_util_get_clk_rate_applied( + &csiphy_dev->soc_info, i, + false, clk_vote_level_high); + if (clk_rate > 0) { + cam_subdev_notify_message( + CAM_TFE_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_CLOCK_UPDATE, + (void *)(&clk_rate)); + } + } } if (csiphy_dev->csiphy_info[offset].secure_mode == 1) { @@ -2689,7 +2839,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, rc = cam_csiphy_program_secure_mode( csiphy_dev, CAM_SECURE_MODE_SECURE, offset, false); - if (rc < 0) { + if (rc) { csiphy_dev->csiphy_info[offset].secure_mode = CAM_SECURE_MODE_NON_SECURE; goto cpas_stop; @@ -2725,7 +2875,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, goto hw_cnt_decrement; } - if (csiphy_onthego_reg_count) + if (csiphy_onthego_reg_count[soc_info->index]) cam_csiphy_apply_onthego_reg_values(csiphybase, soc_info->index); #if defined(CONFIG_CAMERA_CDR_TEST) @@ -2737,7 +2887,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, cam_csiphy_release_from_reset_state(csiphy_dev, csiphybase, offset); - if (g_phy_data[soc_info->index].is_3phase && status_reg_ptr) { + if (g_phy_data[soc_info->index].is_3phase) { for (i = 0; i < CAM_CSIPHY_MAX_CPHY_LANES; i++) { if (status_reg_ptr->cphy_lane_status[i]) { cphy_trio_status = cam_io_r_mb(csiphybase + diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c index 3bfc0fc892..dc408aa423 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_csiphy_dev.h" @@ -11,6 +11,7 @@ #include #include "camera_main.h" #include +#include "cam_cpas_api.h" #if defined(CONFIG_USE_CAMERA_HW_BIG_DATA) #include "cam_sensor_cmn_header.h" @@ -20,6 +21,7 @@ #endif #define CSIPHY_DEBUGFS_NAME_MAX_SIZE 10 +#define CAM_MAX_PHYS_PER_CP_CTRL_REG 4 static struct dentry *root_dentry; static inline void cam_csiphy_trigger_reg_dump(struct csiphy_device *csiphy_dev) @@ -40,7 +42,21 @@ static int cam_csiphy_format_secure_phy_lane_info( { struct cam_csiphy_param *param; uint64_t phy_lane_sel_mask = 0; + uint32_t cpas_version; + uint32_t bit_offset_bet_phys_in_cp_ctrl; + int rc; + if (csiphy_dev->soc_info.index > MAX_SUPPORTED_PHY_IDX) { + CAM_ERR(CAM_CSIPHY, "Invalid PHY index: %u", + csiphy_dev->soc_info.index); + return -EINVAL; + } + rc = cam_cpas_get_cpas_hw_version(&cpas_version); + + if (rc) { + CAM_ERR(CAM_CPAS, "Failed while getting CPAS Version"); + return rc; + } param = &csiphy_dev->csiphy_info[offset]; if (param->csiphy_3phase) { @@ -50,7 +66,6 @@ static int cam_csiphy_format_secure_phy_lane_info( phy_lane_sel_mask |= LANE_1_SEL; if (param->lane_enable & CPHY_LANE_2) phy_lane_sel_mask |= LANE_2_SEL; - phy_lane_sel_mask <<= CPHY_LANE_SELECTION_SHIFT; } else { if (param->lane_enable & DPHY_LANE_0) phy_lane_sel_mask |= LANE_0_SEL; @@ -60,16 +75,51 @@ static int cam_csiphy_format_secure_phy_lane_info( phy_lane_sel_mask |= LANE_2_SEL; if (param->lane_enable & DPHY_LANE_3) phy_lane_sel_mask |= LANE_3_SEL; - phy_lane_sel_mask <<= DPHY_LANE_SELECTION_SHIFT; } - if (csiphy_dev->soc_info.index > MAX_SUPPORTED_PHY_IDX) { - CAM_ERR(CAM_CSIPHY, "Invalid PHY index: %u", - csiphy_dev->soc_info.index); - return -EINVAL; + switch(cpas_version) + { + case CAM_CPAS_TITAN_665_V100: + bit_offset_bet_phys_in_cp_ctrl = + CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES + 1; + break; + default: + bit_offset_bet_phys_in_cp_ctrl = + CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES; + } + + if (CAM_CPAS_TITAN_665_V100 == cpas_version) + { + if (csiphy_dev->soc_info.index < CAM_MAX_PHYS_PER_CP_CTRL_REG) + { + phy_lane_sel_mask = phy_lane_sel_mask << + ((csiphy_dev->soc_info.index * bit_offset_bet_phys_in_cp_ctrl) + + (!param->csiphy_3phase) * + (CAM_CSIPHY_MAX_CPHY_LANES)); + } + else + { + phy_lane_sel_mask = phy_lane_sel_mask << + ((csiphy_dev->soc_info.index - CAM_MAX_PHYS_PER_CP_CTRL_REG) * + bit_offset_bet_phys_in_cp_ctrl + + (!param->csiphy_3phase) * + (CAM_CSIPHY_MAX_CPHY_LANES)); + } + *mask = phy_lane_sel_mask; + } + else + { + if (param->csiphy_3phase) + { + phy_lane_sel_mask = phy_lane_sel_mask << CPHY_LANE_SELECTION_SHIFT; + } + else + { + phy_lane_sel_mask = phy_lane_sel_mask << DPHY_LANE_SELECTION_SHIFT; + } + phy_lane_sel_mask |= BIT(csiphy_dev->soc_info.index); + *mask = phy_lane_sel_mask; } - phy_lane_sel_mask |= BIT(csiphy_dev->soc_info.index); - *mask = phy_lane_sel_mask; CAM_DBG(CAM_CSIPHY, "Formatted PHY[%u] phy_lane_sel_mask: 0x%llx", csiphy_dev->soc_info.index, *mask); @@ -151,6 +201,11 @@ static void cam_csiphy_subdev_handle_message(struct v4l2_subdev *sd, return; } + if (!csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "csiphy_dev ptr is NULL"); + return; + } + phy_idx = *(uint32_t *)data; if (phy_idx != csiphy_dev->soc_info.index) { CAM_DBG(CAM_CSIPHY, "Current HW IDX: %u, Expected IDX: %u", @@ -175,22 +230,14 @@ static void cam_csiphy_subdev_handle_message(struct v4l2_subdev *sd, break; } case CAM_SUBDEV_MESSAGE_APPLY_CSIPHY_AUX: { - csiphy_dev->mipi_error_count++; cam_csiphy_trigger_reg_dump(csiphy_dev); - if (csiphy_dev->mipi_error_count == MAX_MIPI_ERROR_COUNT) { - if (!csiphy_dev->skip_aux_settings) { - if (MAX_MIPI_ERROR_COUNT <= ++csiphy_dev->mipi_error_count) { - cam_csiphy_update_auxiliary_mask(csiphy_dev); - CAM_INFO(CAM_CSIPHY, - "CSIPHY[%u] mipi error count: %u, " - "updating aux settings for data rate idx: %u", - csiphy_dev->soc_info.index, - csiphy_dev->mipi_error_count, - csiphy_dev->curr_data_rate_idx); - csiphy_dev->mipi_error_count = 0; - } - } + if (!csiphy_dev->skip_aux_settings) { + cam_csiphy_update_auxiliary_mask(csiphy_dev); + + CAM_INFO(CAM_CSIPHY, + "CSIPHY[%u] updating aux settings for data rate idx: %u", + csiphy_dev->soc_info.index, csiphy_dev->curr_data_rate_idx); } break; } @@ -395,6 +442,11 @@ static long cam_csiphy_subdev_ioctl(struct v4l2_subdev *sd, struct csiphy_device *csiphy_dev = v4l2_get_subdevdata(sd); int rc = 0; + if (!csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "csiphy_dev ptr is NULL"); + return -EINVAL; + } + switch (cmd) { case VIDIOC_CAM_CONTROL: rc = cam_csiphy_core_cfg(csiphy_dev, arg); @@ -501,7 +553,6 @@ static int cam_csiphy_component_bind(struct device *dev, new_csiphy_dev->soc_info.dev_name = pdev->name; new_csiphy_dev->ref_count = 0; new_csiphy_dev->current_data_rate = 0; - new_csiphy_dev->mipi_error_count = 0; rc = cam_csiphy_parse_dt_info(pdev, new_csiphy_dev); if (rc < 0) { @@ -622,8 +673,27 @@ static void cam_csiphy_component_unbind(struct device *dev, { struct platform_device *pdev = to_platform_device(dev); - struct v4l2_subdev *subdev = platform_get_drvdata(pdev); - struct csiphy_device *csiphy_dev = v4l2_get_subdevdata(subdev); + struct v4l2_subdev *subdev = NULL; + struct csiphy_device *csiphy_dev = NULL; + + subdev = platform_get_drvdata(pdev); + + if (!subdev) { + CAM_ERR(CAM_CSIPHY, "Error No data in subdev"); + return; + } + + csiphy_dev = v4l2_get_subdevdata(subdev); + + if (!csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "Error No data in csiphy_dev"); + return; + } + + if (!csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "csiphy_dev ptr is NULL"); + return; + } cam_csiphy_debug_unregister(); CAM_INFO(CAM_CSIPHY, "Unbind CSIPHY component"); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h index b4da8cca63..3f6c1b2c58 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h @@ -30,7 +30,6 @@ #include "cam_context.h" #define MAX_CSIPHY 8 -#define MAX_MIPI_ERROR_COUNT 3 #define CSIPHY_NUM_CLK_MAX 16 @@ -56,6 +55,7 @@ #define CSIPHY_CDR_LN_SETTINGS BIT(11) #define CSIPHY_SHORT_CHANNEL_PARAMS BIT(12) #define CSIPHY_STANDARD_CHANNEL_PARAMS BIT(13) +#define CSIPHY_DNP_PARAMS BIT(14) #define CSIPHY_MAX_INSTANCES_PER_PHY 3 @@ -419,7 +419,6 @@ struct cam_csiphy_dev_aux_setting_params { * @skip_aux_settings : Debugfs flag to ignore calls to update aux settings * @domain_id_security : Flag to determine if target has domain-id based security * @preamble_enable : To enable preamble pattern - * @mipi_error_count : Mipi Error Counter */ struct csiphy_device { char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; @@ -459,7 +458,6 @@ struct csiphy_device { bool skip_aux_settings; bool domain_id_security; uint16_t preamble_enable; - uint16_t mipi_error_count; }; /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index 1037128f48..49f28e98b8 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_csiphy_soc.h" @@ -11,6 +11,7 @@ #include "include/cam_csiphy_2_1_2_hwreg.h" #include "include/cam_csiphy_2_1_3_hwreg.h" #include "include/cam_csiphy_2_2_0_hwreg.h" +#include "include/cam_csiphy_2_2_1_hwreg.h" #include "include/cam_csiphy_2_3_0_hwreg.h" /* Clock divide factor for CPHY spec v1.0 */ @@ -183,6 +184,7 @@ int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev, int32_t index) struct cam_hw_soc_info *soc_info; enum cam_vote_level vote_level; struct cam_csiphy_param *param = &csiphy_dev->csiphy_info[index]; + unsigned long clk_rate = 0; int i; soc_info = &csiphy_dev->soc_info; @@ -237,6 +239,31 @@ int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev, int32_t index) goto disable_platform_resource; } + } else { + clk_rate = soc_info->clk_rate[0][soc_info->src_clk_idx]; + rc = cam_soc_util_set_src_clk_rate(soc_info, + CAM_CLK_SW_CLIENT_IDX, clk_rate, 0); + if (rc) { + CAM_ERR(CAM_CSIPHY, "csiphy_set_src_clk_rate failed" + " rc: %d", rc); + rc = -EINVAL; + goto disable_platform_resource; + } + + for (i = 0; i < soc_info->num_clk; i++) { + if (i == soc_info->src_clk_idx) { + CAM_DBG(CAM_CSIPHY, "Skipping call back" + " for src clk %s", soc_info->clk_name[i]); + continue; + } + clk_rate = cam_soc_util_get_clk_rate_applied(soc_info, + i, false, vote_level); + if (clk_rate > 0) { + cam_subdev_notify_message(CAM_TFE_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_CLOCK_UPDATE, + (void *)(&clk_rate)); + } + } } cam_csiphy_reset(csiphy_dev); @@ -332,6 +359,11 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->hw_version = CSIPHY_VERSION_V220; csiphy_dev->is_divisor_32_comp = true; csiphy_dev->clk_lane = 0; + } else if (of_device_is_compatible(soc_info->dev->of_node, "qcom,csiphy-v2.2.1")) { + csiphy_dev->ctrl_reg = &ctrl_reg_2_2_1; + csiphy_dev->hw_version = CSIPHY_VERSION_V221; + csiphy_dev->is_divisor_32_comp = true; + csiphy_dev->clk_lane = 0; } else if (of_device_is_compatible(soc_info->dev->of_node, "qcom,csiphy-v2.3.0")) { csiphy_dev->ctrl_reg = &ctrl_reg_2_3_0; csiphy_dev->hw_version = CSIPHY_VERSION_V230; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h index f104d601bf..1dfa3931b8 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h @@ -36,6 +36,7 @@ #define CSIPHY_VERSION_V212 0x212 #define CSIPHY_VERSION_V213 0x213 #define CSIPHY_VERSION_V220 0x220 +#define CSIPHY_VERSION_V221 0x221 #define CSIPHY_VERSION_V230 0x230 /** diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_2_1_hwreg.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_2_1_hwreg.h new file mode 100644 index 0000000000..40fbd2e421 --- /dev/null +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_2_1_hwreg.h @@ -0,0 +1,2218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_2_2_1_HWREG_H_ +#define _CAM_CSIPHY_2_2_1_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct cam_csiphy_aon_sel_params_t aon_cam_select_params_2_2_1 = { + .aon_cam_sel_offset[0] = 0x01E0, + .aon_cam_sel_offset[1] = 0x01E4, + .cam_sel_mask = BIT(0), + .mclk_sel_mask = BIT(8), +}; + +struct cam_cphy_dphy_status_reg_params_t status_regs_2_2_1 = { + .csiphy_3ph_status0_offset = 0x0340, + .csiphy_2ph_status0_offset = 0x00C0, + .cphy_lane_status = {0x0358, 0x0758, 0x0B58}, + .csiphy_3ph_status_size = 24, + .csiphy_2ph_status_size = 20, +}; + +struct csiphy_reg_t csiphy_lane_en_reg_2_2_1[] = { + {0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE}, +}; + +struct csiphy_reg_t csiphy_common_reg_2_2_1[] = { + {0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x108C, 0x00, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x101C, 0x7A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1018, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_reset_enter_reg_2_2_1[] = { + {0x1000, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_reset_exit_reg_2_2_1[] = { + {0x1000, 0x02, 0x00, CSIPHY_2PH_REGS}, + {0x1000, 0x00, 0x00, CSIPHY_2PH_COMBO_REGS}, + {0x1000, 0x0E, 0xBE8, CSIPHY_3PH_REGS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_2_2_1[] = { + {0x102c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1030, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1034, 0xfb, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1038, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x103c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1040, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1044, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1048, 0xef, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x104c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1050, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1054, 0xff, 0x64, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_2ph_v2_2_1_reg[] = { + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E94, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x005C, 0x04, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x045C, 0x04, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x085C, 0x04, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x0C5C, 0x04, 0x00, CSIPHY_SKEW_CAL}, + {0x0C60, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, +}; + +struct csiphy_reg_t csiphy_2ph_v2_2_1_combo_mode_reg[] = { + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E94, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x07, 0xD1, CSIPHY_DEFAULT_PARAMS}, + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0828, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C28, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x005C, 0x04, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x045C, 0x04, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x085C, 0x04, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, +}; + +struct csiphy_reg_t csiphy_3ph_v2_2_1_reg[] = { + {0x02F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02F0, 0xEF, 0xD3, CSIPHY_DEFAULT_PARAMS}, + {0x06F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06F0, 0xEF, 0xD3, CSIPHY_DEFAULT_PARAMS}, + {0x0AF4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AF8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AFC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AF0, 0xEF, 0xD3, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0218, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0224, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0244, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0310, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0254, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0240, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0284, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0618, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0644, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0654, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0640, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0684, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AE4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AE8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AEC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A18, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A1C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A20, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A24, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A28, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A2C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A64, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A44, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B10, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0ABC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A54, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A40, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A60, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_80Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x1F, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x02, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x6B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x1F, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x02, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x6B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x1F, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x02, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x6B, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_100Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0xB6, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x01, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x6B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0xB6, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x01, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x6B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0xB6, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x01, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x6B, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_200Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0xE4, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0xE4, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0xE4, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_300Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x9E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x9E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x9E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_350Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x8A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x8A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x8A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_400Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x7B, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x7B, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x7B, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_500Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x66, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x66, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x66, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_600Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x58, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x58, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x58, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_700Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x4E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x4E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x4E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_800Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x46, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x46, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x46, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_900Msps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x40, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x40, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x40, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_1p0Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x58, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x3C, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x3C, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x3C, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_1p2Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x45, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x45, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x45, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x35, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x35, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x35, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_1p5Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x45, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x45, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x45, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x2E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x2E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x2E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_1p7Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x2E, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x2E, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x2E, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x2A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x2A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x2A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_2p0Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x2E, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x2E, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x2E, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x27, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x27, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x27, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_2p1Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x26, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x26, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x26, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_2p35Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x23, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x23, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x23, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_2p5Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x20, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x05, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x22, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x22, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x22, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_2p6Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x22, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x22, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x22, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_2p8Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x21, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x21, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x21, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_3p0Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x17, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x20, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x20, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x20, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_3p3Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x10, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x10, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x10, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x1E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x1E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x1E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_3p5Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x10, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x10, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x10, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x1E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x1E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x1E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_4p0Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x0C, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0278, 0x0C, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x0C, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0678, 0x0C, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x0C, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A78, 0x0C, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x1C, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x1C, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x1C, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_4p5Gsps[] = { + /* AFE Settings */ + {0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x06, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x06, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x06, 0x00, CSIPHY_CDR_LN_SETTINGS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x3D, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x2D, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x30, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x1B, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x1B, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x1B, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_5p0Gsps[] = { + /* AFE Settings */ + {0x0268, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x82, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0278, 0x82, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x82, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0678, 0x82, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x82, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A78, 0x82, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x1A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x1A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x1A, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_5p5Gsps[] = { + /* AFE Settings */ + {0x0268, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x80, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0278, 0x81, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x80, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0678, 0x81, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x80, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A78, 0x81, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t datarate_221_6p0Gsps[] = { + /* AFE Settings */ + {0x0268, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0294, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0278, 0x80, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0278, 0x81, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0288, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x026C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x026C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x028C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x028C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0668, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0694, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0678, 0x80, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0678, 0x81, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0688, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x066C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x066C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x068C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x068C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A68, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A78, 0x80, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A78, 0x81, 0x00, CSIPHY_CDR_LN_SETTINGS | CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A88, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A6C, 0x03, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A6C, 0x3F, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A8C, 0x33, 0x00, CSIPHY_SHORT_CHANNEL_PARAMS}, + {0x0A8C, 0x37, 0x00, CSIPHY_STANDARD_CHANNEL_PARAMS}, + {0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A74, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS}, + /* Datarate Sensitive */ + {0x020C, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A0C, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +static struct data_rate_reg_info_t data_rate_settings_2_2_1[] = { + { + /* ((80 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 182400000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_80Msps), + .data_rate_reg_array[0][0] = datarate_221_80Msps, + .data_rate_reg_array[1][0] = datarate_221_80Msps, + .data_rate_reg_array[2][0] = datarate_221_80Msps, + .data_rate_reg_array[3][0] = datarate_221_80Msps, + .data_rate_reg_array[4][0] = datarate_221_80Msps, + .data_rate_reg_array[5][0] = datarate_221_80Msps, + .data_rate_reg_array[6][0] = datarate_221_80Msps, + .data_rate_reg_array[7][0] = datarate_221_80Msps, + }, + { + /* ((100 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 228000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_100Msps), + .data_rate_reg_array[0][0] = datarate_221_100Msps, + .data_rate_reg_array[1][0] = datarate_221_100Msps, + .data_rate_reg_array[2][0] = datarate_221_100Msps, + .data_rate_reg_array[3][0] = datarate_221_100Msps, + .data_rate_reg_array[4][0] = datarate_221_100Msps, + .data_rate_reg_array[5][0] = datarate_221_100Msps, + .data_rate_reg_array[6][0] = datarate_221_100Msps, + .data_rate_reg_array[7][0] = datarate_221_100Msps, + }, + { + /* ((200 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 456000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_200Msps), + .data_rate_reg_array[0][0] = datarate_221_200Msps, + .data_rate_reg_array[1][0] = datarate_221_200Msps, + .data_rate_reg_array[2][0] = datarate_221_200Msps, + .data_rate_reg_array[3][0] = datarate_221_200Msps, + .data_rate_reg_array[4][0] = datarate_221_200Msps, + .data_rate_reg_array[5][0] = datarate_221_200Msps, + .data_rate_reg_array[6][0] = datarate_221_200Msps, + .data_rate_reg_array[7][0] = datarate_221_200Msps, + }, + { + /* ((300 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 684000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_300Msps), + .data_rate_reg_array[0][0] = datarate_221_300Msps, + .data_rate_reg_array[1][0] = datarate_221_300Msps, + .data_rate_reg_array[2][0] = datarate_221_300Msps, + .data_rate_reg_array[3][0] = datarate_221_300Msps, + .data_rate_reg_array[4][0] = datarate_221_300Msps, + .data_rate_reg_array[5][0] = datarate_221_300Msps, + .data_rate_reg_array[6][0] = datarate_221_300Msps, + .data_rate_reg_array[7][0] = datarate_221_300Msps, + }, + { + /* ((350 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 798000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_350Msps), + .data_rate_reg_array[0][0] = datarate_221_350Msps, + .data_rate_reg_array[1][0] = datarate_221_350Msps, + .data_rate_reg_array[2][0] = datarate_221_350Msps, + .data_rate_reg_array[3][0] = datarate_221_350Msps, + .data_rate_reg_array[4][0] = datarate_221_350Msps, + .data_rate_reg_array[5][0] = datarate_221_350Msps, + .data_rate_reg_array[6][0] = datarate_221_350Msps, + .data_rate_reg_array[7][0] = datarate_221_350Msps, + }, + { + /* ((400 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 912000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_400Msps), + .data_rate_reg_array[0][0] = datarate_221_400Msps, + .data_rate_reg_array[1][0] = datarate_221_400Msps, + .data_rate_reg_array[2][0] = datarate_221_400Msps, + .data_rate_reg_array[3][0] = datarate_221_400Msps, + .data_rate_reg_array[4][0] = datarate_221_400Msps, + .data_rate_reg_array[5][0] = datarate_221_400Msps, + .data_rate_reg_array[6][0] = datarate_221_400Msps, + .data_rate_reg_array[7][0] = datarate_221_400Msps, + }, + { + /* ((500 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 1140000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_500Msps), + .data_rate_reg_array[0][0] = datarate_221_500Msps, + .data_rate_reg_array[1][0] = datarate_221_500Msps, + .data_rate_reg_array[2][0] = datarate_221_500Msps, + .data_rate_reg_array[3][0] = datarate_221_500Msps, + .data_rate_reg_array[4][0] = datarate_221_500Msps, + .data_rate_reg_array[5][0] = datarate_221_500Msps, + .data_rate_reg_array[6][0] = datarate_221_500Msps, + .data_rate_reg_array[7][0] = datarate_221_500Msps, + }, + { + /* ((600 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 1368000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_600Msps), + .data_rate_reg_array[0][0] = datarate_221_600Msps, + .data_rate_reg_array[1][0] = datarate_221_600Msps, + .data_rate_reg_array[2][0] = datarate_221_600Msps, + .data_rate_reg_array[3][0] = datarate_221_600Msps, + .data_rate_reg_array[4][0] = datarate_221_600Msps, + .data_rate_reg_array[5][0] = datarate_221_600Msps, + .data_rate_reg_array[6][0] = datarate_221_600Msps, + .data_rate_reg_array[7][0] = datarate_221_600Msps, + }, + { + /* ((700 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 1596000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_700Msps), + .data_rate_reg_array[0][0] = datarate_221_700Msps, + .data_rate_reg_array[1][0] = datarate_221_700Msps, + .data_rate_reg_array[2][0] = datarate_221_700Msps, + .data_rate_reg_array[3][0] = datarate_221_700Msps, + .data_rate_reg_array[4][0] = datarate_221_700Msps, + .data_rate_reg_array[5][0] = datarate_221_700Msps, + .data_rate_reg_array[6][0] = datarate_221_700Msps, + .data_rate_reg_array[7][0] = datarate_221_700Msps, + }, + { + /* ((800 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 1824000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_800Msps), + .data_rate_reg_array[0][0] = datarate_221_800Msps, + .data_rate_reg_array[1][0] = datarate_221_800Msps, + .data_rate_reg_array[2][0] = datarate_221_800Msps, + .data_rate_reg_array[3][0] = datarate_221_800Msps, + .data_rate_reg_array[4][0] = datarate_221_800Msps, + .data_rate_reg_array[5][0] = datarate_221_800Msps, + .data_rate_reg_array[6][0] = datarate_221_800Msps, + .data_rate_reg_array[7][0] = datarate_221_800Msps, + }, + { + /* ((900 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 2052000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_900Msps), + .data_rate_reg_array[0][0] = datarate_221_900Msps, + .data_rate_reg_array[1][0] = datarate_221_900Msps, + .data_rate_reg_array[2][0] = datarate_221_900Msps, + .data_rate_reg_array[3][0] = datarate_221_900Msps, + .data_rate_reg_array[4][0] = datarate_221_900Msps, + .data_rate_reg_array[5][0] = datarate_221_900Msps, + .data_rate_reg_array[6][0] = datarate_221_900Msps, + .data_rate_reg_array[7][0] = datarate_221_900Msps, + }, + { + /* ((1000 MSpS) * (10^6) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 2280000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_1p0Gsps), + .data_rate_reg_array[0][0] = datarate_221_1p0Gsps, + .data_rate_reg_array[1][0] = datarate_221_1p0Gsps, + .data_rate_reg_array[2][0] = datarate_221_1p0Gsps, + .data_rate_reg_array[3][0] = datarate_221_1p0Gsps, + .data_rate_reg_array[4][0] = datarate_221_1p0Gsps, + .data_rate_reg_array[5][0] = datarate_221_1p0Gsps, + .data_rate_reg_array[6][0] = datarate_221_1p0Gsps, + .data_rate_reg_array[7][0] = datarate_221_1p0Gsps, + }, + { + /* ((1.2 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 2736000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_1p2Gsps), + .data_rate_reg_array[0][0] = datarate_221_1p2Gsps, + .data_rate_reg_array[1][0] = datarate_221_1p2Gsps, + .data_rate_reg_array[2][0] = datarate_221_1p2Gsps, + .data_rate_reg_array[3][0] = datarate_221_1p2Gsps, + .data_rate_reg_array[4][0] = datarate_221_1p2Gsps, + .data_rate_reg_array[5][0] = datarate_221_1p2Gsps, + .data_rate_reg_array[6][0] = datarate_221_1p2Gsps, + .data_rate_reg_array[7][0] = datarate_221_1p2Gsps, + }, + { + /* ((1.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 3420000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_1p5Gsps), + .data_rate_reg_array[0][0] = datarate_221_1p5Gsps, + .data_rate_reg_array[1][0] = datarate_221_1p5Gsps, + .data_rate_reg_array[2][0] = datarate_221_1p5Gsps, + .data_rate_reg_array[3][0] = datarate_221_1p5Gsps, + .data_rate_reg_array[4][0] = datarate_221_1p5Gsps, + .data_rate_reg_array[5][0] = datarate_221_1p5Gsps, + .data_rate_reg_array[6][0] = datarate_221_1p5Gsps, + .data_rate_reg_array[7][0] = datarate_221_1p5Gsps, + }, + { + /* ((1.7 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 3876000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_1p7Gsps), + .data_rate_reg_array[0][0] = datarate_221_1p7Gsps, + .data_rate_reg_array[1][0] = datarate_221_1p7Gsps, + .data_rate_reg_array[2][0] = datarate_221_1p7Gsps, + .data_rate_reg_array[3][0] = datarate_221_1p7Gsps, + .data_rate_reg_array[4][0] = datarate_221_1p7Gsps, + .data_rate_reg_array[5][0] = datarate_221_1p7Gsps, + .data_rate_reg_array[6][0] = datarate_221_1p7Gsps, + .data_rate_reg_array[7][0] = datarate_221_1p7Gsps, + }, + { + /* ((2.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 4560000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_2p0Gsps), + .data_rate_reg_array[0][0] = datarate_221_2p0Gsps, + .data_rate_reg_array[1][0] = datarate_221_2p0Gsps, + .data_rate_reg_array[2][0] = datarate_221_2p0Gsps, + .data_rate_reg_array[3][0] = datarate_221_2p0Gsps, + .data_rate_reg_array[4][0] = datarate_221_2p0Gsps, + .data_rate_reg_array[5][0] = datarate_221_2p0Gsps, + .data_rate_reg_array[6][0] = datarate_221_2p0Gsps, + .data_rate_reg_array[7][0] = datarate_221_2p0Gsps, + }, + { + /* ((2.1 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 4788000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_2p1Gsps), + .data_rate_reg_array[0][0] = datarate_221_2p1Gsps, + .data_rate_reg_array[1][0] = datarate_221_2p1Gsps, + .data_rate_reg_array[2][0] = datarate_221_2p1Gsps, + .data_rate_reg_array[3][0] = datarate_221_2p1Gsps, + .data_rate_reg_array[4][0] = datarate_221_2p1Gsps, + .data_rate_reg_array[5][0] = datarate_221_2p1Gsps, + .data_rate_reg_array[6][0] = datarate_221_2p1Gsps, + .data_rate_reg_array[7][0] = datarate_221_2p1Gsps, + }, + { + /* ((2.35 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 5358000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_2p35Gsps), + .data_rate_reg_array[0][0] = datarate_221_2p35Gsps, + .data_rate_reg_array[1][0] = datarate_221_2p35Gsps, + .data_rate_reg_array[2][0] = datarate_221_2p35Gsps, + .data_rate_reg_array[3][0] = datarate_221_2p35Gsps, + .data_rate_reg_array[4][0] = datarate_221_2p35Gsps, + .data_rate_reg_array[5][0] = datarate_221_2p35Gsps, + .data_rate_reg_array[6][0] = datarate_221_2p35Gsps, + .data_rate_reg_array[7][0] = datarate_221_2p35Gsps, + }, + { + /* ((2.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 5700000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_2p5Gsps), + .data_rate_reg_array[0][0] = datarate_221_2p5Gsps, + .data_rate_reg_array[1][0] = datarate_221_2p5Gsps, + .data_rate_reg_array[2][0] = datarate_221_2p5Gsps, + .data_rate_reg_array[3][0] = datarate_221_2p5Gsps, + .data_rate_reg_array[4][0] = datarate_221_2p5Gsps, + .data_rate_reg_array[5][0] = datarate_221_2p5Gsps, + .data_rate_reg_array[6][0] = datarate_221_2p5Gsps, + .data_rate_reg_array[7][0] = datarate_221_2p5Gsps, + }, + { + /* ((2.6 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 5928000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_2p6Gsps), + .data_rate_reg_array[0][0] = datarate_221_2p6Gsps, + .data_rate_reg_array[1][0] = datarate_221_2p6Gsps, + .data_rate_reg_array[2][0] = datarate_221_2p6Gsps, + .data_rate_reg_array[3][0] = datarate_221_2p6Gsps, + .data_rate_reg_array[4][0] = datarate_221_2p6Gsps, + .data_rate_reg_array[5][0] = datarate_221_2p6Gsps, + .data_rate_reg_array[6][0] = datarate_221_2p6Gsps, + .data_rate_reg_array[7][0] = datarate_221_2p6Gsps, + }, + { + /* ((2.8 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 6384000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_2p8Gsps), + .data_rate_reg_array[0][0] = datarate_221_2p8Gsps, + .data_rate_reg_array[1][0] = datarate_221_2p8Gsps, + .data_rate_reg_array[2][0] = datarate_221_2p8Gsps, + .data_rate_reg_array[3][0] = datarate_221_2p8Gsps, + .data_rate_reg_array[4][0] = datarate_221_2p8Gsps, + .data_rate_reg_array[5][0] = datarate_221_2p8Gsps, + .data_rate_reg_array[6][0] = datarate_221_2p8Gsps, + .data_rate_reg_array[7][0] = datarate_221_2p8Gsps, + }, + { + /* ((3.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 6840000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_3p0Gsps), + .data_rate_reg_array[0][0] = datarate_221_3p0Gsps, + .data_rate_reg_array[1][0] = datarate_221_3p0Gsps, + .data_rate_reg_array[2][0] = datarate_221_3p0Gsps, + .data_rate_reg_array[3][0] = datarate_221_3p0Gsps, + .data_rate_reg_array[4][0] = datarate_221_3p0Gsps, + .data_rate_reg_array[5][0] = datarate_221_3p0Gsps, + .data_rate_reg_array[6][0] = datarate_221_3p0Gsps, + .data_rate_reg_array[7][0] = datarate_221_3p0Gsps, + }, + { + /* ((3.3 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 7524000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_3p3Gsps), + .data_rate_reg_array[0][0] = datarate_221_3p3Gsps, + .data_rate_reg_array[1][0] = datarate_221_3p3Gsps, + .data_rate_reg_array[2][0] = datarate_221_3p3Gsps, + .data_rate_reg_array[3][0] = datarate_221_3p3Gsps, + .data_rate_reg_array[4][0] = datarate_221_3p3Gsps, + .data_rate_reg_array[5][0] = datarate_221_3p3Gsps, + .data_rate_reg_array[6][0] = datarate_221_3p3Gsps, + .data_rate_reg_array[7][0] = datarate_221_3p3Gsps, + }, + { + /* ((3.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 7980000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_3p5Gsps), + .data_rate_reg_array[0][0] = datarate_221_3p5Gsps, + .data_rate_reg_array[1][0] = datarate_221_3p5Gsps, + .data_rate_reg_array[2][0] = datarate_221_3p5Gsps, + .data_rate_reg_array[3][0] = datarate_221_3p5Gsps, + .data_rate_reg_array[4][0] = datarate_221_3p5Gsps, + .data_rate_reg_array[5][0] = datarate_221_3p5Gsps, + .data_rate_reg_array[6][0] = datarate_221_3p5Gsps, + .data_rate_reg_array[7][0] = datarate_221_3p5Gsps, + }, + { + /* ((4.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 9120000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_4p0Gsps), + .data_rate_reg_array[0][0] = datarate_221_4p0Gsps, + .data_rate_reg_array[1][0] = datarate_221_4p0Gsps, + .data_rate_reg_array[2][0] = datarate_221_4p0Gsps, + .data_rate_reg_array[3][0] = datarate_221_4p0Gsps, + .data_rate_reg_array[4][0] = datarate_221_4p0Gsps, + .data_rate_reg_array[5][0] = datarate_221_4p0Gsps, + .data_rate_reg_array[6][0] = datarate_221_4p0Gsps, + .data_rate_reg_array[7][0] = datarate_221_4p0Gsps, + }, + { + /* ((4.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 10260000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_4p5Gsps), + .data_rate_reg_array[0][0] = datarate_221_4p5Gsps, + .data_rate_reg_array[1][0] = datarate_221_4p5Gsps, + .data_rate_reg_array[2][0] = datarate_221_4p5Gsps, + .data_rate_reg_array[3][0] = datarate_221_4p5Gsps, + .data_rate_reg_array[4][0] = datarate_221_4p5Gsps, + .data_rate_reg_array[5][0] = datarate_221_4p5Gsps, + .data_rate_reg_array[6][0] = datarate_221_4p5Gsps, + .data_rate_reg_array[7][0] = datarate_221_4p5Gsps, + }, + { + /* ((5.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 11400000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_5p0Gsps), + .data_rate_reg_array[0][0] = datarate_221_5p0Gsps, + .data_rate_reg_array[1][0] = datarate_221_5p0Gsps, + .data_rate_reg_array[2][0] = datarate_221_5p0Gsps, + .data_rate_reg_array[3][0] = datarate_221_5p0Gsps, + .data_rate_reg_array[4][0] = datarate_221_5p0Gsps, + .data_rate_reg_array[5][0] = datarate_221_5p0Gsps, + .data_rate_reg_array[6][0] = datarate_221_5p0Gsps, + .data_rate_reg_array[7][0] = datarate_221_5p0Gsps, + }, + { + /* ((5.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 12540000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_5p5Gsps), + .data_rate_reg_array[0][0] = datarate_221_5p5Gsps, + .data_rate_reg_array[1][0] = datarate_221_5p5Gsps, + .data_rate_reg_array[2][0] = datarate_221_5p5Gsps, + .data_rate_reg_array[3][0] = datarate_221_5p5Gsps, + .data_rate_reg_array[4][0] = datarate_221_5p5Gsps, + .data_rate_reg_array[5][0] = datarate_221_5p5Gsps, + .data_rate_reg_array[6][0] = datarate_221_5p5Gsps, + .data_rate_reg_array[7][0] = datarate_221_5p5Gsps, + }, + { + /* ((6.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */ + .bandwidth = 13680000000, + .data_rate_reg_array_size = ARRAY_SIZE(datarate_221_6p0Gsps), + .data_rate_reg_array[0][0] = datarate_221_6p0Gsps, + .data_rate_reg_array[1][0] = datarate_221_6p0Gsps, + .data_rate_reg_array[2][0] = datarate_221_6p0Gsps, + .data_rate_reg_array[3][0] = datarate_221_6p0Gsps, + .data_rate_reg_array[4][0] = datarate_221_6p0Gsps, + .data_rate_reg_array[5][0] = datarate_221_6p0Gsps, + .data_rate_reg_array[6][0] = datarate_221_6p0Gsps, + .data_rate_reg_array[7][0] = datarate_221_6p0Gsps, + }, +}; + +struct csiphy_reg_t bist_3ph_arr_2_2_1[] = { + {0x0230, 0x1C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0xFA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0258, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02C8, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02D0, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02D4, 0x64, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02D8, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0248, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x024C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0250, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0244, 0xB1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0240, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0630, 0x1C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0xFA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0658, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06C8, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06D0, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06D4, 0x64, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06D8, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0648, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x064C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0650, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0644, 0xB1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x065C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0640, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A30, 0x1C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A34, 0xFA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A38, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A3C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A58, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AC8, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AD0, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AD4, 0x64, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AD8, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A48, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A4C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A50, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A44, 0xB1, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A40, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t bist_status_arr_2_2_1[] = { + {0x0344, 0x00, 0x00, CSIPHY_3PH_REGS}, + {0x0744, 0x00, 0x00, CSIPHY_3PH_REGS}, + {0x0B44, 0x00, 0x00, CSIPHY_3PH_REGS}, + {0x00C0, 0x00, 0x00, CSIPHY_2PH_REGS}, + {0x04C0, 0x00, 0x00, CSIPHY_2PH_REGS}, + {0x08C0, 0x00, 0x00, CSIPHY_2PH_REGS}, + {0x0CC0, 0x00, 0x00, CSIPHY_2PH_REGS}, +}; + +struct bist_reg_settings_t bist_setting_2_2_1 = { + .error_status_val_3ph = 0x10, + .error_status_val_2ph = 0x10, + .set_status_update_3ph_base_offset = 0x0240, + .set_status_update_2ph_base_offset = 0x0050, + .bist_status_3ph_base_offset = 0x0344, + .bist_status_2ph_base_offset = 0x00C0, + .bist_sensor_data_3ph_status_base_offset = 0x0340, + .bist_counter_3ph_base_offset = 0x0348, + .bist_counter_2ph_base_offset = 0x00C8, + .number_of_counters = 2, + .num_3ph_bist_settings = ARRAY_SIZE(bist_3ph_arr_2_2_1), + .bist_3ph_settings_arry = bist_3ph_arr_2_2_1, + .bist_2ph_settings_arry = NULL, + .num_2ph_bist_settings = 0, + .num_status_reg = ARRAY_SIZE(bist_status_arr_2_2_1), + .bist_status_arr = bist_status_arr_2_2_1, +}; + +struct data_rate_settings_t data_rate_delta_table_2_2_1 = { + .num_data_rate_settings = ARRAY_SIZE(data_rate_settings_2_2_1), + .data_rate_settings = data_rate_settings_2_2_1, +}; + +struct csiphy_reg_parms_t csiphy_v2_2_1 = { + .mipi_csiphy_interrupt_status0_addr = 0x10B0, + .mipi_csiphy_interrupt_clear0_addr = 0x1058, + .mipi_csiphy_glbl_irq_cmd_addr = 0x1028, + .size_offset_betn_lanes = 0x400, + .status_reg_params = &status_regs_2_2_1, + .csiphy_common_reg_array_size = ARRAY_SIZE(csiphy_common_reg_2_2_1), + .csiphy_reset_enter_array_size = ARRAY_SIZE(csiphy_reset_enter_reg_2_2_1), + .csiphy_reset_exit_array_size = ARRAY_SIZE(csiphy_reset_exit_reg_2_2_1), + .csiphy_2ph_config_array_size = ARRAY_SIZE(csiphy_2ph_v2_2_1_reg), + .csiphy_3ph_config_array_size = ARRAY_SIZE(csiphy_3ph_v2_2_1_reg), + .csiphy_2ph_combo_config_array_size = ARRAY_SIZE(csiphy_2ph_v2_2_1_combo_mode_reg), + .csiphy_3ph_combo_config_array_size = 0, + .csiphy_2ph_3ph_config_array_size = 0, + .csiphy_interrupt_status_size = ARRAY_SIZE(csiphy_irq_reg_2_2_1), + .csiphy_num_common_status_regs = 20, + .aon_sel_params = &aon_cam_select_params_2_2_1, +}; + +struct csiphy_ctrl_t ctrl_reg_2_2_1 = { + .csiphy_common_reg = csiphy_common_reg_2_2_1, + .csiphy_2ph_reg = csiphy_2ph_v2_2_1_reg, + .csiphy_3ph_reg = csiphy_3ph_v2_2_1_reg, + .csiphy_2ph_combo_mode_reg = csiphy_2ph_v2_2_1_combo_mode_reg, + .csiphy_3ph_combo_reg = NULL, + .csiphy_2ph_3ph_mode_reg = NULL, + .csiphy_reg = &csiphy_v2_2_1, + .csiphy_irq_reg = csiphy_irq_reg_2_2_1, + .csiphy_reset_enter_regs = csiphy_reset_enter_reg_2_2_1, + .csiphy_reset_exit_regs = csiphy_reset_exit_reg_2_2_1, + .csiphy_lane_config_reg = csiphy_lane_en_reg_2_2_1, + .data_rates_settings_table = &data_rate_delta_table_2_2_1, + .csiphy_bist_reg = &bist_setting_2_2_1, + .getclockvoting = get_clk_voting_dynamic, +}; + +#endif /* _CAM_CSIPHY_2_2_1_HWREG_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index ba243042d3..f12387c30e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -54,7 +54,7 @@ static int cam_eeprom_read_memory(struct cam_eeprom_ctrl_t *e_ctrl, eb_info->i2c_info.slave_addr = emap[j].saddr; rc = cam_eeprom_update_i2c_info(e_ctrl, &eb_info->i2c_info); - if (rc < 0) { + if (rc) { CAM_ERR(CAM_EEPROM, "failed: to update i2c info rc %d", rc); @@ -72,7 +72,7 @@ static int cam_eeprom_read_memory(struct cam_eeprom_ctrl_t *e_ctrl, i2c_reg_settings.reg_setting = &i2c_reg_array; rc = camera_io_dev_write(&e_ctrl->io_master_info, &i2c_reg_settings); - if (rc < 0) { + if (rc) { CAM_ERR(CAM_EEPROM, "page write failed rc %d", rc); return rc; @@ -89,7 +89,7 @@ static int cam_eeprom_read_memory(struct cam_eeprom_ctrl_t *e_ctrl, i2c_reg_settings.reg_setting = &i2c_reg_array; rc = camera_io_dev_write(&e_ctrl->io_master_info, &i2c_reg_settings); - if (rc < 0) { + if (rc) { CAM_ERR(CAM_EEPROM, "page enable failed rc %d", rc); return rc; @@ -102,7 +102,7 @@ static int cam_eeprom_read_memory(struct cam_eeprom_ctrl_t *e_ctrl, 0, emap[j].poll.addr_type, emap[j].poll.data_type, emap[j].poll.delay); - if (rc < 0) { + if (rc) { CAM_ERR(CAM_EEPROM, "poll failed rc %d", rc); return rc; @@ -174,7 +174,7 @@ static int cam_eeprom_read_memory(struct cam_eeprom_ctrl_t *e_ctrl, i2c_reg_settings.reg_setting = &i2c_reg_array; rc = camera_io_dev_write(&e_ctrl->io_master_info, &i2c_reg_settings); - if (rc < 0) { + if (rc) { CAM_ERR(CAM_EEPROM, "page disable failed rc %d", rc); @@ -522,6 +522,7 @@ static int32_t cam_eeprom_parse_memory_map( int32_t rc = 0; int32_t cnt = 0; int32_t processed_size = 0; + int32_t payload_count; uint8_t generic_op_code; struct cam_eeprom_memory_map_t *map = data->map; struct common_header *cmm_hdr = @@ -551,24 +552,25 @@ static int32_t cam_eeprom_parse_memory_map( switch (cmm_hdr->cmd_type) { case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR: i2c_random_wr = (struct cam_cmd_i2c_random_wr *)cmd_buf; + payload_count = i2c_random_wr->header.count; - if (i2c_random_wr->header.count == 0 || - i2c_random_wr->header.count >= MSM_EEPROM_MAX_MEM_MAP_CNT || + if (payload_count == 0 || + payload_count >= MSM_EEPROM_MAX_MEM_MAP_CNT || (size_t)*num_map >= ((MSM_EEPROM_MAX_MEM_MAP_CNT * MSM_EEPROM_MEMORY_MAP_MAX_SIZE) - - i2c_random_wr->header.count)) { + payload_count)) { CAM_ERR(CAM_EEPROM, "OOB Error"); return -EINVAL; } cmd_length_in_bytes = sizeof(struct cam_cmd_i2c_random_wr) + - ((i2c_random_wr->header.count - 1) * + ((payload_count - 1) * sizeof(struct i2c_random_wr_payload)); if (cmd_length_in_bytes > remain_buf_len) { CAM_ERR(CAM_EEPROM, "Not enough buffer remaining"); return -EINVAL; } - for (cnt = 0; cnt < (i2c_random_wr->header.count); + for (cnt = 0; cnt < (payload_count); cnt++) { map[*num_map + cnt].page.addr = i2c_random_wr->random_wr_payload[cnt].reg_addr; @@ -581,15 +583,16 @@ static int32_t cam_eeprom_parse_memory_map( map[*num_map + cnt].page.valid_size = 1; } - *num_map += (i2c_random_wr->header.count - 1); + *num_map += (payload_count - 1); processed_size += cmd_length_in_bytes; break; case CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD: i2c_cont_rd = (struct cam_cmd_i2c_continuous_rd *)cmd_buf; cmd_length_in_bytes = sizeof(struct cam_cmd_i2c_continuous_rd); + payload_count = i2c_cont_rd->header.count; - if (i2c_cont_rd->header.count >= U32_MAX - data->num_data) { + if (payload_count >= U32_MAX - data->num_data) { CAM_ERR(CAM_EEPROM, "int overflow on eeprom memory block"); return -EINVAL; @@ -598,7 +601,7 @@ static int32_t cam_eeprom_parse_memory_map( map[*num_map].mem.addr_type = i2c_cont_rd->header.addr_type; map[*num_map].mem.data_type = i2c_cont_rd->header.data_type; map[*num_map].mem.valid_size = - i2c_cont_rd->header.count; + payload_count; processed_size += cmd_length_in_bytes; data->num_data += map[*num_map].mem.valid_size; @@ -1184,6 +1187,8 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, { struct cam_buf_io_cfg *io_cfg; uint32_t i = 0; + size_t plane_offset; + int32_t mem_handle; int rc = 0; uintptr_t buf_addr; size_t buf_size; @@ -1193,6 +1198,8 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) &csl_packet->payload + csl_packet->io_configs_offset); + plane_offset = io_cfg->offsets[0]; + mem_handle = io_cfg->mem_handle[0]; CAM_DBG(CAM_EEPROM, "number of IO configs: %d:", csl_packet->num_io_configs); @@ -1200,21 +1207,21 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, for (i = 0; i < csl_packet->num_io_configs; i++) { CAM_DBG(CAM_EEPROM, "Direction: %d:", io_cfg->direction); if (io_cfg->direction == CAM_BUF_OUTPUT) { - rc = cam_mem_get_cpu_buf(io_cfg->mem_handle[0], + rc = cam_mem_get_cpu_buf(mem_handle, &buf_addr, &buf_size); if (rc) { CAM_ERR(CAM_EEPROM, "Fail in get buffer: %d", rc); return rc; } - if (buf_size <= io_cfg->offsets[0]) { + if (buf_size <= plane_offset) { CAM_ERR(CAM_EEPROM, "Not enough buffer"); - cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); + cam_mem_put_cpu_buf(mem_handle); rc = -EINVAL; return rc; } - remain_len = buf_size - io_cfg->offsets[0]; + remain_len = buf_size - plane_offset; CAM_DBG(CAM_EEPROM, "buf_addr : %pK, buf_size : %zu\n", (void *)buf_addr, buf_size); @@ -1222,16 +1229,16 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, if (!read_buffer) { CAM_ERR(CAM_EEPROM, "invalid buffer to copy data"); - cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); + cam_mem_put_cpu_buf(mem_handle); rc = -EINVAL; return rc; } - read_buffer += io_cfg->offsets[0]; + read_buffer += plane_offset; if (remain_len < e_ctrl->cal_data.num_data) { CAM_ERR(CAM_EEPROM, "failed to copy, Invalid size"); - cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); + cam_mem_put_cpu_buf(mem_handle); rc = -EINVAL; return rc; } @@ -1240,7 +1247,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, e_ctrl->cal_data.num_data); memcpy(read_buffer, e_ctrl->cal_data.mapdata, e_ctrl->cal_data.num_data); - cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); + cam_mem_put_cpu_buf(mem_handle); } else { CAM_ERR(CAM_EEPROM, "Invalid direction"); rc = -EINVAL; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi1337_otp.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi1337_otp.h index 6b9167c6a3..6f5b5ac807 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi1337_otp.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi1337_otp.h @@ -1642,4 +1642,4 @@ struct cam_sensor_i2c_reg_array hi1337_otp_finish_reg2[] = { {0x0B00, 0x01, 0}, }; -#endif /* HI1337_OTP_H */ \ No newline at end of file +#endif /* HI1337_OTP_H */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi847_otp.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi847_otp.h index ac8d9c5033..e96051dbcf 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi847_otp.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_eeprom/hi847_otp.h @@ -274,4 +274,4 @@ struct cam_sensor_i2c_reg_array hi847_otp_finish_reg2[] = { {0x0B00, 0x01, 0}, }; -#endif /* HI847_OTP_H */ \ No newline at end of file +#endif /* HI847_OTP_H */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index b54e31a791..fbe08b7180 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -941,8 +941,7 @@ int cam_flash_pmic_apply_setting(struct cam_flash_ctrl *fctrl, goto apply_setting_err; } } - } - else if ((flash_data->opcode == + } else if ((flash_data->opcode == CAMERA_SENSOR_FLASH_OP_FIRELOW) && (flash_data->cmn_attr.is_settings_valid) && (flash_data->cmn_attr.request_id == req_id)) { @@ -1602,6 +1601,8 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_WARN(CAM_FLASH, "Rxed Flash fire ops without linking"); flash_data->cmn_attr.is_settings_valid = false; + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } if (remain_len < sizeof(struct cam_flash_set_on_off)) { diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c index dbf5fb395d..4ded348daf 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -310,6 +310,10 @@ static long cam_flash_subdev_ioctl(struct v4l2_subdev *sd, CAM_DBG(CAM_FLASH, "Enter"); fctrl = v4l2_get_subdevdata(sd); + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Flash ctrl ptr is NULL"); + return -EINVAL; + } soc_private = fctrl->soc_info.soc_private; switch (cmd) { diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h index 8720623f09..f536a1e043 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_FLASH_DEV_H_ @@ -19,9 +20,10 @@ #include #include -#if IS_REACHABLE(CONFIG_LEDS_QPNP_FLASH_V2) +#if IS_REACHABLE(CONFIG_LEDS_QPNP_FLASH_V2) || IS_REACHABLE(CONFIG_BACKLIGHT_QCOM_SPMI_WLED) #include -#elif IS_REACHABLE(CONFIG_LEDS_QTI_FLASH) +#endif +#if IS_REACHABLE(CONFIG_LEDS_QTI_FLASH) #include #endif diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index d60510ed6d..4c3db6c6ac 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -1655,9 +1655,8 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) i2c_reg_settings, &cmd_desc[i], 1, NULL); if (rc < 0) { - CAM_ERR(CAM_OIS, + CAM_DBG(CAM_OIS, "fw init parsing failed: %d", rc); - return rc; } } #endif @@ -1904,14 +1903,15 @@ struct i2c_settings_list *i2c_list; CAM_WARN(CAM_OIS, "Not in right state to read OIS: %d", o_ctrl->cam_ois_state); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } CAM_DBG(CAM_OIS, "number of I/O configs: %d:", csl_packet->num_io_configs); if (csl_packet->num_io_configs == 0) { CAM_ERR(CAM_OIS, "No I/O configs to process"); - cam_mem_put_cpu_buf(dev_config.packet_handle); rc = -EINVAL; + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -1924,8 +1924,8 @@ struct i2c_settings_list *i2c_list; /* validate read data io config */ if (io_cfg == NULL) { CAM_ERR(CAM_OIS, "I/O config is invalid(NULL)"); - cam_mem_put_cpu_buf(dev_config.packet_handle); rc = -EINVAL; + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -1945,7 +1945,7 @@ struct i2c_settings_list *i2c_list; rc = cam_sensor_util_get_current_qtimer_ns(&qtime_ns); if (rc < 0) { - CAM_ERR(CAM_OIS, "failed to get qtimer rc:%d", rc); + CAM_ERR(CAM_OIS, "failed to get qtimer rc:%d"); #if !defined(CONFIG_SAMSUNG_OIS_MCU_STM32) cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; @@ -2481,7 +2481,6 @@ int cam_ois_driver_cmd(struct cam_ois_ctrl_t *o_ctrl, void *arg) } if (o_ctrl->cam_ois_state != CAM_OIS_START) { - rc = 0; rc = -EINVAL; CAM_WARN(CAM_OIS, "Not in right state for stop : %d", diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c index 66c8519700..32e6357341 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c @@ -159,14 +159,7 @@ int cam_res_mgr_util_get_idx_from_shared_pctrl_gpio( uint gpio) { int index = 0; - struct cam_res_mgr_dt *dt = NULL; - - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return -EINVAL; - } - - dt = &cam_res->dt; + struct cam_res_mgr_dt *dt = &cam_res->dt; for (index = 0; index < dt->num_shared_pctrl_gpio; index++) { if (gpio == dt->shared_pctrl_gpio[index]) @@ -184,14 +177,7 @@ int cam_res_mgr_util_get_idx_from_shared_gpio( uint gpio) { int index = 0; - struct cam_res_mgr_dt *dt = NULL; - - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return -EINVAL; - } - - dt = &cam_res->dt; + struct cam_res_mgr_dt *dt = &cam_res->dt; for (index = 0; index < dt->num_shared_gpio; index++) { if (gpio == dt->shared_gpio[index]) @@ -210,14 +196,7 @@ static bool cam_res_mgr_gpio_is_in_shared_pctrl_gpio( { int index = 0; bool found = false; - struct cam_res_mgr_dt *dt = NULL; - - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return false; - } - - dt = &cam_res->dt; + struct cam_res_mgr_dt *dt = &cam_res->dt; for (index = 0; index < dt->num_shared_pctrl_gpio; index++) { if (gpio == dt->shared_pctrl_gpio[index]) { @@ -234,14 +213,7 @@ static bool cam_res_mgr_gpio_is_in_shared_gpio( { int index = 0; bool found = false; - struct cam_res_mgr_dt *dt = NULL; - - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return false; - } - - dt = &cam_res->dt; + struct cam_res_mgr_dt *dt = &cam_res->dt; for (; index < dt->num_shared_gpio; index++) { if (gpio == dt->shared_gpio[index]) { @@ -431,11 +403,6 @@ static struct cam_gpio_res *cam_res_mgr_find_if_gpio_in_list(uint gpio) { struct cam_gpio_res *gpio_res = NULL; - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return NULL; - } - list_for_each_entry(gpio_res, &cam_res->gpio_res_list, list) { if (gpio == gpio_res->gpio) return gpio_res; @@ -476,11 +443,6 @@ int cam_res_mgr_gpio_request(struct device *dev, uint gpio, int pctrl_idx = -1; struct cam_gpio_res *gpio_res = NULL; - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return -EINVAL; - } - mutex_lock(&cam_res->gpio_res_lock); if (cam_res && cam_res->shared_gpio_enabled) { gpio_res = cam_res_mgr_find_if_gpio_in_list(gpio); @@ -619,11 +581,6 @@ static void cam_res_mgr_gpio_free(struct device *dev, uint gpio) bool is_shared_pctrl_gpio = false; int pctrl_idx = -1; - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return; - } - is_shared_pctrl_gpio = cam_res_mgr_gpio_is_in_shared_pctrl_gpio(gpio); @@ -676,13 +633,13 @@ static void cam_res_mgr_gpio_free(struct device *dev, uint gpio) pctrl_idx = cam_res_mgr_util_get_idx_from_shared_pctrl_gpio( gpio); - if (pctrl_idx >= 0) { - cam_res_mgr_shared_pinctrl_select_state( - pctrl_idx, false); - } - else { - CAM_ERR(CAM_RES, "Invalid PinCtrl Idx: %d", pctrl_idx); - } + if (pctrl_idx >= 0) { + cam_res_mgr_shared_pinctrl_select_state( + pctrl_idx, false); + } + else { + CAM_ERR(CAM_RES, "Invalid PinCtrl Idx: %d", pctrl_idx); + } } CAM_DBG(CAM_RES, "freeing gpio: %u", gpio); @@ -706,11 +663,6 @@ int cam_res_mgr_gpio_set_value(unsigned int gpio, int value) bool found = false; struct cam_gpio_res *gpio_res = NULL; - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return -EINVAL; - } - mutex_lock(&cam_res->gpio_res_lock); if (cam_res && cam_res->shared_gpio_enabled) { list_for_each_entry(gpio_res, &cam_res->gpio_res_list, list) { @@ -756,14 +708,7 @@ static int cam_res_mgr_shared_pinctrl_init( int i = 0; char pctrl_active[50]; char pctrl_suspend[50]; - struct cam_res_mgr_dt *dt = NULL; - - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return -EINVAL; - } - - dt = &cam_res->dt; + struct cam_res_mgr_dt *dt = &cam_res->dt; cam_res->pinctrl = devm_pinctrl_get(dev); if (IS_ERR_OR_NULL(cam_res->pinctrl)) { @@ -813,14 +758,7 @@ static int cam_res_mgr_parse_dt_shared_gpio( { int rc = 0; struct device_node *of_node = NULL; - struct cam_res_mgr_dt *dt = NULL; - - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return -EINVAL; - } - - dt = &cam_res->dt; + struct cam_res_mgr_dt *dt = &cam_res->dt; of_node = dev->of_node; dt->num_shared_gpio = of_property_count_u32_elems(of_node, @@ -856,14 +794,7 @@ static int cam_res_mgr_parse_dt_shared_pinctrl_gpio( int rc = 0, i = 0; int pinctrl_name_nodes = 0; struct device_node *of_node = NULL; - struct cam_res_mgr_dt *dt = NULL; - - if (!cam_res) { - CAM_DBG(CAM_RES, "cam_res data is not avaialbe"); - return -EINVAL; - } - - dt = &cam_res->dt; + struct cam_res_mgr_dt *dt = &cam_res->dt; of_node = dev->of_node; dt->num_shared_pctrl_gpio = of_property_count_u32_elems(of_node, diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx258.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx258.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx374.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx374.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx374_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx374_2_0.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx471.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx471.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx471_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx471_2_0.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx564.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx564.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx596_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx596_2_0.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx754.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx754.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx854_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_imx854_2_0.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k2ld.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k2ld.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1.h old mode 100644 new mode 100755 index ecbad785e1..c88f4ea23e --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1.h @@ -1,623 +1,623 @@ -/* Copyright (c) 2017, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_H_ -#define _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_H_ - -#include "cam_sensor_dev.h" - -int num_front_mipi_setting = 2; - -/* -SET A : Other -SET B : M3 4k 60fps -*/ - -/*************************************/ -/* ========== Mode A =============== */ -/*************************************/ - -enum { - CAM_S5K3J1_SET_A_all_992_MHZ = 0, - CAM_S5K3J1_SET_A_all_995_MHZ = 1, - CAM_S5K3J1_SET_A_all_956_MHZ = 2, - CAM_S5K3J1_SET_A_all_950_MHZ = 3 -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_992_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0136, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_995_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0137, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_956_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x012B, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_950_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0129, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_992_mhz[] = { - { MIPI_ALL_992_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_992_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_995_mhz[] = { - { MIPI_ALL_995_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_995_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_956_mhz[] = { - { MIPI_ALL_956_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_956_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_950_mhz[] = { - { MIPI_ALL_950_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_950_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_mipi_setting sensor_s5k3j1_setfile_A_mipi_setting_ALL[] = { - { "992 Mhz", - sensor_s5k3j1_setfile_A_mipi_all_992_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_992_mhz) }, - { "995 Mhz", - sensor_s5k3j1_setfile_A_mipi_all_995_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_995_mhz) }, - { "956 Mhz", - sensor_s5k3j1_setfile_A_mipi_all_956_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_956_mhz) }, - { "950 Mhz", - sensor_s5k3j1_setfile_A_mipi_all_950_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_950_mhz) }, -}; - -static const struct cam_mipi_channel sensor_s5k3j1_setfile_A_mipi_channel_ALL[] = { - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10654, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10655, 10726, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10727, 10729, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10730, 10838, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9665, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9666, 9704, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9705, 9709, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9710, 9740, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9741, 9759, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9760, 9769, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9770, 9779, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9780, 9938, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1293, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1294, 1338, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1339, 1368, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1369, 1423, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1424, 1462, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1463, 1492, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1493, 1513, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1629, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1630, 1701, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1702, 1704, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1705, 1738, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4377, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4378, 4391, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4392, 4440, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4441, 4458, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4387, 4391, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4392, 4413, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2273, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2274, 2306, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2307, 2348, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2349, 2522, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2523, 2554, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2555, 2563, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 2989, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2990, 3048, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3049, 3064, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3065, 3088, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 712, 716, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 717, 763, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 208, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 209, 352, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 353, 358, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 359, 599, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 631, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 632, 708, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 709, 718, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 719, 781, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 782, 819, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 820, 839, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 840, 858, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 859, 1183, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1184, 1199, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1486, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1487, 1576, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1577, 1636, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1637, 1746, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1747, 1824, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1825, 1884, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1885, 1949, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 2158, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2159, 2302, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2303, 2308, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2309, 2399, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2464, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2465, 2492, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2493, 2591, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2592, 2649, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2847, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2848, 2912, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2913, 2997, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2998, 3345, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3346, 3408, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3409, 3449, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3579, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3580, 3695, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3696, 3729, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3730, 3799, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5108, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5109, 5179, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5234, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5235, 5258, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5259, 5279, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5379, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5778, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5779, 5849, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5882, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5883, 5936, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5937, 5999, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6004, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6005, 6032, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6033, 6131, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6132, 6149, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6250, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6251, 6276, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6277, 6449, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6493, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6494, 6599, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8071, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8072, 8148, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8149, 8158, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8159, 8221, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8222, 8259, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8260, 8279, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8280, 8298, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8299, 8623, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8624, 8689, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 8732, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8733, 8786, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8787, 8854, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8855, 8882, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8883, 8981, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8982, 9039, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9516, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9517, 9640, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9641, 9659, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9769, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9869, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 9927, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9928, 10204, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10205, 10252, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10253, 10305, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10306, 10354, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10355, 10359, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36221, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36222, 36267, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36268, 36349, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37850, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37851, 37916, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37917, 38000, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38001, 38098, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38099, 38164, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38165, 38248, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38249, 38249, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38283, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38284, 38372, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38373, 38433, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38434, 38649, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38859, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38860, 39009, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39010, 39334, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39335, 39494, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39495, 39644, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39645, 39649, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39992, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39993, 40060, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40061, 40142, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40143, 40490, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40491, 40556, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40557, 40640, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40641, 40738, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40739, 40804, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40805, 40888, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40889, 40987, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40988, 41052, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41053, 41137, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41138, 41485, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41486, 41548, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41549, 41589, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41739, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41740, 41849, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41850, 41889, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41890, 42235, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42236, 42348, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42349, 42385, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42386, 42497, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42498, 42844, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42845, 42881, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42882, 42994, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42995, 43342, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43343, 43377, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43378, 43475, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43476, 43492, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43493, 43589, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55492, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55493, 55527, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55528, 55625, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55626, 55642, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55643, 55741, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55742, 55775, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55776, 55873, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55874, 55891, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55892, 55989, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55990, 56023, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56024, 56139, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56140, 56487, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56488, 56510, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56511, 56637, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56638, 56739, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66644, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66645, 66788, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66789, 66794, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66795, 67120, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67121, 67267, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67268, 67270, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67271, 67335, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68690, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68691, 68710, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68711, 68809, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68810, 68935, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 174620, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 174621, 175980, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 175981, 176140, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176141, 176540, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176541, 176720, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176721, 178780, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 186680, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 186681, 189900, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189901, 191480, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 191481, 191980, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 146860, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 146861, 149200, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 160670, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160671, 161620, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 161621, 164180, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151660, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151661, 156820, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 156821, 160580, CAM_S5K3J1_SET_A_all_956_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 126380, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126381, 126540, CAM_S5K3J1_SET_A_all_992_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126541, 126780, CAM_S5K3J1_SET_A_all_950_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126781, 126960, CAM_S5K3J1_SET_A_all_995_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126961, 130380, CAM_S5K3J1_SET_A_all_956_MHZ }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_A_mode[] = { - { - sensor_s5k3j1_setfile_A_mipi_channel_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_channel_ALL), - sensor_s5k3j1_setfile_A_mipi_setting_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_setting_ALL) - }, -}; - -/*************************************/ -/* ========== Mode B =============== */ -/*************************************/ - -enum { - CAM_S5K3J1_SET_B_all_1196_MHZ = 0, - CAM_S5K3J1_SET_B_all_1011_MHZ = 1, - CAM_S5K3J1_SET_B_all_1139_MHZ = 2, - CAM_S5K3J1_SET_B_all_1094_MHZ = 3 -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_1196_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x00BB, 0x00, 0x00}, - {0x0312, 0x0000, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_1011_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x013C, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_1139_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x00B2, 0x00, 0x00}, - {0x0312, 0x0000, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_ALL_1094_MHZ_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0156, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1196_mhz[] = { - { MIPI_ALL_1196_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1196_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1011_mhz[] = { - { MIPI_ALL_1011_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1011_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1139_mhz[] = { - { MIPI_ALL_1139_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1139_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1094_mhz[] = { - { MIPI_ALL_1094_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1094_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_mipi_setting sensor_s5k3j1_setfile_B_mipi_setting_ALL[] = { - { "1196 Mhz", - sensor_s5k3j1_setfile_B_mipi_all_1196_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1196_mhz) }, - { "1011 Mhz", - sensor_s5k3j1_setfile_B_mipi_all_1011_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1011_mhz) }, - { "1139 Mhz", - sensor_s5k3j1_setfile_B_mipi_all_1139_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1139_mhz) }, - { "1094 Mhz", - sensor_s5k3j1_setfile_B_mipi_all_1094_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1094_mhz) }, -}; - -static const struct cam_mipi_channel sensor_s5k3j1_setfile_B_mipi_channel_ALL[] = { - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10733, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10734, 10781, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10782, 10808, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10809, 10838, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9686, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9687, 9761, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9762, 9836, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9837, 9896, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9897, 9911, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9912, 9938, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1362, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1363, 1437, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1438, 1513, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1708, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1709, 1738, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4450, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4451, 4458, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2258, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2259, 2308, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2309, 2327, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2328, 2551, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2552, 2560, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2561, 2563, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 3049, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3050, 3065, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3066, 3088, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 367, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 368, 462, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 463, 517, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 518, 599, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 672, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 673, 822, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 823, 972, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 973, 1093, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1094, 1122, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1123, 1199, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1625, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1626, 1775, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1776, 1949, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 2317, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2318, 2399, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2610, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2611, 2632, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2633, 2649, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2815, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2816, 2916, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2917, 2954, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2955, 3402, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3403, 3421, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3422, 3449, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3699, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3700, 3731, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3732, 3799, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5124, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5125, 5179, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5228, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5229, 5274, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5275, 5279, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5379, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5794, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5795, 5849, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5999, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6149, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6449, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6525, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6526, 6599, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8112, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8113, 8262, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8263, 8412, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8413, 8533, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8534, 8562, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8563, 8689, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 9000, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 9001, 9022, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 9023, 9039, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9334, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9335, 9484, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9485, 9659, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9745, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9746, 9769, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9869, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 10284, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10285, 10359, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36349, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37760, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37761, 37856, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37857, 38249, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38523, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38524, 38587, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38588, 38649, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38912, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38913, 38954, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38955, 38982, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38983, 39062, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39063, 39510, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39511, 39590, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39591, 39648, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39649, 39649, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39747, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39748, 39894, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39895, 39897, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39898, 40046, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40047, 40196, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40197, 40346, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40347, 40400, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40401, 40496, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40497, 40955, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40956, 41056, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41057, 41094, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41095, 41542, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41543, 41561, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41562, 41589, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41623, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41624, 41643, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41644, 41691, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41692, 41744, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41745, 41923, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41924, 42045, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42046, 42073, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42074, 42222, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42223, 42372, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42373, 42820, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42821, 42907, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42908, 42970, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42971, 43419, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43420, 43549, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43550, 43562, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43563, 43569, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43570, 43589, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55569, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55570, 55699, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55700, 55712, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55713, 55719, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55720, 56167, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56168, 56218, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56219, 56317, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56318, 56739, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66803, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66804, 66898, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66899, 66953, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66954, 67335, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68923, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68924, 68935, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, CAM_S5K3J1_SET_B_all_1011_MHZ }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 177100, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 177101, 178780, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 189080, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189081, 191980, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 146000, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 146001, 147180, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 147181, 149200, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 164180, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151980, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151981, 153180, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 153181, 157080, CAM_S5K3J1_SET_B_all_1139_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157081, 157980, CAM_S5K3J1_SET_B_all_1094_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157981, 160580, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 129240, CAM_S5K3J1_SET_B_all_1196_MHZ }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 129241, 130380, CAM_S5K3J1_SET_B_all_1139_MHZ }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_B_mode[] = { - { - sensor_s5k3j1_setfile_B_mipi_channel_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_channel_ALL), - sensor_s5k3j1_setfile_B_mipi_setting_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_setting_ALL) - }, -}; - -/*************************************/ -/* ========== DUMMY ================ */ -/*************************************/ -enum { - CAM_FRONT_SET_DUMMY_MHZ = 0, -}; - -struct cam_sensor_i2c_reg_array MIPI_FRONT_DUMMY_MHZ_REG_ARRAY[] = { -}; - -static const struct cam_sensor_i2c_reg_setting sensor_front_setfile_dummy_mhz[] = { - { MIPI_FRONT_DUMMY_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_FRONT_DUMMY_MHZ_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_mipi_setting sensor_front_setfile_dummy_mipi_setting[] = { - { "DUMMY Mhz", - sensor_front_setfile_dummy_mhz, ARRAY_SIZE(sensor_front_setfile_dummy_mhz) }, -}; - -static const struct cam_mipi_channel sensor_front_setfile_dummy_channel[] = { - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, CAM_FRONT_SET_DUMMY_MHZ }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_C_mode[] = { - { - sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), - sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) - }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_D_mode[] = { - { - sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), - sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) - }, -}; - -#endif /* _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_H_ */ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_H_ +#define _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_H_ + +#include "cam_sensor_dev.h" + +int num_front_mipi_setting = 2; + +/* +SET A : Other +SET B : M3 4k 60fps +*/ + +/*************************************/ +/* ========== Mode A =============== */ +/*************************************/ + +enum { + CAM_S5K3J1_SET_A_all_992_MHZ = 0, + CAM_S5K3J1_SET_A_all_995_MHZ = 1, + CAM_S5K3J1_SET_A_all_956_MHZ = 2, + CAM_S5K3J1_SET_A_all_950_MHZ = 3 +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_992_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0136, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_995_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0137, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_956_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x012B, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_950_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0129, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_992_mhz[] = { + { MIPI_ALL_992_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_992_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_995_mhz[] = { + { MIPI_ALL_995_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_995_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_956_mhz[] = { + { MIPI_ALL_956_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_956_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_all_950_mhz[] = { + { MIPI_ALL_950_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_950_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_mipi_setting sensor_s5k3j1_setfile_A_mipi_setting_ALL[] = { + { "992 Mhz", + sensor_s5k3j1_setfile_A_mipi_all_992_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_992_mhz) }, + { "995 Mhz", + sensor_s5k3j1_setfile_A_mipi_all_995_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_995_mhz) }, + { "956 Mhz", + sensor_s5k3j1_setfile_A_mipi_all_956_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_956_mhz) }, + { "950 Mhz", + sensor_s5k3j1_setfile_A_mipi_all_950_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_all_950_mhz) }, +}; + +static const struct cam_mipi_channel sensor_s5k3j1_setfile_A_mipi_channel_ALL[] = { + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10654, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10655, 10726, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10727, 10729, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10730, 10838, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9665, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9666, 9704, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9705, 9709, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9710, 9740, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9741, 9759, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9760, 9769, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9770, 9779, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9780, 9938, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1293, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1294, 1338, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1339, 1368, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1369, 1423, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1424, 1462, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1463, 1492, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1493, 1513, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1629, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1630, 1701, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1702, 1704, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1705, 1738, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4377, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4378, 4391, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4392, 4440, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4441, 4458, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4387, 4391, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4392, 4413, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2273, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2274, 2306, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2307, 2348, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2349, 2522, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2523, 2554, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2555, 2563, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 2989, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2990, 3048, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3049, 3064, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3065, 3088, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 712, 716, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 717, 763, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 208, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 209, 352, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 353, 358, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 359, 599, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 631, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 632, 708, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 709, 718, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 719, 781, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 782, 819, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 820, 839, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 840, 858, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 859, 1183, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1184, 1199, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1486, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1487, 1576, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1577, 1636, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1637, 1746, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1747, 1824, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1825, 1884, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1885, 1949, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 2158, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2159, 2302, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2303, 2308, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2309, 2399, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2464, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2465, 2492, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2493, 2591, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2592, 2649, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2847, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2848, 2912, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2913, 2997, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2998, 3345, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3346, 3408, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3409, 3449, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3579, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3580, 3695, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3696, 3729, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3730, 3799, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5108, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5109, 5179, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5234, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5235, 5258, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5259, 5279, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5379, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5778, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5779, 5849, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5882, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5883, 5936, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5937, 5999, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6004, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6005, 6032, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6033, 6131, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6132, 6149, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6250, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6251, 6276, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6277, 6449, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6493, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6494, 6599, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8071, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8072, 8148, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8149, 8158, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8159, 8221, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8222, 8259, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8260, 8279, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8280, 8298, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8299, 8623, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8624, 8689, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 8732, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8733, 8786, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8787, 8854, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8855, 8882, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8883, 8981, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8982, 9039, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9516, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9517, 9640, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9641, 9659, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9769, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9869, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 9927, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9928, 10204, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10205, 10252, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10253, 10305, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10306, 10354, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10355, 10359, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36221, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36222, 36267, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36268, 36349, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37850, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37851, 37916, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37917, 38000, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38001, 38098, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38099, 38164, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38165, 38248, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38249, 38249, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38283, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38284, 38372, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38373, 38433, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38434, 38649, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38859, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38860, 39009, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39010, 39334, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39335, 39494, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39495, 39644, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39645, 39649, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39992, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39993, 40060, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40061, 40142, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40143, 40490, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40491, 40556, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40557, 40640, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40641, 40738, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40739, 40804, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40805, 40888, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40889, 40987, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40988, 41052, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41053, 41137, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41138, 41485, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41486, 41548, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41549, 41589, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41739, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41740, 41849, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41850, 41889, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41890, 42235, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42236, 42348, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42349, 42385, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42386, 42497, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42498, 42844, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42845, 42881, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42882, 42994, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42995, 43342, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43343, 43377, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43378, 43475, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43476, 43492, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43493, 43589, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55492, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55493, 55527, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55528, 55625, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55626, 55642, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55643, 55741, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55742, 55775, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55776, 55873, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55874, 55891, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55892, 55989, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55990, 56023, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56024, 56139, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56140, 56487, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56488, 56510, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56511, 56637, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56638, 56739, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66644, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66645, 66788, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66789, 66794, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66795, 67120, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67121, 67267, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67268, 67270, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67271, 67335, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68690, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68691, 68710, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68711, 68809, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68810, 68935, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 174620, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 174621, 175980, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 175981, 176140, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176141, 176540, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176541, 176720, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176721, 178780, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 186680, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 186681, 189900, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189901, 191480, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 191481, 191980, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 146860, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 146861, 149200, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 160670, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160671, 161620, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 161621, 164180, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151660, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151661, 156820, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 156821, 160580, CAM_S5K3J1_SET_A_all_956_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 126380, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126381, 126540, CAM_S5K3J1_SET_A_all_992_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126541, 126780, CAM_S5K3J1_SET_A_all_950_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126781, 126960, CAM_S5K3J1_SET_A_all_995_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126961, 130380, CAM_S5K3J1_SET_A_all_956_MHZ }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_A_mode[] = { + { + sensor_s5k3j1_setfile_A_mipi_channel_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_channel_ALL), + sensor_s5k3j1_setfile_A_mipi_setting_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_setting_ALL) + }, +}; + +/*************************************/ +/* ========== Mode B =============== */ +/*************************************/ + +enum { + CAM_S5K3J1_SET_B_all_1196_MHZ = 0, + CAM_S5K3J1_SET_B_all_1011_MHZ = 1, + CAM_S5K3J1_SET_B_all_1139_MHZ = 2, + CAM_S5K3J1_SET_B_all_1094_MHZ = 3 +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_1196_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x00BB, 0x00, 0x00}, + {0x0312, 0x0000, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_1011_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x013C, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_1139_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x00B2, 0x00, 0x00}, + {0x0312, 0x0000, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_ALL_1094_MHZ_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0156, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1196_mhz[] = { + { MIPI_ALL_1196_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1196_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1011_mhz[] = { + { MIPI_ALL_1011_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1011_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1139_mhz[] = { + { MIPI_ALL_1139_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1139_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_all_1094_mhz[] = { + { MIPI_ALL_1094_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_ALL_1094_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_mipi_setting sensor_s5k3j1_setfile_B_mipi_setting_ALL[] = { + { "1196 Mhz", + sensor_s5k3j1_setfile_B_mipi_all_1196_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1196_mhz) }, + { "1011 Mhz", + sensor_s5k3j1_setfile_B_mipi_all_1011_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1011_mhz) }, + { "1139 Mhz", + sensor_s5k3j1_setfile_B_mipi_all_1139_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1139_mhz) }, + { "1094 Mhz", + sensor_s5k3j1_setfile_B_mipi_all_1094_mhz, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_all_1094_mhz) }, +}; + +static const struct cam_mipi_channel sensor_s5k3j1_setfile_B_mipi_channel_ALL[] = { + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10733, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10734, 10781, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10782, 10808, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10809, 10838, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9686, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9687, 9761, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9762, 9836, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9837, 9896, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9897, 9911, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9912, 9938, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1362, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1363, 1437, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1438, 1513, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1708, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1709, 1738, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4450, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4451, 4458, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2258, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2259, 2308, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2309, 2327, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2328, 2551, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2552, 2560, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2561, 2563, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 3049, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3050, 3065, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3066, 3088, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 367, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 368, 462, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 463, 517, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 518, 599, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 672, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 673, 822, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 823, 972, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 973, 1093, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1094, 1122, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1123, 1199, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1625, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1626, 1775, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1776, 1949, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 2317, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2318, 2399, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2610, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2611, 2632, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2633, 2649, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2815, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2816, 2916, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2917, 2954, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2955, 3402, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3403, 3421, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3422, 3449, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3699, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3700, 3731, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3732, 3799, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5124, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5125, 5179, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5228, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5229, 5274, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5275, 5279, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5379, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5794, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5795, 5849, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5999, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6149, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6449, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6525, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6526, 6599, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8112, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8113, 8262, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8263, 8412, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8413, 8533, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8534, 8562, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8563, 8689, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 9000, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 9001, 9022, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 9023, 9039, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9334, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9335, 9484, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9485, 9659, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9745, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9746, 9769, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9869, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 10284, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10285, 10359, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36349, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37760, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37761, 37856, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37857, 38249, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38523, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38524, 38587, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38588, 38649, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38912, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38913, 38954, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38955, 38982, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38983, 39062, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39063, 39510, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39511, 39590, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39591, 39648, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39649, 39649, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39747, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39748, 39894, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39895, 39897, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39898, 40046, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40047, 40196, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40197, 40346, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40347, 40400, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40401, 40496, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40497, 40955, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40956, 41056, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41057, 41094, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41095, 41542, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41543, 41561, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41562, 41589, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41623, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41624, 41643, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41644, 41691, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41692, 41744, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41745, 41923, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41924, 42045, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42046, 42073, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42074, 42222, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42223, 42372, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42373, 42820, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42821, 42907, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42908, 42970, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42971, 43419, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43420, 43549, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43550, 43562, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43563, 43569, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43570, 43589, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55569, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55570, 55699, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55700, 55712, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55713, 55719, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55720, 56167, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56168, 56218, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56219, 56317, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56318, 56739, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66803, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66804, 66898, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66899, 66953, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66954, 67335, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68923, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68924, 68935, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, CAM_S5K3J1_SET_B_all_1011_MHZ }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 177100, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 177101, 178780, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 189080, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189081, 191980, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 146000, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 146001, 147180, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 147181, 149200, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 164180, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151980, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151981, 153180, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 153181, 157080, CAM_S5K3J1_SET_B_all_1139_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157081, 157980, CAM_S5K3J1_SET_B_all_1094_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157981, 160580, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 129240, CAM_S5K3J1_SET_B_all_1196_MHZ }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 129241, 130380, CAM_S5K3J1_SET_B_all_1139_MHZ }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_B_mode[] = { + { + sensor_s5k3j1_setfile_B_mipi_channel_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_channel_ALL), + sensor_s5k3j1_setfile_B_mipi_setting_ALL, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_setting_ALL) + }, +}; + +/*************************************/ +/* ========== DUMMY ================ */ +/*************************************/ +enum { + CAM_FRONT_SET_DUMMY_MHZ = 0, +}; + +struct cam_sensor_i2c_reg_array MIPI_FRONT_DUMMY_MHZ_REG_ARRAY[] = { +}; + +static const struct cam_sensor_i2c_reg_setting sensor_front_setfile_dummy_mhz[] = { + { MIPI_FRONT_DUMMY_MHZ_REG_ARRAY, ARRAY_SIZE(MIPI_FRONT_DUMMY_MHZ_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_mipi_setting sensor_front_setfile_dummy_mipi_setting[] = { + { "DUMMY Mhz", + sensor_front_setfile_dummy_mhz, ARRAY_SIZE(sensor_front_setfile_dummy_mhz) }, +}; + +static const struct cam_mipi_channel sensor_front_setfile_dummy_channel[] = { + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, CAM_FRONT_SET_DUMMY_MHZ }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_C_mode[] = { + { + sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), + sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) + }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_D_mode[] = { + { + sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), + sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) + }, +}; + +#endif /* _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1_2_0.h old mode 100644 new mode 100755 index d85c2b90f4..aa4eb39ed1 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1_2_0.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3j1_2_0.h @@ -1,1915 +1,1915 @@ -/* Copyright (c) 2017, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_2_0_H_ -#define _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_2_0_H_ - -#include "cam_sensor_dev.h" - -int num_front_mipi_setting = 2; - -/* -B6_FrontCAM_Adaptive MIPI 2.0_3J1_231204.xlsx -SET A : Other -SET B : M3 4k 60fps -*/ - -/*************************************/ -/* ========== SET A =============== */ -/*************************************/ -struct cam_sensor_i2c_reg_array MIPI_SET_A_992_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0136, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_SET_A_995_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0137, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_SET_A_956_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x012B, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_SET_A_950_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0129, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_992[] = { - { MIPI_SET_A_992_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_992_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_995[] = { - { MIPI_SET_A_995_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_995_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_956[] = { - { MIPI_SET_A_956_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_956_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_950[] = { - { MIPI_SET_A_950_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_950_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_mipi_setting sensor_s5k3j1_setfile_A_mipi_setting[] = { - { "992 Mhz", 992, - sensor_s5k3j1_setfile_A_mipi_992, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_992) }, - { "995 Mhz", 995, - sensor_s5k3j1_setfile_A_mipi_995, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_995) }, - { "956 Mhz", 956, - sensor_s5k3j1_setfile_A_mipi_956, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_956) }, - { "950 Mhz", 950, - sensor_s5k3j1_setfile_A_mipi_950, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_950) }, -}; - -static const struct cam_mipi_cell_ratings sensor_s5k3j1_setfile_A_mipi_channel[] = { - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, {7, 7, 147, 0} }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, {66, 63, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10628, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10629, 10656, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10657, 10663, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10664, 10698, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10699, 10726, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10727, 10728, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10729, 10733, {0, 3, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10734, 10798, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10799, 10838, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9668, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9669, 9706, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9707, 9738, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9739, 9772, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9773, 9776, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9777, 9842, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9843, 9884, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9885, 9916, {60, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9917, 9938, {60, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1179, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1180, 1188, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1189, 1249, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1250, 1265, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1266, 1295, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1296, 1335, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1336, 1356, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1357, 1365, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1366, 1418, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1419, 1426, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1427, 1488, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1489, 1513, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1603, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1604, 1631, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1632, 1638, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1639, 1673, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1674, 1701, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1702, 1703, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1704, 1708, {0, 3, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1709, 1738, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4428, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4429, 4443, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4444, 4458, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4387, 4413, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2245, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2246, 2276, {2, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2277, 2303, {2, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2304, 2315, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2316, 2346, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2347, 2395, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2396, 2465, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2466, 2481, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2482, 2485, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2486, 2525, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2526, 2551, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2552, 2555, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2556, 2563, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 2976, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2977, 2992, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2993, 3016, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3017, 3046, {7, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3047, 3048, {0, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3049, 3062, {0, 7, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3063, 3086, {0, 0, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3087, 3088, {0, 0, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 712, 753, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 754, 763, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 19, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 20, 157, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 158, 213, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 214, 226, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 227, 297, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 298, 353, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 354, 357, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 358, 366, {0, 3, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 367, 497, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 498, 599, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 636, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 637, 713, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 714, 776, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 777, 844, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 845, 853, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 854, 984, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 985, 1069, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1070, 1133, {60, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1134, 1188, {60, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1189, 1199, {60, 60, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1259, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1260, 1277, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1278, 1399, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1400, 1431, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1432, 1491, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1492, 1571, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1572, 1612, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1613, 1631, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1632, 1737, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1738, 1752, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1753, 1877, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1878, 1927, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1928, 1949, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 1969, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1970, 2107, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2108, 2163, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2164, 2176, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2177, 2247, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2248, 2303, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2304, 2307, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2308, 2316, {0, 3, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2317, 2399, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2567, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2568, 2596, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2597, 2649, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2755, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2756, 2767, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2768, 2791, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2792, 2852, {2, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2853, 2907, {2, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2908, 2931, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2932, 2992, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2993, 3091, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3092, 3231, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3232, 3263, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3264, 3270, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3271, 3350, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3351, 3403, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3404, 3410, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3411, 3449, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3553, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3554, 3584, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3585, 3633, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3634, 3693, {7, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3694, 3697, {0, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3698, 3724, {0, 7, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3725, 3773, {0, 0, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3774, 3799, {0, 0, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5089, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5090, 5113, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5114, 5179, {140, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5229, {140, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5230, 5253, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5254, 5279, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5284, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5285, 5373, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5374, 5379, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5759, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5760, 5783, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5784, 5849, {140, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5873, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5874, 5931, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5932, 5999, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6107, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6108, 6136, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6137, 6149, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6245, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6246, 6248, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6249, 6271, {0, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6272, 6302, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6303, 6388, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6389, 6442, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6443, 6449, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6488, {0, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6489, 6599, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8076, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8077, 8153, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8154, 8216, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8217, 8284, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8285, 8293, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8294, 8424, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8425, 8509, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8510, 8573, {60, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8574, 8628, {60, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8629, 8649, {60, 60, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8650, 8689, {0, 60, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 8723, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8724, 8781, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8782, 8957, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8958, 8986, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8987, 9039, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9214, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9215, 9303, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9304, 9354, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9355, 9495, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9496, 9521, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9522, 9635, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9636, 9638, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9639, 9659, {0, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9687, {0, 0, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9688, 9735, {0, 0, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9736, 9769, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9781, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9782, 9869, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 10061, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10062, 10160, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10161, 10201, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10202, 10209, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10210, 10257, {60, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10258, 10300, {60, 60, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10301, 10349, {60, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10350, 10359, {0, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36262, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36263, 36349, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37771, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37772, 37780, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37781, 37813, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37814, 37855, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37856, 37911, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37912, 37953, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37954, 37995, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37996, 38115, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38116, 38249, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38288, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38289, 38367, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38368, 38387, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38388, 38428, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38429, 38515, {0, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38516, 38527, {0, 0, 60, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38528, 38649, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38683, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38684, 38864, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38865, 38891, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38892, 38967, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38968, 39004, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39005, 39021, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39022, 39031, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39032, 39107, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39108, 39161, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39162, 39339, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39340, 39387, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39388, 39464, {2, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39465, 39479, {2, 2, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39480, 39499, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39500, 39527, {2, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39528, 39604, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39605, 39639, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39640, 39649, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39805, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39806, 39915, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39916, 39945, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39946, 39975, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39976, 39997, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39998, 40055, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40056, 40115, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40116, 40137, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40138, 40280, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40281, 40411, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40412, 40420, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40421, 40453, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40454, 40495, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40496, 40551, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40552, 40593, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40594, 40635, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40636, 40755, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40756, 40895, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40896, 40907, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40908, 40931, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40932, 40992, {2, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40993, 41047, {2, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41048, 41071, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41072, 41132, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41133, 41231, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41232, 41371, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41372, 41403, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41404, 41410, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41411, 41490, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41491, 41543, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41544, 41550, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41551, 41589, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41626, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41627, 41734, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41735, 41744, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41745, 41854, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41855, 41874, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41875, 41884, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41885, 41964, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41965, 41994, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41995, 42104, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42105, 42209, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42210, 42240, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42241, 42349, {40, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42350, 42352, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42353, 42380, {40, 40, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42381, 42443, {0, 40, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42444, 42492, {0, 40, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42493, 42583, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42584, 42684, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42685, 42736, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42737, 42824, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42825, 42849, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42850, 42876, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42877, 42921, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42922, 42989, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42990, 43061, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43062, 43160, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43161, 43232, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43233, 43300, {2, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43301, 43347, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43348, 43372, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43373, 43400, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43401, 43487, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43488, 43540, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43541, 43589, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55310, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55311, 55382, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55383, 55450, {2, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55451, 55497, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55498, 55522, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55523, 55550, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55551, 55637, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55638, 55690, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55691, 55785, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55786, 55878, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55879, 55925, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55926, 55994, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55995, 56018, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56019, 56028, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56029, 56134, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56135, 56168, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56169, 56260, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56261, 56374, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56375, 56400, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56401, 56492, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56493, 56506, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56507, 56514, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56515, 56632, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56633, 56646, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56647, 56735, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56736, 56739, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66455, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66456, 66593, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66594, 66649, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66650, 66662, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66663, 66733, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66734, 66789, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66790, 66793, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66794, 66802, {0, 3, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66803, 66933, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66934, 67089, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67090, 67125, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67126, 67160, {3, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67161, 67229, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67230, 67265, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67266, 67272, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67273, 67300, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67301, 67335, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68663, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68664, 68705, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68706, 68793, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68794, 68814, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68815, 68933, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68934, 68935, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, {0, 0, 126, 63} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, {3, 0, 63, 3} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, {3, 0, 114, 0} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, {3, 3, 0, 66} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, {0, 0, 26, 0} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, {3, 0, 63, 63} }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, {66, 63, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, {0, 7, 14, 14} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422000, 422380, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422381, 425140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 425141, 426260, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 426261, 426520, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 426521, 427940, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 427941, 429060, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429061, 429140, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429141, 429320, {0, 3, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429321, 431940, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 431941, 433980, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 386000, 386720, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 386721, 388260, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 388261, 389520, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 389521, 390880, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 390881, 391060, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 391061, 393680, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 393681, 395380, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 395381, 396660, {60, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 396661, 397760, {60, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 397761, 397980, {60, 60, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 361000, 362180, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362181, 362540, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362541, 364980, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 364981, 365620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 365621, 366820, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 366821, 368420, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 368421, 369240, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 369241, 369620, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 369621, 371740, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 371741, 372040, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 372041, 374540, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 374541, 375540, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 375541, 375980, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 177140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 177141, 177720, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 177721, 178780, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524000, 524100, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524101, 524340, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524341, 524820, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524821, 526040, {2, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 526041, 527140, {2, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527141, 527620, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527621, 528840, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 528841, 530820, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 530821, 533620, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 533621, 534260, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534261, 534400, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534401, 536000, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 536001, 537060, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537061, 537200, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537201, 538000, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 187060, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 187061, 187680, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 187681, 188660, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 188661, 189860, {7, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189861, 189940, {0, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189941, 190480, {0, 7, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 190481, 191460, {0, 0, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 191461, 191980, {0, 0, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 147380, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 147381, 147860, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 147861, 149200, {140, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 149200, 150180, {140, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 150181, 150660, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 150661, 151200, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151600, 151680, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151681, 153460, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 153461, 153580, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172000, 172460, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172461, 173620, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 173621, 175000, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 160100, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160101, 160160, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160161, 160620, {0, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160621, 161240, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 161241, 162960, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 162961, 164040, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 164041, 164180, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 386000, 386720, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 386721, 388260, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 388261, 389520, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 389521, 390880, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 390881, 391060, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 391061, 393680, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 393681, 395380, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 395381, 396660, {60, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 396661, 397760, {60, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 397761, 398180, {60, 60, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 398181, 398980, {0, 60, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 171800, 172460, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 172461, 173620, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 173621, 177140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 177141, 177720, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 177721, 178800, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151680, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151681, 153460, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 153461, 154480, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 154481, 157300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157301, 157820, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157821, 160100, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 160101, 160160, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 160161, 160580, {0, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143400, 143940, {0, 0, 140, 140} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143941, 144900, {0, 0, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 144901, 145580, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_285_NR5G_N030), 470000, 470220, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_285_NR5G_N030), 470221, 471980, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514000, 514420, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514421, 514600, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514601, 515260, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 515261, 516100, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 516101, 517220, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 517221, 518060, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 518061, 518900, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 518901, 521300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 521301, 523980, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 376000, 376760, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 376761, 378340, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 378341, 378740, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 378741, 379560, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 379561, 381300, {0, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381301, 381540, {0, 0, 60, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381541, 384000, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 460000, 460660, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 460661, 464280, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 464281, 464820, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 464821, 466340, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 466341, 467080, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 467081, 467420, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 467421, 467620, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 467621, 469140, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 469141, 470220, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 470221, 473780, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 473781, 474740, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 474741, 476280, {2, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476281, 476580, {2, 2, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476581, 476980, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476981, 477540, {2, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 477541, 479080, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 479081, 479780, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 479781, 480000, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 499200, 502300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 502301, 504500, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504501, 505100, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 505101, 505700, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 505701, 506140, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 506141, 507300, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 507301, 508500, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 508501, 508940, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 508941, 511800, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 511801, 514420, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514421, 514600, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514601, 515260, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 515261, 516100, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 516101, 517220, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 517221, 518060, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 518061, 518900, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 518901, 521300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 521301, 524100, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524101, 524340, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524341, 524820, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524821, 526040, {2, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 526041, 527140, {2, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527141, 527620, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527621, 528840, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 528841, 530820, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 530821, 533620, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 533621, 534260, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534261, 534400, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534401, 536000, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 536001, 537060, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537061, 537200, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537201, 537980, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 636667, 637127, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 637128, 637607, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 637608, 638047, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638048, 638367, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638368, 638547, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638548, 638727, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638728, 639307, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639308, 639647, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639648, 640287, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 640288, 640907, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 640908, 641227, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641228, 641687, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641688, 641847, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641848, 641907, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641908, 642627, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642628, 642847, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642848, 643467, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643468, 644227, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 644228, 644387, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 644388, 645007, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645008, 645107, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645108, 645147, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645148, 645947, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645948, 646027, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646028, 646627, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646628, 646666, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422000, 422380, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422381, 425140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 425141, 426260, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 426261, 426520, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 426521, 427940, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 427941, 429060, {0, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429061, 429140, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429141, 429320, {0, 3, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429321, 431940, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 431941, 435060, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 435061, 435780, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 435781, 436480, {3, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 436481, 437860, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 437861, 438580, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 438581, 438720, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 438721, 439280, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 439281, 439980, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 124940, {0, 0, 7, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 124941, 125780, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 125781, 127540, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 127541, 127960, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 127961, 130340, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 130341, 130380, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620000, 620520, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620521, 621080, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621081, 621280, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621281, 621780, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621781, 622000, {1, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622001, 622220, {0, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622221, 622720, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622721, 622780, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622781, 623700, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 623701, 624380, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 624381, 624460, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 624461, 625100, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625101, 625300, {1, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625301, 625380, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625381, 625960, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625961, 626040, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626041, 626900, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626901, 627620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627621, 627680, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627681, 628420, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628421, 628560, {1, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628561, 628620, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628621, 629160, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629161, 629360, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629361, 630080, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630081, 630780, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630781, 631000, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631001, 631720, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631721, 631740, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631741, 631920, {20, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631921, 632340, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 632341, 632680, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 632681, 633280, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633281, 633960, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633961, 634300, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634301, 634880, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634881, 635060, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635061, 635220, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635221, 635540, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635541, 635980, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635981, 636460, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 636461, 637120, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 637121, 637600, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 637601, 638060, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638061, 638380, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638381, 638540, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638541, 638720, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638721, 639300, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639301, 639660, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639661, 640300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 640301, 640920, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 640921, 641220, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641221, 641680, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641681, 641840, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641841, 641920, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641921, 642620, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642621, 642840, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642841, 643460, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643461, 644220, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 644221, 644400, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 644401, 645000, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645001, 645100, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645101, 645140, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645141, 645940, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645941, 646040, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646041, 646620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646621, 647520, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647521, 647560, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647561, 648300, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648301, 648320, {20, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648321, 648460, {20, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648461, 649220, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649221, 649260, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649261, 649800, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649801, 650720, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650721, 650840, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650841, 651480, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651481, 651640, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651641, 651760, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651761, 652420, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652421, 652580, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652581, 652960, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652961, 653900, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 653901, 654140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654141, 654680, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654681, 654960, {1, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654961, 655080, {1, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655081, 655600, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655601, 655900, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655901, 656140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 656141, 657060, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657061, 657440, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657441, 657860, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657861, 658280, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658281, 658380, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658381, 658800, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658801, 659200, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659201, 659300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659301, 660240, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 660241, 660760, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 660761, 661040, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661041, 661600, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661601, 661680, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661681, 661980, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661981, 662460, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662461, 662520, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662521, 663400, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663401, 664060, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664061, 664240, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664241, 664920, {20, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664921, 664980, {20, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664981, 665180, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665181, 665640, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665641, 665840, {0, 20, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665841, 666560, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666561, 667360, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 667361, 667420, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 667421, 668220, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668221, 668300, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668301, 668360, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668361, 668800, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668801, 669160, {0, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669161, 669740, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669741, 670620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670621, 670680, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670681, 671540, {1, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671541, 671600, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671601, 671980, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671981, 672480, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672481, 672900, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672901, 673800, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673801, 673980, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673981, 674740, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674741, 674860, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674861, 674900, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674901, 675140, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675141, 675800, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675801, 676080, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676081, 677000, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677001, 677280, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677281, 677920, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677921, 678180, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678181, 678220, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678221, 678300, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678301, 679120, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679121, 679240, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679241, 680000, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620000, 620520, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620521, 621080, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621081, 621280, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621281, 621780, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621781, 622000, {1, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622001, 622220, {0, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622221, 622720, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622721, 622780, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622781, 623700, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 623701, 624380, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 624381, 624460, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 624461, 625100, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625101, 625300, {1, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625301, 625380, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625381, 625960, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625961, 626040, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626041, 626900, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626901, 627620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627621, 627680, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627681, 628420, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628421, 628560, {1, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628561, 628620, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628621, 629160, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629161, 629360, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629361, 630080, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630081, 630780, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630781, 631000, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631001, 631720, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631721, 631740, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631741, 631920, {20, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631921, 632340, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 632341, 632680, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 632681, 633280, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633281, 633960, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633961, 634300, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634301, 634880, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634881, 635060, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635061, 635220, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635221, 635540, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635541, 635980, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635981, 636460, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 636461, 637120, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 637121, 637600, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 637601, 638060, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638061, 638380, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638381, 638540, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638541, 638720, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638721, 639300, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639301, 639660, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639661, 640300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 640301, 640920, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 640921, 641220, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641221, 641680, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641681, 641840, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641841, 641920, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641921, 642620, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642621, 642840, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642841, 643460, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643461, 644220, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 644221, 644400, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 644401, 645000, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645001, 645100, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645101, 645140, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645141, 645940, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645941, 646040, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646041, 646620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646621, 647520, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647521, 647560, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647561, 648300, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648301, 648320, {20, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648321, 648460, {20, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648461, 649220, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649221, 649260, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649261, 649800, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649801, 650720, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650721, 650840, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650841, 651480, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651481, 651640, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651641, 651760, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651761, 652420, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652421, 652580, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652581, 652960, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652961, 653333, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693334, 693814, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693815, 693874, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693875, 694154, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694155, 694754, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694755, 694774, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694775, 695074, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695075, 695694, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695695, 696134, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 696135, 697074, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697075, 697134, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697135, 697314, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697315, 698054, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698055, 698094, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698095, 698254, {0, 20, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698255, 699014, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699015, 699314, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699315, 700254, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700255, 700434, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700435, 700494, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700495, 701354, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 701355, 701394, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 701395, 701414, {0, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 701415, 702334, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702335, 702514, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702515, 703434, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703435, 703654, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703655, 703734, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703735, 704594, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704595, 704674, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704675, 704714, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704715, 705654, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 705655, 705694, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 705695, 706634, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706635, 706814, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706815, 707054, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707055, 707754, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707755, 707974, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707975, 708034, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708035, 708894, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708895, 708974, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708975, 709814, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709815, 709994, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709995, 710354, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710355, 710914, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710915, 711294, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711295, 711354, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711355, 712074, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 712075, 712294, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 712295, 713014, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713015, 713154, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713155, 713654, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713655, 714094, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714095, 714594, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714595, 714674, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714675, 715274, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715275, 715594, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715595, 715614, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715615, 716194, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716195, 716334, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716335, 716974, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716975, 717254, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717255, 717894, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717895, 717994, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717995, 718454, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718455, 718914, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718915, 719394, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719395, 719494, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719495, 720274, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720275, 720434, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720435, 721194, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721195, 721314, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721315, 721654, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721655, 722234, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722235, 722574, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722575, 722654, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722655, 723574, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723575, 723594, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723595, 724514, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724515, 724614, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724615, 724834, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724835, 725554, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725555, 725774, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725775, 725834, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725835, 726754, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726755, 726894, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726895, 727814, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727815, 727934, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727935, 728034, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728035, 728874, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728875, 728954, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728955, 728994, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728995, 729934, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 729935, 730194, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730195, 731114, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731115, 731214, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731215, 731254, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731255, 732154, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 732155, 732194, {0, 20, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 732195, 733094, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 733095, 733333, {0, 0, 0, 0} }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_A_mode[] = { - { - sensor_s5k3j1_setfile_A_mipi_channel, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_channel), - sensor_s5k3j1_setfile_A_mipi_setting, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_setting) - }, -}; - -/*************************************/ -/* ========== SET B =============== */ -/*************************************/ -struct cam_sensor_i2c_reg_array MIPI_SET_B_1196_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x00BB, 0x00, 0x00}, - {0x0312, 0x0000, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_SET_B_1011_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x013C, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_SET_B_1139_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x00B2, 0x00, 0x00}, - {0x0312, 0x0000, 0x00, 0x00}, -}; - -struct cam_sensor_i2c_reg_array MIPI_SET_B_1094_REG_ARRAY[] = { - {0x030E, 0x0003, 0x00, 0x00}, - {0x0310, 0x0156, 0x00, 0x00}, - {0x0312, 0x0001, 0x00, 0x00}, -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1196[] = { - { MIPI_SET_B_1196_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1196_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1011[] = { - { MIPI_SET_B_1011_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1011_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1139[] = { - { MIPI_SET_B_1139_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1139_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1094[] = { - { MIPI_SET_B_1094_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1094_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_mipi_setting sensor_s5k3j1_setfile_B_mipi_setting[] = { - { "1196 Mhz", 1196, - sensor_s5k3j1_setfile_B_mipi_1196, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1196) }, - { "1011 Mhz", 1011, - sensor_s5k3j1_setfile_B_mipi_1011, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1011) }, - { "1139 Mhz", 1139, - sensor_s5k3j1_setfile_B_mipi_1139, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1139) }, - { "1094 Mhz", 1094, - sensor_s5k3j1_setfile_B_mipi_1094, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1094) }, -}; - -static const struct cam_mipi_cell_ratings sensor_s5k3j1_setfile_B_mipi_channel[] = { - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, {147, 0, 0, 14} }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, {7, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, {0, 0, 66, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10572, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10573, 10582, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10583, 10635, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10636, 10652, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10653, 10705, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10706, 10736, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10737, 10787, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10788, 10806, {3, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10807, 10835, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10836, 10838, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9718, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9719, 9814, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9815, 9824, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9825, 9838, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9839, 9884, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9885, 9894, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9895, 9908, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9909, 9932, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9933, 9938, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1188, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1189, 1190, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1191, 1203, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1204, 1260, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1261, 1273, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1274, 1365, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1366, 1392, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1393, 1435, {3, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1436, 1443, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1444, 1462, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1463, 1488, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1489, 1513, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1547, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1548, 1557, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1558, 1610, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1611, 1627, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1628, 1680, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1681, 1711, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1712, 1738, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4412, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4413, 4452, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4453, 4458, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4387, 4412, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4413, 4413, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2254, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2255, 2260, {2, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2261, 2292, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2293, 2305, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2306, 2324, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2325, 2475, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2476, 2488, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2489, 2496, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2497, 2545, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2546, 2553, {0, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2554, 2558, {40, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2559, 2563, {40, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 2986, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2987, 3052, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3053, 3068, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3069, 3088, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 712, 737, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 738, 763, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 45, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 46, 65, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 66, 170, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 171, 205, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 206, 310, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 311, 372, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 373, 474, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 475, 512, {3, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 513, 570, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 571, 599, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 736, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 737, 929, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 930, 948, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 949, 977, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 978, 1069, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1070, 1088, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1089, 1117, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1118, 1165, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1166, 1199, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1277, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1278, 1281, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1282, 1307, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1308, 1421, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1422, 1447, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1448, 1630, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1631, 1684, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1685, 1770, {3, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1771, 1787, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1788, 1824, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1825, 1876, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1877, 1927, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1928, 1949, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 1995, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1996, 2015, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2016, 2120, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2121, 2155, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2156, 2260, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2261, 2322, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2323, 2399, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2535, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2536, 2615, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2616, 2649, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2771, {0, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2772, 2809, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2810, 2821, {2, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2822, 2885, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2886, 2911, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2912, 2949, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2950, 3251, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3252, 3276, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3277, 3292, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3293, 3391, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3392, 3407, {0, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3408, 3416, {40, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3417, 3432, {40, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3433, 3449, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3572, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3573, 3704, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3705, 3736, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3737, 3799, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5054, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5055, 5179, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5194, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5195, 5233, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5234, 5279, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5290, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5291, 5353, {0, 140, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5354, 5379, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5849, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5863, {0, 7, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5864, 5915, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5916, 5935, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5936, 5999, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6075, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6076, 6149, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6259, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6260, 6284, {0, 7, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6285, 6377, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6378, 6399, {0, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6400, 6449, {0, 0, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6520, {60, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6521, 6588, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6589, 6599, {0, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8176, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8177, 8369, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8370, 8388, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8389, 8417, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8418, 8509, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8510, 8528, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8529, 8557, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8558, 8605, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8606, 8689, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 8713, {0, 7, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8714, 8765, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8766, 8785, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8786, 8925, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8926, 9005, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 9006, 9039, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9220, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9221, 9283, {0, 140, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9284, 9339, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9340, 9360, {7, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9361, 9479, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9480, 9534, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9535, 9649, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9650, 9659, {0, 7, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9673, {7, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9674, 9740, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9741, 9769, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9869, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 9992, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9993, 10104, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10105, 10132, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10133, 10139, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10140, 10244, {0, 0, 3, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10245, 10279, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10280, 10289, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10290, 10359, {60, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36254, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36255, 36276, {0, 60, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36277, 36349, {0, 60, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37751, {2, 0, 40, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37752, 37765, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37766, 37838, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37839, 37851, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37852, 37905, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37906, 38181, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38182, 38245, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38246, 38249, {0, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38316, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38317, 38528, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38529, 38531, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38532, 38592, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38593, 38649, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38702, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38703, 38837, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38838, 38917, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38918, 38933, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38934, 38977, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38978, 39057, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39058, 39073, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39074, 39109, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39110, 39249, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39250, 39343, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39344, 39483, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39484, 39503, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39504, 39515, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39516, 39643, {40, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39644, 39649, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39682, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39683, 39752, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39753, 39791, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39792, 39822, {2, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39823, 39892, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39893, 39899, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39900, 39931, {0, 40, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39932, 40039, {0, 40, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40040, 40251, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40252, 40338, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40339, 40351, {0, 0, 40, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40352, 40391, {2, 0, 40, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40392, 40405, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40406, 40478, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40479, 40491, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40492, 40545, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40546, 40821, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40822, 40885, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40886, 40911, {0, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40912, 40949, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40950, 40961, {2, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40962, 41025, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41026, 41051, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41052, 41089, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41090, 41391, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41392, 41416, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41417, 41432, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41433, 41531, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41532, 41547, {0, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41548, 41556, {40, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41557, 41572, {40, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41573, 41589, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41628, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41629, 41696, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41697, 41768, {2, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41769, 41836, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41837, 41900, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41901, 41993, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41994, 42040, {0, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42041, 42133, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42134, 42227, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42228, 42265, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42266, 42367, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42368, 42405, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42406, 42406, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42407, 42540, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42541, 42546, {0, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42547, 42680, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42681, 42825, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42826, 42835, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42836, 42912, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42913, 42965, {2, 40, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42966, 42975, {0, 40, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42976, 43052, {0, 40, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43053, 43088, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43089, 43228, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43229, 43404, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43405, 43417, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43418, 43424, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43425, 43544, {40, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43545, 43557, {40, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43558, 43564, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43565, 43589, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55378, {0, 0, 0, 40} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55379, 55554, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55555, 55567, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55568, 55574, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55575, 55694, {40, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55695, 55707, {40, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55708, 55714, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55715, 55785, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55786, 55925, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55926, 56073, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56074, 56124, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56125, 56172, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56173, 56213, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56214, 56264, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56265, 56312, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56313, 56332, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56333, 56472, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56473, 56578, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56579, 56694, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56695, 56718, {0, 2, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56719, 56739, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66481, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66482, 66501, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66502, 66606, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66607, 66641, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66642, 66746, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66747, 66808, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66809, 66910, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66911, 66948, {3, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66949, 67006, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67007, 67050, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67051, 67146, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67147, 67153, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67154, 67293, {0, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67294, 67335, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68611, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68612, 68751, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68752, 68912, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68913, 68918, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68919, 68928, {0, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68929, 68935, {7, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, {6, 3, 0, 126} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, {6, 0, 3, 60} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, {6, 6, 3, 126} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, {3, 3, 12, 6} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, {42, 0, 2, 4} }, - { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, {3, 3, 3, 63} }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, {147, 0, 0, 14} }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, {0, 0, 66, 0} }, - { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, {0, 7, 255, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422000, 422900, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422901, 423300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 423301, 425400, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 425401, 426100, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 426101, 428200, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 428201, 429440, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429441, 431480, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 431481, 432240, {3, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 432241, 433400, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 433401, 433980, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 386000, 388720, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 388721, 392580, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 392581, 392960, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 392961, 393540, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 393541, 395380, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 395381, 395760, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 395761, 396340, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 396341, 397300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 397301, 397980, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 361000, 362540, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362541, 362620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362621, 363140, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 363141, 365420, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 365421, 365940, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 365941, 369600, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 369601, 370680, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 370681, 372400, {3, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 372401, 372740, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 372741, 373480, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 373481, 374520, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 374521, 375540, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 375541, 375980, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 176500, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176501, 178100, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 178101, 178780, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524000, 524420, {0, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524421, 525180, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 525181, 525420, {2, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 525421, 526700, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 526701, 527220, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527221, 527980, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527981, 534020, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534021, 534520, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534521, 534840, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534841, 536820, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 536821, 537140, {0, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537141, 537320, {40, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537321, 537640, {40, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537641, 538000, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 187440, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 187441, 190080, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 190081, 190720, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 190721, 191980, {7, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 146680, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 146681, 149200, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 149200, 149480, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 149481, 150260, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 150261, 151200, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151600, 151800, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151801, 153060, {0, 140, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 153061, 153580, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172000, 172260, {0, 7, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172261, 173300, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 173301, 173700, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 173701, 175000, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 160380, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160381, 160880, {0, 7, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160881, 162740, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 162741, 163180, {0, 7, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 163181, 164180, {0, 0, 0, 140} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 386000, 388720, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 388721, 392580, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 392581, 392960, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 392961, 393540, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 393541, 395380, {3, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 395381, 395760, {3, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 395761, 396340, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 396341, 397300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 397301, 398980, {0, 0, 60, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 171800, 172260, {0, 7, 140, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 172261, 173300, {0, 7, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 173301, 173700, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 173701, 176500, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 176501, 178100, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 178101, 178800, {140, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151800, {0, 140, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151801, 153060, {0, 140, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 153061, 154180, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 154181, 154600, {7, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 154601, 156980, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 156981, 158080, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 158081, 160380, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 160381, 160580, {0, 7, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143400, 143660, {7, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143661, 145000, {7, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 145001, 145580, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_285_NR5G_N030), 470000, 471980, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514000, 514020, {2, 0, 40, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514021, 514300, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514301, 515760, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 515761, 516020, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 516021, 517100, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 517101, 522620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 522621, 523900, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 523901, 523980, {0, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 376000, 377320, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 377321, 381560, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381561, 381620, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381621, 382840, {3, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 382841, 384000, {3, 3, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 460000, 461040, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 461041, 463740, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 463741, 465340, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 465341, 465660, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 465661, 466540, {2, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 466541, 468140, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 468141, 468460, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 468461, 469180, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 469181, 471980, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 471981, 473860, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 473861, 476660, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476661, 477060, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 477061, 477300, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 477301, 479860, {40, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 479861, 480000, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 499200, 499840, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 499841, 501240, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 501241, 502020, {2, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 502021, 502640, {2, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 502641, 504040, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504041, 504180, {0, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504181, 504820, {0, 40, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504821, 506980, {0, 40, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 506981, 511220, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 511221, 512960, {0, 0, 40, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 512961, 513220, {0, 0, 40, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 513221, 514020, {2, 0, 40, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514021, 514300, {2, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514301, 515760, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 515761, 516020, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 516021, 517100, {0, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 517101, 522620, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 522621, 523900, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 523901, 524420, {0, 0, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524421, 525180, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 525181, 525420, {2, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 525421, 526700, {2, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 526701, 527220, {2, 2, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527221, 527980, {2, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527981, 534020, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534021, 534520, {0, 0, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534521, 534840, {0, 2, 2, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534841, 536820, {0, 2, 2, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 536821, 537140, {0, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537141, 537320, {40, 2, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537321, 537640, {40, 0, 0, 2} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537641, 537980, {40, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 636667, 637567, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 637568, 638747, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638748, 638847, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638848, 638887, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638888, 639687, {20, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639688, 639767, {20, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639768, 639807, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639808, 640287, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 640288, 641227, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641228, 642207, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642208, 642547, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642548, 642867, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642868, 643147, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643148, 643487, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643488, 643807, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643808, 643947, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643948, 644867, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 644868, 645587, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645588, 646347, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646348, 646507, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646508, 646666, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422000, 422900, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422901, 423300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 423301, 425400, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 425401, 426100, {0, 3, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 426101, 428200, {0, 0, 0, 3} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 428201, 429440, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429441, 431480, {3, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 431481, 432240, {3, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 432241, 433400, {0, 0, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 433401, 434280, {0, 3, 3, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 434281, 436200, {0, 3, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 436201, 436340, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 436341, 439140, {0, 0, 0, 60} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 439141, 439980, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 123900, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123901, 126700, {0, 0, 7, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126701, 129920, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 129921, 130040, {0, 0, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 130041, 130240, {0, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 130241, 130380, {7, 7, 0, 7} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620000, 620700, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620701, 621980, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621981, 622060, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622061, 622920, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622921, 622980, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622981, 623560, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 623561, 623860, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 623861, 624500, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 624501, 625360, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625361, 625700, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625701, 626300, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626301, 626640, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626641, 626920, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626921, 627360, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627361, 627840, {1, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627841, 628300, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628301, 628720, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628721, 629340, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629341, 629660, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629661, 630280, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630281, 630900, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630901, 631160, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631161, 631840, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631841, 632100, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 632101, 633000, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633001, 633040, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633041, 633920, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633921, 634900, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634901, 634960, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634961, 635480, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635481, 635820, {1, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635821, 635900, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635901, 636400, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 636401, 636640, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 636641, 637580, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 637581, 638760, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638761, 638840, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638841, 638880, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638881, 639680, {20, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639681, 639780, {20, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639781, 639820, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639821, 640300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 640301, 641220, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641221, 642220, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642221, 642560, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642561, 642880, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642881, 643140, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643141, 643480, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643481, 643800, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643801, 643940, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643941, 644880, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 644881, 645580, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645581, 646360, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646361, 646520, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646521, 646860, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646861, 647280, {1, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647281, 647580, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647581, 647800, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647801, 648520, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648521, 648960, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648961, 649880, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649881, 650140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650141, 650860, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650861, 651080, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651081, 651240, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651241, 651780, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651781, 652160, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652161, 652320, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652321, 653260, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 653261, 653940, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 653941, 654840, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654841, 654880, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654881, 655700, {1, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655701, 655780, {1, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655781, 655820, {0, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655821, 656620, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 656621, 657740, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657741, 658540, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658541, 658680, {0, 0, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658681, 658840, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658841, 659060, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659061, 659460, {20, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659461, 659760, {20, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659761, 660000, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 660001, 661540, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661541, 662180, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662181, 662440, {0, 0, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662441, 662480, {0, 1, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662481, 662820, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662821, 663120, {1, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663121, 663360, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663361, 663760, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663761, 665340, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665341, 665800, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665801, 665820, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665821, 666280, {0, 1, 20, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666281, 666740, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666741, 666760, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666761, 666800, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666801, 667740, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 667741, 669140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669141, 669180, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669181, 669480, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669481, 670060, {0, 20, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670061, 670100, {0, 20, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670101, 670400, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670401, 670800, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670801, 671740, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671741, 672540, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672541, 672940, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672941, 673120, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673121, 673480, {0, 1, 1, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673481, 673860, {0, 0, 1, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673861, 674060, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674061, 674780, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674781, 675720, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675721, 675920, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675921, 676720, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676721, 676780, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676781, 676860, {0, 1, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676861, 677660, {0, 0, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677661, 677700, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677701, 678780, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678781, 679280, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679281, 679700, {20, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679701, 680000, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620000, 620700, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620701, 621980, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621981, 622060, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622061, 622920, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622921, 622980, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622981, 623560, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 623561, 623860, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 623861, 624500, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 624501, 625360, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625361, 625700, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625701, 626300, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626301, 626640, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626641, 626920, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626921, 627360, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627361, 627840, {1, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627841, 628300, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628301, 628720, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628721, 629340, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629341, 629660, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629661, 630280, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630281, 630900, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630901, 631160, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631161, 631840, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631841, 632100, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 632101, 633000, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633001, 633040, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633041, 633920, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633921, 634900, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634901, 634960, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634961, 635480, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635481, 635820, {1, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635821, 635900, {0, 20, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635901, 636400, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 636401, 636640, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 636641, 637580, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 637581, 638760, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638761, 638840, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638841, 638880, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638881, 639680, {20, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639681, 639780, {20, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639781, 639820, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639821, 640300, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 640301, 641220, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641221, 642220, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642221, 642560, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642561, 642880, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642881, 643140, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643141, 643480, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643481, 643800, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643801, 643940, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643941, 644880, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 644881, 645580, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645581, 646360, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646361, 646520, {0, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646521, 646860, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646861, 647280, {1, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647281, 647580, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647581, 647800, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647801, 648520, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648521, 648960, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648961, 649880, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649881, 650140, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650141, 650860, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650861, 651080, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651081, 651240, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651241, 651780, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651781, 652160, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652161, 652320, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652321, 653260, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 653261, 653333, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693334, 693714, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693715, 694734, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694735, 695014, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695015, 695674, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695675, 695714, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695715, 695954, {0, 0, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695955, 696134, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 696135, 696654, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 696655, 697074, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697075, 698654, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698655, 698734, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698735, 699514, {20, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699515, 699594, {20, 1, 1, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699595, 699654, {20, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699655, 700454, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700455, 702314, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702315, 702714, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702715, 702894, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702895, 703234, {1, 20, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703235, 703314, {1, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703315, 703654, {1, 20, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703655, 703814, {0, 20, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703815, 704234, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704235, 705954, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 705955, 706254, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706255, 706694, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706695, 706894, {1, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706895, 707114, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707115, 707194, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707195, 707634, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707635, 708034, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708035, 709614, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709615, 709634, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709635, 710534, {0, 1, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710535, 710554, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710555, 710694, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710695, 710914, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710915, 711634, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711635, 711834, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711835, 712994, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 712995, 713254, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713255, 713934, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713935, 714194, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714195, 714674, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714675, 714694, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714695, 715614, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715615, 715634, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715635, 716374, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716375, 716894, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716895, 717294, {0, 1, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717295, 717834, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717835, 718494, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718495, 718674, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718675, 719434, {20, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719435, 719594, {20, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719595, 719734, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719735, 720554, {0, 20, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720555, 720674, {0, 20, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720675, 721474, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721475, 722294, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722295, 722654, {0, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722655, 723114, {1, 0, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723115, 723234, {1, 1, 20, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723235, 723594, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723595, 724034, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724035, 724194, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724195, 725134, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725135, 726094, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726095, 726474, {0, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726475, 726654, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726655, 727034, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727035, 727414, {1, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727415, 727574, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727575, 727854, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727855, 728774, {0, 0, 0, 20} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728775, 729854, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 729855, 729894, {0, 1, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 729895, 730634, {0, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730635, 730774, {1, 1, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730775, 730834, {1, 0, 1, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730835, 731494, {1, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731495, 731574, {1, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731575, 732434, {0, 0, 0, 1} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 732435, 733214, {0, 0, 0, 0} }, - { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 733215, 733333, {0, 1, 0, 0} }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_B_mode[] = { - { - sensor_s5k3j1_setfile_B_mipi_channel, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_channel), - sensor_s5k3j1_setfile_B_mipi_setting, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_setting) - }, -}; - -/*************************************/ -/* ========== DUMMY ================ */ -/*************************************/ -struct cam_sensor_i2c_reg_array MIPI_FRONT_DUMMY_REG_ARRAY[] = { -}; - -static const struct cam_sensor_i2c_reg_setting sensor_front_setfile_dummy[] = { - { MIPI_FRONT_DUMMY_REG_ARRAY, ARRAY_SIZE(MIPI_FRONT_DUMMY_REG_ARRAY), - CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } -}; - -static const struct cam_mipi_setting sensor_front_setfile_dummy_mipi_setting[] = { - { "DUMMY Msps", 0, - sensor_front_setfile_dummy, ARRAY_SIZE(sensor_front_setfile_dummy) }, -}; - -static const struct cam_mipi_cell_ratings sensor_front_setfile_dummy_channel[] = { - { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, {0} }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_C_mode[] = { - { - sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), - sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) - }, -}; - -static const struct cam_mipi_sensor_mode sensor_front_mipi_D_mode[] = { - { - sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), - sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) - }, -}; - -#endif /* _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_2_0_H_ */ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_2_0_H_ +#define _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_2_0_H_ + +#include "cam_sensor_dev.h" + +int num_front_mipi_setting = 2; + +/* +B6_FrontCAM_Adaptive MIPI 2.0_3J1_231204.xlsx +SET A : Other +SET B : M3 4k 60fps +*/ + +/*************************************/ +/* ========== SET A =============== */ +/*************************************/ +struct cam_sensor_i2c_reg_array MIPI_SET_A_992_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0136, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_SET_A_995_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0137, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_SET_A_956_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x012B, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_SET_A_950_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0129, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_992[] = { + { MIPI_SET_A_992_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_992_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_995[] = { + { MIPI_SET_A_995_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_995_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_956[] = { + { MIPI_SET_A_956_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_956_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_A_mipi_950[] = { + { MIPI_SET_A_950_REG_ARRAY, ARRAY_SIZE(MIPI_SET_A_950_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_mipi_setting sensor_s5k3j1_setfile_A_mipi_setting[] = { + { "992 Mhz", 992, + sensor_s5k3j1_setfile_A_mipi_992, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_992) }, + { "995 Mhz", 995, + sensor_s5k3j1_setfile_A_mipi_995, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_995) }, + { "956 Mhz", 956, + sensor_s5k3j1_setfile_A_mipi_956, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_956) }, + { "950 Mhz", 950, + sensor_s5k3j1_setfile_A_mipi_950, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_950) }, +}; + +static const struct cam_mipi_cell_ratings sensor_s5k3j1_setfile_A_mipi_channel[] = { + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, {7, 7, 147, 0} }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, {66, 63, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10628, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10629, 10656, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10657, 10663, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10664, 10698, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10699, 10726, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10727, 10728, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10729, 10733, {0, 3, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10734, 10798, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10799, 10838, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9668, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9669, 9706, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9707, 9738, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9739, 9772, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9773, 9776, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9777, 9842, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9843, 9884, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9885, 9916, {60, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9917, 9938, {60, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1179, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1180, 1188, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1189, 1249, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1250, 1265, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1266, 1295, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1296, 1335, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1336, 1356, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1357, 1365, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1366, 1418, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1419, 1426, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1427, 1488, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1489, 1513, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1603, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1604, 1631, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1632, 1638, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1639, 1673, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1674, 1701, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1702, 1703, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1704, 1708, {0, 3, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1709, 1738, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4428, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4429, 4443, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4444, 4458, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4387, 4413, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2245, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2246, 2276, {2, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2277, 2303, {2, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2304, 2315, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2316, 2346, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2347, 2395, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2396, 2465, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2466, 2481, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2482, 2485, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2486, 2525, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2526, 2551, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2552, 2555, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2556, 2563, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 2976, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2977, 2992, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2993, 3016, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3017, 3046, {7, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3047, 3048, {0, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3049, 3062, {0, 7, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3063, 3086, {0, 0, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3087, 3088, {0, 0, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 712, 753, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 754, 763, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 19, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 20, 157, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 158, 213, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 214, 226, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 227, 297, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 298, 353, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 354, 357, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 358, 366, {0, 3, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 367, 497, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 498, 599, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 636, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 637, 713, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 714, 776, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 777, 844, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 845, 853, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 854, 984, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 985, 1069, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1070, 1133, {60, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1134, 1188, {60, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1189, 1199, {60, 60, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1259, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1260, 1277, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1278, 1399, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1400, 1431, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1432, 1491, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1492, 1571, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1572, 1612, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1613, 1631, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1632, 1737, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1738, 1752, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1753, 1877, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1878, 1927, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1928, 1949, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 1969, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1970, 2107, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2108, 2163, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2164, 2176, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2177, 2247, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2248, 2303, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2304, 2307, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2308, 2316, {0, 3, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2317, 2399, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2567, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2568, 2596, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2597, 2649, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2755, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2756, 2767, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2768, 2791, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2792, 2852, {2, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2853, 2907, {2, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2908, 2931, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2932, 2992, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2993, 3091, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3092, 3231, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3232, 3263, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3264, 3270, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3271, 3350, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3351, 3403, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3404, 3410, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3411, 3449, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3553, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3554, 3584, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3585, 3633, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3634, 3693, {7, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3694, 3697, {0, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3698, 3724, {0, 7, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3725, 3773, {0, 0, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3774, 3799, {0, 0, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5089, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5090, 5113, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5114, 5179, {140, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5229, {140, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5230, 5253, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5254, 5279, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5284, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5285, 5373, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5374, 5379, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5759, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5760, 5783, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5784, 5849, {140, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5873, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5874, 5931, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5932, 5999, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6107, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6108, 6136, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6137, 6149, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6245, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6246, 6248, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6249, 6271, {0, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6272, 6302, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6303, 6388, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6389, 6442, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6443, 6449, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6488, {0, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6489, 6599, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8076, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8077, 8153, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8154, 8216, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8217, 8284, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8285, 8293, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8294, 8424, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8425, 8509, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8510, 8573, {60, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8574, 8628, {60, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8629, 8649, {60, 60, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8650, 8689, {0, 60, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 8723, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8724, 8781, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8782, 8957, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8958, 8986, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8987, 9039, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9214, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9215, 9303, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9304, 9354, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9355, 9495, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9496, 9521, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9522, 9635, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9636, 9638, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9639, 9659, {0, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9687, {0, 0, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9688, 9735, {0, 0, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9736, 9769, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9781, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9782, 9869, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 10061, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10062, 10160, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10161, 10201, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10202, 10209, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10210, 10257, {60, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10258, 10300, {60, 60, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10301, 10349, {60, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10350, 10359, {0, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36262, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36263, 36349, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37771, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37772, 37780, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37781, 37813, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37814, 37855, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37856, 37911, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37912, 37953, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37954, 37995, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37996, 38115, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38116, 38249, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38288, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38289, 38367, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38368, 38387, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38388, 38428, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38429, 38515, {0, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38516, 38527, {0, 0, 60, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38528, 38649, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38683, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38684, 38864, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38865, 38891, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38892, 38967, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38968, 39004, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39005, 39021, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39022, 39031, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39032, 39107, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39108, 39161, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39162, 39339, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39340, 39387, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39388, 39464, {2, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39465, 39479, {2, 2, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39480, 39499, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39500, 39527, {2, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39528, 39604, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39605, 39639, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39640, 39649, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39805, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39806, 39915, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39916, 39945, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39946, 39975, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39976, 39997, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39998, 40055, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40056, 40115, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40116, 40137, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40138, 40280, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40281, 40411, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40412, 40420, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40421, 40453, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40454, 40495, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40496, 40551, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40552, 40593, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40594, 40635, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40636, 40755, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40756, 40895, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40896, 40907, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40908, 40931, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40932, 40992, {2, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40993, 41047, {2, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41048, 41071, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41072, 41132, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41133, 41231, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41232, 41371, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41372, 41403, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41404, 41410, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41411, 41490, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41491, 41543, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41544, 41550, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41551, 41589, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41626, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41627, 41734, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41735, 41744, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41745, 41854, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41855, 41874, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41875, 41884, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41885, 41964, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41965, 41994, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41995, 42104, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42105, 42209, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42210, 42240, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42241, 42349, {40, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42350, 42352, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42353, 42380, {40, 40, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42381, 42443, {0, 40, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42444, 42492, {0, 40, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42493, 42583, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42584, 42684, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42685, 42736, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42737, 42824, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42825, 42849, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42850, 42876, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42877, 42921, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42922, 42989, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42990, 43061, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43062, 43160, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43161, 43232, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43233, 43300, {2, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43301, 43347, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43348, 43372, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43373, 43400, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43401, 43487, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43488, 43540, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43541, 43589, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55310, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55311, 55382, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55383, 55450, {2, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55451, 55497, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55498, 55522, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55523, 55550, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55551, 55637, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55638, 55690, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55691, 55785, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55786, 55878, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55879, 55925, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55926, 55994, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55995, 56018, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56019, 56028, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56029, 56134, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56135, 56168, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56169, 56260, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56261, 56374, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56375, 56400, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56401, 56492, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56493, 56506, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56507, 56514, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56515, 56632, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56633, 56646, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56647, 56735, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56736, 56739, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66455, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66456, 66593, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66594, 66649, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66650, 66662, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66663, 66733, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66734, 66789, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66790, 66793, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66794, 66802, {0, 3, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66803, 66933, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66934, 67089, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67090, 67125, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67126, 67160, {3, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67161, 67229, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67230, 67265, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67266, 67272, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67273, 67300, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67301, 67335, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68663, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68664, 68705, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68706, 68793, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68794, 68814, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68815, 68933, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68934, 68935, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, {0, 0, 126, 63} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, {3, 0, 63, 3} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, {3, 0, 114, 0} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, {3, 3, 0, 66} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, {0, 0, 26, 0} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, {3, 0, 63, 63} }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, {66, 63, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, {0, 7, 14, 14} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422000, 422380, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422381, 425140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 425141, 426260, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 426261, 426520, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 426521, 427940, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 427941, 429060, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429061, 429140, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429141, 429320, {0, 3, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429321, 431940, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 431941, 433980, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 386000, 386720, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 386721, 388260, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 388261, 389520, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 389521, 390880, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 390881, 391060, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 391061, 393680, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 393681, 395380, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 395381, 396660, {60, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 396661, 397760, {60, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 397761, 397980, {60, 60, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 361000, 362180, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362181, 362540, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362541, 364980, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 364981, 365620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 365621, 366820, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 366821, 368420, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 368421, 369240, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 369241, 369620, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 369621, 371740, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 371741, 372040, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 372041, 374540, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 374541, 375540, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 375541, 375980, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 177140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 177141, 177720, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 177721, 178780, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524000, 524100, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524101, 524340, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524341, 524820, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524821, 526040, {2, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 526041, 527140, {2, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527141, 527620, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527621, 528840, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 528841, 530820, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 530821, 533620, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 533621, 534260, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534261, 534400, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534401, 536000, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 536001, 537060, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537061, 537200, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537201, 538000, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 187060, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 187061, 187680, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 187681, 188660, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 188661, 189860, {7, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189861, 189940, {0, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 189941, 190480, {0, 7, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 190481, 191460, {0, 0, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 191461, 191980, {0, 0, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 147380, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 147381, 147860, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 147861, 149200, {140, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 149200, 150180, {140, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 150181, 150660, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 150661, 151200, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151600, 151680, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151681, 153460, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 153461, 153580, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172000, 172460, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172461, 173620, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 173621, 175000, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 160100, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160101, 160160, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160161, 160620, {0, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160621, 161240, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 161241, 162960, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 162961, 164040, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 164041, 164180, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 386000, 386720, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 386721, 388260, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 388261, 389520, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 389521, 390880, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 390881, 391060, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 391061, 393680, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 393681, 395380, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 395381, 396660, {60, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 396661, 397760, {60, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 397761, 398180, {60, 60, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 398181, 398980, {0, 60, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 171800, 172460, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 172461, 173620, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 173621, 177140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 177141, 177720, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 177721, 178800, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151680, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151681, 153460, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 153461, 154480, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 154481, 157300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157301, 157820, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 157821, 160100, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 160101, 160160, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 160161, 160580, {0, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143400, 143940, {0, 0, 140, 140} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143941, 144900, {0, 0, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 144901, 145580, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_285_NR5G_N030), 470000, 470220, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_285_NR5G_N030), 470221, 471980, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514000, 514420, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514421, 514600, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514601, 515260, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 515261, 516100, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 516101, 517220, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 517221, 518060, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 518061, 518900, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 518901, 521300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 521301, 523980, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 376000, 376760, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 376761, 378340, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 378341, 378740, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 378741, 379560, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 379561, 381300, {0, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381301, 381540, {0, 0, 60, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381541, 384000, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 460000, 460660, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 460661, 464280, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 464281, 464820, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 464821, 466340, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 466341, 467080, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 467081, 467420, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 467421, 467620, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 467621, 469140, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 469141, 470220, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 470221, 473780, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 473781, 474740, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 474741, 476280, {2, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476281, 476580, {2, 2, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476581, 476980, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476981, 477540, {2, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 477541, 479080, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 479081, 479780, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 479781, 480000, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 499200, 502300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 502301, 504500, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504501, 505100, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 505101, 505700, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 505701, 506140, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 506141, 507300, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 507301, 508500, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 508501, 508940, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 508941, 511800, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 511801, 514420, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514421, 514600, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514601, 515260, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 515261, 516100, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 516101, 517220, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 517221, 518060, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 518061, 518900, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 518901, 521300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 521301, 524100, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524101, 524340, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524341, 524820, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524821, 526040, {2, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 526041, 527140, {2, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527141, 527620, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527621, 528840, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 528841, 530820, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 530821, 533620, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 533621, 534260, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534261, 534400, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534401, 536000, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 536001, 537060, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537061, 537200, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537201, 537980, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 636667, 637127, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 637128, 637607, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 637608, 638047, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638048, 638367, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638368, 638547, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638548, 638727, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638728, 639307, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639308, 639647, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639648, 640287, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 640288, 640907, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 640908, 641227, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641228, 641687, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641688, 641847, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641848, 641907, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641908, 642627, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642628, 642847, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642848, 643467, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643468, 644227, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 644228, 644387, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 644388, 645007, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645008, 645107, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645108, 645147, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645148, 645947, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645948, 646027, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646028, 646627, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646628, 646666, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422000, 422380, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422381, 425140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 425141, 426260, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 426261, 426520, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 426521, 427940, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 427941, 429060, {0, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429061, 429140, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429141, 429320, {0, 3, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429321, 431940, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 431941, 435060, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 435061, 435780, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 435781, 436480, {3, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 436481, 437860, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 437861, 438580, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 438581, 438720, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 438721, 439280, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 439281, 439980, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 124940, {0, 0, 7, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 124941, 125780, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 125781, 127540, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 127541, 127960, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 127961, 130340, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 130341, 130380, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620000, 620520, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620521, 621080, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621081, 621280, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621281, 621780, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621781, 622000, {1, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622001, 622220, {0, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622221, 622720, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622721, 622780, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622781, 623700, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 623701, 624380, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 624381, 624460, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 624461, 625100, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625101, 625300, {1, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625301, 625380, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625381, 625960, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625961, 626040, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626041, 626900, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626901, 627620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627621, 627680, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627681, 628420, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628421, 628560, {1, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628561, 628620, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628621, 629160, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629161, 629360, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629361, 630080, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630081, 630780, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630781, 631000, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631001, 631720, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631721, 631740, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631741, 631920, {20, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631921, 632340, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 632341, 632680, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 632681, 633280, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633281, 633960, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633961, 634300, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634301, 634880, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634881, 635060, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635061, 635220, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635221, 635540, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635541, 635980, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635981, 636460, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 636461, 637120, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 637121, 637600, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 637601, 638060, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638061, 638380, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638381, 638540, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638541, 638720, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638721, 639300, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639301, 639660, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639661, 640300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 640301, 640920, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 640921, 641220, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641221, 641680, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641681, 641840, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641841, 641920, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641921, 642620, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642621, 642840, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642841, 643460, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643461, 644220, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 644221, 644400, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 644401, 645000, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645001, 645100, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645101, 645140, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645141, 645940, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645941, 646040, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646041, 646620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646621, 647520, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647521, 647560, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647561, 648300, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648301, 648320, {20, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648321, 648460, {20, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648461, 649220, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649221, 649260, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649261, 649800, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649801, 650720, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650721, 650840, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650841, 651480, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651481, 651640, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651641, 651760, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651761, 652420, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652421, 652580, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652581, 652960, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652961, 653900, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 653901, 654140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654141, 654680, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654681, 654960, {1, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654961, 655080, {1, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655081, 655600, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655601, 655900, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655901, 656140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 656141, 657060, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657061, 657440, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657441, 657860, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657861, 658280, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658281, 658380, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658381, 658800, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658801, 659200, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659201, 659300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659301, 660240, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 660241, 660760, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 660761, 661040, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661041, 661600, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661601, 661680, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661681, 661980, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661981, 662460, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662461, 662520, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662521, 663400, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663401, 664060, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664061, 664240, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664241, 664920, {20, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664921, 664980, {20, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 664981, 665180, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665181, 665640, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665641, 665840, {0, 20, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665841, 666560, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666561, 667360, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 667361, 667420, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 667421, 668220, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668221, 668300, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668301, 668360, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668361, 668800, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 668801, 669160, {0, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669161, 669740, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669741, 670620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670621, 670680, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670681, 671540, {1, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671541, 671600, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671601, 671980, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671981, 672480, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672481, 672900, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672901, 673800, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673801, 673980, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673981, 674740, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674741, 674860, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674861, 674900, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674901, 675140, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675141, 675800, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675801, 676080, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676081, 677000, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677001, 677280, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677281, 677920, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677921, 678180, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678181, 678220, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678221, 678300, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678301, 679120, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679121, 679240, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679241, 680000, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620000, 620520, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620521, 621080, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621081, 621280, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621281, 621780, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621781, 622000, {1, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622001, 622220, {0, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622221, 622720, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622721, 622780, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622781, 623700, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 623701, 624380, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 624381, 624460, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 624461, 625100, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625101, 625300, {1, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625301, 625380, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625381, 625960, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625961, 626040, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626041, 626900, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626901, 627620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627621, 627680, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627681, 628420, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628421, 628560, {1, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628561, 628620, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628621, 629160, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629161, 629360, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629361, 630080, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630081, 630780, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630781, 631000, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631001, 631720, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631721, 631740, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631741, 631920, {20, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631921, 632340, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 632341, 632680, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 632681, 633280, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633281, 633960, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633961, 634300, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634301, 634880, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634881, 635060, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635061, 635220, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635221, 635540, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635541, 635980, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635981, 636460, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 636461, 637120, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 637121, 637600, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 637601, 638060, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638061, 638380, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638381, 638540, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638541, 638720, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638721, 639300, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639301, 639660, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639661, 640300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 640301, 640920, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 640921, 641220, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641221, 641680, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641681, 641840, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641841, 641920, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641921, 642620, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642621, 642840, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642841, 643460, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643461, 644220, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 644221, 644400, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 644401, 645000, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645001, 645100, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645101, 645140, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645141, 645940, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645941, 646040, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646041, 646620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646621, 647520, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647521, 647560, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647561, 648300, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648301, 648320, {20, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648321, 648460, {20, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648461, 649220, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649221, 649260, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649261, 649800, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649801, 650720, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650721, 650840, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650841, 651480, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651481, 651640, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651641, 651760, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651761, 652420, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652421, 652580, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652581, 652960, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652961, 653333, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693334, 693814, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693815, 693874, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693875, 694154, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694155, 694754, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694755, 694774, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694775, 695074, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695075, 695694, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695695, 696134, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 696135, 697074, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697075, 697134, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697135, 697314, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697315, 698054, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698055, 698094, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698095, 698254, {0, 20, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698255, 699014, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699015, 699314, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699315, 700254, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700255, 700434, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700435, 700494, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700495, 701354, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 701355, 701394, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 701395, 701414, {0, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 701415, 702334, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702335, 702514, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702515, 703434, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703435, 703654, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703655, 703734, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703735, 704594, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704595, 704674, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704675, 704714, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704715, 705654, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 705655, 705694, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 705695, 706634, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706635, 706814, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706815, 707054, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707055, 707754, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707755, 707974, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707975, 708034, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708035, 708894, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708895, 708974, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708975, 709814, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709815, 709994, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709995, 710354, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710355, 710914, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710915, 711294, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711295, 711354, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711355, 712074, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 712075, 712294, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 712295, 713014, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713015, 713154, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713155, 713654, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713655, 714094, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714095, 714594, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714595, 714674, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714675, 715274, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715275, 715594, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715595, 715614, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715615, 716194, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716195, 716334, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716335, 716974, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716975, 717254, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717255, 717894, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717895, 717994, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717995, 718454, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718455, 718914, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718915, 719394, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719395, 719494, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719495, 720274, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720275, 720434, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720435, 721194, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721195, 721314, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721315, 721654, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721655, 722234, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722235, 722574, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722575, 722654, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722655, 723574, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723575, 723594, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723595, 724514, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724515, 724614, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724615, 724834, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724835, 725554, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725555, 725774, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725775, 725834, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725835, 726754, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726755, 726894, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726895, 727814, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727815, 727934, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727935, 728034, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728035, 728874, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728875, 728954, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728955, 728994, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728995, 729934, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 729935, 730194, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730195, 731114, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731115, 731214, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731215, 731254, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731255, 732154, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 732155, 732194, {0, 20, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 732195, 733094, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 733095, 733333, {0, 0, 0, 0} }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_A_mode[] = { + { + sensor_s5k3j1_setfile_A_mipi_channel, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_channel), + sensor_s5k3j1_setfile_A_mipi_setting, ARRAY_SIZE(sensor_s5k3j1_setfile_A_mipi_setting) + }, +}; + +/*************************************/ +/* ========== SET B =============== */ +/*************************************/ +struct cam_sensor_i2c_reg_array MIPI_SET_B_1196_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x00BB, 0x00, 0x00}, + {0x0312, 0x0000, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_SET_B_1011_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x013C, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_SET_B_1139_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x00B2, 0x00, 0x00}, + {0x0312, 0x0000, 0x00, 0x00}, +}; + +struct cam_sensor_i2c_reg_array MIPI_SET_B_1094_REG_ARRAY[] = { + {0x030E, 0x0003, 0x00, 0x00}, + {0x0310, 0x0156, 0x00, 0x00}, + {0x0312, 0x0001, 0x00, 0x00}, +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1196[] = { + { MIPI_SET_B_1196_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1196_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1011[] = { + { MIPI_SET_B_1011_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1011_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1139[] = { + { MIPI_SET_B_1139_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1139_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_sensor_i2c_reg_setting sensor_s5k3j1_setfile_B_mipi_1094[] = { + { MIPI_SET_B_1094_REG_ARRAY, ARRAY_SIZE(MIPI_SET_B_1094_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_mipi_setting sensor_s5k3j1_setfile_B_mipi_setting[] = { + { "1196 Mhz", 1196, + sensor_s5k3j1_setfile_B_mipi_1196, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1196) }, + { "1011 Mhz", 1011, + sensor_s5k3j1_setfile_B_mipi_1011, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1011) }, + { "1139 Mhz", 1139, + sensor_s5k3j1_setfile_B_mipi_1139, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1139) }, + { "1094 Mhz", 1094, + sensor_s5k3j1_setfile_B_mipi_1094, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_1094) }, +}; + +static const struct cam_mipi_cell_ratings sensor_s5k3j1_setfile_B_mipi_channel[] = { + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, {147, 0, 0, 14} }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_002_GSM_EGSM900), 0, 0, {7, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_003_GSM_DCS1800), 0, 0, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_004_GSM_PCS1900), 0, 0, {0, 0, 66, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10562, 10572, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10573, 10582, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10583, 10635, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10636, 10652, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10653, 10705, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10706, 10736, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10737, 10787, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10788, 10806, {3, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10807, 10835, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_011_WCDMA_WB01), 10836, 10838, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9662, 9718, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9719, 9814, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9815, 9824, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9825, 9838, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9839, 9884, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9885, 9894, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9895, 9908, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9909, 9932, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_012_WCDMA_WB02), 9933, 9938, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1162, 1188, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1189, 1190, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1191, 1203, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1204, 1260, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1261, 1273, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1274, 1365, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1366, 1392, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1393, 1435, {3, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1436, 1443, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1444, 1462, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1463, 1488, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_013_WCDMA_WB03), 1489, 1513, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1537, 1547, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1548, 1557, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1558, 1610, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1611, 1627, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1628, 1680, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1681, 1711, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_014_WCDMA_WB04), 1712, 1738, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4357, 4412, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4413, 4452, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_015_WCDMA_WB05), 4453, 4458, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4387, 4412, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_016_WCDMA_WB06), 4413, 4413, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2237, 2254, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2255, 2260, {2, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2261, 2292, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2293, 2305, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2306, 2324, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2325, 2475, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2476, 2488, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2489, 2496, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2497, 2545, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2546, 2553, {0, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2554, 2558, {40, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_017_WCDMA_WB07), 2559, 2563, {40, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2937, 2986, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 2987, 3052, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3053, 3068, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_018_WCDMA_WB08), 3069, 3088, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 712, 737, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_2_WCDMA, CAM_BAND_029_WCDMA_WB19), 738, 763, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 0, 45, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 46, 65, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 66, 170, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 171, 205, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 206, 310, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 311, 372, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 373, 474, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 475, 512, {3, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 513, 570, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_091_LTE_LB01), 571, 599, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 600, 736, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 737, 929, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 930, 948, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 949, 977, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 978, 1069, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1070, 1088, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1089, 1117, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1118, 1165, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_092_LTE_LB02), 1166, 1199, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1200, 1277, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1278, 1281, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1282, 1307, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1308, 1421, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1422, 1447, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1448, 1630, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1631, 1684, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1685, 1770, {3, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1771, 1787, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1788, 1824, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1825, 1876, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1877, 1927, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_093_LTE_LB03), 1928, 1949, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1950, 1995, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 1996, 2015, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2016, 2120, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2121, 2155, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2156, 2260, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2261, 2322, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_094_LTE_LB04), 2323, 2399, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2400, 2535, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2536, 2615, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_095_LTE_LB05), 2616, 2649, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2750, 2771, {0, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2772, 2809, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2810, 2821, {2, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2822, 2885, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2886, 2911, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2912, 2949, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 2950, 3251, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3252, 3276, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3277, 3292, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3293, 3391, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3392, 3407, {0, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3408, 3416, {40, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3417, 3432, {40, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_097_LTE_LB07), 3433, 3449, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3450, 3572, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3573, 3704, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3705, 3736, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_098_LTE_LB08), 3737, 3799, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5010, 5054, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_102_LTE_LB12), 5055, 5179, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5180, 5194, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5195, 5233, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_103_LTE_LB13), 5234, 5279, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5280, 5290, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5291, 5353, {0, 140, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_104_LTE_LB14), 5354, 5379, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_107_LTE_LB17), 5730, 5849, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5850, 5863, {0, 7, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5864, 5915, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5916, 5935, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_108_LTE_LB18), 5936, 5999, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6000, 6075, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_109_LTE_LB19), 6076, 6149, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6150, 6259, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6260, 6284, {0, 7, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6285, 6377, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6378, 6399, {0, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_110_LTE_LB20), 6400, 6449, {0, 0, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6450, 6520, {60, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6521, 6588, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_111_LTE_LB21), 6589, 6599, {0, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8040, 8176, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8177, 8369, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8370, 8388, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8389, 8417, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8418, 8509, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8510, 8528, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8529, 8557, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8558, 8605, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_115_LTE_LB25), 8606, 8689, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8690, 8713, {0, 7, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8714, 8765, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8766, 8785, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8786, 8925, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 8926, 9005, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_116_LTE_LB26), 9006, 9039, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9210, 9220, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9221, 9283, {0, 140, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9284, 9339, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9340, 9360, {7, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9361, 9479, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9480, 9534, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9535, 9649, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_118_LTE_LB28), 9650, 9659, {0, 7, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9660, 9673, {7, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9674, 9740, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_119_LTE_LB29), 9741, 9769, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_120_LTE_LB30), 9770, 9869, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9920, 9992, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 9993, 10104, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10105, 10132, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10133, 10139, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10140, 10244, {0, 0, 3, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10245, 10279, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10280, 10289, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_122_LTE_LB32), 10290, 10359, {60, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36200, 36254, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36255, 36276, {0, 60, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_124_LTE_LB34), 36277, 36349, {0, 60, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37750, 37751, {2, 0, 40, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37752, 37765, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37766, 37838, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37839, 37851, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37852, 37905, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 37906, 38181, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38182, 38245, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_128_LTE_LB38), 38246, 38249, {0, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38250, 38316, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38317, 38528, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38529, 38531, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38532, 38592, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_129_LTE_LB39), 38593, 38649, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38650, 38702, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38703, 38837, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38838, 38917, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38918, 38933, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38934, 38977, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 38978, 39057, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39058, 39073, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39074, 39109, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39110, 39249, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39250, 39343, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39344, 39483, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39484, 39503, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39504, 39515, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39516, 39643, {40, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_130_LTE_LB40), 39644, 39649, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39650, 39682, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39683, 39752, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39753, 39791, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39792, 39822, {2, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39823, 39892, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39893, 39899, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39900, 39931, {0, 40, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 39932, 40039, {0, 40, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40040, 40251, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40252, 40338, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40339, 40351, {0, 0, 40, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40352, 40391, {2, 0, 40, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40392, 40405, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40406, 40478, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40479, 40491, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40492, 40545, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40546, 40821, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40822, 40885, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40886, 40911, {0, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40912, 40949, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40950, 40961, {2, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 40962, 41025, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41026, 41051, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41052, 41089, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41090, 41391, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41392, 41416, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41417, 41432, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41433, 41531, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41532, 41547, {0, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41548, 41556, {40, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41557, 41572, {40, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_131_LTE_LB41), 41573, 41589, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41590, 41628, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41629, 41696, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41697, 41768, {2, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41769, 41836, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41837, 41900, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41901, 41993, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 41994, 42040, {0, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42041, 42133, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42134, 42227, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42228, 42265, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42266, 42367, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42368, 42405, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42406, 42406, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42407, 42540, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42541, 42546, {0, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42547, 42680, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42681, 42825, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42826, 42835, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42836, 42912, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42913, 42965, {2, 40, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42966, 42975, {0, 40, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 42976, 43052, {0, 40, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43053, 43088, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43089, 43228, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43229, 43404, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43405, 43417, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43418, 43424, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43425, 43544, {40, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43545, 43557, {40, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43558, 43564, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_132_LTE_LB42), 43565, 43589, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55240, 55378, {0, 0, 0, 40} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55379, 55554, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55555, 55567, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55568, 55574, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55575, 55694, {40, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55695, 55707, {40, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55708, 55714, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55715, 55785, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55786, 55925, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 55926, 56073, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56074, 56124, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56125, 56172, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56173, 56213, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56214, 56264, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56265, 56312, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56313, 56332, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56333, 56472, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56473, 56578, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56579, 56694, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56695, 56718, {0, 2, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_138_LTE_LB48), 56719, 56739, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66436, 66481, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66482, 66501, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66502, 66606, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66607, 66641, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66642, 66746, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66747, 66808, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66809, 66910, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66911, 66948, {3, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 66949, 67006, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67007, 67050, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67051, 67146, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67147, 67153, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67154, 67293, {0, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_156_LTE_LB66), 67294, 67335, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68586, 68611, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68612, 68751, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68752, 68912, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68913, 68918, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68919, 68928, {0, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_3_LTE, CAM_BAND_161_LTE_LB71), 68929, 68935, {7, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_051_TDSCDMA_TD1), 0, 0, {6, 3, 0, 126} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_052_TDSCDMA_TD2), 0, 0, {6, 0, 3, 60} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_053_TDSCDMA_TD3), 0, 0, {6, 6, 3, 126} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_054_TDSCDMA_TD4), 0, 0, {3, 3, 12, 6} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_055_TDSCDMA_TD5), 0, 0, {42, 0, 2, 4} }, + { CAM_RAT_BAND(CAM_RAT_4_TDSCDMA, CAM_BAND_056_TDSCDMA_TD6), 0, 0, {3, 3, 3, 63} }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_061_CDMA_BC0), 0, 0, {147, 0, 0, 14} }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_062_CDMA_BC1), 0, 0, {0, 0, 66, 0} }, + { CAM_RAT_BAND(CAM_RAT_5_CDMA, CAM_BAND_071_CDMA_BC10), 0, 0, {0, 7, 255, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422000, 422900, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 422901, 423300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 423301, 425400, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 425401, 426100, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 426101, 428200, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 428201, 429440, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 429441, 431480, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 431481, 432240, {3, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 432241, 433400, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_256_NR5G_N001), 433401, 433980, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 386000, 388720, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 388721, 392580, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 392581, 392960, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 392961, 393540, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 393541, 395380, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 395381, 395760, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 395761, 396340, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 396341, 397300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_257_NR5G_N002), 397301, 397980, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 361000, 362540, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362541, 362620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 362621, 363140, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 363141, 365420, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 365421, 365940, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 365941, 369600, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 369601, 370680, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 370681, 372400, {3, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 372401, 372740, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 372741, 373480, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 373481, 374520, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 374521, 375540, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_258_NR5G_N003), 375541, 375980, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 173800, 176500, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 176501, 178100, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_260_NR5G_N005), 178101, 178780, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524000, 524420, {0, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 524421, 525180, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 525181, 525420, {2, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 525421, 526700, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 526701, 527220, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527221, 527980, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 527981, 534020, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534021, 534520, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534521, 534840, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 534841, 536820, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 536821, 537140, {0, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537141, 537320, {40, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537321, 537640, {40, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_262_NR5G_N007), 537641, 538000, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 185000, 187440, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 187441, 190080, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 190081, 190720, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_263_NR5G_N008), 190721, 191980, {7, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 145800, 146680, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_267_NR5G_N012), 146681, 149200, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 149200, 149480, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 149481, 150260, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_268_NR5G_N013), 150261, 151200, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151600, 151800, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 151801, 153060, {0, 140, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_269_NR5G_N014), 153061, 153580, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172000, 172260, {0, 7, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 172261, 173300, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 173301, 173700, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_273_NR5G_N018), 173701, 175000, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 158200, 160380, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160381, 160880, {0, 7, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 160881, 162740, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 162741, 163180, {0, 7, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_275_NR5G_N020), 163181, 164180, {0, 0, 0, 140} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 386000, 388720, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 388721, 392580, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 392581, 392960, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 392961, 393540, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 393541, 395380, {3, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 395381, 395760, {3, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 395761, 396340, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 396341, 397300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_280_NR5G_N025), 397301, 398980, {0, 0, 60, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 171800, 172260, {0, 7, 140, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 172261, 173300, {0, 7, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 173301, 173700, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 173701, 176500, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 176501, 178100, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_281_NR5G_N026), 178101, 178800, {140, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151600, 151800, {0, 140, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 151801, 153060, {0, 140, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 153061, 154180, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 154181, 154600, {7, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 154601, 156980, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 156981, 158080, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 158081, 160380, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_283_NR5G_N028), 160381, 160580, {0, 7, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143400, 143660, {7, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 143661, 145000, {7, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_284_NR5G_N029), 145001, 145580, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_285_NR5G_N030), 470000, 471980, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514000, 514020, {2, 0, 40, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514021, 514300, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 514301, 515760, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 515761, 516020, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 516021, 517100, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 517101, 522620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 522621, 523900, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_293_NR5G_N038), 523901, 523980, {0, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 376000, 377320, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 377321, 381560, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381561, 381620, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 381621, 382840, {3, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_294_NR5G_N039), 382841, 384000, {3, 3, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 460000, 461040, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 461041, 463740, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 463741, 465340, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 465341, 465660, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 465661, 466540, {2, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 466541, 468140, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 468141, 468460, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 468461, 469180, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 469181, 471980, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 471981, 473860, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 473861, 476660, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 476661, 477060, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 477061, 477300, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 477301, 479860, {40, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_295_NR5G_N040), 479861, 480000, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 499200, 499840, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 499841, 501240, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 501241, 502020, {2, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 502021, 502640, {2, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 502641, 504040, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504041, 504180, {0, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504181, 504820, {0, 40, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 504821, 506980, {0, 40, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 506981, 511220, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 511221, 512960, {0, 0, 40, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 512961, 513220, {0, 0, 40, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 513221, 514020, {2, 0, 40, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514021, 514300, {2, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 514301, 515760, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 515761, 516020, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 516021, 517100, {0, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 517101, 522620, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 522621, 523900, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 523901, 524420, {0, 0, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 524421, 525180, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 525181, 525420, {2, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 525421, 526700, {2, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 526701, 527220, {2, 2, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527221, 527980, {2, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 527981, 534020, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534021, 534520, {0, 0, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534521, 534840, {0, 2, 2, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 534841, 536820, {0, 2, 2, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 536821, 537140, {0, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537141, 537320, {40, 2, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537321, 537640, {40, 0, 0, 2} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_296_NR5G_N041), 537641, 537980, {40, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 636667, 637567, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 637568, 638747, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638748, 638847, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638848, 638887, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 638888, 639687, {20, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639688, 639767, {20, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639768, 639807, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 639808, 640287, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 640288, 641227, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 641228, 642207, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642208, 642547, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642548, 642867, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 642868, 643147, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643148, 643487, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643488, 643807, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643808, 643947, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 643948, 644867, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 644868, 645587, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 645588, 646347, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646348, 646507, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_303_NR5G_N048), 646508, 646666, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422000, 422900, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 422901, 423300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 423301, 425400, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 425401, 426100, {0, 3, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 426101, 428200, {0, 0, 0, 3} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 428201, 429440, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 429441, 431480, {3, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 431481, 432240, {3, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 432241, 433400, {0, 0, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 433401, 434280, {0, 3, 3, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 434281, 436200, {0, 3, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 436201, 436340, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 436341, 439140, {0, 0, 0, 60} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_321_NR5G_N066), 439141, 439980, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123400, 123900, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 123901, 126700, {0, 0, 7, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 126701, 129920, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 129921, 130040, {0, 0, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 130041, 130240, {0, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_326_NR5G_N071), 130241, 130380, {7, 7, 0, 7} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620000, 620700, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 620701, 621980, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 621981, 622060, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622061, 622920, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622921, 622980, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 622981, 623560, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 623561, 623860, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 623861, 624500, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 624501, 625360, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625361, 625700, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 625701, 626300, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626301, 626640, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626641, 626920, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 626921, 627360, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627361, 627840, {1, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 627841, 628300, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628301, 628720, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 628721, 629340, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629341, 629660, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 629661, 630280, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630281, 630900, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 630901, 631160, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631161, 631840, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 631841, 632100, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 632101, 633000, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633001, 633040, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633041, 633920, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 633921, 634900, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634901, 634960, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 634961, 635480, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635481, 635820, {1, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635821, 635900, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 635901, 636400, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 636401, 636640, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 636641, 637580, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 637581, 638760, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638761, 638840, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638841, 638880, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 638881, 639680, {20, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639681, 639780, {20, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639781, 639820, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 639821, 640300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 640301, 641220, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 641221, 642220, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642221, 642560, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642561, 642880, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 642881, 643140, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643141, 643480, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643481, 643800, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643801, 643940, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 643941, 644880, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 644881, 645580, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 645581, 646360, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646361, 646520, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646521, 646860, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 646861, 647280, {1, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647281, 647580, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647581, 647800, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 647801, 648520, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648521, 648960, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 648961, 649880, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 649881, 650140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650141, 650860, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 650861, 651080, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651081, 651240, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651241, 651780, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 651781, 652160, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652161, 652320, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 652321, 653260, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 653261, 653940, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 653941, 654840, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654841, 654880, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 654881, 655700, {1, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655701, 655780, {1, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655781, 655820, {0, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 655821, 656620, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 656621, 657740, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 657741, 658540, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658541, 658680, {0, 0, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658681, 658840, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 658841, 659060, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659061, 659460, {20, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659461, 659760, {20, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 659761, 660000, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 660001, 661540, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 661541, 662180, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662181, 662440, {0, 0, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662441, 662480, {0, 1, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662481, 662820, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 662821, 663120, {1, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663121, 663360, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663361, 663760, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 663761, 665340, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665341, 665800, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665801, 665820, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 665821, 666280, {0, 1, 20, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666281, 666740, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666741, 666760, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666761, 666800, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 666801, 667740, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 667741, 669140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669141, 669180, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669181, 669480, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 669481, 670060, {0, 20, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670061, 670100, {0, 20, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670101, 670400, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670401, 670800, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 670801, 671740, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 671741, 672540, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672541, 672940, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 672941, 673120, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673121, 673480, {0, 1, 1, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673481, 673860, {0, 0, 1, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 673861, 674060, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674061, 674780, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 674781, 675720, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675721, 675920, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 675921, 676720, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676721, 676780, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676781, 676860, {0, 1, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 676861, 677660, {0, 0, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677661, 677700, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 677701, 678780, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 678781, 679280, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679281, 679700, {20, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_332_NR5G_N077), 679701, 680000, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620000, 620700, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 620701, 621980, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 621981, 622060, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622061, 622920, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622921, 622980, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 622981, 623560, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 623561, 623860, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 623861, 624500, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 624501, 625360, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625361, 625700, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 625701, 626300, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626301, 626640, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626641, 626920, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 626921, 627360, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627361, 627840, {1, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 627841, 628300, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628301, 628720, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 628721, 629340, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629341, 629660, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 629661, 630280, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630281, 630900, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 630901, 631160, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631161, 631840, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 631841, 632100, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 632101, 633000, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633001, 633040, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633041, 633920, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 633921, 634900, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634901, 634960, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 634961, 635480, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635481, 635820, {1, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635821, 635900, {0, 20, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 635901, 636400, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 636401, 636640, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 636641, 637580, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 637581, 638760, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638761, 638840, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638841, 638880, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 638881, 639680, {20, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639681, 639780, {20, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639781, 639820, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 639821, 640300, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 640301, 641220, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 641221, 642220, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642221, 642560, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642561, 642880, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 642881, 643140, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643141, 643480, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643481, 643800, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643801, 643940, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 643941, 644880, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 644881, 645580, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 645581, 646360, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646361, 646520, {0, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646521, 646860, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 646861, 647280, {1, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647281, 647580, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647581, 647800, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 647801, 648520, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648521, 648960, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 648961, 649880, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 649881, 650140, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650141, 650860, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 650861, 651080, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651081, 651240, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651241, 651780, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 651781, 652160, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652161, 652320, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 652321, 653260, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_333_NR5G_N078), 653261, 653333, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693334, 693714, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 693715, 694734, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 694735, 695014, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695015, 695674, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695675, 695714, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695715, 695954, {0, 0, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 695955, 696134, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 696135, 696654, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 696655, 697074, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 697075, 698654, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698655, 698734, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 698735, 699514, {20, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699515, 699594, {20, 1, 1, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699595, 699654, {20, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 699655, 700454, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 700455, 702314, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702315, 702714, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702715, 702894, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 702895, 703234, {1, 20, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703235, 703314, {1, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703315, 703654, {1, 20, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703655, 703814, {0, 20, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 703815, 704234, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 704235, 705954, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 705955, 706254, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706255, 706694, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706695, 706894, {1, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 706895, 707114, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707115, 707194, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707195, 707634, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 707635, 708034, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 708035, 709614, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709615, 709634, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 709635, 710534, {0, 1, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710535, 710554, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710555, 710694, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710695, 710914, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 710915, 711634, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711635, 711834, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 711835, 712994, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 712995, 713254, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713255, 713934, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 713935, 714194, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714195, 714674, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714675, 714694, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 714695, 715614, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715615, 715634, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 715635, 716374, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716375, 716894, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 716895, 717294, {0, 1, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717295, 717834, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 717835, 718494, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718495, 718674, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 718675, 719434, {20, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719435, 719594, {20, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719595, 719734, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 719735, 720554, {0, 20, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720555, 720674, {0, 20, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 720675, 721474, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 721475, 722294, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722295, 722654, {0, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 722655, 723114, {1, 0, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723115, 723234, {1, 1, 20, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723235, 723594, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 723595, 724034, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724035, 724194, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 724195, 725134, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 725135, 726094, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726095, 726474, {0, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726475, 726654, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 726655, 727034, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727035, 727414, {1, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727415, 727574, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727575, 727854, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 727855, 728774, {0, 0, 0, 20} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 728775, 729854, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 729855, 729894, {0, 1, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 729895, 730634, {0, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730635, 730774, {1, 1, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730775, 730834, {1, 0, 1, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 730835, 731494, {1, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731495, 731574, {1, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 731575, 732434, {0, 0, 0, 1} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 732435, 733214, {0, 0, 0, 0} }, + { CAM_RAT_BAND(CAM_RAT_7_NR5G, CAM_BAND_334_NR5G_N079), 733215, 733333, {0, 1, 0, 0} }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_B_mode[] = { + { + sensor_s5k3j1_setfile_B_mipi_channel, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_channel), + sensor_s5k3j1_setfile_B_mipi_setting, ARRAY_SIZE(sensor_s5k3j1_setfile_B_mipi_setting) + }, +}; + +/*************************************/ +/* ========== DUMMY ================ */ +/*************************************/ +struct cam_sensor_i2c_reg_array MIPI_FRONT_DUMMY_REG_ARRAY[] = { +}; + +static const struct cam_sensor_i2c_reg_setting sensor_front_setfile_dummy[] = { + { MIPI_FRONT_DUMMY_REG_ARRAY, ARRAY_SIZE(MIPI_FRONT_DUMMY_REG_ARRAY), + CAMERA_SENSOR_I2C_TYPE_WORD, CAMERA_SENSOR_I2C_TYPE_WORD, 0 } +}; + +static const struct cam_mipi_setting sensor_front_setfile_dummy_mipi_setting[] = { + { "DUMMY Msps", 0, + sensor_front_setfile_dummy, ARRAY_SIZE(sensor_front_setfile_dummy) }, +}; + +static const struct cam_mipi_cell_ratings sensor_front_setfile_dummy_channel[] = { + { CAM_RAT_BAND(CAM_RAT_1_GSM, CAM_BAND_001_GSM_GSM850), 0, 0, {0} }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_C_mode[] = { + { + sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), + sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) + }, +}; + +static const struct cam_mipi_sensor_mode sensor_front_mipi_D_mode[] = { + { + sensor_front_setfile_dummy_channel, ARRAY_SIZE(sensor_front_setfile_dummy_channel), + sensor_front_setfile_dummy_mipi_setting, ARRAY_SIZE(sensor_front_setfile_dummy_mipi_setting) + }, +}; + +#endif /* _CAM_SENSOR_ADAPTIVE_MIPI_S5K3J1_2_0_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3k1.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3k1.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu_2_0_q6a.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu_2_0_q6a.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu_uw_2_0.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5k3lu_uw_2_0.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5kgn3.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5kgn3.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5khp2.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/adaptive_mipi/cam_sensor_adaptive_mipi_s5khp2.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index a4c68d2803..fddc66849f 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -693,7 +693,7 @@ static int cam_sensor_handle_res_info(struct cam_sensor_res_info *res_info, s_ctrl->is_res_info_updated = true; /* If request id is 0, it will be during an initial config/acquire */ - CAM_DBG(CAM_SENSOR, + CAM_INFO(CAM_SENSOR, "Sensor[%s-%d] Feature: 0x%x updated for request id: %lu, res index: %u, width: 0x%x, height: 0x%x, capability: %s, fps: %u", s_ctrl->sensor_name, s_ctrl->soc_info.index, s_ctrl->sensor_res[idx].feature_mask, @@ -1638,13 +1638,16 @@ int cam_sensor_match_id(struct cam_sensor_ctrl_t *s_ctrl) return -EINVAL; } + if (s_ctrl->hw_no_ops) + return rc; + rc = camera_io_dev_read( &(s_ctrl->io_master_info), slave_info->sensor_id_reg_addr, &chipid, s_ctrl->sensor_probe_addr_type, s_ctrl->sensor_probe_data_type, true); - CAM_INFO(CAM_SENSOR, "%s read id: 0x%x expected id 0x%x:", + CAM_DBG(CAM_SENSOR, "%s read id: 0x%x expected id 0x%x:", s_ctrl->sensor_name, chipid, slave_info->sensor_id); if (cam_sensor_id_by_mask(s_ctrl, chipid) != slave_info->sensor_id) { @@ -1689,12 +1692,11 @@ int cam_sensor_stream_off(struct cam_sensor_ctrl_t *s_ctrl) CAM_CONVERT_TIMESTAMP_FORMAT(ts, hrs, min, sec, ms); CAM_INFO(CAM_SENSOR, - "%llu:%llu:%llu.%llu CAM_STOP_DEV Success for %s sensor_id:0x%x,sensor_slave_addr:0x%x last_applied: %lld", + "%llu:%llu:%llu.%llu CAM_STOP_DEV Success for %s sensor_id:0x%x,sensor_slave_addr:0x%x", hrs, min, sec, ms, s_ctrl->sensor_name, s_ctrl->sensordata->slave_info.sensor_id, - s_ctrl->sensordata->slave_info.sensor_slave_addr, - s_ctrl->last_applied_req); + s_ctrl->sensordata->slave_info.sensor_slave_addr); end: return rc; @@ -1824,7 +1826,7 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, { int rc = 0, pkt_opcode = 0; struct cam_control *cmd = (struct cam_control *)arg; - struct cam_sensor_power_ctrl_t *power_info = NULL; + struct cam_sensor_power_ctrl_t *power_info = NULL; struct timespec64 ts; uint64_t ms, sec, min, hrs; #if defined(CONFIG_SAMSUNG_READ_BPC_FROM_OTP) @@ -1839,8 +1841,8 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, return -EINVAL; } - power_info = &s_ctrl->sensordata->power_info; - + power_info = &s_ctrl->sensordata->power_info; + if (cmd->op_code != CAM_SENSOR_PROBE_CMD) { if (cmd->handle_type != CAM_HANDLE_USER_POINTER) { CAM_ERR(CAM_SENSOR, "Invalid handle type: %d", @@ -2449,9 +2451,10 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, func0(s_ctrl); } #endif - rc = cam_sensor_i2c_read_data( - &s_ctrl->i2c_data.read_settings, - &s_ctrl->io_master_info); + if (!s_ctrl->hw_no_ops) + rc = cam_sensor_i2c_read_data( + &s_ctrl->i2c_data.read_settings, + &s_ctrl->io_master_info); if (rc < 0) { CAM_ERR(CAM_SENSOR, "%s: cannot read data: %d", s_ctrl->sensor_name, rc); @@ -2557,6 +2560,10 @@ int cam_sensor_establish_link(struct cam_req_mgr_core_dev_link_setup *link) int cam_sensor_power(struct v4l2_subdev *sd, int on) { struct cam_sensor_ctrl_t *s_ctrl = v4l2_get_subdevdata(sd); + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "s_ctrl ptr is NULL"); + return -EINVAL; + } mutex_lock(&(s_ctrl->cam_sensor_mutex)); if (!on && s_ctrl->sensor_state == CAM_SENSOR_START) { @@ -2570,7 +2577,7 @@ int cam_sensor_power(struct v4l2_subdev *sd, int on) int cam_sensor_power_up(struct cam_sensor_ctrl_t *s_ctrl) { - int rc; + int rc = 0; struct cam_sensor_power_ctrl_t *power_info; struct cam_camera_slave_info *slave_info; struct cam_hw_soc_info *soc_info = &s_ctrl->soc_info; @@ -2586,6 +2593,8 @@ int cam_sensor_power_up(struct cam_sensor_ctrl_t *s_ctrl) hw_bigdata_init_mipi_param_sensor(s_ctrl); } #endif + if (s_ctrl->hw_no_ops) + return rc; power_info = &s_ctrl->sensordata->power_info; slave_info = &(s_ctrl->sensordata->slave_info); @@ -2656,6 +2665,8 @@ int cam_sensor_power_down(struct cam_sensor_ctrl_t *s_ctrl) hw_bigdata_deinit_mipi_param_sensor(s_ctrl); } #endif + if (s_ctrl->hw_no_ops) + return rc; power_info = &s_ctrl->sensordata->power_info; soc_info = &s_ctrl->soc_info; @@ -2760,9 +2771,10 @@ int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, &to_dbg_sen_id, &sen_upd_evt_type); #endif - rc = cam_sensor_i2c_modes_util( - &(s_ctrl->io_master_info), - i2c_list); + if (!s_ctrl->hw_no_ops) + rc = cam_sensor_i2c_modes_util( + &(s_ctrl->io_master_info), + i2c_list); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed to apply settings: %d", @@ -2811,9 +2823,10 @@ int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, &to_dbg_sen_id, &sen_upd_evt_type); #endif - rc = cam_sensor_i2c_modes_util( - &(s_ctrl->io_master_info), - i2c_list); + if (!s_ctrl->hw_no_ops) + rc = cam_sensor_i2c_modes_util( + &(s_ctrl->io_master_info), + i2c_list); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed to apply settings: %d", @@ -2978,7 +2991,7 @@ int32_t cam_sensor_notify_frame_skip(struct cam_req_mgr_apply_request *apply) return -EINVAL; } - CAM_INFO(CAM_REQ, " Sensor[%d] handle frame skip for req id: %lld", + CAM_DBG(CAM_REQ, " Sensor[%d] handle frame skip for req id: %lld", s_ctrl->soc_info.index, apply->request_id); trace_cam_notify_frame_skip("Sensor", apply->request_id); mutex_lock(&(s_ctrl->cam_sensor_mutex)); @@ -3086,7 +3099,7 @@ int32_t cam_sensor_flush_request(struct cam_req_mgr_flush_request *flush_req) if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ && !cancel_req_id_found) - CAM_INFO(CAM_SENSOR, + CAM_DBG(CAM_SENSOR, "Flush request id:%lld not found in the pending list", flush_req->req_id); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c index 9003db6c95..bbde2805ec 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c @@ -386,7 +386,7 @@ static int cam_sensor_i2c_driver_probe(struct i2c_client *client, return -EFAULT; } - CAM_ERR(CAM_SENSOR, "Adding sensor component: %s", client->name); + CAM_DBG(CAM_SENSOR, "Adding sensor component"); rc = component_add(&client->dev, &cam_sensor_i2c_component_ops); if (rc) CAM_ERR(CAM_SENSOR, "failed to add component rc: %d", rc); @@ -511,7 +511,7 @@ static int cam_sensor_component_bind(struct device *dev, s_ctrl->sensordata->power_info.dev = &pdev->dev; platform_set_drvdata(pdev, s_ctrl); s_ctrl->sensor_state = CAM_SENSOR_INIT; - CAM_ERR(CAM_SENSOR, "Component bound successfully for %s", pdev->name); + CAM_DBG(CAM_SENSOR, "Component bound successfully for %s", pdev->name); g_i3c_sensor_data[soc_info->index].s_ctrl = s_ctrl; init_completion(&g_i3c_sensor_data[soc_info->index].probe_complete); @@ -609,7 +609,7 @@ static int32_t cam_sensor_driver_platform_probe( { int rc = 0; - CAM_INFO(CAM_SENSOR, "Adding Sensor component for %s", pdev->name); + CAM_DBG(CAM_SENSOR, "Adding Sensor component for %s", pdev->name); rc = component_add(&pdev->dev, &cam_sensor_component_ops); if (rc) CAM_ERR(CAM_SENSOR, "failed to add component rc: %d", rc); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h index fcbbc7767a..aa9b448e84 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h @@ -118,6 +118,7 @@ struct cam_sensor_dev_res_info { * @is_stopped_by_user: Indicate if sensor has been stopped by userland * @stream_off_after_eof: Indicates if sensor needs to stream off after eof * @is_res_info_updated: Indicate if resolution info is updated + * @hw_no_ops: To determine whether HW operations need to be disabled */ struct cam_sensor_ctrl_t { char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; @@ -155,6 +156,7 @@ struct cam_sensor_ctrl_t { bool is_stopped_by_user; bool stream_off_after_eof; bool is_res_info_updated; + bool hw_no_ops; #if defined(CONFIG_SAMSUNG_DEBUG_SENSOR_TIMING) uint32_t camera_shooting_mode; #endif diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c index f3b711beaa..7b3077fb0d 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c @@ -388,6 +388,10 @@ static int32_t cam_sensor_driver_get_dt_data(struct cam_sensor_ctrl_t *s_ctrl) goto FREE_SENSOR_DATA; } + if (!of_property_read_bool(of_node, "hw-no-ops")) + s_ctrl->hw_no_ops = false; + else + s_ctrl->hw_no_ops = true; #if defined(CONFIG_CAMERA_SYSFS_V2) cam_sensor_get_dt_camera_info(s_ctrl, of_node); if (rc < 0) { diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c index e41c917a34..4b4134f728 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c @@ -188,7 +188,7 @@ static int32_t cam_cci_i2c_compare(struct cam_sensor_cci_client *client, if (data == (reg_data & ~data_mask)) return I2C_COMPARE_MATCH; else { - CAM_DBG(CAM_SENSOR, + CAM_WARN(CAM_SENSOR, "mismatch: reg_data 0x%x: data: 0x%x, data_mask: 0x%x", reg_data, data, data_mask); return I2C_COMPARE_MISMATCH; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c index 5744c8ac7d..79de829aca 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c @@ -56,7 +56,7 @@ static int32_t cam_qup_i2c_rxdata( static inline void cam_qup_i2c_txdata_fill( struct camera_io_master *dev_client, unsigned char *txdata, - int length, struct i2c_msg *msgs, int curr_mindx) + uint16_t length, struct i2c_msg *msgs, int curr_mindx) { msgs[curr_mindx].addr = dev_client->client->addr >> 1; msgs[curr_mindx].flags = 0; @@ -66,7 +66,7 @@ static inline void cam_qup_i2c_txdata_fill( static int32_t cam_qup_i2c_txdata( struct camera_io_master *dev_client, unsigned char *txdata, - int length) + uint16_t length) { int32_t rc = 0; uint16_t saddr = dev_client->client->addr >> 1; @@ -271,9 +271,9 @@ static inline int32_t cam_qup_i2c_write_optimized(struct camera_io_master *clien unsigned char *buf) { int32_t rc = 0; - uint8_t len = 0; + uint16_t len = 0; struct cam_sensor_i2c_reg_array *reg_setting_previous = NULL; - uint32_t offset = 0; + uint16_t offset = 0; struct cam_sensor_i2c_reg_array *reg_setting; enum camera_sensor_i2c_type addr_type; enum camera_sensor_i2c_type data_type; @@ -457,7 +457,7 @@ static int32_t cam_qup_i2c_write_burst(struct camera_io_master *client, { int i; int32_t rc = 0; - uint32_t len = 0; + uint16_t len = 0; unsigned char *buf = NULL; struct cam_sensor_i2c_reg_array *reg_setting; enum camera_sensor_i2c_type addr_type; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i3c.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i3c.c index fcfe37a9bd..038cb52d1d 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i3c.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i3c.c @@ -50,7 +50,7 @@ static int cam_qup_i3c_rxdata(struct i3c_device *dev_client, unsigned char *rxda } static inline void cam_qup_i3c_txdata_fill(struct camera_io_master *dev_client, - unsigned char *txdata, int length, + unsigned char *txdata, uint16_t length, struct i3c_priv_xfer *msgs, int curr_mindx) { msgs[curr_mindx].rnw = 0; @@ -59,7 +59,7 @@ static inline void cam_qup_i3c_txdata_fill(struct camera_io_master *dev_client, } static int cam_qup_i3c_txdata(struct camera_io_master *dev_client, unsigned char *txdata, - int length) + uint16_t length) { int rc; uint32_t us = 0; @@ -262,9 +262,9 @@ static inline int32_t cam_qup_i3c_write_optimized(struct camera_io_master *clien unsigned char *buf) { int32_t rc = 0; - uint8_t len = 0; + uint16_t len = 0; struct cam_sensor_i2c_reg_array *reg_setting_previous = NULL; - uint32_t offset = 0; + uint16_t offset = 0; struct cam_sensor_i2c_reg_array *reg_setting; enum camera_sensor_i2c_type addr_type; enum camera_sensor_i2c_type data_type; @@ -456,7 +456,7 @@ static int cam_qup_i3c_write_burst(struct camera_io_master *client, { int i; int rc; - uint32_t len = 0; + uint16_t len = 0; unsigned char *buf; struct cam_sensor_i2c_reg_array *reg_setting; enum camera_sensor_i2c_type addr_type; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index 5c1ebfcd29..961183753b 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -294,10 +294,11 @@ int32_t cam_sensor_handle_random_write( struct list_head **list) { struct i2c_settings_list *i2c_list; - int32_t rc = 0, cnt; + int32_t rc = 0, cnt, payload_count; + payload_count = cam_cmd_i2c_random_wr->header.count; i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, - cam_cmd_i2c_random_wr->header.count); + payload_count); if (i2c_list == NULL || i2c_list->i2c_settings.reg_setting == NULL) { CAM_ERR(CAM_SENSOR_UTIL, "Failed in allocating i2c_list"); @@ -306,15 +307,14 @@ int32_t cam_sensor_handle_random_write( *cmd_length_in_bytes = (sizeof(struct i2c_rdwr_header) + sizeof(struct i2c_random_wr_payload) * - (cam_cmd_i2c_random_wr->header.count)); + payload_count); i2c_list->op_code = CAM_SENSOR_I2C_WRITE_RANDOM; i2c_list->i2c_settings.addr_type = cam_cmd_i2c_random_wr->header.addr_type; i2c_list->i2c_settings.data_type = cam_cmd_i2c_random_wr->header.data_type; - for (cnt = 0; cnt < (cam_cmd_i2c_random_wr->header.count); - cnt++) { + for (cnt = 0; cnt < payload_count; cnt++) { i2c_list->i2c_settings.reg_setting[cnt].reg_addr = cam_cmd_i2c_random_wr->random_wr_payload[cnt].reg_addr; i2c_list->i2c_settings.reg_setting[cnt].reg_data = @@ -334,10 +334,11 @@ int32_t cam_sensor_handle_continuous_write( struct list_head **list) { struct i2c_settings_list *i2c_list; - int32_t rc = 0, cnt; + int32_t rc = 0, cnt, payload_count; + payload_count = cam_cmd_i2c_continuous_wr->header.count; i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, - cam_cmd_i2c_continuous_wr->header.count); + payload_count); if (i2c_list == NULL || i2c_list->i2c_settings.reg_setting == NULL) { CAM_ERR(CAM_SENSOR_UTIL, "Failed in allocating i2c_list"); @@ -347,7 +348,7 @@ int32_t cam_sensor_handle_continuous_write( *cmd_length_in_bytes = (sizeof(struct i2c_rdwr_header) + sizeof(cam_cmd_i2c_continuous_wr->reg_addr) + sizeof(struct cam_cmd_read) * - (cam_cmd_i2c_continuous_wr->header.count)); + (payload_count)); if (cam_cmd_i2c_continuous_wr->header.op_code == CAMERA_SENSOR_I2C_OP_CONT_WR_BRST) i2c_list->op_code = CAM_SENSOR_I2C_WRITE_BURST; @@ -364,8 +365,7 @@ int32_t cam_sensor_handle_continuous_write( i2c_list->i2c_settings.size = cam_cmd_i2c_continuous_wr->header.count; - for (cnt = 0; cnt < (cam_cmd_i2c_continuous_wr->header.count); - cnt++) { + for (cnt = 0; cnt < payload_count; cnt++) { i2c_list->i2c_settings.reg_setting[cnt].reg_addr = cam_cmd_i2c_continuous_wr->reg_addr; i2c_list->i2c_settings.reg_setting[cnt].reg_data = @@ -889,7 +889,7 @@ int cam_sensor_i2c_command_parser( (struct cam_cmd_i2c_continuous_rd *)cmd_buf; if (remain_len - byte_cnt < - sizeof(struct cam_cmd_i2c_continuous_rd)) { + sizeof(struct cam_cmd_i2c_continuous_rd)) { CAM_ERR(CAM_SENSOR_UTIL, "Not enough buffer space"); rc = -EINVAL; @@ -1265,7 +1265,6 @@ int32_t msm_camera_fill_vreg_params( if (j == num_vreg) power_setting[i].seq_val = INVALID_VREG; break; - case SENSOR_CUSTOM_REG2: for (j = 0; j < num_vreg; j++) { @@ -1481,22 +1480,29 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, int32_t i = 0, pwr_up = 0, pwr_down = 0; struct cam_sensor_power_setting *pwr_settings; void *ptr = cmd_buf, *scr; - struct cam_cmd_power *pwr_cmd = (struct cam_cmd_power *)cmd_buf; struct common_header *cmm_hdr = (struct common_header *)cmd_buf; + struct cam_cmd_power *pwr_cmd = + kzalloc(sizeof(struct cam_cmd_power), GFP_KERNEL); + if (!pwr_cmd) + return -ENOMEM; + memcpy(pwr_cmd, cmd_buf, sizeof(struct cam_cmd_power)); if (!pwr_cmd || !cmd_length || cmd_buf_len < (size_t)cmd_length || cam_sensor_validate(cmd_buf, cmd_buf_len)) { CAM_ERR(CAM_SENSOR_UTIL, "Invalid Args: pwr_cmd %pK, cmd_length: %d", pwr_cmd, cmd_length); - return -EINVAL; + rc = -EINVAL; + goto free_power_command; } power_info->power_setting_size = 0; power_info->power_setting = kzalloc(sizeof(struct cam_sensor_power_setting) * MAX_POWER_CONFIG, GFP_KERNEL); - if (!power_info->power_setting) - return -ENOMEM; + if (!power_info->power_setting) { + rc = -ENOMEM; + goto free_power_command; + } power_info->power_down_setting_size = 0; power_info->power_down_setting = @@ -1506,7 +1512,8 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, kfree(power_info->power_setting); power_info->power_setting = NULL; power_info->power_setting_size = 0; - return -ENOMEM; + rc = -ENOMEM; + goto free_power_command; } while (tot_size < cmd_length) { @@ -1690,7 +1697,7 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, } } - return rc; + goto free_power_command; free_power_settings: kfree(power_info->power_down_setting); kfree(power_info->power_setting); @@ -1698,6 +1705,9 @@ free_power_settings: power_info->power_setting = NULL; power_info->power_down_setting_size = 0; power_info->power_setting_size = 0; +free_power_command: + kfree(pwr_cmd); + pwr_cmd = NULL; return rc; } diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/kunit_test/cam_hw_bigdata_test.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/kunit_test/cam_hw_bigdata_test.h index f41245e359..7e26b7dc5f 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/kunit_test/cam_hw_bigdata_test.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_sensor_utils/kunit_test/cam_hw_bigdata_test.h @@ -29,4 +29,4 @@ void hw_bigdata_mipi_sensor_front_top_test(struct kunit *test); void hw_bigdata_mipi_init_param_test(struct kunit *test); void hw_bigdata_file_test(struct kunit *test); -#endif /* _CAM_HW_BIGDATA_TEST_H_ */ \ No newline at end of file +#endif /* _CAM_HW_BIGDATA_TEST_H_ */ diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_core.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_core.c index d86eb0498a..943bc9ca12 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_core.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_tpg_core.h" @@ -14,7 +14,8 @@ int cam_tpg_shutdown(struct cam_tpg_device *tpg_dev) if (tpg_dev != NULL) { CAM_INFO(CAM_TPG, "TPG[%d] shutdown cleanup.", tpg_dev->soc_info.index); - tpg_hw_reset(&tpg_dev->tpg_hw); + if (!tpg_dev->hw_no_ops) + tpg_hw_reset(&tpg_dev->tpg_hw); tpg_dev->state = CAM_TPG_STATE_INIT; } return 0; @@ -149,7 +150,11 @@ static int cam_tpg_process_crm_evt( switch(event->evt_type) { case CAM_REQ_MGR_LINK_EVT_SOF_FREEZE: - tpg_hw_dump_status(&tpg_dev->tpg_hw); + if (tpg_dev->hw_no_ops) { + CAM_DBG(CAM_TPG, "TPG[%d] SOF Freeze hw_no_ops: %d", + tpg_dev->soc_info.index, tpg_dev->hw_no_ops); + } else + tpg_hw_dump_status(&tpg_dev->tpg_hw); break; default: CAM_DBG(CAM_TPG, "Got crm event notification: %d", event->evt_type); @@ -286,11 +291,13 @@ static int __cam_tpg_handle_release_dev( if (tpg_dev->state == CAM_TPG_STATE_START) { CAM_DBG(CAM_TPG, "TPG[%d] release from start state", tpg_dev->soc_info.index); - rc = tpg_hw_stop(&tpg_dev->tpg_hw); - if (rc < 0) { - CAM_ERR(CAM_TPG, "TPG[%d] unable to stop tpg", + if (!tpg_dev->hw_no_ops) { + rc = tpg_hw_stop(&tpg_dev->tpg_hw); + if (rc < 0) { + CAM_ERR(CAM_TPG, "TPG[%d] unable to stop tpg", tpg_dev->soc_info.index); - return rc; + return rc; + } } } rc = tpg_hw_release(&tpg_dev->tpg_hw); @@ -330,12 +337,16 @@ static int __cam_tpg_handle_start_dev( tpg_dev->soc_info.index, tpg_dev->state); return -EINVAL; } - rc = tpg_hw_start(&tpg_dev->tpg_hw); + if (!tpg_dev->hw_no_ops) + rc = tpg_hw_start(&tpg_dev->tpg_hw); + if (rc) { - CAM_ERR(CAM_TPG, "TPG[%d] START_DEV failed", tpg_dev->soc_info.index); + CAM_ERR(CAM_TPG, "TPG[%d] START_DEV failed hw_no_ops: %d", + tpg_dev->soc_info.index, tpg_dev->hw_no_ops); } else { tpg_dev->state = CAM_TPG_STATE_START; - CAM_INFO(CAM_TPG, "TPG[%d] START_DEV done.", tpg_dev->soc_info.index); + CAM_INFO(CAM_TPG, "TPG[%d] START_DEV done hw_no_ops: %d.", + tpg_dev->soc_info.index, tpg_dev->hw_no_ops); } return rc; @@ -359,19 +370,18 @@ static int __cam_tpg_handle_stop_dev( return -EINVAL; } if (tpg_dev->state != CAM_TPG_STATE_START) { - CAM_ERR(CAM_TPG, "TPG[%d] not in right state[%d] to stop", + CAM_WARN(CAM_TPG, "TPG[%d] not in right state[%d] to stop", tpg_dev->soc_info.index, tpg_dev->state); - rc = -EINVAL; } - - if (!rc) { + if (!tpg_dev->hw_no_ops) rc = tpg_hw_stop(&tpg_dev->tpg_hw); - } if (rc) { - CAM_ERR(CAM_TPG, "TPG[%d] STOP_DEV failed", tpg_dev->soc_info.index); + CAM_ERR(CAM_TPG, "TPG[%d] STOP_DEV failed hw_no_ops: %d", + tpg_dev->soc_info.index, tpg_dev->hw_no_ops); } else { tpg_dev->state = CAM_TPG_STATE_ACQUIRE; - CAM_INFO(CAM_TPG, "TPG[%d] STOP_DEV done.", tpg_dev->soc_info.index); + CAM_INFO(CAM_TPG, "TPG[%d] STOP_DEV done hw_no_ops: %d.", + tpg_dev->soc_info.index, tpg_dev->hw_no_ops); } return rc; @@ -543,13 +553,15 @@ static int cam_tpg_cmd_buf_parse( tpg_dev->tpg_hw.tpg_clock = req->global_config.tpg_clock; break; case TPG_CMD_TYPE_STREAM_CONFIG: { - if (cmd_header->cmd_version == 3) { + if ((cmd_header->cmd_version == 3) && + (!tpg_dev->hw_no_ops)) { rc = tpg_hw_add_stream_v3(&tpg_dev->tpg_hw, req, (struct tpg_stream_config_v3_t *)cmd_addr); CAM_DBG(CAM_TPG, "Stream config v3"); - } else if (cmd_header->cmd_version == 1 || - cmd_header->cmd_version == 2) { + } else if ((cmd_header->cmd_version == 1 || + cmd_header->cmd_version == 2) && + (!tpg_dev->hw_no_ops)) { rc = tpg_hw_add_stream(&tpg_dev->tpg_hw, req, (struct tpg_stream_config_t *)cmd_addr); @@ -562,7 +574,9 @@ static int cam_tpg_cmd_buf_parse( case TPG_CMD_TYPE_SETTINGS_CONFIG: { CAM_DBG(CAM_TPG, "TPG[%d] Got TPG Settings Config", tpg_dev->soc_info.index); - rc = tpg_hw_copy_settings_config(&tpg_dev->tpg_hw, + if (!tpg_dev->hw_no_ops) + rc = tpg_hw_copy_settings_config( + &tpg_dev->tpg_hw, (struct tpg_settings_config_t *)cmd_addr); break; } @@ -579,7 +593,8 @@ static int cam_tpg_cmd_buf_parse( break; } } - tpg_hw_add_request(&tpg_dev->tpg_hw, req); + if (!tpg_dev->hw_no_ops) + tpg_hw_add_request(&tpg_dev->tpg_hw, req); end: return rc; free_request: @@ -645,7 +660,9 @@ static int cam_tpg_packet_parse( CAM_ERR(CAM_TPG, "CMD buffer parse failed"); goto end; } - tpg_hw_config(&tpg_dev->tpg_hw, TPG_HW_CMD_INIT_CONFIG, NULL); + if (!tpg_dev->hw_no_ops) + tpg_hw_config(&tpg_dev->tpg_hw, + TPG_HW_CMD_INIT_CONFIG, NULL); break; } case CAM_TPG_PACKET_OPCODE_NOP: diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.c index 780f2a3485..b04b903b7a 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_tpg_dev.h" @@ -208,8 +208,15 @@ static int tpg_soc_info_init(struct cam_tpg_device *tpg_dev, for (i = 0; i < tpg_dev->soc_info.irq_count; i++) irq_data[i] = tpg_dev; - rc = cam_soc_util_request_platform_resource( - &tpg_dev->soc_info, cam_tpg_irq_handler, &(irq_data[0])); + if (!of_property_read_bool(of_node, "hw-no-ops")) + tpg_dev->hw_no_ops = false; + else + tpg_dev->hw_no_ops = true; + + if (!tpg_dev->hw_no_ops) + rc = cam_soc_util_request_platform_resource( + &tpg_dev->soc_info, cam_tpg_irq_handler, + &(irq_data[0])); if (rc) CAM_ERR(CAM_TPG, "unable to request platfrom resources"); else @@ -336,7 +343,14 @@ static void cam_tpg_component_unbind(struct device *dev, struct device *master_dev, void *data) { struct platform_device *pdev = to_platform_device(dev); - struct cam_tpg_device *tpg_dev = platform_get_drvdata(pdev); + struct cam_tpg_device *tpg_dev = NULL; + + tpg_dev = platform_get_drvdata(pdev); + + if (!tpg_dev) { + CAM_ERR(CAM_TPG, "Error No data in tpg_dev"); + return; + } CAM_INFO(CAM_TPG, "Unbind TPG component"); cam_cpas_unregister_client(tpg_dev->cpas_handle); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.h b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.h index 7d63130b60..2b1a8cb939 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.h +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __CAM_TPG_DEV_H__ @@ -112,6 +112,7 @@ struct tpg_crm_intf_params { * @state : state machine states * @slot_id : slot index of this tpg * @phy_id : phy index mapped to this tpg + * @hw_no_ops: To determine whether HW operations need to be disabled * @waiting_request_q : waiting request queue * @active_request_q : active request queue * @tpg_irq_state : tpg irq state @@ -128,6 +129,7 @@ struct cam_tpg_device { int state; int slot_id; int phy_id; + bool hw_no_ops; atomic_t tpg_irq_state; struct list_head waiting_request_q; struct list_head active_request_q; diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.c index 25c55cd2ef..84f4f5f503 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.c @@ -1345,6 +1345,7 @@ struct tpg_hw_request *tpg_hw_create_request( } num_vc_channels = hw->hw_info->max_vc_channels; + /* Allocate request */ req = kzalloc(sizeof(struct tpg_hw_request), GFP_KERNEL); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.c b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.c index 136db75cdd..4ce790992f 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "tpg_hw_v_1_3.h" @@ -874,7 +874,6 @@ int tpg_1_3_layer_init(struct tpg_hw *hw) if (!dbgfileptr_parent) { CAM_ERR(CAM_TPG, "Debug fs could not create directory"); rc = -ENOENT; - return rc; } debugfs_create_file("tpg_xcfa_test", 0644, dbgfileptr_parent, hw, &tpg_1_3_xcfa_test); diff --git a/qcom/opensource/camera-kernel/drivers/cam_smmu/cam_smmu_api.c b/qcom/opensource/camera-kernel/drivers/cam_smmu/cam_smmu_api.c index 50857584b3..53be90aa57 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_smmu/cam_smmu_api.c +++ b/qcom/opensource/camera-kernel/drivers/cam_smmu/cam_smmu_api.c @@ -2690,12 +2690,6 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, goto err_detach; } - if (!table->sgl) { - rc = -EINVAL; - CAM_ERR(CAM_SMMU, "Error: table sgl is null"); - goto err_unmap_sg; - } - domain = iommu_cb_set.cb_info[idx].domain; if (!domain) { CAM_ERR(CAM_SMMU, "CB has no domain set"); @@ -2757,14 +2751,6 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, goto err_detach; } - CAM_DBG(CAM_SMMU, - "DMA buf: %pK, device: %pK, attach: %pK, table: %pK", - (void *)buf, - (void *)iommu_cb_set.cb_info[idx].dev, - (void *)attach, (void *)table); - CAM_DBG(CAM_SMMU, "table sgl: %pK, rc: %d, dma_address: 0x%x", - (void *)table->sgl, rc, - (unsigned int)table->sgl->dma_address); CAM_DBG(CAM_SMMU, "iova=%pK, region_id=%d, paddr=0x%llx, len=%zu, dma_map_attrs=%d", iova, region_id, *paddr_ptr, *len_ptr, attach->dma_map_attrs); @@ -2776,6 +2762,20 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, *len_ptr, microsec); } + if (table->sgl) { + CAM_DBG(CAM_SMMU, + "DMA buf: %pK, device: %pK, attach: %pK, table: %pK", + (void *)buf, + (void *)iommu_cb_set.cb_info[idx].dev, + (void *)attach, (void *)table); + CAM_DBG(CAM_SMMU, "table sgl: %pK, rc: %d, dma_address: 0x%x", + (void *)table->sgl, rc, + (unsigned int)table->sgl->dma_address); + } else { + rc = -EINVAL; + CAM_ERR(CAM_SMMU, "Error: table sgl is null"); + goto err_unmap_sg; + } /* fill up mapping_info */ *mapping_info = kzalloc(sizeof(struct cam_dma_buff_info), GFP_KERNEL); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_dma_fence.c b/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_dma_fence.c index 24cd9b6dbd..71e57e714e 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_dma_fence.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_dma_fence.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_sync_dma_fence.h" @@ -97,16 +97,9 @@ static void __cam_dma_fence_print_table(void) struct cam_dma_fence_row *row; struct dma_fence *fence; - /* Index zero is marked as an invalid slot */ - for (i = 1; i < CAM_DMA_FENCE_MAX_FENCES; i++) { + for (i = 0; i < CAM_DMA_FENCE_MAX_FENCES; i++) { spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]); row = &g_cam_dma_fence_dev->rows[i]; - - /* free slots starting this index */ - if (row->state == CAM_DMA_FENCE_STATE_INVALID) { - spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]); - return; - } fence = row->fence; CAM_INFO(CAM_DMA_FENCE, "Idx: %d seqno: %llu name: %s state: %d", @@ -337,6 +330,7 @@ struct dma_fence *cam_dma_fence_get_fence_from_fd( int32_t fd, int32_t *dma_fence_row_idx) { struct dma_fence *dma_fence = NULL; + struct cam_dma_fence_row *row; dma_fence = __cam_dma_fence_find_fence_in_table(fd, dma_fence_row_idx); if (IS_ERR_OR_NULL(dma_fence)) { @@ -346,7 +340,19 @@ struct dma_fence *cam_dma_fence_get_fence_from_fd( return cam_dma_fence_get_fence_from_sync_file(fd, dma_fence_row_idx); } + spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[*dma_fence_row_idx]); + row = &g_cam_dma_fence_dev->rows[*dma_fence_row_idx]; + + if (row->state == CAM_DMA_FENCE_STATE_INVALID) { + CAM_ERR(CAM_DMA_FENCE, + "dma fence at idx: %d is in invalid state: %d", + dma_fence_row_idx, row->state); + spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[*dma_fence_row_idx]); + return ERR_PTR(-EINVAL); + } + dma_fence_get(dma_fence); + spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[*dma_fence_row_idx]); CAM_DBG(CAM_DMA_FENCE, "dma fence found for fd: %d with seqno: %llu ref_cnt: %u", fd, dma_fence->seqno, kref_read(&dma_fence->refcount)); @@ -786,7 +792,7 @@ void cam_dma_fence_close(void) if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask)) cam_generic_fence_update_monitor_array(i, - &g_cam_dma_fence_dev->dev_lock, + NULL, g_cam_dma_fence_dev->monitor_data, CAM_FENCE_OP_UNREGISTER_CB); dma_fence_remove_callback(row->fence, &row->fence_cb); @@ -797,7 +803,7 @@ void cam_dma_fence_close(void) if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask)) cam_generic_fence_update_monitor_array(i, - &g_cam_dma_fence_dev->dev_lock, + NULL, g_cam_dma_fence_dev->monitor_data, CAM_FENCE_OP_SIGNAL); __cam_dma_fence_signal_fence(row->fence, -EADV); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_synx.c b/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_synx.c index 6def0e9011..53002001f5 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_synx.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_synx.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_sync_synx.h" @@ -810,7 +810,7 @@ void cam_synx_obj_close(void) if (test_bit(CAM_GENERIC_FENCE_TYPE_SYNX_OBJ, &cam_sync_monitor_mask)) cam_generic_fence_update_monitor_array(i, - &g_cam_synx_obj_dev->dev_lock, + NULL, g_cam_synx_obj_dev->monitor_data, CAM_FENCE_OP_UNREGISTER_CB); @@ -822,7 +822,7 @@ void cam_synx_obj_close(void) if (test_bit(CAM_GENERIC_FENCE_TYPE_SYNX_OBJ, &cam_sync_monitor_mask)) cam_generic_fence_update_monitor_array(i, - &g_cam_synx_obj_dev->dev_lock, + NULL, g_cam_synx_obj_dev->monitor_data, CAM_FENCE_OP_SIGNAL); @@ -832,7 +832,7 @@ void cam_synx_obj_close(void) if (test_bit(CAM_GENERIC_FENCE_TYPE_SYNX_OBJ, &cam_sync_monitor_mask)) cam_generic_fence_update_monitor_array(i, - &g_cam_synx_obj_dev->dev_lock, + NULL, g_cam_synx_obj_dev->monitor_data, CAM_FENCE_OP_DESTROY); diff --git a/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_util.c b/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_util.c index 4bc3e6824d..86e78b4a4d 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_util.c +++ b/qcom/opensource/camera-kernel/drivers/cam_sync/cam_sync_util.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2018, 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "cam_sync_util.h" @@ -15,7 +15,8 @@ static int cam_generic_expand_monitor_table(int idx, struct mutex *lock, { struct cam_generic_fence_monitor_data *row_mon_data; - mutex_lock(lock); + if (lock) + mutex_lock(lock); row_mon_data = mon_data[(idx / CAM_GENERIC_MONITOR_TABLE_ENTRY_SZ)]; if (!row_mon_data) { row_mon_data = kzalloc( @@ -27,11 +28,15 @@ static int cam_generic_expand_monitor_table(int idx, struct mutex *lock, CAM_ERR(CAM_SYNC, "Error allocating memory %d, idx %d", sizeof(struct cam_generic_fence_monitor_data) * CAM_GENERIC_MONITOR_TABLE_ENTRY_SZ, idx); - mutex_unlock(lock); + + if (lock) + mutex_unlock(lock); + return -ENOMEM; } - mutex_unlock(lock); + if (lock) + mutex_unlock(lock); return 0; } @@ -115,7 +120,7 @@ void cam_generic_fence_update_monitor_array(int idx, struct cam_generic_fence_monitor_entry *row_mon_entries; /* Validate inputs */ - if (!lock || !mon_data) + if (!mon_data) return; row_mon_data = mon_data[(idx / CAM_GENERIC_MONITOR_TABLE_ENTRY_SZ)]; diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.c b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.c index e5e2d85973..f2fb4b59f5 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.c +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.c @@ -212,7 +212,8 @@ void cam_common_util_thread_switch_delay_detect(char *wq_name, const char *state scheduled_ts = ktime_to_timespec64(scheduled_time); cur_ts = ktime_to_timespec64(cur_time); CAM_WARN_RATE_LIMIT_CUSTOM(CAM_UTIL, 1, 1, - "%s cb: %ps delay in %s detected %ld:%06ld cur %ld:%06ld diff %ld: threshold %d", + "%s cb: %ps delay in %s detected %ld:%06ld cur %ld:%06ld\n" + "diff %ld: threshold %d", wq_name, cb, state, scheduled_ts.tv_sec, scheduled_ts.tv_nsec/NSEC_PER_USEC, cur_ts.tv_sec, cur_ts.tv_nsec/NSEC_PER_USEC, @@ -451,7 +452,9 @@ void cam_common_release_evt_params(int32_t dev_hdl) static inline int cam_common_evt_inject_get_hw_id(uint8_t *hw_id, char *token) { if (strcmp(token, CAM_COMMON_IFE_NODE) == 0) - *hw_id = CAM_COMMON_EVT_INJECT_HW_ISP; + *hw_id = CAM_COMMON_EVT_INJECT_HW_IFE; + else if (strcmp(token, CAM_COMMON_TFE_NODE) == 0) + *hw_id = CAM_COMMON_EVT_INJECT_HW_TFE; else if (strcmp(token, CAM_COMMON_ICP_NODE) == 0) *hw_id = CAM_COMMON_EVT_INJECT_HW_ICP; else if (strcmp(token, CAM_COMMON_JPEG_NODE) == 0) @@ -791,9 +794,12 @@ static int cam_common_evt_inject_get(char *buffer, evt_params = &inject_params->evt_params; switch (inject_params->hw_id) { - case CAM_COMMON_EVT_INJECT_HW_ISP: + case CAM_COMMON_EVT_INJECT_HW_IFE: strscpy(hw_name, CAM_COMMON_IFE_NODE, sizeof(hw_name)); break; + case CAM_COMMON_EVT_INJECT_HW_TFE: + strscpy(hw_name, CAM_COMMON_TFE_NODE, sizeof(hw_name)); + break; case CAM_COMMON_EVT_INJECT_HW_ICP: strscpy(hw_name, CAM_COMMON_ICP_NODE, sizeof(hw_name)); break; diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.h b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.h index de2adac6a4..9089343d60 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.h +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_common_util.h @@ -30,6 +30,7 @@ #define CAM_COMMON_IFE_NODE "IFE" #define CAM_COMMON_ICP_NODE "IPE" #define CAM_COMMON_JPEG_NODE "JPEG" +#define CAM_COMMON_TFE_NODE "TFE" #define CAM_COMMON_NS_PER_MS 1000000ULL @@ -160,7 +161,8 @@ enum cam_common_evt_inject_str_id_type { }; enum cam_common_evt_inject_hw_id { - CAM_COMMON_EVT_INJECT_HW_ISP, + CAM_COMMON_EVT_INJECT_HW_IFE, + CAM_COMMON_EVT_INJECT_HW_TFE, CAM_COMMON_EVT_INJECT_HW_ICP, CAM_COMMON_EVT_INJECT_HW_JPEG, CAM_COMMON_EVT_INJECT_HW_MAX diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.c b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.c index b0a97029c6..e00ab05241 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.c +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -318,7 +318,7 @@ void cam_free_clear(const void * ptr) } #endif -#ifdef CONFIG_DOMAIN_ID_SECURE_CAMERA +#ifdef CONFIG_CSF_2_5_SECURE_CAMERA int cam_csiphy_notify_secure_mode(struct csiphy_device *csiphy_dev, bool protect, int32_t offset, bool is_shutdown) { @@ -441,6 +441,20 @@ int cam_csiphy_notify_secure_mode(struct csiphy_device *csiphy_dev, } #endif +int cam_update_camnoc_qos_settings(uint32_t use_case_id, + uint32_t qos_cnt, struct qcom_scm_camera_qos *scm_buf) +{ + int rc = 0; + + rc = qcom_scm_camera_update_camnoc_qos(use_case_id, qos_cnt, scm_buf); + if (rc) { + CAM_ERR(CAM_ISP, "scm call to update QoS failed: %d", rc); + rc = -EINVAL; + } + + return rc; +} + /* Callback to compare device from match list before adding as component */ static inline int camera_component_compare_dev(struct device *dev, void *data) { @@ -676,8 +690,8 @@ int cam_i3c_driver_remove(struct i3c_device *client) } #endif -#if (KERNEL_VERSION(5, 15, 0) <= LINUX_VERSION_CODE && \ - KERNEL_VERSION(5, 18, 0) > LINUX_VERSION_CODE) +#if (KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE && \ + KERNEL_VERSION(6, 6, 0) > LINUX_VERSION_CODE) long cam_dma_buf_set_name(struct dma_buf *dmabuf, const char *name) { long ret = 0; diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.h b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.h index 4486cce08d..d1832908b0 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.h +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_compat.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_COMPAT_H_ @@ -44,8 +44,7 @@ MODULE_IMPORT_NS(DMA_BUF); #endif -#ifdef CONFIG_DOMAIN_ID_SECURE_CAMERA -#include +#ifdef CONFIG_CSF_2_5_SECURE_CAMERA #include #include #include @@ -62,6 +61,8 @@ struct cam_fw_alloc_info { int cam_reserve_icp_fw(struct cam_fw_alloc_info *icp_fw, size_t fw_length); void cam_unreserve_icp_fw(struct cam_fw_alloc_info *icp_fw, size_t fw_length); void cam_cpastop_scm_write(struct cam_cpas_hw_errata_wa *errata_wa); +int cam_update_camnoc_qos_settings(uint32_t use_case_id, + uint32_t num_arg, struct qcom_scm_camera_qos *scm_buf); int cam_ife_notify_safe_lut_scm(bool safe_trigger); int camera_component_match_add_drivers(struct device *master_dev, struct component_match **match_list); diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_debug_util.c b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_debug_util.c index ed01d0efd5..86f4c1ca08 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_debug_util.c +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_debug_util.c @@ -299,6 +299,5 @@ void cam_print_log(int type, int module, int tag, const char *func, __cam_print_log(type, __CAM_LOG_FMT, CAM_LOG_TAG_NAME(tag), CAM_DBG_MOD_NAME(module), func, line, buf); - vprintk("\n\0", args); va_end(args); } diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_bus.h b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_bus.h index a631592860..c6475b573f 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_bus.h +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_bus.h @@ -13,7 +13,7 @@ #include "cam_debug_util.h" #include "cam_cpas.h" -#define CAM_SOC_BUS_MAX_NUM_USECASES 8 +#define CAM_SOC_BUS_MAX_NUM_USECASES 9 enum cam_soc_bus_path_data { CAM_SOC_BUS_PATH_DATA_HLOS, diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.c b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.c index 0b89b7bf5c..49711c8bf6 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.c +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -9,6 +9,7 @@ #include #include #include +#include #include "cam_soc_util.h" #include "cam_debug_util.h" #include "cam_cx_ipeak.h" @@ -97,6 +98,12 @@ static LIST_HEAD(wrapper_clk_list); const struct device *cam_cesta_crm_dev; +#if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API) +static int cam_soc_util_set_hw_client_rate_through_mmrm( + void *mmrm_handle, long low_val, long high_val, + uint32_t num_hw_blocks, int cesta_client_idx); +#endif + #if IS_ENABLED(CONFIG_QCOM_CRM) static inline const struct device *cam_wrapper_crm_get_device( const char *name) @@ -403,6 +410,23 @@ static int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info, src_clk_idx = soc_info->src_clk_idx; clk = soc_info->clk[src_clk_idx]; + if (!skip_mmrm_set_rate && soc_info->mmrm_handle) { + CAM_DBG(CAM_UTIL, "cesta mmrm hw client: set %s, high-rate %lld low-rate %lld", + soc_info->clk_name[src_clk_idx], high_val, low_val); + + rc = cam_soc_util_set_hw_client_rate_through_mmrm( + soc_info->mmrm_handle, low_val, high_val, 1, + cesta_client_idx); + if (rc) { + CAM_ERR(CAM_UTIL, + "set_sw_client_rate through mmrm failed on %s clk_id %d low_val %llu high_val %llu client idx=%d", + soc_info->clk_name[src_clk_idx], soc_info->clk_id[src_clk_idx], + low_val, high_val, cesta_client_idx); + return rc; + } + goto end; + } + CAM_DBG(CAM_UTIL, "%s Requested clk rate [high low]: [%llu %llu] cesta_client_idx: %d", soc_info->clk_name[src_clk_idx], high_val, low_val, cesta_client_idx); @@ -424,6 +448,7 @@ static int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info, return rc; } +end: if (applied_high_val) *applied_high_val = high_val; @@ -433,6 +458,52 @@ static int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info, return rc; } +#if IS_REACHABLE(CONFIG_MSM_MMRM) +int cam_soc_util_set_hw_client_rate_through_mmrm( + void *mmrm_handle, long low_val, long high_val, + uint32_t num_hw_blocks, int cesta_client_idx) +{ + int rc = 0; + struct mmrm_client_data client_data; + + client_data.num_hw_blocks = num_hw_blocks; + client_data.crm_drv_idx = cesta_client_idx; + client_data.drv_type = MMRM_CRM_HW_DRV; + client_data.pwr_st = CRM_PWR_STATE1; + client_data.flags = 0; + + CAM_DBG(CAM_UTIL, + "hw client mmrm=%pK, high_val %ld, low_val %ld, num_blocks=%d, pwr_state: %u, client_idx: %d", + mmrm_handle, high_val, low_val, num_hw_blocks, CRM_PWR_STATE1, cesta_client_idx); + + rc = mmrm_client_set_value((struct mmrm_client *)mmrm_handle, + &client_data, high_val); + if (rc) { + CAM_ERR(CAM_UTIL, "Set high rate failed rate %ld rc %d", + high_val, rc); + return rc; + } + + /* We vote a second time for pwr_st = low */ + client_data.pwr_st = CRM_PWR_STATE0; + + rc = mmrm_client_set_value((struct mmrm_client *)mmrm_handle, + &client_data, low_val); + if (rc) + CAM_ERR(CAM_UTIL, "Set low rate failed rate %ld rc %d", low_val, rc); + + return rc; +} + +#else +int cam_soc_util_set_hw_client_rate_through_mmrm( + void *mmrm_handle, long low_val, long high_val, + uint32_t num_hw_blocks, int cesta_client_idx) +{ + return 0; +} +#endif + #else static inline int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info, uint32_t cesta_client_idx, unsigned long high_val, unsigned long low_val, @@ -508,6 +579,16 @@ int cam_soc_util_register_mmrm_client( desc.client_info.desc.client_id = clk_id; desc.client_info.desc.clk = clk; +#if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API) + if (soc_info->is_clk_drv_en) { + desc.client_info.desc.hw_drv_instances = CAM_CESTA_MAX_CLIENTS; + desc.client_info.desc.num_pwr_states = CAM_NUM_PWR_STATES; + } else { + desc.client_info.desc.hw_drv_instances = 0; + desc.client_info.desc.num_pwr_states = 0; + } +#endif + snprintf((char *)desc.client_info.desc.name, sizeof(desc.client_info.desc.name), "%s_%s", soc_info->dev_name, clk_name); @@ -551,7 +632,7 @@ int cam_soc_util_unregister_mmrm_client( return rc; } -static int cam_soc_util_set_rate_through_mmrm( +static int cam_soc_util_set_sw_client_rate_through_mmrm( void *mmrm_handle, bool is_nrt_dev, long min_rate, long req_rate, uint32_t num_hw_blocks) { @@ -562,8 +643,12 @@ static int cam_soc_util_set_rate_through_mmrm( client_data.num_hw_blocks = num_hw_blocks; client_data.flags = 0; +#if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API) + client_data.drv_type = MMRM_CRM_SW_DRV; +#endif + CAM_DBG(CAM_UTIL, - "mmrm=%pK, nrt=%d, min_rate=%ld req_rate %ld, num_blocks=%d", + "sw client mmrm=%pK, nrt=%d, min_rate=%ld req_rate %ld, num_blocks=%d", mmrm_handle, is_nrt_dev, min_rate, req_rate, num_hw_blocks); if (is_nrt_dev) { @@ -606,7 +691,7 @@ int cam_soc_util_unregister_mmrm_client( return 0; } -static int cam_soc_util_set_rate_through_mmrm( +static int cam_soc_util_set_sw_client_rate_through_mmrm( void *mmrm_handle, bool is_nrt_dev, long min_rate, long req_rate, uint32_t num_hw_blocks) { @@ -851,14 +936,14 @@ static int cam_soc_util_clk_wrapper_set_clk_rate( bool set_rate_finish = false; if (!skip_mmrm_set_rate && wrapper_clk->mmrm_handle) { - rc = cam_soc_util_set_rate_through_mmrm( + rc = cam_soc_util_set_sw_client_rate_through_mmrm( wrapper_clk->mmrm_handle, wrapper_clk->is_nrt_dev, wrapper_clk->min_clk_rate, final_clk_rate, active_clients); if (rc) { CAM_ERR(CAM_UTIL, - "set_rate through mmrm failed clk_id %d, rate=%ld", + "set_sw_client_rate through mmrm failed clk_id %d, rate=%ld", wrapper_clk->clk_id, final_clk_rate); goto end; } @@ -1202,6 +1287,31 @@ static int cam_soc_util_get_clk_level_to_apply( return 0; } +unsigned long cam_soc_util_get_clk_rate_applied( + struct cam_hw_soc_info *soc_info, int32_t index, bool is_src, + enum cam_vote_level clk_level) +{ + unsigned long clk_rate = 0; + struct clk *clk = NULL; + int rc = 0; + enum cam_vote_level apply_level; + + if (is_src) { + clk = soc_info->clk[index]; + clk_rate = cam_wrapper_clk_get_rate(clk); + } else { + rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level, + &apply_level); + if (rc) + return rc; + if (soc_info->clk_rate[apply_level][index] > 0) { + clk = soc_info->clk[index]; + clk_rate = cam_wrapper_clk_get_rate(clk); + } + } + return clk_rate; +} + int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info) { int i, rc = 0; @@ -1342,16 +1452,10 @@ static int cam_soc_util_set_clk_rate(struct cam_hw_soc_info *soc_info, if (is_src_clk && soc_info->mmrm_handle && !skip_mmrm_set_rate) { - int32_t idx = soc_info->src_clk_idx; + uint32_t idx = soc_info->src_clk_idx; uint32_t min_level = soc_info->lowest_clk_level; - if (idx < 0) { - CAM_ERR(CAM_UTIL, "Negative value of source clk index"); - return -EINVAL; - } - - - rc = cam_soc_util_set_rate_through_mmrm( + rc = cam_soc_util_set_sw_client_rate_through_mmrm( soc_info->mmrm_handle, soc_info->is_nrt_dev, soc_info->clk_rate[min_level][idx], @@ -1359,7 +1463,7 @@ static int cam_soc_util_set_clk_rate(struct cam_hw_soc_info *soc_info, if (rc) { CAM_ERR(CAM_UTIL, - "set_rate through mmrm failed on %s clk_id %d, rate=%ld", + "set_sw_client_rate through mmrm failed on %s clk_id %d, rate=%ld", clk_name, clk_id, clk_rate_round); return rc; } @@ -1376,7 +1480,7 @@ static int cam_soc_util_set_clk_rate(struct cam_hw_soc_info *soc_info, } } - if (applied_clk_rate) + if (applied_clk_rate && set_rate) *applied_clk_rate = clk_rate_round; return rc; @@ -1776,7 +1880,7 @@ int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info, int cesta_client_ (soc_info->src_clk_idx == clk_idx)) { CAM_DBG(CAM_UTIL, "Dev %s Disabling %s clk, set 0 rate", soc_info->dev_name, clk_name); - cam_soc_util_set_rate_through_mmrm( + cam_soc_util_set_sw_client_rate_through_mmrm( soc_info->mmrm_handle, soc_info->is_nrt_dev, 0, 0, 1); @@ -2233,6 +2337,21 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info, return rc; }; +int cam_soc_util_dump_clk(struct cam_hw_soc_info *soc_info) +{ + int i, rc = 0; + + if (!soc_info) + return -EINVAL; + + for (i = 0; i < soc_info->num_clk; i++) { + CAM_INFO(CAM_UTIL, "Dumping clock = %s", soc_info->clk_name[i]); + qcom_clk_dump(soc_info->clk[i], NULL, false); + } + + return rc; +} + static int cam_soc_util_get_dt_gpio_req_tbl(struct device_node *of_node, struct cam_soc_gpio_data *gconf, uint16_t *gpio_array, uint16_t gpio_array_size) @@ -2950,8 +3069,7 @@ static void cam_soc_util_regulator_disable_default( soc_info->rgltr_delay[j]); } else { if (soc_info->rgltr[j]) - if (regulator_is_enabled(soc_info->rgltr[j])) - cam_wrapper_regulator_disable(soc_info->rgltr[j]); + cam_wrapper_regulator_disable(soc_info->rgltr[j]); } } } diff --git a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.h b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.h index e01238ff94..9729fe7efb 100644 --- a/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.h +++ b/qcom/opensource/camera-kernel/drivers/cam_utils/cam_soc_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_SOC_UTIL_H_ @@ -614,6 +614,18 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info, int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info, int cesta_client_idx, bool optional_clk, int32_t clk_idx); +/** + * cam_soc_util_dump_clk() + * + * @brief: Dumps all the clocks of the caller hw, using + * clock api. + * + * @soc_info: Device soc information + * @return: Success or failure + */ + +int cam_soc_util_dump_clk(struct cam_hw_soc_info *soc_info); + /** * cam_soc_util_irq_enable() * @@ -794,6 +806,10 @@ int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info, int cesta_ int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info, int64_t clk_rate, int clk_idx, int32_t *clk_lvl); +unsigned long cam_soc_util_get_clk_rate_applied( + struct cam_hw_soc_info *soc_info, int32_t index, bool is_src, + enum cam_vote_level clk_level); + /* Callback to get reg space data for specific HW */ typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type, void *ctx, struct cam_hw_soc_info **soc_info_ptr, diff --git a/qcom/opensource/camera-kernel/drivers/kunit_test/camera_kunit_main.c b/qcom/opensource/camera-kernel/drivers/kunit_test/camera_kunit_main.c old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/drivers/kunit_test/camera_kunit_main.h b/qcom/opensource/camera-kernel/drivers/kunit_test/camera_kunit_main.h old mode 100644 new mode 100755 diff --git a/qcom/opensource/camera-kernel/dt-bindings/msm-camera.h b/qcom/opensource/camera-kernel/dt-bindings/msm-camera.h index 4857b0de94..a798b2bf60 100644 --- a/qcom/opensource/camera-kernel/dt-bindings/msm-camera.h +++ b/qcom/opensource/camera-kernel/dt-bindings/msm-camera.h @@ -118,7 +118,8 @@ #define CAM_CPAS_SFE_FUSE 9 #define CAM_CPAS_CUSTOM_FUSE 10 #define CAM_CPAS_CAM_FUSE 11 -#define CAM_CPAS_FUSE_FEATURE_MAX 12 +#define CAM_CPAS_SHDR_FUSE 12 +#define CAM_CPAS_FUSE_FEATURE_MAX 13 #define CCI_MASTER_0 0 #define CCI_MASTER_1 1 diff --git a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_cpas.h b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_cpas.h index f662aba783..345ef03833 100644 --- a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_cpas.h +++ b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_cpas.h @@ -277,4 +277,18 @@ struct cam_axi_per_path_bw_vote { __u64 ddr_ib_bw; }; +#define CAM_CPAS_CUSTOM_CMD_FD_PORT_CFG 0 + +/** + * struct cam_cpas_fd_port_config : CPAS custom cmd struct for updating FD + * port config + * + * @is_secure Security mode of the FD port + * @reserved Reserved for alignment + */ +struct cam_cpas_fd_port_config { + __u32 is_secure; + __u32 reserved; +}; + #endif /* __UAPI_CAM_CPAS_H__ */ diff --git a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_defs.h b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_defs.h index 3af78c4400..87bb4a14e9 100644 --- a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_defs.h +++ b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_defs.h @@ -31,6 +31,7 @@ #define CAM_DUMP_REQ (CAM_COMMON_OPCODE_BASE_v2 + 0x3) #define CAM_QUERY_CAP_V3 (CAM_COMMON_OPCODE_BASE_v2 + 0x4) #define CAM_SYNX_TEST_TRIGGER (CAM_COMMON_OPCODE_BASE_v2 + 0x5) +#define CAM_CUSTOM_DEV_CONFIG (CAM_COMMON_OPCODE_BASE_v2 + 0x6) #define CAM_EXT_OPCODE_BASE 0x200 #define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) @@ -96,6 +97,20 @@ struct cam_control { __u64 handle; }; +/** + * struct cam_custom_cmd - Structure used by ioctl control for camera + * devices to send custom commands. + * + * @cmd_type: Command type + * @size: Size of the data + * @handle: Pointer to the command data + */ +struct cam_custom_cmd { + __u32 cmd_type; + __u32 size; + __u64 handle; +}; + /* camera IOCTL */ #define VIDIOC_CAM_CONTROL \ _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control) diff --git a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_isp_tfe.h b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_isp_tfe.h index 755bd13525..4a307d6581 100644 --- a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_isp_tfe.h +++ b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_isp_tfe.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __UAPI_CAM_ISP_TFE_H__ @@ -24,7 +25,10 @@ #define CAM_ISP_TFE_OUT_RES_DS4 (CAM_ISP_TFE_OUT_RES_BASE + 12) #define CAM_ISP_TFE_OUT_RES_DS16 (CAM_ISP_TFE_OUT_RES_BASE + 13) #define CAM_ISP_TFE_OUT_RES_AI (CAM_ISP_TFE_OUT_RES_BASE + 14) -#define CAM_ISP_TFE_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_BASE + 15) +#define CAM_ISP_TFE_OUT_RES_PD_LCR_STATS (CAM_ISP_TFE_OUT_RES_BASE + 15) +#define CAM_ISP_TFE_OUT_RES_PD_PREPROCESSED (CAM_ISP_TFE_OUT_RES_BASE + 16) +#define CAM_ISP_TFE_OUT_RES_PD_PARSED (CAM_ISP_TFE_OUT_RES_BASE + 17) +#define CAM_ISP_TFE_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_BASE + 18) /* TFE input port resource type */ diff --git a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_tfe.h b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_tfe.h index 7b9b008b22..4544cda9da 100644 --- a/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_tfe.h +++ b/qcom/opensource/camera-kernel/include/uapi/camera/media/cam_tfe.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __UAPI_CAM_TFE_H__ @@ -66,13 +66,20 @@ #define CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST 6 #define CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH 7 #define CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR 8 +#define CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_LEFT 9 +#define CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_RIGHT 10 /* ISP TFE Generic Cmd Buffer Blob types */ -#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_HFR_CONFIG 0 -#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 -#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_CONFIG_V2 2 -#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 3 -#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_LIMITER_CFG 16 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_HFR_CONFIG 0 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_CONFIG_V2 2 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 3 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_INIT_CONFIG 4 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_DYNAMIC_MODE_SWITCH 15 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_LIMITER_CFG 16 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_ALIGNMENT_OFFSET_INFO 17 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_UPDATE_OUT_RES 18 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_DISCARD_INITIAL_FRAMES 19 /* DSP mode */ #define CAM_ISP_TFE_DSP_MODE_NONE 0 @@ -95,6 +102,9 @@ /* Feature Flag indicators */ #define CAM_ISP_TFE_FLAG_QCFA_BIN BIT(0) #define CAM_ISP_TFE_FLAG_BAYER_BIN BIT(1) +#define CAM_ISP_TFE_FLAG_SHDR_MASTER_EN BIT(2) +#define CAM_ISP_TFE_FLAG_SHDR_SLAVE_EN BIT(3) +#define CAM_ISP_TFE_FLAG_EPD_SUPPORT BIT(4) /* Query devices */ /** @@ -130,6 +140,25 @@ struct cam_isp_tfe_query_cap_cmd { struct cam_isp_tfe_dev_cap_info dev_caps[CAM_ISP_TFE_HW_MAX]; }; +/** + * struct cam_isp_tfe_query_cap_cmd_v2 - ISP TFE query device + * capability payload + * + * @version returned query cap cmd api version + * @num_dev: returned number of device capabilities + * @device_iommu: returned iommu handles for device + * @cdm_iommu: returned iommu handles for cdm + * @dev_caps: returned device capability array + * + */ +struct cam_isp_tfe_query_cap_cmd_v2 { + __u32 version; + __s32 num_dev; + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + struct cam_isp_tfe_dev_cap_info dev_caps[1]; +}; + /* Acquire Device */ /** * struct cam_isp_tfe_out_port_info - An output port resource info @@ -505,6 +534,84 @@ struct cam_isp_tfe_out_rsrc_bw_limiter_config { struct cam_isp_tfe_wm_bw_limiter_config bw_limiter_config[1]; }; +/** + * struct cam_isp_tfe_alignment_offset_config - ISP TFE buffer alignment config + * + * @resource_type: Resourse type + * @x_offset: Offset of the buffer from x-axies + * @y_offset: Offset of the buffer from y-axies + * @width: Width of out resource + * @height: Height of out resource + * @stride: Stride of out resource + * + */ +struct cam_isp_tfe_alignment_offset_config { + __u32 resource_type; + __u32 x_offset; + __u32 y_offset; + __u32 width; + __u32 height; + __u32 stride; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_alignment_resource_info - ISP TFE Resource Alignment + * + * @version: Alignment api version + * @num_ports: Number of ports + * @port_alignment_cfg: Buffer alignment for each IO port + */ +struct cam_isp_tfe_alignment_resource_info { + __u32 version; + __u32 num_ports; + struct cam_isp_tfe_alignment_offset_config port_alignment_cfg[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_wm_dimension_config - ISP TFE res Dimension config + * + * @res_id : Resource id + * @mode : Mode of out resource + * @height : Out resource height + * @width : Out resource width + * + */ +struct cam_isp_tfe_wm_dimension_config { + __u32 res_id; + __u32 mode; + __u32 height; + __u32 width; +}; + +/** + * struct cam_isp_tfe_out_resource_config - ISP TFE out config + * + * @num_ports : Num of out res + * @reserved : Reserved field + * @dimention_config : Out resource dimension config + */ +struct cam_isp_tfe_out_resource_config { + __u32 num_ports; + __u32 reserved; + struct cam_isp_tfe_wm_dimension_config dimension_config[1]; +}; + +/** + * struct cam_isp_tfe_discard_initial_frames - Discard init frames + * + * Some sensors require discarding the initial frames + * after the sensor is streamed on. The discard would be + * applied on all paths [IPP/PPP/RDIx] for the given + * pipeline. + * + * @version : Version field + * @num_frames : Number of frames to be discarded + */ +struct cam_isp_tfe_discard_initial_frames { + __u32 version; + __u32 num_frames; +} __attribute__((packed)); + #define CAM_TFE_ACQUIRE_COMMON_VER0 0x1000 #define CAM_TFE_ACQUIRE_COMMON_SIZE_VER0 0x0 diff --git a/qcom/opensource/camera-kernel/pineapple_consolidate_defconfig b/qcom/opensource/camera-kernel/pineapple_consolidate_defconfig deleted file mode 100644 index b4e8049267..0000000000 --- a/qcom/opensource/camera-kernel/pineapple_consolidate_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_SPECTRA_ISP=y -CONFIG_SPECTRA_ICP=y -CONFIG_SPECTRA_JPEG=y -CONFIG_SPECTRA_SENSOR=y -CONFIG_SPECTRA_USE_CLK_CRM_API=y -CONFIG_SPECTRA_USE_RPMH_DRV_API=y -CONFIG_SPECTRA_LLCC_STALING=y -CONFIG_TARGET_SYNX_ENABLE=y -CONFIG_MSM_MMRM=y -CONFIG_INTERCONNECT_QCOM=y -CONFIG_DOMAIN_ID_SECURE_CAMERA=y diff --git a/qcom/opensource/camera-kernel/pineapple_defconfig b/qcom/opensource/camera-kernel/pineapple_defconfig index b4e8049267..eeb372bd13 100644 --- a/qcom/opensource/camera-kernel/pineapple_defconfig +++ b/qcom/opensource/camera-kernel/pineapple_defconfig @@ -1,6 +1,7 @@ CONFIG_SPECTRA_ISP=y CONFIG_SPECTRA_ICP=y CONFIG_SPECTRA_JPEG=y +CONFIG_SPECTRA_CRE=y CONFIG_SPECTRA_SENSOR=y CONFIG_SPECTRA_USE_CLK_CRM_API=y CONFIG_SPECTRA_USE_RPMH_DRV_API=y @@ -9,3 +10,5 @@ CONFIG_TARGET_SYNX_ENABLE=y CONFIG_MSM_MMRM=y CONFIG_INTERCONNECT_QCOM=y CONFIG_DOMAIN_ID_SECURE_CAMERA=y +CONFIG_DYNAMIC_FD_PORT_CONFIG=y +CONFIG_CSF_2_5_SECURE_CAMERA=y diff --git a/qcom/opensource/camera-kernel/pineapple_gki_defconfig b/qcom/opensource/camera-kernel/pineapple_gki_defconfig deleted file mode 100644 index b4e8049267..0000000000 --- a/qcom/opensource/camera-kernel/pineapple_gki_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_SPECTRA_ISP=y -CONFIG_SPECTRA_ICP=y -CONFIG_SPECTRA_JPEG=y -CONFIG_SPECTRA_SENSOR=y -CONFIG_SPECTRA_USE_CLK_CRM_API=y -CONFIG_SPECTRA_USE_RPMH_DRV_API=y -CONFIG_SPECTRA_LLCC_STALING=y -CONFIG_TARGET_SYNX_ENABLE=y -CONFIG_MSM_MMRM=y -CONFIG_INTERCONNECT_QCOM=y -CONFIG_DOMAIN_ID_SECURE_CAMERA=y