android/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge 065610f845 on remote branch

Browse Source 
Change-Id: I04de031893e50db404bd7cd8478d827a12665ab7
This commit is contained in:
Linux Build Service Account 2024-09-11 04:21:04 -07:00
commit 971d4062cc
4 changed files with 18 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
adreno-gpulist.h
View File

@ -2758,7 +2758,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_3_0 = {
.compatible = "qcom,adreno-gpu-gen8-3-0",
.features = ADRENO_APRIV | ADRENO_IOCOHERENT |
ADRENO_CONTENT_PROTECTION | ADRENO_IFPC | ADRENO_BCL |
ADRENO_PREEMPTION,
ADRENO_PREEMPTION | ADRENO_ACD,
.gpudev = &adreno_gen8_hwsched_gpudev.base,
.perfcounters = &adreno_gen8_perfcounters,
.uche_gmem_alignment = SZ_64M,

38
adreno_gen8_gmu.c
View File

@ -13,7 +13,6 @@
#include <linux/interconnect.h>
#include <linux/io.h>
#include <linux/kobject.h>
#include <linux/mailbox/qmp.h>
#include <linux/of_platform.h>
#include <linux/qcom-iommu-util.h>
#include <linux/regulator/consumer.h>
@ -1770,26 +1769,20 @@ static irqreturn_t gen8_gmu_irq_handler(int irq, void *data)
void gen8_gmu_aop_send_acd_state(struct gen8_gmu_device *gmu, bool flag)
{
struct qmp_pkt msg;
char msg_buf[36];
u32 size;
int ret;
if (IS_ERR_OR_NULL(gmu->mailbox.channel))
if (IS_ERR_OR_NULL(gmu->qmp))
return;
size = scnprintf(msg_buf, sizeof(msg_buf),
"{class: gpu, res: acd, val: %d}", flag);
/* mailbox controller expects 4-byte aligned buffer */
msg.size = ALIGN((size + 1), SZ_4);
msg.data = msg_buf;
ret = mbox_send_message(gmu->mailbox.channel, &msg);
ret = qmp_send(gmu->qmp, msg_buf, ALIGN((size + 1), SZ_4));
if (ret < 0)
dev_err(&gmu->pdev->dev,
"AOP mbox send message failed: %d\n", ret);
"AOP qmp send message failed: %d\n", ret);
}
int gen8_gmu_enable_clks(struct adreno_device *adreno_dev, u32 level)
@ -2021,7 +2014,7 @@ static int gen8_gmu_acd_set(struct kgsl_device *device, bool val)
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct gen8_gmu_device *gmu = to_gen8_gmu(adreno_dev);
if (IS_ERR_OR_NULL(gmu->mailbox.channel))
if (IS_ERR_OR_NULL(gmu->qmp))
return -EINVAL;
/* Don't do any unneeded work if ACD is already in the correct state */
@ -2224,19 +2217,12 @@ static void gen8_free_gmu_globals(struct gen8_gmu_device *gmu)
gmu->global_entries = 0;
}
static int gen8_gmu_aop_mailbox_init(struct adreno_device *adreno_dev,
static int gen8_gmu_qmp_aoss_init(struct adreno_device *adreno_dev,
struct gen8_gmu_device *gmu)
{
struct kgsl_mailbox *mailbox = &gmu->mailbox;
mailbox->client.dev = &gmu->pdev->dev;
mailbox->client.tx_block = true;
mailbox->client.tx_tout = 1000;
mailbox->client.knows_txdone = false;
mailbox->channel = mbox_request_channel(&mailbox->client, 0);
if (IS_ERR(mailbox->channel))
return PTR_ERR(mailbox->channel);
gmu->qmp = qmp_get(&gmu->pdev->dev);
if (IS_ERR(gmu->qmp))
return PTR_ERR(gmu->qmp);
adreno_dev->acd_enabled = true;
return 0;
@ -2279,10 +2265,10 @@ static void gen8_gmu_acd_probe(struct kgsl_device *device,
cmd->num_levels = cmd_idx;
ret = gen8_gmu_aop_mailbox_init(adreno_dev, gmu);
ret = gen8_gmu_qmp_aoss_init(adreno_dev, gmu);
if (ret)
dev_err(&gmu->pdev->dev,
"AOP mailbox init failed: %d\n", ret);
"AOP qmp init failed: %d\n", ret);
}
static int gen8_gmu_reg_probe(struct adreno_device *adreno_dev)
@ -2386,8 +2372,8 @@ void gen8_gmu_remove(struct kgsl_device *device)
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct gen8_gmu_device *gmu = to_gen8_gmu(adreno_dev);
if (!IS_ERR_OR_NULL(gmu->mailbox.channel))
mbox_free_channel(gmu->mailbox.channel);
if (!IS_ERR_OR_NULL(gmu->qmp))
qmp_put(gmu->qmp);
adreno_dev->acd_enabled = false;

8
adreno_gen8_gmu.h
View File

@ -7,7 +7,7 @@
#ifndef __ADRENO_GEN8_GMU_H
#define __ADRENO_GEN8_GMU_H
#include <linux/mailbox_client.h>
#include <linux/soc/qcom/qcom_aoss.h>
#include "adreno_gen8_hfi.h"
#include "kgsl_gmu_core.h"
@ -37,7 +37,6 @@ struct gen8_dcvs_table {
* than default power level
* @idle_level: Minimal GPU idle power level
* @fault_count: GMU fault count
* @mailbox: Messages to AOP for ACD enable/disable go through this
* @log_wptr_retention: Store the log wptr offset on slumber
*/
struct gen8_gmu_device {
@ -71,7 +70,8 @@ struct gen8_gmu_device {
u32 freqs[GMU_MAX_PWRLEVELS];
/** @vlvls: Array of GMU voltage levels */
u32 vlvls[GMU_MAX_PWRLEVELS];
struct kgsl_mailbox mailbox;
/** @qmp: aoss_qmp handle */
struct qmp *qmp;
/** @gmu_globals: Array to store gmu global buffers */
struct kgsl_memdesc gmu_globals[GMU_KERNEL_ENTRIES];
/** @global_entries: To keep track of number of gmu buffers */
@ -299,7 +299,7 @@ int gen8_gmu_memory_init(struct adreno_device *adreno_dev);
* @gmu: Pointer to the gen8 gmu device
* @flag: Boolean to enable or disable acd in aop
*
* This function enables or disables gpu acd feature using mailbox
* This function enables or disables gpu acd feature using qmp
*/
void gen8_gmu_aop_send_acd_state(struct gen8_gmu_device *gmu, bool flag);

2
kgsl_pwrctrl.c
View File

@ -314,7 +314,7 @@ void kgsl_pwrctrl_set_constraint(struct kgsl_device *device,
kgsl_pwrctrl_pwrlevel_change(device, constraint);
/* Trace the constraint being set by the driver */
trace_kgsl_constraint(device, pwrc_old->type, constraint, 1);
} else if (pwrc_old->type == pwrc->type) {
} else if ((pwrc_old->type == pwrc->type) && (pwrc_old->sub_type == pwrc->sub_type)) {
pwrc_old->owner_id = id;
pwrc_old->owner_timestamp = ts;
pwrc_old->expires = jiffies +