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Merge "kgsl: Fix AB voting in gen8_3_0"

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qctecmdr 2024-06-07 09:20:41 -07:00 committed by Gerrit - the friendly Code Review server
commit 936ce39f2a
6 changed files with 20 additions and 10 deletions
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4
adreno-gpulist.h
View File

@ -2392,6 +2392,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_9_0 = {
.gmem_size = 3 * SZ_1M,
.bus_width = 32,
.snapshot_size = SZ_8M,
.num_ddr_channels = 4,
},
.aqefw_name = "gen70900_aqe.fw",
.sqefw_name = "gen70900_sqe.fw",
@ -2430,6 +2431,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_9_1 = {
.gmem_size = 3 * SZ_1M,
.bus_width = 32,
.snapshot_size = SZ_8M,
.num_ddr_channels = 4,
},
.aqefw_name = "gen70900_aqe.fw",
.sqefw_name = "gen70900_sqe.fw",
@ -2468,6 +2470,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_11_0 = {
.gmem_size = SZ_1M + SZ_512K,
.bus_width = 32,
.snapshot_size = SZ_4M,
.num_ddr_channels = 4,
},
.sqefw_name = "gen71100_sqe.fw",
.gmufw_name = "gen71100_gmu.bin",
@ -2761,6 +2764,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_3_0 = {
.gmem_size = (SZ_512K + SZ_64K),
.bus_width = 32,
.snapshot_size = SZ_8M,
.num_ddr_channels = 2,
},
.sqefw_name = "gen80300_sqe.fw",
.gmufw_name = "gen80300_gmu.bin",

2
adreno.h
View File

@ -485,6 +485,8 @@ struct adreno_gpu_core {
u32 bus_width;
/** @snapshot_size: Size of the static snapshot region in bytes */
u32 snapshot_size;
/** @num_ddr_channels: Number of DDR channels */
u32 num_ddr_channels;
};
/**

8
adreno_gen7_gmu.c
View File

@ -1987,7 +1987,9 @@ static int gen7_gmu_first_boot(struct adreno_device *adreno_dev)
if (ret)
goto err;
if (gen7_hfi_send_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE, 0) == 1) {
if (gen7_hfi_send_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE, 0) == 1 &&
!WARN_ONCE(!adreno_dev->gpucore->num_ddr_channels,
"Number of DDR channel is not specified in gpu core")) {
adreno_dev->gmu_ab = true;
set_bit(ADRENO_DEVICE_GMU_AB, &adreno_dev->priv);
}
@ -2241,8 +2243,6 @@ static int gen7_gmu_bus_set(struct adreno_device *adreno_dev, int buslevel,
return ret;
}
#define NUM_CHANNELS 4
u32 gen7_bus_ab_quantize(struct adreno_device *adreno_dev, u32 ab)
{
u16 vote = 0;
@ -2257,7 +2257,7 @@ u32 gen7_bus_ab_quantize(struct adreno_device *adreno_dev, u32 ab)
* max ddr bandwidth (kbps) = (Max bw in kbps per channel * number of channel)
* max ab (Mbps) = max ddr bandwidth (kbps) / 1000
*/
max_bw = pwr->ddr_table[pwr->ddr_table_count - 1] * NUM_CHANNELS;
max_bw = pwr->ddr_table[pwr->ddr_table_count - 1] * adreno_dev->gpucore->num_ddr_channels;
max_ab = max_bw / 1000;
/*

4
adreno_gen7_hwsched.c
View File

@ -562,7 +562,9 @@ static int gen7_hwsched_gmu_first_boot(struct adreno_device *adreno_dev)
goto err;
}
if (gen7_hwsched_hfi_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE) == 1) {
if (gen7_hwsched_hfi_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE) == 1 &&
!WARN_ONCE(!adreno_dev->gpucore->num_ddr_channels,
"Number of DDR channel is not specified in gpu core")) {
adreno_dev->gmu_ab = true;
set_bit(ADRENO_DEVICE_GMU_AB, &adreno_dev->priv);
}

8
adreno_gen8_gmu.c
View File

@ -1895,7 +1895,9 @@ static int gen8_gmu_first_boot(struct adreno_device *adreno_dev)
if (ret)
goto err;
if (gen8_hfi_send_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE, 0) == 1) {
if (gen8_hfi_send_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE, 0) == 1 &&
!WARN_ONCE(!adreno_dev->gpucore->num_ddr_channels,
"Number of DDR channel is not specified in gpu core")) {
adreno_dev->gmu_ab = true;
set_bit(ADRENO_DEVICE_GMU_AB, &adreno_dev->priv);
}
@ -2144,8 +2146,6 @@ static int gen8_gmu_bus_set(struct adreno_device *adreno_dev, int buslevel,
return ret;
}
#define NUM_CHANNELS 4
u32 gen8_bus_ab_quantize(struct adreno_device *adreno_dev, u32 ab)
{
u16 vote = 0;
@ -2160,7 +2160,7 @@ u32 gen8_bus_ab_quantize(struct adreno_device *adreno_dev, u32 ab)
* max ddr bandwidth (kbps) = (Max bw in kbps per channel * number of channel)
* max ab (Mbps) = max ddr bandwidth (kbps) / 1000
*/
max_bw = pwr->ddr_table[pwr->ddr_table_count - 1] * NUM_CHANNELS;
max_bw = pwr->ddr_table[pwr->ddr_table_count - 1] * adreno_dev->gpucore->num_ddr_channels;
max_ab = max_bw / 1000;
/*

4
adreno_gen8_hwsched.c
View File

@ -543,7 +543,9 @@ static int gen8_hwsched_gmu_first_boot(struct adreno_device *adreno_dev)
goto err;
}
if (gen8_hwsched_hfi_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE) == 1) {
if (gen8_hwsched_hfi_get_value(adreno_dev, HFI_VALUE_GMU_AB_VOTE) == 1 &&
!WARN_ONCE(!adreno_dev->gpucore->num_ddr_channels,
"Number of DDR channel is not specified in gpu core")) {
adreno_dev->gmu_ab = true;
set_bit(ADRENO_DEVICE_GMU_AB, &adreno_dev->priv);
}