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fw-api: Add HW header files for QCA5018

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Add the E3 release HW header files for QCA5018

Change-Id: Iab5b1cedf7b72f391adc4ebe57a4376a9c1c4239
This commit is contained in:
Basamma Yakkanahalli 2020-04-17 04:55:05 +05:30 committed by Gerrit - the friendly Code Review server
parent b331b8d91d
commit 84c021cfef
99 changed files with 109166 additions and 0 deletions
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131
hw/qca5018/HALcomdef.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_COMDEF_H
#define HAL_COMDEF_H
/*
==============================================================================
FILE: HALcomdef.h
DESCRIPTION:
==============================================================================
Edit History
$Header: //depot/prj/qca/lithium3/wcss/maple_verif/native/register/include/HALcomdef.h#1 $
when who what, where, why
-------- --- -----------------------------------------------------------
06/17/10 sc Included com_dtypes.h and cleaned up typedefs
05/15/08 gfr Added HAL_ENUM_32BITS macro.
02/14/08 gfr Added bool32 type.
11/13/07 gfr Removed dependency on comdef.h
01/08/07 hxw Created
==============================================================================
*/
/*
* Assembly wrapper
*/
#ifndef _ARM_ASM_
/*
* C++ wrapper
*/
#ifdef __cplusplus
extern "C" {
#endif
#include "com_dtypes.h"
/* -----------------------------------------------------------------------
** Types
** ----------------------------------------------------------------------- */
/*
* Standard integer types.
*
* bool32 - boolean, 32 bit (TRUE or FALSE)
*/
#ifndef _BOOL32_DEFINED
typedef unsigned long int bool32;
#define _BOOL32_DEFINED
#endif
/*
* Macro to allow forcing an enum to 32 bits. The argument should be
* an identifier in the namespace of the enumeration in question, i.e.
* for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
*/
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
/*===========================================================================
FUNCTION inp, outp, inpw, outpw, inpdw, outpdw
DESCRIPTION
IN/OUT port macros for byte and word ports, typically inlined by compilers
which support these routines
PARAMETERS
inp( xx_addr )
inpw( xx_addr )
inpdw( xx_addr )
outp( xx_addr, xx_byte_val )
outpw( xx_addr, xx_word_val )
outpdw( xx_addr, xx_dword_val )
xx_addr - Address of port to read or write (may be memory mapped)
xx_byte_val - 8 bit value to write
xx_word_val - 16 bit value to write
xx_dword_val - 32 bit value to write
DEPENDENCIES
None
RETURN VALUE
inp/inpw/inpdw: the byte, word or dword read from the given address
outp/outpw/outpdw: the byte, word or dword written to the given address
SIDE EFFECTS
None.
===========================================================================*/
/* ARM based targets use memory mapped i/o, so the inp/outp calls are
** macroized to access memory directly
*/
#if defined(VV_FEATURE_COMPILING_64BIT)
#define inp(port) (*((volatile dword *) (port)))
#define inpw(port) (*((volatile word *) (port)))
#define inpdw(port) (*((volatile dword *)(port)))
#define outp(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
#endif
#ifdef __cplusplus
}
#endif
#endif /* !_ARM_ASM_ */
#endif /* HAL_COMDEF_H */

490
hw/qca5018/HALhwio.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_HWIO_H
#define HAL_HWIO_H
/*
===========================================================================
*/
/**
@file HALhwio.h
Public interface include file for accessing the HWIO HAL definitions.
The HALhwio.h file is the public API interface to the HW I/O (HWIO)
register access definitions.
*/
/*=========================================================================
Include Files
==========================================================================*/
/*
* Common types.
*/
#include "HALcomdef.h"
/* -----------------------------------------------------------------------
** Macros
** ----------------------------------------------------------------------- */
#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET
#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET
/**
@addtogroup macros
@{
*/
/**
* Map a base name to the pointer to access the base.
*
* This macro maps a base name to the pointer to access the base.
* This is generally just used internally.
*
*/
#define HWIO_BASE_PTR(base) base##_BASE_PTR
/**
* Declare a HWIO base pointer.
*
* This macro will declare a HWIO base pointer data structure. The pointer
* will always be declared as a weak symbol so multiple declarations will
* resolve correctly to the same data at link-time.
*/
#ifdef __ARMCC_VERSION
#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
#else
#define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
#endif
/**
@}
*/
/**
@addtogroup hwio_macros
@{
*/
/**
* @name Address Macros
*
* Macros for getting register addresses.
* These macros are used for retrieving the address of a register.
* HWIO_ADDR* will return the directly accessible address (virtual or physical based
* on environment), HWIO_PHYS* will always return the physical address.
* The offset from the base region can be retrieved using HWIO_OFFS*.
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
*
* @{
*/
#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
/** @} */
/**
* @name Input Macros
*
* These macros are used for reading from a named hardware register. Register
* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
* indicates that the input will be masked with the supplied mask. The HWIO_INF*
* macros take a field name and will do the appropriate masking and shifting
* to return just the value of that field.
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
*
* Generally you want to use either HWIO_IN or HWIO_INF (with required indexing).
*
* @{
*/
#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
/** @} */
/**
* @name Output Macros
*
* These macros are used for writing to a named hardware register. Register
* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
* indicates that the output will be masked with the supplied mask (meaning these
* macros do a read first, mask in the supplied data, then write it back).
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
* The HWIO_OUTF* macros take a field name and will do the appropriate masking
* and shifting to output just the value of that field.
* HWIO_OUTV* registers take a named value instead of a numeric value and
* do the same masking/shifting as HWIO_OUTF.
*
* Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing).
*
* @{
*/
#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
/** @} */
/**
* @name Shift and Mask Macros
*
* Macros for getting shift and mask values for fields and registers.
* HWIO_RMSK: The mask value for accessing an entire register. For example:
* @code
* HWIO_RMSK(REG) -> 0xFFFFFFFF
* @endcode
* HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n
* HWIO_SHFT: The right-shift value for accessing a field in a register. For example:
* @code
* HWIO_SHFT(REG, FLD) -> 8
* @endcode
* HWIO_FMSK: The mask value for accessing a field in a register. For example:
* @code
* HWIO_FMSK(REG, FLD) -> 0xFF00
* @endcode
* HWIO_VAL: The value for a field in a register. For example:
* @code
* HWIO_VAL(REG, FLD, ON) -> 0x1
* @endcode
* HWIO_FVAL: This macro takes a numerical value and will shift and mask it into
* the given field position. For example:
* @code
* HWIO_FVAL(REG, FLD, 0x1) -> 0x100
* @endcode
* HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it
* into the given field position. For example:
* @code
* HWIO_FVALV(REG, FLD, ON) -> 0x100
* @endcode
*
* @{
*/
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
/** @} */
/**
* @name Shadow Register Macros
*
* These macros are used for directly reading the value stored in a
* shadow register.
* Shadow registers are defined for write-only registers. Generally these
* macros should not be necessary as HWIO_OUTM* macros will automatically use
* the shadow values internally.
*
* @{
*/
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
/** @} */
/**
@}
*/ /* end_group */
/** @cond */
/*
* Map to final symbols. This remapping is done to allow register
* redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN
* then remappings like "#define xreg xregnew" do not work as expected.
*/
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
}
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
}
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
HWIO_##hwiosym##_OUTM(base, mask4, val4); \
}
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
/*
* HWIO_INTLOCK
*
* Macro used by autogenerated code for mutual exclusion around
* read-mask-write operations. This is not supported in HAL
* code but can be overridden by non-HAL code.
*/
#define HWIO_INTLOCK()
#define HWIO_INTFREE()
/*
* Input/output port macros for memory mapped IO.
*/
#define __inp(port) (*((volatile uint8 *) (port)))
#define __inpw(port) (*((volatile uint16 *) (port)))
#define __inpdw(port) (*((volatile uint32 *) (port)))
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
#ifdef HAL_HWIO_EXTERNAL
/*
* Replace macros with externally supplied functions.
*/
#undef __inp
#undef __inpw
#undef __inpdw
#undef __outp
#undef __outpw
#undef __outpdw
#define __inp(port) __inp_extern(port)
#define __inpw(port) __inpw_extern(port)
#define __inpdw(port) __inpdw_extern(port)
#define __outp(port, val) __outp_extern(port, val)
#define __outpw(port, val) __outpw_extern(port, val)
#define __outpdw(port, val) __outpdw_extern(port, val)
extern uint8 __inp_extern ( uint32 nAddr );
extern uint16 __inpw_extern ( uint32 nAddr );
extern uint32 __inpdw_extern ( uint32 nAddr );
extern void __outp_extern ( uint32 nAddr, uint8 nData );
extern void __outpw_extern ( uint32 nAddr, uint16 nData );
extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
#endif /* HAL_HWIO_EXTERNAL */
/*
* Base 8-bit byte accessing macros.
*/
#define in_byte(addr) (__inp(addr))
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
#define out_byte(addr, val) __outp(addr,val)
#define out_byte_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
out_byte( io, shadow); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
HWIO_INTFREE()
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
/*
* Base 16-bit word accessing macros.
*/
#define in_word(addr) (__inpw(addr))
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
#define out_word(addr, val) __outpw(addr,val)
#define out_word_masked(io, mask, val, shadow) \
HWIO_INTLOCK( ); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
out_word( io, shadow); \
HWIO_INTFREE( )
#define out_word_masked_ns(io, mask, val, current_reg_content) \
out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
/*
* Base 32-bit double-word accessing macros.
*/
#define in_dword(addr) (__inpdw(addr))
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
#define out_dword(addr, val) __outpdw(addr,val)
#define out_dword_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
out_dword( io, shadow); \
HWIO_INTFREE()
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
((uint32)((val) & (mask)))) )
/** @endcond */
#endif /* HAL_HWIO_H */

385
hw/qca5018/buffer_addr_info.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BUFFER_ADDR_INFO_H_
#define _BUFFER_ADDR_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 buffer_addr_31_0[31:0]
// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
struct buffer_addr_info {
uint32_t buffer_addr_31_0 : 32; //[31:0]
uint32_t buffer_addr_39_32 : 8, //[7:0]
return_buffer_manager : 3, //[10:8]
sw_buffer_cookie : 21; //[31:11]
};
/*
buffer_addr_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
buffer_addr_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
return_buffer_manager
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<enum 7 SW4_BM> This buffer shall be returned to the SW,
ring 4
<legal all>
sw_buffer_cookie
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE1:
The three most significant bits can have a special
meaning in case this struct is embedded in a TX_MPDU_DETAILS
STRUCT, and field transmit_bw_restriction is set
In case of NON punctured transmission:
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
In case of punctured transmission:
Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
Note: a punctured transmission is indicated by the
presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
TLV
NOTE 2:The five most significant bits can have a special
meaning in case this struct is embedded in an
RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
configured for passing on the additional info
from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
(FR56821). This is not supported in HastingsPrime, Pine or
Moselle.
Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
control field
Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
indicates MPDUs with a QoS control field.
<legal all>
*/
/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<enum 7 SW4_BM> This buffer shall be returned to the SW,
ring 4
<legal all>
*/
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE1:
The three most significant bits can have a special
meaning in case this struct is embedded in a TX_MPDU_DETAILS
STRUCT, and field transmit_bw_restriction is set
In case of NON punctured transmission:
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
In case of punctured transmission:
Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
Note: a punctured transmission is indicated by the
presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
TLV
NOTE 2:The five most significant bits can have a special
meaning in case this struct is embedded in an
RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
configured for passing on the additional info
from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
(FR56821). This is not supported in HastingsPrime, Pine or
Moselle.
Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
control field
Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
indicates MPDUs with a QoS control field.
<legal all>
*/
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800
#endif // _BUFFER_ADDR_INFO_H_

352
hw/qca5018/ce_src_desc.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _CE_SRC_DESC_H_
#define _CE_SRC_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 src_buffer_low[31:0]
// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16]
// 2 fw_metadata[15:0], ce_res_1[31:16]
// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_CE_SRC_DESC 4
struct ce_src_desc {
uint32_t src_buffer_low : 32; //[31:0]
uint32_t src_buffer_high : 8, //[7:0]
toeplitz_en : 1, //[8]
src_swap : 1, //[9]
dest_swap : 1, //[10]
gather : 1, //[11]
ce_res_0 : 4, //[15:12]
length : 16; //[31:16]
uint32_t fw_metadata : 16, //[15:0]
ce_res_1 : 16; //[31:16]
uint32_t ce_res_2 : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
src_buffer_low
LSB 32 bits of the 40 Bit Pointer to the source buffer
<legal all>
src_buffer_high
MSB 8 bits of the 40 Bit Pointer to the source buffer
<legal all>
toeplitz_en
Enable generation of 32-bit Toeplitz-LFSR hash for the
data transfer
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
src_swap
Treats source memory organization as big-endian. For
each dword read (4 bytes), the byte 0 is swapped with byte 3
and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
dest_swap
Treats destination memory organization as big-endian.
For each dword write (4 bytes), the byte 0 is swapped with
byte 3 and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
gather
Enables gather of multiple copy engine source
descriptors to one destination.
<legal all>
ce_res_0
Reserved
<legal all>
length
Length of the buffer in units of octets of the current
descriptor
<legal all>
fw_metadata
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
ce_res_1
Reserved
<legal all>
ce_res_2
Reserved
<legal all>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW
LSB 32 bits of the 40 Bit Pointer to the source buffer
<legal all>
*/
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff
/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH
MSB 8 bits of the 40 Bit Pointer to the source buffer
<legal all>
*/
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff
/* Description CE_SRC_DESC_1_TOEPLITZ_EN
Enable generation of 32-bit Toeplitz-LFSR hash for the
data transfer
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004
#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8
#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100
/* Description CE_SRC_DESC_1_SRC_SWAP
Treats source memory organization as big-endian. For
each dword read (4 bytes), the byte 0 is swapped with byte 3
and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_1_SRC_SWAP_LSB 9
#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200
/* Description CE_SRC_DESC_1_DEST_SWAP
Treats destination memory organization as big-endian.
For each dword write (4 bytes), the byte 0 is swapped with
byte 3 and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_1_DEST_SWAP_LSB 10
#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400
/* Description CE_SRC_DESC_1_GATHER
Enables gather of multiple copy engine source
descriptors to one destination.
<legal all>
*/
#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004
#define CE_SRC_DESC_1_GATHER_LSB 11
#define CE_SRC_DESC_1_GATHER_MASK 0x00000800
/* Description CE_SRC_DESC_1_CE_RES_0
Reserved
<legal all>
*/
#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004
#define CE_SRC_DESC_1_CE_RES_0_LSB 12
#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000
/* Description CE_SRC_DESC_1_LENGTH
Length of the buffer in units of octets of the current
descriptor
<legal all>
*/
#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004
#define CE_SRC_DESC_1_LENGTH_LSB 16
#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000
/* Description CE_SRC_DESC_2_FW_METADATA
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008
#define CE_SRC_DESC_2_FW_METADATA_LSB 0
#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff
/* Description CE_SRC_DESC_2_CE_RES_1
Reserved
<legal all>
*/
#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008
#define CE_SRC_DESC_2_CE_RES_1_LSB 16
#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000
/* Description CE_SRC_DESC_3_CE_RES_2
Reserved
<legal all>
*/
#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c
#define CE_SRC_DESC_3_CE_RES_2_LSB 0
#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff
/* Description CE_SRC_DESC_3_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c
#define CE_SRC_DESC_3_RING_ID_LSB 20
#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000
/* Description CE_SRC_DESC_3_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28
#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000
#endif // _CE_SRC_DESC_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _CE_STAT_DESC_H_
#define _CE_STAT_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16]
// 1 toeplitz_hash_0[31:0]
// 2 toeplitz_hash_1[31:0]
// 3 fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_CE_STAT_DESC 4
struct ce_stat_desc {
uint32_t ce_res_5 : 8, //[7:0]
toeplitz_en : 1, //[8]
src_swap : 1, //[9]
dest_swap : 1, //[10]
gather : 1, //[11]
ce_res_6 : 4, //[15:12]
length : 16; //[31:16]
uint32_t toeplitz_hash_0 : 32; //[31:0]
uint32_t toeplitz_hash_1 : 32; //[31:0]
uint32_t fw_metadata : 16, //[15:0]
ce_res_7 : 4, //[19:16]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
ce_res_5
Reserved
<legal all>
toeplitz_en
<legal all>
src_swap
Source memory buffer swapped
<legal all>
dest_swap
Destination memory buffer swapped
<legal all>
gather
Gather of multiple copy engine source descriptors to one
destination enabled
<legal all>
ce_res_6
Reserved
<legal all>
length
Sum of all the Lengths of the source descriptor in the
gather chain
<legal all>
toeplitz_hash_0
32 LS bits of 64 bit Toeplitz LFSR hash result
<legal all>
toeplitz_hash_1
32 MS bits of 64 bit Toeplitz LFSR hash result
<legal all>
fw_metadata
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
ce_res_7
Reserved
<legal all>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description CE_STAT_DESC_0_CE_RES_5
Reserved
<legal all>
*/
#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000
#define CE_STAT_DESC_0_CE_RES_5_LSB 0
#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff
/* Description CE_STAT_DESC_0_TOEPLITZ_EN
<legal all>
*/
#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000
#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8
#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100
/* Description CE_STAT_DESC_0_SRC_SWAP
Source memory buffer swapped
<legal all>
*/
#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_0_SRC_SWAP_LSB 9
#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200
/* Description CE_STAT_DESC_0_DEST_SWAP
Destination memory buffer swapped
<legal all>
*/
#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_0_DEST_SWAP_LSB 10
#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400
/* Description CE_STAT_DESC_0_GATHER
Gather of multiple copy engine source descriptors to one
destination enabled
<legal all>
*/
#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000
#define CE_STAT_DESC_0_GATHER_LSB 11
#define CE_STAT_DESC_0_GATHER_MASK 0x00000800
/* Description CE_STAT_DESC_0_CE_RES_6
Reserved
<legal all>
*/
#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000
#define CE_STAT_DESC_0_CE_RES_6_LSB 12
#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000
/* Description CE_STAT_DESC_0_LENGTH
Sum of all the Lengths of the source descriptor in the
gather chain
<legal all>
*/
#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000
#define CE_STAT_DESC_0_LENGTH_LSB 16
#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000
/* Description CE_STAT_DESC_1_TOEPLITZ_HASH_0
32 LS bits of 64 bit Toeplitz LFSR hash result
<legal all>
*/
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff
/* Description CE_STAT_DESC_2_TOEPLITZ_HASH_1
32 MS bits of 64 bit Toeplitz LFSR hash result
<legal all>
*/
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff
/* Description CE_STAT_DESC_3_FW_METADATA
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c
#define CE_STAT_DESC_3_FW_METADATA_LSB 0
#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff
/* Description CE_STAT_DESC_3_CE_RES_7
Reserved
<legal all>
*/
#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c
#define CE_STAT_DESC_3_CE_RES_7_LSB 16
#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000
/* Description CE_STAT_DESC_3_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c
#define CE_STAT_DESC_3_RING_ID_LSB 20
#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000
/* Description CE_STAT_DESC_3_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28
#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000
#endif // _CE_STAT_DESC_H_

300
hw/qca5018/com_dtypes.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef COM_DTYPES_H
#define COM_DTYPES_H
/**
@file com_dtypes.h
@brief This header file contains general data types that are of use to all
modules.
*/
/*===========================================================================
NOTE: The @brief description and any detailed descriptions above do not appear
in the PDF.
The Utility_Services_API_mainpage.dox file contains all file/group
descriptions that are in the output PDF generated using Doxygen and
Latex. To edit or update any of the file/group text in the PDF, edit
the Utility_Services_API_mainpage.dox file or contact Tech Pubs.
The above description for this file is part of the "utils_services"
group description in the Utility_Services_API_mainpage.dox file.
===========================================================================*/
/*===========================================================================
S T A N D A R D D E C L A R A T I O N S
DESCRIPTION
This header file contains general data types that are of use to all modules.
The values or definitions are dependent on the specified
target. T_WINNT specifies Windows NT based targets, otherwise the
default is for ARM targets.
T_WINNT Software is hosted on an NT platforn, triggers macro and
type definitions, unlike definition above which triggers
actual OS calls
===========================================================================*/
/*===========================================================================
EDIT HISTORY FOR FILE
This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.
$Header: //depot/prj/qca/lithium3/wcss/maple_verif/native/register/include/com_dtypes.h#1 $
when who what, where, why
-------- --- ----------------------------------------------------------
03/21/11 llg (Tech Pubs) Edited/added Doxygen comments and markup.
11/09/10 EBR Doxygenated file.
09/15/09 pc Created file.
===========================================================================*/
/*===========================================================================
Data Declarations
===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
/* For NT apps we want to use the Win32 definitions and/or those
supplied by the Win32 compiler for things like NULL, MAX, MIN
abs, labs, etc.
*/
#ifdef T_WINNT
#ifndef WIN32
#define WIN32
#endif
#include <stdlib.h>
#endif
/* ------------------------------------------------------------------------
** Constants
** ------------------------------------------------------------------------ */
#ifdef TRUE
#undef TRUE
#endif
#ifdef FALSE
#undef FALSE
#endif
/** @addtogroup utils_services
@{ */
/** @name Macros for Common Data Types
@{ */
#define TRUE 1 /**< Boolean TRUE value. */
#define FALSE 0 /**< Boolean FALSE value. */
#define ON 1 /**< ON value. */
#define OFF 0 /**< OFF value. */
#ifndef NULL
#define NULL 0 /**< NULL value. */
#endif
/** @} */ /* end_name_group Macros for Common Data Types */
/* -----------------------------------------------------------------------
** Standard Types
** ----------------------------------------------------------------------- */
/** @} */ /* end_addtogroup utils_services */
/* The following definitions are the same across platforms. This first
group are the sanctioned types.
*/
#ifndef _ARM_ASM_
#ifndef _BOOLEAN_DEFINED
/** @addtogroup utils_services
@{ */
/** Boolean value type.
*/
typedef unsigned char boolean;
#define _BOOLEAN_DEFINED
#endif
/** @cond
*/
#if defined(DALSTDDEF_H) /* guards against a known re-definer */
#define _BOOLEAN_DEFINED
#define _UINT32_DEFINED
#define _UINT16_DEFINED
#define _UINT8_DEFINED
#define _INT32_DEFINED
#define _INT16_DEFINED
#define _INT8_DEFINED
#define _UINT64_DEFINED
#define _INT64_DEFINED
#define _BYTE_DEFINED
#endif /* #if !defined(DALSTDDEF_H) */
/** @endcond */
#ifndef _UINT32_DEFINED
/** Unsigned 32-bit value.
*/
typedef unsigned long int uint32;
#define _UINT32_DEFINED
#endif
#ifndef _UINT16_DEFINED
/** Unsigned 16-bit value.
*/
typedef unsigned short uint16;
#define _UINT16_DEFINED
#endif
#ifndef _UINT8_DEFINED
/** Unsigned 8-bit value.
*/
typedef unsigned char uint8;
#define _UINT8_DEFINED
#endif
#ifndef _INT32_DEFINED
/** Signed 32-bit value.
*/
typedef signed long int int32;
#define _INT32_DEFINED
#endif
#ifndef _INT16_DEFINED
/** Signed 16-bit value.
*/
typedef signed short int16;
#define _INT16_DEFINED
#endif
#ifndef _INT8_DEFINED
/** Signed 8-bit value.
*/
typedef signed char int8;
#define _INT8_DEFINED
#endif
/** @cond
*/
/* This group are the deprecated types. Their use should be
** discontinued and new code should use the types above
*/
#ifndef _BYTE_DEFINED
/** DEPRECATED: Unsigned 8 bit value type.
*/
typedef unsigned char byte;
#define _BYTE_DEFINED
#endif
/** DEPRECATED: Unsinged 16 bit value type.
*/
typedef unsigned short word;
/** DEPRECATED: Unsigned 32 bit value type.
*/
typedef unsigned long dword;
/** DEPRECATED: Unsigned 8 bit value type.
*/
typedef unsigned char uint1;
/** DEPRECATED: Unsigned 16 bit value type.
*/
typedef unsigned short uint2;
/** DEPRECATED: Unsigned 32 bit value type.
*/
typedef unsigned long uint4;
/** DEPRECATED: Signed 8 bit value type.
*/
typedef signed char int1;
/** DEPRECATED: Signed 16 bit value type.
*/
typedef signed short int2;
/** DEPRECATED: Signed 32 bit value type.
*/
typedef long int int4;
/** DEPRECATED: Signed 32 bit value.
*/
typedef signed long sint31;
/** DEPRECATED: Signed 16 bit value.
*/
typedef signed short sint15;
/** DEPRECATED: Signed 8 bit value.
*/
typedef signed char sint7;
typedef uint16 UWord16 ;
typedef uint32 UWord32 ;
typedef int32 Word32 ;
typedef int16 Word16 ;
typedef uint8 UWord8 ;
typedef int8 Word8 ;
typedef int32 Vect32 ;
/** @endcond */
#if (! defined T_WINNT) && (! defined __GNUC__)
/* Non WinNT Targets */
#ifndef _INT64_DEFINED
/** Signed 64-bit value.
*/
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
/** Unsigned 64-bit value.
*/
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */
/* WINNT or SOLARIS based targets */
#if (defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
typedef __int64 int64; /* Signed 64-bit value */
#ifndef _UINT64_DEFINED
typedef unsigned __int64 uint64; /* Unsigned 64-bit value */
#define _UINT64_DEFINED
#endif
#endif
#endif /* T_WINNT */
#endif /* _ARM_ASM_ */
#ifdef __cplusplus
}
#endif
/** @} */ /* end_addtogroup utils_services */
#endif /* COM_DTYPES_H */

686
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_MU_DL_INFO_H_
#define _HE_SIG_A_MU_DL_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 dl_ul_flag[0], mcs_of_sig_b[3:1], dcm_of_sig_b[4], bss_color_id[10:5], spatial_reuse[14:11], transmit_bw[17:15], num_sig_b_symbols[21:18], comp_mode_sig_b[22], cp_ltf_size[24:23], doppler_indication[25], reserved_0a[31:26]
// 1 txop_duration[6:0], reserved_1a[7], num_ltf_symbols[10:8], ldpc_extra_symbol[11], stbc[12], packet_extension_a_factor[14:13], packet_extension_pe_disambiguity[15], crc[19:16], tail[25:20], reserved_1b[31:26]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
struct he_sig_a_mu_dl_info {
uint32_t dl_ul_flag : 1, //[0]
mcs_of_sig_b : 3, //[3:1]
dcm_of_sig_b : 1, //[4]
bss_color_id : 6, //[10:5]
spatial_reuse : 4, //[14:11]
transmit_bw : 3, //[17:15]
num_sig_b_symbols : 4, //[21:18]
comp_mode_sig_b : 1, //[22]
cp_ltf_size : 2, //[24:23]
doppler_indication : 1, //[25]
reserved_0a : 6; //[31:26]
uint32_t txop_duration : 7, //[6:0]
reserved_1a : 1, //[7]
num_ltf_symbols : 3, //[10:8]
ldpc_extra_symbol : 1, //[11]
stbc : 1, //[12]
packet_extension_a_factor : 2, //[14:13]
packet_extension_pe_disambiguity: 1, //[15]
crc : 4, //[19:16]
tail : 6, //[25:20]
reserved_1b : 6; //[31:26]
};
/*
dl_ul_flag
Differentiates between DL and UL transmission
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
<enum 1 DL_UL_FLAG_IS_UL>
NOTE: This is unsupported for HE MU format (including
MU_SU) Tx in Napier and Hastings80.
<legal all>
mcs_of_sig_b
Indicates the MCS of HE-SIG-B
<legal 0-5>
dcm_of_sig_b
Indicates whether dual sub-carrier modulation is applied
to HE-SIG-B
0: No DCM for HE_SIG_B
1: DCM for HE_SIG_B
<legal all>
bss_color_id
BSS color ID
Field Used by MAC HW
<legal all>
spatial_reuse
Spatial reuse
For 20MHz one SR field corresponding to entire 20MHz
(other 3 fields indicate identical values)
For 40MHz two SR fields for each 20MHz (other 2 fields
indicate identical values)
For 80MHz four SR fields for each 20MHz
For 160MHz four SR fields for each 40MHz
<legal all>
transmit_bw
Bandwidth of the PPDU.
<enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
<enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
<enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble
puncturing mode
<enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz
non-preamble puncturing mode
<enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble
puncturing in 80 MHz, where in the preamble only the
secondary 20 MHz is punctured
<enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for
preamble puncturing in 80 MHz, where in the preamble only
one of the two 20 MHz sub-channels in secondary 40 MHz is
punctured.
<enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble
puncturing in 160 MHz or 80+80 MHz, where in the primary 80
MHz of the preamble only the secondary 20 MHz is punctured.
<enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for
preamble puncturing in 160 MHz or 80+80 MHz, where in the
primary 80 MHz of the preamble the primary 40 MHz is
present.
On RX side, Field Used by MAC HW
<legal 0-7>
num_sig_b_symbols
Number of symbols
For OFDMA, the actual number of symbols is 1 larger then
indicated in this field.
For MU-MIMO this is equal to the number of users - 1:
the following encoding is used:
1 => 2 users
2 => 3 users
Etc.
<legal all>
comp_mode_sig_b
Indicates the compression mode of HE-SIG-B
0: Regular [uncomp mode]
1: compressed mode (full-BW MU-MIMO only)
<legal all>
cp_ltf_size
Indicates the CP and HE-LTF type
<enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
<enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
<enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
<enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
<legal all>
doppler_indication
0: No Doppler support
1: Doppler support
<legal all>
reserved_0a
<legal 0>
txop_duration
Indicates the remaining time in the current TXOP
Field Used by MAC HW
<legal all>
reserved_1a
Note: spec indicates this shall be set to 1
<legal 1>
num_ltf_symbols
Indicates the number of HE-LTF symbols
0: 1 LTF
1: 2 LTFs
2: 4 LTFs
3: 6 LTFs
4: 8 LTFs
<legal all>
ldpc_extra_symbol
If LDPC,
0: LDPC extra symbol not present
1: LDPC extra symbol present
Else
Set to 1
<legal all>
stbc
Indicates whether STBC is applied
0: No STBC
1: STBC
<legal all>
packet_extension_a_factor
the packet extension duration of the trigger-based PPDU
response with these two bits indicating the a-factor
<enum 0 a_factor_4>
<enum 1 a_factor_1>
<enum 2 a_factor_2>
<enum 3 a_factor_3>
<legal all>
packet_extension_pe_disambiguity
the packet extension duration of the trigger-based PPDU
response with this bit indicating the PE-Disambiguity
<legal all>
crc
CRC for HE-SIG-A contents.
<legal all>
tail
<legal 0>
reserved_1b
<legal 0>
*/
/* Description HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG
Differentiates between DL and UL transmission
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
<enum 1 DL_UL_FLAG_IS_UL>
NOTE: This is unsupported for HE MU format (including
MU_SU) Tx in Napier and Hastings80.
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB 0
#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK 0x00000001
/* Description HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B
Indicates the MCS of HE-SIG-B
<legal 0-5>
*/
#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB 1
#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK 0x0000000e
/* Description HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B
Indicates whether dual sub-carrier modulation is applied
to HE-SIG-B
0: No DCM for HE_SIG_B
1: DCM for HE_SIG_B
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB 4
#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK 0x00000010
/* Description HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID
BSS color ID
Field Used by MAC HW
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB 5
#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK 0x000007e0
/* Description HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE
Spatial reuse
For 20MHz one SR field corresponding to entire 20MHz
(other 3 fields indicate identical values)
For 40MHz two SR fields for each 20MHz (other 2 fields
indicate identical values)
For 80MHz four SR fields for each 20MHz
For 160MHz four SR fields for each 40MHz
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB 11
#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK 0x00007800
/* Description HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW
Bandwidth of the PPDU.
<enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
<enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
<enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble
puncturing mode
<enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz
non-preamble puncturing mode
<enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble
puncturing in 80 MHz, where in the preamble only the
secondary 20 MHz is punctured
<enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for
preamble puncturing in 80 MHz, where in the preamble only
one of the two 20 MHz sub-channels in secondary 40 MHz is
punctured.
<enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble
puncturing in 160 MHz or 80+80 MHz, where in the primary 80
MHz of the preamble only the secondary 20 MHz is punctured.
<enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for
preamble puncturing in 160 MHz or 80+80 MHz, where in the
primary 80 MHz of the preamble the primary 40 MHz is
present.
On RX side, Field Used by MAC HW
<legal 0-7>
*/
#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB 15
#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK 0x00038000
/* Description HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS
Number of symbols
For OFDMA, the actual number of symbols is 1 larger then
indicated in this field.
For MU-MIMO this is equal to the number of users - 1:
the following encoding is used:
1 => 2 users
2 => 3 users
Etc.
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB 18
#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
/* Description HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B
Indicates the compression mode of HE-SIG-B
0: Regular [uncomp mode]
1: compressed mode (full-BW MU-MIMO only)
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB 22
#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK 0x00400000
/* Description HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE
Indicates the CP and HE-LTF type
<enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
<enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
<enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
<enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB 23
#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK 0x01800000
/* Description HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION
0: No Doppler support
1: Doppler support
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB 25
#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK 0x02000000
/* Description HE_SIG_A_MU_DL_INFO_0_RESERVED_0A
<legal 0>
*/
#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB 26
#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK 0xfc000000
/* Description HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION
Indicates the remaining time in the current TXOP
Field Used by MAC HW
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK 0x0000007f
/* Description HE_SIG_A_MU_DL_INFO_1_RESERVED_1A
Note: spec indicates this shall be set to 1
<legal 1>
*/
#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK 0x00000080
/* Description HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS
Indicates the number of HE-LTF symbols
0: 1 LTF
1: 2 LTFs
2: 4 LTFs
3: 6 LTFs
4: 8 LTFs
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB 8
#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK 0x00000700
/* Description HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL
If LDPC,
0: LDPC extra symbol not present
1: LDPC extra symbol present
Else
Set to 1
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB 11
#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000800
/* Description HE_SIG_A_MU_DL_INFO_1_STBC
Indicates whether STBC is applied
0: No STBC
1: STBC
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB 12
#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK 0x00001000
/* Description HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR
the packet extension duration of the trigger-based PPDU
response with these two bits indicating the a-factor
<enum 0 a_factor_4>
<enum 1 a_factor_1>
<enum 2 a_factor_2>
<enum 3 a_factor_3>
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 13
#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
/* Description HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY
the packet extension duration of the trigger-based PPDU
response with this bit indicating the PE-Disambiguity
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
/* Description HE_SIG_A_MU_DL_INFO_1_CRC
CRC for HE-SIG-A contents.
<legal all>
*/
#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB 16
#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK 0x000f0000
/* Description HE_SIG_A_MU_DL_INFO_1_TAIL
<legal 0>
*/
#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB 20
#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK 0x03f00000
/* Description HE_SIG_A_MU_DL_INFO_1_RESERVED_1B
<legal 0>
*/
#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK 0xfc000000
#endif // _HE_SIG_A_MU_DL_INFO_H_

266
hw/qca5018/he_sig_a_mu_ul_info.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_MU_UL_INFO_H_
#define _HE_SIG_A_MU_UL_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 format_indication[0], bss_color_id[6:1], spatial_reuse[22:7], reserved_0a[23], transmit_bw[25:24], reserved_0b[31:26]
// 1 txop_duration[6:0], reserved_1a[15:7], crc[19:16], tail[25:20], reserved_1b[31:26]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
struct he_sig_a_mu_ul_info {
uint32_t format_indication : 1, //[0]
bss_color_id : 6, //[6:1]
spatial_reuse : 16, //[22:7]
reserved_0a : 1, //[23]
transmit_bw : 2, //[25:24]
reserved_0b : 6; //[31:26]
uint32_t txop_duration : 7, //[6:0]
reserved_1a : 9, //[15:7]
crc : 4, //[19:16]
tail : 6, //[25:20]
reserved_1b : 6; //[31:26]
};
/*
format_indication
Indicates whether the transmission is SU PPDU or a
trigger based UL MU PDDU
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
<legal all>
bss_color_id
BSS color ID
<legal all>
spatial_reuse
Spatial reuse
<legal all>
reserved_0a
Note: spec indicates this shall be set to 1
<legal 1>
transmit_bw
Bandwidth of the PPDU.
<enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
<enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
<enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
<enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
On RX side, Field Used by MAC HW
<legal 0-3>
reserved_0b
<legal 0>
txop_duration
Indicates the remaining time in the current TXOP <legal
all>
reserved_1a
Set to value indicated in the trigger frame
<legal 255>
crc
CRC for HE-SIG-A contents.
This CRC may also cover some fields of L-SIG (TBD)
<legal all>
tail
BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
used
<legal 0>
reserved_1b
<legal 0>
*/
/* Description HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION
Indicates whether the transmission is SU PPDU or a
trigger based UL MU PDDU
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
<legal all>
*/
#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK 0x00000001
/* Description HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID
BSS color ID
<legal all>
*/
#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB 1
#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK 0x0000007e
/* Description HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE
Spatial reuse
<legal all>
*/
#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB 7
#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK 0x007fff80
/* Description HE_SIG_A_MU_UL_INFO_0_RESERVED_0A
Note: spec indicates this shall be set to 1
<legal 1>
*/
#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB 23
#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK 0x00800000
/* Description HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW
Bandwidth of the PPDU.
<enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
<enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
<enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
<enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
On RX side, Field Used by MAC HW
<legal 0-3>
*/
#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB 24
#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK 0x03000000
/* Description HE_SIG_A_MU_UL_INFO_0_RESERVED_0B
<legal 0>
*/
#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB 26
#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK 0xfc000000
/* Description HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION
Indicates the remaining time in the current TXOP <legal
all>
*/
#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK 0x0000007f
/* Description HE_SIG_A_MU_UL_INFO_1_RESERVED_1A
Set to value indicated in the trigger frame
<legal 255>
*/
#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK 0x0000ff80
/* Description HE_SIG_A_MU_UL_INFO_1_CRC
CRC for HE-SIG-A contents.
This CRC may also cover some fields of L-SIG (TBD)
<legal all>
*/
#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB 16
#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK 0x000f0000
/* Description HE_SIG_A_MU_UL_INFO_1_TAIL
BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
used
<legal 0>
*/
#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB 20
#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK 0x03f00000
/* Description HE_SIG_A_MU_UL_INFO_1_RESERVED_1B
<legal 0>
*/
#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK 0xfc000000
#endif // _HE_SIG_A_MU_UL_INFO_H_

832
hw/qca5018/he_sig_a_su_info.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_SU_INFO_H_
#define _HE_SIG_A_SU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 format_indication[0], beam_change[1], dl_ul_flag[2], transmit_mcs[6:3], dcm[7], bss_color_id[13:8], reserved_0a[14], spatial_reuse[18:15], transmit_bw[20:19], cp_ltf_size[22:21], nsts[25:23], reserved_0b[31:26]
// 1 txop_duration[6:0], coding[7], ldpc_extra_symbol[8], stbc[9], txbf[10], packet_extension_a_factor[12:11], packet_extension_pe_disambiguity[13], reserved_1a[14], doppler_indication[15], crc[19:16], tail[25:20], dot11ax_su_extended[26], dot11ax_ext_ru_size[30:27], rx_ndp[31]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
struct he_sig_a_su_info {
uint32_t format_indication : 1, //[0]
beam_change : 1, //[1]
dl_ul_flag : 1, //[2]
transmit_mcs : 4, //[6:3]
dcm : 1, //[7]
bss_color_id : 6, //[13:8]
reserved_0a : 1, //[14]
spatial_reuse : 4, //[18:15]
transmit_bw : 2, //[20:19]
cp_ltf_size : 2, //[22:21]
nsts : 3, //[25:23]
reserved_0b : 6; //[31:26]
uint32_t txop_duration : 7, //[6:0]
coding : 1, //[7]
ldpc_extra_symbol : 1, //[8]
stbc : 1, //[9]
txbf : 1, //[10]
packet_extension_a_factor : 2, //[12:11]
packet_extension_pe_disambiguity: 1, //[13]
reserved_1a : 1, //[14]
doppler_indication : 1, //[15]
crc : 4, //[19:16]
tail : 6, //[25:20]
dot11ax_su_extended : 1, //[26]
dot11ax_ext_ru_size : 4, //[30:27]
rx_ndp : 1; //[31]
};
/*
format_indication
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
<legal all>
beam_change
Indicates whether spatial mapping is changed between
legacy and HE portion of preamble. If not, channel
estimation can include legacy preamble to improve accuracy
<legal all>
dl_ul_flag
Differentiates between DL and UL transmission
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
<enum 1 DL_UL_FLAG_IS_UL>
<legal all>
transmit_mcs
Indicates the data MCS
Field Used by MAC HW
<legal all>
dcm
0: No DCM
1:DCM
<legal all>
bss_color_id
BSS color ID
Field Used by MAC HW
<legal all>
reserved_0a
Note: spec indicates this shall be set to 1
<legal 1>
spatial_reuse
Spatial reuse
For 20MHz one SR field corresponding to entire 20MHz
(other 3 fields indicate identical values)
For 40MHz two SR fields for each 20MHz (other 2 fields
indicate identical values)
For 80MHz four SR fields for each 20MHz
For 160MHz four SR fields for each 40MHz
<legal all>
transmit_bw
Bandwidth of the PPDU.
For HE SU PPDU
<enum 0 HE_SIG_A_BW20> 20 Mhz
<enum 1 HE_SIG_A_BW40> 40 Mhz
<enum 2 HE_SIG_A_BW80> 80 Mhz
<enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
For HE Extended Range SU PPDU
Set to 0 for 242-tone RU
Set to 1 for right 106-tone RU within the primary 20 MHz
On RX side, Field Used by MAC HW
<legal all>
cp_ltf_size
Indicates the CP and HE-LTF type
<enum 3 FourX_LTF_0_8CP_3_2CP>
When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
In this scenario, Neither DCM nor STBC is applied to HE data
field.
NOTE:
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
0 = 1xLTF + 0.4 usec
1 = 2xLTF + 0.4 usec
2~3 = Reserved
<legal all>
nsts
For HE SU PPDU
For HE Extended Range PPDU
<legal all>
reserved_0b
<legal 0>
txop_duration
Indicates the remaining time in the current TXOP
Field Used by MAC HW
<legal all>
coding
Distinguishes between BCC and LDPC coding.
0: BCC
1: LDPC
<legal all>
ldpc_extra_symbol
If LDPC,
0: LDPC extra symbol not present
1: LDPC extra symbol present
Else
Set to 1
<legal all>
stbc
Indicates whether STBC is applied
0: No STBC
1: STBC
<legal all>
txbf
Indicates whether beamforming is applied
0: No beamforming
1: beamforming
<legal all>
packet_extension_a_factor
Common trigger info
the packet extension duration of the trigger-based PPDU
response with these two bits indicating the a-factor
<enum 0 a_factor_4>
<enum 1 a_factor_1>
<enum 2 a_factor_2>
<enum 3 a_factor_3>
<legal all>
packet_extension_pe_disambiguity
Common trigger info
the packet extension duration of the trigger-based PPDU
response with this bit indicating the PE-Disambiguity
<legal all>
reserved_1a
Note: per standard, set to 1
<legal 1>
doppler_indication
0: No Doppler support
1: Doppler support
<legal all>
crc
CRC for HE-SIG-A contents.
<legal all>
tail
<legal 0>
dot11ax_su_extended
TX side:
Set to 0
RX side:
On RX side, evaluated by MAC HW. This is the only way
for MAC RX to know that this was an HE_SIG_A_SU received in
'extended' format
<legal all>
dot11ax_ext_ru_size
TX side:
Set to 0
RX side:
Field only contains valid info when dot11ax_su_extended
is set.
On RX side, evaluated by MAC HW. This is the only way
for MAC RX to know what the number of based RUs was in this
extended range reception. It is used by the MAC to determine
the RU size for the response...
<legal all>
rx_ndp
TX side:
Set to 0
RX side:Valid on RX side only, and looked at by MAC HW
When set, PHY has received (expected) NDP frame
<legal all>
*/
/* Description HE_SIG_A_SU_INFO_0_FORMAT_INDICATION
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK 0x00000001
/* Description HE_SIG_A_SU_INFO_0_BEAM_CHANGE
Indicates whether spatial mapping is changed between
legacy and HE portion of preamble. If not, channel
estimation can include legacy preamble to improve accuracy
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB 1
#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK 0x00000002
/* Description HE_SIG_A_SU_INFO_0_DL_UL_FLAG
Differentiates between DL and UL transmission
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
<enum 1 DL_UL_FLAG_IS_UL>
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB 2
#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK 0x00000004
/* Description HE_SIG_A_SU_INFO_0_TRANSMIT_MCS
Indicates the data MCS
Field Used by MAC HW
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB 3
#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK 0x00000078
/* Description HE_SIG_A_SU_INFO_0_DCM
0: No DCM
1:DCM
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_DCM_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_DCM_LSB 7
#define HE_SIG_A_SU_INFO_0_DCM_MASK 0x00000080
/* Description HE_SIG_A_SU_INFO_0_BSS_COLOR_ID
BSS color ID
Field Used by MAC HW
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB 8
#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK 0x00003f00
/* Description HE_SIG_A_SU_INFO_0_RESERVED_0A
Note: spec indicates this shall be set to 1
<legal 1>
*/
#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB 14
#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK 0x00004000
/* Description HE_SIG_A_SU_INFO_0_SPATIAL_REUSE
Spatial reuse
For 20MHz one SR field corresponding to entire 20MHz
(other 3 fields indicate identical values)
For 40MHz two SR fields for each 20MHz (other 2 fields
indicate identical values)
For 80MHz four SR fields for each 20MHz
For 160MHz four SR fields for each 40MHz
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB 15
#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK 0x00078000
/* Description HE_SIG_A_SU_INFO_0_TRANSMIT_BW
Bandwidth of the PPDU.
For HE SU PPDU
<enum 0 HE_SIG_A_BW20> 20 Mhz
<enum 1 HE_SIG_A_BW40> 40 Mhz
<enum 2 HE_SIG_A_BW80> 80 Mhz
<enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
For HE Extended Range SU PPDU
Set to 0 for 242-tone RU
Set to 1 for right 106-tone RU within the primary 20 MHz
On RX side, Field Used by MAC HW
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB 19
#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK 0x00180000
/* Description HE_SIG_A_SU_INFO_0_CP_LTF_SIZE
Indicates the CP and HE-LTF type
<enum 3 FourX_LTF_0_8CP_3_2CP>
When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
In this scenario, Neither DCM nor STBC is applied to HE data
field.
NOTE:
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
0 = 1xLTF + 0.4 usec
1 = 2xLTF + 0.4 usec
2~3 = Reserved
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB 21
#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK 0x00600000
/* Description HE_SIG_A_SU_INFO_0_NSTS
For HE SU PPDU
For HE Extended Range PPDU
<legal all>
*/
#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_NSTS_LSB 23
#define HE_SIG_A_SU_INFO_0_NSTS_MASK 0x03800000
/* Description HE_SIG_A_SU_INFO_0_RESERVED_0B
<legal 0>
*/
#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB 26
#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK 0xfc000000
/* Description HE_SIG_A_SU_INFO_1_TXOP_DURATION
Indicates the remaining time in the current TXOP
Field Used by MAC HW
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB 0
#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK 0x0000007f
/* Description HE_SIG_A_SU_INFO_1_CODING
Distinguishes between BCC and LDPC coding.
0: BCC
1: LDPC
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_CODING_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_CODING_LSB 7
#define HE_SIG_A_SU_INFO_1_CODING_MASK 0x00000080
/* Description HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL
If LDPC,
0: LDPC extra symbol not present
1: LDPC extra symbol present
Else
Set to 1
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB 8
#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000100
/* Description HE_SIG_A_SU_INFO_1_STBC
Indicates whether STBC is applied
0: No STBC
1: STBC
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_STBC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_STBC_LSB 9
#define HE_SIG_A_SU_INFO_1_STBC_MASK 0x00000200
/* Description HE_SIG_A_SU_INFO_1_TXBF
Indicates whether beamforming is applied
0: No beamforming
1: beamforming
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_TXBF_LSB 10
#define HE_SIG_A_SU_INFO_1_TXBF_MASK 0x00000400
/* Description HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR
Common trigger info
the packet extension duration of the trigger-based PPDU
response with these two bits indicating the a-factor
<enum 0 a_factor_4>
<enum 1 a_factor_1>
<enum 2 a_factor_2>
<enum 3 a_factor_3>
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 11
#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
/* Description HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY
Common trigger info
the packet extension duration of the trigger-based PPDU
response with this bit indicating the PE-Disambiguity
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
/* Description HE_SIG_A_SU_INFO_1_RESERVED_1A
Note: per standard, set to 1
<legal 1>
*/
#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB 14
#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK 0x00004000
/* Description HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION
0: No Doppler support
1: Doppler support
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB 15
#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK 0x00008000
/* Description HE_SIG_A_SU_INFO_1_CRC
CRC for HE-SIG-A contents.
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_CRC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_CRC_LSB 16
#define HE_SIG_A_SU_INFO_1_CRC_MASK 0x000f0000
/* Description HE_SIG_A_SU_INFO_1_TAIL
<legal 0>
*/
#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_TAIL_LSB 20
#define HE_SIG_A_SU_INFO_1_TAIL_MASK 0x03f00000
/* Description HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED
TX side:
Set to 0
RX side:
On RX side, evaluated by MAC HW. This is the only way
for MAC RX to know that this was an HE_SIG_A_SU received in
'extended' format
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB 26
#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK 0x04000000
/* Description HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE
TX side:
Set to 0
RX side:
Field only contains valid info when dot11ax_su_extended
is set.
On RX side, evaluated by MAC HW. This is the only way
for MAC RX to know what the number of based RUs was in this
extended range reception. It is used by the MAC to determine
the RU size for the response...
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB 27
#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK 0x78000000
/* Description HE_SIG_A_SU_INFO_1_RX_NDP
TX side:
Set to 0
RX side:Valid on RX side only, and looked at by MAC HW
When set, PHY has received (expected) NDP frame
<legal all>
*/
#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB 31
#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK 0x80000000
#endif // _HE_SIG_A_SU_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B1_MU_INFO_H_
#define _HE_SIG_B1_MU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 ru_allocation[7:0], reserved_0[31:8]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
struct he_sig_b1_mu_info {
uint32_t ru_allocation : 8, //[7:0]
reserved_0 : 24; //[31:8]
};
/*
ru_allocation
RU allocation for the user(s) following this common
portion of the SIG
For details, refer to RU_TYPE description
<legal all>
reserved_0
<legal 0>
*/
/* Description HE_SIG_B1_MU_INFO_0_RU_ALLOCATION
RU allocation for the user(s) following this common
portion of the SIG
For details, refer to RU_TYPE description
<legal all>
*/
#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB 0
#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK 0x000000ff
/* Description HE_SIG_B1_MU_INFO_0_RESERVED_0
<legal 0>
*/
#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB 8
#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK 0xffffff00
#endif // _HE_SIG_B1_MU_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B2_MU_INFO_H_
#define _HE_SIG_B2_MU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 sta_id[10:0], sta_spatial_config[14:11], sta_mcs[18:15], reserved_set_to_1[19], sta_coding[20], reserved_0a[28:21], nsts[31:29]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1
struct he_sig_b2_mu_info {
uint32_t sta_id : 11, //[10:0]
sta_spatial_config : 4, //[14:11]
sta_mcs : 4, //[18:15]
reserved_set_to_1 : 1, //[19]
sta_coding : 1, //[20]
reserved_0a : 8, //[28:21]
nsts : 3; //[31:29]
};
/*
sta_id
Identifies the STA that is addressed. Details of STA ID
are TBD
sta_spatial_config
Number of assigned spatial streams and their
corresponding index.
Total number of spatial streams assigned for the MU-MIMO
allocation is also signaled.
sta_mcs
Indicates the data MCS
reserved_set_to_1
<legal 1>
sta_coding
Distinguishes between BCC/LDPC
0: BCC
1: LDPC
<legal all>
reserved_0a
<legal 0>
nsts
MAC RX side usage only:
Needed by RXPCU. Provided by PHY so that RXPCU does not
need to have the RU number decoding logic.
Number of spatial streams for this user
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
*/
/* Description HE_SIG_B2_MU_INFO_0_STA_ID
Identifies the STA that is addressed. Details of STA ID
are TBD
*/
#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB 0
#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK 0x000007ff
/* Description HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG
Number of assigned spatial streams and their
corresponding index.
Total number of spatial streams assigned for the MU-MIMO
allocation is also signaled.
*/
#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB 11
#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK 0x00007800
/* Description HE_SIG_B2_MU_INFO_0_STA_MCS
Indicates the data MCS
*/
#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB 15
#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK 0x00078000
/* Description HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1
<legal 1>
*/
#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB 19
#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK 0x00080000
/* Description HE_SIG_B2_MU_INFO_0_STA_CODING
Distinguishes between BCC/LDPC
0: BCC
1: LDPC
<legal all>
*/
#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB 20
#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK 0x00100000
/* Description HE_SIG_B2_MU_INFO_0_RESERVED_0A
<legal 0>
*/
#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB 21
#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK 0x1fe00000
/* Description HE_SIG_B2_MU_INFO_0_NSTS
MAC RX side usage only:
Needed by RXPCU. Provided by PHY so that RXPCU does not
need to have the RU number decoding logic.
Number of spatial streams for this user
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
*/
#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_0_NSTS_LSB 29
#define HE_SIG_B2_MU_INFO_0_NSTS_MASK 0xe0000000
#endif // _HE_SIG_B2_MU_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B2_OFDMA_INFO_H_
#define _HE_SIG_B2_OFDMA_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 sta_id[10:0], nsts[13:11], txbf[14], sta_mcs[18:15], sta_dcm[19], sta_coding[20], reserved_0[31:21]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1
struct he_sig_b2_ofdma_info {
uint32_t sta_id : 11, //[10:0]
nsts : 3, //[13:11]
txbf : 1, //[14]
sta_mcs : 4, //[18:15]
sta_dcm : 1, //[19]
sta_coding : 1, //[20]
reserved_0 : 11; //[31:21]
};
/*
sta_id
Identifies the STA that is addressed. Details of STA ID
are TBD
nsts
MAC RX side usage only:
Number of spatial streams for this user
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
txbf
Indicates whether beamforming is applied
0: No beamforming
1: beamforming
<legal all>
sta_mcs
Indicates the data MCS
sta_dcm
0: No DCM
1:DCM
<legal all>
sta_coding
Distinguishes between BCC/LDPC
0: BCC
1: LDPC
<legal all>
reserved_0
<legal 0>
*/
/* Description HE_SIG_B2_OFDMA_INFO_0_STA_ID
Identifies the STA that is addressed. Details of STA ID
are TBD
*/
#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB 0
#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK 0x000007ff
/* Description HE_SIG_B2_OFDMA_INFO_0_NSTS
MAC RX side usage only:
Number of spatial streams for this user
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
*/
#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB 11
#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK 0x00003800
/* Description HE_SIG_B2_OFDMA_INFO_0_TXBF
Indicates whether beamforming is applied
0: No beamforming
1: beamforming
<legal all>
*/
#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB 14
#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK 0x00004000
/* Description HE_SIG_B2_OFDMA_INFO_0_STA_MCS
Indicates the data MCS
*/
#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB 15
#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK 0x00078000
/* Description HE_SIG_B2_OFDMA_INFO_0_STA_DCM
0: No DCM
1:DCM
<legal all>
*/
#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB 19
#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK 0x00080000
/* Description HE_SIG_B2_OFDMA_INFO_0_STA_CODING
Distinguishes between BCC/LDPC
0: BCC
1: LDPC
<legal all>
*/
#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB 20
#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK 0x00100000
/* Description HE_SIG_B2_OFDMA_INFO_0_RESERVED_0
<legal 0>
*/
#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB 21
#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK 0xffe00000
#endif // _HE_SIG_B2_OFDMA_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HT_SIG_INFO_H_
#define _HT_SIG_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 mcs[6:0], cbw[7], length[23:8], reserved_0[31:24]
// 1 smoothing[0], not_sounding[1], ht_reserved[2], aggregation[3], stbc[5:4], fec_coding[6], short_gi[7], num_ext_sp_str[9:8], crc[17:10], signal_tail[23:18], reserved_1[31:24]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_HT_SIG_INFO 2
struct ht_sig_info {
uint32_t mcs : 7, //[6:0]
cbw : 1, //[7]
length : 16, //[23:8]
reserved_0 : 8; //[31:24]
uint32_t smoothing : 1, //[0]
not_sounding : 1, //[1]
ht_reserved : 1, //[2]
aggregation : 1, //[3]
stbc : 2, //[5:4]
fec_coding : 1, //[6]
short_gi : 1, //[7]
num_ext_sp_str : 2, //[9:8]
crc : 8, //[17:10]
signal_tail : 6, //[23:18]
reserved_1 : 8; //[31:24]
};
/*
mcs
Modulation Coding Scheme:
0-7 are used for single stream
8-15 are used for 2 streams
16-23 are used for 3 streams
24-31 are used for 4 streams
32 is used for duplicate HT20 (unsupported)
33-76 is used for unequal modulation (unsupported)
77-127 is reserved.
<legal 0-31>
cbw
Packet bandwidth:
<enum 0 ht_20_mhz>
<enum 1 ht_40_mhz>
<legal 0-1>
length
This is the MPDU or A-MPDU length in octets of the PPDU
<legal all>
reserved_0
This field is not part of HT-SIG
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
smoothing
Field indicates if smoothing is needed
E_num 0 do_smoothing Unsupported setting: indicates
smoothing is often used for beamforming
<legal 1>
not_sounding
E_num 0 sounding Unsupported setting: indicates
sounding is used
<enum 1 no_sounding> Indicates no sounding is used
<legal 1>
ht_reserved
Reserved: Should be set to 1 by the MAC and ignored by
the PHY
<legal 1>
aggregation
<enum 0 mpdu> Indicates MPDU format
<enum 1 a_mpdu> Indicates A-MPDU format
<legal 0-1>
stbc
<enum 0 no_stbc> Indicates no STBC
<enum 1 1_str_stbc> Indicates 1 stream STBC
E_num 2 2_str_stbc Indicates 2 stream STBC
(Unsupported)
<legal 0-1>
fec_coding
<enum 0 ht_bcc> Indicates BCC coding
<enum 1 ht_ldpc> Indicates LDPC coding
<legal 0-1>
short_gi
<enum 0 ht_normal_gi> Indicates normal guard
interval
<legal 0-1>
num_ext_sp_str
Number of extension spatial streams: (Used for TxBF)
<enum 0 0_ext_sp_str> No extension spatial streams
E_num 1 1_ext_sp_str Not supported: 1 extension
spatial streams
E_num 2 2_ext_sp_str Not supported: 2 extension
spatial streams
<legal 0>
crc
The CRC protects the HT-SIG (HT-SIG[0][23:0] and
HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 +
D + 1. <legal all>
signal_tail
The 6 bits of tail is always set to 0 is used to flush
the BCC encoder and decoder. <legal 0>
reserved_1
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY. <legal 0>
*/
/* Description HT_SIG_INFO_0_MCS
Modulation Coding Scheme:
0-7 are used for single stream
8-15 are used for 2 streams
16-23 are used for 3 streams
24-31 are used for 4 streams
32 is used for duplicate HT20 (unsupported)
33-76 is used for unequal modulation (unsupported)
77-127 is reserved.
<legal 0-31>
*/
#define HT_SIG_INFO_0_MCS_OFFSET 0x00000000
#define HT_SIG_INFO_0_MCS_LSB 0
#define HT_SIG_INFO_0_MCS_MASK 0x0000007f
/* Description HT_SIG_INFO_0_CBW
Packet bandwidth:
<enum 0 ht_20_mhz>
<enum 1 ht_40_mhz>
<legal 0-1>
*/
#define HT_SIG_INFO_0_CBW_OFFSET 0x00000000
#define HT_SIG_INFO_0_CBW_LSB 7
#define HT_SIG_INFO_0_CBW_MASK 0x00000080
/* Description HT_SIG_INFO_0_LENGTH
This is the MPDU or A-MPDU length in octets of the PPDU
<legal all>
*/
#define HT_SIG_INFO_0_LENGTH_OFFSET 0x00000000
#define HT_SIG_INFO_0_LENGTH_LSB 8
#define HT_SIG_INFO_0_LENGTH_MASK 0x00ffff00
/* Description HT_SIG_INFO_0_RESERVED_0
This field is not part of HT-SIG
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
*/
#define HT_SIG_INFO_0_RESERVED_0_OFFSET 0x00000000
#define HT_SIG_INFO_0_RESERVED_0_LSB 24
#define HT_SIG_INFO_0_RESERVED_0_MASK 0xff000000
/* Description HT_SIG_INFO_1_SMOOTHING
Field indicates if smoothing is needed
E_num 0 do_smoothing Unsupported setting: indicates
smoothing is often used for beamforming
<legal 1>
*/
#define HT_SIG_INFO_1_SMOOTHING_OFFSET 0x00000004
#define HT_SIG_INFO_1_SMOOTHING_LSB 0
#define HT_SIG_INFO_1_SMOOTHING_MASK 0x00000001
/* Description HT_SIG_INFO_1_NOT_SOUNDING
E_num 0 sounding Unsupported setting: indicates
sounding is used
<enum 1 no_sounding> Indicates no sounding is used
<legal 1>
*/
#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET 0x00000004
#define HT_SIG_INFO_1_NOT_SOUNDING_LSB 1
#define HT_SIG_INFO_1_NOT_SOUNDING_MASK 0x00000002
/* Description HT_SIG_INFO_1_HT_RESERVED
Reserved: Should be set to 1 by the MAC and ignored by
the PHY
<legal 1>
*/
#define HT_SIG_INFO_1_HT_RESERVED_OFFSET 0x00000004
#define HT_SIG_INFO_1_HT_RESERVED_LSB 2
#define HT_SIG_INFO_1_HT_RESERVED_MASK 0x00000004
/* Description HT_SIG_INFO_1_AGGREGATION
<enum 0 mpdu> Indicates MPDU format
<enum 1 a_mpdu> Indicates A-MPDU format
<legal 0-1>
*/
#define HT_SIG_INFO_1_AGGREGATION_OFFSET 0x00000004
#define HT_SIG_INFO_1_AGGREGATION_LSB 3
#define HT_SIG_INFO_1_AGGREGATION_MASK 0x00000008
/* Description HT_SIG_INFO_1_STBC
<enum 0 no_stbc> Indicates no STBC
<enum 1 1_str_stbc> Indicates 1 stream STBC
E_num 2 2_str_stbc Indicates 2 stream STBC
(Unsupported)
<legal 0-1>
*/
#define HT_SIG_INFO_1_STBC_OFFSET 0x00000004
#define HT_SIG_INFO_1_STBC_LSB 4
#define HT_SIG_INFO_1_STBC_MASK 0x00000030
/* Description HT_SIG_INFO_1_FEC_CODING
<enum 0 ht_bcc> Indicates BCC coding
<enum 1 ht_ldpc> Indicates LDPC coding
<legal 0-1>
*/
#define HT_SIG_INFO_1_FEC_CODING_OFFSET 0x00000004
#define HT_SIG_INFO_1_FEC_CODING_LSB 6
#define HT_SIG_INFO_1_FEC_CODING_MASK 0x00000040
/* Description HT_SIG_INFO_1_SHORT_GI
<enum 0 ht_normal_gi> Indicates normal guard
interval
<legal 0-1>
*/
#define HT_SIG_INFO_1_SHORT_GI_OFFSET 0x00000004
#define HT_SIG_INFO_1_SHORT_GI_LSB 7
#define HT_SIG_INFO_1_SHORT_GI_MASK 0x00000080
/* Description HT_SIG_INFO_1_NUM_EXT_SP_STR
Number of extension spatial streams: (Used for TxBF)
<enum 0 0_ext_sp_str> No extension spatial streams
E_num 1 1_ext_sp_str Not supported: 1 extension
spatial streams
E_num 2 2_ext_sp_str Not supported: 2 extension
spatial streams
<legal 0>
*/
#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET 0x00000004
#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB 8
#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK 0x00000300
/* Description HT_SIG_INFO_1_CRC
The CRC protects the HT-SIG (HT-SIG[0][23:0] and
HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 +
D + 1. <legal all>
*/
#define HT_SIG_INFO_1_CRC_OFFSET 0x00000004
#define HT_SIG_INFO_1_CRC_LSB 10
#define HT_SIG_INFO_1_CRC_MASK 0x0003fc00
/* Description HT_SIG_INFO_1_SIGNAL_TAIL
The 6 bits of tail is always set to 0 is used to flush
the BCC encoder and decoder. <legal 0>
*/
#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET 0x00000004
#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB 18
#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK 0x00fc0000
/* Description HT_SIG_INFO_1_RESERVED_1
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY. <legal 0>
*/
#define HT_SIG_INFO_1_RESERVED_1_OFFSET 0x00000004
#define HT_SIG_INFO_1_RESERVED_1_LSB 24
#define HT_SIG_INFO_1_RESERVED_1_MASK 0xff000000
#endif // _HT_SIG_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _L_SIG_A_INFO_H_
#define _L_SIG_A_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 rate[3:0], lsig_reserved[4], length[16:5], parity[17], tail[23:18], pkt_type[27:24], captured_implicit_sounding[28], reserved[31:29]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_L_SIG_A_INFO 1
struct l_sig_a_info {
uint32_t rate : 4, //[3:0]
lsig_reserved : 1, //[4]
length : 12, //[16:5]
parity : 1, //[17]
tail : 6, //[23:18]
pkt_type : 4, //[27:24]
captured_implicit_sounding : 1, //[28]
reserved : 3; //[31:29]
};
/*
rate
This format is originally defined for OFDM as a 4 bit
field but the 5th bit was added to indicate 11b formatted
frames. In the standard bit [4] is specified as reserved.
For 11b frames this L-SIG is transformed in the PHY into the
11b preamble format. The following are the rates:
<enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
<enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
<enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
<enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
<enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
<enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
<enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
<enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
<legal 8-15>
lsig_reserved
Reserved: Should be set to 0 by the MAC and ignored by
the PHY
<legal 0>
length
The length indicates the number of octets in this MPDU.
Note that when using mixed mode 11n preamble this length
provides the spoofed length for the PPDU. This length
provides part of the information to derive the actually PPDU
length. For legacy OFDM and 11B frames the maximum length
is
<legal all>
parity
11a/n/ac TX: This field provides even parity over the
first 18 bits of the signal field which means that the sum
of 1s in the signal field will always be even on
11a/n/ac RX: this field contains the received parity
field from the L-SIG symbol for the current packet.
<legal 0-1>
tail
The 6 bits of tail is always set to 0 is used to flush
the BCC encoder and decoder. <legal 0>
pkt_type
Only used on the RX side.
Note: This is not really part of L-SIG
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
captured_implicit_sounding
Only used on the RX side.
Note: This is not really part of L-SIG
This indicates that the PHY has captured implicit
sounding.
reserved
Reserved: Should be set to 0 by the transmitting MAC and
ignored by the PHY <legal 0>
*/
/* Description L_SIG_A_INFO_0_RATE
This format is originally defined for OFDM as a 4 bit
field but the 5th bit was added to indicate 11b formatted
frames. In the standard bit [4] is specified as reserved.
For 11b frames this L-SIG is transformed in the PHY into the
11b preamble format. The following are the rates:
<enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
<enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
<enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
<enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
<enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
<enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
<enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
<enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
<legal 8-15>
*/
#define L_SIG_A_INFO_0_RATE_OFFSET 0x00000000
#define L_SIG_A_INFO_0_RATE_LSB 0
#define L_SIG_A_INFO_0_RATE_MASK 0x0000000f
/* Description L_SIG_A_INFO_0_LSIG_RESERVED
Reserved: Should be set to 0 by the MAC and ignored by
the PHY
<legal 0>
*/
#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB 4
#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK 0x00000010
/* Description L_SIG_A_INFO_0_LENGTH
The length indicates the number of octets in this MPDU.
Note that when using mixed mode 11n preamble this length
provides the spoofed length for the PPDU. This length
provides part of the information to derive the actually PPDU
length. For legacy OFDM and 11B frames the maximum length
is
<legal all>
*/
#define L_SIG_A_INFO_0_LENGTH_OFFSET 0x00000000
#define L_SIG_A_INFO_0_LENGTH_LSB 5
#define L_SIG_A_INFO_0_LENGTH_MASK 0x0001ffe0
/* Description L_SIG_A_INFO_0_PARITY
11a/n/ac TX: This field provides even parity over the
first 18 bits of the signal field which means that the sum
of 1s in the signal field will always be even on
11a/n/ac RX: this field contains the received parity
field from the L-SIG symbol for the current packet.
<legal 0-1>
*/
#define L_SIG_A_INFO_0_PARITY_OFFSET 0x00000000
#define L_SIG_A_INFO_0_PARITY_LSB 17
#define L_SIG_A_INFO_0_PARITY_MASK 0x00020000
/* Description L_SIG_A_INFO_0_TAIL
The 6 bits of tail is always set to 0 is used to flush
the BCC encoder and decoder. <legal 0>
*/
#define L_SIG_A_INFO_0_TAIL_OFFSET 0x00000000
#define L_SIG_A_INFO_0_TAIL_LSB 18
#define L_SIG_A_INFO_0_TAIL_MASK 0x00fc0000
/* Description L_SIG_A_INFO_0_PKT_TYPE
Only used on the RX side.
Note: This is not really part of L-SIG
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
*/
#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET 0x00000000
#define L_SIG_A_INFO_0_PKT_TYPE_LSB 24
#define L_SIG_A_INFO_0_PKT_TYPE_MASK 0x0f000000
/* Description L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING
Only used on the RX side.
Note: This is not really part of L-SIG
This indicates that the PHY has captured implicit
sounding.
*/
#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
/* Description L_SIG_A_INFO_0_RESERVED
Reserved: Should be set to 0 by the transmitting MAC and
ignored by the PHY <legal 0>
*/
#define L_SIG_A_INFO_0_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_0_RESERVED_LSB 29
#define L_SIG_A_INFO_0_RESERVED_MASK 0xe0000000
#endif // _L_SIG_A_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _L_SIG_B_INFO_H_
#define _L_SIG_B_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 rate[3:0], length[15:4], reserved[31:16]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_L_SIG_B_INFO 1
struct l_sig_b_info {
uint32_t rate : 4, //[3:0]
length : 12, //[15:4]
reserved : 16; //[31:16]
};
/*
rate
<enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
<enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
<enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
<enum 4 cck_11_mbps_long> CCK 11 Mbps long
<enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
<enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
<enum 7 cck_11_mbps_short> CCK 11 Mbps short
<legal 1-7>
length
The length indicates the number of octets in this MPDU.
<legal all>
reserved
Reserved: Should be set to 0 by the transmitting MAC and
ignored by the PHY <legal 0>
*/
/* Description L_SIG_B_INFO_0_RATE
<enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
<enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
<enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
<enum 4 cck_11_mbps_long> CCK 11 Mbps long
<enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
<enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
<enum 7 cck_11_mbps_short> CCK 11 Mbps short
<legal 1-7>
*/
#define L_SIG_B_INFO_0_RATE_OFFSET 0x00000000
#define L_SIG_B_INFO_0_RATE_LSB 0
#define L_SIG_B_INFO_0_RATE_MASK 0x0000000f
/* Description L_SIG_B_INFO_0_LENGTH
The length indicates the number of octets in this MPDU.
<legal all>
*/
#define L_SIG_B_INFO_0_LENGTH_OFFSET 0x00000000
#define L_SIG_B_INFO_0_LENGTH_LSB 4
#define L_SIG_B_INFO_0_LENGTH_MASK 0x0000fff0
/* Description L_SIG_B_INFO_0_RESERVED
Reserved: Should be set to 0 by the transmitting MAC and
ignored by the PHY <legal 0>
*/
#define L_SIG_B_INFO_0_RESERVED_OFFSET 0x00000000
#define L_SIG_B_INFO_0_RESERVED_LSB 16
#define L_SIG_B_INFO_0_RESERVED_MASK 0xffff0000
#endif // _L_SIG_B_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
// User Name:c_landav
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __MAC_TCL_REG_SEQ_BASE_H__
#define __MAC_TCL_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#endif

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACRX_ABORT_REQUEST_INFO_H_
#define _MACRX_ABORT_REQUEST_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 macrx_abort_reason[7:0], reserved_0[15:8]
//
// ################ END SUMMARY #################
#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
struct macrx_abort_request_info {
uint16_t macrx_abort_reason : 8, //[7:0]
reserved_0 : 8; //[15:8]
};
/*
macrx_abort_reason
<enum 0 macrx_abort_sw_initiated>
<enum 1 macrx_abort_obss_reception> Upon receiving this
abort reason, PHY should stop reception of the current frame
and go back into a search mode
<enum 2 macrx_abort_other>
<enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW
issued an abort for channel switch reasons
<enum 4 macrx_abort_sw_initiated_power_save > MAC FW
issued an abort power save reasons
<enum 5 macrx_abort_too_much_bad_data > RXPCU is
terminating the current ongoing reception, as the data that
MAC is receiving seems to be all garbage... The PER is too
high, or in case of MU UL, Likely the trigger frame never
got properly received by any of the targeted MU UL devices.
After the abort, PHYRX can resume a normal search mode.
<legal 0-5>
reserved_0
<legal 0>
*/
/* Description MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON
<enum 0 macrx_abort_sw_initiated>
<enum 1 macrx_abort_obss_reception> Upon receiving this
abort reason, PHY should stop reception of the current frame
and go back into a search mode
<enum 2 macrx_abort_other>
<enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW
issued an abort for channel switch reasons
<enum 4 macrx_abort_sw_initiated_power_save > MAC FW
issued an abort power save reasons
<enum 5 macrx_abort_too_much_bad_data > RXPCU is
terminating the current ongoing reception, as the data that
MAC is receiving seems to be all garbage... The PER is too
high, or in case of MU UL, Likely the trigger frame never
got properly received by any of the targeted MU UL devices.
After the abort, PHYRX can resume a normal search mode.
<legal 0-5>
*/
#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB 0
#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK 0x000000ff
/* Description MACRX_ABORT_REQUEST_INFO_0_RESERVED_0
<legal 0>
*/
#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 8
#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000ff00
#endif // _MACRX_ABORT_REQUEST_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
#define _PHYRX_ABORT_REQUEST_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 phyrx_abort_reason[7:0], phy_enters_nap_state[8], phy_enters_defer_state[9], reserved_0[15:10], receive_duration[31:16]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
struct phyrx_abort_request_info {
uint32_t phyrx_abort_reason : 8, //[7:0]
phy_enters_nap_state : 1, //[8]
phy_enters_defer_state : 1, //[9]
reserved_0 : 6, //[15:10]
receive_duration : 16; //[31:16]
};
/*
phyrx_abort_reason
<enum 0 phyrx_err_phy_off> Reception aborted due to
receiving a PHY_OFF TLV
<enum 1 phyrx_err_synth_off>
<enum 2 phyrx_err_ofdma_timing>
<enum 3 phyrx_err_ofdma_signal_parity>
<enum 4 phyrx_err_ofdma_rate_illegal>
<enum 5 phyrx_err_ofdma_length_illegal>
<enum 6 phyrx_err_ofdma_restart>
<enum 7 phyrx_err_ofdma_service>
<enum 8 phyrx_err_ppdu_ofdma_power_drop>
<enum 9 phyrx_err_cck_blokker>
<enum 10 phyrx_err_cck_timing>
<enum 11 phyrx_err_cck_header_crc>
<enum 12 phyrx_err_cck_rate_illegal>
<enum 13 phyrx_err_cck_length_illegal>
<enum 14 phyrx_err_cck_restart>
<enum 15 phyrx_err_cck_service>
<enum 16 phyrx_err_cck_power_drop>
<enum 17 phyrx_err_ht_crc_err>
<enum 18 phyrx_err_ht_length_illegal>
<enum 19 phyrx_err_ht_rate_illegal>
<enum 20 phyrx_err_ht_zlf>
<enum 21 phyrx_err_false_radar_ext>
<enum 22 phyrx_err_green_field>
<enum 23 phyrx_err_bw_gt_dyn_bw>
<enum 24 phyrx_err_leg_ht_mismatch>
<enum 25 phyrx_err_vht_crc_error>
<enum 26 phyrx_err_vht_siga_unsupported>
<enum 27 phyrx_err_vht_lsig_len_invalid>
<enum 28 phyrx_err_vht_ndp_or_zlf>
<enum 29 phyrx_err_vht_nsym_lt_zero>
<enum 30 phyrx_err_vht_rx_extra_symbol_mismatch>
<enum 31 phyrx_err_vht_rx_skip_group_id0>
<enum 32 phyrx_err_vht_rx_skip_group_id1to62>
<enum 33 phyrx_err_vht_rx_skip_group_id63>
<enum 34 phyrx_err_ofdm_ldpc_decoder_disabled>
<enum 35 phyrx_err_defer_nap>
<enum 36 phyrx_err_fdomain_timeout>
<enum 37 phyrx_err_lsig_rel_check>
<enum 38 phyrx_err_bt_collision>
<enum 39 phyrx_err_unsupported_mu_feedback>
<enum 40 phyrx_err_ppdu_tx_interrupt_rx>
<enum 41 phyrx_err_unsupported_cbf>
<enum 42 phyrx_err_other> Should not really be used. If
needed, ask for documentation update
<enum 43 phyrx_err_he_siga_unsupported > <enum 44
phyrx_err_he_crc_error > <enum 45
phyrx_err_he_sigb_unsupported > <enum 46
phyrx_err_he_mu_mode_unsupported > <enum 47
phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero
> <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50
phyrx_err_he_num_users_unsupported ><enum 51
phyrx_err_he_sounding_params_unsupported >
<enum 52 phyrx_err_MU_UL_no_power_detected>
<enum 53 phyrx_err_MU_UL_not_for_me>
<legal 0 - 53>
phy_enters_nap_state
When set, PHY enters PHY NAP state after sending this
abort
Note that nap and defer state are mutually exclusive.
Field put pro-actively in place....usage still to be
agreed upon.
<legal all>
phy_enters_defer_state
When set, PHY enters PHY defer state after sending this
abort
Note that nap and defer state are mutually exclusive.
Field put pro-actively in place....usage still to be
agreed upon.
<legal all>
reserved_0
<legal 0>
receive_duration
The remaining receive duration of this PPDU in the
medium (in us). When PHY does not know this duration when
this TLV is generated, the field will be set to 0.
The timing reference point is the reception by the MAC
of this TLV. The value shall be accurate to within 2us.
In case Phy_enters_nap_state and/or
Phy_enters_defer_state is set, there is a possibility that
MAC PMM can also decide to go into a low(er) power state.
<legal all>
*/
/* Description PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON
<enum 0 phyrx_err_phy_off> Reception aborted due to
receiving a PHY_OFF TLV
<enum 1 phyrx_err_synth_off>
<enum 2 phyrx_err_ofdma_timing>
<enum 3 phyrx_err_ofdma_signal_parity>
<enum 4 phyrx_err_ofdma_rate_illegal>
<enum 5 phyrx_err_ofdma_length_illegal>
<enum 6 phyrx_err_ofdma_restart>
<enum 7 phyrx_err_ofdma_service>
<enum 8 phyrx_err_ppdu_ofdma_power_drop>
<enum 9 phyrx_err_cck_blokker>
<enum 10 phyrx_err_cck_timing>
<enum 11 phyrx_err_cck_header_crc>
<enum 12 phyrx_err_cck_rate_illegal>
<enum 13 phyrx_err_cck_length_illegal>
<enum 14 phyrx_err_cck_restart>
<enum 15 phyrx_err_cck_service>
<enum 16 phyrx_err_cck_power_drop>
<enum 17 phyrx_err_ht_crc_err>
<enum 18 phyrx_err_ht_length_illegal>
<enum 19 phyrx_err_ht_rate_illegal>
<enum 20 phyrx_err_ht_zlf>
<enum 21 phyrx_err_false_radar_ext>
<enum 22 phyrx_err_green_field>
<enum 23 phyrx_err_bw_gt_dyn_bw>
<enum 24 phyrx_err_leg_ht_mismatch>
<enum 25 phyrx_err_vht_crc_error>
<enum 26 phyrx_err_vht_siga_unsupported>
<enum 27 phyrx_err_vht_lsig_len_invalid>
<enum 28 phyrx_err_vht_ndp_or_zlf>
<enum 29 phyrx_err_vht_nsym_lt_zero>
<enum 30 phyrx_err_vht_rx_extra_symbol_mismatch>
<enum 31 phyrx_err_vht_rx_skip_group_id0>
<enum 32 phyrx_err_vht_rx_skip_group_id1to62>
<enum 33 phyrx_err_vht_rx_skip_group_id63>
<enum 34 phyrx_err_ofdm_ldpc_decoder_disabled>
<enum 35 phyrx_err_defer_nap>
<enum 36 phyrx_err_fdomain_timeout>
<enum 37 phyrx_err_lsig_rel_check>
<enum 38 phyrx_err_bt_collision>
<enum 39 phyrx_err_unsupported_mu_feedback>
<enum 40 phyrx_err_ppdu_tx_interrupt_rx>
<enum 41 phyrx_err_unsupported_cbf>
<enum 42 phyrx_err_other> Should not really be used. If
needed, ask for documentation update
<enum 43 phyrx_err_he_siga_unsupported > <enum 44
phyrx_err_he_crc_error > <enum 45
phyrx_err_he_sigb_unsupported > <enum 46
phyrx_err_he_mu_mode_unsupported > <enum 47
phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero
> <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50
phyrx_err_he_num_users_unsupported ><enum 51
phyrx_err_he_sounding_params_unsupported >
<enum 52 phyrx_err_MU_UL_no_power_detected>
<enum 53 phyrx_err_MU_UL_not_for_me>
<legal 0 - 53>
*/
#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0
#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff
/* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE
When set, PHY enters PHY NAP state after sending this
abort
Note that nap and defer state are mutually exclusive.
Field put pro-actively in place....usage still to be
agreed upon.
<legal all>
*/
#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8
#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100
/* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE
When set, PHY enters PHY defer state after sending this
abort
Note that nap and defer state are mutually exclusive.
Field put pro-actively in place....usage still to be
agreed upon.
<legal all>
*/
#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9
#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
/* Description PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0
<legal 0>
*/
#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10
#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00
/* Description PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION
The remaining receive duration of this PPDU in the
medium (in us). When PHY does not know this duration when
this TLV is generated, the field will be set to 0.
The timing reference point is the reception by the MAC
of this TLV. The value shall be accurate to within 2us.
In case Phy_enters_nap_state and/or
Phy_enters_defer_state is set, there is a possibility that
MAC PMM can also decide to go into a low(er) power state.
<legal all>
*/
#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16
#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000
#endif // _PHYRX_ABORT_REQUEST_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
#define _PHYRX_HE_SIG_A_MU_DL_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_mu_dl_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
struct phyrx_he_sig_a_mu_dl {
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
};
/*
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details */
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG
Differentiates between DL and UL transmission
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
<enum 1 DL_UL_FLAG_IS_UL>
NOTE: This is unsupported for HE MU format (including
MU_SU) Tx in Napier and Hastings80.
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B
Indicates the MCS of HE-SIG-B
<legal 0-5>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B
Indicates whether dual sub-carrier modulation is applied
to HE-SIG-B
0: No DCM for HE_SIG_B
1: DCM for HE_SIG_B
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID
BSS color ID
Field Used by MAC HW
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE
Spatial reuse
For 20MHz one SR field corresponding to entire 20MHz
(other 3 fields indicate identical values)
For 40MHz two SR fields for each 20MHz (other 2 fields
indicate identical values)
For 80MHz four SR fields for each 20MHz
For 160MHz four SR fields for each 40MHz
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW
Bandwidth of the PPDU.
<enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
<enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
<enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble
puncturing mode
<enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz
non-preamble puncturing mode
<enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble
puncturing in 80 MHz, where in the preamble only the
secondary 20 MHz is punctured
<enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for
preamble puncturing in 80 MHz, where in the preamble only
one of the two 20 MHz sub-channels in secondary 40 MHz is
punctured.
<enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble
puncturing in 160 MHz or 80+80 MHz, where in the primary 80
MHz of the preamble only the secondary 20 MHz is punctured.
<enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for
preamble puncturing in 160 MHz or 80+80 MHz, where in the
primary 80 MHz of the preamble the primary 40 MHz is
present.
On RX side, Field Used by MAC HW
<legal 0-7>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS
Number of symbols
For OFDMA, the actual number of symbols is 1 larger then
indicated in this field.
For MU-MIMO this is equal to the number of users - 1:
the following encoding is used:
1 => 2 users
2 => 3 users
Etc.
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B
Indicates the compression mode of HE-SIG-B
0: Regular [uncomp mode]
1: compressed mode (full-BW MU-MIMO only)
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE
Indicates the CP and HE-LTF type
<enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
<enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
<enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
<enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION
0: No Doppler support
1: Doppler support
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A
<legal 0>
*/
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION
Indicates the remaining time in the current TXOP
Field Used by MAC HW
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A
Note: spec indicates this shall be set to 1
<legal 1>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS
Indicates the number of HE-LTF symbols
0: 1 LTF
1: 2 LTFs
2: 4 LTFs
3: 6 LTFs
4: 8 LTFs
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL
If LDPC,
0: LDPC extra symbol not present
1: LDPC extra symbol present
Else
Set to 1
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC
Indicates whether STBC is applied
0: No STBC
1: STBC
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR
the packet extension duration of the trigger-based PPDU
response with these two bits indicating the a-factor
<enum 0 a_factor_4>
<enum 1 a_factor_1>
<enum 2 a_factor_2>
<enum 3 a_factor_3>
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY
the packet extension duration of the trigger-based PPDU
response with this bit indicating the PE-Disambiguity
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC
CRC for HE-SIG-A contents.
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL
<legal 0>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B
<legal 0>
*/
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
#endif // _PHYRX_HE_SIG_A_MU_DL_H_

178
hw/qca5018/phyrx_he_sig_a_mu_ul.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
#define _PHYRX_HE_SIG_A_MU_UL_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_mu_ul_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
struct phyrx_he_sig_a_mu_ul {
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
};
/*
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details */
/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION
Indicates whether the transmission is SU PPDU or a
trigger based UL MU PDDU
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID
BSS color ID
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE
Spatial reuse
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A
Note: spec indicates this shall be set to 1
<legal 1>
*/
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW
Bandwidth of the PPDU.
<enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
<enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
<enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
<enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
On RX side, Field Used by MAC HW
<legal 0-3>
*/
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B
<legal 0>
*/
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION
Indicates the remaining time in the current TXOP <legal
all>
*/
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A
Set to value indicated in the trigger frame
<legal 255>
*/
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC
CRC for HE-SIG-A contents.
This CRC may also cover some fields of L-SIG (TBD)
<legal all>
*/
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL
BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
used
<legal 0>
*/
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B
<legal 0>
*/
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
#endif // _PHYRX_HE_SIG_A_MU_UL_H_

483
hw/qca5018/phyrx_he_sig_a_su.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_SU_H_
#define _PHYRX_HE_SIG_A_SU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_su_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
struct phyrx_he_sig_a_su {
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
};
/*
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct he_sig_a_su_info phyrx_he_sig_a_su_info_details */
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE
Indicates whether spatial mapping is changed between
legacy and HE portion of preamble. If not, channel
estimation can include legacy preamble to improve accuracy
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG
Differentiates between DL and UL transmission
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
<enum 1 DL_UL_FLAG_IS_UL>
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS
Indicates the data MCS
Field Used by MAC HW
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM
0: No DCM
1:DCM
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID
BSS color ID
Field Used by MAC HW
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A
Note: spec indicates this shall be set to 1
<legal 1>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE
Spatial reuse
For 20MHz one SR field corresponding to entire 20MHz
(other 3 fields indicate identical values)
For 40MHz two SR fields for each 20MHz (other 2 fields
indicate identical values)
For 80MHz four SR fields for each 20MHz
For 160MHz four SR fields for each 40MHz
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW
Bandwidth of the PPDU.
For HE SU PPDU
<enum 0 HE_SIG_A_BW20> 20 Mhz
<enum 1 HE_SIG_A_BW40> 40 Mhz
<enum 2 HE_SIG_A_BW80> 80 Mhz
<enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
For HE Extended Range SU PPDU
Set to 0 for 242-tone RU
Set to 1 for right 106-tone RU within the primary 20 MHz
On RX side, Field Used by MAC HW
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE
Indicates the CP and HE-LTF type
<enum 3 FourX_LTF_0_8CP_3_2CP>
When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
In this scenario, Neither DCM nor STBC is applied to HE data
field.
NOTE:
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
0 = 1xLTF + 0.4 usec
1 = 2xLTF + 0.4 usec
2~3 = Reserved
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS
For HE SU PPDU
For HE Extended Range PPDU
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B
<legal 0>
*/
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION
Indicates the remaining time in the current TXOP
Field Used by MAC HW
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING
Distinguishes between BCC and LDPC coding.
0: BCC
1: LDPC
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL
If LDPC,
0: LDPC extra symbol not present
1: LDPC extra symbol present
Else
Set to 1
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC
Indicates whether STBC is applied
0: No STBC
1: STBC
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF
Indicates whether beamforming is applied
0: No beamforming
1: beamforming
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR
Common trigger info
the packet extension duration of the trigger-based PPDU
response with these two bits indicating the a-factor
<enum 0 a_factor_4>
<enum 1 a_factor_1>
<enum 2 a_factor_2>
<enum 3 a_factor_3>
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY
Common trigger info
the packet extension duration of the trigger-based PPDU
response with this bit indicating the PE-Disambiguity
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A
Note: per standard, set to 1
<legal 1>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION
0: No Doppler support
1: Doppler support
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC
CRC for HE-SIG-A contents.
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL
<legal 0>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED
TX side:
Set to 0
RX side:
On RX side, evaluated by MAC HW. This is the only way
for MAC RX to know that this was an HE_SIG_A_SU received in
'extended' format
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE
TX side:
Set to 0
RX side:
Field only contains valid info when dot11ax_su_extended
is set.
On RX side, evaluated by MAC HW. This is the only way
for MAC RX to know what the number of based RUs was in this
extended range reception. It is used by the MAC to determine
the RU size for the response...
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000
/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP
TX side:
Set to 0
RX side:Valid on RX side only, and looked at by MAC HW
When set, PHY has received (expected) NDP frame
<legal all>
*/
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31
#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000
#endif // _PHYRX_HE_SIG_A_SU_H_

72
hw/qca5018/phyrx_he_sig_b1_mu.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B1_MU_H_
#define _PHYRX_HE_SIG_B1_MU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b1_mu_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1
struct phyrx_he_sig_b1_mu {
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
};
/*
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details */
/* Description PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION
RU allocation for the user(s) following this common
portion of the SIG
For details, refer to RU_TYPE description
<legal all>
*/
#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
/* Description PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0
<legal 0>
*/
#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00
#endif // _PHYRX_HE_SIG_B1_MU_H_

143
hw/qca5018/phyrx_he_sig_b2_mu.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B2_MU_H_
#define _PHYRX_HE_SIG_B2_MU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b2_mu_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1
struct phyrx_he_sig_b2_mu {
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
};
/*
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details */
/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID
Identifies the STA that is addressed. Details of STA ID
are TBD
*/
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG
Number of assigned spatial streams and their
corresponding index.
Total number of spatial streams assigned for the MU-MIMO
allocation is also signaled.
*/
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS
Indicates the data MCS
*/
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1
<legal 1>
*/
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING
Distinguishes between BCC/LDPC
0: BCC
1: LDPC
<legal all>
*/
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A
<legal 0>
*/
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000
/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS
MAC RX side usage only:
Needed by RXPCU. Provided by PHY so that RXPCU does not
need to have the RU number decoding logic.
Number of spatial streams for this user
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
*/
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29
#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000
#endif // _PHYRX_HE_SIG_B2_MU_H_

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hw/qca5018/phyrx_he_sig_b2_ofdma.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
#define _PHYRX_HE_SIG_B2_OFDMA_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b2_ofdma_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1
struct phyrx_he_sig_b2_ofdma {
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
};
/*
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details */
/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID
Identifies the STA that is addressed. Details of STA ID
are TBD
*/
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS
MAC RX side usage only:
Number of spatial streams for this user
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
*/
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF
Indicates whether beamforming is applied
0: No beamforming
1: beamforming
<legal all>
*/
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS
Indicates the data MCS
*/
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM
0: No DCM
1:DCM
<legal all>
*/
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING
Distinguishes between BCC/LDPC
0: BCC
1: LDPC
<legal all>
*/
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0
<legal 0>
*/
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000
#endif // _PHYRX_HE_SIG_B2_OFDMA_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HT_SIG_H_
#define _PHYRX_HT_SIG_H_
#if !defined(__ASSEMBLER__)
#endif
#include "ht_sig_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct ht_sig_info phyrx_ht_sig_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
struct phyrx_ht_sig {
struct ht_sig_info phyrx_ht_sig_info_details;
};
/*
struct ht_sig_info phyrx_ht_sig_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct ht_sig_info phyrx_ht_sig_info_details */
/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS
Modulation Coding Scheme:
0-7 are used for single stream
8-15 are used for 2 streams
16-23 are used for 3 streams
24-31 are used for 4 streams
32 is used for duplicate HT20 (unsupported)
33-76 is used for unequal modulation (unsupported)
77-127 is reserved.
<legal 0-31>
*/
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f
/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW
Packet bandwidth:
<enum 0 ht_20_mhz>
<enum 1 ht_40_mhz>
<legal 0-1>
*/
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080
/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH
This is the MPDU or A-MPDU length in octets of the PPDU
<legal all>
*/
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00
/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0
This field is not part of HT-SIG
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
*/
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING
Field indicates if smoothing is needed
E_num 0 do_smoothing Unsupported setting: indicates
smoothing is often used for beamforming
<legal 1>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING
E_num 0 sounding Unsupported setting: indicates
sounding is used
<enum 1 no_sounding> Indicates no sounding is used
<legal 1>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED
Reserved: Should be set to 1 by the MAC and ignored by
the PHY
<legal 1>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION
<enum 0 mpdu> Indicates MPDU format
<enum 1 a_mpdu> Indicates A-MPDU format
<legal 0-1>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC
<enum 0 no_stbc> Indicates no STBC
<enum 1 1_str_stbc> Indicates 1 stream STBC
E_num 2 2_str_stbc Indicates 2 stream STBC
(Unsupported)
<legal 0-1>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING
<enum 0 ht_bcc> Indicates BCC coding
<enum 1 ht_ldpc> Indicates LDPC coding
<legal 0-1>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI
<enum 0 ht_normal_gi> Indicates normal guard
interval
<legal 0-1>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR
Number of extension spatial streams: (Used for TxBF)
<enum 0 0_ext_sp_str> No extension spatial streams
E_num 1 1_ext_sp_str Not supported: 1 extension
spatial streams
E_num 2 2_ext_sp_str Not supported: 2 extension
spatial streams
<legal 0>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC
The CRC protects the HT-SIG (HT-SIG[0][23:0] and
HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 +
D + 1. <legal all>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL
The 6 bits of tail is always set to 0 is used to flush
the BCC encoder and decoder. <legal 0>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000
/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY. <legal 0>
*/
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24
#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0xff000000
#endif // _PHYRX_HT_SIG_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_L_SIG_A_H_
#define _PHYRX_L_SIG_A_H_
#if !defined(__ASSEMBLER__)
#endif
#include "l_sig_a_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct l_sig_a_info phyrx_l_sig_a_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1
struct phyrx_l_sig_a {
struct l_sig_a_info phyrx_l_sig_a_info_details;
};
/*
struct l_sig_a_info phyrx_l_sig_a_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct l_sig_a_info phyrx_l_sig_a_info_details */
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE
This format is originally defined for OFDM as a 4 bit
field but the 5th bit was added to indicate 11b formatted
frames. In the standard bit [4] is specified as reserved.
For 11b frames this L-SIG is transformed in the PHY into the
11b preamble format. The following are the rates:
<enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
<enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
<enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
<enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
<enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
<enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
<enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
<enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
<legal 8-15>
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED
Reserved: Should be set to 0 by the MAC and ignored by
the PHY
<legal 0>
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH
The length indicates the number of octets in this MPDU.
Note that when using mixed mode 11n preamble this length
provides the spoofed length for the PPDU. This length
provides part of the information to derive the actually PPDU
length. For legacy OFDM and 11B frames the maximum length
is
<legal all>
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY
11a/n/ac TX: This field provides even parity over the
first 18 bits of the signal field which means that the sum
of 1s in the signal field will always be even on
11a/n/ac RX: this field contains the received parity
field from the L-SIG symbol for the current packet.
<legal 0-1>
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL
The 6 bits of tail is always set to 0 is used to flush
the BCC encoder and decoder. <legal 0>
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE
Only used on the RX side.
Note: This is not really part of L-SIG
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING
Only used on the RX side.
Note: This is not really part of L-SIG
This indicates that the PHY has captured implicit
sounding.
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED
Reserved: Should be set to 0 by the transmitting MAC and
ignored by the PHY <legal 0>
*/
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0xe0000000
#endif // _PHYRX_L_SIG_A_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_L_SIG_B_H_
#define _PHYRX_L_SIG_B_H_
#if !defined(__ASSEMBLER__)
#endif
#include "l_sig_b_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct l_sig_b_info phyrx_l_sig_b_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1
struct phyrx_l_sig_b {
struct l_sig_b_info phyrx_l_sig_b_info_details;
};
/*
struct l_sig_b_info phyrx_l_sig_b_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct l_sig_b_info phyrx_l_sig_b_info_details */
/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE
<enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
<enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
<enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
<enum 4 cck_11_mbps_long> CCK 11 Mbps long
<enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
<enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
<enum 7 cck_11_mbps_short> CCK 11 Mbps short
<legal 1-7>
*/
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f
/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH
The length indicates the number of octets in this MPDU.
<legal all>
*/
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0
/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED
Reserved: Should be set to 0 by the transmitting MAC and
ignored by the PHY <legal 0>
*/
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0xffff0000
#endif // _PHYRX_L_SIG_B_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_VHT_SIG_A_H_
#define _PHYRX_VHT_SIG_A_H_
#if !defined(__ASSEMBLER__)
#endif
#include "vht_sig_a_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct vht_sig_a_info phyrx_vht_sig_a_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
struct phyrx_vht_sig_a {
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
};
/*
struct vht_sig_a_info phyrx_vht_sig_a_info_details
See detailed description of the STRUCT
*/
/* EXTERNAL REFERENCE : struct vht_sig_a_info phyrx_vht_sig_a_info_details */
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH
Packet bandwidth
<enum 0 20_MHZ_11AC>
<enum 1 40_MHZ_11AC>
<enum 2 80_MHZ_11AC>
<enum 3 160_MHZ_11AC>
<legal 0-3>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0
Reserved. Set to 1 by MAC, PHY should ignore
<legal 1>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC
Space time block coding:
<enum 0 stbc_disabled> Indicates STBC is disabled
<enum 1 stbc_enabled> Indicates STBC is enabled on
all streams
<legal 0-1>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID
In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
to an AP or to a mesh STA, the Group ID field is set to 0,
otherwise it is set to 63. In an NDP PPDU the Group ID is
set according to IEEE 802.11ac_D1.0 Section 9.30.6
(Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID
is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID).
<legal all>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS
For MU:
3 bits/user with maximum of 4 users (user u uses
vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
3)
Set to 0 for 0 space time streams
Set to 1 for 1 space time stream
Set to 2 for 2 space time streams
Set to 3 for 3 space time streams
Set to 4 for 4 space time streams (not supported in Wifi
3.0)
Values 5-7 are reserved
In this field, references to user u should be
interpreted as MU user u. As described in the previous
chapter in this document (see chapter on User number), the
MU user value for a given client is defined for each MU
group that the client participates in. The MU user number is
not related to the internal user number that is used within
the BFer.
For SU:
vht_sig_a[0][12:10]
Set to 0 for 1 space time stream
Set to 1 for 2 space time streams
Set to 2 for 3 space time streams
Set to 3 for 4 space time streams
Set to 4 for 5 space time streams
Set to 5 for 6 space time streams
Set to 6 for 7 space time streams
Set to 7 for 8 space time streams
vht_sig_a[0][21:13]
Partial AID:
Set to the value of the TXVECTOR parameter PARTIAL_AID.
Partial AID provides an abbreviated indication of the
intended recipient(s) of the frame (see IEEE802.11ac_D1.0
Section 9.17a (Partial AID in VHT PPDUs)).
<legal all>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED
E_num 0 txop_ps_allowed Not supported: If set to by
VHT AP if it allows non-AP VHT STAs in TXOP power save mode
to enter Doze state during a TXOP
<enum 1 no_txop_ps_allowed> Otherwise
<legal 1>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B
Reserved: Should be set to 1 by the MAC and ignored by
the PHY <legal 1>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
*/
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING
<enum 0 normal_gi> Indicates short guard interval
is not used in the data field
<enum 1 short_gi> Indicates short guard interval is
used in the data field
<enum 3 short_gi_ambiguity> Indicates short guard
interval is used in the data field and NSYM mod 10 = 9
NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3
(TXTIME and PSDU_LENGTH calculation).
<legal 0,1,3>
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING
For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For
an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
B2 indicates the coding used for user 0; set to 0 for BCC
and 1 for LDPC. If the MU[0] NSTS field is 0, then this
field is reserved and set to 1
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL
Set to 1 if the LDPC PPDU encoding process (if an SU
PPDU), or at least one LDPC user's PPDU encoding process (if
an MU PPDU), results in an extra OFDM symbol (or symbols) as
described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
(Encoding process for MU PPDUs). Set to 0 otherwise.
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS
For SU:
Set to 0 for BPSK 1/2
Set to 1 for QPSK 1/2
Set to 2 for QPSK 3/4
Set to 3 for 16-QAM 1/2
Set to 4 for 16-QAM 3/4
Set to 5 for 64-QAM 2/3
Set to 6 for 64-QAM 3/4
Set to 7 for 64-QAM 5/6
Set to 8 for 256-QAM 3/4
Set to 9 for 256-QAM 5/6
For MU:
If NSTS for user 1 is non-zero, then vht_sig_a[1][4]
indicates coding for user 1: set to 0 for BCC, 1 for LDPC.
If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
reserved and set to 1.
If NSTS for user 2 is non-zero, then vht_sig_a[1][5]
indicates coding for user 2: set to 0 for BCC, 1 for LDPC.
If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
reserved and set to 1.
If NSTS for user 3 is non-zero, then vht_sig_a[1][6]
indicates coding for user 3: set to 0 for BCC, 1 for LDPC.
If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
reserved and set to 1.
vht_sig_a[1][7] is reserved and set to 1
<legal 0-15>
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED
For SU:
Set to 1 if a Beamforming steering matrix is applied to
the waveform in an SU transmission as described in
IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping),
set to 0 otherwise.
For MU:
Reserved and set to 1
<legal 0-1>
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1
Reserved and set to 1. <legal 1>
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC
CRC calculated as in IEEE802.11ac_D1.0 Section
19.3.9.4.4 (CRC calculation for HTSIG) with C7 in
vht_sig_a[1][10], etc. <legal all>
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL
Used to terminate the trellis of the convolutional
decoder. Set to 0. <legal 0>
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
*/
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000
#endif // _PHYRX_VHT_SIG_A_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RECEIVE_USER_INFO_H_
#define _RECEIVE_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 phy_ppdu_id[15:0], user_rssi[23:16], pkt_type[27:24], stbc[28], reception_type[31:29]
// 1 rate_mcs[3:0], sgi[5:4], receive_bandwidth[7:6], mimo_ss_bitmap[15:8], ofdma_ru_allocation[23:16], ofdma_user_index[30:24], ofdma_content_channel[31]
// 2 ldpc[0], ru_width[7:1], reserved_2a[31:8]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3
struct receive_user_info {
uint32_t phy_ppdu_id : 16, //[15:0]
user_rssi : 8, //[23:16]
pkt_type : 4, //[27:24]
stbc : 1, //[28]
reception_type : 3; //[31:29]
uint32_t rate_mcs : 4, //[3:0]
sgi : 2, //[5:4]
receive_bandwidth : 2, //[7:6]
mimo_ss_bitmap : 8, //[15:8]
ofdma_ru_allocation : 8, //[23:16]
ofdma_user_index : 7, //[30:24]
ofdma_content_channel : 1; //[31]
uint32_t ldpc : 1, //[0]
ru_width : 7, //[7:1]
reserved_2a : 24; //[31:8]
};
/*
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
user_rssi
RSSI for this user
Frequency domain RSSI measurement for this user. Based
on the channel estimate.
<legal all>
pkt_type
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
stbc
When set, use STBC transmission rates
reception_type
Indicates what type of reception this is.
<enum 0 reception_type_SU > Basic SU reception (not
part of OFDMA or MU-MIMO)
<enum 1 reception_type_MU_MIMO > This is related to
DL type of reception
<enum 2 reception_type_MU_OFDMA > This is related
to DL type of reception
<enum 3 reception_type_MU_OFDMA_MIMO > This is
related to DL type of reception
<enum 4 reception_type_UL_MU_MIMO > This is related
to UL type of reception
<enum 5 reception_type_UL_MU_OFDMA > This is
related to UL type of reception
<enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
related to UL type of reception
<legal 0-6>
rate_mcs
For details, refer to MCS_TYPE description
<legal all>
sgi
Field only valid when pkt type is HT, VHT or HE.
<enum 0 gi_0_8_us > Legacy normal GI. Can also be
used for HE
<enum 1 gi_0_4_us > Legacy short GI. Can also be
used for HE
<enum 2 gi_1_6_us > HE related GI
<enum 3 gi_3_2_us > HE related GI
<legal 0 - 3>
receive_bandwidth
Full receive Bandwidth
<enum 0 full_rx_bw_20_mhz>
<enum 1 full_rx_bw_40_mhz>
<enum 2 full_rx_bw_80_mhz>
<enum 3 full_rx_bw_160_mhz>
<legal 0-3>
mimo_ss_bitmap
Bitmap, with each bit indicating if the related spatial
stream is used for this STA
LSB related to SS 0
0: spatial stream not used for this reception
1: spatial stream used for this reception
<legal all>
ofdma_ru_allocation
Field only valid in case of OFDMA type receptions (DL
and UL)
Indicates the RU number associated with this user.
In case of reception where the transmission was DL MU
OFDMA, this field provides the RU pattern. Note that fields
ofdma_user_index and ofdma_content_channel are needed to
determine which RU (within a 40 MHz channel) was actually
assigned to this user, but this does not give info on which
40 MHz channel was assigned to this user. Please refer
DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for
this user.
In case of reception where the transmission was UL MU
OFDMA, PHY is recommended to insert the RU start index in
this field. Note that PHY may insert the RU width in
Reserved_2a[6:0].
<legal all>
ofdma_user_index
Field only valid in the of DL MU OFDMA reception
The user number within the RU_allocation.
This is needed for SW to determine the exact RU position
within the reception.
<legal all>
ofdma_content_channel
Field only valid in the of DL MU OFDMA/MIMO reception
In case of DL MU reception, this field indicates the
content channel number where PHY found the RU information
for this user
This is needed for SW to determine the exact RU position
within the reception.
<enum 0 content_channel_1>
<enum 1 content_channel_2>
<legal all>
ldpc
When set, use LDPC transmission rates were used.
<legal all>
ru_width
In case of UL OFDMA reception, PHY is recommended to
insert the RU width
In Hastings80: was using Reserved_2a[6:0].
<legal 1 - 74>
reserved_2a
<legal 0>
*/
/* Description RECEIVE_USER_INFO_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0
#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff
/* Description RECEIVE_USER_INFO_0_USER_RSSI
RSSI for this user
Frequency domain RSSI measurement for this user. Based
on the channel estimate.
<legal all>
*/
#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16
#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000
/* Description RECEIVE_USER_INFO_0_PKT_TYPE
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
*/
#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24
#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000
/* Description RECEIVE_USER_INFO_0_STBC
When set, use STBC transmission rates
*/
#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_STBC_LSB 28
#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000
/* Description RECEIVE_USER_INFO_0_RECEPTION_TYPE
Indicates what type of reception this is.
<enum 0 reception_type_SU > Basic SU reception (not
part of OFDMA or MU-MIMO)
<enum 1 reception_type_MU_MIMO > This is related to
DL type of reception
<enum 2 reception_type_MU_OFDMA > This is related
to DL type of reception
<enum 3 reception_type_MU_OFDMA_MIMO > This is
related to DL type of reception
<enum 4 reception_type_UL_MU_MIMO > This is related
to UL type of reception
<enum 5 reception_type_UL_MU_OFDMA > This is
related to UL type of reception
<enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
related to UL type of reception
<legal 0-6>
*/
#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB 29
#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK 0xe0000000
/* Description RECEIVE_USER_INFO_1_RATE_MCS
For details, refer to MCS_TYPE description
<legal all>
*/
#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0
#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f
/* Description RECEIVE_USER_INFO_1_SGI
Field only valid when pkt type is HT, VHT or HE.
<enum 0 gi_0_8_us > Legacy normal GI. Can also be
used for HE
<enum 1 gi_0_4_us > Legacy short GI. Can also be
used for HE
<enum 2 gi_1_6_us > HE related GI
<enum 3 gi_3_2_us > HE related GI
<legal 0 - 3>
*/
#define RECEIVE_USER_INFO_1_SGI_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_SGI_LSB 4
#define RECEIVE_USER_INFO_1_SGI_MASK 0x00000030
/* Description RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH
Full receive Bandwidth
<enum 0 full_rx_bw_20_mhz>
<enum 1 full_rx_bw_40_mhz>
<enum 2 full_rx_bw_80_mhz>
<enum 3 full_rx_bw_160_mhz>
<legal 0-3>
*/
#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6
#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0
/* Description RECEIVE_USER_INFO_1_MIMO_SS_BITMAP
Bitmap, with each bit indicating if the related spatial
stream is used for this STA
LSB related to SS 0
0: spatial stream not used for this reception
1: spatial stream used for this reception
<legal all>
*/
#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8
#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00
/* Description RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION
Field only valid in case of OFDMA type receptions (DL
and UL)
Indicates the RU number associated with this user.
In case of reception where the transmission was DL MU
OFDMA, this field provides the RU pattern. Note that fields
ofdma_user_index and ofdma_content_channel are needed to
determine which RU (within a 40 MHz channel) was actually
assigned to this user, but this does not give info on which
40 MHz channel was assigned to this user. Please refer
DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for
this user.
In case of reception where the transmission was UL MU
OFDMA, PHY is recommended to insert the RU start index in
this field. Note that PHY may insert the RU width in
Reserved_2a[6:0].
<legal all>
*/
#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB 16
#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
/* Description RECEIVE_USER_INFO_1_OFDMA_USER_INDEX
Field only valid in the of DL MU OFDMA reception
The user number within the RU_allocation.
This is needed for SW to determine the exact RU position
within the reception.
<legal all>
*/
#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB 24
#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK 0x7f000000
/* Description RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL
Field only valid in the of DL MU OFDMA/MIMO reception
In case of DL MU reception, this field indicates the
content channel number where PHY found the RU information
for this user
This is needed for SW to determine the exact RU position
within the reception.
<enum 0 content_channel_1>
<enum 1 content_channel_2>
<legal all>
*/
#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB 31
#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
/* Description RECEIVE_USER_INFO_2_LDPC
When set, use LDPC transmission rates were used.
<legal all>
*/
#define RECEIVE_USER_INFO_2_LDPC_OFFSET 0x00000008
#define RECEIVE_USER_INFO_2_LDPC_LSB 0
#define RECEIVE_USER_INFO_2_LDPC_MASK 0x00000001
/* Description RECEIVE_USER_INFO_2_RU_WIDTH
In case of UL OFDMA reception, PHY is recommended to
insert the RU width
In Hastings80: was using Reserved_2a[6:0].
<legal 1 - 74>
*/
#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET 0x00000008
#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB 1
#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK 0x000000fe
/* Description RECEIVE_USER_INFO_2_RESERVED_2A
<legal 0>
*/
#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET 0x00000008
#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB 8
#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK 0xffffff00
#endif // _RECEIVE_USER_INFO_H_

657
hw/qca5018/reo_descriptor_threshold_reached_status.h Normal file
View File

@ -0,0 +1,657 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 threshold_index[1:0], reserved_2[31:2]
// 3 link_descriptor_counter0[23:0], reserved_3[31:24]
// 4 link_descriptor_counter1[23:0], reserved_4[31:24]
// 5 link_descriptor_counter2[23:0], reserved_5[31:24]
// 6 link_descriptor_counter_sum[25:0], reserved_6[31:26]
// 7 reserved_7[31:0]
// 8 reserved_8[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
struct reo_descriptor_threshold_reached_status {
struct uniform_reo_status_header status_header;
uint32_t threshold_index : 2, //[1:0]
reserved_2 : 30; //[31:2]
uint32_t link_descriptor_counter0 : 24, //[23:0]
reserved_3 : 8; //[31:24]
uint32_t link_descriptor_counter1 : 24, //[23:0]
reserved_4 : 8; //[31:24]
uint32_t link_descriptor_counter2 : 24, //[23:0]
reserved_5 : 8; //[31:24]
uint32_t link_descriptor_counter_sum : 26, //[25:0]
reserved_6 : 6; //[31:26]
uint32_t reserved_7 : 32; //[31:0]
uint32_t reserved_8 : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
threshold_index
The index of the threshold register whose value got
reached
<enum 0 reo_desc_counter0_threshold>
<enum 1 reo_desc_counter1_threshold>
<enum 2 reo_desc_counter2_threshold>
<enum 3 reo_desc_counter_sum_threshold>
<legal all>
reserved_2
<legal 0>
link_descriptor_counter0
Value of this counter at generation of this message
<legal all>
reserved_3
<legal 0>
link_descriptor_counter1
Value of this counter at generation of this message
<legal all>
reserved_4
<legal 0>
link_descriptor_counter2
Value of this counter at generation of this message
<legal all>
reserved_5
<legal 0>
link_descriptor_counter_sum
Value of this counter at generation of this message
<legal all>
reserved_6
<legal 0>
reserved_7
<legal 0>
reserved_8
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX
The index of the threshold register whose value got
reached
<enum 0 reo_desc_counter0_threshold>
<enum 1 reo_desc_counter1_threshold>
<enum 2 reo_desc_counter2_threshold>
<enum 3 reo_desc_counter_sum_threshold>
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_

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hw/qca5018/reo_destination_ring.h Normal file
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1547
hw/qca5018/reo_entrance_ring.h Normal file
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533
hw/qca5018/reo_flush_cache.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_CACHE_H_
#define _REO_FLUSH_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 flush_addr_31_0[31:0]
// 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
struct reo_flush_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_addr_31_0 : 32; //[31:0]
uint32_t flush_addr_39_32 : 8, //[7:0]
forward_all_mpdus_in_queue : 1, //[8]
release_cache_block_index : 1, //[9]
cache_block_resource_index : 2, //[11:10]
flush_without_invalidate : 1, //[12]
block_cache_usage_after_flush : 1, //[13]
flush_entire_cache : 1, //[14]
reserved_2b : 17; //[31:15]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
flush_addr_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
flush_addr_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
forward_all_mpdus_in_queue
Is only allowed to be set when the flush address
corresponds with a REO descriptor.
When set, REO shall first forward all the MPDUs held in
the indicated re-order queue, before flushing the descriptor
from the cache.
<legal all>
release_cache_block_index
Field not valid when Flush_entire_cache is set.
If SW has previously used a blocking resource that it
now wants to re-use for this command, this bit shall be set.
It prevents SW from having to send a separate
REO_UNBLOCK_CACHE command.
When set, HW will first release the blocking resource
(indicated in field 'Cache_block_resouce_index') before this
command gets executed.
If that resource was already unblocked, this will be
considered an error. This command will not be executed, and
an error shall be returned.
<legal all>
cache_block_resource_index
Field not valid when Flush_entire_cache is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this
(descriptor) address
<legal all>
flush_without_invalidate
Field not valid when Flush_entire_cache is set.
When set, REO shall flush the cache line contents from
the cache, but there is NO need to invalidate the cache line
entry... The contents in the cache can be maintained. This
feature can be used by SW (and DV) to get a current snapshot
of the contents in the cache
<legal all>
block_cache_usage_after_flush
Field not valid when Flush_entire_cache is set.
When set, REO shall block any cache accesses to this
address till explicitly unblocked.
Whenever SW sets this bit, SW shall also set bit
'Forward_all_mpdus_in_queue' to ensure all packets are
flushed out in order to make sure this queue desc is not in
one of the aging link lists. In case SW does not want to
flush the MPDUs in the queue, see the recipe description
below this TLV definition.
The 'blocking' index to be used for this is indicated in
field 'cache_block_resource_index'. If SW had previously
used this blocking resource and was not freed up yet, SW
shall first unblock that index (by setting bit
Release_cache_block_index) or use an unblock command.
If the resource indicated here was already blocked (and
did not get unblocked in this command), it is considered an
error scenario...
No flush shall happen. The status for this command shall
indicate error.
<legal all>
flush_entire_cache
When set, the entire cache shall be flushed. The entire
cache will also remain blocked, till the
'REO_UNBLOCK_COMMAND' is received with bit unblock type set
to unblock_cache. All other fields in this command are to be
ignored.
Note that flushing the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
reserved_2b
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
/* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
*/
#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
/* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
*/
#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
/* Description REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
/* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff
/* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
Is only allowed to be set when the flush address
corresponds with a REO descriptor.
When set, REO shall first forward all the MPDUs held in
the indicated re-order queue, before flushing the descriptor
from the cache.
<legal all>
*/
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100
/* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
Field not valid when Flush_entire_cache is set.
If SW has previously used a blocking resource that it
now wants to re-use for this command, this bit shall be set.
It prevents SW from having to send a separate
REO_UNBLOCK_CACHE command.
When set, HW will first release the blocking resource
(indicated in field 'Cache_block_resouce_index') before this
command gets executed.
If that resource was already unblocked, this will be
considered an error. This command will not be executed, and
an error shall be returned.
<legal all>
*/
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200
/* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
Field not valid when Flush_entire_cache is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this
(descriptor) address
<legal all>
*/
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00
/* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
Field not valid when Flush_entire_cache is set.
When set, REO shall flush the cache line contents from
the cache, but there is NO need to invalidate the cache line
entry... The contents in the cache can be maintained. This
feature can be used by SW (and DV) to get a current snapshot
of the contents in the cache
<legal all>
*/
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000
/* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
Field not valid when Flush_entire_cache is set.
When set, REO shall block any cache accesses to this
address till explicitly unblocked.
Whenever SW sets this bit, SW shall also set bit
'Forward_all_mpdus_in_queue' to ensure all packets are
flushed out in order to make sure this queue desc is not in
one of the aging link lists. In case SW does not want to
flush the MPDUs in the queue, see the recipe description
below this TLV definition.
The 'blocking' index to be used for this is indicated in
field 'cache_block_resource_index'. If SW had previously
used this blocking resource and was not freed up yet, SW
shall first unblock that index (by setting bit
Release_cache_block_index) or use an unblock command.
If the resource indicated here was already blocked (and
did not get unblocked in this command), it is considered an
error scenario...
No flush shall happen. The status for this command shall
indicate error.
<legal all>
*/
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000
/* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
When set, the entire cache shall be flushed. The entire
cache will also remain blocked, till the
'REO_UNBLOCK_COMMAND' is received with bit unblock type set
to unblock_cache. All other fields in this command are to be
ignored.
Note that flushing the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
*/
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000
/* Description REO_FLUSH_CACHE_2_RESERVED_2B
<legal 0>
*/
#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15
#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000
/* Description REO_FLUSH_CACHE_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0
#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0
#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0
#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_FLUSH_CACHE_H_

796
hw/qca5018/reo_flush_cache_status.h Normal file
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@ -0,0 +1,796 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_CACHE_STATUS_H_
#define _REO_FLUSH_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], block_error_details[2:1], reserved_2a[7:3], cache_controller_flush_status_hit[8], cache_controller_flush_status_desc_type[11:9], cache_controller_flush_status_client_id[15:12], cache_controller_flush_status_error[17:16], cache_controller_flush_count[25:18], reserved_2b[31:26]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
struct reo_flush_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
block_error_details : 2, //[2:1]
reserved_2a : 5, //[7:3]
cache_controller_flush_status_hit: 1, //[8]
cache_controller_flush_status_desc_type: 3, //[11:9]
cache_controller_flush_status_client_id: 4, //[15:12]
cache_controller_flush_status_error: 2, //[17:16]
cache_controller_flush_count : 8, //[25:18]
reserved_2b : 6; //[31:26]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
Status for blocking resource handling
0: No error has been detected while executing this
command
1: an error in the blocking resource management was
detected
See field 'Block_error_details'
block_error_details
Field only valid when 'Error_detected' is set.
0: no blocking related error found
1: blocking resource was already in use
2: resource that was asked to be unblocked, was not
blocked
<legal 0-2>
reserved_2a
<legal 0>
cache_controller_flush_status_hit
The status that the cache controller returned for
executing the flush command
descriptor hit
1 = hit
0 = miss
<legal all>
cache_controller_flush_status_desc_type
The status that the cache controller returned for
executing the flush command
Descriptor type
FLOW_QUEUE_DESCRIPTOR                
3'd0
<legal all>
cache_controller_flush_status_client_id
The status that the cache controller returned for
executing the flush command
client ID
Module who made flush the request
In REO, this is always set to 0
<legal 0>
cache_controller_flush_status_error
The status that the cache controller returned for
executing the flush command
Error condition
2'b00: No error found
2'b01: HW IF still busy
2'b10: Line is currently locked. Used for the one line
flush command.
2'b11: At least one line is currently still locked. Used
for the cache flush command.
<legal all>
cache_controller_flush_count
The number of lines that were actually flushed out.
<legal all>
reserved_2b
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
/* Description REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED
Status for blocking resource handling
0: No error has been detected while executing this
command
1: an error in the blocking resource management was
detected
See field 'Block_error_details'
*/
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS
Field only valid when 'Error_detected' is set.
0: no blocking related error found
1: blocking resource was already in use
2: resource that was asked to be unblocked, was not
blocked
<legal 0-2>
*/
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006
/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT
The status that the cache controller returned for
executing the flush command
descriptor hit
1 = hit
0 = miss
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE
The status that the cache controller returned for
executing the flush command
Descriptor type
FLOW_QUEUE_DESCRIPTOR                
3'd0
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID
The status that the cache controller returned for
executing the flush command
client ID
Module who made flush the request
In REO, this is always set to 0
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR
The status that the cache controller returned for
executing the flush command
Error condition
2'b00: No error found
2'b01: HW IF still busy
2'b10: Line is currently locked. Used for the one line
flush command.
2'b11: At least one line is currently still locked. Used
for the cache flush command.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT
The number of lines that were actually flushed out.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000
/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2B
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000
/* Description REO_FLUSH_CACHE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_FLUSH_CACHE_STATUS_H_

350
hw/qca5018/reo_flush_queue.h Normal file
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@ -0,0 +1,350 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_QUEUE_H_
#define _REO_FLUSH_QUEUE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 flush_desc_addr_31_0[31:0]
// 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], invalidate_queue_and_flush[11], reserved_2a[31:12]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
struct reo_flush_queue {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_desc_addr_31_0 : 32; //[31:0]
uint32_t flush_desc_addr_39_32 : 8, //[7:0]
block_desc_addr_usage_after_flush: 1, //[8]
block_resource_index : 2, //[10:9]
invalidate_queue_and_flush : 1, //[11]
reserved_2a : 20; //[31:12]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
flush_desc_addr_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
flush_desc_addr_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
block_desc_addr_usage_after_flush
When set, REO shall not re-fetch this address till SW
explicitly unblocked this address
If the blocking resource was already used, this command
shall fail and an error is reported
<legal all>
block_resource_index
Field only valid when 'Block_desc_addr_usage_after_flush
' is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this address.
<legal all>
invalidate_queue_and_flush
When set, after the queue has been completely flushed,
invalidate the queue by clearing VLD and flush the queue
descriptor from the cache.
<legal all>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
*/
#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
*/
#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
/* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
When set, REO shall not re-fetch this address till SW
explicitly unblocked this address
If the blocking resource was already used, this command
shall fail and an error is reported
<legal all>
*/
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100
/* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
Field only valid when 'Block_desc_addr_usage_after_flush
' is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this address.
<legal all>
*/
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600
/* Description REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH
When set, after the queue has been completely flushed,
invalidate the queue by clearing VLD and flush the queue
descriptor from the cache.
<legal all>
*/
#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11
#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800
/* Description REO_FLUSH_QUEUE_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12
#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000
/* Description REO_FLUSH_QUEUE_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0
#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0
#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0
#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_FLUSH_QUEUE_H_

571
hw/qca5018/reo_flush_queue_status.h Normal file
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@ -0,0 +1,571 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_QUEUE_STATUS_H_
#define _REO_FLUSH_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], reserved_2a[31:1]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
struct reo_flush_queue_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
reserved_2a : 31; //[31:1]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
Status of the blocking resource
0: No error has been detected while executing this
command
1: Error detected: The resource to be used for blocking
was already in use.
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
/* Description REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED
Status of the blocking resource
0: No error has been detected while executing this
command
1: Error detected: The resource to be used for blocking
was already in use.
*/
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe
/* Description REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_FLUSH_QUEUE_STATUS_H_

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hw/qca5018/reo_flush_timeout_list.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
#define _REO_FLUSH_TIMEOUT_LIST_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 ac_timout_list[1:0], reserved_1[31:2]
// 2 minimum_release_desc_count[15:0], minimum_forward_buf_count[31:16]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
struct reo_flush_timeout_list {
struct uniform_reo_cmd_header cmd_header;
uint32_t ac_timout_list : 2, //[1:0]
reserved_1 : 30; //[31:2]
uint32_t minimum_release_desc_count : 16, //[15:0]
minimum_forward_buf_count : 16; //[31:16]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
ac_timout_list
Consumer: REO
Producer: SW
The AC_timeout list to be used for this command
<legal all>
reserved_1
<legal 0>
minimum_release_desc_count
Consumer: REO
Producer: SW
The minimum number of link descriptors requested to be
released. If set to 0, only buffer release counts seems to
be important... When set to very high value, likely the
entire timeout list will be exhausted before this count is
reached or maybe this count will not get reached. REO
however will stop here as it can not do anything else.
When both this field and field Minimum_forward_buf_count
are > 0, REO needs to meet both requirements. When both
entries are 0 (which should be a programming error), REO
does not need to do anything.
Note that this includes counts of MPDU link Desc as well
as MSDU link Desc. Where the count of MSDU link Desc is not
known to REO it's approximated by deriving from MSDU count
<legal all>
minimum_forward_buf_count
Consumer: REO
Producer: SW
The minimum number of buffer descriptors requested to be
passed on to the REO destination rings.
If set to 0, only descriptor release counts seems to be
important...
When set to very high value, likely the entire timeout
list will be exhausted before this count is reached or maybe
this count will not get reached. REO however will stop here
as it can not do anything else.
Note that REO does not know the exact buffer count. This
can be approximated by using the MSDU_COUNT
<legal all>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
/* Description REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST
Consumer: REO
Producer: SW
The AC_timeout list to be used for this command
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003
/* Description REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc
/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT
Consumer: REO
Producer: SW
The minimum number of link descriptors requested to be
released. If set to 0, only buffer release counts seems to
be important... When set to very high value, likely the
entire timeout list will be exhausted before this count is
reached or maybe this count will not get reached. REO
however will stop here as it can not do anything else.
When both this field and field Minimum_forward_buf_count
are > 0, REO needs to meet both requirements. When both
entries are 0 (which should be a programming error), REO
does not need to do anything.
Note that this includes counts of MPDU link Desc as well
as MSDU link Desc. Where the count of MSDU link Desc is not
known to REO it's approximated by deriving from MSDU count
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff
/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT
Consumer: REO
Producer: SW
The minimum number of buffer descriptors requested to be
passed on to the REO destination rings.
If set to 0, only descriptor release counts seems to be
important...
When set to very high value, likely the entire timeout
list will be exhausted before this count is reached or maybe
this count will not get reached. REO however will stop here
as it can not do anything else.
Note that REO does not know the exact buffer count. This
can be approximated by using the MSDU_COUNT
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000
/* Description REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_FLUSH_TIMEOUT_LIST_H_

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hw/qca5018/reo_flush_timeout_list_status.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], timout_list_empty[1], reserved_2a[31:2]
// 3 release_desc_count[15:0], forward_buf_count[31:16]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
struct reo_flush_timeout_list_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
timout_list_empty : 1, //[1]
reserved_2a : 30; //[31:2]
uint32_t release_desc_count : 16, //[15:0]
forward_buf_count : 16; //[31:16]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
0: No error has been detected while executing this
command
1: command not properly executed and returned with an
error
NOTE: Current no error is defined, but field is put in
place to avoid data structure changes in future...
timout_list_empty
When set, REO has depleted the timeout list and all
entries are gone.
<legal all>
reserved_2a
<legal 0>
release_desc_count
Consumer: REO
Producer: SW
The number of link descriptors released
<legal all>
forward_buf_count
Consumer: REO
Producer: SW
The number of buffers forwarded to the REO destination
rings
<legal all>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED
0: No error has been detected while executing this
command
1: command not properly executed and returned with an
error
NOTE: Current no error is defined, but field is put in
place to avoid data structure changes in future...
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY
When set, REO has depleted the timeout list and all
entries are gone.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT
Consumer: REO
Producer: SW
The number of link descriptors released
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT
Consumer: REO
Producer: SW
The number of buffers forwarded to the REO destination
rings
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_

348
hw/qca5018/reo_get_queue_stats.h Normal file
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@ -0,0 +1,348 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_GET_QUEUE_STATS_H_
#define _REO_GET_QUEUE_STATS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 rx_reo_queue_desc_addr_31_0[31:0]
// 2 rx_reo_queue_desc_addr_39_32[7:0], clear_stats[8], reserved_2a[31:9]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
struct reo_get_queue_stats {
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
clear_stats : 1, //[8]
reserved_2a : 23; //[31:9]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
rx_reo_queue_desc_addr_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the REO queue descriptor
<legal all>
rx_reo_queue_desc_addr_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the REO queue descriptor
<legal all>
clear_stats
Clear stat settings....
<enum 0 no_clear> Do NOT clear the stats after
generating the status
<enum 1 clear_the_stats> Clear the stats after
generating the status.
The stats actually cleared are:
Timeout_count
Forward_due_to_bar_count
Duplicate_count
Frames_in_order_count
BAR_received_count
MPDU_Frames_processed_count
MSDU_Frames_processed_count
Total_processed_byte_count
Late_receive_MPDU_count
window_jump_2k
Hole_count
<legal 0-1>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
*/
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
*/
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
/* Description REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the REO queue descriptor
<legal all>
*/
#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the REO queue descriptor
<legal all>
*/
#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_GET_QUEUE_STATS_2_CLEAR_STATS
Clear stat settings....
<enum 0 no_clear> Do NOT clear the stats after
generating the status
<enum 1 clear_the_stats> Clear the stats after
generating the status.
The stats actually cleared are:
Timeout_count
Forward_due_to_bar_count
Duplicate_count
Frames_in_order_count
BAR_received_count
MPDU_Frames_processed_count
MSDU_Frames_processed_count
Total_processed_byte_count
Late_receive_MPDU_count
window_jump_2k
Hole_count
<legal 0-1>
*/
#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8
#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100
/* Description REO_GET_QUEUE_STATS_2_RESERVED_2A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9
#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00
/* Description REO_GET_QUEUE_STATS_3_RESERVED_3A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0
#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_4_RESERVED_4A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0
#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_5_RESERVED_5A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0
#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_6_RESERVED_6A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0
#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_7_RESERVED_7A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0
#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_8_RESERVED_8A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0
#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_GET_QUEUE_STATS_H_

965
hw/qca5018/reo_get_queue_stats_status.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
#define _REO_GET_QUEUE_STATS_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 ssn[11:0], current_index[19:12], reserved_2[31:20]
// 3 pn_31_0[31:0]
// 4 pn_63_32[31:0]
// 5 pn_95_64[31:0]
// 6 pn_127_96[31:0]
// 7 last_rx_enqueue_timestamp[31:0]
// 8 last_rx_dequeue_timestamp[31:0]
// 9 rx_bitmap_31_0[31:0]
// 10 rx_bitmap_63_32[31:0]
// 11 rx_bitmap_95_64[31:0]
// 12 rx_bitmap_127_96[31:0]
// 13 rx_bitmap_159_128[31:0]
// 14 rx_bitmap_191_160[31:0]
// 15 rx_bitmap_223_192[31:0]
// 16 rx_bitmap_255_224[31:0]
// 17 current_mpdu_count[6:0], current_msdu_count[31:7]
// 18 reserved_18[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16]
// 19 frames_in_order_count[23:0], bar_received_count[31:24]
// 20 mpdu_frames_processed_count[31:0]
// 21 msdu_frames_processed_count[31:0]
// 22 total_processed_byte_count[31:0]
// 23 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25
struct reo_get_queue_stats_status {
struct uniform_reo_status_header status_header;
uint32_t ssn : 12, //[11:0]
current_index : 8, //[19:12]
reserved_2 : 12; //[31:20]
uint32_t pn_31_0 : 32; //[31:0]
uint32_t pn_63_32 : 32; //[31:0]
uint32_t pn_95_64 : 32; //[31:0]
uint32_t pn_127_96 : 32; //[31:0]
uint32_t last_rx_enqueue_timestamp : 32; //[31:0]
uint32_t last_rx_dequeue_timestamp : 32; //[31:0]
uint32_t rx_bitmap_31_0 : 32; //[31:0]
uint32_t rx_bitmap_63_32 : 32; //[31:0]
uint32_t rx_bitmap_95_64 : 32; //[31:0]
uint32_t rx_bitmap_127_96 : 32; //[31:0]
uint32_t rx_bitmap_159_128 : 32; //[31:0]
uint32_t rx_bitmap_191_160 : 32; //[31:0]
uint32_t rx_bitmap_223_192 : 32; //[31:0]
uint32_t rx_bitmap_255_224 : 32; //[31:0]
uint32_t current_mpdu_count : 7, //[6:0]
current_msdu_count : 25; //[31:7]
uint32_t reserved_18 : 4, //[3:0]
timeout_count : 6, //[9:4]
forward_due_to_bar_count : 6, //[15:10]
duplicate_count : 16; //[31:16]
uint32_t frames_in_order_count : 24, //[23:0]
bar_received_count : 8; //[31:24]
uint32_t mpdu_frames_processed_count : 32; //[31:0]
uint32_t msdu_frames_processed_count : 32; //[31:0]
uint32_t total_processed_byte_count : 32; //[31:0]
uint32_t late_receive_mpdu_count : 12, //[11:0]
window_jump_2k : 4, //[15:12]
hole_count : 16; //[31:16]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
ssn
Starting Sequence number of the session, this changes
whenever window moves. (can be filled by SW then maintained
by REO)
<legal all>
current_index
Points to last forwarded packet
<legal all>
reserved_2
<legal 0>
pn_31_0
<legal all>
pn_63_32
Bits [63:32] of the PN number.
<legal all>
pn_95_64
Bits [95:64] of the PN number.
<legal all>
pn_127_96
Bits [127:96] of the PN number.
<legal all>
last_rx_enqueue_timestamp
Timestamp of arrival of the last MPDU for this queue
<legal all>
last_rx_dequeue_timestamp
Timestamp of forwarding an MPDU
If the queue is empty when a frame gets received, this
time shall be initialized to the 'enqueue' timestamp
Used for aging
<legal all>
rx_bitmap_31_0
When a bit is set, the corresponding frame is currently
held in the re-order queue.
The bitmap is Fully managed by HW.
SW shall init this to 0, and then never ever change it
<legal all>
rx_bitmap_63_32
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_95_64
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_127_96
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_159_128
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_191_160
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_223_192
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_255_224
See Rx_bitmap_31_0 description
<legal all>
current_mpdu_count
The number of MPDUs in the queue.
<legal all>
current_msdu_count
The number of MSDUs in the queue.
<legal all>
reserved_18
<legal 0>
timeout_count
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is Timeout
The counter saturates and freezes at 0x3F
<legal all>
forward_due_to_bar_count
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is reception of BAR frame.
The counter saturates and freezes at 0x3F
<legal all>
duplicate_count
The number of duplicate frames that have been detected
<legal all>
frames_in_order_count
The number of frames that have been received in order
(without a hole that prevented them from being forwarded
immediately)
This corresponds to the Reorder opcodes:
'FWDCUR' and 'FWD BUF'
<legal all>
bar_received_count
The number of times a BAR frame is received.
This corresponds to the Reorder opcodes with 'DROP'
The counter saturates and freezes at 0xFF
<legal all>
mpdu_frames_processed_count
The total number of MPDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
msdu_frames_processed_count
The total number of MSDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
total_processed_byte_count
An approximation of the number of bytes received for
this queue.
In 64 byte units
<legal all>
late_receive_mpdu_count
The number of MPDUs received after the window had
already moved on. The 'late' sequence window is defined as
(Window SSN - 256) - (Window SSN - 1)
This corresponds with Out of order detection in
duplicate detect FSM
The counter saturates and freezes at 0xFFF
<legal all>
window_jump_2k
The number of times the window moved more then 2K
The counter saturates and freezes at 0xF
(Note: field name can not start with number: previous
2k_window_jump)
<legal all>
hole_count
The number of times a hole was created in the receive
bitmap.
This corresponds to the Reorder opcodes with 'QCUR'
<legal all>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
/* Description REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_2_SSN
Starting Sequence number of the session, this changes
whenever window moves. (can be filled by SW then maintained
by REO)
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff
/* Description REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX
Points to last forwarded packet
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000
/* Description REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2
<legal 0>
*/
#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20
#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000
/* Description REO_GET_QUEUE_STATS_STATUS_3_PN_31_0
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c
#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_4_PN_63_32
Bits [63:32] of the PN number.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010
#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_5_PN_95_64
Bits [95:64] of the PN number.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014
#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_6_PN_127_96
Bits [127:96] of the PN number.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018
#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP
Timestamp of arrival of the last MPDU for this queue
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c
#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP
Timestamp of forwarding an MPDU
If the queue is empty when a frame gets received, this
time shall be initialized to the 'enqueue' timestamp
Used for aging
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020
#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0
When a bit is set, the corresponding frame is currently
held in the re-order queue.
The bitmap is Fully managed by HW.
SW shall init this to 0, and then never ever change it
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024
#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028
#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c
#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030
#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034
#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038
#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c
#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040
#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT
The number of MPDUs in the queue.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f
/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT
The number of MSDUs in the queue.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80
/* Description REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18
<legal 0>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f
/* Description REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is Timeout
The counter saturates and freezes at 0x3F
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4
#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0
/* Description REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is reception of BAR frame.
The counter saturates and freezes at 0x3F
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10
#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
/* Description REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT
The number of duplicate frames that have been detected
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000
/* Description REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT
The number of frames that have been received in order
(without a hole that prevented them from being forwarded
immediately)
This corresponds to the Reorder opcodes:
'FWDCUR' and 'FWD BUF'
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c
#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
/* Description REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT
The number of times a BAR frame is received.
This corresponds to the Reorder opcodes with 'DROP'
The counter saturates and freezes at 0xFF
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c
#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24
#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000
/* Description REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT
The total number of MPDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050
#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT
The total number of MSDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054
#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT
An approximation of the number of bytes received for
this queue.
In 64 byte units
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058
#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT
The number of MPDUs received after the window had
already moved on. The 'late' sequence window is defined as
(Window SSN - 256) - (Window SSN - 1)
This corresponds with Out of order detection in
duplicate detect FSM
The counter saturates and freezes at 0xFFF
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c
#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
/* Description REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K
The number of times the window moved more then 2K
The counter saturates and freezes at 0xF
(Note: field name can not start with number: previous
2k_window_jump)
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c
#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000
/* Description REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT
The number of times a hole was created in the receive
bitmap.
This corresponds to the Reorder opcodes with 'QCUR'
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c
#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000
/* Description REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_GET_QUEUE_STATS_STATUS_H_

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hw/qca5018/reo_reg_seq_hwiobase.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
///////////////////////////////////////////////////////////////////////////////////////////////
//
// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
// User Name:c_landav
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __REO_REG_SEQ_BASE_H__
#define __REO_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#endif

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hw/qca5018/reo_reg_seq_hwioreg.h Normal file
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312
hw/qca5018/reo_unblock_cache.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UNBLOCK_CACHE_H_
#define _REO_UNBLOCK_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 unblock_type[0], cache_block_resource_index[2:1], reserved_1a[31:3]
// 2 reserved_2a[31:0]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
struct reo_unblock_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t unblock_type : 1, //[0]
cache_block_resource_index : 2, //[2:1]
reserved_1a : 29; //[31:3]
uint32_t reserved_2a : 32; //[31:0]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
unblock_type
Unblock type
<enum 0 unblock_resource_index> Unblock a block
resource, whose index is given in field
'cache_block_resource_index'.
If the indicated blocking resource is not in use (=> not
blocking an address at the moment), the command status will
indicate an error.
<enum 1 unblock_cache> The entire cache usage is
unblocked.
If the entire cache is not in a blocked mode at the
moment this command is received, the command status will
indicate an error.
Note that unlocking the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
cache_block_resource_index
Field not valid when field Unblock_type is set to
unblock_cache.
Indicates which of the four blocking resources in REO
should be released from blocking a (descriptor) address.
<legal all>
reserved_1a
<legal 0>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
*/
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
*/
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
/* Description REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE
Unblock type
<enum 0 unblock_resource_index> Unblock a block
resource, whose index is given in field
'cache_block_resource_index'.
If the indicated blocking resource is not in use (=> not
blocking an address at the moment), the command status will
indicate an error.
<enum 1 unblock_cache> The entire cache usage is
unblocked.
If the entire cache is not in a blocked mode at the
moment this command is received, the command status will
indicate an error.
Note that unlocking the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
*/
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001
/* Description REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX
Field not valid when field Unblock_type is set to
unblock_cache.
Indicates which of the four blocking resources in REO
should be released from blocking a (descriptor) address.
<legal all>
*/
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006
/* Description REO_UNBLOCK_CACHE_1_RESERVED_1A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8
/* Description REO_UNBLOCK_CACHE_2_RESERVED_2A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_3_RESERVED_3A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_4_RESERVED_4A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_5_RESERVED_5A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_6_RESERVED_6A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_7_RESERVED_7A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_8_RESERVED_8A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_UNBLOCK_CACHE_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
#define _REO_UNBLOCK_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], unblock_type[1], reserved_2a[31:2]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
struct reo_unblock_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
unblock_type : 1, //[1]
reserved_2a : 30; //[31:2]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
Status for blocking resource handling
0: No error has been detected while executing this
command
1: The blocking resource was not in use, and therefor it
could not be 'unblocked'
unblock_type
Reference to the type of Unblock command type...
<enum 0 unblock_resource_index> Unblock a blocking
resource
<enum 1 unblock_cache> The entire cache usage is
unblock.
<legal all>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
/* Description REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED
Status for blocking resource handling
0: No error has been detected while executing this
command
1: The blocking resource was not in use, and therefor it
could not be 'unblocked'
*/
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE
Reference to the type of Unblock command type...
<enum 0 unblock_resource_index> Unblock a blocking
resource
<enum 1 unblock_cache> The entire cache usage is
unblock.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002
/* Description REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc
/* Description REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_UNBLOCK_CACHE_STATUS_H_

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hw/qca5018/reo_update_rx_reo_queue.h Normal file
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hw/qca5018/reo_update_rx_reo_queue_status.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 reserved_2a[31:0]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
struct reo_update_rx_reo_queue_status {
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 32; //[31:0]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_

155
hw/qca5018/rfa_from_wsi_seq_hwiobase.h Normal file
View File

@ -0,0 +1,155 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// rfa_from_wsi_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
// User Name:c_landav
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __RFA_FROM_WSI_SEQ_BASE_H__
#define __RFA_FROM_WSI_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_from_wsi
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x000142e0
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480
#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800
#define SEQ_RFA_FROM_WSI_RFA_CMN_DPLL_OFFSET 0x00014c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016240
#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00
#define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000
#define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000
#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_HLS_BT_REGFILE_OFFSET 0x0001c400
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001c800
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001c840
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001c880
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001c8c0
#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_cmn
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_CMN_AON_OFFSET 0x00000000
#define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240
#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0
#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x000002e0
#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300
#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400
#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480
#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800
#define SEQ_RFA_CMN_DPLL_OFFSET 0x00000c00
#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000
#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040
#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100
#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140
#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180
#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0
#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002240
#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_pmu
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_PMU_PMU_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_bt
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_BT_BT_CH2_OFFSET 0x00000000
#define SEQ_RFA_BT_HLS_BT_REGFILE_OFFSET 0x00000400
#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00000800
#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00000840
#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00000880
#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x000008c0
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_wl
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000
#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400
#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800
#define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000
#define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300
#define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600
#define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640
#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000
#define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000
#define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000
#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400
#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800
#define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000
#define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300
#define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600
#define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640
#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000
#define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000
#endif

1178
hw/qca5018/rx_attention.h Normal file
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hw/qca5018/rx_flow_search_entry.h Normal file
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@ -0,0 +1,786 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_FLOW_SEARCH_ENTRY_H_
#define _RX_FLOW_SEARCH_ENTRY_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 src_ip_127_96[31:0]
// 1 src_ip_95_64[31:0]
// 2 src_ip_63_32[31:0]
// 3 src_ip_31_0[31:0]
// 4 dest_ip_127_96[31:0]
// 5 dest_ip_95_64[31:0]
// 6 dest_ip_63_32[31:0]
// 7 dest_ip_31_0[31:0]
// 8 src_port[15:0], dest_port[31:16]
// 9 l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30]
// 10 metadata[31:0]
// 11 aggregation_count[6:0], lro_eligible[7], msdu_count[31:8]
// 12 msdu_byte_count[31:0]
// 13 timestamp[31:0]
// 14 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16]
// 15 tcp_sequence_number[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
struct rx_flow_search_entry {
uint32_t src_ip_127_96 : 32; //[31:0]
uint32_t src_ip_95_64 : 32; //[31:0]
uint32_t src_ip_63_32 : 32; //[31:0]
uint32_t src_ip_31_0 : 32; //[31:0]
uint32_t dest_ip_127_96 : 32; //[31:0]
uint32_t dest_ip_95_64 : 32; //[31:0]
uint32_t dest_ip_63_32 : 32; //[31:0]
uint32_t dest_ip_31_0 : 32; //[31:0]
uint32_t src_port : 16, //[15:0]
dest_port : 16; //[31:16]
uint32_t l4_protocol : 8, //[7:0]
valid : 1, //[8]
reserved_9 : 15, //[23:9]
reo_destination_indication : 5, //[28:24]
msdu_drop : 1, //[29]
reo_destination_handler : 2; //[31:30]
uint32_t metadata : 32; //[31:0]
uint32_t aggregation_count : 7, //[6:0]
lro_eligible : 1, //[7]
msdu_count : 24; //[31:8]
uint32_t msdu_byte_count : 32; //[31:0]
uint32_t timestamp : 32; //[31:0]
uint32_t cumulative_l4_checksum : 16, //[15:0]
cumulative_ip_length : 16; //[31:16]
uint32_t tcp_sequence_number : 32; //[31:0]
};
/*
src_ip_127_96
Uppermost 32 bits of source IPv6 address or prefix as
per Common Parser register field IP_DA_SA_PREFIX (with the
first byte in the MSB and the last byte in the LSB, i.e.
requiring a byte-swap for little-endian SW w.r.t. the byte
order in an IPv6 packet)
<legal all>
src_ip_95_64
Next 32 bits of source IPv6 address or prefix (requiring
a byte-swap for little-endian SW) <legal all>
src_ip_63_32
Next 32 bits of source IPv6 address or lowest 32 bits of
prefix (requiring a byte-swap for little-endian SW)
<legal all>
src_ip_31_0
Lowest 32 bits of source IPv6 address, or source IPv4
address (requiring a byte-swap for little-endian SW w.r.t.
the byte order in an IPv6 or IPv4 packet)
<legal all>
dest_ip_127_96
Uppermost 32 bits of destination IPv6 address or prefix
as per Common Parser register field IP_DA_SA_PREFIX (with
the first byte in the MSB and the last byte in the LSB, i.e.
requiring a byte-swap for little-endian SW w.r.t. the byte
order as in an IPv6 packet)
<legal all>
dest_ip_95_64
Next 32 bits of destination IPv6 address or prefix
(requiring a byte-swap for little-endian SW)
<legal all>
dest_ip_63_32
Next 32 bits of destination IPv6 address or lowest 32
bits of prefix (requiring a byte-swap for little-endian SW)
<legal all>
dest_ip_31_0
Lowest 32 bits of destination IPv6 address, or
destination IPv4 address (requiring a byte-swap for
little-endian SW w.r.t. the byte order in an IPv6 or IPv4
packet)
<legal all>
src_port
LSB of SPI in case of ESP/AH
else source port in case of TCP/UDP without IPsec,
else zeros in case of ICMP (with the first/third byte in
the MSB and the second/fourth byte in the LSB, i.e.
requiring a byte-swap for little-endian SW w.r.t. the byte
order as in an IPv6 or IPv4 packet) <legal all>
dest_port
MSB of SPI in case of ESP/AH
else destination port in case of TCP/UDP without IPsec,
else zeros in case of ICMP (with the first byte in the
MSB and the second byte in the LSB, i.e. requiring a
byte-swap for little-endian SW w.r.t. the byte order as in
an IPv6 or IPv4 packet)
<legal all>
l4_protocol
IPsec or L4 protocol
<enum 1 ICMPV4>
<enum 6 TCP>
<enum 17 UDP>
<enum 50 ESP>
<enum 51 AH>
<enum 58 ICMPV6>
<legal 1, 6, 17, 50, 51, 58>
valid
Indicates validity of entry
<legal all>
reserved_9
<legal 0>
reo_destination_indication
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW2 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW3 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW4 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_sw5> Reo will push the frame
into the REO2SW5 ring (REO remaps this in chips without
REO2SW5 ring, e.g. Pine)
<enum 8 reo_destination_sw6> Reo will push the frame
into the REO2SW6 ring (REO remaps this in chips without
REO2SW6 ring, e.g. Pine)
<enum 9 reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
msdu_drop
Overriding indication to REO to forward to REO release
ring
<legal all>
reo_destination_handler
Indicates how to decide the REO destination indication
<enum 0 RXFT_USE_FT> Follow this entry
<enum 1 RXFT_USE_ASPT> Use address search+peer table
entry
<enum 2 RXFT_USE_FT2> Follow this entry
<enum 3 RXFT_USE_CCE> Use CCE super-rule
<legal all>
metadata
Value to be passed to SW if this flow search entry
matches
<legal all>
aggregation_count
FISA: Number'of MSDU's aggregated so far
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
lro_eligible
FISA: To indicate whether the previous MSDU for this
flow is eligible for LRO/FISA
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
msdu_count
Number of Rx MSDUs matching this flow
<legal all>
msdu_byte_count
Number of bytes in Rx MSDUs matching this flow
<legal all>
timestamp
Time of last reception (as measured at Rx OLE) matching
this flow
<legal all>
cumulative_l4_checksum
FISA: checksum 'or MSDU's that is part of this flow
aggregated so far
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
cumulative_ip_length
FISA: Total MSDU length that is part of this flow
aggregated so far
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
tcp_sequence_number
FISA: TCP Sequence number of the last packet in this
flow to detect sequence number jump
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
*/
/* Description RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96
Uppermost 32 bits of source IPv6 address or prefix as
per Common Parser register field IP_DA_SA_PREFIX (with the
first byte in the MSB and the last byte in the LSB, i.e.
requiring a byte-swap for little-endian SW w.r.t. the byte
order in an IPv6 packet)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000
#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0
#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64
Next 32 bits of source IPv6 address or prefix (requiring
a byte-swap for little-endian SW) <legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004
#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0
#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32
Next 32 bits of source IPv6 address or lowest 32 bits of
prefix (requiring a byte-swap for little-endian SW)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008
#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0
#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0
Lowest 32 bits of source IPv6 address, or source IPv4
address (requiring a byte-swap for little-endian SW w.r.t.
the byte order in an IPv6 or IPv4 packet)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c
#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0
#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96
Uppermost 32 bits of destination IPv6 address or prefix
as per Common Parser register field IP_DA_SA_PREFIX (with
the first byte in the MSB and the last byte in the LSB, i.e.
requiring a byte-swap for little-endian SW w.r.t. the byte
order as in an IPv6 packet)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010
#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0
#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64
Next 32 bits of destination IPv6 address or prefix
(requiring a byte-swap for little-endian SW)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014
#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0
#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32
Next 32 bits of destination IPv6 address or lowest 32
bits of prefix (requiring a byte-swap for little-endian SW)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018
#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0
#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0
Lowest 32 bits of destination IPv6 address, or
destination IPv4 address (requiring a byte-swap for
little-endian SW w.r.t. the byte order in an IPv6 or IPv4
packet)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c
#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0
#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_8_SRC_PORT
LSB of SPI in case of ESP/AH
else source port in case of TCP/UDP without IPsec,
else zeros in case of ICMP (with the first/third byte in
the MSB and the second/fourth byte in the LSB, i.e.
requiring a byte-swap for little-endian SW w.r.t. the byte
order as in an IPv6 or IPv4 packet) <legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020
#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff
/* Description RX_FLOW_SEARCH_ENTRY_8_DEST_PORT
MSB of SPI in case of ESP/AH
else destination port in case of TCP/UDP without IPsec,
else zeros in case of ICMP (with the first byte in the
MSB and the second byte in the LSB, i.e. requiring a
byte-swap for little-endian SW w.r.t. the byte order as in
an IPv6 or IPv4 packet)
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020
#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16
#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000
/* Description RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL
IPsec or L4 protocol
<enum 1 ICMPV4>
<enum 6 TCP>
<enum 17 UDP>
<enum 50 ESP>
<enum 51 AH>
<enum 58 ICMPV6>
<legal 1, 6, 17, 50, 51, 58>
*/
#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0
#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff
/* Description RX_FLOW_SEARCH_ENTRY_9_VALID
Indicates validity of entry
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8
#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100
/* Description RX_FLOW_SEARCH_ENTRY_9_RESERVED_9
<legal 0>
*/
#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9
#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00
/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW2 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW3 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW4 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_sw5> Reo will push the frame
into the REO2SW5 ring (REO remaps this in chips without
REO2SW5 ring, e.g. Pine)
<enum 8 reo_destination_sw6> Reo will push the frame
into the REO2SW6 ring (REO remaps this in chips without
REO2SW6 ring, e.g. Pine)
<enum 9 reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24
#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000
/* Description RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP
Overriding indication to REO to forward to REO release
ring
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29
#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000
/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER
Indicates how to decide the REO destination indication
<enum 0 RXFT_USE_FT> Follow this entry
<enum 1 RXFT_USE_ASPT> Use address search+peer table
entry
<enum 2 RXFT_USE_FT2> Follow this entry
<enum 3 RXFT_USE_CCE> Use CCE super-rule
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30
#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000
/* Description RX_FLOW_SEARCH_ENTRY_10_METADATA
Value to be passed to SW if this flow search entry
matches
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028
#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0
#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT
FISA: Number'of MSDU's aggregated so far
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f
/* Description RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE
FISA: To indicate whether the previous MSDU for this
flow is eligible for LRO/FISA
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7
#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080
/* Description RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT
Number of Rx MSDUs matching this flow
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8
#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00
/* Description RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT
Number of bytes in Rx MSDUs matching this flow
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030
#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP
Time of last reception (as measured at Rx OLE) matching
this flow
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034
#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0
#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff
/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM
FISA: checksum 'or MSDU's that is part of this flow
aggregated so far
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038
#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0
#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH
FISA: Total MSDU length that is part of this flow
aggregated so far
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038
#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16
#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
/* Description RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER
FISA: TCP Sequence number of the last packet in this
flow to detect sequence number jump
Set to zero in chips not supporting FISA, e.g. Pine
<legal all>
*/
#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c
#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0
#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff
#endif // _RX_FLOW_SEARCH_ENTRY_H_

1369
hw/qca5018/rx_location_info.h Normal file
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468
hw/qca5018/rx_mpdu_desc_info.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_DESC_INFO_H_
#define _RX_MPDU_DESC_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 msdu_count[7:0], mpdu_sequence_number[19:8], fragment_flag[20], mpdu_retry_bit[21], ampdu_flag[22], bar_frame[23], pn_fields_contain_valid_info[24], sa_is_valid[25], sa_idx_timeout[26], da_is_valid[27], da_is_mcbc[28], da_idx_timeout[29], raw_mpdu[30], more_fragment_flag[31]
// 1 peer_meta_data[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
struct rx_mpdu_desc_info {
uint32_t msdu_count : 8, //[7:0]
mpdu_sequence_number : 12, //[19:8]
fragment_flag : 1, //[20]
mpdu_retry_bit : 1, //[21]
ampdu_flag : 1, //[22]
bar_frame : 1, //[23]
pn_fields_contain_valid_info : 1, //[24]
sa_is_valid : 1, //[25]
sa_idx_timeout : 1, //[26]
da_is_valid : 1, //[27]
da_is_mcbc : 1, //[28]
da_idx_timeout : 1, //[29]
raw_mpdu : 1, //[30]
more_fragment_flag : 1; //[31]
uint32_t peer_meta_data : 32; //[31:0]
};
/*
msdu_count
Consumer: REO/SW/FW
Producer: RXDMA
The number of MSDUs within the MPDU
<legal all>
mpdu_sequence_number
Consumer: REO/SW/FW
Producer: RXDMA
The field can have two different meanings based on the
setting of field 'BAR_frame':
'BAR_frame' is NOT set:
The MPDU sequence number of the received frame.
'BAR_frame' is set.
The MPDU Start sequence number from the BAR frame
<legal all>
fragment_flag
Consumer: REO/SW/FW
Producer: RXDMA
When set, this MPDU is a fragment and REO should forward
this fragment MPDU to the REO destination ring without any
reorder checks, pn checks or bitmap update. This implies
that REO is forwarding the pointer to the MSDU link
descriptor. The destination ring is coming from a
programmable register setting in REO
<legal all>
mpdu_retry_bit
Consumer: REO/SW/FW
Producer: RXDMA
The retry bit setting from the MPDU header of the
received frame
<legal all>
ampdu_flag
Consumer: REO/SW/FW
Producer: RXDMA
When set, the MPDU was received as part of an A-MPDU.
<legal all>
bar_frame
Consumer: REO/SW/FW
Producer: RXDMA
When set, the received frame is a BAR frame. After
processing, this frame shall be pushed to SW or deleted.
<legal all>
pn_fields_contain_valid_info
Consumer: REO/SW/FW
Producer: RXDMA
Copied here by RXDMA from RX_MPDU_END
When not set, REO will Not perform a PN sequence number
check
sa_is_valid
When set, OLE found a valid SA entry for all MSDUs in
this MPDU
<legal all>
sa_idx_timeout
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC source address search due to the expiration
of the search timer.
<legal all>
da_is_valid
When set, OLE found a valid DA entry for all MSDUs in
this MPDU
<legal all>
da_is_mcbc
Field Only valid if da_is_valid is set
When set, at least one of the DA addresses is a
Multicast or Broadcast address.
<legal all>
da_idx_timeout
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC destination address search due to the
expiration of the search timer.
<legal all>
raw_mpdu
Field only valid when first_msdu_in_mpdu_flag is set.
When set, the contents in the MSDU buffer contains a
'RAW' MPDU. This 'RAW' MPDU might be spread out over
multiple MSDU buffers.
<legal all>
more_fragment_flag
The More Fragment bit setting from the MPDU header of
the received frame
<legal all>
peer_meta_data
Meta data that SW has programmed in the Peer table entry
of the transmitting STA.
<legal all>
*/
/* Description RX_MPDU_DESC_INFO_0_MSDU_COUNT
Consumer: REO/SW/FW
Producer: RXDMA
The number of MSDUs within the MPDU
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0
#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff
/* Description RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER
Consumer: REO/SW/FW
Producer: RXDMA
The field can have two different meanings based on the
setting of field 'BAR_frame':
'BAR_frame' is NOT set:
The MPDU sequence number of the received frame.
'BAR_frame' is set.
The MPDU Start sequence number from the BAR frame
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8
#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
/* Description RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG
Consumer: REO/SW/FW
Producer: RXDMA
When set, this MPDU is a fragment and REO should forward
this fragment MPDU to the REO destination ring without any
reorder checks, pn checks or bitmap update. This implies
that REO is forwarding the pointer to the MSDU link
descriptor. The destination ring is coming from a
programmable register setting in REO
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20
#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000
/* Description RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT
Consumer: REO/SW/FW
Producer: RXDMA
The retry bit setting from the MPDU header of the
received frame
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21
#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000
/* Description RX_MPDU_DESC_INFO_0_AMPDU_FLAG
Consumer: REO/SW/FW
Producer: RXDMA
When set, the MPDU was received as part of an A-MPDU.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22
#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000
/* Description RX_MPDU_DESC_INFO_0_BAR_FRAME
Consumer: REO/SW/FW
Producer: RXDMA
When set, the received frame is a BAR frame. After
processing, this frame shall be pushed to SW or deleted.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23
#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000
/* Description RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO
Consumer: REO/SW/FW
Producer: RXDMA
Copied here by RXDMA from RX_MPDU_END
When not set, REO will Not perform a PN sequence number
check
*/
#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
/* Description RX_MPDU_DESC_INFO_0_SA_IS_VALID
When set, OLE found a valid SA entry for all MSDUs in
this MPDU
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25
#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000
/* Description RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC source address search due to the expiration
of the search timer.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26
#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000
/* Description RX_MPDU_DESC_INFO_0_DA_IS_VALID
When set, OLE found a valid DA entry for all MSDUs in
this MPDU
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27
#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000
/* Description RX_MPDU_DESC_INFO_0_DA_IS_MCBC
Field Only valid if da_is_valid is set
When set, at least one of the DA addresses is a
Multicast or Broadcast address.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28
#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000
/* Description RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC destination address search due to the
expiration of the search timer.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29
#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000
/* Description RX_MPDU_DESC_INFO_0_RAW_MPDU
Field only valid when first_msdu_in_mpdu_flag is set.
When set, the contents in the MSDU buffer contains a
'RAW' MPDU. This 'RAW' MPDU might be spread out over
multiple MSDU buffers.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30
#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000
/* Description RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG
The More Fragment bit setting from the MPDU header of
the received frame
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB 31
#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK 0x80000000
/* Description RX_MPDU_DESC_INFO_1_PEER_META_DATA
Meta data that SW has programmed in the Peer table entry
of the transmitting STA.
<legal all>
*/
#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004
#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0
#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff
#endif // _RX_MPDU_DESC_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_DETAILS_H_
#define _RX_MPDU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#include "rx_mpdu_desc_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info msdu_link_desc_addr_info;
// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
struct rx_mpdu_details {
struct buffer_addr_info msdu_link_desc_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
};
/*
struct buffer_addr_info msdu_link_desc_addr_info
Consumer: REO/SW/FW
Producer: RXDMA
Details of the physical address of the MSDU link
descriptor that contains pointers to MSDUs related to this
MPDU
struct rx_mpdu_desc_info rx_mpdu_desc_info_details
Consumer: REO/SW/FW
Producer: RXDMA
General information related to the MPDU that should be
*/
/* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
/* Description RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<enum 7 SW4_BM> This buffer shall be returned to the SW,
ring 4
<legal all>
*/
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE1:
The three most significant bits can have a special
meaning in case this struct is embedded in a TX_MPDU_DETAILS
STRUCT, and field transmit_bw_restriction is set
In case of NON punctured transmission:
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
In case of punctured transmission:
Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
Note: a punctured transmission is indicated by the
presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
TLV
NOTE 2:The five most significant bits can have a special
meaning in case this struct is embedded in an
RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
configured for passing on the additional info
from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
(FR56821). This is not supported in HastingsPrime, Pine or
Moselle.
Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
control field
Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
indicates MPDUs with a QoS control field.
<legal all>
*/
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
/* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
Consumer: REO/SW/FW
Producer: RXDMA
The number of MSDUs within the MPDU
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
Consumer: REO/SW/FW
Producer: RXDMA
The field can have two different meanings based on the
setting of field 'BAR_frame':
'BAR_frame' is NOT set:
The MPDU sequence number of the received frame.
'BAR_frame' is set.
The MPDU Start sequence number from the BAR frame
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
Consumer: REO/SW/FW
Producer: RXDMA
When set, this MPDU is a fragment and REO should forward
this fragment MPDU to the REO destination ring without any
reorder checks, pn checks or bitmap update. This implies
that REO is forwarding the pointer to the MSDU link
descriptor. The destination ring is coming from a
programmable register setting in REO
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
Consumer: REO/SW/FW
Producer: RXDMA
The retry bit setting from the MPDU header of the
received frame
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
Consumer: REO/SW/FW
Producer: RXDMA
When set, the MPDU was received as part of an A-MPDU.
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
Consumer: REO/SW/FW
Producer: RXDMA
When set, the received frame is a BAR frame. After
processing, this frame shall be pushed to SW or deleted.
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
Consumer: REO/SW/FW
Producer: RXDMA
Copied here by RXDMA from RX_MPDU_END
When not set, REO will Not perform a PN sequence number
check
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
When set, OLE found a valid SA entry for all MSDUs in
this MPDU
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC source address search due to the expiration
of the search timer.
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
When set, OLE found a valid DA entry for all MSDUs in
this MPDU
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
Field Only valid if da_is_valid is set
When set, at least one of the DA addresses is a
Multicast or Broadcast address.
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC destination address search due to the
expiration of the search timer.
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
Field only valid when first_msdu_in_mpdu_flag is set.
When set, the contents in the MSDU buffer contains a
'RAW' MPDU. This 'RAW' MPDU might be spread out over
multiple MSDU buffers.
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
The More Fragment bit setting from the MPDU header of
the received frame
<legal all>
*/
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
/* Description RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
Meta data that SW has programmed in the Peer table entry
of the transmitting STA.
<legal all>
*/
#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#endif // _RX_MPDU_DETAILS_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_END_H_
#define _RX_MPDU_END_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
// 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_END 2
struct rx_mpdu_end {
uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
sw_frame_group_id : 7, //[8:2]
reserved_0 : 7, //[15:9]
phy_ppdu_id : 16; //[31:16]
uint32_t reserved_1a : 11, //[10:0]
unsup_ktype_short_frame : 1, //[11]
rx_in_tx_decrypt_byp : 1, //[12]
overflow_err : 1, //[13]
mpdu_length_err : 1, //[14]
tkip_mic_err : 1, //[15]
decrypt_err : 1, //[16]
unencrypted_frame_err : 1, //[17]
pn_fields_contain_valid_info : 1, //[18]
fcs_err : 1, //[19]
msdu_length_err : 1, //[20]
rxdma0_destination_ring : 2, //[22:21]
rxdma1_destination_ring : 2, //[24:23]
decrypt_status_code : 3, //[27:25]
rx_bitmap_not_updated : 1, //[28]
reserved_1b : 3; //[31:29]
};
/*
rxpcu_mpdu_filter_in_category
Field indicates what the reason was that this MPDU frame
was allowed to come into the receive path by RXPCU
<enum 0 rxpcu_filter_pass> This MPDU passed the normal
frame filter programming of rxpcu
<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
regular frame filter and would have been dropped, were it
not for the frame fitting into the 'monitor_client'
category.
<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
regular frame filter and also did not pass the
rxpcu_monitor_client filter. It would have been dropped
accept that it did pass the 'monitor_other' category.
<legal 0-2>
sw_frame_group_id
SW processes frames based on certain classifications.
This field indicates to what sw classification this MPDU is
mapped.
The classification is given in priority order
<enum 0 sw_frame_group_NDP_frame>
<enum 1 sw_frame_group_Multicast_data>
<enum 2 sw_frame_group_Unicast_data>
<enum 3 sw_frame_group_Null_data > This includes mpdus
of type Data Null as well as QoS Data Null
<enum 4 sw_frame_group_mgmt_0000 >
<enum 5 sw_frame_group_mgmt_0001 >
<enum 6 sw_frame_group_mgmt_0010 >
<enum 7 sw_frame_group_mgmt_0011 >
<enum 8 sw_frame_group_mgmt_0100 >
<enum 9 sw_frame_group_mgmt_0101 >
<enum 10 sw_frame_group_mgmt_0110 >
<enum 11 sw_frame_group_mgmt_0111 >
<enum 12 sw_frame_group_mgmt_1000 >
<enum 13 sw_frame_group_mgmt_1001 >
<enum 14 sw_frame_group_mgmt_1010 >
<enum 15 sw_frame_group_mgmt_1011 >
<enum 16 sw_frame_group_mgmt_1100 >
<enum 17 sw_frame_group_mgmt_1101 >
<enum 18 sw_frame_group_mgmt_1110 >
<enum 19 sw_frame_group_mgmt_1111 >
<enum 20 sw_frame_group_ctrl_0000 >
<enum 21 sw_frame_group_ctrl_0001 >
<enum 22 sw_frame_group_ctrl_0010 >
<enum 23 sw_frame_group_ctrl_0011 >
<enum 24 sw_frame_group_ctrl_0100 >
<enum 25 sw_frame_group_ctrl_0101 >
<enum 26 sw_frame_group_ctrl_0110 >
<enum 27 sw_frame_group_ctrl_0111 >
<enum 28 sw_frame_group_ctrl_1000 >
<enum 29 sw_frame_group_ctrl_1001 >
<enum 30 sw_frame_group_ctrl_1010 >
<enum 31 sw_frame_group_ctrl_1011 >
<enum 32 sw_frame_group_ctrl_1100 >
<enum 33 sw_frame_group_ctrl_1101 >
<enum 34 sw_frame_group_ctrl_1110 >
<enum 35 sw_frame_group_ctrl_1111 >
<enum 36 sw_frame_group_unsupported> This covers type 3
and protocol version != 0
<legal 0-37>
reserved_0
<legal 0>
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
reserved_1a
<legal 0>
unsup_ktype_short_frame
This bit will be '1' when WEP or TKIP or WAPI key type
is received for 11ah short frame. Crypto will bypass the
received packet without decryption to RxOLE after setting
this bit.
rx_in_tx_decrypt_byp
Indicates that RX packet is not decrypted as Crypto is
busy with TX packet processing.
overflow_err
RXPCU Receive FIFO ran out of space to receive the full
MPDU. Therefor this MPDU is terminated early and is thus
corrupted.
This MPDU will not be ACKed.
RXPCU might still be able to correctly receive the
following MPDUs in the PPDU if enough fifo space became
available in time
mpdu_length_err
Set by RXPCU if the expected MPDU length does not
correspond with the actually received number of bytes in the
MPDU.
tkip_mic_err
Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
for this MPDU
decrypt_err
Set by RX CRYPTO when CRYPTO detected a decrypt error
for this MPDU or CRYPTO received an encrypted frame, but did
not get a valid corresponding key id in the peer entry.
unencrypted_frame_err
Set by RX CRYPTO when CRYPTO detected an unencrypted
frame while in the peer entry field
'All_frames_shall_be_encrypted' is set.
pn_fields_contain_valid_info
Set by RX CRYPTO to indicate that there is a valid PN
field present in this MPDU
fcs_err
Set by RXPCU when there is an FCS error detected for
this MPDU
NOTE that when this field is set, all other (error)
field settings should be ignored as modules could have made
wrong decisions based on the corrupted data.
msdu_length_err
Set by RXOLE when there is an msdu length error detected
in at least 1 of the MSDUs embedded within the MPDU
rxdma0_destination_ring
The ring to which RXDMA0 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA0 might change the RXDMA0 destination
<enum 0 rxdma_release_ring > RXDMA0 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
to the REO entrance ring
<legal all>
rxdma1_destination_ring
The ring to which RXDMA1 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA1 might change the RXDMA destination
<enum 0 rxdma_release_ring > RXDMA1 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
to the REO entrance ring
<legal all>
decrypt_status_code
Field provides insight into the decryption performed
<enum 0 decrypt_ok> Frame had protection enabled and
decrypted properly
<enum 1 decrypt_unprotected_frame > Frame is unprotected
and hence bypassed
<enum 2 decrypt_data_err > Frame has protection enabled
and could not be properly decrypted due to MIC/ICV mismatch
etc.
<enum 3 decrypt_key_invalid > Frame has protection
enabled but the key that was required to decrypt this frame
was not valid
<enum 4 decrypt_peer_entry_invalid > Frame has
protection enabled but the key that was required to decrypt
this frame was not valid
<enum 5 decrypt_other > Reserved for other indications
<legal 0 - 5>
rx_bitmap_not_updated
Frame is received, but RXPCU could not update the
receive bitmap due to (temporary) fifo contraints.
<legal all>
reserved_1b
<legal 0>
*/
/* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
Field indicates what the reason was that this MPDU frame
was allowed to come into the receive path by RXPCU
<enum 0 rxpcu_filter_pass> This MPDU passed the normal
frame filter programming of rxpcu
<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
regular frame filter and would have been dropped, were it
not for the frame fitting into the 'monitor_client'
category.
<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
regular frame filter and also did not pass the
rxpcu_monitor_client filter. It would have been dropped
accept that it did pass the 'monitor_other' category.
<legal 0-2>
*/
#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
/* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID
SW processes frames based on certain classifications.
This field indicates to what sw classification this MPDU is
mapped.
The classification is given in priority order
<enum 0 sw_frame_group_NDP_frame>
<enum 1 sw_frame_group_Multicast_data>
<enum 2 sw_frame_group_Unicast_data>
<enum 3 sw_frame_group_Null_data > This includes mpdus
of type Data Null as well as QoS Data Null
<enum 4 sw_frame_group_mgmt_0000 >
<enum 5 sw_frame_group_mgmt_0001 >
<enum 6 sw_frame_group_mgmt_0010 >
<enum 7 sw_frame_group_mgmt_0011 >
<enum 8 sw_frame_group_mgmt_0100 >
<enum 9 sw_frame_group_mgmt_0101 >
<enum 10 sw_frame_group_mgmt_0110 >
<enum 11 sw_frame_group_mgmt_0111 >
<enum 12 sw_frame_group_mgmt_1000 >
<enum 13 sw_frame_group_mgmt_1001 >
<enum 14 sw_frame_group_mgmt_1010 >
<enum 15 sw_frame_group_mgmt_1011 >
<enum 16 sw_frame_group_mgmt_1100 >
<enum 17 sw_frame_group_mgmt_1101 >
<enum 18 sw_frame_group_mgmt_1110 >
<enum 19 sw_frame_group_mgmt_1111 >
<enum 20 sw_frame_group_ctrl_0000 >
<enum 21 sw_frame_group_ctrl_0001 >
<enum 22 sw_frame_group_ctrl_0010 >
<enum 23 sw_frame_group_ctrl_0011 >
<enum 24 sw_frame_group_ctrl_0100 >
<enum 25 sw_frame_group_ctrl_0101 >
<enum 26 sw_frame_group_ctrl_0110 >
<enum 27 sw_frame_group_ctrl_0111 >
<enum 28 sw_frame_group_ctrl_1000 >
<enum 29 sw_frame_group_ctrl_1001 >
<enum 30 sw_frame_group_ctrl_1010 >
<enum 31 sw_frame_group_ctrl_1011 >
<enum 32 sw_frame_group_ctrl_1100 >
<enum 33 sw_frame_group_ctrl_1101 >
<enum 34 sw_frame_group_ctrl_1110 >
<enum 35 sw_frame_group_ctrl_1111 >
<enum 36 sw_frame_group_unsupported> This covers type 3
and protocol version != 0
<legal 0-37>
*/
#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2
#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
/* Description RX_MPDU_END_0_RESERVED_0
<legal 0>
*/
#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000
#define RX_MPDU_END_0_RESERVED_0_LSB 9
#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00
/* Description RX_MPDU_END_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16
#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
/* Description RX_MPDU_END_1_RESERVED_1A
<legal 0>
*/
#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004
#define RX_MPDU_END_1_RESERVED_1A_LSB 0
#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff
/* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME
This bit will be '1' when WEP or TKIP or WAPI key type
is received for 11ah short frame. Crypto will bypass the
received packet without decryption to RxOLE after setting
this bit.
*/
#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004
#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11
#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800
/* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP
Indicates that RX packet is not decrypted as Crypto is
busy with TX packet processing.
*/
#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12
#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000
/* Description RX_MPDU_END_1_OVERFLOW_ERR
RXPCU Receive FIFO ran out of space to receive the full
MPDU. Therefor this MPDU is terminated early and is thus
corrupted.
This MPDU will not be ACKed.
RXPCU might still be able to correctly receive the
following MPDUs in the PPDU if enough fifo space became
available in time
*/
#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13
#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000
/* Description RX_MPDU_END_1_MPDU_LENGTH_ERR
Set by RXPCU if the expected MPDU length does not
correspond with the actually received number of bytes in the
MPDU.
*/
#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14
#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000
/* Description RX_MPDU_END_1_TKIP_MIC_ERR
Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
for this MPDU
*/
#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15
#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000
/* Description RX_MPDU_END_1_DECRYPT_ERR
Set by RX CRYPTO when CRYPTO detected a decrypt error
for this MPDU or CRYPTO received an encrypted frame, but did
not get a valid corresponding key id in the peer entry.
*/
#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16
#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000
/* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR
Set by RX CRYPTO when CRYPTO detected an unencrypted
frame while in the peer entry field
'All_frames_shall_be_encrypted' is set.
*/
#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17
#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000
/* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO
Set by RX CRYPTO to indicate that there is a valid PN
field present in this MPDU
*/
#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004
#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18
#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000
/* Description RX_MPDU_END_1_FCS_ERR
Set by RXPCU when there is an FCS error detected for
this MPDU
NOTE that when this field is set, all other (error)
field settings should be ignored as modules could have made
wrong decisions based on the corrupted data.
*/
#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_FCS_ERR_LSB 19
#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000
/* Description RX_MPDU_END_1_MSDU_LENGTH_ERR
Set by RXOLE when there is an msdu length error detected
in at least 1 of the MSDUs embedded within the MPDU
*/
#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20
#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000
/* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING
The ring to which RXDMA0 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA0 might change the RXDMA0 destination
<enum 0 rxdma_release_ring > RXDMA0 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
to the REO entrance ring
<legal all>
*/
#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004
#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21
#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000
/* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING
The ring to which RXDMA1 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA1 might change the RXDMA destination
<enum 0 rxdma_release_ring > RXDMA1 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
to the REO entrance ring
<legal all>
*/
#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004
#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23
#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000
/* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE
Field provides insight into the decryption performed
<enum 0 decrypt_ok> Frame had protection enabled and
decrypted properly
<enum 1 decrypt_unprotected_frame > Frame is unprotected
and hence bypassed
<enum 2 decrypt_data_err > Frame has protection enabled
and could not be properly decrypted due to MIC/ICV mismatch
etc.
<enum 3 decrypt_key_invalid > Frame has protection
enabled but the key that was required to decrypt this frame
was not valid
<enum 4 decrypt_peer_entry_invalid > Frame has
protection enabled but the key that was required to decrypt
this frame was not valid
<enum 5 decrypt_other > Reserved for other indications
<legal 0 - 5>
*/
#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004
#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25
#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000
/* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED
Frame is received, but RXPCU could not update the
receive bitmap due to (temporary) fifo contraints.
<legal all>
*/
#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004
#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28
#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000
/* Description RX_MPDU_END_1_RESERVED_1B
<legal 0>
*/
#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004
#define RX_MPDU_END_1_RESERVED_1B_LSB 29
#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000
#endif // _RX_MPDU_END_H_

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hw/qca5018/rx_mpdu_info.h Normal file
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hw/qca5018/rx_mpdu_link_ptr.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_LINK_PTR_H_
#define _RX_MPDU_LINK_PTR_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info mpdu_link_desc_addr_info;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
struct rx_mpdu_link_ptr {
struct buffer_addr_info mpdu_link_desc_addr_info;
};
/*
struct buffer_addr_info mpdu_link_desc_addr_info
Details of the physical address of an MPDU link
descriptor
*/
/* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
/* Description RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<enum 7 SW4_BM> This buffer shall be returned to the SW,
ring 4
<legal all>
*/
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE1:
The three most significant bits can have a special
meaning in case this struct is embedded in a TX_MPDU_DETAILS
STRUCT, and field transmit_bw_restriction is set
In case of NON punctured transmission:
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
In case of punctured transmission:
Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
Note: a punctured transmission is indicated by the
presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
TLV
NOTE 2:The five most significant bits can have a special
meaning in case this struct is embedded in an
RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
configured for passing on the additional info
from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
(FR56821). This is not supported in HastingsPrime, Pine or
Moselle.
Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
control field
Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
indicates MPDUs with a QoS control field.
<legal all>
*/
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
#endif // _RX_MPDU_LINK_PTR_H_

1974
hw/qca5018/rx_mpdu_start.h Normal file
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840
hw/qca5018/rx_msdu_desc_info.h Normal file
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@ -0,0 +1,840 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MSDU_DESC_INFO_H_
#define _RX_MSDU_DESC_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], l3_header_padding_msb[28], tcp_udp_chksum_fail[29], ip_chksum_fail[30], raw_mpdu[31]
// 1 sa_idx_or_sw_peer_id_14_0[14:0], mpdu_ast_idx_or_sw_peer_id_14_0[29:15], fr_ds[30], to_ds[31]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2
struct rx_msdu_desc_info {
uint32_t first_msdu_in_mpdu_flag : 1, //[0]
last_msdu_in_mpdu_flag : 1, //[1]
msdu_continuation : 1, //[2]
msdu_length : 14, //[16:3]
reo_destination_indication : 5, //[21:17]
msdu_drop : 1, //[22]
sa_is_valid : 1, //[23]
sa_idx_timeout : 1, //[24]
da_is_valid : 1, //[25]
da_is_mcbc : 1, //[26]
da_idx_timeout : 1, //[27]
l3_header_padding_msb : 1, //[28]
tcp_udp_chksum_fail : 1, //[29]
ip_chksum_fail : 1, //[30]
raw_mpdu : 1; //[31]
uint32_t sa_idx_or_sw_peer_id_14_0 : 15, //[14:0]
mpdu_ast_idx_or_sw_peer_id_14_0 : 15, //[29:15]
fr_ds : 1, //[30]
to_ds : 1; //[31]
};
/*
first_msdu_in_mpdu_flag
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
<enum 0 Not_first_msdu> This is not the first MSDU in
the MPDU.
<enum 1 first_msdu> This MSDU is the first one in the
MPDU.
<legal all>
last_msdu_in_mpdu_flag
Consumer: WBM/REO/SW/FW
Producer: RXDMA
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
<enum 0 Not_last_msdu> There are more MSDUs linked to
this MSDU that belongs to this MPDU
<enum 1 Last_msdu> this MSDU is the last one in the
MPDU. This setting is only allowed in combination with
'Msdu_continuation' set to 0. This implies that when an msdu
is spread out over multiple buffers and thus
msdu_continuation is set, only for the very last buffer of
the msdu, can the 'last_msdu_in_mpdu_flag' be set.
When both first_msdu_in_mpdu_flag and
last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
belongs to only contains a single MSDU.
<legal all>
msdu_continuation
When set, this MSDU buffer was not able to hold the
entire MSDU. The next buffer will therefor contain
additional information related to this MSDU.
<legal all>
msdu_length
Parsed from RX_MSDU_START TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the First
buffer used by MSDU.
Full MSDU length in bytes after decapsulation.
This field is still valid for MPDU frames without
A-MSDU. It still represents MSDU length after decapsulation
Or in case of RAW MPDUs, it indicates the length of the
entire MPDU (without FCS field)
<legal all>
reo_destination_indication
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW2 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW3 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW4 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_sw5> Reo will push the frame
into the REO2SW5 ring (REO remaps this in chips without
REO2SW5 ring, e.g. Pine)
<enum 8 reo_destination_sw6> Reo will push the frame
into the REO2SW6 ring (REO remaps this in chips without
REO2SW6 ring, e.g. Pine)
<enum 9 reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
msdu_drop
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
When set, REO shall drop this MSDU and not forward it to
any other ring...
<legal all>
sa_is_valid
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates that OLE found a valid SA entry for this MSDU
<legal all>
sa_idx_timeout
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates an unsuccessful MAC source address search due
to the expiring of the search timer for this MSDU
<legal all>
da_is_valid
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates that OLE found a valid DA entry for this MSDU
<legal all>
da_is_mcbc
Field Only valid if da_is_valid is set
Indicates the DA address was a Multicast of Broadcast
address for this MSDU
<legal all>
da_idx_timeout
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates an unsuccessful MAC destination address search
due to the expiring of the search timer for this MSDU
<legal all>
l3_header_padding_msb
Passed on from 'RX_MSDU_END' TLV (only the MSB is
reported as the LSB is always zero)
Number of bytes padded to make sure that the L3 header
will always start of a Dword boundary
<legal all>
tcp_udp_chksum_fail
Passed on from 'RX_ATTENTION' TLV
Indicates that the computed checksum did not match the
checksum in the TCP/UDP header.
<legal all>
ip_chksum_fail
Passed on from 'RX_ATTENTION' TLV
Indicates that the computed checksum did not match the
checksum in the IP header.
<legal all>
raw_mpdu
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set to 1 by RXOLE when it has not performed any 802.11
to Ethernet/Natvie WiFi header conversion on this MPDU.
<legal all>
sa_idx_or_sw_peer_id_14_0
Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
Based on a register configuration in RXDMA, this field
will contain:
The offset in the address search table which matches the
MAC source address
OR
'sw_peer_id' from the address search entry corresponding
to the source address of the MSDU
<legal all>
mpdu_ast_idx_or_sw_peer_id_14_0
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV (one MSB is omitted)
Based on a register configuration in RXDMA, this field
will contain:
The index of the address search entry corresponding to
this MPDU (a value of 0xFFFF indicates an invalid AST index,
meaning that no AST entry was found or no AST search was
performed)
OR:
'sw_peer_id' from the address search entry corresponding
to this MPDU (in case of ndp or phy_err or
AST_based_lookup_valid == 0, this field will be set to 0)
<legal all>
fr_ds
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set if the 'from DS' bit is set in the frame control.
<legal all>
to_ds
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set if the 'to DS' bit is set in the frame control.
<legal all>
*/
/* Description RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
<enum 0 Not_first_msdu> This is not the first MSDU in
the MPDU.
<enum 1 first_msdu> This MSDU is the first one in the
MPDU.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
/* Description RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG
Consumer: WBM/REO/SW/FW
Producer: RXDMA
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
<enum 0 Not_last_msdu> There are more MSDUs linked to
this MSDU that belongs to this MPDU
<enum 1 Last_msdu> this MSDU is the last one in the
MPDU. This setting is only allowed in combination with
'Msdu_continuation' set to 0. This implies that when an msdu
is spread out over multiple buffers and thus
msdu_continuation is set, only for the very last buffer of
the msdu, can the 'last_msdu_in_mpdu_flag' be set.
When both first_msdu_in_mpdu_flag and
last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
belongs to only contains a single MSDU.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
/* Description RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION
When set, this MSDU buffer was not able to hold the
entire MSDU. The next buffer will therefor contain
additional information related to this MSDU.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2
#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004
/* Description RX_MSDU_DESC_INFO_0_MSDU_LENGTH
Parsed from RX_MSDU_START TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the First
buffer used by MSDU.
Full MSDU length in bytes after decapsulation.
This field is still valid for MPDU frames without
A-MSDU. It still represents MSDU length after decapsulation
Or in case of RAW MPDUs, it indicates the length of the
entire MPDU (without FCS field)
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3
#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8
/* Description RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW2 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW3 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW4 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_sw5> Reo will push the frame
into the REO2SW5 ring (REO remaps this in chips without
REO2SW5 ring, e.g. Pine)
<enum 8 reo_destination_sw6> Reo will push the frame
into the REO2SW6 ring (REO remaps this in chips without
REO2SW6 ring, e.g. Pine)
<enum 9 reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17
#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000
/* Description RX_MSDU_DESC_INFO_0_MSDU_DROP
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
When set, REO shall drop this MSDU and not forward it to
any other ring...
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22
#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000
/* Description RX_MSDU_DESC_INFO_0_SA_IS_VALID
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates that OLE found a valid SA entry for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23
#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000
/* Description RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates an unsuccessful MAC source address search due
to the expiring of the search timer for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24
#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000
/* Description RX_MSDU_DESC_INFO_0_DA_IS_VALID
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates that OLE found a valid DA entry for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25
#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000
/* Description RX_MSDU_DESC_INFO_0_DA_IS_MCBC
Field Only valid if da_is_valid is set
Indicates the DA address was a Multicast of Broadcast
address for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26
#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000
/* Description RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates an unsuccessful MAC destination address search
due to the expiring of the search timer for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27
#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000
/* Description RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB
Passed on from 'RX_MSDU_END' TLV (only the MSB is
reported as the LSB is always zero)
Number of bytes padded to make sure that the L3 header
will always start of a Dword boundary
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB 28
#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK 0x10000000
/* Description RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL
Passed on from 'RX_ATTENTION' TLV
Indicates that the computed checksum did not match the
checksum in the TCP/UDP header.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB 29
#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
/* Description RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL
Passed on from 'RX_ATTENTION' TLV
Indicates that the computed checksum did not match the
checksum in the IP header.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB 30
#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK 0x40000000
/* Description RX_MSDU_DESC_INFO_0_RAW_MPDU
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set to 1 by RXOLE when it has not performed any 802.11
to Ethernet/Natvie WiFi header conversion on this MPDU.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB 31
#define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK 0x80000000
/* Description RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0
Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
Based on a register configuration in RXDMA, this field
will contain:
The offset in the address search table which matches the
MAC source address
OR
'sw_peer_id' from the address search entry corresponding
to the source address of the MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004
#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
/* Description RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV (one MSB is omitted)
Based on a register configuration in RXDMA, this field
will contain:
The index of the address search entry corresponding to
this MPDU (a value of 0xFFFF indicates an invalid AST index,
meaning that no AST entry was found or no AST search was
performed)
OR:
'sw_peer_id' from the address search entry corresponding
to this MPDU (in case of ndp or phy_err or
AST_based_lookup_valid == 0, this field will be set to 0)
<legal all>
*/
#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004
#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
/* Description RX_MSDU_DESC_INFO_1_FR_DS
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set if the 'from DS' bit is set in the frame control.
<legal all>
*/
#define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET 0x00000004
#define RX_MSDU_DESC_INFO_1_FR_DS_LSB 30
#define RX_MSDU_DESC_INFO_1_FR_DS_MASK 0x40000000
/* Description RX_MSDU_DESC_INFO_1_TO_DS
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set if the 'to DS' bit is set in the frame control.
<legal all>
*/
#define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET 0x00000004
#define RX_MSDU_DESC_INFO_1_TO_DS_LSB 31
#define RX_MSDU_DESC_INFO_1_TO_DS_MASK 0x80000000
#endif // _RX_MSDU_DESC_INFO_H_

680
hw/qca5018/rx_msdu_details.h Normal file
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@ -0,0 +1,680 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MSDU_DETAILS_H_
#define _RX_MSDU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#include "rx_msdu_desc_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info buffer_addr_info_details;
// 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
struct rx_msdu_details {
struct buffer_addr_info buffer_addr_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
};
/*
struct buffer_addr_info buffer_addr_info_details
Consumer: REO/SW
Producer: RXDMA
Details of the physical address of the buffer containing
an MSDU (or entire MPDU)
struct rx_msdu_desc_info rx_msdu_desc_info_details
Consumer: REO/SW
Producer: RXDMA
General information related to the MSDU that should be
passed on from RXDMA all the way to to the REO destination
ring.
*/
/* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
/* Description RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<enum 7 SW4_BM> This buffer shall be returned to the SW,
ring 4
<legal all>
*/
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE1:
The three most significant bits can have a special
meaning in case this struct is embedded in a TX_MPDU_DETAILS
STRUCT, and field transmit_bw_restriction is set
In case of NON punctured transmission:
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
In case of punctured transmission:
Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
Note: a punctured transmission is indicated by the
presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
TLV
NOTE 2:The five most significant bits can have a special
meaning in case this struct is embedded in an
RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
configured for passing on the additional info
from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
(FR56821). This is not supported in HastingsPrime, Pine or
Moselle.
Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
control field
Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
indicates MPDUs with a QoS control field.
<legal all>
*/
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
/* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
<enum 0 Not_first_msdu> This is not the first MSDU in
the MPDU.
<enum 1 first_msdu> This MSDU is the first one in the
MPDU.
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
Consumer: WBM/REO/SW/FW
Producer: RXDMA
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
<enum 0 Not_last_msdu> There are more MSDUs linked to
this MSDU that belongs to this MPDU
<enum 1 Last_msdu> this MSDU is the last one in the
MPDU. This setting is only allowed in combination with
'Msdu_continuation' set to 0. This implies that when an msdu
is spread out over multiple buffers and thus
msdu_continuation is set, only for the very last buffer of
the msdu, can the 'last_msdu_in_mpdu_flag' be set.
When both first_msdu_in_mpdu_flag and
last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
belongs to only contains a single MSDU.
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
When set, this MSDU buffer was not able to hold the
entire MSDU. The next buffer will therefor contain
additional information related to this MSDU.
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
Parsed from RX_MSDU_START TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the First
buffer used by MSDU.
Full MSDU length in bytes after decapsulation.
This field is still valid for MPDU frames without
A-MSDU. It still represents MSDU length after decapsulation
Or in case of RAW MPDUs, it indicates the length of the
entire MPDU (without FCS field)
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW2 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW3 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW4 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_sw5> Reo will push the frame
into the REO2SW5 ring (REO remaps this in chips without
REO2SW5 ring, e.g. Pine)
<enum 8 reo_destination_sw6> Reo will push the frame
into the REO2SW6 ring (REO remaps this in chips without
REO2SW6 ring, e.g. Pine)
<enum 9 reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
When set, REO shall drop this MSDU and not forward it to
any other ring...
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates that OLE found a valid SA entry for this MSDU
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates an unsuccessful MAC source address search due
to the expiring of the search timer for this MSDU
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates that OLE found a valid DA entry for this MSDU
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
Field Only valid if da_is_valid is set
Indicates the DA address was a Multicast of Broadcast
address for this MSDU
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
Parsed from RX_MSDU_END TLV . In the case MSDU spans
over multiple buffers, this field will be valid in the Last
buffer used by the MSDU
Indicates an unsuccessful MAC destination address search
due to the expiring of the search timer for this MSDU
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
Passed on from 'RX_MSDU_END' TLV (only the MSB is
reported as the LSB is always zero)
Number of bytes padded to make sure that the L3 header
will always start of a Dword boundary
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
Passed on from 'RX_ATTENTION' TLV
Indicates that the computed checksum did not match the
checksum in the TCP/UDP header.
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
Passed on from 'RX_ATTENTION' TLV
Indicates that the computed checksum did not match the
checksum in the IP header.
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set to 1 by RXOLE when it has not performed any 802.11
to Ethernet/Natvie WiFi header conversion on this MPDU.
<legal all>
*/
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
Based on a register configuration in RXDMA, this field
will contain:
The offset in the address search table which matches the
MAC source address
OR
'sw_peer_id' from the address search entry corresponding
to the source address of the MSDU
<legal all>
*/
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV (one MSB is omitted)
Based on a register configuration in RXDMA, this field
will contain:
The index of the address search entry corresponding to
this MPDU (a value of 0xFFFF indicates an invalid AST index,
meaning that no AST entry was found or no AST search was
performed)
OR:
'sw_peer_id' from the address search entry corresponding
to this MPDU (in case of ndp or phy_err or
AST_based_lookup_valid == 0, this field will be set to 0)
<legal all>
*/
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set if the 'from DS' bit is set in the frame control.
<legal all>
*/
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS
Passed on from 'RX_MPDU_INFO' structure in
'RX_MPDU_START' TLV
Set if the 'to DS' bit is set in the frame control.
<legal all>
*/
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
#endif // _RX_MSDU_DETAILS_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
#define _RX_PPDU_END_USER_STATS_EXT_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_rxpcu_classification_overview.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct rx_rxpcu_classification_overview rxpcu_classification_details;
// 1 fcs_ok_bitmap_95_64[31:0]
// 2 fcs_ok_bitmap_127_96[31:0]
// 3 fcs_ok_bitmap_159_128[31:0]
// 4 fcs_ok_bitmap_191_160[31:0]
// 5 fcs_ok_bitmap_223_192[31:0]
// 6 fcs_ok_bitmap_255_224[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7
struct rx_ppdu_end_user_stats_ext {
struct rx_rxpcu_classification_overview rxpcu_classification_details;
uint32_t fcs_ok_bitmap_95_64 : 32; //[31:0]
uint32_t fcs_ok_bitmap_127_96 : 32; //[31:0]
uint32_t fcs_ok_bitmap_159_128 : 32; //[31:0]
uint32_t fcs_ok_bitmap_191_160 : 32; //[31:0]
uint32_t fcs_ok_bitmap_223_192 : 32; //[31:0]
uint32_t fcs_ok_bitmap_255_224 : 32; //[31:0]
};
/*
struct rx_rxpcu_classification_overview rxpcu_classification_details
Details related to what RXPCU classification types of
MPDUs have been received
fcs_ok_bitmap_95_64
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_127_96
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_159_128
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_191_160
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_223_192
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_255_224
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
/* EXTERNAL REFERENCE : struct rx_rxpcu_classification_overview rxpcu_classification_details */
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS
When set, at least one Filter Pass MPDU has been
received. FCS might or might not have been passing.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK
When set, at least one Filter Pass MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED
When set, PPDU reception was aborted by the PHY
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0
<legal 0>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80
/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
/* Description RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004
#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008
#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c
#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010
#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014
#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018
#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff
#endif // _RX_PPDU_END_USER_STATS_EXT_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_PPDU_START_H_
#define _RX_PPDU_START_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 phy_ppdu_id[15:0], reserved_15[31:16]
// 1 sw_phy_meta_data[31:0]
// 2 ppdu_start_timestamp[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_PPDU_START 3
struct rx_ppdu_start {
uint32_t phy_ppdu_id : 16, //[15:0]
reserved_15 : 16; //[31:16]
uint32_t sw_phy_meta_data : 32; //[31:0]
uint32_t ppdu_start_timestamp : 32; //[31:0]
};
/*
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
reserved_15
Reserved
<legal 0>
sw_phy_meta_data
SW programmed Meta data provided by the PHY.
Can be used for SW to indicate the channel the device is
on.
ppdu_start_timestamp
Timestamp that indicates when the PPDU that contained
this MPDU started on the medium.
The timestamp is captured by the PHY and given to the
MAC in PHYRX_RSSI_LEGACY.ppdu_start_timestamp
<legal all>
*/
/* Description RX_PPDU_START_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0
#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff
/* Description RX_PPDU_START_0_RESERVED_15
Reserved
<legal 0>
*/
#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000
#define RX_PPDU_START_0_RESERVED_15_LSB 16
#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000
/* Description RX_PPDU_START_1_SW_PHY_META_DATA
SW programmed Meta data provided by the PHY.
Can be used for SW to indicate the channel the device is
on.
*/
#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004
#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0
#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff
/* Description RX_PPDU_START_2_PPDU_START_TIMESTAMP
Timestamp that indicates when the PPDU that contained
this MPDU started on the medium.
The timestamp is captured by the PHY and given to the
MAC in PHYRX_RSSI_LEGACY.ppdu_start_timestamp
<legal all>
*/
#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008
#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0
#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff
#endif // _RX_PPDU_START_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_PPDU_START_USER_INFO_H_
#define _RX_PPDU_START_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#include "receive_user_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-2 struct receive_user_info receive_user_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3
struct rx_ppdu_start_user_info {
struct receive_user_info receive_user_info_details;
};
/*
struct receive_user_info receive_user_info_details
Overview of receive parameters that the MAC needs to
prepend to every received MSDU/MPDU.
*/
/* EXTERNAL REFERENCE : struct receive_user_info receive_user_info_details */
/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI
RSSI for this user
Frequency domain RSSI measurement for this user. Based
on the channel estimate.
<legal all>
*/
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
*/
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC
When set, use STBC transmission rates
*/
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE
Indicates what type of reception this is.
<enum 0 reception_type_SU > Basic SU reception (not
part of OFDMA or MU-MIMO)
<enum 1 reception_type_MU_MIMO > This is related to
DL type of reception
<enum 2 reception_type_MU_OFDMA > This is related
to DL type of reception
<enum 3 reception_type_MU_OFDMA_MIMO > This is
related to DL type of reception
<enum 4 reception_type_UL_MU_MIMO > This is related
to UL type of reception
<enum 5 reception_type_UL_MU_OFDMA > This is
related to UL type of reception
<enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
related to UL type of reception
<legal 0-6>
*/
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS
For details, refer to MCS_TYPE description
<legal all>
*/
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI
Field only valid when pkt type is HT, VHT or HE.
<enum 0 gi_0_8_us > Legacy normal GI. Can also be
used for HE
<enum 1 gi_0_4_us > Legacy short GI. Can also be
used for HE
<enum 2 gi_1_6_us > HE related GI
<enum 3 gi_3_2_us > HE related GI
<legal 0 - 3>
*/
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH
Full receive Bandwidth
<enum 0 full_rx_bw_20_mhz>
<enum 1 full_rx_bw_40_mhz>
<enum 2 full_rx_bw_80_mhz>
<enum 3 full_rx_bw_160_mhz>
<legal 0-3>
*/
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0
/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP
Bitmap, with each bit indicating if the related spatial
stream is used for this STA
LSB related to SS 0
0: spatial stream not used for this reception
1: spatial stream used for this reception
<legal all>
*/
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION
Field only valid in case of OFDMA type receptions (DL
and UL)
Indicates the RU number associated with this user.
In case of reception where the transmission was DL MU
OFDMA, this field provides the RU pattern. Note that fields
ofdma_user_index and ofdma_content_channel are needed to
determine which RU (within a 40 MHz channel) was actually
assigned to this user, but this does not give info on which
40 MHz channel was assigned to this user. Please refer
DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for
this user.
In case of reception where the transmission was UL MU
OFDMA, PHY is recommended to insert the RU start index in
this field. Note that PHY may insert the RU width in
Reserved_2a[6:0].
<legal all>
*/
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX
Field only valid in the of DL MU OFDMA reception
The user number within the RU_allocation.
This is needed for SW to determine the exact RU position
within the reception.
<legal all>
*/
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000
/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL
Field only valid in the of DL MU OFDMA/MIMO reception
In case of DL MU reception, this field indicates the
content channel number where PHY found the RU information
for this user
This is needed for SW to determine the exact RU position
within the reception.
<enum 0 content_channel_1>
<enum 1 content_channel_2>
<legal all>
*/
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC
When set, use LDPC transmission rates were used.
<legal all>
*/
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001
/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH
In case of UL OFDMA reception, PHY is recommended to
insert the RU width
In Hastings80: was using Reserved_2a[6:0].
<legal 1 - 74>
*/
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe
/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A
<legal 0>
*/
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8
#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00
#endif // _RX_PPDU_START_USER_INFO_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 filter_pass_mpdus[0], filter_pass_mpdus_fcs_ok[1], monitor_direct_mpdus[2], monitor_direct_mpdus_fcs_ok[3], monitor_other_mpdus[4], monitor_other_mpdus_fcs_ok[5], phyrx_abort_received[6], reserved_0[15:7], phy_ppdu_id[31:16]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
struct rx_rxpcu_classification_overview {
uint32_t filter_pass_mpdus : 1, //[0]
filter_pass_mpdus_fcs_ok : 1, //[1]
monitor_direct_mpdus : 1, //[2]
monitor_direct_mpdus_fcs_ok : 1, //[3]
monitor_other_mpdus : 1, //[4]
monitor_other_mpdus_fcs_ok : 1, //[5]
phyrx_abort_received : 1, //[6]
reserved_0 : 9, //[15:7]
phy_ppdu_id : 16; //[31:16]
};
/*
filter_pass_mpdus
When set, at least one Filter Pass MPDU has been
received. FCS might or might not have been passing.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
filter_pass_mpdus_fcs_ok
When set, at least one Filter Pass MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
monitor_direct_mpdus
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
monitor_direct_mpdus_fcs_ok
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
monitor_other_mpdus
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
monitor_other_mpdus_fcs_ok
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
phyrx_abort_received
When set, PPDU reception was aborted by the PHY
<legal all>
reserved_0
<legal 0>
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS
When set, at least one Filter Pass MPDU has been
received. FCS might or might not have been passing.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK
When set, at least one Filter Pass MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
For MU UL, in TLVs RX_PPDU_END and
RX_PPDU_END_STATUS_DONE, this field is the OR of all the
users.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED
When set, PPDU reception was aborted by the PHY
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB 6
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0
<legal 0>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 7
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ff80
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000
#endif // _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_

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hw/qca5018/rx_timing_offset_info.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_TIMING_OFFSET_INFO_H_
#define _RX_TIMING_OFFSET_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 residual_phase_offset[11:0], reserved[31:12]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1
struct rx_timing_offset_info {
uint32_t residual_phase_offset : 12, //[11:0]
reserved : 20; //[31:12]
};
/*
residual_phase_offset
Cumulative reference frequency error at end of RX
<legal all>
reserved
<legal 0>
*/
/* Description RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET
Cumulative reference frequency error at end of RX
<legal all>
*/
#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000
#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB 0
#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
/* Description RX_TIMING_OFFSET_INFO_0_RESERVED
<legal 0>
*/
#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET 0x00000000
#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB 12
#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK 0xfffff000
#endif // _RX_TIMING_OFFSET_INFO_H_

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hw/qca5018/rxpt_classify_info.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RXPT_CLASSIFY_INFO_H_
#define _RXPT_CLASSIFY_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 reo_destination_indication[4:0], lmac_peer_id_msb[6:5], use_flow_id_toeplitz_clfy[7], pkt_selection_fp_ucast_data[8], pkt_selection_fp_mcast_data[9], pkt_selection_fp_1000[10], rxdma0_source_ring_selection[12:11], rxdma0_destination_ring_selection[14:13], reserved_0b[31:15]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
struct rxpt_classify_info {
uint32_t reo_destination_indication : 5, //[4:0]
lmac_peer_id_msb : 2, //[6:5]
use_flow_id_toeplitz_clfy : 1, //[7]
pkt_selection_fp_ucast_data : 1, //[8]
pkt_selection_fp_mcast_data : 1, //[9]
pkt_selection_fp_1000 : 1, //[10]
rxdma0_source_ring_selection : 2, //[12:11]
rxdma0_destination_ring_selection: 2, //[14:13]
reserved_0b : 17; //[31:15]
};
/*
reo_destination_indication
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW2 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW3 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW4 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_sw5> Reo will push the frame
into the REO2SW5 ring (REO remaps this in chips without
REO2SW5 ring, e.g. Pine)
<enum 8 reo_destination_sw6> Reo will push the frame
into the REO2SW6 ring (REO remaps this in chips without
REO2SW6 ring, e.g. Pine)
<enum 9 reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
lmac_peer_id_msb
If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
hash[3:0]} using the chosen Toeplitz hash from Common Parser
if flow search fails.
If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
's not 2'b00, Rx OLE uses a REO desination indication of
{lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
from Common Parser if flow search fails.
This LMAC/peer-based routing is not supported in
Hastings80 and HastingsPrime.
<legal all>
use_flow_id_toeplitz_clfy
Indication to Rx OLE to enable REO destination routing
based on the chosen Toeplitz hash from Common Parser, in
case flow search fails
<legal all>
pkt_selection_fp_ucast_data
Filter pass Unicast data frame (matching
rxpcu_filter_pass and sw_frame_group_Unicast_data) routing
selection
1'b0: source and destination rings are selected from the
RxOLE register settings for the packet type
1'b1: source ring and destination ring is selected from
the rxdma0_source_ring_selection and
rxdma0_destination_ring_selection fields in this STRUCT
<legal all>
pkt_selection_fp_mcast_data
Filter pass Multicast data frame (matching
rxpcu_filter_pass and sw_frame_group_Multicast_data) routing
selection
1'b0: source and destination rings are selected from the
RxOLE register settings for the packet type
1'b1: source ring and destination ring is selected from
the rxdma0_source_ring_selection and
rxdma0_destination_ring_selection fields in this STRUCT
<legal all>
pkt_selection_fp_1000
Filter pass BAR frame (matching rxpcu_filter_pass and
sw_frame_group_ctrl_1000) routing selection
1'b0: source and destination rings are selected from the
RxOLE register settings for the packet type
1'b1: source ring and destination ring is selected from
the rxdma0_source_ring_selection and
rxdma0_destination_ring_selection fields in this STRUCT
<legal all>
rxdma0_source_ring_selection
Field only valid when for the received frame type the
corresponding pkt_selection_fp_... bit is set
<enum 0 wbm2rxdma_buf_source_ring> The data buffer for
<enum 1 fw2rxdma_buf_source_ring> The data buffer for
this frame shall be sourced by fw2rxdma buffer source ring.
<enum 2 sw2rxdma_buf_source_ring> The data buffer for
this frame shall be sourced by sw2rxdma buffer source ring.
<enum 3 no_buffer_ring> The frame shall not be written
to any data buffer.
<legal all>
rxdma0_destination_ring_selection
Field only valid when for the received frame type the
corresponding pkt_selection_fp_... bit is set
<enum 0 rxdma_release_ring> RXDMA0 shall push the frame
to the Release ring. Effectively this means the frame needs
to be dropped.
<enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to
the FW ring.
<enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to
the SW ring.
<enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to
the REO entrance ring.
<legal all>
reserved_0b
<legal 0>
*/
/* Description RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW2 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW3 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW4 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_sw5> Reo will push the frame
into the REO2SW5 ring (REO remaps this in chips without
REO2SW5 ring, e.g. Pine)
<enum 8 reo_destination_sw6> Reo will push the frame
into the REO2SW6 ring (REO remaps this in chips without
REO2SW6 ring, e.g. Pine)
<enum 9 reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0
#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f
/* Description RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB
If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
hash[3:0]} using the chosen Toeplitz hash from Common Parser
if flow search fails.
If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
's not 2'b00, Rx OLE uses a REO desination indication of
{lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
from Common Parser if flow search fails.
This LMAC/peer-based routing is not supported in
Hastings80 and HastingsPrime.
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5
#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK 0x00000060
/* Description RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY
Indication to Rx OLE to enable REO destination routing
based on the chosen Toeplitz hash from Common Parser, in
case flow search fails
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA
Filter pass Unicast data frame (matching
rxpcu_filter_pass and sw_frame_group_Unicast_data) routing
selection
1'b0: source and destination rings are selected from the
RxOLE register settings for the packet type
1'b1: source ring and destination ring is selected from
the rxdma0_source_ring_selection and
rxdma0_destination_ring_selection fields in this STRUCT
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB 8
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA
Filter pass Multicast data frame (matching
rxpcu_filter_pass and sw_frame_group_Multicast_data) routing
selection
1'b0: source and destination rings are selected from the
RxOLE register settings for the packet type
1'b1: source ring and destination ring is selected from
the rxdma0_source_ring_selection and
rxdma0_destination_ring_selection fields in this STRUCT
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB 9
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000
Filter pass BAR frame (matching rxpcu_filter_pass and
sw_frame_group_ctrl_1000) routing selection
1'b0: source and destination rings are selected from the
RxOLE register settings for the packet type
1'b1: source ring and destination ring is selected from
the rxdma0_source_ring_selection and
rxdma0_destination_ring_selection fields in this STRUCT
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB 10
#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK 0x00000400
/* Description RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION
Field only valid when for the received frame type the
corresponding pkt_selection_fp_... bit is set
<enum 0 wbm2rxdma_buf_source_ring> The data buffer for
<enum 1 fw2rxdma_buf_source_ring> The data buffer for
this frame shall be sourced by fw2rxdma buffer source ring.
<enum 2 sw2rxdma_buf_source_ring> The data buffer for
this frame shall be sourced by sw2rxdma buffer source ring.
<enum 3 no_buffer_ring> The frame shall not be written
to any data buffer.
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB 11
#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
/* Description RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION
Field only valid when for the received frame type the
corresponding pkt_selection_fp_... bit is set
<enum 0 rxdma_release_ring> RXDMA0 shall push the frame
to the Release ring. Effectively this means the frame needs
to be dropped.
<enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to
the FW ring.
<enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to
the SW ring.
<enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to
the REO entrance ring.
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
/* Description RXPT_CLASSIFY_INFO_0_RESERVED_0B
<legal 0>
*/
#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB 15
#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK 0xffff8000
#endif // _RXPT_CLASSIFY_INFO_H_

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hw/qca5018/seq_hwio.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*********************************************************************************
*
* DESCRIPTION
* - This is an extension of standard msmhwio.h to support relative addressing
* scheme used in SCALe auto-generated sequences.
* - The objective of this new addressing scheme is enable the same C function
* definition to be applicable to multiple baseances of the same block.
* - Such code reuse is not feasible with the standard HWIO macros that use a
* absolute addressing scheme.
* - Compared to the standard HWIO macros, the new macros defined here take an
* additional parameter 'baseance offset'. So are the C functions generated
* by SCALe Autoseq from .seq inputs.
* - As such, macros defined in this file must be used with 'seq_msmhwiobase.h',
* 'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq.
* - Macros defined in this file leverage the lower-level macros from the
* standard 'msmhwio.h', and the two sets of macros are compatible.
*
********************************************************************************/
#ifndef __SEQ_H__
#define __SEQ_H__
#include "HALhwio.h"
/**** Register Ref Read ****/
#define SEQ_INH(base, regtype, reg) \
SEQ_##regtype##_INH(base, reg)
/**** Masked Register Read ****/
#define SEQ_INMH(base, regtype, reg, mask) \
SEQ_##regtype##_INMH(base, reg, mask)
/**** Ref Reg Field Read ****/
#define SEQ_INFH(base, regtype, reg, fld) \
(SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
/**** Ref Register Write ****/
#define SEQ_OUTH(base, regtype, reg, val) \
SEQ_##regtype##_OUTH(base, reg, val)
/**** Ref Register Masked Write ****/
#define SEQ_OUTMH(base, regtype, reg, mask, val) \
SEQ_##regtype##_OUTMH(base, reg, mask, val)
/**** Ref Register Field Write ****/
#define SEQ_OUTFH(base, regtype, reg, fld, val) \
SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
/**** seq_msg() ****
typedef enum {
DEBUG,
INFO,
WARNING,
ERROR,
FATAL
} SeverityLevel ;
void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... );
*/
/************ seq_wait() ************/
typedef enum {
SEC,
MS,
US,
NS
} SEQ_TimeUnit;
extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
/************ seq_poll() ************/
extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
#endif /* __SEQ_H__ */

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hw/qca5018/sw_xml_headers.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SW_XML_HEADERS_H_
#define _SW_XML_HEADERS_H_
#include "ack_report.h"
#include "addr_search_entry.h"
#include "buffer_addr_info.h"
#include "cce_rule.h"
#include "ce_dst_desc.h"
#include "ce_src_desc.h"
#include "ce_stat_desc.h"
#include "he_sig_a_mu_dl_info.h"
#include "he_sig_a_mu_ul_info.h"
#include "he_sig_a_su_info.h"
#include "he_sig_b1_mu_info.h"
#include "he_sig_b2_mu_info.h"
#include "he_sig_b2_ofdma_info.h"
#include "ht_sig_info.h"
#include "l_sig_a_info.h"
#include "l_sig_b_info.h"
#include "mactx_abort_request_info.h"
#include "mactx_prefetch_cv_bulk_user.h"
#include "mimo_control_info.h"
#include "mimo_control_info_l1.h"
#include "no_ack_report.h"
#include "pcu_ppdu_setup_end_info.h"
#include "pdg_response_rate_setting.h"
#include "peer_table_entry.h"
#include "phyrx_abort_request_info.h"
#include "phyrx_pkt_end_info.h"
#include "ppdu_rate_setting.h"
#include "prot_rate_setting.h"
#include "receive_rssi_info.h"
#include "receive_user_info.h"
#include "receive_user_info_l1.h"
#include "received_response_user_info.h"
#include "received_trigger_info_details.h"
#include "reo_destination_ring.h"
#include "reo_entrance_ring.h"
#include "reo_to_ppe_ring.h"
#include "response_rate_setting.h"
#include "rx_flow_search_entry.h"
#include "rx_location_info.h"
#include "rx_mpdu_desc_info.h"
#include "rx_mpdu_details.h"
#include "rx_mpdu_info.h"
#include "rx_mpdu_link.h"
#include "rx_mpdu_link_ptr.h"
#include "rx_msdu_desc_info.h"
#include "rx_msdu_details.h"
#include "rx_msdu_link.h"
#include "rx_peer_entry_details.h"
#include "rx_reo_queue.h"
#include "rx_reo_queue_ext.h"
#include "rx_reo_queue_reference.h"
#include "rx_rxpcu_classification_overview.h"
#include "rx_timing_offset_info.h"
#include "rxole_cce_classify_info.h"
#include "rxole_cce_info.h"
#include "rxole_cce_superrule.h"
#include "rxpt_classify_info.h"
#include "scheduler_cmd.h"
#include "service_info.h"
#include "sw_monitor_ring.h"
#include "sw_peer_info.h"
#include "tcl_cce_classify_info.h"
#include "tcl_cce_info.h"
#include "tcl_cce_superrule.h"
#include "tcl_compact_exit_ring.h"
#include "tcl_entrance_from_ppe_ring.h"
#include "tcl_exit_base.h"
#include "tcl_extended_exit_ring.h"
#include "tcl_regular_exit_ring.h"
#include "tcl_status_ring.h"
#include "tqm_entrance_ring.h"
#include "tx_flow_search_entry.h"
#include "tx_mpdu_details.h"
#include "tx_mpdu_link.h"
#include "tx_mpdu_link_ptr.h"
#include "tx_mpdu_queue_ext.h"
#include "tx_mpdu_queue_ext_ptr.h"
#include "tx_mpdu_queue_head.h"
#include "tx_msdu_details.h"
#include "tx_msdu_extension.h"
#include "tx_msdu_flow.h"
#include "tx_msdu_link.h"
#include "tx_msdu_link_entry_ptr.h"
#include "tx_puncture_pattern.h"
#include "tx_rate_stats_info.h"
#include "txpcu_buffer_basics.h"
#include "txpt_classify_info.h"
#include "uniform_descriptor_header.h"
#include "uniform_reo_cmd_header.h"
#include "uniform_reo_status_header.h"
#include "uniform_tqm_cmd_header.h"
#include "uniform_tqm_status_header.h"
#include "uplink_common_info.h"
#include "uplink_common_info_punc.h"
#include "uplink_user_setup_info.h"
#include "user_rate_setting.h"
#include "vht_sig_a_info.h"
#include "vht_sig_b_mu160_info.h"
#include "vht_sig_b_mu20_info.h"
#include "vht_sig_b_mu40_info.h"
#include "vht_sig_b_mu80_info.h"
#include "vht_sig_b_su160_info.h"
#include "vht_sig_b_su20_info.h"
#include "vht_sig_b_su40_info.h"
#include "vht_sig_b_su80_info.h"
#include "wbm_buffer_ring.h"
#include "wbm_link_descriptor_ring.h"
#include "wbm_release_ring.h"
#include "who_classify_info.h"
#include "macrx_abort_request_info.h"
#include "phytx_abort_request_info.h"
#include "abort_from_phyrx_details.h"
#include "coex_mac_nap.h"
#include "coex_rx_status.h"
#include "coex_status_broadcast.h"
#include "coex_tx_req.h"
#include "coex_tx_resp.h"
#include "coex_tx_status.h"
#include "coex_tx_stop_ctrl.h"
#include "crypto_status.h"
#include "expected_response.h"
#include "hwsch_rxpcu_mac_info_announcement.h"
#include "mactx_abort_request.h"
#include "mactx_bf_params_common.h"
#include "mactx_coex_phy_ctrl.h"
#include "mactx_delete_cv.h"
#include "mactx_expect_cbf_common.h"
#include "mactx_he_sig_a_mu_dl.h"
#include "mactx_he_sig_a_mu_ul.h"
#include "mactx_he_sig_a_su.h"
#include "mactx_he_sig_b1_mu.h"
#include "mactx_ht_sig.h"
#include "mactx_l_sig_a.h"
#include "mactx_l_sig_b.h"
#include "mactx_mu_uplink_common.h"
#include "mactx_mu_uplink_common_punc.h"
#include "mactx_other_transmit_info_dl_ofdma_tx.h"
#include "mactx_other_transmit_info_emuphy_setup.h"
#include "mactx_other_transmit_info_sch_details.h"
#include "mactx_phy_desc.h"
#include "mactx_phy_nap.h"
#include "mactx_pre_phy_desc.h"
#include "mactx_prefetch_cv.h"
#include "mactx_prefetch_cv_bulk.h"
#include "mactx_prefetch_cv_common.h"
#include "mactx_user_desc_common.h"
#include "mactx_vht_sig_a.h"
#include "mactx_vht_sig_b_su160.h"
#include "mactx_vht_sig_b_su20.h"
#include "mactx_vht_sig_b_su40.h"
#include "mactx_vht_sig_b_su80.h"
#include "obss_sr_info.h"
#include "ofdma_trigger_details.h"
#include "ole_buf_status.h"
#include "pcu_ppdu_setup_end.h"
#include "pcu_ppdu_setup_init.h"
#include "pcu_ppdu_setup_start.h"
#include "pdg_fes_setup.h"
#include "pdg_response.h"
#include "pdg_sw_mode_bw_start.h"
#include "pdg_tx_req.h"
#include "pdg_wait_for_mac_request.h"
#include "pdg_wait_for_phy_request.h"
#include "phyrx_cbf_read_request_ack.h"
#include "phyrx_generated_cbf_details.h"
#include "phyrx_he_sig_a_mu_dl.h"
#include "phyrx_he_sig_a_mu_ul.h"
#include "phyrx_he_sig_a_su.h"
#include "phyrx_he_sig_b1_mu.h"
#include "phyrx_ht_sig.h"
#include "phyrx_l_sig_a.h"
#include "phyrx_l_sig_b.h"
#include "phyrx_other_receive_info_108p_evm_details.h"
#include "phyrx_other_receive_info_evm_details.h"
#include "phyrx_other_receive_info_mu_rssi_common.h"
#include "phyrx_pkt_end.h"
#include "phyrx_rssi_ht.h"
#include "phyrx_rssi_legacy.h"
#include "phyrx_tx_start_timing.h"
#include "phyrx_vht_sig_a.h"
#include "phyrx_vht_sig_b_su160.h"
#include "phyrx_vht_sig_b_su20.h"
#include "phyrx_vht_sig_b_su40.h"
#include "phyrx_vht_sig_b_su80.h"
#include "received_response_info.h"
#include "received_response_info_part2.h"
#include "received_response_user_15_8.h"
#include "received_response_user_23_16.h"
#include "received_response_user_31_24.h"
#include "received_response_user_36_32.h"
#include "received_response_user_7_0.h"
#include "received_trigger_info.h"
#include "reo_descriptor_threshold_reached_status.h"
#include "reo_flush_cache.h"
#include "reo_flush_cache_status.h"
#include "reo_flush_queue.h"
#include "reo_flush_queue_status.h"
#include "reo_flush_timeout_list.h"
#include "reo_flush_timeout_list_status.h"
#include "reo_get_queue_stats.h"
#include "reo_get_queue_stats_status.h"
#include "reo_unblock_cache.h"
#include "reo_unblock_cache_status.h"
#include "reo_update_rx_reo_queue.h"
#include "reo_update_rx_reo_queue_status.h"
#include "response_end_status.h"
#include "response_start_status.h"
#include "rx_frame_bitmap_req.h"
#include "rx_pm_info.h"
#include "rx_ppdu_ack_report.h"
#include "rx_ppdu_end_status_done.h"
#include "rx_ppdu_no_ack_report.h"
#include "rx_ppdu_start.h"
#include "rx_preamble.h"
#include "rx_response_required_info.h"
#include "rx_ring_mask.h"
#include "rx_start_param.h"
#include "rx_trig_info.h"
#include "rxpcu_ppdu_end_info.h"
#include "rxpcu_setup.h"
#include "sch_coex_status.h"
#include "sch_wait_instr.h"
#include "sch_wait_instr_tx_path.h"
#include "scheduler_command_status.h"
#include "scheduler_rx_ppdu_no_response_status.h"
#include "scheduler_rx_sifs_response_trigger_status.h"
#include "scheduler_selfgen_response_status.h"
#include "scheduler_sw_msg_status.h"
#include "snoop_ppdu_end.h"
#include "snoop_ppdu_start.h"
#include "srp_info.h"
#include "tcl_data_cmd.h"
#include "tcl_gse_cmd.h"
#include "tqm_2_sch_mpdu_available.h"
#include "tqm_acked_mpdu_status.h"
#include "tqm_add_msdu_status.h"
#include "tqm_descriptor_threshold_reached_status.h"
#include "tqm_flow_empty_status.h"
#include "tqm_flow_not_empty_status.h"
#include "tqm_flush_cache.h"
#include "tqm_flush_cache_status.h"
#include "tqm_gen_mpdu_length_list.h"
#include "tqm_gen_mpdu_length_list_status.h"
#include "tqm_gen_mpdus.h"
#include "tqm_gen_mpdus_status.h"
#include "tqm_get_mpdu_head_info.h"
#include "tqm_get_mpdu_head_info_status.h"
#include "tqm_get_mpdu_queue_stats.h"
#include "tqm_get_mpdu_queue_stats_status.h"
#include "tqm_get_msdu_flow_stats.h"
#include "tqm_get_msdu_flow_stats_status.h"
#include "tqm_mpdu_queue_empty_status.h"
#include "tqm_remove_mpdu.h"
#include "tqm_remove_mpdu_status.h"
#include "tqm_remove_msdu.h"
#include "tqm_remove_msdu_status.h"
#include "tqm_sync_cmd.h"
#include "tqm_sync_cmd_status.h"
#include "tqm_threshold_drop_notification_status.h"
#include "tqm_unblock_cache.h"
#include "tqm_unblock_cache_status.h"
#include "tqm_update_tx_mpdu_count_status.h"
#include "tqm_update_tx_mpdu_queue_head.h"
#include "tqm_update_tx_mpdu_queue_head_status.h"
#include "tqm_update_tx_msdu_flow.h"
#include "tqm_update_tx_msdu_flow_status.h"
#include "tqm_write_cmd.h"
#include "tqm_write_cmd_status.h"
#include "tx_cbf_info.h"
#include "tx_data_sync.h"
#include "tx_fes_setup.h"
#include "tx_fes_status_end.h"
#include "tx_fes_status_prot.h"
#include "tx_fes_status_start.h"
#include "tx_fes_status_start_ppdu.h"
#include "tx_fes_status_start_prot.h"
#include "tx_flush_req.h"
#include "tx_loopback_setup.h"
#include "tx_puncture_setup.h"
#include "tx_sw_mode_setup.h"
#include "txpcu_buffer_status.h"
#include "who_terminate.h"
#include "data_to_time_config.h"
#include "mactx_bf_params_per_user.h"
#include "mactx_expect_cbf_per_user.h"
#include "mactx_he_sig_b2_mu.h"
#include "mactx_he_sig_b2_ofdma.h"
#include "mactx_mu_uplink_user_setup.h"
#include "mactx_mu_uplink_user_setup_punc.h"
#include "mactx_service.h"
#include "mactx_user_desc_per_user.h"
#include "mactx_vht_sig_b_mu160.h"
#include "mactx_vht_sig_b_mu20.h"
#include "mactx_vht_sig_b_mu40.h"
#include "mactx_vht_sig_b_mu80.h"
#include "mpdu_info.h"
#include "mpdu_info_bitmap.h"
#include "mpdu_limit.h"
#include "pcu_ppdu_setup_user.h"
#include "pdg_user_setup.h"
#include "phyrx_common_user_info.h"
#include "phyrx_he_sig_b2_mu.h"
#include "phyrx_he_sig_b2_ofdma.h"
#include "phyrx_other_receive_info_mu_rssi_user.h"
#include "phyrx_other_receive_info_ru_details.h"
#include "phyrx_user_info.h"
#include "phyrx_vht_sig_b_mu160.h"
#include "phyrx_vht_sig_b_mu20.h"
#include "phyrx_vht_sig_b_mu40.h"
#include "phyrx_vht_sig_b_mu80.h"
#include "rx_attention.h"
#include "rx_frame_bitmap_ack.h"
#include "rx_frameless_bar_details.h"
#include "rx_header.h"
#include "rx_mpdu_end.h"
#include "rx_mpdu_pcu_start.h"
#include "rx_mpdu_start.h"
#include "rx_msdu_end.h"
#include "rx_msdu_start.h"
#include "rx_peer_entry.h"
#include "rx_ppdu_end_user_stats.h"
#include "rx_ppdu_end_user_stats_ext.h"
#include "rx_ppdu_start_user_info.h"
#include "rxpcu_user_setup.h"
#include "rxpcu_user_setup_ext.h"
#include "snoop_mpdu_usr_dbg_info.h"
#include "snoop_mpdu_usr_stat_info.h"
#include "snoop_msdu_usr_dbg_info.h"
#include "tqm_acked_mpdu.h"
#include "tqm_update_tx_mpdu_count.h"
#include "tx_11ah_setup.h"
#include "tx_fes_status_ack_or_ba.h"
#include "tx_fes_status_user_ppdu.h"
#include "tx_fes_status_user_response.h"
#include "tx_mpdu_start.h"
#include "tx_msdu_start.h"
#include "tx_peer_entry.h"
#include "tx_queue_extension.h"
#include "tx_raw_or_native_frame_setup.h"
#include "txpcu_user_buffer_status.h"
#include "txpcu_user_setup.h"
#include "who_anchor_value.h"
#include "who_cce_info.h"
#include "who_commit_done.h"
#include "who_l2_llc.h"
#include "who_l3_checksum.h"
#include "who_l3_info.h"
#include "who_l4_checksum.h"
#include "who_l4_info.h"
#include "who_mesh_control.h"
#include "who_msdu_misc.h"
#include "who_packet_hdr.h"
#include "who_tso.h"
#include "who_wmac_header_pv0.h"
#include "who_wmac_header_pv1.h"
#include "who_wmac_iv.h"
#include "tlv_tag_def.h"
#include "mactx_cbf_data.h"
#include "mactx_cbf_done.h"
#include "mactx_cbf_start.h"
#include "mactx_data_resp.h"
#include "phyrx_abort_request.h"
#include "phyrx_cbf_data_resp.h"
#include "phyrx_data.h"
#include "phyrx_user_abort_notification.h"
#include "macrx_abort_request.h"
#include "macrx_cbf_data_request.h"
#include "macrx_cbf_read_request.h"
#include "macrx_chain_mask.h"
#include "macrx_expect_ndp_reception.h"
#include "macrx_freeze_capture_channel.h"
#include "macrx_req_implicit_fb.h"
#include "phytx_abort_request.h"
#include "phytx_bf_cv_loading_done.h"
#include "phytx_nap_ack.h"
#include "phytx_pkt_end.h"
#include "phytx_ppdu_header_info_request.h"
#include "phytx_request_ctrl_info.h"
#endif

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hw/qca5018/tcl_data_cmd.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TCL_GSE_CMD_H_
#define _TCL_GSE_CMD_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 control_buffer_addr_31_0[31:0]
// 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], index_search_en[15], cache_set_num[19:16], reserved_1a[31:20]
// 2 cmd_meta_data_31_0[31:0]
// 3 cmd_meta_data_63_32[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TCL_GSE_CMD 7
struct tcl_gse_cmd {
uint32_t control_buffer_addr_31_0 : 32; //[31:0]
uint32_t control_buffer_addr_39_32 : 8, //[7:0]
gse_ctrl : 4, //[11:8]
gse_sel : 1, //[12]
status_destination_ring_id : 1, //[13]
swap : 1, //[14]
index_search_en : 1, //[15]
cache_set_num : 4, //[19:16]
reserved_1a : 12; //[31:20]
uint32_t cmd_meta_data_31_0 : 32; //[31:0]
uint32_t cmd_meta_data_63_32 : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
control_buffer_addr_31_0
Address (lower 32 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
control_buffer_addr_39_32
Address (upper 8 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
gse_ctrl
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
gse_sel
Bit to select the ASE or FSE to do the operation mention
by GSE_ctrl bit
0: FSE select
1: ASE select
status_destination_ring_id
The TCL status ring to which the GSE status needs to be
send.
<enum 0 tcl_status_0_ring>
<enum 1 tcl_status_1_ring>
<legal all>
swap
Bit to enable byte swapping of contents of buffer
<enum 0 Byte_swap_disable >
<enum 1 byte_swap_enable >
<legal all>
index_search_en
When this bit is set to 1 control_buffer_addr[19:0] will
be considered as index of the AST or Flow table and GSE
commands will be executed accordingly on the entry pointed
by the index.
This feature is disabled by setting this bit to 0.
<enum 0 index_based_cmd_disable>
<enum 1 index_based_cmd_enable>
<legal all>
cache_set_num
Cache set number that should be used to cache the index
based search results, for address and flow search. This
value should be equal to value of cache_set_num for the
index that is issued in TCL_DATA_CMD during search index
based ASE or FSE. This field is valid for index based GSE
commands
<legal all>
reserved_1a
<legal 0>
cmd_meta_data_31_0
Meta data to be returned in the status descriptor
<legal all>
cmd_meta_data_63_32
Meta data to be returned in the status descriptor
<legal all>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
ring_id
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0
Address (lower 32 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
*/
#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0
#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32
Address (upper 8 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
*/
#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0
#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description TCL_GSE_CMD_1_GSE_CTRL
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
*/
#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004
#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8
#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00
/* Description TCL_GSE_CMD_1_GSE_SEL
Bit to select the ASE or FSE to do the operation mention
by GSE_ctrl bit
0: FSE select
1: ASE select
*/
#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004
#define TCL_GSE_CMD_1_GSE_SEL_LSB 12
#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000
/* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID
The TCL status ring to which the GSE status needs to be
send.
<enum 0 tcl_status_0_ring>
<enum 1 tcl_status_1_ring>
<legal all>
*/
#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13
#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000
/* Description TCL_GSE_CMD_1_SWAP
Bit to enable byte swapping of contents of buffer
<enum 0 Byte_swap_disable >
<enum 1 byte_swap_enable >
<legal all>
*/
#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004
#define TCL_GSE_CMD_1_SWAP_LSB 14
#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000
/* Description TCL_GSE_CMD_1_INDEX_SEARCH_EN
When this bit is set to 1 control_buffer_addr[19:0] will
be considered as index of the AST or Flow table and GSE
commands will be executed accordingly on the entry pointed
by the index.
This feature is disabled by setting this bit to 0.
<enum 0 index_based_cmd_disable>
<enum 1 index_based_cmd_enable>
<legal all>
*/
#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004
#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15
#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000
/* Description TCL_GSE_CMD_1_CACHE_SET_NUM
Cache set number that should be used to cache the index
based search results, for address and flow search. This
value should be equal to value of cache_set_num for the
index that is issued in TCL_DATA_CMD during search index
based ASE or FSE. This field is valid for index based GSE
commands
<legal all>
*/
#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004
#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16
#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000
/* Description TCL_GSE_CMD_1_RESERVED_1A
<legal 0>
*/
#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004
#define TCL_GSE_CMD_1_RESERVED_1A_LSB 20
#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000
/* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0
Meta data to be returned in the status descriptor
<legal all>
*/
#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008
#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0
#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff
/* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32
Meta data to be returned in the status descriptor
<legal all>
*/
#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c
#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0
#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff
/* Description TCL_GSE_CMD_4_RESERVED_4A
<legal 0>
*/
#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010
#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0
#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff
/* Description TCL_GSE_CMD_5_RESERVED_5A
<legal 0>
*/
#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014
#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0
#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff
/* Description TCL_GSE_CMD_6_RESERVED_6A
<legal 0>
*/
#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018
#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0
#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff
/* Description TCL_GSE_CMD_6_RING_ID
Helps with debugging when dumping ring contents.
<legal all>
*/
#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018
#define TCL_GSE_CMD_6_RING_ID_LSB 20
#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000
/* Description TCL_GSE_CMD_6_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28
#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000
#endif // _TCL_GSE_CMD_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TCL_STATUS_RING_H_
#define _TCL_STATUS_RING_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], index_search_en[7], msdu_cnt_n[31:8]
// 1 msdu_byte_cnt_n[31:0]
// 2 msdu_timestmp_n[31:0]
// 3 cmd_meta_data_31_0[31:0]
// 4 cmd_meta_data_63_32[31:0]
// 5 hash_indx_val[19:0], cache_set_num[23:20], reserved_5a[31:24]
// 6 reserved_6a[31:0]
// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TCL_STATUS_RING 8
struct tcl_status_ring {
uint32_t gse_ctrl : 4, //[3:0]
ase_fse_sel : 1, //[4]
cache_op_res : 2, //[6:5]
index_search_en : 1, //[7]
msdu_cnt_n : 24; //[31:8]
uint32_t msdu_byte_cnt_n : 32; //[31:0]
uint32_t msdu_timestmp_n : 32; //[31:0]
uint32_t cmd_meta_data_31_0 : 32; //[31:0]
uint32_t cmd_meta_data_63_32 : 32; //[31:0]
uint32_t hash_indx_val : 20, //[19:0]
cache_set_num : 4, //[23:20]
reserved_5a : 8; //[31:24]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
gse_ctrl
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
ase_fse_sel
Search Engine for which operation is done.
1'b0: Address Search Engine Result
1'b1: Flow Search Engine result
cache_op_res
Cache operation result. Following are results of cache
operation.
<enum 0 op_done> Operation successful
<enum 1 not_fnd> Entry not found in Table
<enum 2 timeout_er> Timeout Error
<legal 0-2>
index_search_en
When this bit is set to 1 control_buffer_addr[19:0] will
be considered as index of the AST or Flow table and GSE
commands will be executed accordingly on the entry pointed
by the index.
This feature is disabled by setting this bit to 0.
<enum 0 index_based_cmd_disable>
<enum 1 index_based_cmd_enable>
<legal all>
msdu_cnt_n
MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
4'b1000
msdu_byte_cnt_n
MSDU byte count for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
msdu_timestmp_n
MSDU timestamp for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
cmd_meta_data_31_0
Meta data from input ring
<legal all>
cmd_meta_data_63_32
Meta data from input ring
<legal all>
hash_indx_val
Hash value of the entry in table in case of search
failed or search disable.
<legal all>
cache_set_num
Cache set number copied from TCL_GSE_CMD
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
ring_id
The buffer pointer ring ID.
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description TCL_STATUS_RING_0_GSE_CTRL
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
*/
#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000
#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0
#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f
/* Description TCL_STATUS_RING_0_ASE_FSE_SEL
Search Engine for which operation is done.
1'b0: Address Search Engine Result
1'b1: Flow Search Engine result
*/
#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000
#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4
#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010
/* Description TCL_STATUS_RING_0_CACHE_OP_RES
Cache operation result. Following are results of cache
operation.
<enum 0 op_done> Operation successful
<enum 1 not_fnd> Entry not found in Table
<enum 2 timeout_er> Timeout Error
<legal 0-2>
*/
#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000
#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5
#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060
/* Description TCL_STATUS_RING_0_INDEX_SEARCH_EN
When this bit is set to 1 control_buffer_addr[19:0] will
be considered as index of the AST or Flow table and GSE
commands will be executed accordingly on the entry pointed
by the index.
This feature is disabled by setting this bit to 0.
<enum 0 index_based_cmd_disable>
<enum 1 index_based_cmd_enable>
<legal all>
*/
#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000
#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7
#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080
/* Description TCL_STATUS_RING_0_MSDU_CNT_N
MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
4'b1000
*/
#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000
#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8
#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00
/* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N
MSDU byte count for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
*/
#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004
#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0
#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff
/* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N
MSDU timestamp for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
*/
#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008
#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0
#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff
/* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0
Meta data from input ring
<legal all>
*/
#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c
#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0
#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff
/* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32
Meta data from input ring
<legal all>
*/
#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010
#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0
#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff
/* Description TCL_STATUS_RING_5_HASH_INDX_VAL
Hash value of the entry in table in case of search
failed or search disable.
<legal all>
*/
#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014
#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0
#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff
/* Description TCL_STATUS_RING_5_CACHE_SET_NUM
Cache set number copied from TCL_GSE_CMD
*/
#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014
#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20
#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000
/* Description TCL_STATUS_RING_5_RESERVED_5A
<legal 0>
*/
#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014
#define TCL_STATUS_RING_5_RESERVED_5A_LSB 24
#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000
/* Description TCL_STATUS_RING_6_RESERVED_6A
<legal 0>
*/
#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018
#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0
#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff
/* Description TCL_STATUS_RING_7_RESERVED_7A
<legal 0>
*/
#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c
#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0
#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff
/* Description TCL_STATUS_RING_7_RING_ID
The buffer pointer ring ID.
Helps with debugging when dumping ring contents.
<legal all>
*/
#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c
#define TCL_STATUS_RING_7_RING_ID_LSB 20
#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000
/* Description TCL_STATUS_RING_7_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28
#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000
#endif // _TCL_STATUS_RING_H_

75
hw/qca5018/tlv_hdr.h Normal file
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@ -0,0 +1,75 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TLV_HDR_H_
#define _TLV_HDR_H_
#if !defined(__ASSEMBLER__)
#endif
struct tlv_usr_16_hdr {
volatile uint16_t tlv_cflg_reserved : 1,
tlv_tag : 5,
tlv_len : 4,
tlv_usrid : 6;
};
struct tlv_16_hdr {
volatile uint16_t tlv_cflg_reserved : 1,
tlv_tag : 5,
tlv_len : 4,
tlv_reserved : 6;
};
struct tlv_usr_32_hdr {
volatile uint32_t tlv_cflg_reserved : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_usrid : 6;
};
struct tlv_32_hdr {
volatile uint32_t tlv_cflg_reserved : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_reserved : 6;
};
struct tlv_usr_42_hdr {
volatile uint64_t tlv_compression : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_usrid : 6,
tlv_reserved : 10,
pad_42to64_bit : 22;
};
struct tlv_42_hdr {
volatile uint64_t tlv_compression : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_reserved : 16,
pad_42to64_bit : 22;
};
struct tlv_usr_c_42_hdr {
volatile uint64_t tlv_compression : 1,
tlv_ctag : 3,
tlv_usrid : 6,
tlv_cdata : 32,
pad_42to64_bit : 22;
};
#endif

511
hw/qca5018/tlv_tag_def.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TLV_TAG_DEF_
#define _TLV_TAG_DEF_
typedef enum {
WIFIMACTX_CBF_START_E = 0 /* 0x0 */,
WIFIPHYRX_DATA_E = 1 /* 0x1 */,
WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */,
WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */,
WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */,
WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */,
WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */,
WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */,
WIFIMACRX_CBF_READ_REQUEST_E = 8 /* 0x8 */,
WIFIMACRX_CBF_DATA_REQUEST_E = 9 /* 0x9 */,
WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 /* 0xa */,
WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 /* 0xb */,
WIFIMACRX_NDP_TIMEOUT_E = 12 /* 0xc */,
WIFIMACRX_ABORT_ACK_E = 13 /* 0xd */,
WIFIMACRX_REQ_IMPLICIT_FB_E = 14 /* 0xe */,
WIFIMACRX_CHAIN_MASK_E = 15 /* 0xf */,
WIFIMACRX_NAP_USER_E = 16 /* 0x10 */,
WIFIMACRX_ABORT_REQUEST_E = 17 /* 0x11 */,
WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 /* 0x12 */,
WIFIPHYTX_ABORT_ACK_E = 19 /* 0x13 */,
WIFIPHYTX_ABORT_REQUEST_E = 20 /* 0x14 */,
WIFIPHYTX_PKT_END_E = 21 /* 0x15 */,
WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 /* 0x16 */,
WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 /* 0x17 */,
WIFIPHYTX_DATA_REQUEST_E = 24 /* 0x18 */,
WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 /* 0x19 */,
WIFIPHYTX_NAP_ACK_E = 26 /* 0x1a */,
WIFIPHYTX_NAP_DONE_E = 27 /* 0x1b */,
WIFIPHYTX_OFF_ACK_E = 28 /* 0x1c */,
WIFIPHYTX_ON_ACK_E = 29 /* 0x1d */,
WIFIPHYTX_SYNTH_OFF_ACK_E = 30 /* 0x1e */,
WIFIPHYTX_DEBUG16_E = 31 /* 0x1f */,
WIFIMACTX_ABORT_REQUEST_E = 32 /* 0x20 */,
WIFIMACTX_ABORT_ACK_E = 33 /* 0x21 */,
WIFIMACTX_PKT_END_E = 34 /* 0x22 */,
WIFIMACTX_PRE_PHY_DESC_E = 35 /* 0x23 */,
WIFIMACTX_BF_PARAMS_COMMON_E = 36 /* 0x24 */,
WIFIMACTX_BF_PARAMS_PER_USER_E = 37 /* 0x25 */,
WIFIMACTX_PREFETCH_CV_E = 38 /* 0x26 */,
WIFIMACTX_USER_DESC_COMMON_E = 39 /* 0x27 */,
WIFIMACTX_USER_DESC_PER_USER_E = 40 /* 0x28 */,
WIFIEXAMPLE_USER_TLV_16_E = 41 /* 0x29 */,
WIFIEXAMPLE_TLV_16_E = 42 /* 0x2a */,
WIFIMACTX_PHY_OFF_E = 43 /* 0x2b */,
WIFIMACTX_PHY_ON_E = 44 /* 0x2c */,
WIFIMACTX_SYNTH_OFF_E = 45 /* 0x2d */,
WIFIMACTX_EXPECT_CBF_COMMON_E = 46 /* 0x2e */,
WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 /* 0x2f */,
WIFIMACTX_PHY_DESC_E = 48 /* 0x30 */,
WIFIMACTX_L_SIG_A_E = 49 /* 0x31 */,
WIFIMACTX_L_SIG_B_E = 50 /* 0x32 */,
WIFIMACTX_HT_SIG_E = 51 /* 0x33 */,
WIFIMACTX_VHT_SIG_A_E = 52 /* 0x34 */,
WIFIMACTX_VHT_SIG_B_SU20_E = 53 /* 0x35 */,
WIFIMACTX_VHT_SIG_B_SU40_E = 54 /* 0x36 */,
WIFIMACTX_VHT_SIG_B_SU80_E = 55 /* 0x37 */,
WIFIMACTX_VHT_SIG_B_SU160_E = 56 /* 0x38 */,
WIFIMACTX_VHT_SIG_B_MU20_E = 57 /* 0x39 */,
WIFIMACTX_VHT_SIG_B_MU40_E = 58 /* 0x3a */,
WIFIMACTX_VHT_SIG_B_MU80_E = 59 /* 0x3b */,
WIFIMACTX_VHT_SIG_B_MU160_E = 60 /* 0x3c */,
WIFIMACTX_SERVICE_E = 61 /* 0x3d */,
WIFIMACTX_HE_SIG_A_SU_E = 62 /* 0x3e */,
WIFIMACTX_HE_SIG_A_MU_DL_E = 63 /* 0x3f */,
WIFIMACTX_HE_SIG_A_MU_UL_E = 64 /* 0x40 */,
WIFIMACTX_HE_SIG_B1_MU_E = 65 /* 0x41 */,
WIFIMACTX_HE_SIG_B2_MU_E = 66 /* 0x42 */,
WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 /* 0x43 */,
WIFIMACTX_DELETE_CV_E = 68 /* 0x44 */,
WIFIMACTX_MU_UPLINK_COMMON_E = 69 /* 0x45 */,
WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 /* 0x46 */,
WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 /* 0x47 */,
WIFIMACTX_PHY_NAP_E = 72 /* 0x48 */,
WIFIMACTX_DEBUG_E = 73 /* 0x49 */,
WIFIPHYRX_ABORT_ACK_E = 74 /* 0x4a */,
WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 /* 0x4b */,
WIFIPHYRX_RSSI_LEGACY_E = 76 /* 0x4c */,
WIFIPHYRX_RSSI_HT_E = 77 /* 0x4d */,
WIFIPHYRX_USER_INFO_E = 78 /* 0x4e */,
WIFIPHYRX_PKT_END_E = 79 /* 0x4f */,
WIFIPHYRX_DEBUG_E = 80 /* 0x50 */,
WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 /* 0x51 */,
WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 /* 0x52 */,
WIFIPHYRX_L_SIG_A_E = 83 /* 0x53 */,
WIFIPHYRX_L_SIG_B_E = 84 /* 0x54 */,
WIFIPHYRX_HT_SIG_E = 85 /* 0x55 */,
WIFIPHYRX_VHT_SIG_A_E = 86 /* 0x56 */,
WIFIPHYRX_VHT_SIG_B_SU20_E = 87 /* 0x57 */,
WIFIPHYRX_VHT_SIG_B_SU40_E = 88 /* 0x58 */,
WIFIPHYRX_VHT_SIG_B_SU80_E = 89 /* 0x59 */,
WIFIPHYRX_VHT_SIG_B_SU160_E = 90 /* 0x5a */,
WIFIPHYRX_VHT_SIG_B_MU20_E = 91 /* 0x5b */,
WIFIPHYRX_VHT_SIG_B_MU40_E = 92 /* 0x5c */,
WIFIPHYRX_VHT_SIG_B_MU80_E = 93 /* 0x5d */,
WIFIPHYRX_VHT_SIG_B_MU160_E = 94 /* 0x5e */,
WIFIPHYRX_HE_SIG_A_SU_E = 95 /* 0x5f */,
WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 /* 0x60 */,
WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 /* 0x61 */,
WIFIPHYRX_HE_SIG_B1_MU_E = 98 /* 0x62 */,
WIFIPHYRX_HE_SIG_B2_MU_E = 99 /* 0x63 */,
WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 /* 0x64 */,
WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 /* 0x65 */,
WIFIPHYRX_COMMON_USER_INFO_E = 102 /* 0x66 */,
WIFIPHYRX_DATA_DONE_E = 103 /* 0x67 */,
WIFIRECEIVE_RSSI_INFO_E = 104 /* 0x68 */,
WIFIRECEIVE_USER_INFO_E = 105 /* 0x69 */,
WIFIMIMO_CONTROL_INFO_E = 106 /* 0x6a */,
WIFIRX_LOCATION_INFO_E = 107 /* 0x6b */,
WIFICOEX_TX_REQ_E = 108 /* 0x6c */,
WIFIDUMMY_E = 109 /* 0x6d */,
WIFIRX_TIMING_OFFSET_INFO_E = 110 /* 0x6e */,
WIFIEXAMPLE_TLV_32_NAME_E = 111 /* 0x6f */,
WIFIMPDU_LIMIT_E = 112 /* 0x70 */,
WIFINA_LENGTH_END_E = 113 /* 0x71 */,
WIFIOLE_BUF_STATUS_E = 114 /* 0x72 */,
WIFIPCU_PPDU_SETUP_DONE_E = 115 /* 0x73 */,
WIFIPCU_PPDU_SETUP_END_E = 116 /* 0x74 */,
WIFIPCU_PPDU_SETUP_INIT_E = 117 /* 0x75 */,
WIFIPCU_PPDU_SETUP_START_E = 118 /* 0x76 */,
WIFIPDG_FES_SETUP_E = 119 /* 0x77 */,
WIFIPDG_RESPONSE_E = 120 /* 0x78 */,
WIFIPDG_TX_REQ_E = 121 /* 0x79 */,
WIFISCH_WAIT_INSTR_E = 122 /* 0x7a */,
WIFISCHEDULER_TLV_E = 123 /* 0x7b */,
WIFITQM_FLOW_EMPTY_STATUS_E = 124 /* 0x7c */,
WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 /* 0x7d */,
WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 /* 0x7e */,
WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 /* 0x7f */,
WIFITQM_GEN_MPDUS_E = 128 /* 0x80 */,
WIFITQM_GEN_MPDUS_STATUS_E = 129 /* 0x81 */,
WIFITQM_REMOVE_MPDU_E = 130 /* 0x82 */,
WIFITQM_REMOVE_MPDU_STATUS_E = 131 /* 0x83 */,
WIFITQM_REMOVE_MSDU_E = 132 /* 0x84 */,
WIFITQM_REMOVE_MSDU_STATUS_E = 133 /* 0x85 */,
WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 /* 0x86 */,
WIFITQM_WRITE_CMD_E = 135 /* 0x87 */,
WIFIOFDMA_TRIGGER_DETAILS_E = 136 /* 0x88 */,
WIFITX_DATA_E = 137 /* 0x89 */,
WIFITX_FES_SETUP_E = 138 /* 0x8a */,
WIFIRX_PACKET_E = 139 /* 0x8b */,
WIFIEXPECTED_RESPONSE_E = 140 /* 0x8c */,
WIFITX_MPDU_END_E = 141 /* 0x8d */,
WIFITX_MPDU_START_E = 142 /* 0x8e */,
WIFITX_MSDU_END_E = 143 /* 0x8f */,
WIFITX_MSDU_START_E = 144 /* 0x90 */,
WIFITX_SW_MODE_SETUP_E = 145 /* 0x91 */,
WIFITXPCU_BUFFER_STATUS_E = 146 /* 0x92 */,
WIFITXPCU_USER_BUFFER_STATUS_E = 147 /* 0x93 */,
WIFIDATA_TO_TIME_CONFIG_E = 148 /* 0x94 */,
WIFIEXAMPLE_USER_TLV_32_E = 149 /* 0x95 */,
WIFIMPDU_INFO_E = 150 /* 0x96 */,
WIFIPDG_USER_SETUP_E = 151 /* 0x97 */,
WIFITX_11AH_SETUP_E = 152 /* 0x98 */,
WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 /* 0x99 */,
WIFITX_PEER_ENTRY_E = 154 /* 0x9a */,
WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */,
WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */,
WIFIPCU_PPDU_SETUP_END_INFO_E = 157 /* 0x9d */,
WIFIPPDU_RATE_SETTING_E = 158 /* 0x9e */,
WIFIPROT_RATE_SETTING_E = 159 /* 0x9f */,
WIFIRX_MPDU_DETAILS_E = 160 /* 0xa0 */,
WIFIEXAMPLE_USER_TLV_42_E = 161 /* 0xa1 */,
WIFIRX_MSDU_LINK_E = 162 /* 0xa2 */,
WIFIRX_REO_QUEUE_E = 163 /* 0xa3 */,
WIFIADDR_SEARCH_ENTRY_E = 164 /* 0xa4 */,
WIFISCHEDULER_CMD_E = 165 /* 0xa5 */,
WIFITX_FLUSH_E = 166 /* 0xa6 */,
WIFITQM_ENTRANCE_RING_E = 167 /* 0xa7 */,
WIFITX_DATA_WORD_E = 168 /* 0xa8 */,
WIFITX_MPDU_DETAILS_E = 169 /* 0xa9 */,
WIFITX_MPDU_LINK_E = 170 /* 0xaa */,
WIFITX_MPDU_LINK_PTR_E = 171 /* 0xab */,
WIFITX_MPDU_QUEUE_HEAD_E = 172 /* 0xac */,
WIFITX_MPDU_QUEUE_EXT_E = 173 /* 0xad */,
WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 /* 0xae */,
WIFITX_MSDU_DETAILS_E = 175 /* 0xaf */,
WIFITX_MSDU_EXTENSION_E = 176 /* 0xb0 */,
WIFITX_MSDU_FLOW_E = 177 /* 0xb1 */,
WIFITX_MSDU_LINK_E = 178 /* 0xb2 */,
WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 /* 0xb3 */,
WIFIRESPONSE_RATE_SETTING_E = 180 /* 0xb4 */,
WIFITXPCU_BUFFER_BASICS_E = 181 /* 0xb5 */,
WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 /* 0xb6 */,
WIFIUNIFORM_TQM_CMD_HEADER_E = 183 /* 0xb7 */,
WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 /* 0xb8 */,
WIFIUSER_RATE_SETTING_E = 185 /* 0xb9 */,
WIFIWBM_BUFFER_RING_E = 186 /* 0xba */,
WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 /* 0xbb */,
WIFIWBM_RELEASE_RING_E = 188 /* 0xbc */,
WIFITX_FLUSH_REQ_E = 189 /* 0xbd */,
WIFIRX_MSDU_DETAILS_E = 190 /* 0xbe */,
WIFITQM_WRITE_CMD_STATUS_E = 191 /* 0xbf */,
WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 /* 0xc0 */,
WIFITQM_GET_MSDU_FLOW_STATS_E = 193 /* 0xc1 */,
WIFIEXAMPLE_USER_CTLV_32_E = 194 /* 0xc2 */,
WIFITX_FES_STATUS_START_E = 195 /* 0xc3 */,
WIFITX_FES_STATUS_USER_PPDU_E = 196 /* 0xc4 */,
WIFITX_FES_STATUS_USER_RESPONSE_E = 197 /* 0xc5 */,
WIFITX_FES_STATUS_END_E = 198 /* 0xc6 */,
WIFIRX_TRIG_INFO_E = 199 /* 0xc7 */,
WIFIRXPCU_TX_SETUP_CLEAR_E = 200 /* 0xc8 */,
WIFIRX_FRAME_BITMAP_REQ_E = 201 /* 0xc9 */,
WIFIRX_FRAME_BITMAP_ACK_E = 202 /* 0xca */,
WIFICOEX_RX_STATUS_E = 203 /* 0xcb */,
WIFIRX_START_PARAM_E = 204 /* 0xcc */,
WIFIRX_PPDU_START_E = 205 /* 0xcd */,
WIFIRX_PPDU_END_E = 206 /* 0xce */,
WIFIRX_MPDU_START_E = 207 /* 0xcf */,
WIFIRX_MPDU_END_E = 208 /* 0xd0 */,
WIFIRX_MSDU_START_E = 209 /* 0xd1 */,
WIFIRX_MSDU_END_E = 210 /* 0xd2 */,
WIFIRX_ATTENTION_E = 211 /* 0xd3 */,
WIFIRECEIVED_RESPONSE_INFO_E = 212 /* 0xd4 */,
WIFIRX_PHY_SLEEP_E = 213 /* 0xd5 */,
WIFIRX_HEADER_E = 214 /* 0xd6 */,
WIFIRX_PEER_ENTRY_E = 215 /* 0xd7 */,
WIFIRX_FLUSH_E = 216 /* 0xd8 */,
WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 /* 0xd9 */,
WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 /* 0xda */,
WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 /* 0xdb */,
WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 /* 0xdc */,
WIFITX_CBF_INFO_E = 221 /* 0xdd */,
WIFIPCU_PPDU_SETUP_USER_E = 222 /* 0xde */,
WIFIRX_MPDU_PCU_START_E = 223 /* 0xdf */,
WIFIRX_PM_INFO_E = 224 /* 0xe0 */,
WIFIRX_USER_PPDU_END_E = 225 /* 0xe1 */,
WIFIRX_PRE_PPDU_START_E = 226 /* 0xe2 */,
WIFIRX_PREAMBLE_E = 227 /* 0xe3 */,
WIFITX_FES_SETUP_COMPLETE_E = 228 /* 0xe4 */,
WIFITX_LAST_MPDU_FETCHED_E = 229 /* 0xe5 */,
WIFITXDMA_STOP_REQUEST_E = 230 /* 0xe6 */,
WIFIRXPCU_SETUP_E = 231 /* 0xe7 */,
WIFIRXPCU_USER_SETUP_E = 232 /* 0xe8 */,
WIFITX_FES_STATUS_ACK_OR_BA_E = 233 /* 0xe9 */,
WIFITQM_ACKED_MPDU_E = 234 /* 0xea */,
WIFICOEX_TX_RESP_E = 235 /* 0xeb */,
WIFICOEX_TX_STATUS_E = 236 /* 0xec */,
WIFIMACTX_COEX_PHY_CTRL_E = 237 /* 0xed */,
WIFICOEX_STATUS_BROADCAST_E = 238 /* 0xee */,
WIFIRESPONSE_START_STATUS_E = 239 /* 0xef */,
WIFIRESPONSE_END_STATUS_E = 240 /* 0xf0 */,
WIFICRYPTO_STATUS_E = 241 /* 0xf1 */,
WIFIRECEIVED_TRIGGER_INFO_E = 242 /* 0xf2 */,
WIFIREO_ENTRANCE_RING_E = 243 /* 0xf3 */,
WIFIRX_MPDU_LINK_E = 244 /* 0xf4 */,
WIFICOEX_TX_STOP_CTRL_E = 245 /* 0xf5 */,
WIFIRX_PPDU_ACK_REPORT_E = 246 /* 0xf6 */,
WIFIRX_PPDU_NO_ACK_REPORT_E = 247 /* 0xf7 */,
WIFISCH_COEX_STATUS_E = 248 /* 0xf8 */,
WIFISCHEDULER_COMMAND_STATUS_E = 249 /* 0xf9 */,
WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 /* 0xfa */,
WIFITX_FES_STATUS_PROT_E = 251 /* 0xfb */,
WIFITX_FES_STATUS_START_PPDU_E = 252 /* 0xfc */,
WIFITX_FES_STATUS_START_PROT_E = 253 /* 0xfd */,
WIFITXPCU_PHYTX_DEBUG32_E = 254 /* 0xfe */,
WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 /* 0xff */,
WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 /* 0x100 */,
WIFIWHO_ANCHOR_OFFSET_E = 257 /* 0x101 */,
WIFIWHO_ANCHOR_VALUE_E = 258 /* 0x102 */,
WIFIWHO_CCE_INFO_E = 259 /* 0x103 */,
WIFIWHO_COMMIT_E = 260 /* 0x104 */,
WIFIWHO_COMMIT_DONE_E = 261 /* 0x105 */,
WIFIWHO_FLUSH_E = 262 /* 0x106 */,
WIFIWHO_L2_LLC_E = 263 /* 0x107 */,
WIFIWHO_L2_PAYLOAD_E = 264 /* 0x108 */,
WIFIWHO_L3_CHECKSUM_E = 265 /* 0x109 */,
WIFIWHO_L3_INFO_E = 266 /* 0x10a */,
WIFIWHO_L4_CHECKSUM_E = 267 /* 0x10b */,
WIFIWHO_L4_INFO_E = 268 /* 0x10c */,
WIFIWHO_MSDU_E = 269 /* 0x10d */,
WIFIWHO_MSDU_MISC_E = 270 /* 0x10e */,
WIFIWHO_PACKET_DATA_E = 271 /* 0x10f */,
WIFIWHO_PACKET_HDR_E = 272 /* 0x110 */,
WIFIWHO_PPDU_END_E = 273 /* 0x111 */,
WIFIWHO_PPDU_START_E = 274 /* 0x112 */,
WIFIWHO_TSO_E = 275 /* 0x113 */,
WIFIWHO_WMAC_HEADER_PV0_E = 276 /* 0x114 */,
WIFIWHO_WMAC_HEADER_PV1_E = 277 /* 0x115 */,
WIFIWHO_WMAC_IV_E = 278 /* 0x116 */,
WIFIMPDU_INFO_END_E = 279 /* 0x117 */,
WIFIMPDU_INFO_BITMAP_E = 280 /* 0x118 */,
WIFITX_QUEUE_EXTENSION_E = 281 /* 0x119 */,
WIFIRX_PEER_ENTRY_DETAILS_E = 282 /* 0x11a */,
WIFIRX_REO_QUEUE_REFERENCE_E = 283 /* 0x11b */,
WIFIRX_REO_QUEUE_EXT_E = 284 /* 0x11c */,
WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 /* 0x11d */,
WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 /* 0x11e */,
WIFITQM_ACKED_MPDU_STATUS_E = 287 /* 0x11f */,
WIFITQM_ADD_MSDU_STATUS_E = 288 /* 0x120 */,
WIFIRX_MPDU_LINK_PTR_E = 289 /* 0x121 */,
WIFIREO_DESTINATION_RING_E = 290 /* 0x122 */,
WIFITQM_LIST_GEN_DONE_E = 291 /* 0x123 */,
WIFIWHO_TERMINATE_E = 292 /* 0x124 */,
WIFITX_LAST_MPDU_END_E = 293 /* 0x125 */,
WIFITX_CV_DATA_E = 294 /* 0x126 */,
WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 /* 0x127 */,
WIFIPPDU_TX_END_E = 296 /* 0x128 */,
WIFIPROT_TX_END_E = 297 /* 0x129 */,
WIFIPDG_RESPONSE_RATE_SETTING_E = 298 /* 0x12a */,
WIFIMPDU_INFO_GLOBAL_END_E = 299 /* 0x12b */,
WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 /* 0x12c */,
WIFIRX_PPDU_END_USER_STATS_E = 301 /* 0x12d */,
WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 /* 0x12e */,
WIFINO_ACK_REPORT_E = 303 /* 0x12f */,
WIFIACK_REPORT_E = 304 /* 0x130 */,
WIFIUNIFORM_REO_CMD_HEADER_E = 305 /* 0x131 */,
WIFIREO_GET_QUEUE_STATS_E = 306 /* 0x132 */,
WIFIREO_FLUSH_QUEUE_E = 307 /* 0x133 */,
WIFIREO_FLUSH_CACHE_E = 308 /* 0x134 */,
WIFIREO_UNBLOCK_CACHE_E = 309 /* 0x135 */,
WIFIUNIFORM_REO_STATUS_HEADER_E = 310 /* 0x136 */,
WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 /* 0x137 */,
WIFIREO_FLUSH_QUEUE_STATUS_E = 312 /* 0x138 */,
WIFIREO_FLUSH_CACHE_STATUS_E = 313 /* 0x139 */,
WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 /* 0x13a */,
WIFITQM_FLUSH_CACHE_E = 315 /* 0x13b */,
WIFITQM_UNBLOCK_CACHE_E = 316 /* 0x13c */,
WIFITQM_FLUSH_CACHE_STATUS_E = 317 /* 0x13d */,
WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 /* 0x13e */,
WIFIRX_PPDU_END_STATUS_DONE_E = 319 /* 0x13f */,
WIFIRX_STATUS_BUFFER_DONE_E = 320 /* 0x140 */,
WIFIBUFFER_ADDR_INFO_E = 321 /* 0x141 */,
WIFIRX_MSDU_DESC_INFO_E = 322 /* 0x142 */,
WIFIRX_MPDU_DESC_INFO_E = 323 /* 0x143 */,
WIFITCL_DATA_CMD_E = 324 /* 0x144 */,
WIFITCL_GSE_CMD_E = 325 /* 0x145 */,
WIFITCL_EXIT_BASE_E = 326 /* 0x146 */,
WIFITCL_COMPACT_EXIT_RING_E = 327 /* 0x147 */,
WIFITCL_REGULAR_EXIT_RING_E = 328 /* 0x148 */,
WIFITCL_EXTENDED_EXIT_RING_E = 329 /* 0x149 */,
WIFIUPLINK_COMMON_INFO_E = 330 /* 0x14a */,
WIFIUPLINK_USER_SETUP_INFO_E = 331 /* 0x14b */,
WIFITX_DATA_SYNC_E = 332 /* 0x14c */,
WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 /* 0x14d */,
WIFITCL_STATUS_RING_E = 334 /* 0x14e */,
WIFITQM_GET_MPDU_HEAD_INFO_E = 335 /* 0x14f */,
WIFITQM_SYNC_CMD_E = 336 /* 0x150 */,
WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 /* 0x151 */,
WIFITQM_SYNC_CMD_STATUS_E = 338 /* 0x152 */,
WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 /* 0x153 */,
WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 /* 0x154 */,
WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 /* 0x155 */,
WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 /* 0x156 */,
WIFIREO_TO_PPE_RING_E = 343 /* 0x157 */,
WIFIRX_MPDU_INFO_E = 344 /* 0x158 */,
WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 /* 0x159 */,
WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 /* 0x15a */,
WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 /* 0x15b */,
WIFIRX_PPDU_START_USER_INFO_E = 348 /* 0x15c */,
WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 /* 0x15d */,
WIFIRX_RING_MASK_E = 350 /* 0x15e */,
WIFIWHO_CLASSIFY_INFO_E = 351 /* 0x15f */,
WIFITXPT_CLASSIFY_INFO_E = 352 /* 0x160 */,
WIFIRXPT_CLASSIFY_INFO_E = 353 /* 0x161 */,
WIFITX_FLOW_SEARCH_ENTRY_E = 354 /* 0x162 */,
WIFIRX_FLOW_SEARCH_ENTRY_E = 355 /* 0x163 */,
WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 /* 0x164 */,
WIFICOEX_MAC_NAP_E = 357 /* 0x165 */,
WIFIMACRX_ABORT_REQUEST_INFO_E = 358 /* 0x166 */,
WIFIMACTX_ABORT_REQUEST_INFO_E = 359 /* 0x167 */,
WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 /* 0x168 */,
WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 /* 0x169 */,
WIFIRXPCU_PPDU_END_INFO_E = 362 /* 0x16a */,
WIFIWHO_MESH_CONTROL_E = 363 /* 0x16b */,
WIFIL_SIG_A_INFO_E = 364 /* 0x16c */,
WIFIL_SIG_B_INFO_E = 365 /* 0x16d */,
WIFIHT_SIG_INFO_E = 366 /* 0x16e */,
WIFIVHT_SIG_A_INFO_E = 367 /* 0x16f */,
WIFIVHT_SIG_B_SU20_INFO_E = 368 /* 0x170 */,
WIFIVHT_SIG_B_SU40_INFO_E = 369 /* 0x171 */,
WIFIVHT_SIG_B_SU80_INFO_E = 370 /* 0x172 */,
WIFIVHT_SIG_B_SU160_INFO_E = 371 /* 0x173 */,
WIFIVHT_SIG_B_MU20_INFO_E = 372 /* 0x174 */,
WIFIVHT_SIG_B_MU40_INFO_E = 373 /* 0x175 */,
WIFIVHT_SIG_B_MU80_INFO_E = 374 /* 0x176 */,
WIFIVHT_SIG_B_MU160_INFO_E = 375 /* 0x177 */,
WIFISERVICE_INFO_E = 376 /* 0x178 */,
WIFIHE_SIG_A_SU_INFO_E = 377 /* 0x179 */,
WIFIHE_SIG_A_MU_DL_INFO_E = 378 /* 0x17a */,
WIFIHE_SIG_A_MU_UL_INFO_E = 379 /* 0x17b */,
WIFIHE_SIG_B1_MU_INFO_E = 380 /* 0x17c */,
WIFIHE_SIG_B2_MU_INFO_E = 381 /* 0x17d */,
WIFIHE_SIG_B2_OFDMA_INFO_E = 382 /* 0x17e */,
WIFIPDG_SW_MODE_BW_START_E = 383 /* 0x17f */,
WIFIPDG_SW_MODE_BW_END_E = 384 /* 0x180 */,
WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 /* 0x181 */,
WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 /* 0x182 */,
WIFISCHEDULER_END_E = 387 /* 0x183 */,
WIFIPEER_TABLE_ENTRY_E = 388 /* 0x184 */,
WIFISW_PEER_INFO_E = 389 /* 0x185 */,
WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 /* 0x186 */,
WIFITCL_CCE_CLASSIFY_INFO_E = 391 /* 0x187 */,
WIFIRXOLE_CCE_INFO_E = 392 /* 0x188 */,
WIFITCL_CCE_INFO_E = 393 /* 0x189 */,
WIFITCL_CCE_SUPERRULE_E = 394 /* 0x18a */,
WIFICCE_RULE_E = 395 /* 0x18b */,
WIFIRX_PPDU_START_DROPPED_E = 396 /* 0x18c */,
WIFIRX_PPDU_END_DROPPED_E = 397 /* 0x18d */,
WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 /* 0x18e */,
WIFIRX_MPDU_START_DROPPED_E = 399 /* 0x18f */,
WIFIRX_MSDU_START_DROPPED_E = 400 /* 0x190 */,
WIFIRX_MSDU_END_DROPPED_E = 401 /* 0x191 */,
WIFIRX_MPDU_END_DROPPED_E = 402 /* 0x192 */,
WIFIRX_ATTENTION_DROPPED_E = 403 /* 0x193 */,
WIFITXPCU_USER_SETUP_E = 404 /* 0x194 */,
WIFIRXPCU_USER_SETUP_EXT_E = 405 /* 0x195 */,
WIFICE_SRC_DESC_E = 406 /* 0x196 */,
WIFICE_STAT_DESC_E = 407 /* 0x197 */,
WIFIRXOLE_CCE_SUPERRULE_E = 408 /* 0x198 */,
WIFITX_RATE_STATS_INFO_E = 409 /* 0x199 */,
WIFICMD_PART_0_END_E = 410 /* 0x19a */,
WIFIMACTX_SYNTH_ON_E = 411 /* 0x19b */,
WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 /* 0x19c */,
WIFITQM_MPDU_GLOBAL_START_E = 413 /* 0x19d */,
WIFIEXAMPLE_TLV_32_E = 414 /* 0x19e */,
WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 /* 0x19f */,
WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 /* 0x1a0 */,
WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */,
WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */,
WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */,
WIFICE_DST_DESC_E = 420 /* 0x1a4 */,
WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 421 /* 0x1a5 */,
WIFITQM_2_SCH_MPDU_AVAILABLE_E = 422 /* 0x1a6 */,
WIFIPDG_TRIG_RESPONSE_E = 423 /* 0x1a7 */,
WIFITRIGGER_RESPONSE_TX_DONE_E = 424 /* 0x1a8 */,
WIFIABORT_FROM_PHYRX_DETAILS_E = 425 /* 0x1a9 */,
WIFISCH_TQM_CMD_WRAPPER_E = 426 /* 0x1aa */,
WIFIMPDUS_AVAILABLE_E = 427 /* 0x1ab */,
WIFIRECEIVED_RESPONSE_INFO_PART2_E = 428 /* 0x1ac */,
WIFIPHYRX_PKT_END_INFO_E = 429 /* 0x1ad */,
WIFIPHYRX_TX_START_TIMING_E = 430 /* 0x1ae */,
WIFITXPCU_PREAMBLE_DONE_E = 431 /* 0x1af */,
WIFINDP_PREAMBLE_DONE_E = 432 /* 0x1b0 */,
WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 433 /* 0x1b1 */,
WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 434 /* 0x1b2 */,
WIFIMACTX_CLEAR_PREV_TX_INFO_E = 435 /* 0x1b3 */,
WIFITX_PUNCTURE_SETUP_E = 436 /* 0x1b4 */,
WIFITX_PUNCTURE_PATTERN_E = 437 /* 0x1b5 */,
WIFIR2R_STATUS_END_E = 438 /* 0x1b6 */,
WIFIMACTX_PREFETCH_CV_COMMON_E = 439 /* 0x1b7 */,
WIFIEND_OF_FLUSH_MARKER_E = 440 /* 0x1b8 */,
WIFIUPLINK_COMMON_INFO_PUNC_E = 441 /* 0x1b9 */,
WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 442 /* 0x1ba */,
WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 443 /* 0x1bb */,
WIFIRECEIVED_RESPONSE_USER_7_0_E = 444 /* 0x1bc */,
WIFIRECEIVED_RESPONSE_USER_15_8_E = 445 /* 0x1bd */,
WIFIRECEIVED_RESPONSE_USER_23_16_E = 446 /* 0x1be */,
WIFIRECEIVED_RESPONSE_USER_31_24_E = 447 /* 0x1bf */,
WIFIRECEIVED_RESPONSE_USER_36_32_E = 448 /* 0x1c0 */,
WIFIRECEIVED_RESPONSE_USER_INFO_E = 449 /* 0x1c1 */,
WIFITX_LOOPBACK_SETUP_E = 450 /* 0x1c2 */,
WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451 /* 0x1c3 */,
WIFISCH_WAIT_INSTR_TX_PATH_E = 452 /* 0x1c4 */,
WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 453 /* 0x1c5 */,
WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454 /* 0x1c6 */,
WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455 /* 0x1c7 */,
WIFITX_WUR_DATA_E = 456 /* 0x1c8 */,
WIFIRX_PPDU_END_START_E = 457 /* 0x1c9 */,
WIFIRX_PPDU_END_MIDDLE_E = 458 /* 0x1ca */,
WIFIRX_PPDU_END_LAST_E = 459 /* 0x1cb */,
WIFIRECEIVE_USER_INFO_L1_E = 460 /* 0x1cc */,
WIFIMIMO_CONTROL_INFO_L1_E = 461 /* 0x1cd */,
WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 462 /* 0x1ce */,
WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463 /* 0x1cf */,
WIFISRP_INFO_E = 464 /* 0x1d0 */,
WIFIOBSS_SR_INFO_E = 465 /* 0x1d1 */,
WIFISCHEDULER_SW_MSG_STATUS_E = 466 /* 0x1d2 */,
WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 467 /* 0x1d3 */,
WIFIRXPCU_SETUP_COMPLETE_E = 468 /* 0x1d4 */,
WIFISNOOP_PPDU_START_E = 469 /* 0x1d5 */,
WIFISNOOP_MPDU_USR_DBG_INFO_E = 470 /* 0x1d6 */,
WIFISNOOP_MSDU_USR_DBG_INFO_E = 471 /* 0x1d7 */,
WIFISNOOP_MSDU_USR_DATA_E = 472 /* 0x1d8 */,
WIFISNOOP_MPDU_USR_STAT_INFO_E = 473 /* 0x1d9 */,
WIFISNOOP_PPDU_END_E = 474 /* 0x1da */,
WIFISNOOP_SPARE_E = 475 /* 0x1db */,
WIFIMACTX_PREFETCH_CV_BULK_E = 476 /* 0x1dc */,
WIFIMACTX_PREFETCH_CV_BULK_USER_E = 477 /* 0x1dd */,
WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 /* 0x1de */,
WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 /* 0x1df */,
WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 /* 0x1e0 */,
WIFISW_MONITOR_RING_E = 481 /* 0x1e1 */,
WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 /* 0x1e2 */,
WIFISCH_TLV_WRAPPER_E = 483 /* 0x1e3 */,
WIFISCHEDULER_STATUS_WRAPPER_E = 484 /* 0x1e4 */,
WIFITLV_BASE_E = 511 /* 0x1ff */
} tlv_tag_def__e; ///< tlv_tag_def Enum Type
#endif // _TLV_TAG_DEF_

750
hw/qca5018/tx_msdu_extension.h Normal file
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@ -0,0 +1,750 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TX_MSDU_EXTENSION_H_
#define _TX_MSDU_EXTENSION_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 tso_enable[0], reserved_0a[6:1], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25]
// 1 l2_length[15:0], ip_length[31:16]
// 2 tcp_seq_number[31:0]
// 3 ip_identification[15:0], udp_length[31:16]
// 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30]
// 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17]
// 6 buf0_ptr_31_0[31:0]
// 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16]
// 8 buf1_ptr_31_0[31:0]
// 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16]
// 10 buf2_ptr_31_0[31:0]
// 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16]
// 12 buf3_ptr_31_0[31:0]
// 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16]
// 14 buf4_ptr_31_0[31:0]
// 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16]
// 16 buf5_ptr_31_0[31:0]
// 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
struct tx_msdu_extension {
uint32_t tso_enable : 1, //[0]
reserved_0a : 6, //[6:1]
tcp_flag : 9, //[15:7]
tcp_flag_mask : 9, //[24:16]
reserved_0b : 7; //[31:25]
uint32_t l2_length : 16, //[15:0]
ip_length : 16; //[31:16]
uint32_t tcp_seq_number : 32; //[31:0]
uint32_t ip_identification : 16, //[15:0]
udp_length : 16; //[31:16]
uint32_t checksum_offset : 14, //[13:0]
partial_checksum_en : 1, //[14]
reserved_4a : 1, //[15]
payload_start_offset : 14, //[29:16]
reserved_4b : 2; //[31:30]
uint32_t payload_end_offset : 14, //[13:0]
reserved_5a : 2, //[15:14]
wds : 1, //[16]
reserved_5b : 15; //[31:17]
uint32_t buf0_ptr_31_0 : 32; //[31:0]
uint32_t buf0_ptr_39_32 : 8, //[7:0]
reserved_7a : 8, //[15:8]
buf0_len : 16; //[31:16]
uint32_t buf1_ptr_31_0 : 32; //[31:0]
uint32_t buf1_ptr_39_32 : 8, //[7:0]
reserved_9a : 8, //[15:8]
buf1_len : 16; //[31:16]
uint32_t buf2_ptr_31_0 : 32; //[31:0]
uint32_t buf2_ptr_39_32 : 8, //[7:0]
reserved_11a : 8, //[15:8]
buf2_len : 16; //[31:16]
uint32_t buf3_ptr_31_0 : 32; //[31:0]
uint32_t buf3_ptr_39_32 : 8, //[7:0]
reserved_13a : 8, //[15:8]
buf3_len : 16; //[31:16]
uint32_t buf4_ptr_31_0 : 32; //[31:0]
uint32_t buf4_ptr_39_32 : 8, //[7:0]
reserved_15a : 8, //[15:8]
buf4_len : 16; //[31:16]
uint32_t buf5_ptr_31_0 : 32; //[31:0]
uint32_t buf5_ptr_39_32 : 8, //[7:0]
reserved_17a : 8, //[15:8]
buf5_len : 16; //[31:16]
};
/*
tso_enable
Enable transmit segmentation offload <legal all>
reserved_0a
FW will set to 0, MAC will ignore.  <legal 0>
tcp_flag
TCP flags
{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
tcp_flag_mask
TCP flag mask. Tcp_flag is inserted into the header
based on the mask, if TSO is enabled
reserved_0b
FW will set to 0, MAC will ignore.  <legal 0>
l2_length
L2 length for the msdu, if TSO is enabled <legal all>
ip_length
IP length for the msdu, if TSO is enabled <legal all>
tcp_seq_number
Tcp_seq_number for the msdu, if TSO is enabled <legal
all>
ip_identification
IP_identification for the msdu, if TSO is enabled <legal
all>
udp_length
TXDMA is copies this field into MSDU START TLV
checksum_offset
The calculated checksum from start offset to end offset
will be added to the checksum at the offset given by this
field<legal all>
partial_checksum_en
Partial Checksum Enable Bit.
<legal 0-1>
reserved_4a
<Legal 0>
payload_start_offset
L4 checksum calculations will start fromt this offset
<Legal all>
reserved_4b
<Legal 0>
payload_end_offset
L4 checksum calculations will end at this offset.
<Legal all>
reserved_5a
<Legal 0>
wds
If set the current packet is 4-address frame. Required
because an aggregate can include some frames with 3 address
format and other frames with 4 address format. Used by the
OLE during encapsulation.
Note: there is also global wds tx control in the
TX_PEER_ENTRY
<legal all>
reserved_5b
<Legal 0>
buf0_ptr_31_0
Lower 32 bits of the first buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf0_ptr_39_32
Upper 8 bits of the first buffer pointer <legal all>
reserved_7a
<Legal 0>
buf0_len
Length of the first buffer <legal all>
buf1_ptr_31_0
Lower 32 bits of the second buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf1_ptr_39_32
Upper 8 bits of the second buffer pointer <legal all>
reserved_9a
<Legal 0>
buf1_len
Length of the second buffer <legal all>
buf2_ptr_31_0
Lower 32 bits of the third buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf2_ptr_39_32
Upper 8 bits of the third buffer pointer <legal all>
reserved_11a
<Legal 0>
buf2_len
Length of the third buffer <legal all>
buf3_ptr_31_0
Lower 32 bits of the fourth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf3_ptr_39_32
Upper 8 bits of the fourth buffer pointer <legal all>
reserved_13a
<Legal 0>
buf3_len
Length of the fourth buffer <legal all>
buf4_ptr_31_0
Lower 32 bits of the fifth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf4_ptr_39_32
Upper 8 bits of the fifth buffer pointer <legal all>
reserved_15a
<Legal 0>
buf4_len
Length of the fifth buffer <legal all>
buf5_ptr_31_0
Lower 32 bits of the sixth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf5_ptr_39_32
Upper 8 bits of the sixth buffer pointer <legal all>
reserved_17a
<Legal 0>
buf5_len
Length of the sixth buffer <legal all>
*/
/* Description TX_MSDU_EXTENSION_0_TSO_ENABLE
Enable transmit segmentation offload <legal all>
*/
#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0
#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001
/* Description TX_MSDU_EXTENSION_0_RESERVED_0A
FW will set to 0, MAC will ignore.  <legal 0>
*/
#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1
#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e
/* Description TX_MSDU_EXTENSION_0_TCP_FLAG
TCP flags
{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
*/
#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80
/* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK
TCP flag mask. Tcp_flag is inserted into the header
based on the mask, if TSO is enabled
*/
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000
/* Description TX_MSDU_EXTENSION_0_RESERVED_0B
FW will set to 0, MAC will ignore.  <legal 0>
*/
#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25
#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000
/* Description TX_MSDU_EXTENSION_1_L2_LENGTH
L2 length for the msdu, if TSO is enabled <legal all>
*/
#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004
#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0
#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff
/* Description TX_MSDU_EXTENSION_1_IP_LENGTH
IP length for the msdu, if TSO is enabled <legal all>
*/
#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004
#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16
#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER
Tcp_seq_number for the msdu, if TSO is enabled <legal
all>
*/
#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008
#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0
#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION
IP_identification for the msdu, if TSO is enabled <legal
all>
*/
#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c
#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0
#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff
/* Description TX_MSDU_EXTENSION_3_UDP_LENGTH
TXDMA is copies this field into MSDU START TLV
*/
#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c
#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16
#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET
The calculated checksum from start offset to end offset
will be added to the checksum at the offset given by this
field<legal all>
*/
#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0
#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff
/* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN
Partial Checksum Enable Bit.
<legal 0-1>
*/
#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14
#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000
/* Description TX_MSDU_EXTENSION_4_RESERVED_4A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15
#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000
/* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET
L4 checksum calculations will start fromt this offset
<Legal all>
*/
#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16
#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000
/* Description TX_MSDU_EXTENSION_4_RESERVED_4B
<Legal 0>
*/
#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30
#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000
/* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET
L4 checksum calculations will end at this offset.
<Legal all>
*/
#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0
#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff
/* Description TX_MSDU_EXTENSION_5_RESERVED_5A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14
#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000
/* Description TX_MSDU_EXTENSION_5_WDS
If set the current packet is 4-address frame. Required
because an aggregate can include some frames with 3 address
format and other frames with 4 address format. Used by the
OLE during encapsulation.
Note: there is also global wds tx control in the
TX_PEER_ENTRY
<legal all>
*/
#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_WDS_LSB 16
#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000
/* Description TX_MSDU_EXTENSION_5_RESERVED_5B
<Legal 0>
*/
#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17
#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000
/* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0
Lower 32 bits of the first buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018
#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32
Upper 8 bits of the first buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_7_RESERVED_7A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8
#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_7_BUF0_LEN
Length of the first buffer <legal all>
*/
#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16
#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0
Lower 32 bits of the second buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020
#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32
Upper 8 bits of the second buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_9_RESERVED_9A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8
#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_9_BUF1_LEN
Length of the second buffer <legal all>
*/
#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16
#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0
Lower 32 bits of the third buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028
#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32
Upper 8 bits of the third buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_11_RESERVED_11A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8
#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_11_BUF2_LEN
Length of the third buffer <legal all>
*/
#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16
#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0
Lower 32 bits of the fourth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030
#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32
Upper 8 bits of the fourth buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_13_RESERVED_13A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8
#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_13_BUF3_LEN
Length of the fourth buffer <legal all>
*/
#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16
#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0
Lower 32 bits of the fifth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038
#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32
Upper 8 bits of the fifth buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_15_RESERVED_15A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8
#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_15_BUF4_LEN
Length of the fifth buffer <legal all>
*/
#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16
#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0
Lower 32 bits of the sixth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040
#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32
Upper 8 bits of the sixth buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_17_RESERVED_17A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8
#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_17_BUF5_LEN
Length of the sixth buffer <legal all>
*/
#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16
#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000
#endif // _TX_MSDU_EXTENSION_H_

466
hw/qca5018/tx_rate_stats_info.h Normal file
View File

@ -0,0 +1,466 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TX_RATE_STATS_INFO_H_
#define _TX_RATE_STATS_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 tx_rate_stats_info_valid[0], transmit_bw[2:1], transmit_pkt_type[6:3], transmit_stbc[7], transmit_ldpc[8], transmit_sgi[10:9], transmit_mcs[14:11], ofdma_transmission[15], tones_in_ru[27:16], reserved_0a[31:28]
// 1 ppdu_transmission_tsf[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
struct tx_rate_stats_info {
uint32_t tx_rate_stats_info_valid : 1, //[0]
transmit_bw : 2, //[2:1]
transmit_pkt_type : 4, //[6:3]
transmit_stbc : 1, //[7]
transmit_ldpc : 1, //[8]
transmit_sgi : 2, //[10:9]
transmit_mcs : 4, //[14:11]
ofdma_transmission : 1, //[15]
tones_in_ru : 12, //[27:16]
reserved_0a : 4; //[31:28]
uint32_t ppdu_transmission_tsf : 32; //[31:0]
};
/*
tx_rate_stats_info_valid
When set all other fields in this STRUCT contain valid
info.
<legal all>
transmit_bw
Field only valid when Tx_rate_stats_info_valid is set
Indicates the BW of the upcoming transmission that shall
likely start in about 3 -4 us on the medium
<enum 0 transmit_bw_20_MHz>
<enum 1 transmit_bw_40_MHz>
<enum 2 transmit_bw_80_MHz>
<enum 3 transmit_bw_160_MHz>
<legal all>
transmit_pkt_type
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The packet type
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
transmit_stbc
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, STBC transmission rate was used.
transmit_ldpc
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, use LDPC transmission rates
transmit_sgi
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
<enum 0 0_8_us_sgi > Legacy normal GI. Can also be
used for HE
<enum 1 0_4_us_sgi > Legacy short GI. Can also be
used for HE
<enum 2 1_6_us_sgi > HE related GI
<enum 3 3_2_us_sgi > HE related GI
<legal 0 - 3>
transmit_mcs
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
For details, refer to MCS_TYPE description
<legal all>
ofdma_transmission
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Set when the transmission was an OFDMA transmission (DL
or UL).
<legal all>
tones_in_ru
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The number of tones in the RU used.
<legal all>
reserved_0a
<legal 0>
ppdu_transmission_tsf
Field only valid when Tx_rate_stats_info_valid is set
Based on a HWSCH configuration register setting, this
field either contains:
Lower 32 bits of the TSF, snapshot of this value when
transmission of the PPDU containing the frame finished.
OR
Lower 32 bits of the TSF, snapshot of this value when
transmission of the PPDU containing the frame started
<legal all>
*/
/* Description TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID
When set all other fields in this STRUCT contain valid
info.
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0
#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_BW
Field only valid when Tx_rate_stats_info_valid is set
Indicates the BW of the upcoming transmission that shall
likely start in about 3 -4 us on the medium
<enum 0 transmit_bw_20_MHz>
<enum 1 transmit_bw_40_MHz>
<enum 2 transmit_bw_80_MHz>
<enum 3 transmit_bw_160_MHz>
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1
#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The packet type
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
<enum 5 dot11ba>802.11ba (WUR) PPDU type
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3
#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_STBC
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, STBC transmission rate was used.
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7
#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_LDPC
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, use LDPC transmission rates
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8
#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_SGI
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
<enum 0 0_8_us_sgi > Legacy normal GI. Can also be
used for HE
<enum 1 0_4_us_sgi > Legacy short GI. Can also be
used for HE
<enum 2 1_6_us_sgi > HE related GI
<enum 3 3_2_us_sgi > HE related GI
<legal 0 - 3>
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9
#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_MCS
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
For details, refer to MCS_TYPE description
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11
#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800
/* Description TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Set when the transmission was an OFDMA transmission (DL
or UL).
<legal all>
*/
#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15
#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000
/* Description TX_RATE_STATS_INFO_0_TONES_IN_RU
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The number of tones in the RU used.
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16
#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000
/* Description TX_RATE_STATS_INFO_0_RESERVED_0A
<legal 0>
*/
#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28
#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000
/* Description TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF
Field only valid when Tx_rate_stats_info_valid is set
Based on a HWSCH configuration register setting, this
field either contains:
Lower 32 bits of the TSF, snapshot of this value when
transmission of the PPDU containing the frame finished.
OR
Lower 32 bits of the TSF, snapshot of this value when
transmission of the PPDU containing the frame started
<legal all>
*/
#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004
#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB 0
#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
#endif // _TX_RATE_STATS_INFO_H_

221
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
#define _UNIFORM_DESCRIPTOR_HEADER_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
struct uniform_descriptor_header {
uint32_t owner : 4, //[3:0]
buffer_type : 4, //[7:4]
reserved_0a : 24; //[31:8]
};
/*
owner
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
The owner of this data structure:
<enum 0 WBM_owned> Buffer Manager currently owns this
data structure.
<enum 1 SW_OR_FW_owned> Software of FW currently owns
this data structure.
<enum 2 TQM_owned> Transmit Queue Manager currently owns
this data structure.
<enum 3 RXDMA_owned> Receive DMA currently owns this
data structure.
<enum 4 REO_owned> Reorder currently owns this data
structure.
<enum 5 SWITCH_owned> SWITCH currently owns this data
structure.
<legal 0-5>
buffer_type
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Field describing what contents format is of this
descriptor
<enum 0 Transmit_MSDU_Link_descriptor >
<enum 1 Transmit_MPDU_Link_descriptor >
<enum 2 Transmit_MPDU_Queue_head_descriptor>
<enum 3 Transmit_MPDU_Queue_ext_descriptor>
<enum 4 Transmit_flow_descriptor>
<enum 5 Transmit_buffer > NOT TO BE USED:
<enum 6 Receive_MSDU_Link_descriptor >
<enum 7 Receive_MPDU_Link_descriptor >
<enum 8 Receive_REO_queue_descriptor >
<enum 9 Receive_REO_queue_ext_descriptor >
<enum 10 Receive_buffer >
<enum 11 Idle_link_list_entry>
<legal 0-11>
reserved_0a
<legal 0>
*/
/* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
The owner of this data structure:
<enum 0 WBM_owned> Buffer Manager currently owns this
data structure.
<enum 1 SW_OR_FW_owned> Software of FW currently owns
this data structure.
<enum 2 TQM_owned> Transmit Queue Manager currently owns
this data structure.
<enum 3 RXDMA_owned> Receive DMA currently owns this
data structure.
<enum 4 REO_owned> Reorder currently owns this data
structure.
<enum 5 SWITCH_owned> SWITCH currently owns this data
structure.
<legal 0-5>
*/
#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000
#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0
#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f
/* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Field describing what contents format is of this
descriptor
<enum 0 Transmit_MSDU_Link_descriptor >
<enum 1 Transmit_MPDU_Link_descriptor >
<enum 2 Transmit_MPDU_Queue_head_descriptor>
<enum 3 Transmit_MPDU_Queue_ext_descriptor>
<enum 4 Transmit_flow_descriptor>
<enum 5 Transmit_buffer > NOT TO BE USED:
<enum 6 Receive_MSDU_Link_descriptor >
<enum 7 Receive_MPDU_Link_descriptor >
<enum 8 Receive_REO_queue_descriptor >
<enum 9 Receive_REO_queue_ext_descriptor >
<enum 10 Receive_buffer >
<enum 11 Idle_link_list_entry>
<legal 0-11>
*/
#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000
#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4
#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0
/* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A
<legal 0>
*/
#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8
#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00
#endif // _UNIFORM_DESCRIPTOR_HEADER_H_

133
hw/qca5018/uniform_reo_cmd_header.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _UNIFORM_REO_CMD_HEADER_H_
#define _UNIFORM_REO_CMD_HEADER_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 reo_cmd_number[15:0], reo_status_required[16], reserved_0a[31:17]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
struct uniform_reo_cmd_header {
uint32_t reo_cmd_number : 16, //[15:0]
reo_status_required : 1, //[16]
reserved_0a : 15; //[31:17]
};
/*
reo_cmd_number
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
reo_status_required
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
reserved_0a
<legal 0>
*/
/* Description UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
*/
#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0
#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff
/* Description UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
*/
#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16
#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000
/* Description UNIFORM_REO_CMD_HEADER_0_RESERVED_0A
<legal 0>
*/
#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17
#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000
#endif // _UNIFORM_REO_CMD_HEADER_H_

242
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _UNIFORM_REO_STATUS_HEADER_H_
#define _UNIFORM_REO_STATUS_HEADER_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 reo_status_number[15:0], cmd_execution_time[25:16], reo_cmd_execution_status[27:26], reserved_0a[31:28]
// 1 timestamp[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
struct uniform_reo_status_header {
uint32_t reo_status_number : 16, //[15:0]
cmd_execution_time : 10, //[25:16]
reo_cmd_execution_status : 2, //[27:26]
reserved_0a : 4; //[31:28]
uint32_t timestamp : 32; //[31:0]
};
/*
reo_status_number
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
cmd_execution_time
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
reo_cmd_execution_status
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
reserved_0a
<legal 0>
timestamp
Timestamp at the moment that this status report is
written.
<legal all>
*/
/* Description UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0
#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16
#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26
#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A
<legal 0>
*/
#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28
#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000
/* Description UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004
#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0
#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff
#endif // _UNIFORM_REO_STATUS_HEADER_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _VHT_SIG_A_INFO_H_
#define _VHT_SIG_A_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 bandwidth[1:0], vhta_reserved_0[2], stbc[3], group_id[9:4], n_sts[21:10], txop_ps_not_allowed[22], vhta_reserved_0b[23], reserved_0[31:24]
// 1 gi_setting[1:0], su_mu_coding[2], ldpc_extra_symbol[3], mcs[7:4], beamformed[8], vhta_reserved_1[9], crc[17:10], tail[23:18], reserved_1[31:24]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
struct vht_sig_a_info {
uint32_t bandwidth : 2, //[1:0]
vhta_reserved_0 : 1, //[2]
stbc : 1, //[3]
group_id : 6, //[9:4]
n_sts : 12, //[21:10]
txop_ps_not_allowed : 1, //[22]
vhta_reserved_0b : 1, //[23]
reserved_0 : 8; //[31:24]
uint32_t gi_setting : 2, //[1:0]
su_mu_coding : 1, //[2]
ldpc_extra_symbol : 1, //[3]
mcs : 4, //[7:4]
beamformed : 1, //[8]
vhta_reserved_1 : 1, //[9]
crc : 8, //[17:10]
tail : 6, //[23:18]
reserved_1 : 8; //[31:24]
};
/*
bandwidth
Packet bandwidth
<enum 0 20_MHZ_11AC>
<enum 1 40_MHZ_11AC>
<enum 2 80_MHZ_11AC>
<enum 3 160_MHZ_11AC>
<legal 0-3>
vhta_reserved_0
Reserved. Set to 1 by MAC, PHY should ignore
<legal 1>
stbc
Space time block coding:
<enum 0 stbc_disabled> Indicates STBC is disabled
<enum 1 stbc_enabled> Indicates STBC is enabled on
all streams
<legal 0-1>
group_id
In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
to an AP or to a mesh STA, the Group ID field is set to 0,
otherwise it is set to 63. In an NDP PPDU the Group ID is
set according to IEEE 802.11ac_D1.0 Section 9.30.6
(Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID
is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID).
<legal all>
n_sts
For MU:
3 bits/user with maximum of 4 users (user u uses
vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
3)
Set to 0 for 0 space time streams
Set to 1 for 1 space time stream
Set to 2 for 2 space time streams
Set to 3 for 3 space time streams
Set to 4 for 4 space time streams (not supported in Wifi
3.0)
Values 5-7 are reserved
In this field, references to user u should be
interpreted as MU user u. As described in the previous
chapter in this document (see chapter on User number), the
MU user value for a given client is defined for each MU
group that the client participates in. The MU user number is
not related to the internal user number that is used within
the BFer.
For SU:
vht_sig_a[0][12:10]
Set to 0 for 1 space time stream
Set to 1 for 2 space time streams
Set to 2 for 3 space time streams
Set to 3 for 4 space time streams
Set to 4 for 5 space time streams
Set to 5 for 6 space time streams
Set to 6 for 7 space time streams
Set to 7 for 8 space time streams
vht_sig_a[0][21:13]
Partial AID:
Set to the value of the TXVECTOR parameter PARTIAL_AID.
Partial AID provides an abbreviated indication of the
intended recipient(s) of the frame (see IEEE802.11ac_D1.0
Section 9.17a (Partial AID in VHT PPDUs)).
<legal all>
txop_ps_not_allowed
E_num 0 txop_ps_allowed Not supported: If set to by
VHT AP if it allows non-AP VHT STAs in TXOP power save mode
to enter Doze state during a TXOP
<enum 1 no_txop_ps_allowed> Otherwise
<legal 1>
vhta_reserved_0b
Reserved: Should be set to 1 by the MAC and ignored by
the PHY <legal 1>
reserved_0
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
gi_setting
<enum 0 normal_gi> Indicates short guard interval
is not used in the data field
<enum 1 short_gi> Indicates short guard interval is
used in the data field
<enum 3 short_gi_ambiguity> Indicates short guard
interval is used in the data field and NSYM mod 10 = 9
NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3
(TXTIME and PSDU_LENGTH calculation).
<legal 0,1,3>
su_mu_coding
For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For
an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
B2 indicates the coding used for user 0; set to 0 for BCC
and 1 for LDPC. If the MU[0] NSTS field is 0, then this
field is reserved and set to 1
ldpc_extra_symbol
Set to 1 if the LDPC PPDU encoding process (if an SU
PPDU), or at least one LDPC user's PPDU encoding process (if
an MU PPDU), results in an extra OFDM symbol (or symbols) as
described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
(Encoding process for MU PPDUs). Set to 0 otherwise.
mcs
For SU:
Set to 0 for BPSK 1/2
Set to 1 for QPSK 1/2
Set to 2 for QPSK 3/4
Set to 3 for 16-QAM 1/2
Set to 4 for 16-QAM 3/4
Set to 5 for 64-QAM 2/3
Set to 6 for 64-QAM 3/4
Set to 7 for 64-QAM 5/6
Set to 8 for 256-QAM 3/4
Set to 9 for 256-QAM 5/6
For MU:
If NSTS for user 1 is non-zero, then vht_sig_a[1][4]
indicates coding for user 1: set to 0 for BCC, 1 for LDPC.
If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
reserved and set to 1.
If NSTS for user 2 is non-zero, then vht_sig_a[1][5]
indicates coding for user 2: set to 0 for BCC, 1 for LDPC.
If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
reserved and set to 1.
If NSTS for user 3 is non-zero, then vht_sig_a[1][6]
indicates coding for user 3: set to 0 for BCC, 1 for LDPC.
If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
reserved and set to 1.
vht_sig_a[1][7] is reserved and set to 1
<legal 0-15>
beamformed
For SU:
Set to 1 if a Beamforming steering matrix is applied to
the waveform in an SU transmission as described in
IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping),
set to 0 otherwise.
For MU:
Reserved and set to 1
<legal 0-1>
vhta_reserved_1
Reserved and set to 1. <legal 1>
crc
CRC calculated as in IEEE802.11ac_D1.0 Section
19.3.9.4.4 (CRC calculation for HTSIG) with C7 in
vht_sig_a[1][10], etc. <legal all>
tail
Used to terminate the trellis of the convolutional
decoder. Set to 0. <legal 0>
reserved_1
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
*/
/* Description VHT_SIG_A_INFO_0_BANDWIDTH
Packet bandwidth
<enum 0 20_MHZ_11AC>
<enum 1 40_MHZ_11AC>
<enum 2 80_MHZ_11AC>
<enum 3 160_MHZ_11AC>
<legal 0-3>
*/
#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB 0
#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK 0x00000003
/* Description VHT_SIG_A_INFO_0_VHTA_RESERVED_0
Reserved. Set to 1 by MAC, PHY should ignore
<legal 1>
*/
#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB 2
#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK 0x00000004
/* Description VHT_SIG_A_INFO_0_STBC
Space time block coding:
<enum 0 stbc_disabled> Indicates STBC is disabled
<enum 1 stbc_enabled> Indicates STBC is enabled on
all streams
<legal 0-1>
*/
#define VHT_SIG_A_INFO_0_STBC_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_STBC_LSB 3
#define VHT_SIG_A_INFO_0_STBC_MASK 0x00000008
/* Description VHT_SIG_A_INFO_0_GROUP_ID
In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
to an AP or to a mesh STA, the Group ID field is set to 0,
otherwise it is set to 63. In an NDP PPDU the Group ID is
set according to IEEE 802.11ac_D1.0 Section 9.30.6
(Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID
is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID).
<legal all>
*/
#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_GROUP_ID_LSB 4
#define VHT_SIG_A_INFO_0_GROUP_ID_MASK 0x000003f0
/* Description VHT_SIG_A_INFO_0_N_STS
For MU:
3 bits/user with maximum of 4 users (user u uses
vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
3)
Set to 0 for 0 space time streams
Set to 1 for 1 space time stream
Set to 2 for 2 space time streams
Set to 3 for 3 space time streams
Set to 4 for 4 space time streams (not supported in Wifi
3.0)
Values 5-7 are reserved
In this field, references to user u should be
interpreted as MU user u. As described in the previous
chapter in this document (see chapter on User number), the
MU user value for a given client is defined for each MU
group that the client participates in. The MU user number is
not related to the internal user number that is used within
the BFer.
For SU:
vht_sig_a[0][12:10]
Set to 0 for 1 space time stream
Set to 1 for 2 space time streams
Set to 2 for 3 space time streams
Set to 3 for 4 space time streams
Set to 4 for 5 space time streams
Set to 5 for 6 space time streams
Set to 6 for 7 space time streams
Set to 7 for 8 space time streams
vht_sig_a[0][21:13]
Partial AID:
Set to the value of the TXVECTOR parameter PARTIAL_AID.
Partial AID provides an abbreviated indication of the
intended recipient(s) of the frame (see IEEE802.11ac_D1.0
Section 9.17a (Partial AID in VHT PPDUs)).
<legal all>
*/
#define VHT_SIG_A_INFO_0_N_STS_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_N_STS_LSB 10
#define VHT_SIG_A_INFO_0_N_STS_MASK 0x003ffc00
/* Description VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED
E_num 0 txop_ps_allowed Not supported: If set to by
VHT AP if it allows non-AP VHT STAs in TXOP power save mode
to enter Doze state during a TXOP
<enum 1 no_txop_ps_allowed> Otherwise
<legal 1>
*/
#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB 22
#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
/* Description VHT_SIG_A_INFO_0_VHTA_RESERVED_0B
Reserved: Should be set to 1 by the MAC and ignored by
the PHY <legal 1>
*/
#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB 23
#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK 0x00800000
/* Description VHT_SIG_A_INFO_0_RESERVED_0
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
*/
#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET 0x00000000
#define VHT_SIG_A_INFO_0_RESERVED_0_LSB 24
#define VHT_SIG_A_INFO_0_RESERVED_0_MASK 0xff000000
/* Description VHT_SIG_A_INFO_1_GI_SETTING
<enum 0 normal_gi> Indicates short guard interval
is not used in the data field
<enum 1 short_gi> Indicates short guard interval is
used in the data field
<enum 3 short_gi_ambiguity> Indicates short guard
interval is used in the data field and NSYM mod 10 = 9
NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3
(TXTIME and PSDU_LENGTH calculation).
<legal 0,1,3>
*/
#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_GI_SETTING_LSB 0
#define VHT_SIG_A_INFO_1_GI_SETTING_MASK 0x00000003
/* Description VHT_SIG_A_INFO_1_SU_MU_CODING
For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For
an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
B2 indicates the coding used for user 0; set to 0 for BCC
and 1 for LDPC. If the MU[0] NSTS field is 0, then this
field is reserved and set to 1
*/
#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB 2
#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK 0x00000004
/* Description VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL
Set to 1 if the LDPC PPDU encoding process (if an SU
PPDU), or at least one LDPC user's PPDU encoding process (if
an MU PPDU), results in an extra OFDM symbol (or symbols) as
described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
(Encoding process for MU PPDUs). Set to 0 otherwise.
*/
#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB 3
#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000008
/* Description VHT_SIG_A_INFO_1_MCS
For SU:
Set to 0 for BPSK 1/2
Set to 1 for QPSK 1/2
Set to 2 for QPSK 3/4
Set to 3 for 16-QAM 1/2
Set to 4 for 16-QAM 3/4
Set to 5 for 64-QAM 2/3
Set to 6 for 64-QAM 3/4
Set to 7 for 64-QAM 5/6
Set to 8 for 256-QAM 3/4
Set to 9 for 256-QAM 5/6
For MU:
If NSTS for user 1 is non-zero, then vht_sig_a[1][4]
indicates coding for user 1: set to 0 for BCC, 1 for LDPC.
If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
reserved and set to 1.
If NSTS for user 2 is non-zero, then vht_sig_a[1][5]
indicates coding for user 2: set to 0 for BCC, 1 for LDPC.
If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
reserved and set to 1.
If NSTS for user 3 is non-zero, then vht_sig_a[1][6]
indicates coding for user 3: set to 0 for BCC, 1 for LDPC.
If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
reserved and set to 1.
vht_sig_a[1][7] is reserved and set to 1
<legal 0-15>
*/
#define VHT_SIG_A_INFO_1_MCS_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_MCS_LSB 4
#define VHT_SIG_A_INFO_1_MCS_MASK 0x000000f0
/* Description VHT_SIG_A_INFO_1_BEAMFORMED
For SU:
Set to 1 if a Beamforming steering matrix is applied to
the waveform in an SU transmission as described in
IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping),
set to 0 otherwise.
For MU:
Reserved and set to 1
<legal 0-1>
*/
#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB 8
#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK 0x00000100
/* Description VHT_SIG_A_INFO_1_VHTA_RESERVED_1
Reserved and set to 1. <legal 1>
*/
#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB 9
#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK 0x00000200
/* Description VHT_SIG_A_INFO_1_CRC
CRC calculated as in IEEE802.11ac_D1.0 Section
19.3.9.4.4 (CRC calculation for HTSIG) with C7 in
vht_sig_a[1][10], etc. <legal all>
*/
#define VHT_SIG_A_INFO_1_CRC_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_CRC_LSB 10
#define VHT_SIG_A_INFO_1_CRC_MASK 0x0003fc00
/* Description VHT_SIG_A_INFO_1_TAIL
Used to terminate the trellis of the convolutional
decoder. Set to 0. <legal 0>
*/
#define VHT_SIG_A_INFO_1_TAIL_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_TAIL_LSB 18
#define VHT_SIG_A_INFO_1_TAIL_MASK 0x00fc0000
/* Description VHT_SIG_A_INFO_1_RESERVED_1
This field is not part of HT-SIG:
Reserved: Should be set to 0 by the MAC and ignored by
the PHY <legal 0>
*/
#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET 0x00000004
#define VHT_SIG_A_INFO_1_RESERVED_1_LSB 24
#define VHT_SIG_A_INFO_1_RESERVED_1_MASK 0xff000000
#endif // _VHT_SIG_A_INFO_H_

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hw/qca5018/wbm_buffer_ring.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _WBM_BUFFER_RING_H_
#define _WBM_BUFFER_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info buf_addr_info;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
struct wbm_buffer_ring {
struct buffer_addr_info buf_addr_info;
};
/*
struct buffer_addr_info buf_addr_info
Consumer: WBM
Producer: WBM
Details of the physical address of the buffer + source
buffer owner + some SW meta data.
All modules getting this buffer address info, shall keep
all the 64 bits of info in this descriptor together and
eventually all 64 bits shall be given back to WMB when the
buffer is released.
*/
/* EXTERNAL REFERENCE : struct buffer_addr_info buf_addr_info */
/* Description WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<enum 7 SW4_BM> This buffer shall be returned to the SW,
ring 4
<legal all>
*/
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE1:
The three most significant bits can have a special
meaning in case this struct is embedded in a TX_MPDU_DETAILS
STRUCT, and field transmit_bw_restriction is set
In case of NON punctured transmission:
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
In case of punctured transmission:
Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
Note: a punctured transmission is indicated by the
presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
TLV
NOTE 2:The five most significant bits can have a special
meaning in case this struct is embedded in an
RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
configured for passing on the additional info
from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
(FR56821). This is not supported in HastingsPrime, Pine or
Moselle.
Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
control field
Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
indicates MPDUs with a QoS control field.
<legal all>
*/
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
#endif // _WBM_BUFFER_RING_H_

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hw/qca5018/wbm_link_descriptor_ring.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
#define _WBM_LINK_DESCRIPTOR_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info desc_addr_info;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
struct wbm_link_descriptor_ring {
struct buffer_addr_info desc_addr_info;
};
/*
struct buffer_addr_info desc_addr_info
Consumer: WBM
Producer: WBM
Details of the physical address of the buffer + source
buffer owner + some SW meta data
All modules getting this link descriptor address info,
shall keep all the 64 bits in this descriptor together and
eventually all 64 bits shall be given back to WBM when the
link descriptor is released.
*/
/* EXTERNAL REFERENCE : struct buffer_addr_info desc_addr_info */
/* Description WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<enum 7 SW4_BM> This buffer shall be returned to the SW,
ring 4
<legal all>
*/
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE1:
The three most significant bits can have a special
meaning in case this struct is embedded in a TX_MPDU_DETAILS
STRUCT, and field transmit_bw_restriction is set
In case of NON punctured transmission:
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
In case of punctured transmission:
Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
Note: a punctured transmission is indicated by the
presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
TLV
NOTE 2:The five most significant bits can have a special
meaning in case this struct is embedded in an
RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
configured for passing on the additional info
from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
(FR56821). This is not supported in HastingsPrime, Pine or
Moselle.
Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
control field
Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
indicates MPDUs with a QoS control field.
<legal all>
*/
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
#endif // _WBM_LINK_DESCRIPTOR_RING_H_

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
// User Name:c_landav
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __WBM_REG_SEQ_BASE_H__
#define __WBM_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#endif

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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
// User Name:c_landav
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __WCSS_SEQ_BASE_H__
#define __WCSS_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wcss
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WCSS_ECAHB_OFFSET 0x00008400
#define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000
#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000
#define SEQ_WCSS_PHYA_OFFSET 0x00300000
#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000
#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400
#define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00381800
#define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00
#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00382c00
#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00383000
#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000
#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000
#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000
#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000
#define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000
#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00400000
#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000
#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_OFFSET 0x004c0000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x004d4000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x004d4000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x004d4240
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x004d42c0
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x004d42e0
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x004d4300
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x004d4400
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x004d4480
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x004d4800
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_DPLL_OFFSET 0x004d4c00
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x004d6000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x004d6040
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x004d6100
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x004d6140
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x004d6180
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x004d61c0
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x004d6240
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x004d7c00
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET 0x004da000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET 0x004da000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x004dc000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x004dc000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_HLS_BT_REGFILE_OFFSET 0x004dc400
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x004dc800
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x004dc840
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x004dc880
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x004dc8c0
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x004e0000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x004e0000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x004e0400
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x004e0800
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x004e1000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x004e1300
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x004e1600
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x004e1640
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x004e2000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x004e4000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x004e8000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x004e8400
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x004e8800
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x004e9000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x004e9300
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x004e9600
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x004e9640
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x004ea000
#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x004ec000
#define SEQ_WCSS_UMAC_OFFSET 0x00a00000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000
#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000
#define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000
#define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000
#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000
#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000
#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000
#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000
#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000
#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000
#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000
#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000
#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000
#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000
#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000
#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000
#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000
#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000
#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000
#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000
#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000
#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000
#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000
#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000
#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000
#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000
#define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000
#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000
#define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000
#define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000
#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000
#define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000
#define SEQ_WCSS_WL_MSIP_OFFSET 0x00b80000
#define SEQ_WCSS_WL_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000
#define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET 0x00b80180
#define SEQ_WCSS_WL_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00b80190
#define SEQ_WCSS_WL_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00b80200
#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b802c0
#define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET 0x00b80400
#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b80428
#define SEQ_WCSS_WL_MSIP_RBIST_TX_CH1_OFFSET 0x00b81000
#define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET 0x00b81180
#define SEQ_WCSS_WL_MSIP_WL_DAC_CALIB_CH1_OFFSET 0x00b81190
#define SEQ_WCSS_WL_MSIP_WL_DAC_REGARRAY_CH1_OFFSET 0x00b81200
#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x00b812c0
#define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET 0x00b81400
#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00b81428
#define SEQ_WCSS_WL_MSIP_MSIP_TMUX_OFFSET 0x00b8d000
#define SEQ_WCSS_WL_MSIP_MSIP_OTP_OFFSET 0x00b8d080
#define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0ac
#define SEQ_WCSS_WL_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100
#define SEQ_WCSS_WL_MSIP_MSIP_BIAS_OFFSET 0x00b8e000
#define SEQ_WCSS_WL_MSIP_BBPLL_OFFSET 0x00b8f000
#define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET 0x00b8f100
#define SEQ_WCSS_WL_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00
#define SEQ_WCSS_DBG_OFFSET 0x00b90000
#define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000
#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000
#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000
#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000
#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000
#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000
#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000
#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000
#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000
#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000
#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000
#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000
#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000
#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000
#define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000
#define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000
#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000
#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000
#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000
#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000
#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000
#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000
#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000
#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280
#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000
#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000
#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280
#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000
#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000
#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000
#define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000
#define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000
#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_OFFSET 0x00be0000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_PHYB_NOC_OFFSET 0x00be0000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_ITM_OFFSET 0x00be8000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_DWT_OFFSET 0x00be9000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_FPB_OFFSET 0x00bea000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_SCS_OFFSET 0x00beb000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_ETM_OFFSET 0x00bec000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000
#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000
#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000
#define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000
#define SEQ_WCSS_WCSS_ACMT_OFFSET 0x00c9f000
#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000
#define SEQ_WCSS_CC_OFFSET 0x00cb0000
#define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000
#define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wfax_top
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000
#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400
#define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800
#define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00
#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00082c00
#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00083000
#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000
#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000
#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000
#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000
#define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000
#define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00100000
#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000
#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_from_wsi
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x000142e0
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480
#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800
#define SEQ_RFA_FROM_WSI_RFA_CMN_DPLL_OFFSET 0x00014c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016240
#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00
#define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000
#define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000
#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_HLS_BT_REGFILE_OFFSET 0x0001c400
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001c800
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001c840
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001c880
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001c8c0
#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_cmn
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_CMN_AON_OFFSET 0x00000000
#define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240
#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0
#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x000002e0
#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300
#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400
#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480
#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800
#define SEQ_RFA_CMN_DPLL_OFFSET 0x00000c00
#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000
#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040
#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100
#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140
#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180
#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0
#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002240
#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_pmu
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_PMU_PMU_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_bt
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_BT_BT_CH2_OFFSET 0x00000000
#define SEQ_RFA_BT_HLS_BT_REGFILE_OFFSET 0x00000400
#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00000800
#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00000840
#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00000880
#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x000008c0
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_wl
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000
#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400
#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800
#define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000
#define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300
#define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600
#define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640
#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000
#define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000
#define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000
#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400
#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800
#define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000
#define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300
#define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600
#define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640
#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000
#define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block umac_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000
#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000
#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000
#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000
#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000
#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000
#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000
#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block cxc_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000
#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000
#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000
#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000
#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000
#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wmac_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000
#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000
#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000
#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000
#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000
#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000
#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000
#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000
#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000
#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000
#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000
#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000
#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000
#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block msip
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000
#define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000180
#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00000190
#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00000200
#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000002c0
#define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400
#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00000428
#define SEQ_MSIP_RBIST_TX_CH1_OFFSET 0x00001000
#define SEQ_MSIP_WL_DAC_CH1_OFFSET 0x00001180
#define SEQ_MSIP_WL_DAC_CALIB_CH1_OFFSET 0x00001190
#define SEQ_MSIP_WL_DAC_REGARRAY_CH1_OFFSET 0x00001200
#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x000012c0
#define SEQ_MSIP_WL_ADC_CH1_OFFSET 0x00001400
#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00001428
#define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d000
#define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080
#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0ac
#define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100
#define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000
#define SEQ_MSIP_BBPLL_OFFSET 0x0000f000
#define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET 0x0000f100
#define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wcssdbg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000
#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000
#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000
#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000
#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000
#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000
#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000
#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000
#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000
#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000
#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000
#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000
#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000
#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000
#define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000
#define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000
#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000
#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000
#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000
#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000
#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000
#define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000
#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000
#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280
#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000
#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000
#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280
#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000
#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000
#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000
#define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000
#define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000
#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_OFFSET 0x00050000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_PHYB_NOC_OFFSET 0x00050000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_ITM_OFFSET 0x00058000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_DWT_OFFSET 0x00059000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_FPB_OFFSET 0x0005a000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_SCS_OFFSET 0x0005b000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_ETM_OFFSET 0x0005c000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000
#define SEQ_WCSSDBG_PHYA_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000
#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block tpdm_atb128_cmb64
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280
#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block phyb_dbg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_PHYB_DBG_PHYB_NOC_OFFSET 0x00000000
#define SEQ_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000
#define SEQ_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000
#define SEQ_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000
#define SEQ_PHYB_DBG_ITM_OFFSET 0x00008000
#define SEQ_PHYB_DBG_DWT_OFFSET 0x00009000
#define SEQ_PHYB_DBG_FPB_OFFSET 0x0000a000
#define SEQ_PHYB_DBG_SCS_OFFSET 0x0000b000
#define SEQ_PHYB_DBG_ETM_OFFSET 0x0000c000
#define SEQ_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000
#define SEQ_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss_wlan
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_OFFSET 0x00000000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss_public
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss_private
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000
#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000
#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000
#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block q6ss_rscc
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000
#endif

49
hw/qca5018/wcss_seq_hwiobase_ext.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/8/2019
// User Name:dsriniva
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __WCSS_SEQ_BASE_EXT_H__
#define __WCSS_SEQ_BASE_EXT_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_CSR_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_L2VIC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_RSCC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET
#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6V67SS_PUB_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET
#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET
#endif

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hw/qca5018/wcss_version.h Normal file
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/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define WCSS_VERSION 55

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hw/qca5018/wfss_ce_reg_seq_hwioreg.h Normal file
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51
hw/qca5018/wfss_pmm_base_struct.h Normal file
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/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
//////////////////////////////////////////////////////////////////////////////
// wfss_pmm_base_struct.h generated by: GenCStruct.pm
//////////////////////////////////////////////////////////////////////////////
// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// RCS File : -USE CVS LOG-
// Revision : -USE CVS LOG-
// Last Check In : -USE CVS LOG-
//////////////////////////////////////////////////////////////////////////////
// Description : Top C Struct file
//
//////////////////////////////////////////////////////////////////////////////
#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#ifdef _LSB_TO_MSB_REGS
#ifdef _MSB_TO_LSB_REGS
#error You can not define both _LSB_TO_MSB_REGS and _MSB_TO_LSB_REGS!
#endif
#define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#include "wfss_pmm_base_struct_ltm.h"
#endif
#ifdef _MSB_TO_LSB_REGS
#define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#include "wfss_pmm_base_struct_mtl.h"
#endif
#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#error You have to define _LSB_TO_MSB_REGS or _MSB_TO_LSB_REGS
#endif
#endif