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Add 'qcom/opensource/camera-kernel/' from commit 'e28c84a69982150918a8a8c48c730ac1c2c5ce34'

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git-subtree-dir: qcom/opensource/camera-kernel
git-subtree-mainline: 7870029999
git-subtree-split: e28c84a699
Change-Id:
repo: https://git.codelinaro.org/clo/la/platform/vendor/opensource/camera-kernel
tag: CAMERA.LA.4.0.r2-07000-lanai.0
This commit is contained in:
David Wronek 2024-10-06 16:44:01 +02:00
commit 78e1eefbdb
590 changed files with 368802 additions and 0 deletions
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5
qcom/opensource/camera-kernel/.gitignore vendored Normal file
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clangd*
.cache
compile_commands.json
cscope*
cam_generated_h

99
qcom/opensource/camera-kernel/Android.mk Normal file
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CAMERA_DLKM_ENABLED := true
ifeq ($(TARGET_KERNEL_DLKM_DISABLE), true)
ifeq ($(TARGET_KERNEL_DLKM_CAMERA_OVERRIDE), false)
CAMERA_DLKM_ENABLED := false;
endif
endif
ifeq ($(CAMERA_DLKM_ENABLED),true)
ifeq ($(call is-board-platform-in-list, $(TARGET_BOARD_PLATFORM)),true)
# Make target to specify building the camera.ko from within Android build system.
LOCAL_PATH := $(call my-dir)
# Path to DLKM make scripts
DLKM_DIR := $(TOP)/device/qcom/common/dlkm
LOCAL_MODULE_DDK_BUILD := true
LOCAL_MODULE_DDK_SUBTARGET_REGEX := "camera.*"
ifeq ($(TARGET_BOARD_PLATFORM), volcano)
LOCAL_MODULE_DDK_SUBTARGET_REGEX := "$(TARGET_BOARD_PLATFORM)_camera.*"
endif
# List of board platforms for which MMRM driver API should be enabled
MMRM_BOARDS := taro parrot kalama pineapple crow volcano
# List of board platforms for which Synx V2 vendor driver API should be enabled
SYNX_VENDOR_BOARDS := pineapple
# List of board platforms for which SMCINVOKE_DLKM driver API should be enabled
SMCINVOKE_DLKM_BOARDS := pineapple
# List of board platforms for which SMMU_PROXY_DLKM driver API should be enabled
SMMU_PROXY_DLKM_BOARDS := pineapple
CAMERA_SRC_FILES := \
$(addprefix $(LOCAL_PATH)/, $(call all-named-files-under,*.h,drivers dt-bindings include))\
$(addprefix $(LOCAL_PATH)/, $(call all-named-files-under,*.mk,config))\
$(addprefix $(LOCAL_PATH)/, $(call all-named-files-under,*.c,drivers))\
$(LOCAL_PATH)/dependency.mk \
$(LOCAL_PATH)/board.mk \
$(LOCAL_PATH)/product.mk \
$(LOCAL_PATH)/Kbuild
# Target for pre-sil symbols
ifeq ($(CONFIG_CAM_PRESIL), y)
$(warning camera-kernel: Enabling Pre-Sil Kbuild Options!)
KBUILD_OPTIONS := CONFIG_CAM_PRESIL=y
include $(CLEAR_VARS)
$(warning camera-kernel: Enabling Pre-Sil build, exporting symbols!)
LOCAL_SRC_FILES := $(CAMERA_SRC_FILES)
LOCAL_MODULE := camera-kernel-symvers
LOCAL_MODULE_STEM := Module.symvers
LOCAL_MODULE_KBUILD_NAME := Module.symvers
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
# Check build for optional dependencies
include $(LOCAL_PATH)/dependency.mk
include $(DLKM_DIR)/Build_external_kernelmodule.mk
endif
# Kbuild options
KBUILD_OPTIONS := CAMERA_KERNEL_ROOT=$(TOP)/$(LOCAL_PATH)
KBUILD_OPTIONS += KERNEL_ROOT=$(TOP)/kernel_platform/common
KBUILD_OPTIONS += MODNAME=camera
KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
# Clear shell environment variables from previous android module during build
include $(CLEAR_VARS)
# For incremental compilation support.
LOCAL_SRC_FILES := $(CAMERA_SRC_FILES)
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
LOCAL_MODULE := camera.ko
LOCAL_MODULE_TAGS := optional
#LOCAL_MODULE_KBUILD_NAME := camera.ko
#LOCAL_MODULE_DEBUG_ENABLE := true
# Check build for optional dependencies
include $(LOCAL_PATH)/dependency.mk
# $(info LOCAL_SRC_FILES = $(LOCAL_SRC_FILES))
# $(info intermediates mmrm symvers path = $(call intermediates-dir-for,DLKM,mmrm-module-symvers))
# $(info CAMERA_EXTRA_SYMBOLS = $(CAMERA_EXTRA_SYMBOLS))
# $(info CAMERA_EXTRA_CONFIGS = $(CAMERA_EXTRA_CONFIGS))
# $(info LOCAL_ADDITIONAL_DEPENDENCIES = $(LOCAL_ADDITIONAL_DEPENDENCIES))
# $(info LOCAL_REQUIRED_MODULES = $(LOCAL_REQUIRED_MODULES))
# $(info DLKM_DIR = $(DLKM_DIR))
$(info KBUILD_OPTIONS = $(KBUILD_OPTIONS))
ifeq ($(TARGET_BOARD_PLATFORM), lahaina)
# Include Kernel DLKM Android.mk target to place generated .ko file in image
include $(DLKM_DIR)/AndroidKernelModule.mk
# Include Camera UAPI Android.mk target to copy headers
include $(LOCAL_PATH)/include/uapi/Android.mk
else
include $(DLKM_DIR)/Build_external_kernelmodule.mk
endif
endif # End of check for board platform
endif # ifeq ($(CAMERA_DLKM_ENABLED),true)

153
qcom/opensource/camera-kernel/BUILD.bazel Normal file
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package(
default_visibility = [
"//visibility:public",
],
)
load("//build/kernel/kleaf:kernel.bzl", "ddk_headers")
ddk_headers(
name = "camera_uapi_headers",
hdrs = glob(["include/uapi/camera/**/*.h"]),
includes = [
"include/uapi/camera",
"include/uapi/camera/media",
],
)
driver_header_globs = [
"drivers/**/*.h",
"drivers/camera_main.h",
"dt-bindings/msm-camera.h",
]
# Generated list with: find drivers -type f -name '*.h' -printf '"%h",\n' | sort -u
driver_includes = [
"drivers",
"drivers/cam_cdm",
"drivers/cam_core",
"drivers/cam_cpas",
"drivers/cam_cpas/cpas_top",
"drivers/cam_cpas/include",
"drivers/cam_cre",
"drivers/cam_cre/cam_cre_hw_mgr",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/include",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top",
"drivers/cam_cust",
"drivers/cam_cust/cam_custom_hw_mgr",
"drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid",
"drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1",
"drivers/cam_cust/cam_custom_hw_mgr/include",
"drivers/cam_fd",
"drivers/cam_fd/fd_hw_mgr",
"drivers/cam_fd/fd_hw_mgr/fd_hw",
"drivers/cam_icp",
"drivers/cam_icp/fw_inc",
"drivers/cam_icp/icp_hw/bps_hw",
"drivers/cam_icp/icp_hw/icp_hw_mgr",
"drivers/cam_icp/icp_hw/icp_hw_mgr/include",
"drivers/cam_icp/icp_hw/icp_proc",
"drivers/cam_icp/icp_hw/icp_proc/icp_common",
"drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw",
"drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw",
"drivers/cam_icp/icp_hw/include",
"drivers/cam_icp/icp_hw/ipe_hw",
"drivers/cam_icp/icp_hw/ofe_hw",
"drivers/cam_isp",
"drivers/cam_isp/isp_hw_mgr",
"drivers/cam_isp/isp_hw_mgr/hw_utils/include",
"drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller",
"drivers/cam_isp/isp_hw_mgr/include",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw",
"drivers/cam_isp/isp_hw_mgr/isp_hw/include",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/include",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include",
"drivers/cam_jpeg",
"drivers/cam_jpeg/jpeg_hw",
"drivers/cam_jpeg/jpeg_hw/include",
"drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw",
"drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw",
"drivers/cam_lrme",
"drivers/cam_lrme/lrme_hw_mgr",
"drivers/cam_lrme/lrme_hw_mgr/lrme_hw",
"drivers/cam_ope",
"drivers/cam_ope/ope_hw_mgr",
"drivers/cam_ope/ope_hw_mgr/ope_hw",
"drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd",
"drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr",
"drivers/cam_ope/ope_hw_mgr/ope_hw/top",
"drivers/cam_presil/inc",
"drivers/cam_req_mgr",
"drivers/cam_sensor_module/cam_actuator",
"drivers/cam_sensor_module/cam_cci",
"drivers/cam_sensor_module/cam_csiphy",
"drivers/cam_sensor_module/cam_csiphy/include",
"drivers/cam_sensor_module/cam_eeprom",
"drivers/cam_sensor_module/cam_flash",
"drivers/cam_sensor_module/cam_ois",
"drivers/cam_sensor_module/cam_res_mgr",
"drivers/cam_sensor_module/cam_sensor",
"drivers/cam_sensor_module/cam_sensor_io",
"drivers/cam_sensor_module/cam_sensor_utils",
"drivers/cam_sensor_module/cam_tpg",
"drivers/cam_sensor_module/cam_tpg/tpg_hw",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_0",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_2",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_4",
"drivers/cam_smmu",
"drivers/cam_sync",
"drivers/cam_utils",
]
ddk_headers(
name = "camera_src_headers",
hdrs = glob(driver_header_globs),
includes = driver_includes + [
".",
],
)
ddk_headers(
name = "camera_headers",
hdrs = [
":camera_src_headers",
":camera_uapi_headers",
],
)
genrule(
name = "camera_banner_header",
srcs = [],
outs = ["cam_generated.h"],
cmd = """
{
printf '#define CAMERA_COMPILE_TIME "%s"\n' "$$(date)"
printf '#define CAMERA_COMPILE_BY "%s"\n' "$$(whoami)"
printf '#define CAMERA_COMPILE_HOST "%s"\n' "$$(uname -n)"
} > "$@"
"""
)
ddk_headers(
name = "camera_banner",
hdrs = [":camera_banner_header"],
)
load(":camera_modules.bzl", "define_camera_module")
define_camera_module()

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qcom/opensource/camera-kernel/Kbuild Normal file
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# SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_QCOM_CAMERA_DEBUG), y)
$(info "CAMERA_KERNEL_ROOT is: $(CAMERA_KERNEL_ROOT)")
$(info "KERNEL_ROOT is: $(KERNEL_ROOT)")
endif
# Include Architecture configurations
ifeq ($(CONFIG_ARCH_CLIFFS), y)
include $(CAMERA_KERNEL_ROOT)/config/cliffs.mk
endif
ifeq ($(CONFIG_ARCH_WAIPIO), y)
include $(CAMERA_KERNEL_ROOT)/config/waipio.mk
endif
ifeq ($(CONFIG_ARCH_LAHAINA), y)
include $(CAMERA_KERNEL_ROOT)/config/lahaina.mk
endif
ifeq ($(CONFIG_ARCH_KONA), y)
include $(CAMERA_KERNEL_ROOT)/config/kona.mk
endif
ifeq ($(CONFIG_ARCH_BENGAL), y)
include $(CAMERA_KERNEL_ROOT)/config/holi.mk
endif
ifeq ($(CONFIG_ARCH_HOLI), y)
include $(CAMERA_KERNEL_ROOT)/config/holi.mk
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(CAMERA_KERNEL_ROOT)/config/lito.mk
endif
ifeq ($(CONFIG_ARCH_SHIMA), y)
include $(CAMERA_KERNEL_ROOT)/config/shima.mk
endif
ifeq ($(CONFIG_ARCH_DIWALI), y)
include $(CAMERA_KERNEL_ROOT)/config/diwali.mk
endif
ifeq ($(CONFIG_ARCH_CAPE), y)
include $(CAMERA_KERNEL_ROOT)/config/cape.mk
endif
ifeq ($(CONFIG_ARCH_PARROT), y)
include $(CAMERA_KERNEL_ROOT)/config/parrot.mk
endif
# For some targets which have binary compatible gki kernel with another one,
# we cannot rely on CONFIG_ARCH_* symbol which is defined in Kernel defconfig
ifeq ($(BOARD_PLATFORM), kalama)
include $(CAMERA_KERNEL_ROOT)/config/kalama.mk
endif
ifeq ($(BOARD_PLATFORM), crow)
include $(CAMERA_KERNEL_ROOT)/config/crow.mk
endif
ifeq ($(BOARD_PLATFORM), pineapple)
include $(CAMERA_KERNEL_ROOT)/config/pineapple.mk
endif
ifeq ($(BOARD_PLATFORM), volcano)
include $(CAMERA_KERNEL_ROOT)/config/volcano.mk
endif
ifneq ($(KBUILD_EXTRA_CONFIGS),)
include $(KBUILD_EXTRA_CONFIGS)
endif
# List of all camera-kernel headers
cam_include_dirs := $(shell dirname `find $(CAMERA_KERNEL_ROOT) -name '*.h'` | uniq)
# Include UAPI headers
USERINCLUDE += \
-I$(CAMERA_KERNEL_ROOT)/include/uapi/
# Include Kernel headers
LINUXINCLUDE += \
-I$(KERNEL_ROOT) \
$(addprefix -I,$(cam_include_dirs)) \
-I$(CAMERA_KERNEL_ROOT)/include/uapi/camera \
-I$(CAMERA_KERNEL_ROOT)/
# Optional include directories
SYNXVENDORDIR=$(CAMERA_KERNEL_ROOT)/../synx-kernel
ccflags-$(CONFIG_MSM_GLOBAL_SYNX) += -I$(KERNEL_ROOT)/drivers/media/platform/msm/synx
ccflags-$(TARGET_SYNX_ENABLE) += -I$(SYNXVENDORDIR)/include/uapi/synx/media
ccflags-$(TARGET_SYNX_ENABLE) += -I$(SYNXVENDORDIR)/msm/synx
ccflags-$(TARGET_SYNX_ENABLE) += -DCONFIG_TARGET_SYNX_ENABLE=1
ccflags-y += -I$(CAMERA_KERNEL_ROOT)/../securemsm-kernel/
ccflags-y += -I$(CAMERA_KERNEL_ROOT)/../securemsm-kernel/include/
# After creating lists, add content of 'ccflags-m' variable to 'ccflags-y' one.
ccflags-y += ${ccflags-m}
camera-y := \
drivers/cam_req_mgr/cam_req_mgr_core.o \
drivers/cam_req_mgr/cam_req_mgr_dev.o \
drivers/cam_req_mgr/cam_req_mgr_util.o \
drivers/cam_req_mgr/cam_mem_mgr.o \
drivers/cam_req_mgr/cam_req_mgr_workq.o \
drivers/cam_req_mgr/cam_req_mgr_timer.o \
drivers/cam_req_mgr/cam_req_mgr_debug.o \
drivers/cam_utils/cam_soc_util.o \
drivers/cam_utils/cam_packet_util.o \
drivers/cam_utils/cam_debug_util.o \
drivers/cam_utils/cam_trace.o \
drivers/cam_utils/cam_common_util.o \
drivers/cam_utils/cam_compat.o \
drivers/cam_core/cam_context.o \
drivers/cam_core/cam_context_utils.o \
drivers/cam_core/cam_node.o \
drivers/cam_core/cam_subdev.o \
drivers/cam_smmu/cam_smmu_api.o \
drivers/cam_sync/cam_sync.o \
drivers/cam_sync/cam_sync_util.o \
drivers/cam_sync/cam_sync_dma_fence.o \
drivers/cam_cpas/cpas_top/cam_cpastop_hw.o \
drivers/cam_cpas/camss_top/cam_camsstop_hw.o \
drivers/cam_cpas/cam_cpas_soc.o \
drivers/cam_cpas/cam_cpas_intf.o \
drivers/cam_cpas/cam_cpas_hw.o \
drivers/cam_cdm/cam_cdm_soc.o \
drivers/cam_cdm/cam_cdm_util.o \
drivers/cam_cdm/cam_cdm_intf.o \
drivers/cam_cdm/cam_cdm_core_common.o \
drivers/cam_cdm/cam_cdm_virtual_core.o \
drivers/cam_cdm/cam_cdm_hw_core.o
ifeq (,$(filter $(CONFIG_CAM_PRESIL),y m))
camera-y += drivers/cam_presil/stub/cam_presil_hw_access_stub.o
camera-y += drivers/cam_utils/cam_io_util.o
else
camera-y += drivers/cam_presil/presil/cam_presil_io_util.o
camera-y += drivers/cam_presil/presil/cam_presil_hw_access.o
camera-y += drivers/cam_presil/presil_framework_dev/cam_presil_framework_dev.o
ccflags-y += -DCONFIG_CAM_PRESIL=1
endif
camera-$(TARGET_SYNX_ENABLE) += drivers/cam_sync/cam_sync_synx.o
camera-$(CONFIG_QCOM_CX_IPEAK) += drivers/cam_utils/cam_cx_ipeak.o
camera-$(CONFIG_QCOM_BUS_SCALING) += drivers/cam_utils/cam_soc_bus.o
camera-$(CONFIG_INTERCONNECT_QCOM) += drivers/cam_utils/cam_soc_icc.o
camera-$(CONFIG_SPECTRA_ISP) += \
drivers/cam_isp/isp_hw_mgr/hw_utils/cam_tasklet_util.o \
drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.o \
drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_soc.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_core.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.o \
drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.o \
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.o \
drivers/cam_isp/cam_isp_dev.o \
drivers/cam_isp/cam_isp_context.o
camera-$(CONFIG_SPECTRA_ICP) += \
drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.o \
drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.o \
drivers/cam_icp/icp_hw/ipe_hw/ipe_core.o \
drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.o \
drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_dev.o \
drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_core.o \
drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_dev.o \
drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_core.o \
drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_proc_common.o \
drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_soc_common.o \
drivers/cam_icp/icp_hw/icp_proc/cam_icp_proc.o \
drivers/cam_icp/icp_hw/bps_hw/bps_dev.o \
drivers/cam_icp/icp_hw/bps_hw/bps_core.o \
drivers/cam_icp/icp_hw/bps_hw/bps_soc.o \
drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.o \
drivers/cam_icp/icp_hw/ofe_hw/ofe_core.o \
drivers/cam_icp/icp_hw/ofe_hw/ofe_soc.o \
drivers/cam_icp/cam_icp_subdev.o \
drivers/cam_icp/cam_icp_context.o \
drivers/cam_icp/hfi.o
camera-$(CONFIG_SPECTRA_JPEG) += \
drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.o \
drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.o \
drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.o \
drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.o \
drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.o \
drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.o \
drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.o \
drivers/cam_jpeg/cam_jpeg_dev.o \
drivers/cam_jpeg/cam_jpeg_context.o
camera-$(CONFIG_SPECTRA_FD) += \
drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.o \
drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.o \
drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.o \
drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.o \
drivers/cam_fd/cam_fd_dev.o \
drivers/cam_fd/cam_fd_context.o
camera-$(CONFIG_SPECTRA_LRME) += \
drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.o \
drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.o \
drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.o \
drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.o \
drivers/cam_lrme/cam_lrme_dev.o \
drivers/cam_lrme/cam_lrme_context.o
camera-$(CONFIG_SPECTRA_SENSOR) += \
drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.o \
drivers/cam_sensor_module/cam_actuator/cam_actuator_core.o \
drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.o \
drivers/cam_sensor_module/cam_cci/cam_cci_dev.o \
drivers/cam_sensor_module/cam_cci/cam_cci_core.o \
drivers/cam_sensor_module/cam_cci/cam_cci_soc.o \
drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.o \
drivers/cam_sensor_module/cam_tpg/cam_tpg_core.o \
drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.o \
drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_common.o \
drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_0/tpg_hw_v_1_0.o \
drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_2/tpg_hw_v_1_2.o \
drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.o \
drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_4/tpg_hw_v_1_4.o \
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.o \
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.o \
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.o \
drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.o \
drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.o \
drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.o \
drivers/cam_sensor_module/cam_ois/cam_ois_dev.o \
drivers/cam_sensor_module/cam_ois/cam_ois_core.o \
drivers/cam_sensor_module/cam_ois/cam_ois_soc.o \
drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.o \
drivers/cam_sensor_module/cam_sensor/cam_sensor_core.o \
drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.o \
drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.o \
drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.o \
drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.o \
drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i3c.o \
drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.o \
drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.o \
drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.o \
drivers/cam_sensor_module/cam_flash/cam_flash_dev.o \
drivers/cam_sensor_module/cam_flash/cam_flash_core.o \
drivers/cam_sensor_module/cam_flash/cam_flash_soc.o \
drivers/cam_sensor_module/cam_sensor_module_debug.o
camera-$(CONFIG_SPECTRA_CUSTOM) += \
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.o \
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.o \
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.o \
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.o \
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.o \
drivers/cam_cust/cam_custom_dev.o \
drivers/cam_cust/cam_custom_context.o
camera-$(CONFIG_SPECTRA_OPE) += \
drivers/cam_ope/cam_ope_subdev.o \
drivers/cam_ope/cam_ope_context.o \
drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.o \
drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.o \
drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.o \
drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.o \
drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.o \
drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.o\
drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.o
camera-$(CONFIG_SPECTRA_CRE) += \
drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.o \
drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_soc.o \
drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.o \
drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top/cre_top.o \
drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.o \
drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.o \
drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.o \
drivers/cam_cre/cam_cre_dev.o \
drivers/cam_cre/cam_cre_context.o
camera-$(CONFIG_SPECTRA_TFE) += \
drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.o \
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid.o \
drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.o
camera-y += drivers/camera_main.o
obj-m += camera.o
BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/camera.ko

116
qcom/opensource/camera-kernel/Kconfig Normal file
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config SPECTRA_ISP
bool "enable camera ISP module"
help
This is enabling camera ISP module.
IFE camera driver file be included.
This will enable camera ISP driver to handle IFE driver.
Core camera driver to handle VFE HW.
config SPECTRA_TFE
bool "enable camera tfe modele"
help
This is enabling camera tfe module.
tfe module files will be included to enable tfe based driver,
files.
config SPECTRA_ICP
bool "enable camera ICP module"
help
This is enabling camera ICP module.
Camera ICP driver file be included.
This will enable camera ICP driver to interact with,
ICP FW. Which can control IPE and BPS HW.
config SPECTRA_JPEG
bool "enable camera jpeg module"
help
This is enabling camera JPEG module.
camera jpeg module will be functional.
This module interact with jpeg HW for
snapshot processing.
config SPECTRA_CRE
bool "enable camera jpeg module"
help
This is enabling camera CRE module.
camera cre module will be functional.
This module interact with cre HW for
format conversion.
config SPECTRA_SENSOR
bool "enable camera sensor module"
help
This is enabling camera sensor module.
sensor module files will be included to enable the driver.
eeprom, flash, csiphy all other module will be included
to make the sensor functional.
config SPECTRA_USE_CLK_CRM_API
bool "enable camera cesta clk feature"
help
This is enabling camera cesta feature.
kernel clk driver api will cache the clk value
send by camera hw and apply to CRM hw.
CRM hw will consolidate and apply the clk to camera HW.
config SPECTRA_USE_RPMH_DRV_API
bool "enable camera new ICC BW api"
help
This is helping to set BW through kernel icc driver.
Kernel icc driver do caching the bw information.
icc driver will update the bw information RPMH,
to apply proper bw voting for camera to mmnoc
config SPECTRA_LLCC_STALING
bool "enable camera new LLCC staling feature"
help
This will enable to call LLCC driver cache notification API
and increment count API.
Which will enable LLCC staling feature,based on counter
invalidate the cache slice.
config TARGET_SYNX_ENABLE
bool "enable HW synx"
help
This is enabling HW syx feature.
synx hw signaling external to camera,
like EVA and other.
This is to avoid sw signaling latency.
config MSM_MMRM
bool "enable MSM MMRM"
help
This is enabling mmrm api access.
mmrm to cahce the clk voting.
mmrm knows about all clients' clock rates.
MMRM can decide whether new peak power usage is within allowed value
config INTERCONNECT_QCOM
bool "enabling icc bus driver"
help
This is to access icc driver api.
To cache AB and IB vote will
use ICC kernel driver API.
So that ICC driver can consolidate the vote
config DOMAIN_ID_SECURE_CAMERA
bool "enable domain ID based secure camera flow"
help
This is to enable domain ID based secure
camera flow on the hardware platforms with
domain ID based security architecture.
VC based security can be achieved with this.
config CSF_2_5_SECURE_CAMERA
bool "enable CSF2.5 feature flow"
help
This is to enable Call flow for CSF2.5
enabled platforms. this config differentiates
between csf2.0 and csf 2.5 compliant
scm calls.
config DYNAMIC_FD_PORT_CONFIG
bool "enable dynamic FD port config feature"
help
This config enables dynamic FD port config
feature that allows the userspace to configure
the FD port to secure or non-secure based on
the FD solution in use in secure camera use cases.

27
qcom/opensource/camera-kernel/Makefile Normal file
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# Makefile for use with Android's kernel/build system
KBUILD_OPTIONS += CAMERA_KERNEL_ROOT=$(shell pwd)
KBUILD_OPTIONS += KERNEL_ROOT=$(ROOT_DIR)/$(KERNEL_DIR)
KBUILD_OPTIONS += MODNAME=camera
all: modules
CAMERA_COMPILE_TIME = $(shell date)
CAMERA_COMPILE_BY = $(shell whoami | sed 's/\\/\\\\/')
CAMERA_COMPILE_HOST = $(shell uname -n)
cam_generated_h: $(shell find . -iname "*.c") $(shell find . -iname "*.h") $(shell find . -iname "*.mk")
echo '#define CAMERA_COMPILE_TIME "$(CAMERA_COMPILE_TIME)"' > cam_generated_h
echo '#define CAMERA_COMPILE_BY "$(CAMERA_COMPILE_BY)"' >> cam_generated_h
echo '#define CAMERA_COMPILE_HOST "$(CAMERA_COMPILE_HOST)"' >> cam_generated_h
modules: cam_generated_h
modules dtbs:
$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS)
modules_install:
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

15
qcom/opensource/camera-kernel/board.mk Normal file
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# Build camera kernel driver
CAMERA_DLKM_ENABLED := true
ifeq ($(TARGET_KERNEL_DLKM_DISABLE), true)
ifeq ($(TARGET_KERNEL_DLKM_CAMERA_OVERRIDE), false)
CAMERA_DLKM_ENABLED := false;
endif
endif
ifeq ($(CAMERA_DLKM_ENABLED),true)
ifneq ($(TARGET_BOARD_AUTO),true)
ifeq ($(call is-board-platform-in-list,$(TARGET_BOARD_PLATFORM)),true)
BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/camera.ko
endif
endif
endif

292
qcom/opensource/camera-kernel/camera_modules.bzl Normal file
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load("//build/kernel/kleaf:kernel.bzl", "ddk_module")
load("//build/bazel_common_rules/dist:dist.bzl", "copy_to_dist_dir")
load("//msm-kernel:target_variants.bzl", "get_all_variants")
load("//msm-kernel:target_variants.bzl", "get_all_lunch_target_base_target_variants")
def _define_module(target, variant, lunch_target=None):
if lunch_target:
tv = "{}_{}".format(target, variant)
tvl = "{}_{}_{}".format(target, variant, lunch_target)
ddk_mod_name = "{}_camera".format(tvl)
defconfig = "{}_defconfig".format(lunch_target)
else:
tv = "{}_{}".format(target, variant)
ddk_mod_name = "{}_camera".format(tv)
defconfig = "{}_defconfig".format(target)
deps = [
":camera_headers",
":camera_banner",
"//msm-kernel:all_headers",
"//vendor/qcom/opensource/securemsm-kernel:smcinvoke_kernel_headers",
"//vendor/qcom/opensource/securemsm-kernel:smmu_proxy_headers",
"//vendor/qcom/opensource/securemsm-kernel:{}_smcinvoke_dlkm".format(tv),
"//vendor/qcom/opensource/securemsm-kernel:{}_smmu_proxy_dlkm".format(tv),
"//vendor/qcom/opensource/mmrm-driver:{}_mmrm_driver".format(tv),
]
if target == "pineapple":
deps.extend([
"//vendor/qcom/opensource/synx-kernel:synx_headers",
"//vendor/qcom/opensource/synx-kernel:{}_modules".format(tv),
])
ddk_module(
name = ddk_mod_name,
out = "camera.ko",
srcs = [
"drivers/cam_req_mgr/cam_req_mgr_core.c",
"drivers/cam_req_mgr/cam_req_mgr_dev.c",
"drivers/cam_req_mgr/cam_req_mgr_util.c",
"drivers/cam_req_mgr/cam_mem_mgr.c",
"drivers/cam_req_mgr/cam_req_mgr_workq.c",
"drivers/cam_req_mgr/cam_req_mgr_timer.c",
"drivers/cam_req_mgr/cam_req_mgr_debug.c",
"drivers/cam_utils/cam_soc_util.c",
"drivers/cam_utils/cam_packet_util.c",
"drivers/cam_utils/cam_debug_util.c",
"drivers/cam_utils/cam_trace.c",
"drivers/cam_utils/cam_common_util.c",
"drivers/cam_utils/cam_compat.c",
"drivers/cam_core/cam_context.c",
"drivers/cam_core/cam_context_utils.c",
"drivers/cam_core/cam_node.c",
"drivers/cam_core/cam_subdev.c",
"drivers/cam_smmu/cam_smmu_api.c",
"drivers/cam_sync/cam_sync.c",
"drivers/cam_sync/cam_sync_util.c",
"drivers/cam_sync/cam_sync_dma_fence.c",
"drivers/cam_cpas/cpas_top/cam_cpastop_hw.c",
"drivers/cam_cpas/camss_top/cam_camsstop_hw.c",
"drivers/cam_cpas/cam_cpas_soc.c",
"drivers/cam_cpas/cam_cpas_intf.c",
"drivers/cam_cpas/cam_cpas_hw.c",
"drivers/cam_cdm/cam_cdm_soc.c",
"drivers/cam_cdm/cam_cdm_util.c",
"drivers/cam_cdm/cam_cdm_intf.c",
"drivers/cam_cdm/cam_cdm_core_common.c",
"drivers/cam_cdm/cam_cdm_virtual_core.c",
"drivers/cam_cdm/cam_cdm_hw_core.c",
"drivers/cam_utils/cam_soc_icc.c",
"drivers/camera_main.c",
],
conditional_srcs = {
"CONFIG_TARGET_SYNX_ENABLE": {
True: ["drivers/cam_sync/cam_sync_synx.c"],
},
"CONFIG_QCOM_CX_IPEAK": {
True: ["drivers/cam_utils/cam_cx_ipeak.c"],
},
"CONFIG_INTERCONNECT_QCOM": {
True: ["drivers/cam_utils/cam_soc_icc.c"],
},
"CONFIG_SPECTRA_ISP": {
True: [
"drivers/cam_isp/isp_hw_mgr/hw_utils/cam_tasklet_util.c",
"drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c",
"drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_soc.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_core.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c",
"drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c",
"drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c",
"drivers/cam_isp/cam_isp_dev.c",
"drivers/cam_isp/cam_isp_context.c",
],
},
"CONFIG_SPECTRA_ICP": {
True: [
"drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c",
"drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c",
"drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c",
"drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c",
"drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_dev.c",
"drivers/cam_icp/icp_hw/icp_proc/icp_v1_hw/cam_icp_v1_core.c",
"drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_dev.c",
"drivers/cam_icp/icp_hw/icp_proc/icp_v2_hw/cam_icp_v2_core.c",
"drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_proc_common.c",
"drivers/cam_icp/icp_hw/icp_proc/icp_common/cam_icp_soc_common.c",
"drivers/cam_icp/icp_hw/icp_proc/cam_icp_proc.c",
"drivers/cam_icp/icp_hw/bps_hw/bps_dev.c",
"drivers/cam_icp/icp_hw/bps_hw/bps_core.c",
"drivers/cam_icp/icp_hw/bps_hw/bps_soc.c",
"drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.c",
"drivers/cam_icp/icp_hw/ofe_hw/ofe_core.c",
"drivers/cam_icp/icp_hw/ofe_hw/ofe_soc.c",
"drivers/cam_icp/cam_icp_subdev.c",
"drivers/cam_icp/cam_icp_context.c",
"drivers/cam_icp/hfi.c",
],
},
"CONFIG_SPECTRA_TFE": {
True: [
"drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c",
"drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c",
"drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c",
],
},
"CONFIG_SPECTRA_JPEG": {
True: [
"drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c",
"drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c",
"drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.c",
"drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c",
"drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c",
"drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.c",
"drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c",
"drivers/cam_jpeg/cam_jpeg_dev.c",
"drivers/cam_jpeg/cam_jpeg_context.c",
],
},
"CONFIG_SPECTRA_CRE": {
True: [
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_soc.c",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top/cre_top.c",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c",
"drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c",
"drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c",
"drivers/cam_cre/cam_cre_dev.c",
"drivers/cam_cre/cam_cre_context.c",
],
},
"CONFIG_SPECTRA_SENSOR": {
True: [
"drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c",
"drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c",
"drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.c",
"drivers/cam_sensor_module/cam_cci/cam_cci_dev.c",
"drivers/cam_sensor_module/cam_cci/cam_cci_core.c",
"drivers/cam_sensor_module/cam_cci/cam_cci_soc.c",
"drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.c",
"drivers/cam_sensor_module/cam_tpg/cam_tpg_core.c",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.c",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_common.c",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_0/tpg_hw_v_1_0.c",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_2/tpg_hw_v_1_2.c",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.c",
"drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_4/tpg_hw_v_1_4.c",
"drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c",
"drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c",
"drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c",
"drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.c",
"drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c",
"drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.c",
"drivers/cam_sensor_module/cam_ois/cam_ois_dev.c",
"drivers/cam_sensor_module/cam_ois/cam_ois_core.c",
"drivers/cam_sensor_module/cam_ois/cam_ois_soc.c",
"drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c",
"drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c",
"drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c",
"drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.c",
"drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c",
"drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c",
"drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i3c.c",
"drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.c",
"drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c",
"drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c",
"drivers/cam_sensor_module/cam_flash/cam_flash_dev.c",
"drivers/cam_sensor_module/cam_flash/cam_flash_core.c",
"drivers/cam_sensor_module/cam_flash/cam_flash_soc.c",
"drivers/cam_sensor_module/cam_sensor_module_debug.c",
],
},
"CONFIG_SPECTRA_CUSTOM": {
True: [
"drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.c",
"drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.c",
"drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.c",
"drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c",
"drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c",
"drivers/cam_cust/cam_custom_dev.c",
"drivers/cam_cust/cam_custom_context.c",
],
},
"CONFIG_QCOM_BUS_SCALING": {
True: ["drivers/cam_utils/cam_soc_bus.c"],
},
"CONFIG_CAM_PRESIL": {
# Sources need to be available to specify
# True: [
# "drivers/cam_presil/presil/cam_presil_io_util.c",
# "drivers/cam_presil/presil/cam_presil_hw_access.c",
# "drivers/cam_presil/presil_framework_dev/cam_presil_framework_dev.c",
# ],
False: [
"drivers/cam_presil/stub/cam_presil_hw_access_stub.c",
"drivers/cam_utils/cam_io_util.c",
],
},
},
copts = ["-Wno-implicit-fallthrough", "-include", "$(location :camera_banner)"],
deps = deps,
kconfig = "Kconfig",
defconfig = defconfig,
kernel_build = "//msm-kernel:{}".format(tv),
)
if lunch_target:
dist_target_name = "{}_camera_dist".format(tvl)
data = [":{}_camera".format(tvl)]
else:
dist_target_name = "{}_camera_dist".format(tv)
data = [":{}_camera".format(tv)]
copy_to_dist_dir(
name = dist_target_name,
data = data,
dist_dir = "out/target/product/{}/dlkm/lib/modules/".format(target),
flat = True,
wipe_dist_dir = False,
allow_duplicate_filenames = False,
mode_overrides = {"**/*": "644"},
)
def define_camera_module():
for (t, v) in get_all_variants():
_define_module(t, v)
for (lt, bt, v) in get_all_lunch_target_base_target_variants():
_define_module(bt, v, lt)

22
qcom/opensource/camera-kernel/config/cape.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
# Settings for compiling cape camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_CUSTOM := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_CUSTOM=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
# External Dependencies
KBUILD_CPPFLAGS += -DCONFIG_MSM_MMRM=1
ifeq ($(CONFIG_QCOM_VA_MINIDUMP), y)
KBUILD_CPPFLAGS += -DCONFIG_QCOM_VA_MINIDUMP=1
endif

29
qcom/opensource/camera-kernel/config/cliffs.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_SENSOR := y
CONFIG_SPECTRA_LLCC_STALING := y
CONFIG_SPECTRA_USE_RPMH_DRV_API := y
CONFIG_SPECTRA_USE_CLK_CRM_API := y
CONFIG_DOMAIN_ID_SECURE_CAMERA := y
CONFIG_CSF_2_5_SECURE_CAMERA := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
ccflags-y += -DCONFIG_SPECTRA_LLCC_STALING=1
ccflags-y += -DCONFIG_SPECTRA_USE_RPMH_DRV_API=1
ccflags-y += -DCONFIG_SPECTRA_USE_CLK_CRM_API=1
ccflags-y += -DCONFIG_DOMAIN_ID_SECURE_CAMERA=1
ccflags-y += -DCONFIG_CSF_2_5_SECURE_CAMERA=1
# External Dependencies
KBUILD_CPPFLAGS += -DCONFIG_MSM_MMRM=1
ifeq ($(CONFIG_QCOM_VA_MINIDUMP), y)
KBUILD_CPPFLAGS += -DCONFIG_QCOM_VA_MINIDUMP=1
endif

17
qcom/opensource/camera-kernel/config/crow.mk Normal file
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# Settings for compiling crow camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_TFE := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_CRE := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_TFE=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_CRE=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

14
qcom/opensource/camera-kernel/config/diwali.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
# Settings for compiling diwali camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

13
qcom/opensource/camera-kernel/config/holi.mk Normal file
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# Settings for compiling holi camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_OPE := y
CONFIG_SPECTRA_TFE := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_OPE=1
ccflags-y += -DCONFIG_SPECTRA_TFE=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

21
qcom/opensource/camera-kernel/config/kalama.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_SENSOR := y
CONFIG_SPECTRA_USE_RPMH_DRV_API := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
ccflags-y += -DCONFIG_SPECTRA_USE_RPMH_DRV_API=1
# External Dependencies
KBUILD_CPPFLAGS += -DCONFIG_MSM_MMRM=1
ifeq ($(CONFIG_QCOM_VA_MINIDUMP), y)
KBUILD_CPPFLAGS += -DCONFIG_QCOM_VA_MINIDUMP=1
endif

15
qcom/opensource/camera-kernel/config/kona.mk Normal file
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# Settings for compiling kona camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_FD := y
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_FD=1
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

15
qcom/opensource/camera-kernel/config/lahaina.mk Normal file
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# Settings for compiling lahaina camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_CUSTOM := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_CUSTOM=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

17
qcom/opensource/camera-kernel/config/lito.mk Normal file
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# Settings for compiling lito camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_FD := y
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_LRME := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_FD=1
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_LRME=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

15
qcom/opensource/camera-kernel/config/parrot.mk Normal file
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# Settings for compiling netrani camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_TFE := y
CONFIG_SPECTRA_CRE := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_TFE=1
ccflags-y += -DCONFIG_SPECTRA_CRE=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

33
qcom/opensource/camera-kernel/config/pineapple.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_CRE := y
CONFIG_SPECTRA_SENSOR := y
CONFIG_SPECTRA_LLCC_STALING := y
CONFIG_SPECTRA_USE_RPMH_DRV_API := y
CONFIG_SPECTRA_USE_CLK_CRM_API := y
CONFIG_DOMAIN_ID_SECURE_CAMERA := y
CONFIG_DYNAMIC_FD_PORT_CONFIG := y
CONFIG_CSF_2_5_SECURE_CAMERA := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_CRE=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
ccflags-y += -DCONFIG_SPECTRA_LLCC_STALING=1
ccflags-y += -DCONFIG_SPECTRA_USE_RPMH_DRV_API=1
ccflags-y += -DCONFIG_SPECTRA_USE_CLK_CRM_API=1
ccflags-y += -DCONFIG_DOMAIN_ID_SECURE_CAMERA=1
ccflags-y += -DCONFIG_DYNAMIC_FD_PORT_CONFIG=1
ccflags-y += -DCONFIG_CSF_2_5_SECURE_CAMERA=1
# External Dependencies
KBUILD_CPPFLAGS += -DCONFIG_MSM_MMRM=1
ifeq ($(CONFIG_QCOM_VA_MINIDUMP), y)
KBUILD_CPPFLAGS += -DCONFIG_QCOM_VA_MINIDUMP=1
endif

13
qcom/opensource/camera-kernel/config/shima.mk Normal file
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# Settings for compiling shima camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

17
qcom/opensource/camera-kernel/config/volcano.mk Normal file
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# Settings for compiling volcano camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_TFE := y
CONFIG_SPECTRA_CRE := y
CONFIG_SPECTRA_SENSOR := y
CONFIG_CSF_2_5_SECURE_CAMERA := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_TFE=1
ccflags-y += -DCONFIG_SPECTRA_CRE=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
ccflags-y += -DCONFIG_CSF_2_5_SECURE_CAMERA=1

19
qcom/opensource/camera-kernel/config/waipio.mk Normal file
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# Settings for compiling waipio camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
# External Dependencies
KBUILD_CPPFLAGS += -DCONFIG_MSM_MMRM=1
ifeq ($(CONFIG_QCOM_VA_MINIDUMP), y)
KBUILD_CPPFLAGS += -DCONFIG_QCOM_VA_MINIDUMP=1
endif

15
qcom/opensource/camera-kernel/config/yupik.mk Normal file
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# Settings for compiling yupik camera architecture
# Localized KCONFIG settings
CONFIG_SPECTRA_ISP := y
CONFIG_SPECTRA_ICP := y
CONFIG_SPECTRA_JPEG := y
CONFIG_SPECTRA_LRME := y
CONFIG_SPECTRA_SENSOR := y
# Flags to pass into C preprocessor
ccflags-y += -DCONFIG_SPECTRA_ISP=1
ccflags-y += -DCONFIG_SPECTRA_ICP=1
ccflags-y += -DCONFIG_SPECTRA_JPEG=1
ccflags-y += -DCONFIG_SPECTRA_LRME=1
ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

7
qcom/opensource/camera-kernel/crow_defconfig Normal file
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CONFIG_SPECTRA_ISP=y
CONFIG_SPECTRA_ICP=y
CONFIG_SPECTRA_TFE=y
CONFIG_SPECTRA_JPEG=y
CONFIG_SPECTRA_CRE=y
CONFIG_SPECTRA_SENSOR=y
CONFIG_INTERCONNECT_QCOM=y

66
qcom/opensource/camera-kernel/dependency.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
# Check if this board's product.mk finds msm-mmrm.ko driver
ifeq ($(findstring msm-mmrm.ko,$(BOARD_VENDOR_KERNEL_MODULES)), msm-mmrm.ko)
# Assume if msm-mmrm.ko driver is found, then symbols will be required!
ifeq ($(call is-board-platform-in-list, $(MMRM_BOARDS)),true)
# Add MMRM driver symbols, requires absolute path
CAM_MMRM_EXTRA_SYMBOLS ?= $(realpath $(TOP))/$(call intermediates-dir-for,DLKM,mmrm-module-symvers)/Module.symvers
$(info camera-kernel: Found msm-mmrm driver, adding symbol dependency! $(CAM_MMRM_EXTRA_SYMBOLS))
ifneq ($(TARGET_BOARD_PLATFORM), pineapple)
LOCAL_REQUIRED_MODULES := mmrm-module-symvers
endif # End of check lanai
CAM_MMRM_EXTRA_CONFIGS ?= $(realpath $(TOP))/vendor/qcom/opensource/mmrm-driver/config/waipiommrm.conf
LOCAL_ADDITIONAL_DEPENDENCIES := $(call intermediates-dir-for,DLKM,mmrm-module-symvers)/Module.symvers
endif # End of check for board platform MMRM_BOARDS
endif # End of find msm-mmrm driver
# Check if this board's product.mk finds synx-driver.ko driver
ifeq ($(findstring synx-driver.ko,$(BOARD_VENDOR_KERNEL_MODULES)), synx-driver.ko)
# Assume if synx-driver.ko driver is found, then symbols will be required!
ifeq ($(call is-board-platform-in-list, $(SYNX_VENDOR_BOARDS)),true)
# Add SYNX driver symbols, requires absolute path
CAM_SYNX_EXTRA_SYMBOLS ?= $(realpath $(TOP))/$(call intermediates-dir-for,DLKM,synx-driver-symvers)/synx-driver-symvers
$(info camera-kernel: Found synx driver, adding symbol dependency! $(CAM_SYNX_EXTRA_SYMBOLS))
LOCAL_REQUIRED_MODULES := synx-driver-symvers
CAM_SYNX_EXTRA_CONFIGS ?= $(realpath $(TOP))/vendor/qcom/opensource/synx-kernel/config/pineapplesynx.conf
LOCAL_ADDITIONAL_DEPENDENCIES += $(call intermediates-dir-for,DLKM,synx-driver-symvers)/synx-driver-symvers
endif # End of check for board platform SYNX_VENDOR_BOARDS
endif # End of find synx driver
# Check if this board's product.mk finds smcinvoke_dlkm.ko driver
ifeq ($(findstring smcinvoke_dlkm.ko, $(BOARD_VENDOR_KERNEL_MODULES)), smcinvoke_dlkm.ko)
ifeq ($(call is-board-platform-in-list, $(SMCINVOKE_DLKM_BOARDS)),true)
SMCINVOKE_EXTRA_SYMBOLS ?= $(realpath $(TOP))/$(call intermediates-dir-for,DLKM,smcinvoke_dlkm.ko)/Module.symvers
$(info camera-kernel: Found smcinvoke driver, adding symbol dependency! $(SMCINVOKE_EXTRA_SYMBOLS))
LOCAL_REQUIRED_MODULES += smcinvoke_dlkm.ko
CAM_SMCINOKE_EXTRA_CONFIGS ?= $(realpath $(TOP))/vendor/qcom/opensource/securemsm-kernel/config/sec-kernel_defconfig_smcinvoke.conf
LOCAL_ADDITIONAL_DEPENDENCIES += $(call intermediates-dir-for,DLKM,smcinvoke_dlkm.ko)/Module.symvers
endif # End of check for board platform SMCINVOKE_DLKM_BOARDS
endif # End of find smcinvoke_dlkm driver
# Check if this board's product.mk finds smmu_proxy_dlkm.ko driver
ifeq ($(findstring smmu_proxy_dlkm.ko, $(BOARD_VENDOR_KERNEL_MODULES)), smmu_proxy_dlkm.ko)
ifeq ($(call is-board-platform-in-list, $(SMMU_PROXY_DLKM_BOARDS)),true)
SMMU_PROXY_EXTRA_SYMBOLS ?= $(realpath $(TOP))/$(call intermediates-dir-for,DLKM,smmu_proxy_dlkm.ko)/Module.symvers
$(info camera-kernel: Found smmu proxy driver, adding symbol dependency! $(SMMU_PROXY_EXTRA_SYMBOLS))
LOCAL_REQUIRED_MODULES += smmu_proxy_dlkm.ko
CAM_SMMU_PROXY_EXTRA_CONFIGS ?= $(realpath $(TOP))/vendor/qcom/opensource/securemsm-kernel/config/sec-kernel_defconfig_smmu_proxy.conf
LOCAL_ADDITIONAL_DEPENDENCIES += $(call intermediates-dir-for,DLKM,smmu_proxy_dlkm.ko)/Module.symvers
endif # End of check for board platform SMMU_PROXY_DLKM_BOARDS
endif # End of find smmu_proxy_dlkm driver
KBUILD_OPTIONS += KBUILD_EXTRA_SYMBOLS=$(CAM_MMRM_EXTRA_SYMBOLS) KBUILD_EXTRA_SYMBOLS+=$(CAM_SYNX_EXTRA_SYMBOLS) KBUILD_EXTRA_SYMBOLS+=$(SMCINVOKE_EXTRA_SYMBOLS) KBUILD_EXTRA_SYMBOLS+=$(SMMU_PROXY_EXTRA_SYMBOLS)
KBUILD_OPTIONS += KBUILD_EXTRA_CONFIGS=$(CAM_MMRM_EXTRA_CONFIGS) KBUILD_EXTRA_CONFIGS+=$(CAM_SYNX_EXTRA_CONFIGS) KBUILD_EXTRA_CONFIGS+=$(CAM_SMCINOKE_EXTRA_CONFIGS) KBUILD_EXTRA_CONFIGS+=$(CAM_SMMU_PROXY_EXTRA_CONFIGS)

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CDM_H_
#define _CAM_CDM_H_
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/random.h>
#include <linux/spinlock_types.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <linux/bug.h>
#include "cam_cdm_intf_api.h"
#include "cam_soc_util.h"
#include "cam_cpas_api.h"
#include "cam_hw_intf.h"
#include "cam_hw.h"
#include "cam_debug_util.h"
#define CAM_MAX_SW_CDM_VERSION_SUPPORTED 1
#define CAM_SW_CDM_INDEX 0
#define CAM_CDM_INFLIGHT_WORKS 5
#define CAM_CDM_HW_RESET_TIMEOUT 300
#define CAM_CDM_PAUSE_CORE_US_TIMEOUT 10000
/*
* Macros to get prepare and get information
* from client CDM handles.
*/
#define CAM_CDM_HW_ID_MASK 0xF
#define CAM_CDM_HW_ID_SHIFT 0x10
#define CAM_CDM_CLIENTS_ID_MASK 0xFF
#define CAM_CDM_BL_FIFO_ID_MASK 0xF
#define CAM_CDM_BL_FIFO_ID_SHIFT 0x8
#define CAM_CDM_GET_HW_IDX(x) (((x) >> CAM_CDM_HW_ID_SHIFT) & \
CAM_CDM_HW_ID_MASK)
#define CAM_CDM_GET_BLFIFO_IDX(x) (((x) >> CAM_CDM_BL_FIFO_ID_SHIFT) & \
CAM_CDM_BL_FIFO_ID_MASK)
#define CAM_CDM_CREATE_CLIENT_HANDLE(hw_idx, priority, client_idx) \
((((hw_idx) & CAM_CDM_HW_ID_MASK) << CAM_CDM_HW_ID_SHIFT) | \
(((priority) & CAM_CDM_BL_FIFO_ID_MASK) << CAM_CDM_BL_FIFO_ID_SHIFT)| \
((client_idx) & CAM_CDM_CLIENTS_ID_MASK))
#define CAM_CDM_GET_CLIENT_IDX(x) ((x) & CAM_CDM_CLIENTS_ID_MASK)
#define CAM_PER_CDM_MAX_REGISTERED_CLIENTS (CAM_CDM_CLIENTS_ID_MASK + 1)
#define CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM (CAM_CDM_HW_ID_MASK + 1)
/* Number of FIFO supported on CDM */
#define CAM_CDM_NUM_BL_FIFO 0x4
#define CAM_CDM_NUM_TEST_BUS 16
/* Max number of register set for different CDM */
#define CAM_CDM_BL_FIFO_REG_NUM 0x4
#define CAM_CDM_BL_FIFO_IRQ_REG_NUM 0x4
#define CAM_CDM_BL_FIFO_PENDING_REQ_REG_NUM 0x2
#define CAM_CDM_SCRATCH_REG_NUM 0xc
#define CAM_CDM_COMP_WAIT_STATUS_REG_NUM 0x2
#define CAM_CDM_PERF_MON_REG_NUM 0x2
/* BL_FIFO configurations*/
#define CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT 0x40
#define CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT 0x10
#define CAM_CDM_BL_FIFO_FLUSH_SHIFT 0x3
#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX 0x00
#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV2 0x01
#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV4 0x10
#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV8 0x11
/* CDM core status bitmap */
#define CAM_CDM_HW_INIT_STATUS 0x0
#define CAM_CDM_FIFO_0_BLDONE_STATUS 0x0
#define CAM_CDM_FIFO_1_BLDONE_STATUS 0x1
#define CAM_CDM_FIFO_2_BLDONE_STATUS 0x2
#define CAM_CDM_FIFO_3_BLDONE_STATUS 0x3
#define CAM_CDM_RESET_HW_STATUS 0x4
#define CAM_CDM_ERROR_HW_STATUS 0x5
#define CAM_CDM_FLUSH_HW_STATUS 0x6
#define CAM_CDM_RESET_ERR_STATUS 0x7
#define CAM_CDM_PF_HW_STATUS 0x8
/* Curent used AHB masks and shifts */
#define CAM_CDM_AHB_LOG_CID_SHIFT 28
#define CAM_CDM_AHB_LOG_CID_MASK 0X30000000
#define CAM_CDM_AHB_ADDR_MASK 0x00FFFFFF
/* Invalid command status register's masks and shifts */
#define CAM_CDM_ICL_STATUS_LAST_CID_SHIFT 4
#define CAM_CDM_ICL_STATUS_LAST_CID_MASK 0X30
#define CAM_CDM_ICL_STATUS_INV_CID_MASK 0x03
/* Core_cfg register's masks and shifts */
#define CAM_CDM_CORE_CFG_PRIORITY_MASK 0XF00000
#define CAM_CDM_CORE_CFG_PRIORITY_SHIFT 20
#define CAM_CDM_CORE_CFG_IMPLICIT_WAIT_EN_MASK 0x20000
#define CAM_CDM_CORE_CFG_ARB_SEL_RR_MASK 0x10000
#define CAM_CDM_CORE_CFG_AHB_STOP_ON_ERR_MASK 0x100
#define CAM_CDM_CORE_CFG_AHB_BURST_EN_MASK 0x10
#define CAM_CDM_CORE_CFG_AHB_BURST_LEN_MASK 0x0F
/* Core enable register masks and shifts */
#define CAM_CDM_CORE_EN_MASK 0x1
#define CAM_CDM_CORE_PAUSE_MASK 0X2
/* Core Debug register masks and shifts */
#define CAM_CDM_CORE_DBG_TEST_BUS_EN_MASK 0X01
#define CAM_CDM_CORE_DBG_TEST_BUS_SEL_MASK 0XF0
#define CAM_CDM_CORE_DBG_TEST_BUS_SEL_SHIFT 4
#define CAM_CDM_CORE_DBG_LOG_AHB_MASK 0X100
#define CAM_CDM_CORE_DBG_LOG_SHIFT 8
#define CAM_CDM_CORE_DBG_FIFO_RB_EN_MASK 0x10000
#define CAM_CDM_CORE_DBG_FIFO_RB_EN_SHIFT 16
/* Curent BL command masks and shifts */
#define CAM_CDM_CURRENT_BL_LEN 0xFFFFF
#define CAM_CDM_CURRENT_BL_ARB 0x100000
#define CAM_CDM_CURRENT_BL_FIFO 0xC00000
#define CAM_CDM_CURRENT_BL_TAG 0xFF000000
#define CAM_CDM_CURRENT_BL_ARB_SHIFT 0x14
#define CAM_CDM_CURRENT_BL_FIFO_SHIFT 0x16
#define CAM_CDM_CURRENT_BL_TAG_SHIFT 0x18
/* IRQ bit-masks */
#define CAM_CDM_IRQ_STATUS_RST_DONE_MASK 0x1
#define CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK 0x2
#define CAM_CDM_IRQ_STATUS_BL_DONE_MASK 0x4
#define CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK 0x10000
#define CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK 0x20000
#define CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK 0x40000
#define CAM_CDM_IRQ_STATUS_USR_DATA_MASK 0xFF
#define CAM_CDM_IRQ_STATUS_ERRORS \
(CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK | \
CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK | \
CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK)
/* Structure to store hw version info */
struct cam_version_reg {
uint32_t hw_version;
};
/**
* struct cam_cdm_irq_regs - CDM IRQ registers
*
* @irq_mask: register offset for irq_mask
* @irq_clear: register offset for irq_clear
* @irq_clear_cmd: register offset to initiate irq clear
* @irq_set: register offset to set irq
* @irq_set_cmd: register offset to issue set_irq from irq_set
* @irq_status: register offset to look which irq is received
*/
struct cam_cdm_irq_regs {
uint32_t irq_mask;
uint32_t irq_clear;
uint32_t irq_clear_cmd;
uint32_t irq_set;
uint32_t irq_set_cmd;
uint32_t irq_status;
};
/**
* struct cam_cdm_bl_fifo_regs - BL_FIFO registers
*
* @bl_fifo_base: register offset to write bl_cmd base address
* @bl_fifo_len: register offset to write bl_cmd length
* @bl_fifo_store: register offset to commit the BL cmd
* @bl_fifo_cfg: register offset to config BL_FIFO depth, etc.
*/
struct cam_cdm_bl_fifo_regs {
uint32_t bl_fifo_base;
uint32_t bl_fifo_len;
uint32_t bl_fifo_store;
uint32_t bl_fifo_cfg;
};
/**
* struct cam_cdm_bl_pending_req_reg_params - BL_FIFO pending registers
*
* @rb_offset: register offset pending bl request in BL_FIFO
* @rb_mask: mask to get number of pending BLs in BL_FIFO
* @rb_num_fifo: number of BL_FIFO's information in the register
* @rb_next_fifo_shift: shift to get next fifo's pending BLs.
*/
struct cam_cdm_bl_pending_req_reg_params {
uint32_t rb_offset;
uint32_t rb_mask;
uint32_t rb_num_fifo;
uint32_t rb_next_fifo_shift;
};
/**
* struct cam_cdm_scratch_reg - scratch register
*
* @scratch_reg: offset of scratch register
*/
struct cam_cdm_scratch_reg {
uint32_t scratch_reg;
};
/* struct cam_cdm_perf_mon_regs - perf_mon registers */
struct cam_cdm_perf_mon_regs {
uint32_t perf_mon_ctrl;
uint32_t perf_mon_0;
uint32_t perf_mon_1;
uint32_t perf_mon_2;
};
/**
* struct cam_cdm_perf_mon_regs - perf mon counter's registers
*
* @count_cfg_0: register offset to configure perf measures
* @always_count_val: register offset for always count value
* @busy_count_val: register offset to get busy count
* @stall_axi_count_val: register offset to get axi stall counts
* @count_status: register offset to know if count status finished
* for stall, busy and always.
*/
struct cam_cdm_perf_regs {
uint32_t count_cfg_0;
uint32_t always_count_val;
uint32_t busy_count_val;
uint32_t stall_axi_count_val;
uint32_t count_status;
};
/**
* struct cam_cdm_icl_data_regs - CDM icl data registers
*
* @icl_last_data_0: register offset to log last known good command
* @icl_last_data_1: register offset to log last known good command 1
* @icl_last_data_2: register offset to log last known good command 2
* @icl_inv_data: register offset to log CDM cmd that triggered
* invalid command.
*/
struct cam_cdm_icl_data_regs {
uint32_t icl_last_data_0;
uint32_t icl_last_data_1;
uint32_t icl_last_data_2;
uint32_t icl_inv_data;
};
/**
* struct cam_cdm_icl_misc_regs - CDM icl misc registers
*
* @icl_inv_bl_addr: register offset to give address of bl_cmd that
* gave invalid command
* @icl_status: register offset for context that gave good BL
* command and invalid command.
*/
struct cam_cdm_icl_misc_regs {
uint32_t icl_inv_bl_addr;
uint32_t icl_status;
};
/**
* struct cam_cdm_icl_regs - CDM icl registers
*
* @data_regs: structure with registers of all cdm good and invalid
* BL command information.
* @misc_regs: structure with registers for invalid command address
* and context
*/
struct cam_cdm_icl_regs {
struct cam_cdm_icl_data_regs *data_regs;
struct cam_cdm_icl_misc_regs *misc_regs;
};
/**
* struct cam_cdm_comp_wait_status - BL_FIFO comp_event status register
*
* @comp_wait_status: register offset to give information on whether the
* CDM is waiting for an event from another module
*/
struct cam_cdm_comp_wait_status {
uint32_t comp_wait_status;
};
/**
* struct cam_cdm_common_reg_data - structure for register data
*
* @num_bl_fifo: number of FIFO are there in CDM
* @num_bl_fifo_irq: number of FIFO irqs in CDM
* @num_bl_pending_req_reg: number of pending_requests register in CDM
* @num_scratch_reg: number of scratch registers in CDM
*/
struct cam_cdm_common_reg_data {
uint32_t num_bl_fifo;
uint32_t num_bl_fifo_irq;
uint32_t num_bl_pending_req_reg;
uint32_t num_scratch_reg;
};
/**
* struct cam_cdm_common_regs - common structure to get common registers
* of CDM
*
* @cdm_hw_version: offset to read cdm_hw_version
* @cam_version: offset to read the camera Titan architecture version
* @rst_cmd: offset to reset the CDM
* @cgc_cfg: offset to configure CDM CGC logic
* @core_cfg: offset to configure CDM core with ARB_SEL, implicit
* wait, etc.
* @core_en: offset to pause/enable CDM
* @fe_cfg: offset to configure CDM fetch engine
* @cdm_status: offset to read CDM status register, this register
* indicates if CDM is idle, and if a pause operation
* is successfully completed or not
* @irq_context_status offset to read back irq context status
* @bl_fifo_rb: offset to set BL_FIFO read back
* @bl_fifo_base_rb: offset to read back base address on offset set by
* bl_fifo_rb
* @bl_fifo_len_rb: offset to read back base len and tag on offset set by
* bl_fifo_rb
* @usr_data: offset to read user data from GEN_IRQ commands
* @wait_status: offset to read status for last WAIT command
* @last_ahb_addr: offset to read back last AHB address generated by CDM
* @last_ahb_data: offset to read back last AHB data generated by CDM
* @core_debug: offset to configure CDM debug bus and debug features
* @last_ahb_err_addr: offset to read back last AHB Error address generated
* by CDM
* @last_ahb_err_data: offset to read back last AHB Error data generated
* by CDM
* @current_bl_base: offset to read back current command buffer BASE address
* value out of BL_FIFO
* @current_bl_len: offset to read back current command buffer len, TAG,
* context ID ARB value out of BL_FIFO
* @current_used_ahb_base: offset to read back current base address used by
* CDM to access camera register
* @debug_status: offset to read back current CDM status
* @bus_misr_cfg0: offset to enable bus MISR and configure sampling mode
* @bus_misr_cfg1: offset to select from one of the six MISR's for reading
* signature value
* @bus_misr_rd_val: offset to read MISR signature
* @pending_req: registers to read pending request in FIFO
* @comp_wait: registers to read comp_event CDM is waiting for
* @perf_mon: registers to read perf_mon information
* @scratch: registers to read scratch register value
* @perf_reg: registers to read performance counters value
* @icl_reg: registers to read information related to good
* and invalid commands in FIFO
* @spare: spare register
* @priority_group_bit_offset offset of priority group bits
*
*/
struct cam_cdm_common_regs {
uint32_t cdm_hw_version;
const struct cam_version_reg *cam_version;
uint32_t rst_cmd;
uint32_t cgc_cfg;
uint32_t core_cfg;
uint32_t core_en;
uint32_t fe_cfg;
uint32_t cdm_status;
uint32_t irq_context_status;
uint32_t bl_fifo_rb;
uint32_t bl_fifo_base_rb;
uint32_t bl_fifo_len_rb;
uint32_t usr_data;
uint32_t wait_status;
uint32_t last_ahb_addr;
uint32_t last_ahb_data;
uint32_t core_debug;
uint32_t last_ahb_err_addr;
uint32_t last_ahb_err_data;
uint32_t current_bl_base;
uint32_t current_bl_len;
uint32_t current_used_ahb_base;
uint32_t debug_status;
uint32_t bus_misr_cfg0;
uint32_t bus_misr_cfg1;
uint32_t bus_misr_rd_val;
const struct cam_cdm_bl_pending_req_reg_params
*pending_req[CAM_CDM_BL_FIFO_PENDING_REQ_REG_NUM];
const struct cam_cdm_comp_wait_status
*comp_wait[CAM_CDM_COMP_WAIT_STATUS_REG_NUM];
const struct cam_cdm_perf_mon_regs
*perf_mon[CAM_CDM_PERF_MON_REG_NUM];
const struct cam_cdm_scratch_reg
*scratch[CAM_CDM_SCRATCH_REG_NUM];
const struct cam_cdm_perf_regs *perf_reg;
const struct cam_cdm_icl_regs *icl_reg;
uint32_t spare;
uint32_t priority_group_bit_offset;
};
/**
* struct cam_cdm_hw_reg_offset - BL_FIFO comp_event status register
*
* @cmn_reg: pointer to structure to get common registers of a CDM
* @bl_fifo_reg: pointer to structure to get BL_FIFO registers of a CDM
* @irq_reg: pointer to structure to get IRQ registers of a CDM
* @reg_data: pointer to structure to reg_data related to CDM
* registers
*/
struct cam_cdm_hw_reg_offset {
const struct cam_cdm_common_regs *cmn_reg;
const struct cam_cdm_bl_fifo_regs *bl_fifo_reg[CAM_CDM_BL_FIFO_REG_NUM];
const struct cam_cdm_irq_regs *irq_reg[CAM_CDM_BL_FIFO_IRQ_REG_NUM];
const struct cam_cdm_common_reg_data *reg_data;
};
/* enum cam_cdm_hw_process_intf_cmd - interface commands.*/
enum cam_cdm_hw_process_intf_cmd {
CAM_CDM_HW_INTF_CMD_ACQUIRE,
CAM_CDM_HW_INTF_CMD_RELEASE,
CAM_CDM_HW_INTF_CMD_SUBMIT_BL,
CAM_CDM_HW_INTF_CMD_RESET_HW,
CAM_CDM_HW_INTF_CMD_FLUSH_HW,
CAM_CDM_HW_INTF_CMD_HANDLE_ERROR,
CAM_CDM_HW_INTF_CMD_HANG_DETECT,
CAM_CDM_HW_INTF_DUMP_DBG_REGS,
CAM_CDM_HW_INTF_CMD_INVALID,
};
/* enum cam_cdm_flags - Bit fields for CDM flags used */
enum cam_cdm_flags {
CAM_CDM_FLAG_SHARED_CDM,
CAM_CDM_FLAG_PRIVATE_CDM,
};
/* enum cam_cdm_type - Enum for possible CAM CDM types */
enum cam_cdm_type {
CAM_VIRTUAL_CDM,
CAM_HW_CDM,
};
/* enum cam_cdm_mem_base_index - Enum for possible CAM CDM types */
enum cam_cdm_mem_base_index {
CAM_HW_CDM_BASE_INDEX,
CAM_HW_CDM_MAX_INDEX = CAM_SOC_MAX_BLOCK,
};
/* enum cam_cdm_bl_cb_type - Enum for possible CAM CDM cb request types */
enum cam_cdm_bl_cb_type {
CAM_HW_CDM_BL_CB_CLIENT = 1,
CAM_HW_CDM_BL_CB_INTERNAL,
};
/* enum cam_cdm_arbitration - Enum type of arbitration */
enum cam_cdm_arbitration {
CAM_CDM_ARBITRATION_NONE,
CAM_CDM_ARBITRATION_ROUND_ROBIN,
CAM_CDM_ARBITRATION_PRIORITY_BASED,
CAM_CDM_ARBITRATION_MAX,
};
enum cam_cdm_hw_version {
CAM_CDM_VERSION = 0,
CAM_CDM_VERSION_1_0 = 0x10000000,
CAM_CDM_VERSION_1_1 = 0x10010000,
CAM_CDM_VERSION_1_2 = 0x10020000,
CAM_CDM_VERSION_2_0 = 0x20000000,
CAM_CDM_VERSION_2_1 = 0x20010000,
CAM_CDM_VERSION_2_2 = 0x20020000,
CAM_CDM_VERSION_MAX,
};
/* struct cam_cdm_client - struct for cdm clients data.*/
struct cam_cdm_client {
struct cam_cdm_acquire_data data;
void __iomem *changebase_addr;
uint32_t stream_on;
uint32_t refcount;
struct mutex lock;
uint32_t handle;
};
/* struct cam_cdm_work_payload - struct for cdm work payload data.*/
struct cam_cdm_work_payload {
struct cam_hw_info *hw;
uint32_t irq_status;
uint32_t irq_data;
int fifo_idx;
ktime_t workq_scheduled_ts;
struct work_struct work;
};
/* struct cam_cdm_bl_cb_request_entry - callback entry for work to process.*/
struct cam_cdm_bl_cb_request_entry {
uint8_t bl_tag;
enum cam_cdm_bl_cb_type request_type;
uint32_t client_hdl;
void *userdata;
uint32_t cookie;
struct list_head entry;
};
/* struct cam_cdm_hw_intf_cmd_submit_bl - cdm interface submit command.*/
struct cam_cdm_hw_intf_cmd_submit_bl {
uint32_t handle;
struct cam_cdm_bl_request *data;
};
/* struct cam_cdm_bl_fifo - CDM hw memory struct */
struct cam_cdm_bl_fifo {
struct completion bl_complete;
struct workqueue_struct *work_queue;
struct list_head bl_request_list;
struct mutex fifo_lock;
uint8_t bl_tag;
uint32_t bl_depth;
uint8_t last_bl_tag_done;
atomic_t work_record;
};
/**
* struct cam_cdm - CDM hw device struct
*
* @index: index of CDM hardware
* @name: cdm_name
* @id: enum for possible CDM hardwares
* @flags: enum to tell if CDM is private of shared
* @reset_complete: completion event to make CDM wait for reset
* @work_queue: workqueue to schedule work for virtual CDM
* @bl_request_list: bl_request list for submitted commands in
* virtual CDM
* @version: CDM version with major, minor, incr and reserved
* @hw_version: CDM version as read from the cdm_version register
* @hw_family_version: version of hw family the CDM belongs to
* @iommu_hdl: CDM iommu handle
* @offsets: pointer to structure of CDM registers
* @ops: CDM ops for generating cdm commands
* @clients: CDM clients array currently active on CDM
* @bl_fifo: structure with per fifo related attributes
* @cdm_status: bitfield with bits assigned for different cdm status
* @bl_tag: slot value at which the next bl cmd will be written
* in case of virtual CDM
* @gen_irq: memory region in which gen_irq command will be written
* @cpas_handle: handle for cpas driver
* @arbitration: type of arbitration to be used for the CDM
* @num_active_clients: Number of currently active clients
*/
struct cam_cdm {
uint32_t index;
char name[128];
enum cam_cdm_id id;
enum cam_cdm_flags flags;
struct completion reset_complete;
struct workqueue_struct *work_queue;
struct list_head bl_request_list;
struct cam_hw_version version;
uint32_t hw_version;
uint32_t hw_family_version;
struct cam_iommu_handle iommu_hdl;
struct cam_cdm_hw_reg_offset *offsets;
struct cam_cdm_utils_ops *ops;
struct cam_cdm_client *clients[CAM_PER_CDM_MAX_REGISTERED_CLIENTS];
struct cam_cdm_bl_fifo bl_fifo[CAM_CDM_BL_FIFO_MAX];
unsigned long cdm_status;
uint8_t bl_tag;
uint32_t cpas_handle;
enum cam_cdm_arbitration arbitration;
uint8_t num_active_clients;
};
/* struct cam_cdm_private_dt_data - CDM hw custom dt data */
struct cam_cdm_private_dt_data {
bool dt_cdm_shared;
bool config_fifo;
bool is_single_ctx_cdm;
uint8_t priority_group;
uint32_t fifo_depth[CAM_CDM_BL_FIFO_MAX];
uint32_t dt_num_supported_clients;
uint32_t pid;
uint32_t mid;
const char *dt_cdm_client_name[CAM_PER_CDM_MAX_REGISTERED_CLIENTS];
};
/* struct cam_cdm_intf_devices - CDM mgr interface devices */
struct cam_cdm_intf_devices {
struct mutex lock;
uint32_t refcount;
struct cam_hw_intf *device;
struct cam_cdm_private_dt_data *data;
};
/* struct cam_cdm_intf_mgr - CDM mgr interface device struct */
struct cam_cdm_intf_mgr {
bool probe_done;
uint32_t cdm_count;
uint32_t dt_supported_hw_cdm;
int32_t refcount;
struct cam_cdm_intf_devices nodes[CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM];
struct dentry *dentry;
};
int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw,
struct cam_cdm_private_dt_data *data, enum cam_cdm_type type,
uint32_t *index);
int cam_cdm_intf_deregister_hw_cdm(struct cam_hw_intf *hw,
struct cam_cdm_private_dt_data *data, enum cam_cdm_type type,
uint32_t index);
#endif /* _CAM_CDM_H_ */

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/kernel.h>
#include "cam_soc_util.h"
#include "cam_smmu_api.h"
#include "cam_io_util.h"
#include "cam_cdm_intf_api.h"
#include "cam_cdm.h"
#include "cam_cdm_soc.h"
#include "cam_cdm_core_common.h"
int cam_cdm_util_cpas_start(struct cam_hw_info *cdm_hw)
{
struct cam_cdm *core = NULL;
struct cam_ahb_vote ahb_vote;
struct cam_axi_vote axi_vote = {0};
int rc = 0;
if (!cdm_hw) {
CAM_ERR(CAM_CDM, "Invalid cdm hw");
return -EINVAL;
}
core = (struct cam_cdm *)cdm_hw->core_info;
ahb_vote.type = CAM_VOTE_ABSOLUTE;
ahb_vote.vote.level = CAM_LOWSVS_D1_VOTE;
axi_vote.num_paths = 1;
axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL;
axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_READ;
axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW;
axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW;
axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW;
rc = cam_cpas_start(core->cpas_handle, &ahb_vote, &axi_vote);
if (rc) {
CAM_ERR(CAM_CDM, "CDM[%d] CPAS start failed rc=%d", core->index, rc);
return rc;
}
return rc;
}
static void cam_cdm_get_client_refcount(struct cam_cdm_client *client)
{
mutex_lock(&client->lock);
CAM_DBG(CAM_CDM, "CDM client get refcount=%d",
client->refcount);
client->refcount++;
mutex_unlock(&client->lock);
}
static void cam_cdm_put_client_refcount(struct cam_cdm_client *client)
{
mutex_lock(&client->lock);
CAM_DBG(CAM_CDM, "CDM client put refcount=%d",
client->refcount);
if (client->refcount > 0) {
client->refcount--;
} else {
CAM_ERR(CAM_CDM, "Refcount put when zero");
WARN_ON(1);
}
mutex_unlock(&client->lock);
}
bool cam_cdm_set_cam_hw_version(
uint32_t ver, struct cam_hw_version *cam_version)
{
switch (ver) {
case CAM_CDM100_VERSION:
case CAM_CDM110_VERSION:
case CAM_CDM120_VERSION:
case CAM_CDM200_VERSION:
case CAM_CDM210_VERSION:
case CAM_CDM220_VERSION:
cam_version->major = (ver & 0xF0000000);
cam_version->minor = (ver & 0xFFF0000);
cam_version->incr = (ver & 0xFFFF);
cam_version->reserved = 0;
return true;
default:
CAM_ERR(CAM_CDM, "CDM Version=%x not supported in util", ver);
break;
}
return false;
}
bool cam_cdm_cpas_cb(uint32_t client_handle, void *userdata,
struct cam_cpas_irq_data *irq_data)
{
if (!irq_data)
return false;
CAM_DBG(CAM_CDM, "CPAS error callback type=%d", irq_data->irq_type);
return false;
}
struct cam_cdm_utils_ops *cam_cdm_get_ops(
uint32_t ver, struct cam_hw_version *cam_version, bool by_cam_version)
{
if (by_cam_version == false) {
switch (ver) {
case CAM_CDM100_VERSION:
case CAM_CDM110_VERSION:
case CAM_CDM120_VERSION:
case CAM_CDM200_VERSION:
case CAM_CDM210_VERSION:
case CAM_CDM220_VERSION:
return &CDM170_ops;
default:
CAM_ERR(CAM_CDM, "CDM Version=%x not supported in util",
ver);
}
} else if (cam_version) {
if (((cam_version->major == 1) &&
(cam_version->minor == 0) &&
(cam_version->incr == 0)) ||
((cam_version->major == 1) &&
(cam_version->minor == 1) &&
(cam_version->incr == 0)) ||
((cam_version->major == 1) &&
(cam_version->minor == 2) &&
(cam_version->incr == 0))) {
CAM_DBG(CAM_CDM,
"cam_hw_version=%x:%x:%x supported",
cam_version->major, cam_version->minor,
cam_version->incr);
return &CDM170_ops;
}
CAM_ERR(CAM_CDM, "cam_hw_version=%x:%x:%x not supported",
cam_version->major, cam_version->minor,
cam_version->incr);
}
return NULL;
}
struct cam_cdm_bl_cb_request_entry *cam_cdm_find_request_by_bl_tag(
uint32_t tag, struct list_head *bl_list)
{
struct cam_cdm_bl_cb_request_entry *node;
list_for_each_entry(node, bl_list, entry) {
if (node->bl_tag == tag)
return node;
}
CAM_ERR(CAM_CDM, "Could not find the bl request for tag=%x", tag);
return NULL;
}
int cam_cdm_get_caps(void *hw_priv,
void *get_hw_cap_args, uint32_t arg_size)
{
struct cam_hw_info *cdm_hw = hw_priv;
struct cam_cdm *cdm_core;
if ((cdm_hw) && (cdm_hw->core_info) && (get_hw_cap_args) &&
(sizeof(struct cam_iommu_handle) == arg_size)) {
cdm_core = (struct cam_cdm *)cdm_hw->core_info;
*((struct cam_iommu_handle *)get_hw_cap_args) =
cdm_core->iommu_hdl;
return 0;
}
return -EINVAL;
}
int cam_cdm_find_free_client_slot(struct cam_cdm *hw)
{
int i;
for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) {
if (hw->clients[i] == NULL) {
CAM_DBG(CAM_CDM, "Found client slot %d", i);
return i;
}
}
CAM_ERR(CAM_CDM, "No more client slots");
return -EBUSY;
}
static int cam_cdm_get_last_client_idx(struct cam_cdm *core)
{
int i, last_client = 0;
for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) {
if (core->clients[i])
last_client = i;
}
return last_client;
}
void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw,
enum cam_cdm_cb_status status, void *data)
{
int i;
struct cam_cdm *core = NULL;
struct cam_cdm_client *client = NULL;
struct cam_cdm_bl_cb_request_entry *node = NULL;
struct cam_hw_dump_pf_args pf_args = {0};
int client_idx, last_client;
if (!cdm_hw) {
CAM_ERR(CAM_CDM, "CDM Notify called with NULL hw info");
return;
}
core = (struct cam_cdm *)cdm_hw->core_info;
switch (status) {
case CAM_CDM_CB_STATUS_BL_SUCCESS:
node = (struct cam_cdm_bl_cb_request_entry *)data;
client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl);
client = core->clients[client_idx];
if ((!client) || (client->handle != node->client_hdl)) {
CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client,
node->client_hdl);
return;
}
cam_cdm_get_client_refcount(client);
mutex_lock(&client->lock);
if (client->data.cam_cdm_callback) {
CAM_DBG(CAM_CDM, "Calling client=%s cb cookie=%d",
client->data.identifier, node->cookie);
client->data.cam_cdm_callback(node->client_hdl,
node->userdata, CAM_CDM_CB_STATUS_BL_SUCCESS,
(void *)(&node->cookie));
CAM_DBG(CAM_CDM, "Exit client cb cookie=%d",
node->cookie);
} else {
CAM_ERR(CAM_CDM, "No cb registered for client hdl=%x",
node->client_hdl);
}
mutex_unlock(&client->lock);
cam_cdm_put_client_refcount(client);
break;
case CAM_CDM_CB_STATUS_HW_RESET_DONE:
case CAM_CDM_CB_STATUS_HW_FLUSH:
case CAM_CDM_CB_STATUS_HW_RESUBMIT:
case CAM_CDM_CB_STATUS_INVALID_BL_CMD:
case CAM_CDM_CB_STATUS_HW_ERROR:
node = (struct cam_cdm_bl_cb_request_entry *)data;
client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl);
client = core->clients[client_idx];
if ((!client) || (client->handle != node->client_hdl)) {
CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client,
node->client_hdl);
return;
}
cam_cdm_get_client_refcount(client);
mutex_lock(&client->lock);
if (client->data.cam_cdm_callback) {
client->data.cam_cdm_callback(
client->handle,
client->data.userdata,
status,
(void *)(&node->cookie));
} else {
CAM_ERR(CAM_CDM,
"No cb registered for client: name %s, hdl=%x",
client->data.identifier, client->handle);
}
mutex_unlock(&client->lock);
cam_cdm_put_client_refcount(client);
break;
case CAM_CDM_CB_STATUS_PAGEFAULT:
last_client = cam_cdm_get_last_client_idx(core);
pf_args.pf_smmu_info = (struct cam_smmu_pf_info *)data;
pf_args.handle_sec_pf = true;
for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) {
client = core->clients[i];
if (!client)
continue;
cam_cdm_get_client_refcount(client);
if (client->data.cam_cdm_callback) {
if (i == last_client)
/*
* If the fault causing client is not found,
* make the last client of this CDM sends PF
* notification to userspace. This avoids multiple
* PF notifications and ensures at least one
* notification is sent.
*/
pf_args.pf_context_info.force_send_pf_evt = true;
mutex_lock(&client->lock);
CAM_DBG(CAM_CDM, "Found client slot %d name %s",
i, client->data.identifier);
client->data.cam_cdm_callback(
client->handle,
client->data.userdata,
status,
&pf_args);
if (pf_args.pf_context_info.ctx_found ||
pf_args.pf_context_info.force_send_pf_evt) {
if (pf_args.pf_context_info.ctx_found)
CAM_ERR(CAM_CDM,
"Page Fault found on client: [%s][%u]",
client->data.identifier,
client->data.cell_index);
mutex_unlock(&client->lock);
cam_cdm_put_client_refcount(client);
break;
}
mutex_unlock(&client->lock);
} else {
CAM_ERR(CAM_CDM, "No cb registered for client hdl=%x",
client->handle);
}
cam_cdm_put_client_refcount(client);
}
break;
default:
CAM_ERR(CAM_CDM, "Invalid cdm cb status: %u", status);
}
}
static int cam_cdm_stream_handle_init(void *hw_priv, bool init)
{
int rc = -EPERM;
if (init) {
rc = cam_hw_cdm_init(hw_priv, NULL, 0);
if (rc) {
CAM_ERR(CAM_CDM, "CDM HW init failed");
return rc;
}
} else {
rc = cam_hw_cdm_deinit(hw_priv, NULL, 0);
if (rc)
CAM_ERR(CAM_CDM, "Deinit failed in streamoff");
}
return rc;
}
int cam_cdm_stream_ops_internal(void *hw_priv,
void *start_args, bool operation)
{
struct cam_hw_info *cdm_hw = hw_priv;
struct cam_cdm *core = NULL;
int rc = -EPERM;
int client_idx;
struct cam_cdm_client *client;
uint32_t *handle = start_args;
if (!hw_priv)
return -EINVAL;
core = (struct cam_cdm *)cdm_hw->core_info;
/*
* If this CDM HW encounters Page Fault, block any futher
* stream on/off until this CDM get released and acquired
* again. CDM page fault handler will stream off the device.
*/
if (test_bit(CAM_CDM_PF_HW_STATUS, &core->cdm_status)) {
CAM_WARN(CAM_CDM,
"Attempt to stream %s failed. %s%u has encountered a page fault",
operation ? "on" : "off",
core->name, core->id);
return -EAGAIN;
}
mutex_lock(&cdm_hw->hw_mutex);
client_idx = CAM_CDM_GET_CLIENT_IDX(*handle);
client = core->clients[client_idx];
if (!client) {
CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, *handle);
mutex_unlock(&cdm_hw->hw_mutex);
return -EINVAL;
}
cam_cdm_get_client_refcount(client);
if (*handle != client->handle) {
CAM_ERR(CAM_CDM, "client id given handle=%x invalid", *handle);
rc = -EINVAL;
goto end;
}
if (operation == true) {
if (true == client->stream_on) {
CAM_ERR(CAM_CDM,
"Invalid CDM client is already streamed ON");
goto end;
}
} else {
if (client->stream_on == false) {
CAM_ERR(CAM_CDM,
"Invalid CDM client is already streamed Off");
goto end;
}
}
if (operation == true) {
if (!cdm_hw->open_count) {
rc = cam_cdm_util_cpas_start(cdm_hw);
if (rc != 0) {
CAM_ERR(CAM_CDM, "CPAS start failed");
goto end;
}
CAM_DBG(CAM_CDM, "CDM init first time");
if (core->id == CAM_CDM_VIRTUAL) {
CAM_DBG(CAM_CDM,
"Virtual CDM HW init first time");
rc = 0;
} else {
CAM_DBG(CAM_CDM, "CDM HW init first time");
rc = cam_cdm_stream_handle_init(hw_priv, true);
}
if (rc == 0) {
cdm_hw->open_count++;
client->stream_on = true;
} else {
if (cam_cpas_stop(core->cpas_handle))
CAM_ERR(CAM_CDM, "CPAS stop failed");
}
} else {
cdm_hw->open_count++;
CAM_DBG(CAM_CDM, "CDM HW already ON count=%d",
cdm_hw->open_count);
rc = 0;
client->stream_on = true;
}
} else {
if (cdm_hw->open_count) {
cdm_hw->open_count--;
CAM_DBG(CAM_CDM, "stream OFF CDM %d",
cdm_hw->open_count);
if (!cdm_hw->open_count) {
CAM_DBG(CAM_CDM, "CDM Deinit now");
if (core->id == CAM_CDM_VIRTUAL) {
CAM_DBG(CAM_CDM,
"Virtual CDM HW Deinit");
rc = 0;
} else {
CAM_DBG(CAM_CDM, "CDM HW Deinit now");
rc = cam_cdm_stream_handle_init(hw_priv,
false);
}
if (rc == 0) {
client->stream_on = false;
rc = cam_cpas_stop(core->cpas_handle);
if (rc)
CAM_ERR(CAM_CDM,
"CPAS stop failed");
}
} else {
client->stream_on = false;
rc = 0;
CAM_DBG(CAM_CDM,
"Client stream off success =%d",
cdm_hw->open_count);
}
} else {
CAM_DBG(CAM_CDM, "stream OFF CDM Invalid %d",
cdm_hw->open_count);
rc = -ENXIO;
}
}
end:
cam_cdm_put_client_refcount(client);
mutex_unlock(&cdm_hw->hw_mutex);
return rc;
}
int cam_cdm_pf_stream_off_all_clients(struct cam_hw_info *cdm_hw)
{
struct cam_cdm *core;
struct cam_cdm_client *client;
int i, rc;
if (!cdm_hw)
return -EINVAL;
core = cdm_hw->core_info;
if (!cdm_hw->open_count) {
CAM_DBG(CAM_CDM, "%s%u already streamed off. Open count %d",
core->name, core->id, cdm_hw->open_count);
return -EPERM;
}
CAM_DBG(CAM_CDM, "streaming off %s%u internally",
core->name, core->id);
rc = cam_hw_cdm_pf_deinit(cdm_hw, NULL, 0);
if (rc)
CAM_ERR(CAM_CDM, "Deinit failed in stream off rc: %d", rc);
for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) {
client = core->clients[i];
if (!client)
continue;
mutex_lock(&client->lock);
client->stream_on = false;
mutex_unlock(&client->lock);
}
rc = cam_cpas_stop(core->cpas_handle);
if (rc)
CAM_ERR(CAM_CDM, "CPAS stop failed in stream off rc %d", rc);
cdm_hw->open_count = 0;
return rc;
}
int cam_cdm_stream_start(void *hw_priv,
void *start_args, uint32_t size)
{
int rc = 0;
if (!hw_priv)
return -EINVAL;
rc = cam_cdm_stream_ops_internal(hw_priv, start_args, true);
return rc;
}
int cam_cdm_stream_stop(void *hw_priv,
void *start_args, uint32_t size)
{
int rc = 0;
if (!hw_priv)
return -EINVAL;
rc = cam_cdm_stream_ops_internal(hw_priv, start_args, false);
return rc;
}
int cam_cdm_process_cmd(void *hw_priv,
uint32_t cmd, void *cmd_args, uint32_t arg_size)
{
struct cam_hw_info *cdm_hw = hw_priv;
struct cam_cdm *core = NULL;
int rc = -EINVAL;
if ((!hw_priv) || (!cmd_args) ||
(cmd >= CAM_CDM_HW_INTF_CMD_INVALID))
return rc;
core = (struct cam_cdm *)cdm_hw->core_info;
/*
* When CDM has encountered a page fault, other than release no
* other command will be serviced. PF handler notifies all clients
* on the error, clients are expected to handle it, and release
* its reference to the CDM core.
*/
if (test_bit(CAM_CDM_PF_HW_STATUS, &core->cdm_status) &&
(cmd != CAM_CDM_HW_INTF_CMD_RELEASE)) {
CAM_ERR(CAM_CDM,
"%s%u has encountered a page fault, unable to service cmd %u",
core->name, core->id, cmd);
return -EAGAIN;
}
switch (cmd) {
case CAM_CDM_HW_INTF_CMD_SUBMIT_BL: {
struct cam_cdm_hw_intf_cmd_submit_bl *req;
int idx;
struct cam_cdm_client *client;
if (sizeof(struct cam_cdm_hw_intf_cmd_submit_bl) != arg_size) {
CAM_ERR(CAM_CDM, "Invalid CDM cmd %d arg size=%x", cmd,
arg_size);
break;
}
req = (struct cam_cdm_hw_intf_cmd_submit_bl *)cmd_args;
if ((req->data->type < 0) ||
(req->data->type > CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA)) {
CAM_ERR(CAM_CDM, "Invalid req bl cmd addr type=%d",
req->data->type);
break;
}
idx = CAM_CDM_GET_CLIENT_IDX(req->handle);
client = core->clients[idx];
if ((!client) || (req->handle != client->handle)) {
CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client,
req->handle);
break;
}
cam_cdm_get_client_refcount(client);
if (req->data->flag &&
(!client->data.cam_cdm_callback)) {
CAM_ERR(CAM_CDM,
"CDM request cb without registering cb");
cam_cdm_put_client_refcount(client);
break;
}
if (client->stream_on != true) {
CAM_ERR(CAM_CDM,
"Invalid CDM needs to be streamed ON first");
cam_cdm_put_client_refcount(client);
break;
}
if (core->id == CAM_CDM_VIRTUAL)
rc = cam_virtual_cdm_submit_bl(cdm_hw, req, client);
else
rc = cam_hw_cdm_submit_bl(cdm_hw, req, client);
cam_cdm_put_client_refcount(client);
break;
}
case CAM_CDM_HW_INTF_CMD_ACQUIRE: {
struct cam_cdm_acquire_data *data;
int idx;
struct cam_cdm_client *client;
if (sizeof(struct cam_cdm_acquire_data) != arg_size) {
CAM_ERR(CAM_CDM, "Invalid CDM cmd %d arg size=%x", cmd,
arg_size);
break;
}
mutex_lock(&cdm_hw->hw_mutex);
data = (struct cam_cdm_acquire_data *)cmd_args;
CAM_DBG(CAM_CDM, "Trying to acquire client=%s in hw idx=%d",
data->identifier, core->index);
if (data->priority >= CAM_CDM_BL_FIFO_MAX) {
mutex_unlock(&cdm_hw->hw_mutex);
CAM_ERR(CAM_CDM,
"Invalid priority requested %d",
data->priority);
rc = -EINVAL;
break;
}
if (core->id != CAM_CDM_VIRTUAL &&
core->bl_fifo[data->priority].bl_depth == 0) {
mutex_unlock(&cdm_hw->hw_mutex);
CAM_ERR(CAM_CDM,
"FIFO %d not supported for core %d",
data->priority,
core->id);
rc = -EINVAL;
break;
}
idx = cam_cdm_find_free_client_slot(core);
if ((idx < 0) || (core->clients[idx])) {
mutex_unlock(&cdm_hw->hw_mutex);
CAM_ERR(CAM_CDM,
"Fail to client slots, client=%s in hw idx=%d",
data->identifier, core->index);
break;
}
core->clients[idx] = kzalloc(sizeof(struct cam_cdm_client),
GFP_KERNEL);
if (!core->clients[idx]) {
mutex_unlock(&cdm_hw->hw_mutex);
rc = -ENOMEM;
break;
}
core->num_active_clients++;
mutex_unlock(&cdm_hw->hw_mutex);
client = core->clients[idx];
mutex_init(&client->lock);
data->ops = core->ops;
if (core->id == CAM_CDM_VIRTUAL) {
data->cdm_version.major = 1;
data->cdm_version.minor = 0;
data->cdm_version.incr = 0;
data->cdm_version.reserved = 0;
data->ops = cam_cdm_get_ops(0,
&data->cdm_version, true);
if (!data->ops) {
mutex_destroy(&client->lock);
mutex_lock(&cdm_hw->hw_mutex);
kfree(core->clients[idx]);
core->clients[idx] = NULL;
core->num_active_clients--;
mutex_unlock(
&cdm_hw->hw_mutex);
rc = -EPERM;
CAM_ERR(CAM_CDM, "Invalid ops for virtual cdm");
break;
}
} else {
data->cdm_version = core->version;
}
cam_cdm_get_client_refcount(client);
mutex_lock(&client->lock);
memcpy(&client->data, data,
sizeof(struct cam_cdm_acquire_data));
client->handle = CAM_CDM_CREATE_CLIENT_HANDLE(
core->index,
data->priority,
idx);
client->stream_on = false;
data->handle = client->handle;
CAM_DBG(CAM_CDM, "Acquired client=%s in hwidx=%d",
data->identifier, core->index);
mutex_unlock(&client->lock);
rc = 0;
break;
}
case CAM_CDM_HW_INTF_CMD_RELEASE: {
uint32_t *handle = cmd_args;
int idx;
struct cam_cdm_client *client;
if (sizeof(uint32_t) != arg_size) {
CAM_ERR(CAM_CDM,
"Invalid CDM cmd %d size=%x for handle=%x",
cmd, arg_size, *handle);
return -EINVAL;
}
idx = CAM_CDM_GET_CLIENT_IDX(*handle);
mutex_lock(&cdm_hw->hw_mutex);
client = core->clients[idx];
if ((!client) || (*handle != client->handle)) {
CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x",
client, *handle);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
cam_cdm_put_client_refcount(client);
mutex_lock(&client->lock);
if (client->refcount != 0) {
CAM_ERR(CAM_CDM, "CDM Client refcount not zero %d",
client->refcount);
rc = -EPERM;
mutex_unlock(&client->lock);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
core->clients[idx] = NULL;
mutex_unlock(&client->lock);
mutex_destroy(&client->lock);
kfree(client);
if (core->num_active_clients)
core->num_active_clients--;
else
CAM_ERR(CAM_CDM,
"Invalid active client decrement %u for %s%u",
core->num_active_clients, core->name, core->id);
if (!core->num_active_clients) {
CAM_DBG(CAM_CDM, "Clear cdm status bits for %s%u",
core->name, core->id);
core->cdm_status = 0;
}
mutex_unlock(&cdm_hw->hw_mutex);
rc = 0;
break;
}
case CAM_CDM_HW_INTF_CMD_RESET_HW: {
uint32_t *handle = cmd_args;
int idx;
struct cam_cdm_client *client;
if (sizeof(uint32_t) != arg_size) {
CAM_ERR(CAM_CDM,
"Invalid CDM cmd %d size=%x for handle=%x",
cmd, arg_size, *handle);
return -EINVAL;
}
idx = CAM_CDM_GET_CLIENT_IDX(*handle);
mutex_lock(&cdm_hw->hw_mutex);
client = core->clients[idx];
if (!client) {
CAM_ERR(CAM_CDM,
"Client not present for handle %d",
*handle);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
if (*handle != client->handle) {
CAM_ERR(CAM_CDM,
"handle mismatch, client handle %d index %d received handle %d",
client->handle, idx, *handle);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
rc = cam_hw_cdm_reset_hw(cdm_hw, *handle);
if (rc) {
CAM_ERR(CAM_CDM,
"CDM HW reset failed for handle 0x%x rc = %d",
*handle, rc);
} else {
CAM_INFO_RATE_LIMIT(CAM_CDM,
"CDM HW reset done for handle 0x%x",
*handle);
}
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
case CAM_CDM_HW_INTF_CMD_FLUSH_HW: {
uint32_t *handle = cmd_args;
int idx;
struct cam_cdm_client *client;
if (sizeof(uint32_t) != arg_size) {
CAM_ERR(CAM_CDM,
"Invalid CDM cmd %d size=%x for handle=%x",
cmd, arg_size, *handle);
return -EINVAL;
}
idx = CAM_CDM_GET_CLIENT_IDX(*handle);
mutex_lock(&cdm_hw->hw_mutex);
client = core->clients[idx];
if (!client) {
CAM_ERR(CAM_CDM,
"Client not present for handle %d",
*handle);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
if (*handle != client->handle) {
CAM_ERR(CAM_CDM,
"handle mismatch, client handle %d index %d received handle %d",
client->handle, idx, *handle);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
rc = cam_hw_cdm_flush_hw(cdm_hw, *handle);
if (rc) {
CAM_ERR(CAM_CDM,
"CDM HW flush failed for handle 0x%x rc = %d",
*handle, rc);
} else {
CAM_INFO_RATE_LIMIT(CAM_CDM,
"CDM HW flush done for handle 0x%x",
*handle);
}
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
case CAM_CDM_HW_INTF_CMD_HANDLE_ERROR: {
uint32_t *handle = cmd_args;
int idx;
struct cam_cdm_client *client;
if (sizeof(uint32_t) != arg_size) {
CAM_ERR(CAM_CDM,
"Invalid CDM cmd %d size=%x for handle=%x",
cmd, arg_size, *handle);
return -EINVAL;
}
idx = CAM_CDM_GET_CLIENT_IDX(*handle);
mutex_lock(&cdm_hw->hw_mutex);
client = core->clients[idx];
if (!client) {
CAM_ERR(CAM_CDM,
"Client not present for handle %d",
*handle);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
if (*handle != client->handle) {
CAM_ERR(CAM_CDM,
"handle mismatch, client handle %d index %d received handle %d",
client->handle, idx, *handle);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
rc = cam_hw_cdm_handle_error_info(cdm_hw, *handle);
if (rc) {
CAM_ERR(CAM_CDM,
"CDM HW handle error failed for handle 0x%x rc = %d",
*handle, rc);
} else {
CAM_INFO_RATE_LIMIT(CAM_CDM,
"CDM HW handle error done for handle 0x%x",
*handle);
}
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
case CAM_CDM_HW_INTF_CMD_HANG_DETECT: {
uint32_t *handle = cmd_args;
int idx;
struct cam_cdm_client *client;
if (sizeof(uint32_t) != arg_size) {
CAM_ERR(CAM_CDM,
"Invalid CDM cmd %d size=%x for handle=%x",
cmd, arg_size, *handle);
return -EINVAL;
}
idx = CAM_CDM_GET_CLIENT_IDX(*handle);
client = core->clients[idx];
if (!client) {
CAM_ERR(CAM_CDM,
"Client not present for handle %d",
*handle);
break;
}
if (*handle != client->handle) {
CAM_ERR(CAM_CDM,
"handle mismatch, client handle %d index %d received handle %d",
client->handle, idx, *handle);
break;
}
rc = cam_hw_cdm_hang_detect(cdm_hw, *handle);
break;
}
case CAM_CDM_HW_INTF_DUMP_DBG_REGS:
{
uint32_t *handle = cmd_args;
if (sizeof(uint32_t) != arg_size) {
CAM_ERR(CAM_CDM,
"Invalid CDM cmd %d size=%x for handle=0x%x",
cmd, arg_size, *handle);
return -EINVAL;
}
mutex_lock(&cdm_hw->hw_mutex);
cam_hw_cdm_dump_core_debug_registers(cdm_hw, true);
mutex_unlock(&cdm_hw->hw_mutex);
break;
}
default:
CAM_ERR(CAM_CDM, "CDM HW intf command not valid =%d", cmd);
break;
}
return rc;
}

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_core_common.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CDM_CORE_COMMON_H_
#define _CAM_CDM_CORE_COMMON_H_
#include "cam_mem_mgr.h"
#define CAM_CDM100_VERSION 0x10000000
#define CAM_CDM110_VERSION 0x10010000
#define CAM_CDM120_VERSION 0x10020000
#define CAM_CDM200_VERSION 0x20000000
#define CAM_CDM210_VERSION 0x20010000
#define CAM_CDM220_VERSION 0x20020000
#define CAM_CDM_AHB_BURST_LEN_1 (BIT(1) - 1)
#define CAM_CDM_AHB_BURST_LEN_4 (BIT(2) - 1)
#define CAM_CDM_AHB_BURST_LEN_8 (BIT(3) - 1)
#define CAM_CDM_AHB_BURST_LEN_16 (BIT(4) - 1)
#define CAM_CDM_AHB_BURST_EN BIT(4)
#define CAM_CDM_AHB_STOP_ON_ERROR BIT(8)
#define CAM_CDM_ARB_SEL_RR BIT(16)
#define CAM_CDM_IMPLICIT_WAIT_EN BIT(17)
#define CAM_CDM_PAUSE_CORE_ENABLE_MASK (0x1 << 1)
extern struct cam_cdm_utils_ops CDM170_ops;
int cam_hw_cdm_init(void *hw_priv, void *init_hw_args, uint32_t arg_size);
int cam_hw_cdm_deinit(void *hw_priv, void *init_hw_args, uint32_t arg_size);
int cam_hw_cdm_pf_deinit(void *hw_priv, void *init_hw_args,
uint32_t arg_size);
int cam_cdm_get_caps(void *hw_priv, void *get_hw_cap_args, uint32_t arg_size);
int cam_cdm_stream_ops_internal(void *hw_priv, void *start_args,
bool operation);
int cam_cdm_pf_stream_off_all_clients(struct cam_hw_info *cdm_hw);
int cam_cdm_stream_start(void *hw_priv, void *start_args, uint32_t size);
int cam_cdm_stream_stop(void *hw_priv, void *start_args, uint32_t size);
int cam_cdm_process_cmd(void *hw_priv, uint32_t cmd, void *cmd_args,
uint32_t arg_size);
bool cam_cdm_set_cam_hw_version(
uint32_t ver, struct cam_hw_version *cam_version);
bool cam_cdm_cpas_cb(uint32_t client_handle, void *userdata,
struct cam_cpas_irq_data *irq_data);
struct cam_cdm_utils_ops *cam_cdm_get_ops(
uint32_t ver, struct cam_hw_version *cam_version, bool by_cam_version);
int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw,
struct cam_cdm_hw_intf_cmd_submit_bl *req,
struct cam_cdm_client *client);
int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
struct cam_cdm_hw_intf_cmd_submit_bl *req,
struct cam_cdm_client *client);
int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle);
int cam_hw_cdm_flush_hw(struct cam_hw_info *cdm_hw, uint32_t handle);
int cam_hw_cdm_hang_detect(struct cam_hw_info *cdm_hw, uint32_t handle);
int cam_hw_cdm_handle_error_info(struct cam_hw_info *cdm_hw, uint32_t handle);
struct cam_cdm_bl_cb_request_entry *cam_cdm_find_request_by_bl_tag(
uint32_t tag, struct list_head *bl_list);
void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw,
enum cam_cdm_cb_status status, void *data);
void cam_hw_cdm_dump_core_debug_registers(
struct cam_hw_info *cdm_hw, bool pause_core);
int cam_cdm_util_cpas_start(struct cam_hw_info *cdm_hw);
#endif /* _CAM_CDM_CORE_COMMON_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_core.c Normal file
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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_reg_1_0.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_cdm.h"
static struct cam_version_reg cdm_hw_1_0_titan_version = {
.hw_version = 0x4,
};
struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_0_bl_pending_req0 = {
.rb_offset = 0x6c,
.rb_mask = 0x7F,
.rb_num_fifo = 0x1,
.rb_next_fifo_shift = 0x0,
};
static struct cam_cdm_irq_regs cdm_hw_1_0_irq0 = {
.irq_mask = 0x30,
.irq_clear = 0x34,
.irq_clear_cmd = 0x38,
.irq_set = 0x3c,
.irq_set_cmd = 0x40,
.irq_status = 0x44,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_1_0_bl_fifo0 = {
.bl_fifo_base = 0x50,
.bl_fifo_len = 0x54,
.bl_fifo_store = 0x58,
.bl_fifo_cfg = 0x5c,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg0 = {
.scratch_reg = 0x90,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg1 = {
.scratch_reg = 0x94,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg2 = {
.scratch_reg = 0x98,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg3 = {
.scratch_reg = 0x9c,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg4 = {
.scratch_reg = 0xa0,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg5 = {
.scratch_reg = 0xa4,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg6 = {
.scratch_reg = 0xa8,
};
static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg7 = {
.scratch_reg = 0xac,
};
static struct cam_cdm_perf_mon_regs cdm_1_0_perf_mon0 = {
.perf_mon_ctrl = 0x110,
.perf_mon_0 = 0x114,
.perf_mon_1 = 0x118,
.perf_mon_2 = 0x11c,
};
static struct cam_cdm_comp_wait_status cdm_1_0_comp_wait_status0 = {
.comp_wait_status = 0x88,
};
static struct cam_cdm_comp_wait_status cdm_1_0_comp_wait_status1 = {
.comp_wait_status = 0x8c,
};
static struct cam_cdm_common_regs cdm_hw_1_0_cmn_reg_offset = {
.cdm_hw_version = 0x0,
.cam_version = &cdm_hw_1_0_titan_version,
.rst_cmd = 0x10,
.cgc_cfg = 0x14,
.core_cfg = 0x18,
.core_en = 0x1c,
.fe_cfg = 0x20,
.cdm_status = 0x0,
.irq_context_status = 0x0,
.bl_fifo_rb = 0x60,
.bl_fifo_base_rb = 0x64,
.bl_fifo_len_rb = 0x68,
.usr_data = 0x80,
.wait_status = 0x84,
.last_ahb_addr = 0xd0,
.last_ahb_data = 0xd4,
.core_debug = 0xd8,
.last_ahb_err_addr = 0xe0,
.last_ahb_err_data = 0xe4,
.current_bl_base = 0xe8,
.current_bl_len = 0xec,
.current_used_ahb_base = 0xf0,
.debug_status = 0xf4,
.bus_misr_cfg0 = 0x100,
.bus_misr_cfg1 = 0x104,
.bus_misr_rd_val = 0x108,
.pending_req = {
&cdm_hw_1_0_bl_pending_req0,
NULL,
},
.comp_wait = {
&cdm_1_0_comp_wait_status0,
&cdm_1_0_comp_wait_status1,
},
.perf_mon = {
&cdm_1_0_perf_mon0,
NULL,
},
.scratch = {
&cdm_1_0_scratch_reg0,
&cdm_1_0_scratch_reg1,
&cdm_1_0_scratch_reg2,
&cdm_1_0_scratch_reg3,
&cdm_1_0_scratch_reg4,
&cdm_1_0_scratch_reg5,
&cdm_1_0_scratch_reg6,
&cdm_1_0_scratch_reg7,
NULL,
NULL,
NULL,
NULL,
},
.perf_reg = NULL,
.icl_reg = NULL,
.spare = 0x200,
};
static struct cam_cdm_common_reg_data cdm_hw_1_0_cmn_reg_data = {
.num_bl_fifo = 0x1,
.num_bl_fifo_irq = 0x1,
.num_bl_pending_req_reg = 0x1,
.num_scratch_reg = 0x8,
};
static struct cam_cdm_hw_reg_offset cam_cdm_1_0_reg_offset = {
.cmn_reg = &cdm_hw_1_0_cmn_reg_offset,
.bl_fifo_reg = {
&cdm_hw_1_0_bl_fifo0,
NULL,
NULL,
NULL,
},
.irq_reg = {
&cdm_hw_1_0_irq0,
NULL,
NULL,
NULL,
},
.reg_data = &cdm_hw_1_0_cmn_reg_data,
};

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_reg_1_1.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_cdm.h"
static struct cam_version_reg cdm_hw_1_1_titan_version = {
.hw_version = 0x4,
};
struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_1_bl_pending_req0 = {
.rb_offset = 0x6c,
.rb_mask = 0x7f,
.rb_num_fifo = 0x1,
.rb_next_fifo_shift = 0x0,
};
static struct cam_cdm_irq_regs cdm_hw_1_1_irq0 = {
.irq_mask = 0x30,
.irq_clear = 0x34,
.irq_clear_cmd = 0x38,
.irq_set = 0x3c,
.irq_set_cmd = 0x40,
.irq_status = 0x44,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_1_1_bl_fifo0 = {
.bl_fifo_base = 0x50,
.bl_fifo_len = 0x54,
.bl_fifo_store = 0x58,
.bl_fifo_cfg = 0x5c,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg0 = {
.scratch_reg = 0x90,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg1 = {
.scratch_reg = 0x94,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg2 = {
.scratch_reg = 0x98,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg3 = {
.scratch_reg = 0x9c,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg4 = {
.scratch_reg = 0xa0,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg5 = {
.scratch_reg = 0xa4,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg6 = {
.scratch_reg = 0xa8,
};
static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg7 = {
.scratch_reg = 0xac,
};
static struct cam_cdm_perf_mon_regs cdm_1_1_perf_mon0 = {
.perf_mon_ctrl = 0x110,
.perf_mon_0 = 0x114,
.perf_mon_1 = 0x118,
.perf_mon_2 = 0x11c,
};
static struct cam_cdm_comp_wait_status cdm_1_1_comp_wait_status0 = {
.comp_wait_status = 0x88,
};
static struct cam_cdm_comp_wait_status cdm_1_1_comp_wait_status1 = {
.comp_wait_status = 0x8c,
};
static struct cam_cdm_common_regs cdm_hw_1_1_cmn_reg_offset = {
.cdm_hw_version = 0x0,
.cam_version = &cdm_hw_1_1_titan_version,
.rst_cmd = 0x10,
.cgc_cfg = 0x14,
.core_cfg = 0x18,
.core_en = 0x1c,
.fe_cfg = 0x20,
.cdm_status = 0x0,
.irq_context_status = 0x0,
.bl_fifo_rb = 0x60,
.bl_fifo_base_rb = 0x64,
.bl_fifo_len_rb = 0x68,
.usr_data = 0x80,
.wait_status = 0x84,
.last_ahb_addr = 0xd0,
.last_ahb_data = 0xd4,
.core_debug = 0xd8,
.last_ahb_err_addr = 0xe0,
.last_ahb_err_data = 0xe4,
.current_bl_base = 0xe8,
.current_bl_len = 0xec,
.current_used_ahb_base = 0xf0,
.debug_status = 0xf4,
.bus_misr_cfg0 = 0x100,
.bus_misr_cfg1 = 0x104,
.bus_misr_rd_val = 0x108,
.pending_req = {
&cdm_hw_1_1_bl_pending_req0,
NULL,
},
.comp_wait = {
&cdm_1_1_comp_wait_status0,
&cdm_1_1_comp_wait_status1,
},
.perf_mon = {
&cdm_1_1_perf_mon0,
NULL,
},
.scratch = {
&cdm_1_1_scratch_reg0,
&cdm_1_1_scratch_reg1,
&cdm_1_1_scratch_reg2,
&cdm_1_1_scratch_reg3,
&cdm_1_1_scratch_reg4,
&cdm_1_1_scratch_reg5,
&cdm_1_1_scratch_reg6,
&cdm_1_1_scratch_reg7,
NULL,
NULL,
NULL,
NULL,
},
.perf_reg = NULL,
.icl_reg = NULL,
.spare = 0x1fc,
};
static struct cam_cdm_common_reg_data cdm_hw_1_1_cmn_reg_data = {
.num_bl_fifo = 0x1,
.num_bl_fifo_irq = 0x1,
.num_bl_pending_req_reg = 0x1,
.num_scratch_reg = 0x8,
};
struct cam_cdm_hw_reg_offset cam_cdm_1_1_reg_offset = {
.cmn_reg = &cdm_hw_1_1_cmn_reg_offset,
.bl_fifo_reg = {
&cdm_hw_1_1_bl_fifo0,
NULL,
NULL,
NULL,
},
.irq_reg = {
&cdm_hw_1_1_irq0,
NULL,
NULL,
NULL,
},
.reg_data = &cdm_hw_1_1_cmn_reg_data,
};

183
qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_reg_1_2.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_cdm.h"
static struct cam_version_reg cdm_hw_1_2_titan_version = {
.hw_version = 0x4,
};
struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_2_bl_pending_req0 = {
.rb_offset = 0x6c,
.rb_mask = 0x7f,
.rb_num_fifo = 0x1,
.rb_next_fifo_shift = 0x0,
};
static struct cam_cdm_irq_regs cdm_hw_1_2_irq0 = {
.irq_mask = 0x30,
.irq_clear = 0x34,
.irq_clear_cmd = 0x38,
.irq_set = 0x3c,
.irq_set_cmd = 0x40,
.irq_status = 0x44,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_1_2_bl_fifo0 = {
.bl_fifo_base = 0x50,
.bl_fifo_len = 0x54,
.bl_fifo_store = 0x58,
.bl_fifo_cfg = 0x5c,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg0 = {
.scratch_reg = 0x90,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg1 = {
.scratch_reg = 0x94,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg2 = {
.scratch_reg = 0x98,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg3 = {
.scratch_reg = 0x9c,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg4 = {
.scratch_reg = 0xa0,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg5 = {
.scratch_reg = 0xa4,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg6 = {
.scratch_reg = 0xa8,
};
static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg7 = {
.scratch_reg = 0xac,
};
static struct cam_cdm_perf_mon_regs cdm_1_2_perf_mon0 = {
.perf_mon_ctrl = 0x110,
.perf_mon_0 = 0x114,
.perf_mon_1 = 0x118,
.perf_mon_2 = 0x11c,
};
static struct cam_cdm_comp_wait_status cdm_1_2_comp_wait_status0 = {
.comp_wait_status = 0x88,
};
static struct cam_cdm_comp_wait_status cdm_1_2_comp_wait_status1 = {
.comp_wait_status = 0x8c,
};
static struct cam_cdm_perf_regs cdm_1_2_perf = {
.count_cfg_0 = 0x180,
.always_count_val = 0x184,
.busy_count_val = 0x188,
.stall_axi_count_val = 0x18c,
.count_status = 0x190,
};
static struct cam_cdm_icl_data_regs cdm_1_2_icl_data = {
.icl_last_data_0 = 0x1c0,
.icl_last_data_1 = 0x1c4,
.icl_last_data_2 = 0x1c8,
.icl_inv_data = 0x1cc,
};
static struct cam_cdm_icl_regs cdm_1_2_icl = {
.data_regs = &cdm_1_2_icl_data,
.misc_regs = NULL,
};
static struct cam_cdm_common_regs cdm_hw_1_2_cmn_reg_offset = {
.cdm_hw_version = 0x0,
.cam_version = &cdm_hw_1_2_titan_version,
.rst_cmd = 0x10,
.cgc_cfg = 0x14,
.core_cfg = 0x18,
.core_en = 0x1c,
.fe_cfg = 0x20,
.cdm_status = 0x0,
.irq_context_status = 0x0,
.bl_fifo_rb = 0x60,
.bl_fifo_base_rb = 0x64,
.bl_fifo_len_rb = 0x68,
.usr_data = 0x80,
.wait_status = 0x84,
.last_ahb_addr = 0xd0,
.last_ahb_data = 0xd4,
.core_debug = 0xd8,
.last_ahb_err_addr = 0xe0,
.last_ahb_err_data = 0xe4,
.current_bl_base = 0xe8,
.current_bl_len = 0xec,
.current_used_ahb_base = 0xf0,
.debug_status = 0xf4,
.bus_misr_cfg0 = 0x100,
.bus_misr_cfg1 = 0x104,
.bus_misr_rd_val = 0x108,
.pending_req = {
&cdm_hw_1_2_bl_pending_req0,
NULL,
},
.comp_wait = {
&cdm_1_2_comp_wait_status0,
&cdm_1_2_comp_wait_status1,
},
.perf_mon = {
&cdm_1_2_perf_mon0,
NULL,
},
.scratch = {
&cdm_1_2_scratch_reg0,
&cdm_1_2_scratch_reg1,
&cdm_1_2_scratch_reg2,
&cdm_1_2_scratch_reg3,
&cdm_1_2_scratch_reg4,
&cdm_1_2_scratch_reg5,
&cdm_1_2_scratch_reg6,
&cdm_1_2_scratch_reg7,
NULL,
NULL,
NULL,
NULL,
},
.perf_reg = &cdm_1_2_perf,
.icl_reg = &cdm_1_2_icl,
.spare = 0x1fc,
};
static struct cam_cdm_common_reg_data cdm_hw_1_2_cmn_reg_data = {
.num_bl_fifo = 0x1,
.num_bl_fifo_irq = 0x1,
.num_bl_pending_req_reg = 0x1,
.num_scratch_reg = 0x8,
};
struct cam_cdm_hw_reg_offset cam_cdm_1_2_reg_offset = {
.cmn_reg = &cdm_hw_1_2_cmn_reg_offset,
.bl_fifo_reg = {
&cdm_hw_1_2_bl_fifo0,
NULL,
NULL,
NULL,
},
.irq_reg = {
&cdm_hw_1_2_irq0,
NULL,
NULL,
NULL,
},
.reg_data = &cdm_hw_1_2_cmn_reg_data,
};

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_cdm.h"
struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_0_bl_pending_req0 = {
.rb_offset = 0x6c,
.rb_mask = 0x1ff,
.rb_num_fifo = 0x2,
.rb_next_fifo_shift = 0x10,
};
struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_0_bl_pending_req1 = {
.rb_offset = 0x70,
.rb_mask = 0x1ff,
.rb_num_fifo = 0x2,
.rb_next_fifo_shift = 0x10,
};
static struct cam_cdm_irq_regs cdm_hw_2_0_irq0 = {
.irq_mask = 0x30,
.irq_clear = 0x34,
.irq_clear_cmd = 0x38,
.irq_set = 0x3c,
.irq_set_cmd = 0x40,
.irq_status = 0x44,
};
static struct cam_cdm_irq_regs cdm_hw_2_0_irq1 = {
.irq_mask = 0x130,
.irq_clear = 0x134,
.irq_clear_cmd = 0x138,
.irq_set = 0x13c,
.irq_set_cmd = 0x140,
.irq_status = 0x144,
};
static struct cam_cdm_irq_regs cdm_hw_2_0_irq2 = {
.irq_mask = 0x230,
.irq_clear = 0x234,
.irq_clear_cmd = 0x238,
.irq_set = 0x23c,
.irq_set_cmd = 0x240,
.irq_status = 0x244,
};
static struct cam_cdm_irq_regs cdm_hw_2_0_irq3 = {
.irq_mask = 0x330,
.irq_clear = 0x334,
.irq_clear_cmd = 0x338,
.irq_set = 0x33c,
.irq_set_cmd = 0x340,
.irq_status = 0x344,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo0 = {
.bl_fifo_base = 0x50,
.bl_fifo_len = 0x54,
.bl_fifo_store = 0x58,
.bl_fifo_cfg = 0x5c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo1 = {
.bl_fifo_base = 0x150,
.bl_fifo_len = 0x154,
.bl_fifo_store = 0x158,
.bl_fifo_cfg = 0x15c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo2 = {
.bl_fifo_base = 0x250,
.bl_fifo_len = 0x254,
.bl_fifo_store = 0x258,
.bl_fifo_cfg = 0x25c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo3 = {
.bl_fifo_base = 0x350,
.bl_fifo_len = 0x354,
.bl_fifo_store = 0x358,
.bl_fifo_cfg = 0x35c,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg0 = {
.scratch_reg = 0x90,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg1 = {
.scratch_reg = 0x94,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg2 = {
.scratch_reg = 0x98,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg3 = {
.scratch_reg = 0x9c,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg4 = {
.scratch_reg = 0xa0,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg5 = {
.scratch_reg = 0xa4,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg6 = {
.scratch_reg = 0xa8,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg7 = {
.scratch_reg = 0xac,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg8 = {
.scratch_reg = 0xb0,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg9 = {
.scratch_reg = 0xb4,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg10 = {
.scratch_reg = 0xb8,
};
static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg11 = {
.scratch_reg = 0xbc,
};
static struct cam_cdm_perf_mon_regs cdm_2_0_perf_mon0 = {
.perf_mon_ctrl = 0x110,
.perf_mon_0 = 0x114,
.perf_mon_1 = 0x118,
.perf_mon_2 = 0x11c,
};
static struct cam_cdm_perf_mon_regs cdm_2_0_perf_mon1 = {
.perf_mon_ctrl = 0x120,
.perf_mon_0 = 0x124,
.perf_mon_1 = 0x128,
.perf_mon_2 = 0x12c,
};
static struct cam_cdm_comp_wait_status cdm_2_0_comp_wait_status0 = {
.comp_wait_status = 0x88,
};
static struct cam_cdm_comp_wait_status cdm_2_0_comp_wait_status1 = {
.comp_wait_status = 0x8c,
};
static struct cam_cdm_icl_data_regs cdm_2_0_icl_data = {
.icl_last_data_0 = 0x1c0,
.icl_last_data_1 = 0x1c4,
.icl_last_data_2 = 0x1c8,
.icl_inv_data = 0x1cc,
};
static struct cam_cdm_icl_misc_regs cdm_2_0_icl_misc = {
.icl_inv_bl_addr = 0x1d0,
.icl_status = 0x1d4,
};
static struct cam_cdm_icl_regs cdm_2_0_icl = {
.data_regs = &cdm_2_0_icl_data,
.misc_regs = &cdm_2_0_icl_misc,
};
static struct cam_cdm_common_regs cdm_hw_2_0_cmn_reg_offset = {
.cdm_hw_version = 0x0,
.cam_version = NULL,
.rst_cmd = 0x10,
.cgc_cfg = 0x14,
.core_cfg = 0x18,
.core_en = 0x1c,
.fe_cfg = 0x20,
.cdm_status = 0x0,
.irq_context_status = 0x0,
.bl_fifo_rb = 0x60,
.bl_fifo_base_rb = 0x64,
.bl_fifo_len_rb = 0x68,
.usr_data = 0x80,
.wait_status = 0x84,
.last_ahb_addr = 0xd0,
.last_ahb_data = 0xd4,
.core_debug = 0xd8,
.last_ahb_err_addr = 0xe0,
.last_ahb_err_data = 0xe4,
.current_bl_base = 0xe8,
.current_bl_len = 0xec,
.current_used_ahb_base = 0xf0,
.debug_status = 0xf4,
.bus_misr_cfg0 = 0x100,
.bus_misr_cfg1 = 0x104,
.bus_misr_rd_val = 0x108,
.pending_req = {
&cdm_hw_2_0_bl_pending_req0,
&cdm_hw_2_0_bl_pending_req1,
},
.comp_wait = {
&cdm_2_0_comp_wait_status0,
&cdm_2_0_comp_wait_status1,
},
.perf_mon = {
&cdm_2_0_perf_mon0,
&cdm_2_0_perf_mon1,
},
.scratch = {
&cdm_2_0_scratch_reg0,
&cdm_2_0_scratch_reg1,
&cdm_2_0_scratch_reg2,
&cdm_2_0_scratch_reg3,
&cdm_2_0_scratch_reg4,
&cdm_2_0_scratch_reg5,
&cdm_2_0_scratch_reg6,
&cdm_2_0_scratch_reg7,
&cdm_2_0_scratch_reg8,
&cdm_2_0_scratch_reg9,
&cdm_2_0_scratch_reg10,
&cdm_2_0_scratch_reg11,
},
.perf_reg = NULL,
.icl_reg = &cdm_2_0_icl,
.spare = 0x1fc,
};
static struct cam_cdm_common_reg_data cdm_hw_2_0_cmn_reg_data = {
.num_bl_fifo = 0x4,
.num_bl_fifo_irq = 0x4,
.num_bl_pending_req_reg = 0x2,
.num_scratch_reg = 0xc,
};
struct cam_cdm_hw_reg_offset cam_cdm_2_0_reg_offset = {
.cmn_reg = &cdm_hw_2_0_cmn_reg_offset,
.bl_fifo_reg = {
&cdm_hw_2_0_bl_fifo0,
&cdm_hw_2_0_bl_fifo1,
&cdm_hw_2_0_bl_fifo2,
&cdm_hw_2_0_bl_fifo3,
},
.irq_reg = {
&cdm_hw_2_0_irq0,
&cdm_hw_2_0_irq1,
&cdm_hw_2_0_irq2,
&cdm_hw_2_0_irq3,
},
.reg_data = &cdm_hw_2_0_cmn_reg_data,
};

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_reg_2_1.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_cdm.h"
struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_1_bl_pending_req0 = {
.rb_offset = 0x6c,
.rb_mask = 0x1ff,
.rb_num_fifo = 0x2,
.rb_next_fifo_shift = 0x10,
};
struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_1_bl_pending_req1 = {
.rb_offset = 0x70,
.rb_mask = 0x1ff,
.rb_num_fifo = 0x2,
.rb_next_fifo_shift = 0x10,
};
static struct cam_cdm_irq_regs cdm_hw_2_1_irq0 = {
.irq_mask = 0x30,
.irq_clear = 0x34,
.irq_clear_cmd = 0x38,
.irq_set = 0x3c,
.irq_set_cmd = 0x40,
.irq_status = 0x44,
};
static struct cam_cdm_irq_regs cdm_hw_2_1_irq1 = {
.irq_mask = 0x130,
.irq_clear = 0x134,
.irq_clear_cmd = 0x138,
.irq_set = 0x13c,
.irq_set_cmd = 0x140,
.irq_status = 0x144,
};
static struct cam_cdm_irq_regs cdm_hw_2_1_irq2 = {
.irq_mask = 0x230,
.irq_clear = 0x234,
.irq_clear_cmd = 0x238,
.irq_set = 0x23c,
.irq_set_cmd = 0x240,
.irq_status = 0x244,
};
static struct cam_cdm_irq_regs cdm_hw_2_1_irq3 = {
.irq_mask = 0x330,
.irq_clear = 0x334,
.irq_clear_cmd = 0x338,
.irq_set = 0x33c,
.irq_set_cmd = 0x340,
.irq_status = 0x344,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo0 = {
.bl_fifo_base = 0x50,
.bl_fifo_len = 0x54,
.bl_fifo_store = 0x58,
.bl_fifo_cfg = 0x5c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo1 = {
.bl_fifo_base = 0x150,
.bl_fifo_len = 0x154,
.bl_fifo_store = 0x158,
.bl_fifo_cfg = 0x15c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo2 = {
.bl_fifo_base = 0x250,
.bl_fifo_len = 0x254,
.bl_fifo_store = 0x258,
.bl_fifo_cfg = 0x25c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo3 = {
.bl_fifo_base = 0x350,
.bl_fifo_len = 0x354,
.bl_fifo_store = 0x358,
.bl_fifo_cfg = 0x35c,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg0 = {
.scratch_reg = 0x90,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg1 = {
.scratch_reg = 0x94,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg2 = {
.scratch_reg = 0x98,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg3 = {
.scratch_reg = 0x9c,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg4 = {
.scratch_reg = 0xa0,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg5 = {
.scratch_reg = 0xa4,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg6 = {
.scratch_reg = 0xa8,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg7 = {
.scratch_reg = 0xac,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg8 = {
.scratch_reg = 0xb0,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg9 = {
.scratch_reg = 0xb4,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg10 = {
.scratch_reg = 0xb8,
};
static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg11 = {
.scratch_reg = 0xbc,
};
static struct cam_cdm_perf_mon_regs cdm_2_1_perf_mon0 = {
.perf_mon_ctrl = 0x110,
.perf_mon_0 = 0x114,
.perf_mon_1 = 0x118,
.perf_mon_2 = 0x11c,
};
static struct cam_cdm_perf_mon_regs cdm_2_1_perf_mon1 = {
.perf_mon_ctrl = 0x120,
.perf_mon_0 = 0x124,
.perf_mon_1 = 0x128,
.perf_mon_2 = 0x12c,
};
static struct cam_cdm_comp_wait_status cdm_2_1_comp_wait_status0 = {
.comp_wait_status = 0x88,
};
static struct cam_cdm_comp_wait_status cdm_2_1_comp_wait_status1 = {
.comp_wait_status = 0x8c,
};
static struct cam_cdm_icl_data_regs cdm_2_1_icl_data = {
.icl_last_data_0 = 0x1c0,
.icl_last_data_1 = 0x1c4,
.icl_last_data_2 = 0x1c8,
.icl_inv_data = 0x1cc,
};
static struct cam_cdm_icl_misc_regs cdm_2_1_icl_misc = {
.icl_inv_bl_addr = 0x1d0,
.icl_status = 0x1d8,
};
static struct cam_cdm_icl_regs cdm_2_1_icl = {
.data_regs = &cdm_2_1_icl_data,
.misc_regs = &cdm_2_1_icl_misc,
};
static struct cam_cdm_common_regs cdm_hw_2_1_cmn_reg_offset = {
.cdm_hw_version = 0x0,
.cam_version = NULL,
.rst_cmd = 0x10,
.cgc_cfg = 0x14,
.core_cfg = 0x18,
.core_en = 0x1c,
.fe_cfg = 0x20,
.cdm_status = 0x0,
.irq_context_status = 0x2c,
.bl_fifo_rb = 0x60,
.bl_fifo_base_rb = 0x64,
.bl_fifo_len_rb = 0x68,
.usr_data = 0x80,
.wait_status = 0x84,
.last_ahb_addr = 0xd0,
.last_ahb_data = 0xd4,
.core_debug = 0xd8,
.last_ahb_err_addr = 0xe0,
.last_ahb_err_data = 0xe4,
.current_bl_base = 0xe8,
.current_bl_len = 0xec,
.current_used_ahb_base = 0xf0,
.debug_status = 0xf4,
.bus_misr_cfg0 = 0x100,
.bus_misr_cfg1 = 0x104,
.bus_misr_rd_val = 0x108,
.pending_req = {
&cdm_hw_2_1_bl_pending_req0,
&cdm_hw_2_1_bl_pending_req1,
},
.comp_wait = {
&cdm_2_1_comp_wait_status0,
&cdm_2_1_comp_wait_status1,
},
.perf_mon = {
&cdm_2_1_perf_mon0,
&cdm_2_1_perf_mon1,
},
.scratch = {
&cdm_2_1_scratch_reg0,
&cdm_2_1_scratch_reg1,
&cdm_2_1_scratch_reg2,
&cdm_2_1_scratch_reg3,
&cdm_2_1_scratch_reg4,
&cdm_2_1_scratch_reg5,
&cdm_2_1_scratch_reg6,
&cdm_2_1_scratch_reg7,
&cdm_2_1_scratch_reg8,
&cdm_2_1_scratch_reg9,
&cdm_2_1_scratch_reg10,
&cdm_2_1_scratch_reg11,
},
.perf_reg = NULL,
.icl_reg = &cdm_2_1_icl,
.spare = 0x3fc,
.priority_group_bit_offset = 20,
};
static struct cam_cdm_common_reg_data cdm_hw_2_1_cmn_reg_data = {
.num_bl_fifo = 0x4,
.num_bl_fifo_irq = 0x4,
.num_bl_pending_req_reg = 0x2,
.num_scratch_reg = 0xc,
};
struct cam_cdm_hw_reg_offset cam_cdm_2_1_reg_offset = {
.cmn_reg = &cdm_hw_2_1_cmn_reg_offset,
.bl_fifo_reg = {
&cdm_hw_2_1_bl_fifo0,
&cdm_hw_2_1_bl_fifo1,
&cdm_hw_2_1_bl_fifo2,
&cdm_hw_2_1_bl_fifo3,
},
.irq_reg = {
&cdm_hw_2_1_irq0,
&cdm_hw_2_1_irq1,
&cdm_hw_2_1_irq2,
&cdm_hw_2_1_irq3,
},
.reg_data = &cdm_hw_2_1_cmn_reg_data,
};

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_hw_reg_2_2.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_cdm.h"
#define CAM_CDM_PAUSE_CORE_DONE_MASK (0x1 << 1)
struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_2_bl_pending_req0 = {
.rb_offset = 0x6c,
.rb_mask = 0x1ff,
.rb_num_fifo = 0x2,
.rb_next_fifo_shift = 0x10,
};
struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_2_bl_pending_req1 = {
.rb_offset = 0x70,
.rb_mask = 0x1ff,
.rb_num_fifo = 0x2,
.rb_next_fifo_shift = 0x10,
};
static struct cam_cdm_irq_regs cdm_hw_2_2_irq0 = {
.irq_mask = 0x30,
.irq_clear = 0x34,
.irq_clear_cmd = 0x38,
.irq_set = 0x3c,
.irq_set_cmd = 0x40,
.irq_status = 0x44,
};
static struct cam_cdm_irq_regs cdm_hw_2_2_irq1 = {
.irq_mask = 0x130,
.irq_clear = 0x134,
.irq_clear_cmd = 0x138,
.irq_set = 0x13c,
.irq_set_cmd = 0x140,
.irq_status = 0x144,
};
static struct cam_cdm_irq_regs cdm_hw_2_2_irq2 = {
.irq_mask = 0x230,
.irq_clear = 0x234,
.irq_clear_cmd = 0x238,
.irq_set = 0x23c,
.irq_set_cmd = 0x240,
.irq_status = 0x244,
};
static struct cam_cdm_irq_regs cdm_hw_2_2_irq3 = {
.irq_mask = 0x330,
.irq_clear = 0x334,
.irq_clear_cmd = 0x338,
.irq_set = 0x33c,
.irq_set_cmd = 0x340,
.irq_status = 0x344,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo0 = {
.bl_fifo_base = 0x50,
.bl_fifo_len = 0x54,
.bl_fifo_store = 0x58,
.bl_fifo_cfg = 0x5c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo1 = {
.bl_fifo_base = 0x150,
.bl_fifo_len = 0x154,
.bl_fifo_store = 0x158,
.bl_fifo_cfg = 0x15c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo2 = {
.bl_fifo_base = 0x250,
.bl_fifo_len = 0x254,
.bl_fifo_store = 0x258,
.bl_fifo_cfg = 0x25c,
};
static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo3 = {
.bl_fifo_base = 0x350,
.bl_fifo_len = 0x354,
.bl_fifo_store = 0x358,
.bl_fifo_cfg = 0x35c,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg0 = {
.scratch_reg = 0x90,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg1 = {
.scratch_reg = 0x94,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg2 = {
.scratch_reg = 0x98,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg3 = {
.scratch_reg = 0x9c,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg4 = {
.scratch_reg = 0xa0,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg5 = {
.scratch_reg = 0xa4,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg6 = {
.scratch_reg = 0xa8,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg7 = {
.scratch_reg = 0xac,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg8 = {
.scratch_reg = 0xb0,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg9 = {
.scratch_reg = 0xb4,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg10 = {
.scratch_reg = 0xb8,
};
static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg11 = {
.scratch_reg = 0xbc,
};
static struct cam_cdm_perf_mon_regs cdm_2_2_perf_mon0 = {
.perf_mon_ctrl = 0x110,
.perf_mon_0 = 0x114,
.perf_mon_1 = 0x118,
.perf_mon_2 = 0x11c,
};
static struct cam_cdm_perf_mon_regs cdm_2_2_perf_mon1 = {
.perf_mon_ctrl = 0x120,
.perf_mon_0 = 0x124,
.perf_mon_1 = 0x128,
.perf_mon_2 = 0x12c,
};
static struct cam_cdm_comp_wait_status cdm_2_2_comp_wait_status0 = {
.comp_wait_status = 0x88,
};
static struct cam_cdm_comp_wait_status cdm_2_2_comp_wait_status1 = {
.comp_wait_status = 0x8c,
};
static struct cam_cdm_icl_data_regs cdm_2_2_icl_data = {
.icl_last_data_0 = 0x1c0,
.icl_last_data_1 = 0x1c4,
.icl_last_data_2 = 0x1c8,
.icl_inv_data = 0x1cc,
};
static struct cam_cdm_icl_misc_regs cdm_2_2_icl_misc = {
.icl_inv_bl_addr = 0x1d0,
.icl_status = 0x1d8,
};
static struct cam_cdm_icl_regs cdm_2_2_icl = {
.data_regs = &cdm_2_2_icl_data,
.misc_regs = &cdm_2_2_icl_misc,
};
static struct cam_cdm_common_regs cdm_hw_2_2_cmn_reg_offset = {
.cdm_hw_version = 0x0,
.cam_version = NULL,
.rst_cmd = 0x10,
.cgc_cfg = 0x14,
.core_cfg = 0x18,
.core_en = 0x1c,
.fe_cfg = 0x20,
.cdm_status = 0x28,
.irq_context_status = 0x2c,
.bl_fifo_rb = 0x60,
.bl_fifo_base_rb = 0x64,
.bl_fifo_len_rb = 0x68,
.usr_data = 0x80,
.wait_status = 0x84,
.last_ahb_addr = 0xd0,
.last_ahb_data = 0xd4,
.core_debug = 0xd8,
.last_ahb_err_addr = 0xe0,
.last_ahb_err_data = 0xe4,
.current_bl_base = 0xe8,
.current_bl_len = 0xec,
.current_used_ahb_base = 0xf0,
.debug_status = 0xf4,
.bus_misr_cfg0 = 0x100,
.bus_misr_cfg1 = 0x104,
.bus_misr_rd_val = 0x108,
.pending_req = {
&cdm_hw_2_2_bl_pending_req0,
&cdm_hw_2_2_bl_pending_req1,
},
.comp_wait = {
&cdm_2_2_comp_wait_status0,
&cdm_2_2_comp_wait_status1,
},
.perf_mon = {
&cdm_2_2_perf_mon0,
&cdm_2_2_perf_mon1,
},
.scratch = {
&cdm_2_2_scratch_reg0,
&cdm_2_2_scratch_reg1,
&cdm_2_2_scratch_reg2,
&cdm_2_2_scratch_reg3,
&cdm_2_2_scratch_reg4,
&cdm_2_2_scratch_reg5,
&cdm_2_2_scratch_reg6,
&cdm_2_2_scratch_reg7,
&cdm_2_2_scratch_reg8,
&cdm_2_2_scratch_reg9,
&cdm_2_2_scratch_reg10,
&cdm_2_2_scratch_reg11,
},
.perf_reg = NULL,
.icl_reg = &cdm_2_2_icl,
.spare = 0x3fc,
.priority_group_bit_offset = 20,
};
static struct cam_cdm_common_reg_data cdm_hw_2_2_cmn_reg_data = {
.num_bl_fifo = 0x4,
.num_bl_fifo_irq = 0x4,
.num_bl_pending_req_reg = 0x2,
.num_scratch_reg = 0xc,
};
struct cam_cdm_hw_reg_offset cam_cdm_2_2_reg_offset = {
.cmn_reg = &cdm_hw_2_2_cmn_reg_offset,
.bl_fifo_reg = {
&cdm_hw_2_2_bl_fifo0,
&cdm_hw_2_2_bl_fifo1,
&cdm_hw_2_2_bl_fifo2,
&cdm_hw_2_2_bl_fifo3,
},
.irq_reg = {
&cdm_hw_2_2_irq0,
&cdm_hw_2_2_irq1,
&cdm_hw_2_2_irq2,
&cdm_hw_2_2_irq3,
},
.reg_data = &cdm_hw_2_2_cmn_reg_data,
};

830
qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_intf.c Normal file
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@ -0,0 +1,830 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/kernel.h>
#include "cam_cdm_intf_api.h"
#include "cam_cdm.h"
#include "cam_cdm_virtual.h"
#include "cam_soc_util.h"
#include "cam_cdm_soc.h"
#include "cam_cdm_core_common.h"
#include "camera_main.h"
static struct cam_cdm_intf_mgr cdm_mgr;
static DEFINE_MUTEX(cam_cdm_mgr_lock);
static const struct of_device_id msm_cam_cdm_intf_dt_match[] = {
{ .compatible = "qcom,cam-cdm-intf", },
{}
};
static int get_cdm_mgr_refcount(void)
{
int rc = 0;
mutex_lock(&cam_cdm_mgr_lock);
if (cdm_mgr.probe_done == false) {
CAM_ERR(CAM_CDM, "CDM intf mgr not probed yet");
rc = -EPERM;
} else {
CAM_DBG(CAM_CDM, "CDM intf mgr get refcount=%d",
cdm_mgr.refcount);
cdm_mgr.refcount++;
}
mutex_unlock(&cam_cdm_mgr_lock);
return rc;
}
static void put_cdm_mgr_refcount(void)
{
mutex_lock(&cam_cdm_mgr_lock);
if (cdm_mgr.probe_done == false) {
CAM_ERR(CAM_CDM, "CDM intf mgr not probed yet");
} else {
CAM_DBG(CAM_CDM, "CDM intf mgr put refcount=%d",
cdm_mgr.refcount);
if (cdm_mgr.refcount > 0) {
cdm_mgr.refcount--;
} else {
CAM_ERR(CAM_CDM, "Refcount put when zero");
WARN_ON(1);
}
}
mutex_unlock(&cam_cdm_mgr_lock);
}
static int get_cdm_iommu_handle(struct cam_iommu_handle *cdm_handles,
uint32_t hw_idx)
{
int rc = -EPERM;
struct cam_hw_intf *hw = cdm_mgr.nodes[hw_idx].device;
if (hw->hw_ops.get_hw_caps) {
rc = hw->hw_ops.get_hw_caps(hw->hw_priv, cdm_handles,
sizeof(struct cam_iommu_handle));
}
return rc;
}
static int get_cdm_index_by_id(char *identifier,
uint32_t cell_index, uint32_t *hw_index)
{
int rc = -EPERM, i, j;
char client_name[128], name_index[160];
snprintf(client_name, sizeof(client_name), "%s", identifier);
snprintf(name_index, sizeof(name_index), "%s%d",
identifier, cell_index);
CAM_DBG(CAM_CDM,
"Looking for HW id of =%s or %s and index=%d cdm_count %d",
identifier, name_index, cell_index, cdm_mgr.cdm_count);
mutex_lock(&cam_cdm_mgr_lock);
for (i = 0; i < cdm_mgr.cdm_count; i++) {
mutex_lock(&cdm_mgr.nodes[i].lock);
CAM_DBG(CAM_CDM, "dt_num_supported_clients=%d",
cdm_mgr.nodes[i].data->dt_num_supported_clients);
for (j = 0; j <
cdm_mgr.nodes[i].data->dt_num_supported_clients; j++) {
CAM_DBG(CAM_CDM, "client name:%s dev Index: %d",
cdm_mgr.nodes[i].data->dt_cdm_client_name[j],
i);
if (!strcmp(
cdm_mgr.nodes[i].data->dt_cdm_client_name[j],
client_name) || !strcmp(
cdm_mgr.nodes[i].data->dt_cdm_client_name[j],
name_index)) {
rc = 0;
*hw_index = i;
break;
}
}
mutex_unlock(&cdm_mgr.nodes[i].lock);
if (rc == 0)
break;
}
mutex_unlock(&cam_cdm_mgr_lock);
return rc;
}
int cam_cdm_get_iommu_handle(char *identifier,
struct cam_iommu_handle *cdm_handles)
{
int i, j, rc = -EPERM;
if ((!identifier) || (!cdm_handles))
return -EINVAL;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
return rc;
}
CAM_DBG(CAM_CDM, "Looking for Iommu handle of %s", identifier);
for (i = 0; i < cdm_mgr.cdm_count; i++) {
mutex_lock(&cdm_mgr.nodes[i].lock);
if (!cdm_mgr.nodes[i].data) {
mutex_unlock(&cdm_mgr.nodes[i].lock);
continue;
}
CAM_DBG(CAM_CDM, "dt_num_supported_clients=%d",
cdm_mgr.nodes[i].data->dt_num_supported_clients);
for (j = 0; j <
cdm_mgr.nodes[i].data->dt_num_supported_clients;
j++) {
CAM_DBG(CAM_CDM, "client name:%s dev Index: %d",
cdm_mgr.nodes[i].data->dt_cdm_client_name[j],
i);
if (!strcmp(
cdm_mgr.nodes[i].data->dt_cdm_client_name[j],
identifier)) {
rc = get_cdm_iommu_handle(cdm_handles, i);
break;
}
}
mutex_unlock(&cdm_mgr.nodes[i].lock);
if (rc == 0)
break;
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_get_iommu_handle);
int cam_cdm_acquire(struct cam_cdm_acquire_data *data)
{
int rc = -EPERM;
struct cam_hw_intf *hw;
struct cam_hw_info *cdm_hw;
struct cam_cdm *core = NULL;
uint32_t hw_index = 0;
if ((!data) || (!data->base_array_cnt))
return -EINVAL;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
return rc;
}
if (data->id > CAM_CDM_HW_ANY) {
CAM_ERR(CAM_CDM,
"only CAM_CDM_VIRTUAL/CAM_CDM_HW_ANY is supported");
rc = -EPERM;
goto end;
}
rc = get_cdm_index_by_id(data->identifier, data->cell_index,
&hw_index);
if ((rc < 0) && (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM)) {
CAM_ERR(CAM_CDM, "Failed to identify associated hw id");
goto end;
} else {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd) {
cdm_hw = hw->hw_priv;
core = (struct cam_cdm *)cdm_hw->core_info;
data->id = core->id;
data->hw_idx = hw->hw_idx;
CAM_DBG(CAM_CDM,
"Device = %s, hw_index = %d, CDM id = %d",
data->identifier, hw_index, data->id);
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_CMD_ACQUIRE, data,
sizeof(struct cam_cdm_acquire_data));
if (rc < 0) {
CAM_ERR(CAM_CDM, "CDM hw acquire failed");
goto end;
}
} else {
CAM_ERR(CAM_CDM, "idx %d doesn't have acquire ops",
hw_index);
rc = -EPERM;
}
}
end:
if (rc < 0) {
CAM_ERR(CAM_CDM, "CDM acquire failed for id=%d name=%s, idx=%d",
data->id, data->identifier, data->cell_index);
put_cdm_mgr_refcount();
}
return rc;
}
EXPORT_SYMBOL(cam_cdm_acquire);
struct cam_cdm_utils_ops *cam_cdm_publish_ops(void)
{
struct cam_hw_version cdm_version;
cdm_version.major = 1;
cdm_version.minor = 0;
cdm_version.incr = 0;
cdm_version.reserved = 0;
return cam_cdm_get_ops(0, &cdm_version, true);
}
EXPORT_SYMBOL(cam_cdm_publish_ops);
int cam_cdm_release(uint32_t handle)
{
uint32_t hw_index;
int rc = -EPERM;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd) {
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_CMD_RELEASE, &handle,
sizeof(handle));
if (rc < 0)
CAM_ERR(CAM_CDM,
"hw release failed for handle=%x",
handle);
} else
CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops",
hw_index);
}
put_cdm_mgr_refcount();
if (rc == 0)
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_release);
int cam_cdm_submit_bls(uint32_t handle, struct cam_cdm_bl_request *data)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (!data)
return rc;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
struct cam_cdm_hw_intf_cmd_submit_bl req;
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd) {
req.data = data;
req.handle = handle;
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_CMD_SUBMIT_BL, &req,
sizeof(struct cam_cdm_hw_intf_cmd_submit_bl));
if (rc < 0)
CAM_ERR(CAM_CDM,
"hw submit bl failed for handle=%x",
handle);
} else {
CAM_ERR(CAM_CDM, "hw idx %d doesn't have submit ops",
hw_index);
}
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_submit_bls);
int cam_cdm_stream_on(uint32_t handle)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.start) {
rc = hw->hw_ops.start(hw->hw_priv, &handle,
sizeof(uint32_t));
if (rc < 0)
CAM_ERR(CAM_CDM,
"hw start failed handle=%x",
handle);
} else {
CAM_ERR(CAM_CDM,
"hw idx %d doesn't have start ops",
hw_index);
}
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_stream_on);
int cam_cdm_stream_off(uint32_t handle)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.stop) {
rc = hw->hw_ops.stop(hw->hw_priv, &handle,
sizeof(uint32_t));
if (rc < 0)
CAM_ERR(CAM_CDM, "hw stop failed handle=%x",
handle);
} else {
CAM_ERR(CAM_CDM, "hw idx %d doesn't have stop ops",
hw_index);
}
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_stream_off);
int cam_cdm_reset_hw(uint32_t handle)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd) {
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_CMD_RESET_HW, &handle,
sizeof(handle));
if (rc < 0)
CAM_ERR(CAM_CDM,
"CDM hw release failed for handle=%x",
handle);
} else {
CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops",
hw_index);
}
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_reset_hw);
int cam_cdm_flush_hw(uint32_t handle)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd) {
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_CMD_FLUSH_HW, &handle,
sizeof(handle));
if (rc < 0)
CAM_ERR(CAM_CDM,
"CDM hw release failed for handle=%x",
handle);
} else {
CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops",
hw_index);
}
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_flush_hw);
int cam_cdm_handle_error(uint32_t handle)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd) {
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_CMD_HANDLE_ERROR,
&handle,
sizeof(handle));
if (rc < 0)
CAM_ERR(CAM_CDM,
"CDM hw release failed for handle=%x",
handle);
} else {
CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops",
hw_index);
}
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_handle_error);
int cam_cdm_detect_hang_error(uint32_t handle)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd)
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_CMD_HANG_DETECT,
&handle,
sizeof(handle));
}
put_cdm_mgr_refcount();
return rc;
}
EXPORT_SYMBOL(cam_cdm_detect_hang_error);
int cam_cdm_dump_debug_registers(uint32_t handle)
{
uint32_t hw_index;
int rc = -EINVAL;
struct cam_hw_intf *hw;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
hw_index = CAM_CDM_GET_HW_IDX(handle);
if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) {
hw = cdm_mgr.nodes[hw_index].device;
if (hw && hw->hw_ops.process_cmd)
rc = hw->hw_ops.process_cmd(hw->hw_priv,
CAM_CDM_HW_INTF_DUMP_DBG_REGS,
&handle,
sizeof(handle));
}
put_cdm_mgr_refcount();
return rc;
}
int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw,
struct cam_cdm_private_dt_data *data, enum cam_cdm_type type,
uint32_t *index)
{
int rc = -EINVAL;
if ((!hw) || (!data) || (!index))
return rc;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
return rc;
}
mutex_lock(&cam_cdm_mgr_lock);
if ((type == CAM_VIRTUAL_CDM) &&
(!cdm_mgr.nodes[CAM_SW_CDM_INDEX].device)) {
mutex_lock(&cdm_mgr.nodes[CAM_SW_CDM_INDEX].lock);
cdm_mgr.nodes[CAM_SW_CDM_INDEX].device = hw;
cdm_mgr.nodes[CAM_SW_CDM_INDEX].data = data;
*index = cdm_mgr.cdm_count;
mutex_unlock(&cdm_mgr.nodes[CAM_SW_CDM_INDEX].lock);
cdm_mgr.cdm_count++;
rc = 0;
} else if ((type == CAM_HW_CDM) && (cdm_mgr.cdm_count > 0)) {
mutex_lock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock);
cdm_mgr.nodes[cdm_mgr.cdm_count].device = hw;
cdm_mgr.nodes[cdm_mgr.cdm_count].data = data;
*index = cdm_mgr.cdm_count;
mutex_unlock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock);
cdm_mgr.cdm_count++;
rc = 0;
} else {
CAM_ERR(CAM_CDM, "CDM registration failed type=%d count=%d",
type, cdm_mgr.cdm_count);
}
mutex_unlock(&cam_cdm_mgr_lock);
put_cdm_mgr_refcount();
return rc;
}
int cam_cdm_intf_deregister_hw_cdm(struct cam_hw_intf *hw,
struct cam_cdm_private_dt_data *data, enum cam_cdm_type type,
uint32_t index)
{
int rc = -EINVAL;
if ((!hw) || (!data))
return rc;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
rc = -EPERM;
return rc;
}
mutex_lock(&cam_cdm_mgr_lock);
if ((type == CAM_VIRTUAL_CDM) &&
(hw == cdm_mgr.nodes[CAM_SW_CDM_INDEX].device) &&
(index == CAM_SW_CDM_INDEX)) {
mutex_lock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock);
cdm_mgr.nodes[CAM_SW_CDM_INDEX].device = NULL;
cdm_mgr.nodes[CAM_SW_CDM_INDEX].data = NULL;
mutex_unlock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock);
rc = 0;
} else if ((type == CAM_HW_CDM) &&
(hw == cdm_mgr.nodes[index].device)) {
mutex_lock(&cdm_mgr.nodes[index].lock);
cdm_mgr.nodes[index].device = NULL;
cdm_mgr.nodes[index].data = NULL;
mutex_unlock(&cdm_mgr.nodes[index].lock);
cdm_mgr.cdm_count--;
rc = 0;
} else {
CAM_ERR(CAM_CDM, "CDM Deregistration failed type=%d index=%d",
type, index);
}
mutex_unlock(&cam_cdm_mgr_lock);
put_cdm_mgr_refcount();
return rc;
}
static int cam_cdm_set_irq_line_test(void *data, u64 val)
{
int i, rc = 0;
struct cam_hw_intf *hw_intf;
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
return rc;
}
mutex_lock(&cam_cdm_mgr_lock);
for (i = 0 ; i < cdm_mgr.cdm_count; i++) {
if (!cdm_mgr.nodes[i].device || !cdm_mgr.nodes[i].data) {
CAM_ERR(CAM_CDM, "invalid node present in index=%d", i);
continue;
}
hw_intf = cdm_mgr.nodes[i].device;
if (hw_intf->hw_ops.test_irq_line) {
CAM_DBG(CAM_CDM, "Testing irq line for CDM at index %d", i);
rc = hw_intf->hw_ops.test_irq_line(hw_intf->hw_priv);
if (rc)
CAM_ERR(CAM_CDM,
"[%d] : CDM%d type %d - irq line test failed rc %d",
i, hw_intf->hw_idx, hw_intf->hw_type, rc);
else
CAM_INFO(CAM_CDM,
"[%d] : CDM%d type %d - irq line test passed",
i, hw_intf->hw_idx, hw_intf->hw_type);
} else {
CAM_WARN(CAM_CDM, "test irq line interface not present for cdm at index %d",
i);
}
}
mutex_unlock(&cam_cdm_mgr_lock);
put_cdm_mgr_refcount();
return rc;
}
static int cam_cdm_get_irq_line_test(void *data, u64 *val)
{
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(cam_cdm_irq_line_test, cam_cdm_get_irq_line_test,
cam_cdm_set_irq_line_test, "%16llu");
int cam_cdm_debugfs_init(struct cam_cdm_intf_mgr *mgr)
{
struct dentry *dbgfileptr = NULL;
int rc;
if (!cam_debugfs_available())
return 0;
rc = cam_debugfs_create_subdir("cdm", &dbgfileptr);
if (rc) {
CAM_ERR(CAM_CDM, "DebugFS could not create directory!");
return rc;
}
mgr->dentry = dbgfileptr;
debugfs_create_file("test_irq_line", 0644,
mgr->dentry, NULL, &cam_cdm_irq_line_test);
return 0;
}
static int cam_cdm_intf_component_bind(struct device *dev,
struct device *master_dev, void *data)
{
int i, rc;
struct platform_device *pdev = to_platform_device(dev);
rc = cam_cdm_intf_mgr_soc_get_dt_properties(pdev, &cdm_mgr);
if (rc) {
CAM_ERR(CAM_CDM, "Failed to get dt properties");
return rc;
}
mutex_lock(&cam_cdm_mgr_lock);
for (i = 0 ; i < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM; i++) {
mutex_init(&cdm_mgr.nodes[i].lock);
cdm_mgr.nodes[i].device = NULL;
cdm_mgr.nodes[i].data = NULL;
cdm_mgr.nodes[i].refcount = 0;
}
cdm_mgr.probe_done = true;
cdm_mgr.refcount = 0;
mutex_unlock(&cam_cdm_mgr_lock);
rc = cam_virtual_cdm_probe(pdev);
if (rc) {
mutex_lock(&cam_cdm_mgr_lock);
cdm_mgr.probe_done = false;
for (i = 0 ; i < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM; i++) {
if (cdm_mgr.nodes[i].device || cdm_mgr.nodes[i].data ||
(cdm_mgr.nodes[i].refcount != 0))
CAM_ERR(CAM_CDM,
"Valid node present in index=%d", i);
mutex_destroy(&cdm_mgr.nodes[i].lock);
cdm_mgr.nodes[i].device = NULL;
cdm_mgr.nodes[i].data = NULL;
cdm_mgr.nodes[i].refcount = 0;
}
mutex_unlock(&cam_cdm_mgr_lock);
}
cam_cdm_debugfs_init(&cdm_mgr);
CAM_DBG(CAM_CDM, "CDM Intf component bound successfully");
return rc;
}
static void cam_cdm_intf_component_unbind(struct device *dev,
struct device *master_dev, void *data)
{
int i;
struct platform_device *pdev = to_platform_device(dev);
if (get_cdm_mgr_refcount()) {
CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed");
return;
}
if (cam_virtual_cdm_remove(pdev)) {
CAM_ERR(CAM_CDM, "Virtual CDM remove failed");
return;
}
put_cdm_mgr_refcount();
mutex_lock(&cam_cdm_mgr_lock);
if (cdm_mgr.refcount != 0) {
CAM_ERR(CAM_CDM, "cdm manger refcount not zero %d",
cdm_mgr.refcount);
goto end;
}
for (i = 0 ; i < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM; i++) {
if (cdm_mgr.nodes[i].device || cdm_mgr.nodes[i].data ||
(cdm_mgr.nodes[i].refcount != 0)) {
CAM_ERR(CAM_CDM, "Valid node present in index=%d", i);
goto end;
}
mutex_lock(&cdm_mgr.nodes[i].lock);
cdm_mgr.nodes[i].device = NULL;
cdm_mgr.nodes[i].data = NULL;
cdm_mgr.nodes[i].refcount = 0;
mutex_unlock(&cdm_mgr.nodes[i].lock);
mutex_destroy(&cdm_mgr.nodes[i].lock);
}
cdm_mgr.probe_done = false;
end:
mutex_unlock(&cam_cdm_mgr_lock);
}
const static struct component_ops cam_cdm_intf_component_ops = {
.bind = cam_cdm_intf_component_bind,
.unbind = cam_cdm_intf_component_unbind,
};
static int cam_cdm_intf_probe(struct platform_device *pdev)
{
int rc = 0;
CAM_DBG(CAM_CDM, "Adding CDM INTF component");
rc = component_add(&pdev->dev, &cam_cdm_intf_component_ops);
if (rc)
CAM_ERR(CAM_CDM, "failed to add component rc: %d", rc);
return rc;
}
static int cam_cdm_intf_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &cam_cdm_intf_component_ops);
return 0;
}
struct platform_driver cam_cdm_intf_driver = {
.probe = cam_cdm_intf_probe,
.remove = cam_cdm_intf_remove,
.driver = {
.name = "msm_cam_cdm_intf",
.owner = THIS_MODULE,
.of_match_table = msm_cam_cdm_intf_dt_match,
.suppress_bind_attrs = true,
},
};
int cam_cdm_intf_init_module(void)
{
return platform_driver_register(&cam_cdm_intf_driver);
}
void cam_cdm_intf_exit_module(void)
{
platform_driver_unregister(&cam_cdm_intf_driver);
}
MODULE_DESCRIPTION("MSM Camera CDM Intf driver");
MODULE_LICENSE("GPL v2");

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CDM_API_H_
#define _CAM_CDM_API_H_
#include <media/cam_defs.h>
#include "cam_cdm_util.h"
#include "cam_soc_util.h"
#include "cam_packet_util.h"
#define CAM_CDM_BL_CMD_MAX 25
/* enum cam_cdm_id - Enum for possible CAM CDM hardwares */
enum cam_cdm_id {
CAM_CDM_VIRTUAL,
CAM_CDM_HW_ANY,
CAM_CDM_CPAS,
CAM_CDM_IFE,
CAM_CDM_TFE,
CAM_CDM_OPE,
CAM_CDM_IPE0,
CAM_CDM_IPE1,
CAM_CDM_BPS,
CAM_CDM_VFE,
CAM_CDM_RT,
CAM_CDM_MAX
};
/* enum cam_cdm_cb_status - Enum for possible CAM CDM callback */
enum cam_cdm_cb_status {
CAM_CDM_CB_STATUS_BL_SUCCESS,
CAM_CDM_CB_STATUS_INVALID_BL_CMD,
CAM_CDM_CB_STATUS_PAGEFAULT,
CAM_CDM_CB_STATUS_HW_RESET_ONGOING,
CAM_CDM_CB_STATUS_HW_RESET_DONE,
CAM_CDM_CB_STATUS_HW_FLUSH,
CAM_CDM_CB_STATUS_HW_RESUBMIT,
CAM_CDM_CB_STATUS_HW_ERROR,
CAM_CDM_CB_STATUS_UNKNOWN_ERROR,
};
/* enum cam_cdm_bl_cmd_addr_type - Enum for possible CDM bl cmd addr types */
enum cam_cdm_bl_cmd_addr_type {
CAM_CDM_BL_CMD_TYPE_MEM_HANDLE,
CAM_CDM_BL_CMD_TYPE_HW_IOVA,
CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA,
};
/* enum cam_cdm_bl_fifo - interface commands.*/
enum cam_cdm_bl_fifo_queue {
CAM_CDM_BL_FIFO_0,
CAM_CDM_BL_FIFO_1,
CAM_CDM_BL_FIFO_2,
CAM_CDM_BL_FIFO_3,
CAM_CDM_BL_FIFO_MAX,
};
/**
* struct cam_cdm_acquire_data - Cam CDM acquire data structure
*
* @identifier : Input identifier string which is the device label from dt
* like vfe, ife, jpeg etc
* @cell_index : Input integer identifier pointing to the cell index from dt
* of the device. This can be used to form a unique string
* with @identifier like vfe0, ife1, jpeg0 etc
* @id : ID of a specific or any CDM HW which needs to be acquired.
* @userdata : Input private data which will be returned as part
* of callback.
* @cam_cdm_callback : Input callback pointer for triggering the
* callbacks from CDM driver
* @handle : CDM Client handle
* @userdata : Private data given at the time of acquire
* @status : Callback status
* @cookie : Cookie if the callback is gen irq status or
* pf_args if it is page fault
* @base_array_cnt : Input number of ioremapped address pair pointing
* in base_array, needed only if selected cdm is a virtual.
* @base_array : Input pointer to ioremapped address pair arrary
* needed only if selected cdm is a virtual.
* @priority : Priority of the client.
* @cdm_version : CDM version is output while acquiring HW cdm and
* it is Input while acquiring virtual cdm.
* Currently fixing it to one version below
* acquire API.
* @ops : Output pointer updated by cdm driver to the CDM
* util ops for this HW version of CDM acquired.
* @handle : Output Unique handle generated for this acquire
* @hw_idx : The physical CDM acquired
*
*/
struct cam_cdm_acquire_data {
char identifier[128];
uint32_t cell_index;
enum cam_cdm_id id;
void *userdata;
void (*cam_cdm_callback)(uint32_t handle, void *userdata,
enum cam_cdm_cb_status status, void *cookie);
uint32_t base_array_cnt;
struct cam_soc_reg_map *base_array[CAM_SOC_MAX_BLOCK];
enum cam_cdm_bl_fifo_queue priority;
struct cam_hw_version cdm_version;
struct cam_cdm_utils_ops *ops;
uint32_t handle;
uint32_t hw_idx;
};
/**
* struct cam_cdm_bl_cmd - Cam CDM HW bl command
*
* @bl_addr : Union of all three type for CDM BL commands
* @mem_handle : Input mem handle of bl cmd
* @offset : Input offset of the actual bl cmd in the memory pointed
* by mem_handle
* @len : Input length of the BL command, Cannot be more than 1MB and
* this is will be validated with offset+size of the memory pointed
* by mem_handle
* @enable_debug_gen_irq : bool flag to submit extra gen_irq afteR bl_command
* @arbitrate : bool flag to arbitrate on submitted BL boundary
*/
struct cam_cdm_bl_cmd {
union {
int32_t mem_handle;
uint32_t *hw_iova;
uintptr_t kernel_iova;
} bl_addr;
uint32_t offset;
uint32_t len;
bool enable_debug_gen_irq;
bool arbitrate;
};
/**
* struct cam_cdm_bl_request - Cam CDM HW base & length (BL) request
*
* @flag : 1 for callback needed and 0 for no callback when this BL
* request is done
* @gen_irq_arb : enum for setting arbitration in gen_irq
* @userdata :Input private data which will be returned as part
* of callback if request for this bl request in flags.
* @type : type of the submitted bl cmd address.
* @cmd_arrary_count : Input number of BL commands to be submitted to CDM
* @cookie : Cookie if the callback is gen irq status
* @avail_buff_size: Available buffer size in bytes
* @bl_cmd_array : Input payload holding the BL cmd's arrary
* to be sumbitted.
*
*/
struct cam_cdm_bl_request {
bool flag;
bool gen_irq_arb;
void *userdata;
enum cam_cdm_bl_cmd_addr_type type;
uint32_t cmd_arrary_count;
struct cam_kmd_buf_info *genirq_buff;
uint64_t cookie;
struct cam_cdm_bl_cmd cmd[1];
};
/**
* struct cam_cdm_bl_data - last submiited CDM BL data
*
* @mem_handle : Input mem handle of bl cmd
* @hw_addr : Hw address of submitted Bl command
* @offset : Input offset of the actual bl cmd in the memory pointed
* by mem_handle
* @len : length of submitted Bl command to CDM.
* @input_len : Input length of the BL command, Cannot be more than 1MB and
* this is will be validated with offset+size of the memory pointed
* by mem_handle
* @type : CDM bl cmd addr types.
*/
struct cam_cdm_bl_data {
int32_t mem_handle;
dma_addr_t hw_addr;
uint32_t offset;
size_t len;
uint32_t input_len;
enum cam_cdm_bl_cmd_addr_type type;
};
/**
* struct cam_cdm_bl_info
*
* @bl_count : No. of Bl commands submiited to CDM.
* @cmd : payload holding the BL cmd's arrary
* that is sumbitted.
*
*/
struct cam_cdm_bl_info {
int32_t bl_count;
struct cam_cdm_bl_data cmd[CAM_CDM_BL_CMD_MAX];
};
/**
* @brief : API to get the CDM capabilities for a camera device type
*
* @identifier : Input pointer to a string which is the device label from dt
* like vfe, ife, jpeg etc, We do not need cell index
* assuming all devices of a single type maps to one SMMU
* client
* @cdm_handles : Input iommu handle memory pointer to update handles
*
* @return 0 on success
*/
int cam_cdm_get_iommu_handle(char *identifier,
struct cam_iommu_handle *cdm_handles);
/**
* @brief : API to acquire a CDM
*
* @data : Input data for the CDM to be acquired
*
* @return 0 on success
*/
int cam_cdm_acquire(struct cam_cdm_acquire_data *data);
/**
* @brief : API to release a previously acquired CDM
*
* @handle : Input handle for the CDM to be released
*
* @return 0 on success
*/
int cam_cdm_release(uint32_t handle);
/**
* @brief : API to submit the base & length (BL's) for acquired CDM
*
* @handle : Input cdm handle to which the BL's needs to be sumbitted.
* @data : Input pointer to the BL's to be sumbitted
*
* @return 0 on success
*/
int cam_cdm_submit_bls(uint32_t handle, struct cam_cdm_bl_request *data);
/**
* @brief : API to stream ON a previously acquired CDM,
* during this we turn on/off clocks/power based on active clients.
*
* @handle : Input handle for the CDM to be released
*
* @return 0 on success
*/
int cam_cdm_stream_on(uint32_t handle);
/**
* @brief : API to stream OFF a previously acquired CDM,
* during this we turn on/off clocks/power based on active clients.
*
* @handle : Input handle for the CDM to be released
*
* @return 0 on success
*/
int cam_cdm_stream_off(uint32_t handle);
/**
* @brief : API to reset previously acquired CDM,
* this should be only performed only if the CDM is private.
*
* @handle : Input handle of the CDM to reset
*
* @return 0 on success
*/
int cam_cdm_reset_hw(uint32_t handle);
/**
* @brief : API to publish CDM ops to HW blocks like IFE
*
* @return : CDM operations
*
*/
struct cam_cdm_utils_ops *cam_cdm_publish_ops(void);
/**
* @brief : API to register CDM hw to platform framework.
* @return struct platform_device pointer on on success, or ERR_PTR() on error.
*/
int cam_hw_cdm_init_module(void);
/**
* @brief : API to register CDM interface to platform framework.
* @return struct platform_device pointer on on success, or ERR_PTR() on error.
*/
int cam_cdm_intf_init_module(void);
/**
* @brief : API to remove CDM interface from platform framework.
*/
void cam_cdm_intf_exit_module(void);
/**
* @brief : API to remove CDM hw from platform framework.
*/
void cam_hw_cdm_exit_module(void);
/**
* @brief : API to flush previously acquired CDM,
* this should be only performed only if the CDM is private.
*
* @handle : Input handle of the CDM to reset
*
* @return 0 on success
*/
int cam_cdm_flush_hw(uint32_t handle);
/**
* @brief : API to detect culprit bl_tag in previously acquired CDM,
* this should be only performed only if the CDM is private.
*
* @handle : Input handle of the CDM to reset
*
* @return 0 on success
*/
int cam_cdm_handle_error(uint32_t handle);
/**
* @brief : API get CDM ops
*
* @return : CDM operations
*
*/
struct cam_cdm_utils_ops *cam_cdm_publish_ops(void);
/**
* @brief : API to detect hang in previously acquired CDM,
* this should be only performed only if the CDM is private.
*
* @handle : Input handle of the CDM to detect hang
*
* @return 0 on success
*/
int cam_cdm_detect_hang_error(uint32_t handle);
/**
* @brief : API to dump the CDM Debug registers
*
* @handle : Input handle of the CDM to dump the registers
*
* @return 0 on success
*/
int cam_cdm_dump_debug_registers(uint32_t handle);
#endif /* _CAM_CDM_API_H_ */

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/kernel.h>
#include "cam_soc_util.h"
#include "cam_smmu_api.h"
#include "cam_cdm.h"
#include "cam_soc_util.h"
#include "cam_io_util.h"
#include "cam_cdm_soc.h"
#define CAM_CDM_OFFSET_FROM_REG(x, y) ((x)->offsets[y].offset)
#define CAM_CDM_ATTR_FROM_REG(x, y) ((x)->offsets[y].attribute)
bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw,
uint32_t reg, uint32_t *value)
{
void __iomem *reg_addr;
void __iomem *base =
cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base;
resource_size_t mem_len =
cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size;
CAM_DBG(CAM_CDM, "E: b=%pK blen=%d off=%x", (void __iomem *)base,
(int)mem_len, reg);
reg_addr = (base + reg);
if (reg_addr > (base + mem_len)) {
CAM_ERR_RATE_LIMIT(CAM_CDM,
"Invalid mapped region %d", reg);
goto permission_error;
}
*value = cam_io_r_mb(reg_addr);
CAM_DBG(CAM_CDM, "X b=%pK off=%x val=%x",
(void __iomem *)base, reg,
*value);
return false;
permission_error:
*value = 0;
return true;
}
bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw,
uint32_t reg, uint32_t value)
{
void __iomem *reg_addr;
void __iomem *base =
cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base;
resource_size_t mem_len =
cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size;
CAM_DBG(CAM_CDM, "E: b=%pK off=%x val=%x", (void __iomem *)base,
reg, value);
reg_addr = (base + reg);
if (reg_addr > (base + mem_len)) {
CAM_ERR_RATE_LIMIT(CAM_CDM,
"Accessing invalid region:%d\n",
reg);
goto permission_error;
}
cam_io_w_mb(value, reg_addr);
return false;
permission_error:
return true;
}
int cam_cdm_soc_load_dt_private(struct platform_device *pdev,
struct cam_cdm_private_dt_data *cdm_pvt_data)
{
int i, rc = -EINVAL, num_fifo_entries = 0, num_clients = 0;
num_clients = of_property_count_strings(
pdev->dev.of_node, "cdm-client-names");
if ((num_clients <= 0) ||
(num_clients > CAM_PER_CDM_MAX_REGISTERED_CLIENTS)) {
CAM_ERR(CAM_CDM, "Invalid count of client names count=%d",
num_clients);
rc = -EINVAL;
goto end;
}
cdm_pvt_data->dt_num_supported_clients = (uint32_t)num_clients;
CAM_DBG(CAM_CDM, "Num supported cdm_client = %u",
cdm_pvt_data->dt_num_supported_clients);
cdm_pvt_data->dt_cdm_shared = true;
for (i = 0; i < cdm_pvt_data->dt_num_supported_clients; i++) {
rc = of_property_read_string_index(pdev->dev.of_node,
"cdm-client-names", i,
&(cdm_pvt_data->dt_cdm_client_name[i]));
CAM_DBG(CAM_CDM, "cdm-client-names[%d] = %s", i,
cdm_pvt_data->dt_cdm_client_name[i]);
if (rc < 0) {
CAM_ERR(CAM_CDM,
"Reading cdm-client-names failed for client: %d",
i);
goto end;
}
}
cdm_pvt_data->is_single_ctx_cdm =
of_property_read_bool(pdev->dev.of_node, "single-context-cdm");
rc = of_property_read_u32(pdev->dev.of_node, "cam_hw_pid", &cdm_pvt_data->pid);
if (rc)
cdm_pvt_data->pid = -1;
rc = of_property_read_u32(pdev->dev.of_node, "cam-hw-mid", &cdm_pvt_data->mid);
if (rc)
cdm_pvt_data->mid = -1;
rc = of_property_read_u8(pdev->dev.of_node, "cdm-priority-group",
&cdm_pvt_data->priority_group);
if (rc < 0) {
cdm_pvt_data->priority_group = 0;
rc = 0;
}
cdm_pvt_data->config_fifo = of_property_read_bool(pdev->dev.of_node,
"config-fifo");
if (cdm_pvt_data->config_fifo) {
num_fifo_entries = of_property_count_u32_elems(
pdev->dev.of_node,
"fifo-depths");
if (num_fifo_entries != CAM_CDM_NUM_BL_FIFO) {
CAM_ERR(CAM_CDM,
"Wrong number of configurable FIFOs %d",
num_fifo_entries);
rc = -EINVAL;
goto end;
}
for (i = 0; i < num_fifo_entries; i++) {
rc = of_property_read_u32_index(pdev->dev.of_node,
"fifo-depths", i, &cdm_pvt_data->fifo_depth[i]);
if (rc < 0) {
CAM_ERR(CAM_CDM,
"Unable to read fifo-depth rc %d",
rc);
goto end;
}
CAM_DBG(CAM_CDM, "FIFO%d depth is %d",
i, cdm_pvt_data->fifo_depth[i]);
}
} else {
for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) {
cdm_pvt_data->fifo_depth[i] =
CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT;
CAM_DBG(CAM_CDM, "FIFO%d depth is %d",
i, cdm_pvt_data->fifo_depth[i]);
}
}
end:
return rc;
}
int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw,
const struct of_device_id *table)
{
int rc;
struct cam_hw_soc_info *soc_ptr;
const struct of_device_id *id;
struct cam_cdm *cdm_core = NULL;
if (!cdm_hw || (cdm_hw->soc_info.soc_private)
|| !(cdm_hw->soc_info.pdev))
return -EINVAL;
cdm_core = cdm_hw->core_info;
soc_ptr = &cdm_hw->soc_info;
rc = cam_soc_util_get_dt_properties(soc_ptr);
if (rc != 0) {
CAM_ERR(CAM_CDM, "Failed to retrieve the CDM dt properties");
goto end;
}
soc_ptr->soc_private = kzalloc(
sizeof(struct cam_cdm_private_dt_data),
GFP_KERNEL);
if (!soc_ptr->soc_private)
return -ENOMEM;
rc = cam_cdm_soc_load_dt_private(soc_ptr->pdev,
soc_ptr->soc_private);
if (rc != 0) {
CAM_ERR(CAM_CDM, "Failed to load CDM dt private data");
goto error;
}
id = of_match_node(table, soc_ptr->pdev->dev.of_node);
if ((!id) || !(id->data)) {
CAM_ERR(CAM_CDM, "Failed to retrieve the CDM id table");
goto error;
}
cdm_core->offsets =
(struct cam_cdm_hw_reg_offset *)id->data;
CAM_DBG(CAM_CDM, "name %s", cdm_core->name);
snprintf(cdm_core->name, sizeof(cdm_core->name), "%s%d",
id->compatible, soc_ptr->index);
CAM_DBG(CAM_CDM, "name %s", cdm_core->name);
goto end;
error:
rc = -EINVAL;
kfree(soc_ptr->soc_private);
soc_ptr->soc_private = NULL;
end:
return rc;
}
int cam_cdm_intf_mgr_soc_get_dt_properties(
struct platform_device *pdev, struct cam_cdm_intf_mgr *mgr)
{
int rc;
rc = of_property_read_u32(pdev->dev.of_node,
"num-hw-cdm", &mgr->dt_supported_hw_cdm);
CAM_DBG(CAM_CDM, "Number of HW cdm supported =%d",
mgr->dt_supported_hw_cdm);
return rc;
}

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_soc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CDM_SOC_H_
#define _CAM_CDM_SOC_H_
#define CAM_HW_CDM_CPAS_0_NAME "qcom,cam170-cpas-cdm0"
#define CAM_HW_CDM_CPAS_NAME_1_0 "qcom,cam-cpas-cdm1_0"
#define CAM_HW_CDM_CPAS_NAME_1_1 "qcom,cam-cpas-cdm1_1"
#define CAM_HW_CDM_CPAS_NAME_1_2 "qcom,cam-cpas-cdm1_2"
#define CAM_HW_CDM_IFE_NAME_1_2 "qcom,cam-ife-cdm1_2"
#define CAM_HW_CDM_CPAS_NAME_2_0 "qcom,cam-cpas-cdm2_0"
#define CAM_HW_CDM_OPE_NAME_2_0 "qcom,cam-ope-cdm2_0"
#define CAM_HW_CDM_CPAS_NAME_2_1 "qcom,cam-cpas-cdm2_1"
#define CAM_HW_CDM_RT_NAME_2_1 "qcom,cam-rt-cdm2_1"
#define CAM_HW_CDM_OPE_NAME_2_1 "qcom,cam-ope-cdm2_1"
#define CAM_HW_CDM_RT_NAME_2_2 "qcom,cam-rt-cdm2_2"
int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw,
const struct of_device_id *table);
bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw,
uint32_t reg, uint32_t *value);
bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw,
uint32_t reg, uint32_t value);
int cam_cdm_intf_mgr_soc_get_dt_properties(
struct platform_device *pdev,
struct cam_cdm_intf_mgr *mgr);
int cam_cdm_soc_load_dt_private(struct platform_device *pdev,
struct cam_cdm_private_dt_data *ptr);
#endif /* _CAM_CDM_SOC_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_util.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CDM_UTIL_H_
#define _CAM_CDM_UTIL_H_
/* Max len for tag name for header while dumping cmd buffer*/
#define CAM_CDM_CMD_TAG_MAX_LEN 128
#define CAM_CDM_COMMAND_OFFSET 24
#include <linux/types.h>
enum cam_cdm_command {
CAM_CDM_CMD_UNUSED = 0x0,
CAM_CDM_CMD_DMI = 0x1,
CAM_CDM_CMD_NOT_DEFINED = 0x2,
CAM_CDM_CMD_REG_CONT = 0x3,
CAM_CDM_CMD_REG_RANDOM = 0x4,
CAM_CDM_CMD_BUFF_INDIRECT = 0x5,
CAM_CDM_CMD_GEN_IRQ = 0x6,
CAM_CDM_CMD_WAIT_EVENT = 0x7,
CAM_CDM_CMD_CHANGE_BASE = 0x8,
CAM_CDM_CMD_PERF_CTRL = 0x9,
CAM_CDM_CMD_DMI_32 = 0xa,
CAM_CDM_CMD_DMI_64 = 0xb,
CAM_CDM_CMD_COMP_WAIT = 0xc,
CAM_CDM_CLEAR_COMP_WAIT = 0xd,
CAM_CDM_WAIT_PREFETCH_DISABLE = 0xe,
CAM_CDM_CMD_PRIVATE_BASE = 0xf,
CAM_CDM_CMD_SWD_DMI_32 = (CAM_CDM_CMD_PRIVATE_BASE + 0x64),
CAM_CDM_CMD_SWD_DMI_64 = (CAM_CDM_CMD_PRIVATE_BASE + 0x65),
CAM_CDM_CMD_PRIVATE_BASE_MAX = 0x7F,
};
/**
* struct cam_cdm_utils_ops - Camera CDM util ops
*
* @cdm_get_cmd_header_size: Returns the size of the given command header
* in DWORDs.
* @command Command ID
* @return Size of the command in DWORDs
*
* @cdm_required_size_reg_continuous: Calculates the size of a reg-continuous
* command in dwords.
* @numVals Number of continuous values
* @return Size in dwords
*
* @cdm_required_size_reg_random: Calculates the size of a reg-random command
* in dwords.
* @numRegVals Number of register/value pairs
* @return Size in dwords
*
* @cdm_required_size_dmi: Calculates the size of a DMI command in dwords.
* @return Size in dwords
*
* @cdm_required_size_genirq: Calculates size of a Genirq command in dwords.
* @return Size in dwords
*
* @cdm_required_size_indirect: Calculates the size of an indirect command
* in dwords.
* @return Size in dwords
*
* @cdm_required_size_comp_wait: Calculates the size of a comp-wait command
* in dwords.
* @return Size in dwords
*
* @cdm_required_size_clear_comp_event: Calculates the size of clear-comp-event
* command in dwords.
* @return Size in dwords
*
* @cdm_required_size_changebase: Calculates the size of a change-base command
* in dwords.
* @return Size in dwords
*
* @cdm_offsetof_dmi_addr: Returns the offset of address field in the DMI
* command header.
* @return Offset of addr field
*
* @cdm_offsetof_indirect_addr: Returns the offset of address field in the
* indirect command header.
* @return Offset of addr field
*
* @cdm_write_regcontinuous: Writes a command into the command buffer.
* @pCmdBuffer: Pointer to command buffer
* @reg: Beginning of the register address range where
* values will be written.
* @numVals: Number of values (registers) that will be written
* @pVals : An array of values that will be written
* @return Pointer in command buffer pointing past the written commands
*
* @cdm_write_regrandom: Writes a command into the command buffer in
* register/value pairs.
* @pCmdBuffer: Pointer to command buffer
* @numRegVals: Number of register/value pairs that will be written
* @pRegVals: An array of register/value pairs that will be written
* The even indices are registers and the odd indices
* arevalues, e.g., {reg1, val1, reg2, val2, ...}.
* @return Pointer in command buffer pointing past the written commands
*
* @cdm_write_dmi: Writes a DMI command into the command bufferM.
* @pCmdBuffer: Pointer to command buffer
* @dmiCmd: DMI command
* @DMIAddr: Address of the DMI
* @DMISel: Selected bank that the DMI will write to
* @length: Size of data in bytes
* @return Pointer in command buffer pointing past the written commands
*
* @cdm_write_indirect: Writes a indirect command into the command buffer.
* @pCmdBuffer: Pointer to command buffer
* @indirectBufferAddr: Device address of the indirect cmd buffer.
* @length: Size of data in bytes
* @return Pointer in command buffer pointing past the written commands
*
* @cdm_write_changebase: Writes a changing CDM (address) base command into
* the command buffer.
* @pCmdBuffer: Pointer to command buffer
* @base: New base (device) address
* @return Pointer in command buffer pointing past the written commands
*
* @cdm_write_genirq: Writes a gen irq command into the command buffer.
* @pCmdBuffer: Pointer to command buffer
* @userdata: userdata or cookie return by hardware during irq.
*
* @cdm_write_wait_comp_event: Writes a wait comp event cmd into the
* command buffer.
* @pCmdBuffer: Pointer to command buffer
* @mask1: This value decides which comp events to wait (0 - 31).
* @mask2: This value decides which comp events to wait (32 - 65).
*
* @cdm_write_clear_comp_event: Writes a clear comp event cmd into the
* command buffer.
* @pCmdBuffer: Pointer to command buffer
* @mask1: This value decides which comp events to clear (0 - 31).
* @mask2: This value decides which comp events to clear (32 - 65).
*/
struct cam_cdm_utils_ops {
uint32_t (*cdm_get_cmd_header_size)(unsigned int command);
uint32_t (*cdm_required_size_dmi)(void);
uint32_t (*cdm_required_size_reg_continuous)(uint32_t numVals);
uint32_t (*cdm_required_size_reg_random)(uint32_t numRegVals);
uint32_t (*cdm_required_size_indirect)(void);
uint32_t (*cdm_required_size_genirq)(void);
uint32_t (*cdm_required_size_wait_event)(void);
uint32_t (*cdm_required_size_changebase)(void);
uint32_t (*cdm_required_size_comp_wait)(void);
uint32_t (*cdm_required_size_clear_comp_event)(void);
uint32_t (*cdm_required_size_prefetch_disable)(void);
uint32_t (*cdm_offsetof_dmi_addr)(void);
uint32_t (*cdm_offsetof_indirect_addr)(void);
uint32_t *(*cdm_write_dmi)(
uint32_t *pCmdBuffer,
uint8_t dmiCmd,
uint32_t DMIAddr,
uint8_t DMISel,
uint32_t dmiBufferAddr,
uint32_t length);
uint32_t* (*cdm_write_regcontinuous)(
uint32_t *pCmdBuffer,
uint32_t reg,
uint32_t numVals,
uint32_t *pVals);
uint32_t *(*cdm_write_regrandom)(
uint32_t *pCmdBuffer,
uint32_t numRegVals,
uint32_t *pRegVals);
uint32_t *(*cdm_write_indirect)(
uint32_t *pCmdBuffer,
uint32_t indirectBufferAddr,
uint32_t length);
void (*cdm_write_genirq)(
uint32_t *pCmdBuffer,
uint32_t userdata,
bool bit_wr_enable,
uint32_t fifo_idx);
uint32_t *(*cdm_write_wait_event)(
uint32_t *pCmdBuffer,
uint32_t iw,
uint32_t id,
uint32_t mask,
uint32_t offset,
uint32_t data);
uint32_t *(*cdm_write_changebase)(
uint32_t *pCmdBuffer,
uint32_t base);
uint32_t *(*cdm_write_wait_comp_event)(
uint32_t *pCmdBuffer,
uint32_t mask1,
uint32_t mask2);
uint32_t *(*cdm_write_clear_comp_event)(
uint32_t *pCmdBuffer,
uint32_t mask1,
uint32_t mask2);
uint32_t *(*cdm_write_wait_prefetch_disable)(
uint32_t *pCmdBuffer,
uint32_t id,
uint32_t mask1,
uint32_t mask2);
};
/**
* struct cam_cdm_cmd_buf_dump_info; - Camera CDM dump info
* @dst_offset: dst offset
* @dst_max_size max size of destination buffer
* @src_start: source start address
* @src_end: source end address
* @dst_start: dst start address
*/
struct cam_cdm_cmd_buf_dump_info {
size_t dst_offset;
size_t dst_max_size;
uint32_t *src_start;
uint32_t *src_end;
uintptr_t dst_start;
};
/**
* struct cam_cdm_cmd_dump_header- Camera CDM dump header
* @tag: tag name for header
* @size: size of data
* @word_size: size of each word
*/
struct cam_cdm_cmd_dump_header {
uint8_t tag[CAM_CDM_CMD_TAG_MAX_LEN];
uint64_t size;
uint32_t word_size;
};
/**
* cam_cdm_util_validate_cmd_buf()
*
* @brief: Util function to validate cdm command buffers
*
* @cmd_buffer_start: Pointer to start of cmd buffer
* @cmd_buffer_end: Pointer to end of cmd buffer
*
* return true if invalid cmd found, otherwise false
*
*/
bool cam_cdm_util_validate_cmd_buf(
uint32_t *cmd_buffer_start, uint32_t *cmd_buffer_end);
/**
* cam_cdm_util_log_cmd_bufs()
*
* @brief: Util function to log cdm command buffers
*
* @cmd_buffer_start: Pointer to start of cmd buffer
* @cmd_buffer_end: Pointer to end of cmd buffer
*
*/
void cam_cdm_util_dump_cmd_buf(
uint32_t *cmd_buffer_start, uint32_t *cmd_buffer_end);
/**
* cam_cdm_util_dump_cmd_bufs_v2()
*
* @brief: Util function to cdm command buffers
* to a buffer
*
* @dump_info: Information about source and destination buffers
*
* return SUCCESS/FAILURE
*/
int cam_cdm_util_dump_cmd_bufs_v2(
struct cam_cdm_cmd_buf_dump_info *dump_info);
#endif /* _CAM_CDM_UTIL_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_virtual.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_CDM_VIRTUAL_H_
#define _CAM_CDM_VIRTUAL_H_
#include "cam_cdm_intf_api.h"
int cam_virtual_cdm_probe(struct platform_device *pdev);
int cam_virtual_cdm_remove(struct platform_device *pdev);
int cam_cdm_util_cmd_buf_write(void __iomem **current_device_base,
uint32_t *cmd_buf, uint32_t cmd_buf_size,
struct cam_soc_reg_map *base_table[CAM_SOC_MAX_BLOCK],
uint32_t base_array_size, uint8_t bl_tag);
#endif /* _CAM_CDM_VIRTUAL_H_ */

409
qcom/opensource/camera-kernel/drivers/cam_cdm/cam_cdm_virtual_core.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/kernel.h>
#include "cam_soc_util.h"
#include "cam_smmu_api.h"
#include "cam_cdm_intf_api.h"
#include "cam_cdm.h"
#include "cam_cdm_util.h"
#include "cam_cdm_virtual.h"
#include "cam_cdm_core_common.h"
#include "cam_cdm_soc.h"
#include "cam_io_util.h"
#include "cam_req_mgr_workq.h"
#include "cam_common_util.h"
#define CAM_CDM_VIRTUAL_NAME "qcom,cam_virtual_cdm"
static void cam_virtual_cdm_work(struct work_struct *work)
{
struct cam_cdm_work_payload *payload;
struct cam_hw_info *cdm_hw;
struct cam_cdm *core;
payload = container_of(work, struct cam_cdm_work_payload, work);
if (payload) {
cdm_hw = payload->hw;
core = (struct cam_cdm *)cdm_hw->core_info;
cam_common_util_thread_switch_delay_detect(
"virtual_cdm_workq", "schedule", cam_virtual_cdm_work,
payload->workq_scheduled_ts,
CAM_WORKQ_SCHEDULE_TIME_THRESHOLD);
if (payload->irq_status & 0x2) {
struct cam_cdm_bl_cb_request_entry *node;
CAM_DBG(CAM_CDM, "CDM HW Gen/inline IRQ with data=%x",
payload->irq_data);
mutex_lock(&cdm_hw->hw_mutex);
node = cam_cdm_find_request_by_bl_tag(
payload->irq_data,
&core->bl_request_list);
if (node) {
if (node->request_type ==
CAM_HW_CDM_BL_CB_CLIENT) {
cam_cdm_notify_clients(cdm_hw,
CAM_CDM_CB_STATUS_BL_SUCCESS,
(void *)node);
} else if (node->request_type ==
CAM_HW_CDM_BL_CB_INTERNAL) {
CAM_ERR(CAM_CDM, "Invalid node=%pK %d",
node, node->request_type);
}
list_del_init(&node->entry);
kfree(node);
} else {
CAM_ERR(CAM_CDM, "Invalid node for inline irq");
}
mutex_unlock(&cdm_hw->hw_mutex);
}
if (payload->irq_status & 0x1) {
CAM_DBG(CAM_CDM, "CDM HW reset done IRQ");
complete(&core->reset_complete);
}
kfree(payload);
}
}
int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw,
struct cam_cdm_hw_intf_cmd_submit_bl *req,
struct cam_cdm_client *client)
{
int i, rc = -EINVAL;
struct cam_cdm_bl_request *cdm_cmd = req->data;
struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info;
mutex_lock(&client->lock);
for (i = 0; i < req->data->cmd_arrary_count ; i++) {
uintptr_t vaddr_ptr = 0;
size_t len = 0;
if ((!cdm_cmd->cmd[i].len) &&
(cdm_cmd->cmd[i].len > 0x100000)) {
CAM_ERR(CAM_CDM,
"len(%d) is invalid count=%d total cnt=%d",
cdm_cmd->cmd[i].len, i,
req->data->cmd_arrary_count);
rc = -EINVAL;
break;
}
if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) {
rc = cam_mem_get_cpu_buf(
cdm_cmd->cmd[i].bl_addr.mem_handle, &vaddr_ptr,
&len);
if (rc) {
CAM_ERR(CAM_CDM,
"Falied to get CPU addr_i[%d] req_type %d", i,
req->data->type);
}
} else if (req->data->type ==
CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA) {
rc = 0;
vaddr_ptr = cdm_cmd->cmd[i].bl_addr.kernel_iova;
len = cdm_cmd->cmd[i].offset + cdm_cmd->cmd[i].len;
} else {
CAM_ERR(CAM_CDM,
"Only mem hdl/Kernel va type is supported %d",
req->data->type);
rc = -EINVAL;
}
if ((!rc) && (vaddr_ptr) && (len) &&
(len >= cdm_cmd->cmd[i].offset)) {
if ((len - cdm_cmd->cmd[i].offset) <
cdm_cmd->cmd[i].len) {
CAM_ERR(CAM_CDM, "Not enough buffer");
rc = -EINVAL;
goto put_cpu_buf;
}
CAM_DBG(CAM_CDM,
"hdl=%x vaddr=%pK offset=%d cmdlen=%d:%zu",
cdm_cmd->cmd[i].bl_addr.mem_handle,
(void *)vaddr_ptr, cdm_cmd->cmd[i].offset,
cdm_cmd->cmd[i].len, len);
rc = cam_cdm_util_cmd_buf_write(
&client->changebase_addr,
((uint32_t *)vaddr_ptr +
((cdm_cmd->cmd[i].offset)/4)),
cdm_cmd->cmd[i].len, client->data.base_array,
client->data.base_array_cnt, core->bl_tag);
if (rc) {
CAM_ERR(CAM_CDM,
"write failed for cnt=%d:%d len %u",
i, req->data->cmd_arrary_count,
cdm_cmd->cmd[i].len);
goto put_cpu_buf;
}
} else {
CAM_ERR(CAM_CDM,
"Sanity check failed for hdl=%x len=%zu:%d",
cdm_cmd->cmd[i].bl_addr.mem_handle, len,
cdm_cmd->cmd[i].offset);
CAM_ERR(CAM_CDM,
"Sanity check failed for cmd_count=%d cnt=%d",
i, req->data->cmd_arrary_count);
rc = -EINVAL;
goto err;
}
if (!rc) {
struct cam_cdm_work_payload *payload;
CAM_DBG(CAM_CDM,
"write BL success for cnt=%d with tag=%d",
i, core->bl_tag);
if (req->data->flag && (i == req->data->cmd_arrary_count)) {
struct cam_cdm_bl_cb_request_entry *node;
node = kzalloc(sizeof(
struct cam_cdm_bl_cb_request_entry),
GFP_KERNEL);
if (!node) {
rc = -ENOMEM;
goto err;
}
node->request_type = CAM_HW_CDM_BL_CB_CLIENT;
node->client_hdl = req->handle;
node->cookie = req->data->cookie;
node->bl_tag = core->bl_tag;
node->userdata = req->data->userdata;
mutex_lock(&cdm_hw->hw_mutex);
list_add_tail(&node->entry,
&core->bl_request_list);
mutex_unlock(&cdm_hw->hw_mutex);
payload = kzalloc(sizeof(
struct cam_cdm_work_payload),
GFP_ATOMIC);
if (payload) {
payload->irq_status = 0x2;
payload->irq_data = core->bl_tag;
payload->hw = cdm_hw;
INIT_WORK((struct work_struct *)
&payload->work,
cam_virtual_cdm_work);
payload->workq_scheduled_ts =
ktime_get();
queue_work(core->work_queue,
&payload->work);
}
}
core->bl_tag++;
CAM_DBG(CAM_CDM,
"Now commit the BL nothing for virtual");
if (!rc && (core->bl_tag == 63))
core->bl_tag = 0;
if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE)
cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle);
}
}
mutex_unlock(&client->lock);
return rc;
put_cpu_buf:
if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE)
cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle);
err:
mutex_unlock(&client->lock);
return rc;
}
int cam_virtual_cdm_probe(struct platform_device *pdev)
{
struct cam_hw_info *cdm_hw = NULL;
struct cam_hw_intf *cdm_hw_intf = NULL;
struct cam_cdm *cdm_core = NULL;
struct cam_cdm_private_dt_data *soc_private = NULL;
int rc;
struct cam_cpas_register_params cpas_parms;
cdm_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL);
if (!cdm_hw_intf)
return -ENOMEM;
cdm_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL);
if (!cdm_hw) {
kfree(cdm_hw_intf);
return -ENOMEM;
}
cdm_hw->core_info = kzalloc(sizeof(struct cam_cdm), GFP_KERNEL);
if (!cdm_hw->core_info) {
kfree(cdm_hw);
kfree(cdm_hw_intf);
return -ENOMEM;
}
cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN;
cdm_hw->soc_info.pdev = pdev;
cdm_hw_intf->hw_type = CAM_VIRTUAL_CDM;
cdm_hw->soc_info.soc_private = kzalloc(
sizeof(struct cam_cdm_private_dt_data), GFP_KERNEL);
if (!cdm_hw->soc_info.soc_private) {
rc = -ENOMEM;
goto soc_load_failed;
}
rc = cam_cdm_soc_load_dt_private(pdev, cdm_hw->soc_info.soc_private);
if (rc) {
CAM_ERR(CAM_CDM, "Failed to load CDM dt private data");
kfree(cdm_hw->soc_info.soc_private);
cdm_hw->soc_info.soc_private = NULL;
goto soc_load_failed;
}
cdm_core = (struct cam_cdm *)cdm_hw->core_info;
soc_private = (struct cam_cdm_private_dt_data *)
cdm_hw->soc_info.soc_private;
if (soc_private->dt_cdm_shared == true)
cdm_core->flags = CAM_CDM_FLAG_SHARED_CDM;
else
cdm_core->flags = CAM_CDM_FLAG_PRIVATE_CDM;
cdm_core->bl_tag = 0;
INIT_LIST_HEAD(&cdm_core->bl_request_list);
init_completion(&cdm_core->reset_complete);
cdm_hw_intf->hw_priv = cdm_hw;
cdm_hw_intf->hw_ops.get_hw_caps = cam_cdm_get_caps;
cdm_hw_intf->hw_ops.init = NULL;
cdm_hw_intf->hw_ops.deinit = NULL;
cdm_hw_intf->hw_ops.start = cam_cdm_stream_start;
cdm_hw_intf->hw_ops.stop = cam_cdm_stream_stop;
cdm_hw_intf->hw_ops.read = NULL;
cdm_hw_intf->hw_ops.write = NULL;
cdm_hw_intf->hw_ops.process_cmd = cam_cdm_process_cmd;
CAM_DBG(CAM_CDM, "type %d index %d", cdm_hw_intf->hw_type,
cdm_hw_intf->hw_idx);
platform_set_drvdata(pdev, cdm_hw_intf);
cdm_hw->open_count = 0;
cdm_core->iommu_hdl.non_secure = -1;
cdm_core->iommu_hdl.secure = -1;
mutex_init(&cdm_hw->hw_mutex);
spin_lock_init(&cdm_hw->hw_lock);
init_completion(&cdm_hw->hw_complete);
mutex_lock(&cdm_hw->hw_mutex);
cdm_core->id = CAM_CDM_VIRTUAL;
memcpy(cdm_core->name, CAM_CDM_VIRTUAL_NAME,
sizeof(CAM_CDM_VIRTUAL_NAME));
cdm_core->work_queue = alloc_workqueue(cdm_core->name,
WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS,
CAM_CDM_INFLIGHT_WORKS);
cdm_core->ops = NULL;
cpas_parms.cam_cpas_client_cb = cam_cdm_cpas_cb;
cpas_parms.cell_index = cdm_hw->soc_info.index;
cpas_parms.dev = &pdev->dev;
cpas_parms.userdata = cdm_hw_intf;
strlcpy(cpas_parms.identifier, "cam-cdm-intf",
CAM_HW_IDENTIFIER_LENGTH);
rc = cam_cpas_register_client(&cpas_parms);
if (rc) {
CAM_ERR(CAM_CDM, "Virtual CDM CPAS registration failed");
goto cpas_registration_failed;
}
CAM_DBG(CAM_CDM, "CPAS registration successful handle=%d",
cpas_parms.client_handle);
cdm_core->cpas_handle = cpas_parms.client_handle;
CAM_DBG(CAM_CDM, "CDM%d probe successful", cdm_hw_intf->hw_idx);
rc = cam_cdm_intf_register_hw_cdm(cdm_hw_intf,
soc_private, CAM_VIRTUAL_CDM, &cdm_core->index);
if (rc) {
CAM_ERR(CAM_CDM, "Virtual CDM Interface registration failed");
goto intf_registration_failed;
}
CAM_DBG(CAM_CDM, "CDM%d registered to intf successful",
cdm_hw_intf->hw_idx);
mutex_unlock(&cdm_hw->hw_mutex);
return 0;
intf_registration_failed:
cam_cpas_unregister_client(cdm_core->cpas_handle);
cpas_registration_failed:
kfree(cdm_hw->soc_info.soc_private);
flush_workqueue(cdm_core->work_queue);
destroy_workqueue(cdm_core->work_queue);
mutex_unlock(&cdm_hw->hw_mutex);
mutex_destroy(&cdm_hw->hw_mutex);
soc_load_failed:
kfree(cdm_hw->core_info);
kfree(cdm_hw);
kfree(cdm_hw_intf);
return rc;
}
int cam_virtual_cdm_remove(struct platform_device *pdev)
{
struct cam_hw_info *cdm_hw = NULL;
struct cam_hw_intf *cdm_hw_intf = NULL;
struct cam_cdm *cdm_core = NULL;
int rc = -EBUSY;
cdm_hw_intf = platform_get_drvdata(pdev);
if (!cdm_hw_intf) {
CAM_ERR(CAM_CDM, "Failed to get dev private data");
return rc;
}
cdm_hw = cdm_hw_intf->hw_priv;
if (!cdm_hw) {
CAM_ERR(CAM_CDM,
"Failed to get virtual private data for type=%d idx=%d",
cdm_hw_intf->hw_type, cdm_hw_intf->hw_idx);
return rc;
}
cdm_core = cdm_hw->core_info;
if (!cdm_core) {
CAM_ERR(CAM_CDM,
"Failed to get virtual core data for type=%d idx=%d",
cdm_hw_intf->hw_type, cdm_hw_intf->hw_idx);
return rc;
}
rc = cam_cpas_unregister_client(cdm_core->cpas_handle);
if (rc) {
CAM_ERR(CAM_CDM, "CPAS unregister failed");
return rc;
}
rc = cam_cdm_intf_deregister_hw_cdm(cdm_hw_intf,
cdm_hw->soc_info.soc_private, CAM_VIRTUAL_CDM,
cdm_core->index);
if (rc) {
CAM_ERR(CAM_CDM,
"Virtual CDM Interface de-registration failed");
return rc;
}
flush_workqueue(cdm_core->work_queue);
destroy_workqueue(cdm_core->work_queue);
mutex_destroy(&cdm_hw->hw_mutex);
kfree(cdm_hw->soc_info.soc_private);
kfree(cdm_hw->core_info);
kfree(cdm_hw);
kfree(cdm_hw_intf);
rc = 0;
return rc;
}

842
qcom/opensource/camera-kernel/drivers/cam_core/cam_context.c Normal file
View File

@ -0,0 +1,842 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/refcount.h>
#include "cam_context.h"
#include "cam_debug_util.h"
#include "cam_node.h"
#include "cam_context_utils.h"
static int cam_context_handle_hw_event(void *context, uint32_t evt_id,
void *evt_data)
{
int rc = 0;
struct cam_context *ctx = (struct cam_context *)context;
if (!ctx || !ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (ctx->state_machine[ctx->state].irq_ops)
rc = ctx->state_machine[ctx->state].irq_ops(ctx, evt_id,
evt_data);
else
CAM_DBG(CAM_CORE,
"No function to handle event %d in dev %d, state %d",
evt_id, ctx->dev_hdl, ctx->state);
return rc;
}
int cam_context_shutdown(struct cam_context *ctx)
{
int rc = 0;
struct cam_release_dev_cmd cmd;
if (ctx->state > CAM_CTX_AVAILABLE && ctx->state < CAM_CTX_STATE_MAX) {
cmd.session_handle = ctx->session_hdl;
cmd.dev_handle = ctx->dev_hdl;
rc = cam_context_handle_release_dev(ctx, &cmd);
if (rc)
CAM_ERR(CAM_CORE,
"context release failed for dev_name %s",
ctx->dev_name);
else
cam_context_putref(ctx);
} else {
CAM_WARN(CAM_CORE,
"dev %s context id %u state %d invalid to release hdl",
ctx->dev_name, ctx->ctx_id, ctx->state);
rc = -EINVAL;
}
if (ctx->dev_hdl != -1) {
rc = cam_destroy_device_hdl(ctx->dev_hdl);
if (rc)
CAM_ERR(CAM_CORE,
"destroy device hdl failed for node %s",
ctx->dev_name);
else
ctx->dev_hdl = -1;
}
return rc;
}
int cam_context_handle_crm_get_dev_info(struct cam_context *ctx,
struct cam_req_mgr_device_info *info)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!info) {
CAM_ERR(CAM_CORE, "Invalid get device info payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].crm_ops.get_dev_info) {
rc = ctx->state_machine[ctx->state].crm_ops.get_dev_info(
ctx, info);
} else {
CAM_ERR(CAM_CORE, "No get device info in dev %d, state %d",
ctx->dev_hdl, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_crm_link(struct cam_context *ctx,
struct cam_req_mgr_core_dev_link_setup *link)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!link) {
CAM_ERR(CAM_CORE, "Invalid link payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].crm_ops.link) {
rc = ctx->state_machine[ctx->state].crm_ops.link(ctx, link);
} else {
CAM_ERR(CAM_CORE, "No crm link in dev %d, state %d",
ctx->dev_hdl, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_crm_unlink(struct cam_context *ctx,
struct cam_req_mgr_core_dev_link_setup *unlink)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!unlink) {
CAM_ERR(CAM_CORE, "Invalid unlink payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].crm_ops.unlink) {
rc = ctx->state_machine[ctx->state].crm_ops.unlink(
ctx, unlink);
} else {
CAM_ERR(CAM_CORE, "No crm unlink in dev %d, name %s, state %d",
ctx->dev_hdl, ctx->dev_name, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_crm_apply_req(struct cam_context *ctx,
struct cam_req_mgr_apply_request *apply)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!apply) {
CAM_ERR(CAM_CORE, "Invalid apply request payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].crm_ops.apply_req) {
rc = ctx->state_machine[ctx->state].crm_ops.apply_req(ctx,
apply);
} else {
CAM_ERR(CAM_CORE, "No crm apply req in dev %d, state %d",
ctx->dev_hdl, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_crm_notify_frame_skip(
struct cam_context *ctx,
struct cam_req_mgr_apply_request *apply)
{
int rc = 0;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!apply) {
CAM_ERR(CAM_CORE, "Invalid apply request payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].crm_ops.notify_frame_skip)
rc = ctx->state_machine[ctx->state].crm_ops.notify_frame_skip(
ctx, apply);
else
CAM_DBG(CAM_CORE,
"No crm notify_frame_skip in dev %d, state %d",
ctx->dev_hdl, ctx->state);
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_crm_flush_req(struct cam_context *ctx,
struct cam_req_mgr_flush_request *flush)
{
int rc = 0;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state != CAM_CTX_FLUSHED) {
if (ctx->state_machine[ctx->state].crm_ops.flush_req) {
rc = ctx->state_machine[ctx->state].crm_ops.flush_req(ctx,
flush);
} else {
CAM_INFO(CAM_CORE, "No crm flush req in dev %d, state %d, name %s",
ctx->dev_hdl, ctx->state, ctx->dev_name);
rc = -EPROTO;
}
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_crm_process_evt(struct cam_context *ctx,
struct cam_req_mgr_link_evt_data *process_evt)
{
int rc = 0;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].crm_ops.process_evt) {
rc = ctx->state_machine[ctx->state].crm_ops.process_evt(ctx,
process_evt);
} else {
/* handling of this message is optional */
CAM_DBG(CAM_CORE, "No crm process evt in dev %d, state %d",
ctx->dev_hdl, ctx->state);
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_crm_dump_req(struct cam_context *ctx,
struct cam_req_mgr_dump_info *dump)
{
int rc = 0;
if (!ctx) {
CAM_ERR(CAM_CORE, "Invalid Context");
return -EINVAL;
}
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context %s ctx_id %d is not ready",
ctx->dev_name, ctx->ctx_id);
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].crm_ops.dump_req)
rc = ctx->state_machine[ctx->state].crm_ops.dump_req(ctx,
dump);
else
CAM_ERR(CAM_CORE, "No crm dump req for %s dev %d, state %d",
ctx->dev_name, ctx->dev_hdl, ctx->state);
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_mini_dump_from_hw(struct cam_context *ctx,
void *args)
{
int rc = 0;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context [id %d name:%s] is not ready", ctx->ctx_id,
ctx->dev_name);
return -EINVAL;
}
if ((ctx->state >= CAM_CTX_AVAILABLE) && (ctx->state < CAM_CTX_STATE_MAX)) {
if (ctx->state_machine[ctx->state].mini_dump_ops)
rc = ctx->state_machine[ctx->state].mini_dump_ops(ctx, args);
else
CAM_WARN(CAM_CORE, "No dump ctx in dev %d, state %d",
ctx->dev_hdl, ctx->state);
}
return rc;
}
int cam_context_dump_pf_info(void *data, void *args)
{
struct cam_context *ctx = data;
struct cam_hw_dump_pf_args *pf_args = args;
int rc = 0;
if (!pf_args) {
CAM_ERR(CAM_CORE, "PF args is NULL");
return -EINVAL;
}
if (!ctx) {
CAM_ERR(CAM_CORE, "Context is NULL");
if (pf_args->pf_context_info.force_send_pf_evt) {
rc = cam_context_send_pf_evt(ctx, pf_args);
if (rc)
CAM_ERR(CAM_CORE,
"Failed to notify PF event to userspace rc: %d", rc);
}
return -EINVAL;
}
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if ((ctx->state > CAM_CTX_AVAILABLE) &&
(ctx->state < CAM_CTX_STATE_MAX)) {
if (ctx->state_machine[ctx->state].pagefault_ops) {
rc = ctx->state_machine[ctx->state].pagefault_ops(
ctx, pf_args);
} else {
CAM_WARN(CAM_CORE, "No dump ctx in dev %d, state %d",
ctx->dev_hdl, ctx->state);
}
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_message(struct cam_context *ctx,
uint32_t msg_type, void *data)
{
int rc = 0;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if ((ctx->state > CAM_CTX_AVAILABLE) &&
(ctx->state < CAM_CTX_STATE_MAX)) {
if (ctx->state_machine[ctx->state].msg_cb_ops) {
rc = ctx->state_machine[ctx->state].msg_cb_ops(
ctx, msg_type, data);
} else {
CAM_WARN(CAM_CORE,
"No message handler for ctx %d, state %d msg_type :%d",
ctx->dev_hdl, ctx->state, msg_type);
}
}
return rc;
}
int cam_context_handle_acquire_dev(struct cam_context *ctx,
struct cam_acquire_dev_cmd *cmd)
{
int rc;
int i;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!cmd) {
CAM_ERR(CAM_CORE, "Invalid acquire device command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.acquire_dev) {
rc = ctx->state_machine[ctx->state].ioctl_ops.acquire_dev(
ctx, cmd);
} else {
CAM_ERR(CAM_CORE, "No acquire device in dev %d, state %d",
cmd->dev_handle, ctx->state);
rc = -EPROTO;
}
INIT_LIST_HEAD(&ctx->active_req_list);
INIT_LIST_HEAD(&ctx->wait_req_list);
INIT_LIST_HEAD(&ctx->pending_req_list);
INIT_LIST_HEAD(&ctx->free_req_list);
for (i = 0; i < ctx->req_size; i++) {
INIT_LIST_HEAD(&ctx->req_list[i].list);
list_add_tail(&ctx->req_list[i].list, &ctx->free_req_list);
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_acquire_hw(struct cam_context *ctx,
void *args)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!args) {
CAM_ERR(CAM_CORE, "Invalid acquire device hw command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.acquire_hw) {
rc = ctx->state_machine[ctx->state].ioctl_ops.acquire_hw(
ctx, args);
} else {
CAM_ERR(CAM_CORE, "No acquire hw for dev %s, state %d",
ctx->dev_name, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_release_dev(struct cam_context *ctx,
struct cam_release_dev_cmd *cmd)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!cmd) {
CAM_ERR(CAM_CORE, "Invalid release device command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.release_dev) {
rc = ctx->state_machine[ctx->state].ioctl_ops.release_dev(
ctx, cmd);
} else {
CAM_ERR(CAM_CORE, "No release device in dev %d, state %d",
ctx->dev_hdl, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_release_hw(struct cam_context *ctx,
void *args)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!args) {
CAM_ERR(CAM_CORE, "Invalid release HW command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.release_hw) {
rc = ctx->state_machine[ctx->state].ioctl_ops.release_hw(
ctx, args);
} else {
CAM_ERR(CAM_CORE, "No release hw for dev %s, state %d",
ctx->dev_name, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_flush_dev(struct cam_context *ctx,
struct cam_flush_dev_cmd *cmd)
{
int rc = 0;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!cmd) {
CAM_ERR(CAM_CORE, "Invalid flush device command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.flush_dev) {
rc = ctx->state_machine[ctx->state].ioctl_ops.flush_dev(
ctx, cmd);
} else {
CAM_WARN(CAM_CORE, "No flush device in dev %d, state %d",
ctx->dev_hdl, ctx->state);
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_config_dev(struct cam_context *ctx,
struct cam_config_dev_cmd *cmd)
{
int rc;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "context is not ready");
return -EINVAL;
}
if (!cmd) {
CAM_ERR(CAM_CORE, "Invalid config device command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.config_dev) {
rc = ctx->state_machine[ctx->state].ioctl_ops.config_dev(
ctx, cmd);
} else {
CAM_INFO(CAM_CORE, "No config device in dev %d, state %d",
ctx->dev_hdl, ctx->state);
rc = -EPROTO;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_start_dev(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd)
{
int rc = 0;
if (!ctx || !ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!cmd) {
CAM_ERR(CAM_CORE, "Invalid start device command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.start_dev)
rc = ctx->state_machine[ctx->state].ioctl_ops.start_dev(
ctx, cmd);
else
/* start device can be optional for some driver */
CAM_DBG(CAM_CORE, "No start device in dev %d, state %d",
ctx->dev_hdl, ctx->state);
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_stop_dev(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd)
{
int rc = 0;
if (!ctx || !ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
if (!cmd) {
CAM_ERR(CAM_CORE, "Invalid stop device command payload");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].ioctl_ops.stop_dev)
rc = ctx->state_machine[ctx->state].ioctl_ops.stop_dev(
ctx, cmd);
else
/* stop device can be optional for some driver */
CAM_WARN(CAM_CORE, "No stop device in dev %d, name %s state %d",
ctx->dev_hdl, ctx->dev_name, ctx->state);
ctx->last_flush_req = 0;
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_info_dump(void *context,
enum cam_context_dump_id id)
{
int rc = 0;
struct cam_context *ctx = (struct cam_context *)context;
if (!ctx || !ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state_machine[ctx->state].dumpinfo_ops)
rc = ctx->state_machine[ctx->state].dumpinfo_ops(ctx,
id);
mutex_unlock(&ctx->ctx_mutex);
if (rc)
CAM_WARN(CAM_CORE,
"Dump for id %u failed on ctx_id %u name %s state %d",
id, ctx->ctx_id, ctx->dev_name, ctx->state);
return rc;
}
int cam_context_handle_dump_dev(struct cam_context *ctx,
struct cam_dump_req_cmd *cmd)
{
int rc = 0;
if (!ctx) {
CAM_ERR(CAM_CORE, "Invalid Context");
return -EINVAL;
}
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context %s ctx_id %d is not ready",
ctx->dev_name, ctx->ctx_id);
return -EINVAL;
}
if (!cmd) {
CAM_ERR(CAM_CORE,
"Context %s ctx_id %d Invalid dump command payload",
ctx->dev_name, ctx->ctx_id);
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
CAM_DBG(CAM_CORE, "dump device in dev %d, name %s state %d",
ctx->dev_hdl, ctx->dev_name, ctx->state);
if (ctx->state_machine[ctx->state].ioctl_ops.dump_dev)
rc = ctx->state_machine[ctx->state].ioctl_ops.dump_dev(
ctx, cmd);
else
CAM_WARN(CAM_CORE, "No dump device in dev %d, name %s state %d",
ctx->dev_hdl, ctx->dev_name, ctx->state);
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_handle_hw_recovery(void *priv, void *data)
{
struct cam_context *ctx = priv;
int rc = 0;
if (!ctx) {
CAM_ERR(CAM_CORE, "null context");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if (ctx->state != CAM_CTX_ACTIVATED) {
CAM_DBG(CAM_CORE, "skipping recovery for ctx:%d dev:%s in state:%d", ctx->ctx_id,
ctx->dev_name, ctx->state);
goto end;
}
CAM_DBG(CAM_CORE, "try hw recovery for ctx:%d dev:%s", ctx->ctx_id, ctx->dev_name);
if (ctx->state_machine[ctx->state].recovery_ops)
rc = ctx->state_machine[ctx->state].recovery_ops(priv, data);
else
CAM_WARN(CAM_CORE, "no recovery op in state:%d for ctx:%d dev:%s",
ctx->state, ctx->ctx_id, ctx->dev_name);
end:
mutex_unlock(&ctx->ctx_mutex);
return rc;
}
int cam_context_init(struct cam_context *ctx,
const char *dev_name,
uint64_t dev_id,
uint32_t ctx_id,
struct cam_req_mgr_kmd_ops *crm_node_intf,
struct cam_hw_mgr_intf *hw_mgr_intf,
struct cam_ctx_request *req_list,
uint32_t req_size, int img_iommu_hdl)
{
int i;
/* crm_node_intf is optinal */
if (!ctx || !hw_mgr_intf || !req_list) {
CAM_ERR(CAM_CORE, "Invalid input parameters");
return -EINVAL;
}
memset(ctx, 0, sizeof(*ctx));
ctx->dev_hdl = -1;
ctx->link_hdl = -1;
ctx->session_hdl = -1;
INIT_LIST_HEAD(&ctx->list);
mutex_init(&ctx->ctx_mutex);
mutex_init(&ctx->sync_mutex);
spin_lock_init(&ctx->lock);
strlcpy(ctx->dev_name, dev_name, CAM_CTX_DEV_NAME_MAX_LENGTH);
ctx->dev_id = dev_id;
ctx->ctx_id = ctx_id;
ctx->last_flush_req = 0;
ctx->ctx_crm_intf = NULL;
ctx->crm_ctx_intf = crm_node_intf;
ctx->hw_mgr_intf = hw_mgr_intf;
ctx->irq_cb_intf = cam_context_handle_hw_event;
INIT_LIST_HEAD(&ctx->active_req_list);
INIT_LIST_HEAD(&ctx->wait_req_list);
INIT_LIST_HEAD(&ctx->pending_req_list);
INIT_LIST_HEAD(&ctx->free_req_list);
ctx->req_list = req_list;
ctx->req_size = req_size;
for (i = 0; i < req_size; i++) {
INIT_LIST_HEAD(&ctx->req_list[i].list);
list_add_tail(&ctx->req_list[i].list, &ctx->free_req_list);
ctx->req_list[i].ctx = ctx;
ctx->req_list[i].index = i;
}
ctx->state = CAM_CTX_AVAILABLE;
ctx->state_machine = NULL;
ctx->ctx_priv = NULL;
ctx->img_iommu_hdl = img_iommu_hdl;
return 0;
}
int cam_context_deinit(struct cam_context *ctx)
{
if (!ctx)
return -EINVAL;
/**
* This is called from platform device remove.
* Everyting should be released at this moment.
* so we just free the memory for the context
*/
if (ctx->state != CAM_CTX_AVAILABLE)
CAM_ERR(CAM_CORE, "Device did not shutdown cleanly");
memset(ctx, 0, sizeof(*ctx));
return 0;
}
void cam_context_putref(struct cam_context *ctx)
{
if (kref_read(&ctx->refcount))
kref_put(&ctx->refcount, cam_node_put_ctxt_to_free_list);
else
WARN(1, "ctx %s %d state %d devhdl %X\n", ctx->dev_name,
ctx->ctx_id, ctx->state, ctx->dev_hdl);
CAM_DBG(CAM_CORE,
"ctx device hdl %ld, ref count %d, dev_name %s",
ctx->dev_hdl, refcount_read(&(ctx->refcount.refcount)),
ctx->dev_name);
}
void cam_context_getref(struct cam_context *ctx)
{
if (kref_get_unless_zero(&ctx->refcount) == 0) {
/* should never happen */
WARN(1, "%s fail\n", __func__);
}
CAM_DBG(CAM_CORE,
"ctx device hdl %ld, ref count %d, dev_name %s",
ctx->dev_hdl, refcount_read(&(ctx->refcount.refcount)),
ctx->dev_name);
}
int cam_context_add_evt_inject(struct cam_context *ctx, void *evt_args)
{
int rc = 0;
if (!ctx->state_machine) {
CAM_ERR(CAM_CORE, "Context is not ready");
return -EINVAL;
}
mutex_lock(&ctx->ctx_mutex);
if ((ctx->state > CAM_CTX_AVAILABLE) &&
(ctx->state < CAM_CTX_STATE_MAX)) {
if (ctx->state_machine[ctx->state].evt_inject_ops) {
rc = ctx->state_machine[ctx->state].evt_inject_ops(
ctx, evt_args);
} else {
CAM_WARN(CAM_CORE, "No evt inject ops in dev %d, state %d",
ctx->dev_hdl, ctx->state);
}
} else {
rc = -EINVAL;
}
mutex_unlock(&ctx->ctx_mutex);
return rc;
}

668
qcom/opensource/camera-kernel/drivers/cam_core/cam_context.h Normal file
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@ -0,0 +1,668 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CONTEXT_H_
#define _CAM_CONTEXT_H_
#include <linux/mutex.h>
#include <linux/spinlock_types.h>
#include <linux/kref.h>
#include <media/v4l2-subdev.h>
#include "cam_req_mgr_interface.h"
#include "cam_hw_mgr_intf.h"
#include "cam_smmu_api.h"
#include "cam_common_util.h"
/* Forward declarations */
struct cam_context;
/* max device name string length*/
#define CAM_CTX_DEV_NAME_MAX_LENGTH 20
/* max request number */
#define CAM_CTX_REQ_MAX 20
#define CAM_CTX_ICP_REQ_MAX 40
#define CAM_CTX_CFG_MAX 20
#define CAM_CTX_RES_MAX 20
/* max tag dump header string length*/
#define CAM_CTXT_DUMP_TAG_MAX_LEN 128
/* Number of words to be dumped for context*/
#define CAM_CTXT_DUMP_NUM_WORDS 10
/**
* enum cam_ctx_state - context top level states
*
*/
enum cam_context_state {
CAM_CTX_UNINIT = 0,
CAM_CTX_AVAILABLE = 1,
CAM_CTX_ACQUIRED = 2,
CAM_CTX_READY = 3,
CAM_CTX_FLUSHED = 4,
CAM_CTX_ACTIVATED = 5,
CAM_CTX_STATE_MAX = 6,
};
/**
* struct cam_ctx_request - Common request structure for the context
*
* @list: Link list entry
* @status: Request status
* @request_id: Request id
* @req_priv: Derived request object
* @hw_update_entries: Hardware update entries
* @num_hw_update_entries: Number of hardware update entries
* @in_map_entries: Entries for in fences
* @num_in_map_entries: Number of in map entries
* @out_map_entries: Entries for out fences
* @num_out_map_entries: Number of out map entries
* @num_in_acked: Number of in fence acked
* @num_out_acked: Number of out fence acked
* @index: Index of request in the list
* @flushed: Request is flushed
* @ctx: The context to which this request belongs
* @buf_tracker: List of buffers we want to keep ref counts on
* used by the HW block for a particular req
* @pf_data page fault debug data
*
*/
struct cam_ctx_request {
struct list_head list;
uint32_t status;
uint64_t request_id;
void *req_priv;
struct cam_hw_update_entry *hw_update_entries;
uint32_t num_hw_update_entries;
struct cam_hw_fence_map_entry *in_map_entries;
uint32_t num_in_map_entries;
struct cam_hw_fence_map_entry *out_map_entries;
uint32_t num_out_map_entries;
atomic_t num_in_acked;
uint32_t num_out_acked;
uint32_t index;
int flushed;
struct cam_context *ctx;
struct list_head buf_tracker;
struct cam_hw_mgr_pf_request_info pf_data;
};
/**
* struct cam_ctx_ioctl_ops - Function table for handling IOCTL calls
*
* @acquire_dev: Function pointer for acquire device
* @release_dev: Function pointer for release device
* @config_dev: Function pointer for config device
* @start_dev: Function pointer for start device
* @stop_dev: Function pointer for stop device
* @flush_dev: Function pointer for flush device
* @acquire_hw: Function pointer for acquire hw
* @release_hw: Function pointer for release hw
* @dump_dev: Function pointer for dump dev
*
*/
struct cam_ctx_ioctl_ops {
int (*acquire_dev)(struct cam_context *ctx,
struct cam_acquire_dev_cmd *cmd);
int (*release_dev)(struct cam_context *ctx,
struct cam_release_dev_cmd *cmd);
int (*config_dev)(struct cam_context *ctx,
struct cam_config_dev_cmd *cmd);
int (*start_dev)(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd);
int (*stop_dev)(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd);
int (*flush_dev)(struct cam_context *ctx,
struct cam_flush_dev_cmd *cmd);
int (*acquire_hw)(struct cam_context *ctx, void *args);
int (*release_hw)(struct cam_context *ctx, void *args);
int (*dump_dev)(struct cam_context *ctx,
struct cam_dump_req_cmd *cmd);
};
/**
* struct cam_ctx_crm_ops - Function table for handling CRM to context calls
*
* @get_dev_info: Get device informaiton
* @link: Link the context
* @unlink: Unlink the context
* @apply_req: Apply setting for the context
* @notify_frame_skip: Notify device that a frame is skipped
* @flush_req: Flush request to remove request ids
* @process_evt: Handle event notification from CRM.(optional)
* @dump_req: Dump information for the issue request
*
*/
struct cam_ctx_crm_ops {
int (*get_dev_info)(struct cam_context *ctx,
struct cam_req_mgr_device_info *device_info);
int (*link)(struct cam_context *ctx,
struct cam_req_mgr_core_dev_link_setup *link);
int (*unlink)(struct cam_context *ctx,
struct cam_req_mgr_core_dev_link_setup *unlink);
int (*apply_req)(struct cam_context *ctx,
struct cam_req_mgr_apply_request *apply);
int (*notify_frame_skip)(struct cam_context *ctx,
struct cam_req_mgr_apply_request *apply);
int (*flush_req)(struct cam_context *ctx,
struct cam_req_mgr_flush_request *flush);
int (*process_evt)(struct cam_context *ctx,
struct cam_req_mgr_link_evt_data *evt_data);
int (*dump_req)(struct cam_context *ctx,
struct cam_req_mgr_dump_info *dump);
};
/**
* struct cam_ctx_ops - Collection of the interface funciton tables
*
* @ioctl_ops: Ioctl funciton table
* @crm_ops: CRM to context interface function table
* @irq_ops: Hardware event handle function
* @pagefault_ops: Function to be called on page fault
* @dumpinfo_ops: Function to be invoked for dumping any
* context info
* @recovery_ops: Function to be invoked to try hardware recovery
* @mini_dump_ops: Function for mini dump
* @err_inject_ops: Function for error injection
* @msg_cb_ops: Function to be called on any message from
* other subdev notifications
*
*/
struct cam_ctx_ops {
struct cam_ctx_ioctl_ops ioctl_ops;
struct cam_ctx_crm_ops crm_ops;
cam_hw_event_cb_func irq_ops;
cam_hw_pagefault_cb_func pagefault_ops;
cam_ctx_info_dump_cb_func dumpinfo_ops;
cam_ctx_recovery_cb_func recovery_ops;
cam_ctx_mini_dump_cb_func mini_dump_ops;
cam_ctx_err_inject_cb_func evt_inject_ops;
cam_ctx_message_cb_func msg_cb_ops;
};
/**
* struct cam_context - camera context object for the subdevice node
*
* @dev_name: String giving name of device associated
* @dev_id: ID of device associated
* @ctx_id: ID for this context
* @list: Link list entry
* @sessoin_hdl: Session handle
* @dev_hdl: Device handle
* @link_hdl: Link handle
* @ctx_mutex: Mutex for ioctl calls
* @lock: Spin lock
* @active_req_list: Requests pending for done event
* @pending_req_list: Requests pending for reg upd event
* @wait_req_list: Requests waiting for apply
* @free_req_list: Requests that are free
* @req_list: Reference to the request storage
* @req_size: Size of the request storage
* @hw_mgr_intf: Context to HW interface
* @ctx_crm_intf: Context to CRM interface
* @crm_ctx_intf: CRM to context interface
* @irq_cb_intf: HW to context callback interface
* @state: Current state for top level state machine
* @state_machine: Top level state machine
* @ctx_priv: Private context pointer
* @ctxt_to_hw_map: Context to hardware mapping pointer
* @hw_mgr_ctx_id: Hw Mgr context id returned from hw mgr
* @ctx_id_string: Context id string constructed with dev type,
* ctx id, hw mgr ctx id, hw id
* @refcount: Context object refcount
* @node: The main node to which this context belongs
* @sync_mutex: mutex to sync with sync cb thread
* @last_flush_req: Last request to flush
* @max_hw_update_entries: Max hw update entries
* @max_in_map_entries: Max in map entries
* @max_out_map_entries: Max out in map entries
* @hw_updater_entry: Hw update entry
* @in_map_entries: In map update entry
* @out_map_entries: Out map entry
* @mini dump cb: Mini dump cb
* @img_iommu_hdl: Image IOMMU handle
* @cdm_done_ts: CDM callback done timestamp
*/
struct cam_context {
char dev_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
uint64_t dev_id;
uint32_t ctx_id;
struct list_head list;
int32_t session_hdl;
int32_t dev_hdl;
int32_t link_hdl;
struct mutex ctx_mutex;
spinlock_t lock;
struct list_head active_req_list;
struct list_head pending_req_list;
struct list_head wait_req_list;
struct list_head free_req_list;
struct cam_ctx_request *req_list;
uint32_t req_size;
struct cam_hw_mgr_intf *hw_mgr_intf;
struct cam_req_mgr_crm_cb *ctx_crm_intf;
struct cam_req_mgr_kmd_ops *crm_ctx_intf;
cam_hw_event_cb_func irq_cb_intf;
enum cam_context_state state;
struct cam_ctx_ops *state_machine;
void *ctx_priv;
void *ctxt_to_hw_map;
uint32_t hw_mgr_ctx_id;
char ctx_id_string[128];
struct kref refcount;
void *node;
struct mutex sync_mutex;
uint32_t last_flush_req;
uint32_t max_hw_update_entries;
uint32_t max_in_map_entries;
uint32_t max_out_map_entries;
struct cam_hw_update_entry **hw_update_entry;
struct cam_hw_fence_map_entry **in_map_entries;
struct cam_hw_fence_map_entry **out_map_entries;
cam_ctx_mini_dump_cb_func mini_dump_cb;
int img_iommu_hdl;
struct timespec64 cdm_done_ts;
};
/**
* struct cam_context_stream_dump - camera context stream information
*
* @hw_mgr_ctx_id: Hw Mgr context id returned from hw mgr
* @dev_id: ID of device associated
* @dev_hdl: Device handle
* @link_hdl: Link handle
* @sessoin_hdl: Session handle
* @refcount: Context object refcount
* @last_flush_req: Last request to flush
* @state: Current state for top level state machine
*/
struct cam_context_stream_dump {
uint32_t hw_mgr_ctx_id;
uint32_t dev_id;
uint32_t dev_hdl;
uint32_t link_hdl;
uint32_t session_hdl;
uint32_t refcount;
uint32_t last_flush_req;
enum cam_context_state state;
};
/**
* struct cam_context_each_req_info - camera each request information
*
* @request_id: request id
*/
struct cam_context_each_req_info {
uint64_t request_id;
};
/**
* struct cam_context_dump_header - Function for context dump header
*
* @tag : Tag for context dump header
* @size : Size of data
* @word_size : Word size of data
*/
struct cam_context_dump_header {
uint8_t tag[CAM_CTXT_DUMP_TAG_MAX_LEN];
uint64_t size;
uint32_t word_size;
};
/**
* cam_context_shutdown()
*
* @brief: Calls while device close or shutdown
*
* @ctx: Object pointer for cam_context
*
*/
int cam_context_shutdown(struct cam_context *ctx);
/**
* cam_context_handle_crm_get_dev_info()
*
* @brief: Handle get device information command
*
* @ctx: Object pointer for cam_context
* @info: Device information returned
*
*/
int cam_context_handle_crm_get_dev_info(struct cam_context *ctx,
struct cam_req_mgr_device_info *info);
/**
* cam_context_handle_crm_link()
*
* @brief: Handle link command
*
* @ctx: Object pointer for cam_context
* @link: Link command payload
*
*/
int cam_context_handle_crm_link(struct cam_context *ctx,
struct cam_req_mgr_core_dev_link_setup *link);
/**
* cam_context_handle_crm_unlink()
*
* @brief: Handle unlink command
*
* @ctx: Object pointer for cam_context
* @unlink: Unlink command payload
*
*/
int cam_context_handle_crm_unlink(struct cam_context *ctx,
struct cam_req_mgr_core_dev_link_setup *unlink);
/**
* cam_context_handle_crm_apply_req()
*
* @brief: Handle apply request command
*
* @ctx: Object pointer for cam_context
* @apply: Apply request command payload
*
*/
int cam_context_handle_crm_apply_req(struct cam_context *ctx,
struct cam_req_mgr_apply_request *apply);
/**
* cam_context_handle_crm_notify_frame_skip()
*
* @brief: Handle notify frame skip command
*
* @ctx: Object pointer for cam_context
* @apply: Notify frame skip command payload
*
*/
int cam_context_handle_crm_notify_frame_skip(
struct cam_context *ctx, struct cam_req_mgr_apply_request *apply);
/**
* cam_context_handle_crm_flush_req()
*
* @brief: Handle flush request command
*
* @ctx: Object pointer for cam_context
* @apply: Flush request command payload
*
*/
int cam_context_handle_crm_flush_req(struct cam_context *ctx,
struct cam_req_mgr_flush_request *apply);
/**
* cam_context_handle_crm_process_evt()
*
* @brief: Handle process event command
*
* @ctx: Object pointer for cam_context
* @process_evt: process event command payload
*
*/
int cam_context_handle_crm_process_evt(struct cam_context *ctx,
struct cam_req_mgr_link_evt_data *process_evt);
/**
* cam_context_handle_crm_dump_req()
*
* @brief: Handle CRM dump request
*
* @ctx: Object pointer for cam_context
* @dump: Dump request command payload
*
*/
int cam_context_handle_crm_dump_req(struct cam_context *ctx,
struct cam_req_mgr_dump_info *dump);
/**
* cam_context_mini_dump_from_hw()
*
* @brief: Handle mini dump request command
*
* @ctx: Object pointer for cam_context
* @args: Args to be passed
*
*/
int cam_context_mini_dump_from_hw(struct cam_context *ctx,
void *args);
/**
* cam_context_dump_pf_info()
*
* @brief: Handle dump active request request command
*
* @ctx: Object pointer for cam_context
* @pf_args: pf args to dump pf info to hw
*
*/
int cam_context_dump_pf_info(void *ctx,
void *pf_args);
/**
* cam_context_handle_message()
*
* @brief: Handle message callback command
*
* @ctx: Object pointer for cam_context
* @msg_type: message type sent from other subdev
* @data: data from other subdev
*
*/
int cam_context_handle_message(struct cam_context *ctx,
uint32_t msg_type, void *data);
/**
* cam_context_handle_acquire_dev()
*
* @brief: Handle acquire device command
*
* @ctx: Object pointer for cam_context
* @cmd: Acquire device command payload
*
*/
int cam_context_handle_acquire_dev(struct cam_context *ctx,
struct cam_acquire_dev_cmd *cmd);
/**
* cam_context_handle_acquire_hw()
*
* @brief: Handle acquire HW command
*
* @ctx: Object pointer for cam_context
* @cmd: Acquire HW command payload
*
*/
int cam_context_handle_acquire_hw(struct cam_context *ctx,
void *cmd);
/**
* cam_context_handle_release_dev()
*
* @brief: Handle release device command
*
* @ctx: Object pointer for cam_context
* @cmd: Release device command payload
*
*/
int cam_context_handle_release_dev(struct cam_context *ctx,
struct cam_release_dev_cmd *cmd);
/**
* cam_context_handle_release_hw()
*
* @brief: Handle release HW command
*
* @ctx: Object pointer for cam_context
* @cmd: Release HW command payload
*
*/
int cam_context_handle_release_hw(struct cam_context *ctx,
void *cmd);
/**
* cam_context_handle_config_dev()
*
* @brief: Handle config device command
*
* @ctx: Object pointer for cam_context
* @cmd: Config device command payload
*
*/
int cam_context_handle_config_dev(struct cam_context *ctx,
struct cam_config_dev_cmd *cmd);
/**
* cam_context_handle_flush_dev()
*
* @brief: Handle flush device command
*
* @ctx: Object pointer for cam_context
* @cmd: Flush device command payload
*
*/
int cam_context_handle_flush_dev(struct cam_context *ctx,
struct cam_flush_dev_cmd *cmd);
/**
* cam_context_handle_start_dev()
*
* @brief: Handle start device command
*
* @ctx: Object pointer for cam_context
* @cmd: Start device command payload
*
*/
int cam_context_handle_start_dev(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd);
/**
* cam_context_handle_stop_dev()
*
* @brief: Handle stop device command
*
* @ctx: Object pointer for cam_context
* @cmd: Stop device command payload
*
*/
int cam_context_handle_stop_dev(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd);
/**
* cam_context_handle_dump_dev()
*
* @brief: Handle dump device command
*
* @ctx: Object pointer for cam_context
* @cmd: Dump device command payload
*
*/
int cam_context_handle_dump_dev(struct cam_context *ctx,
struct cam_dump_req_cmd *cmd);
/**
* cam_context_handle_info_dump()
*
* @brief: Handle any dump info for the context
*
* @ctx: Object pointer for cam_context
* @id: To indicate which info pertaining
* to that ctx needs to be dumped
*
*/
int cam_context_handle_info_dump(void *context,
enum cam_context_dump_id id);
/**
* cam_context_handle_hw_recovery()
*
* @brief: Handle hardware recovery. This function can be scheduled in
* cam_req_mgr_workq.
*
* @context: Object pointer for cam_context
* @data: Recovery data that is to be passsed to hw mgr
*
*/
int cam_context_handle_hw_recovery(void *context, void *data);
/**
* cam_context_deinit()
*
* @brief: Camera context deinitialize function
*
* @ctx: Object pointer for cam_context
*
*/
int cam_context_deinit(struct cam_context *ctx);
/**
* cam_context_init()
*
* @brief: Camera context initialize function
*
* @ctx: Object pointer for cam_context
* @dev_name: String giving name of device associated
* @dev_id: ID of the device associated
* @ctx_id: ID for this context
* @crm_node_intf: Function table for crm to context interface
* @hw_mgr_intf: Function table for context to hw interface
* @req_list: Requests storage
* @req_size: Size of the request storage
* @img_iommu_hdl: IOMMU Handle for image buffers
*
*/
int cam_context_init(struct cam_context *ctx,
const char *dev_name,
uint64_t dev_id,
uint32_t ctx_id,
struct cam_req_mgr_kmd_ops *crm_node_intf,
struct cam_hw_mgr_intf *hw_mgr_intf,
struct cam_ctx_request *req_list,
uint32_t req_size, int img_iommu_hdl);
/**
* cam_context_putref()
*
* @brief: Put back context reference.
*
* @ctx: Context for which ref is returned
*
*/
void cam_context_putref(struct cam_context *ctx);
/**
* cam_context_getref()
*
* @brief: Get back context reference.
*
* @ctx: Context for which ref is taken
*
*/
void cam_context_getref(struct cam_context *ctx);
/**
* cam_context_add_evt_inject()
*
* @brief: Add error inject parameters through evt_inject_ops.
*
* @ctx: Context for which error is to be injected
*
* @inject_args: Event injection parameters
*
*/
int cam_context_add_evt_inject(struct cam_context *ctx,
void *inject_args);
#endif /* _CAM_CONTEXT_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CONTEXT_UTILS_H_
#define _CAM_CONTEXT_UTILS_H_
#include <linux/types.h>
#include "cam_smmu_api.h"
/**
* struct cam_context_utils_flush_args - arguments for flush context util
*
* @cmd: flush dev command from userland
* @flush_active_req: flag to indicate if the device supports flushing a particular
* active request or not
*/
struct cam_context_utils_flush_args {
struct cam_flush_dev_cmd *cmd;
bool flush_active_req;
};
int cam_context_buf_done_from_hw(struct cam_context *ctx,
void *done_event_data, uint32_t evt_id);
int32_t cam_context_release_dev_to_hw(struct cam_context *ctx,
struct cam_release_dev_cmd *cmd);
int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx,
struct cam_config_dev_cmd *cmd);
int32_t cam_context_config_dev_to_hw(
struct cam_context *ctx, struct cam_config_dev_cmd *cmd);
int32_t cam_context_acquire_dev_to_hw(struct cam_context *ctx,
struct cam_acquire_dev_cmd *cmd);
int32_t cam_context_start_dev_to_hw(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd);
int32_t cam_context_stop_dev_to_hw(struct cam_context *ctx);
int32_t cam_context_flush_dev_to_hw(struct cam_context *ctx,
struct cam_context_utils_flush_args *args);
int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx);
int32_t cam_context_flush_req_to_hw(struct cam_context *ctx,
struct cam_context_utils_flush_args *args);
int32_t cam_context_send_pf_evt(struct cam_context *ctx,
struct cam_hw_dump_pf_args *pf_args);
int32_t cam_context_dump_pf_info_to_hw(struct cam_context *ctx,
struct cam_hw_dump_pf_args *pf_args,
struct cam_hw_mgr_pf_request_info *pf_req_info);
int32_t cam_context_dump_hw_acq_info(struct cam_context *ctx);
int32_t cam_context_dump_dev_to_hw(struct cam_context *ctx,
struct cam_dump_req_cmd *cmd);
size_t cam_context_parse_config_cmd(struct cam_context *ctx, struct cam_config_dev_cmd *cmd,
struct cam_packet **packet);
int cam_context_mini_dump(struct cam_context *ctx, void *args);
int cam_context_apply_evt_injection(struct cam_context *ctx, void *inject_evt_arg);
#endif /* _CAM_CONTEXT_UTILS_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2018, 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_HW_H_
#define _CAM_HW_H_
#include "cam_soc_util.h"
/*
* This file declares Enums, Structures and APIs to be used as template
* when writing any HW driver in the camera subsystem.
*/
/* Hardware state enum */
enum cam_hw_state {
CAM_HW_STATE_POWER_DOWN,
CAM_HW_STATE_POWER_UP,
};
/**
* struct cam_hw_info - Common hardware information
*
* @hw_mutex: Hardware mutex
* @hw_lock: Hardware spinlock
* @hw_complete: Hardware Completion
* @open_count: Count to track the HW enable from the client
* @hw_state: Hardware state
* @soc_info: Platform SOC properties for hardware
* @node_info: Private HW data related to nodes
* @core_info: Private HW data related to core logic
* @presil_hw_lock: Mutex lock used for presil in place of hw_lock,
* for drivers like CDM
*
*/
struct cam_hw_info {
struct mutex hw_mutex;
spinlock_t hw_lock;
struct completion hw_complete;
uint32_t open_count;
enum cam_hw_state hw_state;
struct cam_hw_soc_info soc_info;
void *node_info;
void *core_info;
#ifdef CONFIG_CAM_PRESIL
struct mutex presil_hw_lock;
#endif
};
#endif /* _CAM_HW_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_HW_INTF_H_
#define _CAM_HW_INTF_H_
#include <linux/types.h>
#include "cam_hw.h"
/*
* This file declares Constants, Enums, Structures and APIs to be used as
* Interface between HW driver and HW Manager.
*/
#define CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ 6
enum cam_clk_bw_state {
CAM_CLK_BW_STATE_INIT,
CAM_CLK_BW_STATE_UNCHANGED,
CAM_CLK_BW_STATE_INCREASE,
CAM_CLK_BW_STATE_DECREASE,
};
/**
* struct cam_hw_ops - Hardware layer interface functions
*
* @get_hw_caps: Function pointer for get hw caps
* @init: Function poniter for initialize hardware
* @deinit: Function pointer for deinitialize hardware
* @reset: Function pointer for reset hardware
* @reserve: Function pointer for reserve hardware
* @release: Function pointer for release hardware
* @start: Function pointer for start hardware
* @stop: Function pointer for stop hardware
* @read: Function pointer for read hardware registers
* @write: Function pointer for Write hardware registers
* @process_cmd: Function pointer for additional hardware controls
* @flush_cmd: Function pointer for flush requests
* @test_irq_line: Function pointer for testing irq line
*
*/
struct cam_hw_ops {
int (*get_hw_caps)(void *hw_priv,
void *get_hw_cap_args, uint32_t arg_size);
int (*init)(void *hw_priv,
void *init_hw_args, uint32_t arg_size);
int (*deinit)(void *hw_priv,
void *init_hw_args, uint32_t arg_size);
int (*reset)(void *hw_priv,
void *reset_core_args, uint32_t arg_size);
int (*reserve)(void *hw_priv,
void *reserve_args, uint32_t arg_size);
int (*release)(void *hw_priv,
void *release_args, uint32_t arg_size);
int (*start)(void *hw_priv,
void *start_args, uint32_t arg_size);
int (*stop)(void *hw_priv,
void *stop_args, uint32_t arg_size);
int (*read)(void *hw_priv,
void *read_args, uint32_t arg_size);
int (*write)(void *hw_priv,
void *write_args, uint32_t arg_size);
int (*process_cmd)(void *hw_priv,
uint32_t cmd_type, void *cmd_args, uint32_t arg_size);
int (*flush)(void *hw_priv,
void *flush_args, uint32_t arg_size);
int (*test_irq_line)(void *hw_priv);
};
/**
* struct cam_hw_intf - Common hardware node
*
* @hw_type: Hardware type
* @hw_idx: Hardware ID
* @hw_ops: Hardware interface function table
* @hw_priv: Private hardware node pointer
*
*/
struct cam_hw_intf {
uint32_t hw_type;
uint32_t hw_idx;
struct cam_hw_ops hw_ops;
void *hw_priv;
};
/* hardware event callback function type */
typedef int (*cam_hw_mgr_event_cb_func)(void *priv, uint32_t evt_id,
void *evt_data);
#ifdef CONFIG_CAM_PRESIL
static inline void cam_hw_util_init_hw_lock(struct cam_hw_info *hw_info)
{
mutex_init(&hw_info->presil_hw_lock);
}
static inline unsigned long cam_hw_util_hw_lock_irqsave(struct cam_hw_info *hw_info)
{
mutex_lock(&hw_info->presil_hw_lock);
return 0;
}
static inline void cam_hw_util_hw_unlock_irqrestore(struct cam_hw_info *hw_info,
unsigned long flags)
{
mutex_unlock(&hw_info->presil_hw_lock);
}
static inline void cam_hw_util_hw_lock(struct cam_hw_info *hw_info)
{
mutex_lock(&hw_info->presil_hw_lock);
}
static inline void cam_hw_util_hw_unlock(struct cam_hw_info *hw_info)
{
mutex_unlock(&hw_info->presil_hw_lock);
}
#else
static inline void cam_hw_util_init_hw_lock(struct cam_hw_info *hw_info)
{
spin_lock_init(&hw_info->hw_lock);
}
static inline unsigned long cam_hw_util_hw_lock_irqsave(struct cam_hw_info *hw_info)
{
unsigned long flags = 0;
if (!in_irq())
spin_lock_irqsave(&hw_info->hw_lock, flags);
return flags;
}
static inline void cam_hw_util_hw_unlock_irqrestore(struct cam_hw_info *hw_info,
unsigned long flags)
{
if (!in_irq())
spin_unlock_irqrestore(&hw_info->hw_lock, flags);
}
static inline void cam_hw_util_hw_lock(struct cam_hw_info *hw_info)
{
spin_lock(&hw_info->hw_lock);
}
static inline void cam_hw_util_hw_unlock(struct cam_hw_info *hw_info)
{
spin_unlock(&hw_info->hw_lock);
}
#endif /* CONFIG_CAM_PRESIL */
#endif /* _CAM_HW_INTF_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_HW_MGR_INTF_H_
#define _CAM_HW_MGR_INTF_H_
#include <linux/time64.h>
#include <linux/types.h>
#include <media/cam_defs.h>
#include "cam_smmu_api.h"
/*
* This file declares Constants, Enums, Structures and APIs to be used as
* Interface between HW Manager and Context.
*/
/* maximum context numbers */
#define CAM_CTX_MAX 8
/* maximum buf done irqs */
#define CAM_NUM_OUT_PER_COMP_IRQ_MAX 12
/* Maximum reg dump cmd buffer entries in a context */
#define CAM_REG_DUMP_MAX_BUF_ENTRIES 10
/* max device name string length*/
#define CAM_HW_MINI_DUMP_DEV_NAME_LEN 20
/**
* enum cam_context_dump_id -
* context dump type
*
*/
enum cam_context_dump_id {
CAM_CTX_DUMP_TYPE_NONE,
CAM_CTX_DUMP_ACQ_INFO,
CAM_CTX_DUMP_TYPE_MAX,
};
/**
* enum cam_faulted_mem_type -
* page fault buffer type found in packet
*
*/
enum cam_faulted_mem_type {
CAM_FAULT_BUF_NOT_FOUND,
CAM_FAULT_IO_CFG_BUF,
CAM_FAULT_PATCH_BUF
};
#define CAM_CTX_EVT_ID_SUCCESS 0
#define CAM_CTX_EVT_ID_ERROR 1
#define CAM_CTX_EVT_ID_CANCEL 2
/* hardware event callback function type */
typedef int (*cam_hw_event_cb_func)(void *context, uint32_t evt_id,
void *evt_data);
/* hardware page fault callback function type */
typedef int (*cam_hw_pagefault_cb_func)(void *context,
void *pf_args);
/* ctx dump callback function type */
typedef int (*cam_ctx_info_dump_cb_func)(void *context,
enum cam_context_dump_id dump_id);
/* ctx recovery callback function type */
typedef int (*cam_ctx_recovery_cb_func)(void *context,
void *recovery_data);
/* ctx mini dump callback function type */
typedef int (*cam_ctx_mini_dump_cb_func)(void *context,
void *args);
/* ctx error inject callback function type */
typedef int (*cam_ctx_err_inject_cb_func)(void *context,
void *args);
/* message callback function type */
typedef int (*cam_ctx_message_cb_func)(void *context,
uint32_t message_type, void *data);
/**
* struct cam_hw_update_entry - Entry for hardware config
*
* @handle: Memory handle for the configuration
* @offset: Memory offset
* @len: Size of the configuration
* @flags: Flags for the config entry(eg. DMI)
* @addr: Address of hardware update entry
*
*/
struct cam_hw_update_entry {
int handle;
uint32_t offset;
uint32_t len;
uint32_t flags;
uintptr_t addr;
};
/**
* struct cam_hw_fence_map_entry - Entry for the resource to sync id map
*
* @resrouce_handle: Resource port id for the buffer
* @sync_id: Sync id
* @image_buf_addr: Image buffer address array
* @buffer_tracker: Some buffers with fences have buf dones come
* separately from each out port, and signalled
* independently. Ref counting needs to be handled
* independently as well corresponding to individual
* buf dones.
*
*/
struct cam_hw_fence_map_entry {
uint32_t resource_handle;
int32_t sync_id;
dma_addr_t image_buf_addr[CAM_PACKET_MAX_PLANES];
struct cam_smmu_buffer_tracker *buffer_tracker;
};
/**
* struct cam_hw_done_event_data - Payload for hw done event
*
* @num_handles: number of handles in the event
* @resrouce_handle: list of the resource handle
* @timestamp: time stamp
* @request_id: request identifier
* @evt_param: event parameter
*
*/
struct cam_hw_done_event_data {
uint32_t num_handles;
uint32_t resource_handle[CAM_NUM_OUT_PER_COMP_IRQ_MAX];
struct timespec64 timestamp;
uint64_t request_id;
uint32_t evt_param;
};
/**
* struct cam_hw_acquire_stream_caps - Any HW caps info from HW mgr to ctx
* Params to be interpreted by the
* respective drivers
* @num_valid_params : Number of valid params
* @param_list : List of params interpreted by the driver
*
*/
struct cam_hw_acquire_stream_caps {
uint32_t num_valid_params;
uint32_t param_list[4];
};
/**
* struct cam_hw_acquire_args - Payload for acquire command
*
* @context_data: Context data pointer for the callback function
* @ctx_id: Core context id
* @event_cb: Callback function array
* @sec_pf_evt_cb: Callback function for secondary page fault from HW to ctx.
* It's the callback that pertains to a PF not directly on
* this HW. But a different block to which this HW is
* associated or is a client of
* @num_acq: Total number of acquire in the payload
* @acquire_info: Acquired resource array pointer
* @ctxt_to_hw_map: HW context (returned)
* @hw_mgr_ctx_id HWMgr context id(returned)
* @op_flags: Used as bitwise params from hw_mgr to ctx
* See xxx_hw_mgr_intf.h for definitions
* @link_hdl: Link handle
* @acquired_hw_id: Acquired hardware mask
* @acquired_hw_path: Acquired path mask for an input
* if input splits into multiple paths,
* its updated per hardware
* @valid_acquired_hw: Valid num of acquired hardware
* @total_ports_acq Total ports acquired ipp+ppp+rdi
* @op_params: OP Params from hw_mgr to ctx
* @mini_dump_cb: Mini dump callback function
*
*/
struct cam_hw_acquire_args {
void *context_data;
uint32_t ctx_id;
cam_hw_event_cb_func event_cb;
cam_hw_pagefault_cb_func sec_pf_evt_cb;
uint32_t num_acq;
uint32_t acquire_info_size;
uintptr_t acquire_info;
void *ctxt_to_hw_map;
uint32_t hw_mgr_ctx_id;
uint32_t op_flags;
int32_t link_hdl;
uint32_t acquired_hw_id[CAM_MAX_ACQ_RES];
uint32_t acquired_hw_path[CAM_MAX_ACQ_RES][CAM_MAX_HW_SPLIT];
uint32_t valid_acquired_hw;
uint32_t total_ports_acq;
struct cam_hw_acquire_stream_caps op_params;
cam_ctx_mini_dump_cb_func mini_dump_cb;
};
/**
* struct cam_hw_release_args - Payload for release command
*
* @ctxt_to_hw_map: HW context from the acquire
* @active_req: Active request flag
*
*/
struct cam_hw_release_args {
void *ctxt_to_hw_map;
bool active_req;
};
/**
* struct cam_hw_start_args - Payload for start command
*
* @ctxt_to_hw_map: HW context from the acquire
* @num_hw_update_entries: Number of Hardware configuration
* @hw_update_entries: Hardware configuration list
*
*/
struct cam_hw_start_args {
void *ctxt_to_hw_map;
uint32_t num_hw_update_entries;
struct cam_hw_update_entry *hw_update_entries;
};
/**
* struct cam_hw_stop_args - Payload for stop command
*
* @ctxt_to_hw_map: HW context from the acquire
* @args: Arguments to pass for stop
*
*/
struct cam_hw_stop_args {
void *ctxt_to_hw_map;
void *args;
};
/**
* struct cam_hw_mgr_pf_request_info - page fault debug data
*
* @packet_handle: packet handle
* @offset: packet offset
* @req: pointer to req (HW specific)
*/
struct cam_hw_mgr_pf_request_info {
uint64_t packet_handle;
uint64_t packet_offset;
void *req;
};
/**
* struct cam_hw_prepare_update_args - Payload for prepare command
*
* @packet: CSL packet from user mode driver
* @remain_len Remaining length of CPU buffer after config offset
* @ctxt_to_hw_map: HW context from the acquire
* @max_hw_update_entries: Maximum hardware update entries supported
* @hw_update_entries: Actual hardware update configuration (returned)
* @num_hw_update_entries: Number of actual hardware update entries (returned)
* @max_out_map_entries: Maximum output fence mapping supported
* @out_map_entries: Actual output fence mapping list (returned)
* @num_out_map_entries: Number of actual output fence mapping (returned)
* @max_in_map_entries: Maximum input fence mapping supported
* @in_map_entries: Actual input fence mapping list (returned)
* @num_in_map_entries: Number of acutal input fence mapping (returned)
* @reg_dump_buf_desc: cmd buffer descriptors for reg dump
* @num_reg_dump_buf: Count of descriptors in reg_dump_buf_desc
* @priv: Private pointer of hw update
* @buf_tracker: Ptr to list of buffers we want to keep ref counts on
* @pf_data: Debug data for page fault
*
*/
struct cam_hw_prepare_update_args {
struct cam_packet *packet;
size_t remain_len;
void *ctxt_to_hw_map;
uint32_t max_hw_update_entries;
struct cam_hw_update_entry *hw_update_entries;
uint32_t num_hw_update_entries;
uint32_t max_out_map_entries;
struct cam_hw_fence_map_entry *out_map_entries;
uint32_t num_out_map_entries;
uint32_t max_in_map_entries;
struct cam_hw_fence_map_entry *in_map_entries;
uint32_t num_in_map_entries;
struct cam_cmd_buf_desc reg_dump_buf_desc[
CAM_REG_DUMP_MAX_BUF_ENTRIES];
uint32_t num_reg_dump_buf;
void *priv;
struct list_head *buf_tracker;
struct cam_hw_mgr_pf_request_info *pf_data;
};
/**
* struct cam_hw_stream_setttings - Payload for config stream command
*
* @packet: CSL packet from user mode driver
* @ctxt_to_hw_map: HW context from the acquire
* @priv: Private pointer of hw update
*
*/
struct cam_hw_stream_setttings {
struct cam_packet *packet;
void *ctxt_to_hw_map;
void *priv;
};
/**
* enum cam_hw_config_reapply_type
*/
enum cam_hw_config_reapply_type {
CAM_CONFIG_REAPPLY_NONE,
CAM_CONFIG_REAPPLY_IQ,
CAM_CONFIG_REAPPLY_IO,
};
/**
* struct cam_hw_config_args - Payload for config command
*
* @ctxt_to_hw_map: HW context from the acquire
* @num_hw_update_entries: Number of hardware update entries
* @hw_update_entries: Hardware update list
* @out_map_entries: Out map info
* @num_out_map_entries: Number of out map entries
* @priv: Private pointer
* @request_id: Request ID
* @reapply_type: On reapply determines what is to be applied
* @init_packet: Set if INIT packet
* @cdm_reset_before_apply: True is need to reset CDM before re-apply bubble
* request
*
*/
struct cam_hw_config_args {
void *ctxt_to_hw_map;
uint32_t num_hw_update_entries;
struct cam_hw_update_entry *hw_update_entries;
struct cam_hw_fence_map_entry *out_map_entries;
uint32_t num_out_map_entries;
void *priv;
uint64_t request_id;
enum cam_hw_config_reapply_type reapply_type;
bool init_packet;
bool cdm_reset_before_apply;
};
/**
* struct cam_hw_flush_args - Flush arguments
*
* @ctxt_to_hw_map: HW context from the acquire
* @num_req_pending: Num request to flush, valid when flush type is REQ
* @flush_req_pending: Request pending pointers to flush
* @num_req_active: Num request to flush, valid when flush type is REQ
* @flush_req_active: Request active pointers to flush
* @flush_type: The flush type
* @last_flush_req: last flush req_id notified to hw_mgr for the
* given stream
*
*/
struct cam_hw_flush_args {
void *ctxt_to_hw_map;
uint32_t num_req_pending;
void **flush_req_pending;
uint32_t num_req_active;
void **flush_req_active;
enum flush_type_t flush_type;
uint32_t last_flush_req;
};
/**
* struct cam_context_pf_info - Page Fault related info to the faulted context
*
* @mem_type: Faulted memory type found in packet
* @resource_type: Resource type of the port which caused page fault
* @buf_hdl: Faulted memory handle
* @offset: Offset for faulted buf_hdl
* @req_id: request id for the faulted request
* @delta: Delta size between faulted address and buffer
* Or closest-mapped buffer
* (if faulted addr isn't found to be in any buffer)
* @patch_idx: Index to which patch in the packet is faulted
* @mem_flag: Memory flag of the faulted buffer
* @ctx_found: If fault pid found in context acquired hardware
* @force_send_pf_evt: Must send page fault notification to UMD even if
* current ctx is not the faulted ctx
*/
struct cam_context_pf_info {
enum cam_faulted_mem_type mem_type;
uint32_t resource_type;
int32_t buf_hdl;
uint32_t offset;
unsigned long delta;
uint32_t patch_idx;
uint32_t mem_flag;
uint64_t req_id;
bool ctx_found;
bool force_send_pf_evt;
};
/**
* struct cam_hw_dump_pf_args - General payload contains all PF relateed info.
*
* @pf_smmu_info: Page fault info from SMMU driver
* @pf_context_info: Page fault info related to faulted context or
* faulted request.
* @handle_sec_pf: Indicates if this PF args comes from HW level
*/
struct cam_hw_dump_pf_args {
struct cam_smmu_pf_info *pf_smmu_info;
struct cam_context_pf_info pf_context_info;
bool handle_sec_pf;
};
/**
* struct cam_hw_cmd_pf_args - page fault command payload to hw manager.
* @pf_args: Page Fault related info.
* @cmd_pf_req_info: Command payload related to request info. Used to
* submit to HW for PF processing.
*
*/
struct cam_hw_cmd_pf_args {
struct cam_hw_dump_pf_args *pf_args;
struct cam_hw_mgr_pf_request_info *pf_req_info;
};
/**
* struct cam_hw_reset_args -hw reset arguments
*
* @ctxt_to_hw_map: HW context from the acquire
*
*/
struct cam_hw_reset_args {
void *ctxt_to_hw_map;
};
/**
* struct cam_hw_dump_args - Dump arguments
*
* @request_id: request_id
* @offset: Buffer offset. This is updated by the drivers.
* @buf_handle: Buffer handle
* @error_type: Error type, to be used to extend dump information
* @ctxt_to_hw_map: HW context from the acquire
*/
struct cam_hw_dump_args {
uint64_t request_id;
size_t offset;
uint32_t buf_handle;
uint32_t error_type;
void *ctxt_to_hw_map;
};
/* enum cam_hw_mgr_command - Hardware manager command type */
enum cam_hw_mgr_command {
CAM_HW_MGR_CMD_INTERNAL,
CAM_HW_MGR_CMD_DUMP_PF_INFO,
CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH,
CAM_HW_MGR_CMD_REG_DUMP_ON_ERROR,
CAM_HW_MGR_CMD_DUMP_ACQ_INFO,
};
/**
* struct cam_hw_cmd_args - Payload for hw manager command
*
* @ctxt_to_hw_map: HW context from the acquire
* @cmd_type HW command type
* @internal_args Arguments for internal command
* @pf_cmd_args Arguments for Dump PF info command
*
*/
struct cam_hw_cmd_args {
void *ctxt_to_hw_map;
uint32_t cmd_type;
union {
void *internal_args;
struct cam_hw_cmd_pf_args *pf_cmd_args;
} u;
};
/**
* struct cam_hw_mini_dump_args - Mini Dump arguments
*
* @start_addr: Start address of buffer
* @len: Len of Buffer
* @bytes_written: Bytes written
*/
struct cam_hw_mini_dump_args {
void *start_addr;
unsigned long len;
unsigned long bytes_written;
};
/**
* struct cam_hw_req_mini_dump - Mini dump context req
*
* @fence_map_out: Fence map out array
* @fence_map_in: Fence map in array
* @io_cfg: IO cfg.
* @request_id: Request id
* @num_fence_map_in: num of fence map in
* @num_fence_map_in: num of fence map out
* @num_io_cfg: num of io cfg
* @num_in_acked: num in acked
* @num_out_acked: num out acked
* @status: Status
* @flushed: whether request is flushed
*
*/
struct cam_hw_req_mini_dump {
struct cam_hw_fence_map_entry *fence_map_out;
struct cam_hw_fence_map_entry *fence_map_in;
struct cam_buf_io_cfg *io_cfg;
uint64_t request_id;
uint16_t num_fence_map_in;
uint16_t num_fence_map_out;
uint16_t num_io_cfg;
uint16_t num_in_acked;
uint16_t num_out_acked;
uint8_t status;
uint8_t flushed;
};
/**
* struct cam_hw_mini_dump_info - Mini dump context info
*
* @active_list: array of active req in context
* @wait_list: array of wait req in context
* @pending_list: array of pending req in context
* @name: name of context
* @dev_id: dev id.
* @last_flush_req: last flushed request id
* @refcount: kernel ref count
* @ctx_id: Context id
* @session_hdl: Session handle
* @link_hdl: link handle
* @dev_hdl: Dev hdl
* @state: State of context
* @hw_mgr_ctx_id: ctx id with hw mgr
*
*/
struct cam_hw_mini_dump_info {
struct cam_hw_req_mini_dump *active_list;
struct cam_hw_req_mini_dump *wait_list;
struct cam_hw_req_mini_dump *pending_list;
char name[CAM_HW_MINI_DUMP_DEV_NAME_LEN];
uint64_t dev_id;
uint32_t last_flush_req;
uint32_t refcount;
uint32_t ctx_id;
uint32_t active_cnt;
uint32_t pending_cnt;
uint32_t wait_cnt;
int32_t session_hdl;
int32_t link_hdl;
int32_t dev_hdl;
uint8_t state;
uint8_t hw_mgr_ctx_id;
};
/**
* cam_hw_inject_err_evt_param - error evt injection parameters
*
* @err_type: error type for the injected err evt
* @err_code: error code for the injected err evt
*/
struct cam_hw_inject_err_evt_param {
uint32_t err_type;
uint32_t err_code;
};
/**
* cam_hw_inject_node_evt_param - node evt injection parameters
* @event_type: event type for the injected node evt
* @event_cause: event cause for the injected node evt
*/
struct cam_hw_inject_node_evt_param {
uint32_t event_type;
uint32_t event_cause;
};
/**
* cam_hw_inject_pf_evt_param - pf evt injection parameters
*
* @ctx_found: flag to indicate if page fault notification sent with ctx or not
*/
struct cam_hw_inject_pf_evt_param {
bool ctx_found;
};
/**
* cam_hw_inject_evt_notification_param - notify event parameters
*
* @evt_notify_type: type of event notification
* @u: union which can be either error event/Page Fault event/Node event
*/
struct cam_hw_inject_evt_notification_param {
uint32_t evt_notify_type;
union {
struct cam_hw_inject_err_evt_param err_evt_params;
struct cam_hw_inject_pf_evt_param pf_evt_params;
struct cam_hw_inject_node_evt_param node_evt_params;
} u;
};
/**
* cam_hw_inject_buffer_error_param - buffer error injection parameters
*
* @sync_error: sync error code
*/
struct cam_hw_inject_buffer_error_param {
uint32_t sync_error;
};
/**
* cam_hw_inject_evt_param - CRM event injection parameters
*
* @inject_id: generic inject identifier
* @req_id: Req Id for which the event is injected
* @u: union which can be either buffer done error/event notification
* @is_valid: bool flag to indicate if event injection is enabled for a context
*/
struct cam_hw_inject_evt_param {
uint8_t inject_id;
uint64_t req_id;
union {
struct cam_hw_inject_buffer_error_param buf_err_evt;
struct cam_hw_inject_evt_notification_param evt_notify;
} u;
bool is_valid;
};
/**
* cam_hw_mgr_intf - HW manager interface
*
* @hw_mgr_priv: HW manager object
* @hw_get_caps: Function pointer for get hw caps
* args = cam_query_cap_cmd
* @hw_get_caps_v2: Function pointer for get hw caps v2
* args = cam_query_cap_cmd_v2
* @hw_acquire: Function poniter for acquire hw resources
* args = cam_hw_acquire_args
* @hw_release: Function pointer for release hw device resource
* args = cam_hw_release_args
* @hw_start: Function pointer for start hw devices
* args = cam_hw_start_args
* @hw_stop: Function pointer for stop hw devices
* args = cam_hw_stop_args
* @hw_prepare_update: Function pointer for prepare hw update for hw
* devices args = cam_hw_prepare_update_args
* @hw_config_stream_settings: Function pointer for configure stream for hw
* devices args = cam_hw_stream_setttings
* @hw_config: Function pointer for configure hw devices
* args = cam_hw_config_args
* @hw_read: Function pointer for read hardware registers
* @hw_write: Function pointer for Write hardware registers
* @hw_cmd: Function pointer for any customized commands for
* the hardware manager
* @hw_open: Function pointer for HW init
* @hw_close: Function pointer for HW deinit
* @hw_flush: Function pointer for HW flush
* @hw_reset: Function pointer for HW reset
* @hw_dump: Function pointer for HW dump
* @hw_recovery: Function pointer for HW recovery callback
* @hw_inject_evt: Function pointer for HW event injection callback
* @synx_trigger: Function pointer for synx test trigger
*
*/
struct cam_hw_mgr_intf {
void *hw_mgr_priv;
int (*hw_get_caps)(void *hw_priv, void *hw_caps_args);
int (*hw_get_caps_v2)(void *hw_priv, void *hw_caps_args);
int (*hw_acquire)(void *hw_priv, void *hw_acquire_args);
int (*hw_release)(void *hw_priv, void *hw_release_args);
int (*hw_start)(void *hw_priv, void *hw_start_args);
int (*hw_stop)(void *hw_priv, void *hw_stop_args);
int (*hw_prepare_update)(void *hw_priv, void *hw_prepare_update_args);
int (*hw_config_stream_settings)(void *hw_priv,
void *hw_stream_settings);
int (*hw_config)(void *hw_priv, void *hw_config_args);
int (*hw_read)(void *hw_priv, void *read_args);
int (*hw_write)(void *hw_priv, void *write_args);
int (*hw_cmd)(void *hw_priv, void *write_args);
int (*hw_open)(void *hw_priv, void *fw_download_args);
int (*hw_close)(void *hw_priv, void *hw_close_args);
int (*hw_flush)(void *hw_priv, void *hw_flush_args);
int (*hw_reset)(void *hw_priv, void *hw_reset_args);
int (*hw_dump)(void *hw_priv, void *hw_dump_args);
int (*hw_recovery)(void *hw_priv, void *hw_recovery_args);
void (*hw_inject_evt)(void *hw_priv, void *evt_args);
int (*synx_trigger)(void *hw_priv, void *synx_params);
};
#endif /* _CAM_HW_MGR_INTF_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_NODE_H_
#define _CAM_NODE_H_
#include <linux/kref.h>
#include "cam_context.h"
#include "cam_hw_mgr_intf.h"
#include "cam_req_mgr_interface.h"
#define CAM_NODE_STATE_UNINIT 0
#define CAM_NODE_STATE_INIT 1
/**
* struct cam_node - Singleton Node for camera HW devices
*
* @name: Name for struct cam_node
* @state: Node state:
* 0 = uninitialized, 1 = initialized
* @device_idx: Index to identify which device this node belongs to
* @list_mutex: Mutex for the context pool
* @free_ctx_list: Free context pool list
* @ctx_list: Context list
* @ctx_size: Context list size
* @hw_mgr_intf: Interface for cam_node to HW
* @crm_node_intf: Interface for the CRM to cam_node
* @sd_handler: Shutdown handler for this subdev
*
*/
struct cam_node {
char name[CAM_CTX_DEV_NAME_MAX_LENGTH];
uint32_t state;
uint32_t device_idx;
/* context pool */
struct mutex list_mutex;
struct list_head free_ctx_list;
struct cam_context *ctx_list;
uint32_t ctx_size;
/* interfaces */
struct cam_hw_mgr_intf hw_mgr_intf;
struct cam_req_mgr_kmd_ops crm_node_intf;
int (*sd_handler)(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh);
};
/**
* cam_node_handle_ioctl()
*
* @brief: Handle ioctl commands
*
* @node: Node handle
* @cmd: IOCTL command
*
*/
int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd);
/**
* cam_node_deinit()
*
* @brief: Deinitialization function for the Node interface
*
* @node: Node handle
*
*/
int cam_node_deinit(struct cam_node *node);
/**
* cam_node_shutdown()
*
* @brief: Shutdowns/Closes the cam node.
*
* @node: Cam_node pointer
*
*/
int cam_node_shutdown(struct cam_node *node);
/**
* cam_node_init()
*
* @brief: Initialization function for the Node interface.
*
* @node: Cam_node pointer
* @hw_mgr_intf: HW manager interface blob
* @ctx_list: List of cam_contexts to be added
* @ctx_size: Size of the cam_context
* @name: Name for the node
*
*/
int cam_node_init(struct cam_node *node, struct cam_hw_mgr_intf *hw_mgr_intf,
struct cam_context *ctx_list, uint32_t ctx_size, char *name);
/**
* cam_node_put_ctxt_to_free_list()
*
* @brief: Put context in node free list.
*
* @ref: Context's kref object
*
*/
void cam_node_put_ctxt_to_free_list(struct kref *ref);
/**
* cam_get_dev_handle_info()
*
* @brief: provides the active dev index.
*
* @handle: pointer to struct v4l2_dev
* @ctx: pointer to struct cam_context
* @dev_index: dev index
*
*/
int32_t cam_get_dev_handle_info(uint64_t handle,
struct cam_context **ctx, int32_t dev_index);
#endif /* _CAM_NODE_H_ */

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2018, 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_subdev.h"
#include "cam_node.h"
#include "cam_debug_util.h"
/**
* cam_subdev_subscribe_event()
*
* @brief: function to subscribe to v4l2 events
*
* @sd: Pointer to struct v4l2_subdev.
* @fh: Pointer to struct v4l2_fh.
* @sub: Pointer to struct v4l2_event_subscription.
*/
static int cam_subdev_subscribe_event(struct v4l2_subdev *sd,
struct v4l2_fh *fh,
struct v4l2_event_subscription *sub)
{
return v4l2_event_subscribe(fh, sub, CAM_SUBDEVICE_EVENT_MAX, NULL);
}
/**
* cam_subdev_unsubscribe_event()
*
* @brief: function to unsubscribe from v4l2 events
*
* @sd: Pointer to struct v4l2_subdev.
* @fh: Pointer to struct v4l2_fh.
* @sub: Pointer to struct v4l2_event_subscription.
*/
static int cam_subdev_unsubscribe_event(struct v4l2_subdev *sd,
struct v4l2_fh *fh,
struct v4l2_event_subscription *sub)
{
return v4l2_event_unsubscribe(fh, sub);
}
static long cam_subdev_ioctl(struct v4l2_subdev *sd, unsigned int cmd,
void *arg)
{
long rc;
struct cam_node *node =
(struct cam_node *) v4l2_get_subdevdata(sd);
struct v4l2_subdev_fh *fh = (struct v4l2_subdev_fh *)arg;
if (!node || node->state == CAM_NODE_STATE_UNINIT) {
rc = -EINVAL;
goto end;
}
switch (cmd) {
case VIDIOC_CAM_CONTROL:
cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK);
rc = cam_node_handle_ioctl(node,
(struct cam_control *) arg);
cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK);
break;
case CAM_SD_SHUTDOWN:
if (!cam_req_mgr_is_shutdown()) {
CAM_WARN(CAM_CORE, "SD shouldn't come from user space");
return 0;
}
if (!node->sd_handler) {
CAM_ERR(CAM_CORE,
"No shutdown routine for %s", node->name);
rc = -EINVAL;
goto end;
}
CAM_DBG(CAM_CORE, "Shutdown for %s from media device", node->name);
rc = node->sd_handler(sd, fh);
if (rc)
CAM_ERR(CAM_CORE,
"shutdown device failed(rc = %d) for %s",
rc, node->name);
break;
default:
CAM_ERR(CAM_CORE, "Invalid command %d for %s", cmd,
node->name);
rc = -EINVAL;
}
end:
return rc;
}
#ifdef CONFIG_COMPAT
static long cam_subdev_compat_ioctl(struct v4l2_subdev *sd,
unsigned int cmd, unsigned long arg)
{
struct cam_control cmd_data;
int rc;
if (copy_from_user(&cmd_data, (void __user *)arg,
sizeof(cmd_data))) {
CAM_ERR(CAM_CORE, "Failed to copy from user_ptr=%pK size=%zu",
(void __user *)arg, sizeof(cmd_data));
return -EFAULT;
}
rc = cam_subdev_ioctl(sd, cmd, &cmd_data);
if (!rc) {
if (copy_to_user((void __user *)arg, &cmd_data,
sizeof(cmd_data))) {
CAM_ERR(CAM_CORE,
"Failed to copy to user_ptr=%pK size=%zu",
(void __user *)arg, sizeof(cmd_data));
rc = -EFAULT;
}
}
return rc;
}
#endif
const struct v4l2_subdev_core_ops cam_subdev_core_ops = {
.ioctl = cam_subdev_ioctl,
#ifdef CONFIG_COMPAT
.compat_ioctl32 = cam_subdev_compat_ioctl,
#endif
.subscribe_event = cam_subdev_subscribe_event,
.unsubscribe_event = cam_subdev_unsubscribe_event,
};
static const struct v4l2_subdev_ops cam_subdev_ops = {
.core = &cam_subdev_core_ops,
};
int cam_subdev_remove(struct cam_subdev *sd)
{
if (!sd)
return -EINVAL;
cam_unregister_subdev(sd);
cam_node_deinit((struct cam_node *)sd->token);
kfree(sd->token);
memset(sd, 0, sizeof(struct cam_subdev));
return 0;
}
int cam_subdev_probe(struct cam_subdev *sd, struct platform_device *pdev,
char *name, uint32_t dev_type)
{
int rc;
struct cam_node *node = NULL;
if (!sd || !pdev || !name)
return -EINVAL;
node = kzalloc(sizeof(*node), GFP_KERNEL);
if (!node)
return -ENOMEM;
/* Setup camera v4l2 subdevice */
sd->pdev = pdev;
sd->name = name;
sd->ops = &cam_subdev_ops;
sd->token = node;
sd->sd_flags =
V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
sd->ent_function = dev_type;
rc = cam_register_subdev(sd);
if (rc) {
CAM_ERR(CAM_CORE, "cam_register_subdev() failed for dev: %s",
sd->name);
goto err;
}
platform_set_drvdata(sd->pdev, sd);
return rc;
err:
kfree(node);
return rc;
}

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qcom/opensource/camera-kernel/drivers/cam_cpas/cam_cpas_hw.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CPAS_HW_H_
#define _CAM_CPAS_HW_H_
#include <dt-bindings/msm-camera.h>
#include "cam_cpas_api.h"
#include "cam_cpas_hw_intf.h"
#include "cam_common_util.h"
#include "cam_soc_bus.h"
#define CAM_CPAS_INFLIGHT_WORKS 5
#define CAM_CPAS_MAX_CLIENTS 43
#define CAM_CPAS_MAX_AXI_PORTS 6
#define CAM_CPAS_MAX_DRV_PORTS 4
#define CAM_CPAS_MAX_TREE_LEVELS 4
#define CAM_CPAS_MAX_RT_WR_NIU_NODES 10
#define CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT 32
#define CAM_CPAS_PATH_DATA_MAX 42
#define CAM_CPAS_TRANSACTION_MAX 2
#define CAM_CAMNOC_FILL_LVL_REG_INFO_MAX 6
#define CAM_CPAS_MAX_SLOPE_FACTOR 100
#define CAM_CPAS_MAX_STRESS_INDICATOR 100
/* Number of camera (CAM_SS) instances */
#define CAM_CPAS_CAMERA_INSTANCES 1
#define CAM_CPAS_AXI_MIN_MNOC_AB_BW (2048 * 1024)
#define CAM_CPAS_AXI_MIN_MNOC_IB_BW (2048 * 1024)
#define CAM_CPAS_AXI_MIN_CAMNOC_AB_BW (2048 * 1024)
#define CAM_CPAS_AXI_MIN_CAMNOC_IB_BW (3000000000UL)
#define CAM_CPAS_GET_CLIENT_IDX(handle) (handle)
#define CAM_CPAS_GET_CLIENT_HANDLE(indx) (indx)
#define CAM_CPAS_WORKQUEUE_NAME "cam-cpas"
#define CAM_CPAS_CLIENT_VALID(indx) \
((indx >= 0) && (indx < CAM_CPAS_MAX_CLIENTS))
#define CAM_CPAS_CLIENT_REGISTERED(cpas_core, indx) \
((CAM_CPAS_CLIENT_VALID(indx)) && \
(cpas_core->cpas_client[indx]->registered))
#define CAM_CPAS_CLIENT_STARTED(cpas_core, indx) \
((CAM_CPAS_CLIENT_REGISTERED(cpas_core, indx)) && \
(cpas_core->cpas_client[indx]->started))
/* Array indices to represent corresponding RPMH BCM info */
#define CAM_RPMH_NUMBER_OF_BCMS 0
#define CAM_RPMH_BCM_FE_OFFSET 1
#define CAM_RPMH_BCM_BE_OFFSET 2
#define CAM_RPMH_BCM_DDR_INDEX 3
#define CAM_RPMH_BCM_MNOC_INDEX 4
#define CAM_RPMH_BCM_INFO_MAX 5
#define CAM_CPAS_MONITOR_MAX_ENTRIES 100
#define CAM_CPAS_INC_MONITOR_HEAD(head, ret) \
div_u64_rem(atomic64_add_return(1, head),\
CAM_CPAS_MONITOR_MAX_ENTRIES, (ret))
#define CAM_CPAS_MAX_CESTA_VCD_NUM 9
#define CAM_CPAS_DUMP_NUM_WORDS_COMM 20
#define CAM_CPAS_DUMP_NUM_WORDS_VOTE_TYEP_DRV 4
#define CAM_CPAS_DUMP_NUM_WORDS_VOTE_TYEP_HLOS 2
#define CAM_CPAS_DUMP_NUM_WORDS_RT_WR_NIUS 2
#define CAM_CPAS_DUMP_NUM_WORDS_VCD_CURR_LVL 2
/**
* enum cam_camnoc_domain_type - Enum for different camnoc domains
* @CAM_CAMNOC_HW_COMBINED: refer to legacy camnoc info that combines RT/NRT HW
* @CAM_CAMNOC_HW_RT: type for camnoc RT info
* @CAM_CAMNOC_HW_NRT: type for camnoc NRT info
* @CAM_CAMNOC_HW_TYPE_MAX: camnoc info maximum type
*/
enum cam_camnoc_hw_type {
CAM_CAMNOC_HW_COMBINED,
CAM_CAMNOC_HW_RT,
CAM_CAMNOC_HW_NRT,
CAM_CAMNOC_HW_TYPE_MAX,
};
/**
* enum cam_cpas_access_type - Enum for Register access type
*/
enum cam_cpas_access_type {
CAM_REG_TYPE_READ,
CAM_REG_TYPE_WRITE,
CAM_REG_TYPE_READ_WRITE,
};
/**
* struct cam_cpas_vdd_ahb_mapping : Voltage to ahb level mapping
*
* @vdd_corner : Voltage corner value
* @ahb_level : AHB vote level corresponds to this vdd_corner
*
*/
struct cam_cpas_vdd_ahb_mapping {
unsigned int vdd_corner;
enum cam_vote_level ahb_level;
};
/**
* struct cam_cpas_bw_vote : AXI bw vote
*
* @ab: AB bw value
* @ib: IB bw value
* @camnoc: CAMNOC bw value
*
*/
struct cam_cpas_bw_vote {
uint64_t ab;
uint64_t ib;
uint64_t camnoc;
};
/**
* struct cam_cpas_drv_vote : DRV bw vote
*
* @high: Active bw values
* @low: Sleep bw values
*
*/
struct cam_cpas_drv_vote {
struct cam_cpas_bw_vote high;
struct cam_cpas_bw_vote low;
};
/**
* struct cam_cpas_axi_bw_info : AXI bw info
*
* @vote_type: HLOS or DRV vote type
* @hlos_vote: HLOS bw values
* @drv_vote: DRV bw values
*
*/
struct cam_cpas_axi_bw_info {
enum cam_cpas_vote_type vote_type;
union {
struct cam_cpas_bw_vote hlos_vote;
struct cam_cpas_drv_vote drv_vote;
};
};
/**
* struct cam_cpas_kobj_map: wrapper structure for base kobject
* and cam cpas private soc info
* @base_kobj: kernel object for camera sysfs
* @cpas_hw: pointer to cam_hw_info structure
*/
struct cam_cpas_kobj_map {
struct kobject base_kobj;
struct cam_hw_info *cpas_hw;
};
/**
* struct cam_cpas_internal_ops - CPAS Hardware layer internal ops
*
* @get_hw_info: Function pointer for get hw info
* @init_hw_version: Function pointer for hw init based on version
* @handle_irq: Function poniter for irq handling
* @setup_regbase: Function pointer for setup rebase indices
* @power_on: Function pointer for hw core specific power on settings
* @power_off: Function pointer for hw core specific power off settings
* @setup_qos_settings: Function pointer for hw to select a specific qos header
* @print_poweron_settings: Function pointer for hw to print poweron settings
* @qchannel_handshake: Function pointer for hw core specific qchannel
* handshake settings
* @set_tpg_mux_sel: Set tpg mux select on CPAS TOP register
*
*/
struct cam_cpas_internal_ops {
int (*get_hw_info)(struct cam_hw_info *cpas_hw,
struct cam_cpas_hw_caps *hw_caps);
int (*init_hw_version)(struct cam_hw_info *cpas_hw,
struct cam_cpas_hw_caps *hw_caps);
irqreturn_t (*handle_irq)(int irq_num, void *data);
int (*setup_regbase)(struct cam_hw_soc_info *soc_info,
int32_t regbase_index[], int32_t num_reg_map);
int (*power_on)(struct cam_hw_info *cpas_hw);
int (*power_off)(struct cam_hw_info *cpas_hw);
int (*setup_qos_settings)(struct cam_hw_info *cpas_hw,
uint32_t selection_mask);
int (*print_poweron_settings)(struct cam_hw_info *cpas_hw);
int (*qchannel_handshake)(struct cam_hw_info *cpas_hw, bool power_on, bool force_on);
int (*set_tpg_mux_sel)(struct cam_hw_info *cpas_hw, uint32_t tpg_num);
};
/**
* struct cam_cpas_reg : CPAS register info
*
* @enable: Whether this reg info need to be enabled
* @access_type: Register access type
* @masked_value: Whether this register write/read is based on mask, shift
* @mask: Mask for this register value
* @shift: Shift for this register value
* @value: Register value
*
*/
struct cam_cpas_reg {
bool enable;
enum cam_cpas_access_type access_type;
bool masked_value;
uint32_t offset;
uint32_t mask;
uint32_t shift;
uint32_t value;
};
/**
* struct cam_cpas_client : CPAS Client structure info
*
* @data: Client register params
* @registered: Whether client has registered with cpas
* @started: Whether client has streamed on
* @tree_node_valid: Indicates whether tree node has at least one valid node
* @is_drv_dyn: Indicates whether this client is DRV dynamic voting client
* @ahb_level: Determined/Applied ahb level for the client
* @axi_vote: Determined/Applied axi vote for the client
* @axi_port: Client's parent axi port
* @tree_node: All granular path voting nodes for the client
*
*/
struct cam_cpas_client {
struct cam_cpas_register_params data;
bool registered;
bool started;
bool tree_node_valid;
bool is_drv_dyn;
enum cam_vote_level ahb_level;
struct cam_axi_vote axi_vote;
struct cam_cpas_axi_port *axi_port;
struct cam_cpas_tree_node *tree_node[CAM_CPAS_PATH_DATA_MAX]
[CAM_CPAS_TRANSACTION_MAX];
};
/**
* struct cam_cpas_bus_client : Bus client information
*
* @valid: Whether bus client is valid
* @name: Name of the bus client
* @lock: Mutex lock used while voting on this client
* @curr_vote_level: current voted index
* @common_data: Common data fields for bus client
* @soc_bus_client: Bus client private information
*/
struct cam_cpas_bus_client {
bool valid;
struct mutex lock;
unsigned int curr_vote_level;
struct cam_soc_bus_client_common_data common_data;
void *soc_bus_client;
};
/**
* struct cam_cpas_axi_port : AXI port information
*
* @axi_port_name: Name of this AXI port
* @bus_client: bus client info for this port
* @ib_bw_voting_needed: if this port can update ib bw dynamically
* @is_rt: if this port represents a real time axi port
* @axi_port_node: Node representing AXI Port info in device tree
* @drv_idx: DRV index for axi port node
* @cam_rsc_dev: Cam RSC device for DRV
* @is_drv_started: Indicates if DRV started for RSC device corresponding to port
* @curr_bw: Current voted bw after cpas consolidation
* @additional_bw: Additional bandwidth to cover non-hw cpas clients
* @applied_bw: Actual applied bw to port
*/
struct cam_cpas_axi_port {
const char *axi_port_name;
struct cam_cpas_bus_client bus_client;
bool ib_bw_voting_needed;
bool is_rt;
struct device_node *axi_port_node;
uint32_t drv_idx;
const struct device *cam_rsc_dev;
bool is_drv_started;
struct cam_cpas_axi_bw_info curr_bw;
uint64_t additional_bw;
struct cam_cpas_axi_bw_info applied_bw;
};
/**
* struct cam_cpas_axi_port_debug_info : AXI port information
*
* @axi_port_name: Name of this AXI port
* @curr_bw: Current voted bw after cpas consolidation
* @camnoc_bw: CAMNOC bw value for this port
* @applied_bw: Actual applied bw to port
* @is_drv_started: Indicates if DRV started for RSC device corresponding to port
*/
struct cam_cpas_axi_port_debug_info {
const char *axi_port_name;
struct cam_cpas_axi_bw_info curr_bw;
uint64_t camnoc_bw;
struct cam_cpas_axi_bw_info applied_bw;
bool is_drv_started;
};
struct cam_cpas_cesta_vcd_curr_lvl_debug_info {
uint8_t index;
uint32_t reg_value;
};
/**
* struct cam_cpas_cesta_vcd_reg_debug_info : to hold all cesta register information
*
* @vcd_currol: vcd control reg info
*
*/
struct cam_cpas_cesta_vcd_reg_debug_info {
struct cam_cpas_cesta_vcd_curr_lvl_debug_info
vcd_curr_lvl_debug_info[CAM_CPAS_MAX_CESTA_VCD_NUM];
};
/**
* struct cam_cpas_monitor : CPAS monitor array
*
* @timestamp: Timestamp at which this monitor entry is saved
* @identifier_string: String passed by caller
* @identifier_value: Identifier value passed by caller
* @axi_info: AXI port information
* @applied_camnoc_clk: Applied camnoc axi clock rate with sw, hw clients
* @applied_ahb_level: Applied camcc ahb level
* @fe_ddr: RPMH DDR BCM FE (front-end) status register value.
* This indicates requested clock plan
* @be_ddr: RPMH DDR BCM BE (back-end) status register value.
* This indicates actual current clock plan
* @fe_mnoc: RPMH MNOC BCM FE (front-end) status register value.
* This indicates requested clock plan
* @be_mnoc: RPMH MNOC BCM BE (back-end) status register value.
* This indicates actual current clock plan
* @be_shub: RPMH SHUB BCM BE (back-end) status register value.
* This indicates actual current clock plan
* @num_camnoc_lvl_regs: Number of enabled camnoc fill level
* monitoring registers
* @camnoc_port_name: Camnoc port names
* @camnoc_fill_level: Camnoc fill level register info
* @rt_wr_niu_pri_lut_low: priority lut low values of RT Wr NIUs
* @rt_wr_niu_pri_lut_high: priority lut high values of RT Wr NIUs
* @vcd_reg_debug_info: vcd reg debug information
*/
struct cam_cpas_monitor {
struct timespec64 timestamp;
char identifier_string[128];
int32_t identifier_value;
struct cam_cpas_axi_port_debug_info axi_info[CAM_CPAS_MAX_AXI_PORTS];
struct cam_soc_util_clk_rates applied_camnoc_clk;
unsigned int applied_ahb_level;
uint32_t fe_ddr;
uint32_t be_ddr;
uint32_t fe_mnoc;
uint32_t be_mnoc;
uint32_t be_shub;
uint32_t num_camnoc_lvl_regs[CAM_CAMNOC_HW_TYPE_MAX];
const char *camnoc_port_name[CAM_CAMNOC_HW_TYPE_MAX]
[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
uint32_t camnoc_fill_level[CAM_CAMNOC_HW_TYPE_MAX]
[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
uint32_t rt_wr_niu_pri_lut_low[CAM_CPAS_MAX_RT_WR_NIU_NODES];
uint32_t rt_wr_niu_pri_lut_high[CAM_CPAS_MAX_RT_WR_NIU_NODES];
struct cam_cpas_cesta_vcd_reg_debug_info vcd_reg_debug_info;
struct cam_hw_info *cpas_hw;
};
/**
* struct cam_cpas : CPAS core data structure info
*
* @hw_caps: CPAS hw capabilities
* @cpas_client: Array of pointers to CPAS clients info
* @client_mutex: Mutex for accessing client info
* @tree_lock: Mutex lock for accessing CPAS node tree
* @num_clients: Total number of clients that CPAS supports
* @num_axi_ports: Total number of axi ports found in device tree
* @num_camnoc_axi_ports: Total number of camnoc axi ports found in device tree
* @registered_clients: Number of Clients registered currently
* @streamon_clients: Number of Clients that are in start state currently
* @slave_err_irq_idx: Index of slave error in irq error data structure,
* avoids iterating the entire structure to find this
* idx in irq th
* @regbase_index: Register base indices for CPAS register base IDs
* @ahb_bus_client: AHB Bus client info
* @axi_port: AXI port info for a specific axi index
* @camnoc_axi_port: CAMNOC AXI port info for a specific camnoc axi index
* @cam_subpart_info: camera subparts fuse description
* @internal_ops: CPAS HW internal ops
* @work_queue: Work queue handle
* @soc_access_count: atomic soc_access_count count
* @soc_access_count_wq: wait variable to ensure CPAS is not stop,
* while accessing hw through CPAS
* @dentry: debugfs file entry
* @ahb_bus_scaling_disable: ahb scaling based on src clk corner for bus
* @applied_camnoc_axi_rate: applied camnoc axi clock rate through sw, hw clients
* @monitor_head: Monitor array head
* @monitor_entries: cpas monitor array
* @camnoc_info: array of camnoc info pointer
* @cesta_info: Pointer to cesta header info
* @num_valid_camnoc: number of valid camnoc info
* @camnoc_rt_idx: index to real time camnoc info array
* @camnoc_info_idx: map camnoc hw type to index used for camnoc_info array indexing
* @full_state_dump: Whether to enable full cpas state dump or not
* @smart_qos_dump: Whether to dump smart qos information on update
* @slave_err_irq_en: Whether slave error irq is enabled to detect memory
* config issues
* @smmu_fault_handled: Handled address decode error, on fault at SMMU
* @force_hlos_drv: Whether to force disable DRV voting
* @force_cesta_sw_client: Whether to force voting through cesta sw client
*/
struct cam_cpas {
struct cam_cpas_hw_caps hw_caps;
struct cam_cpas_client *cpas_client[CAM_CPAS_MAX_CLIENTS];
struct mutex client_mutex[CAM_CPAS_MAX_CLIENTS];
struct mutex tree_lock;
uint32_t num_clients;
uint32_t num_axi_ports;
uint32_t num_camnoc_axi_ports;
uint32_t registered_clients;
uint32_t streamon_clients;
uint32_t slave_err_irq_idx[CAM_CAMNOC_HW_TYPE_MAX];
int32_t regbase_index[CAM_CPAS_REG_MAX];
struct cam_cpas_bus_client ahb_bus_client;
struct cam_cpas_axi_port axi_port[CAM_CPAS_MAX_AXI_PORTS];
struct cam_cpas_axi_port camnoc_axi_port[CAM_CPAS_MAX_AXI_PORTS];
struct cam_cpas_subpart_info *cam_subpart_info;
struct cam_cpas_internal_ops internal_ops;
struct workqueue_struct *work_queue;
atomic_t soc_access_count;
wait_queue_head_t soc_access_count_wq;
struct dentry *dentry;
bool ahb_bus_scaling_disable;
struct cam_soc_util_clk_rates applied_camnoc_axi_rate;
atomic64_t monitor_head;
struct cam_cpas_monitor monitor_entries[CAM_CPAS_MONITOR_MAX_ENTRIES];
void *camnoc_info[CAM_CAMNOC_HW_TYPE_MAX];
void *cesta_info;
uint8_t num_valid_camnoc;
int8_t camnoc_rt_idx;
int8_t camnoc_info_idx[CAM_CAMNOC_HW_TYPE_MAX];
bool full_state_dump;
bool smart_qos_dump;
bool slave_err_irq_en[CAM_CAMNOC_HW_TYPE_MAX];
bool smmu_fault_handled;
bool force_hlos_drv;
bool force_cesta_sw_client;
};
int cam_camsstop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops);
int cam_cpastop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops);
int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw,
enum cam_cpas_reg_base reg_base, struct cam_cpas_reg *reg_info);
int cam_cpas_util_reg_read(struct cam_hw_info *cpas_hw,
enum cam_cpas_reg_base reg_base, struct cam_cpas_reg *reg_info);
int cam_cpas_util_client_cleanup(struct cam_hw_info *cpas_hw);
int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw,
int enable);
#endif /* _CAM_CPAS_HW_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CPAS_HW_INTF_H_
#define _CAM_CPAS_HW_INTF_H_
#include <linux/platform_device.h>
#include "cam_cpas_api.h"
#include "cam_hw.h"
#include "cam_hw_intf.h"
#include "cam_debug_util.h"
/* Number of times to retry while polling */
#define CAM_CPAS_POLL_RETRY_CNT 5
/* Minimum usecs to sleep while polling */
#define CAM_CPAS_POLL_MIN_USECS 200
/* Maximum usecs to sleep while polling */
#define CAM_CPAS_POLL_MAX_USECS 250
/* Number of times to retry while polling */
#define CAM_CPAS_POLL_QH_RETRY_CNT 50
/* Number of CPAS hw caps registers */
#define CAM_CPAS_MAX_CAPS_REGS 2
/**
* enum cam_cpas_hw_type - Enum for CPAS HW type
*/
enum cam_cpas_hw_type {
CAM_HW_CPASTOP,
CAM_HW_CAMSSTOP,
};
/**
* enum cam_cpas_reg_base - Enum for register base identifier. These
* are the identifiers used in generic register
* write/read APIs provided by cpas driver.
*/
enum cam_cpas_reg_base {
CAM_CPAS_REG_CPASTOP,
CAM_CPAS_REG_CAMNOC,
CAM_CPAS_REG_CAMSS,
CAM_CPAS_REG_RPMH,
CAM_CPAS_REG_CESTA,
CAM_CPAS_REG_CAMNOC_RT,
CAM_CPAS_REG_CAMNOC_NRT,
CAM_CPAS_REG_MAX
};
/**
* enum cam_cpas_hw_cmd_process - Enum for CPAS HW process command type
*/
enum cam_cpas_hw_cmd_process {
CAM_CPAS_HW_CMD_REGISTER_CLIENT,
CAM_CPAS_HW_CMD_UNREGISTER_CLIENT,
CAM_CPAS_HW_CMD_REG_WRITE,
CAM_CPAS_HW_CMD_REG_READ,
CAM_CPAS_HW_CMD_AHB_VOTE,
CAM_CPAS_HW_CMD_AXI_VOTE,
CAM_CPAS_HW_CMD_LOG_VOTE,
CAM_CPAS_HW_CMD_SELECT_QOS,
CAM_CPAS_HW_CMD_LOG_EVENT,
CAM_CPAS_HW_CMD_GET_SCID,
CAM_CPAS_HW_CMD_ACTIVATE_LLC,
CAM_CPAS_HW_CMD_DEACTIVATE_LLC,
CAM_CPAS_HW_CMD_CONFIGURE_STALING_LLC,
CAM_CPAS_HW_CMD_NOTIF_STALL_INC_LLC,
CAM_CPAS_HW_CMD_DUMP_BUFF_FILL_INFO,
CAM_CPAS_HW_CMD_CSID_INPUT_CORE_INFO_UPDATE,
CAM_CPAS_HW_CMD_CSID_PROCESS_RESUME,
CAM_CPAS_HW_CMD_ENABLE_DISABLE_DOMAIN_ID_CLK,
CAM_CPAS_HW_CMD_TPG_MUX_SEL,
CAM_CPAS_HW_CMD_DUMP_STATE_MONITOR_INFO,
CAM_CPAS_HW_CMD_INVALID,
};
/**
* struct cam_cpas_hw_cmd_csid_input_core_info_update : CPAS cmd struct for updating acquired
* csid core info to cpas
*
* @csid_idx: CSID core index
* @sfe_idx: SFE core index corresponding to CSID core
* @set_port: Indicates whether to set or reset port for given client
*
*/
struct cam_cpas_hw_cmd_csid_input_core_info_update {
int csid_idx;
int sfe_idx;
bool set_port;
};
/**
* struct cam_cpas_hw_cmd_reg_read_write : CPAS cmd struct for reg read, write
*
* @client_handle: Client handle
* @reg_base: Register base type
* @offset: Register offset
* @value: Register value
* @mb: Whether to do operation with memory barrier
*
*/
struct cam_cpas_hw_cmd_reg_read_write {
uint32_t client_handle;
enum cam_cpas_reg_base reg_base;
uint32_t offset;
uint32_t value;
bool mb;
};
/**
* struct cam_cpas_hw_cmd_ahb_vote : CPAS cmd struct for AHB vote
*
* @client_handle: Client handle
* @ahb_vote: AHB voting info
*
*/
struct cam_cpas_hw_cmd_ahb_vote {
uint32_t client_handle;
struct cam_ahb_vote *ahb_vote;
};
/**
* struct cam_cpas_hw_cmd_axi_vote : CPAS cmd struct for AXI vote
*
* @client_handle: Client handle
* @axi_vote: axi bandwidth vote
*
*/
struct cam_cpas_hw_cmd_axi_vote {
uint32_t client_handle;
struct cam_axi_vote *axi_vote;
};
/**
* struct cam_cpas_hw_cmd_start : CPAS cmd struct for start
*
* @client_handle: Client handle
*
*/
struct cam_cpas_hw_cmd_start {
uint32_t client_handle;
struct cam_ahb_vote *ahb_vote;
struct cam_axi_vote *axi_vote;
};
/**
* struct cam_cpas_hw_cmd_stop : CPAS cmd struct for stop
*
* @client_handle: Client handle
*
*/
struct cam_cpas_hw_cmd_stop {
uint32_t client_handle;
};
/**
* struct cam_cpas_hw_cmd_notify_event : CPAS cmd struct for notify event
*
* @identifier_string: Identifier string passed by caller
* @identifier_value: Identifier value passed by caller
*
*/
struct cam_cpas_hw_cmd_notify_event {
const char *identifier_string;
int32_t identifier_value;
};
/**
* struct cam_cpas_hw_caps : CPAS HW capabilities
*
* @camera_family: Camera family type
* @camera_version: Camera version
* @cpas_version: CPAS version
* @camera_capability: array of camera hw capabilities
* @num_capability_reg: Number of camera hw capabilities registers
* @fuse_info: Fuse information
*
*/
struct cam_cpas_hw_caps {
uint32_t camera_family;
struct cam_hw_version camera_version;
struct cam_hw_version cpas_version;
uint32_t camera_capability[CAM_CPAS_MAX_CAPS_REGS];
uint32_t num_capability_reg;
struct cam_cpas_fuse_info fuse_info;
};
int cam_cpas_hw_probe(struct platform_device *pdev,
struct cam_hw_intf **hw_intf);
int cam_cpas_hw_remove(struct cam_hw_intf *cpas_hw_intf);
/**
* @brief : API to register CPAS hw to platform framework.
* @return struct platform_device pointer on on success, or ERR_PTR() on error.
*/
int cam_cpas_dev_init_module(void);
/**
* @brief : API to remove CPAS interface from platform framework.
*/
void cam_cpas_dev_exit_module(void);
/**
* @brief : API to select TPG mux select.
*/
int cam_cpas_enable_tpg_mux_sel(uint32_t tpg_mux_sel);
#endif /* _CAM_CPAS_HW_INTF_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CPAS_SOC_H_
#define _CAM_CPAS_SOC_H_
#include <linux/soc/qcom/llcc-qcom.h>
#include "cam_soc_util.h"
#include "cam_cpas_hw.h"
#define CAM_REGULATOR_LEVEL_MAX 16
#define CAM_CPAS_MAX_TREE_NODES 63
#define CAM_CPAS_MAX_FUSE_FEATURE 10
/**
* enum cam_cpas_num_subparts_types - Enum for types of number of camera subparts
*/
enum cam_cpas_num_subparts_types {
CAM_CPAS_AVAILABLE_NUM_SUBPARTS,
CAM_CPAS_FUNCTIONAL_NUM_SUBPARTS,
CAM_CPAS_NUM_SUBPARTS_MAX_TYPES,
};
/**
* struct cpas_tree_node: Generic cpas tree node for BW voting
*
* @cell_idx: Index to identify node from device tree and its parent
* @level_idx: Index to identify at what level the node is present
* @axi_port_idx_arr: Index to identify which axi port to vote the consolidated bw.
* It can point to multiple indexes in case of camera DRV
* @drv_voting_idx: Specifies the index to which the child node would finally vote.
* @camnoc_axi_port_idx: Index to find which axi port to vote consolidated bw
* @path_data_type: Traffic type info from device tree (ife-vid, ife-disp etc)
* @path_trans_type: Transaction type info from device tree (rd, wr)
* @merge_type: Traffic merge type (calculation info) from device tree
* @bus_width_factor: Factor for accounting bus width in CAMNOC bw calculation
* @bw_info: AXI BW info for all drv ports
* @camnoc_max_needed: If node is needed for CAMNOC BW calculation then true
* @constituent_paths: Constituent paths presence info from device tree
* Ex: For CAM_CPAS_PATH_DATA_IFE_UBWC_STATS, index corresponding to
* CAM_CPAS_PATH_DATA_IFE_VID, CAM_CPAS_PATH_DATA_IFE_DISP and
* CAM_CPAS_PATH_DATA_IFE_STATS
* @tree_dev_node: Device node from devicetree for current tree node
* @parent_node: Pointer to node one or more level above the current level
* (starting from end node of cpas client)
* @pri_lut_low_offset: Register offset value for priority lut low.
* Valid only for level1 nodes (representing NIUs)
* @pri_lut_high_offset: Register offset value for priority lut high.
* Valid only for level1 nodes (representing NIUs)
* @niu_size: Size of NIU that this node represents. Size in KB
* @curr_priority_low: New calculated priority lut low values
* @curr_priority_high: New calculated priority lut high values
* @applied_priority_low: Currently applied priority lut low values
* @applied_priority_high: Currently applied priority lut high values
*
*/
struct cam_cpas_tree_node {
uint32_t cell_idx;
int level_idx;
int *axi_port_idx_arr;
int drv_voting_idx;
int camnoc_axi_port_idx;
const char *node_name;
uint32_t path_data_type;
uint32_t path_trans_type;
uint32_t merge_type;
uint32_t bus_width_factor;
struct cam_cpas_axi_bw_info *bw_info;
bool camnoc_max_needed;
bool constituent_paths[CAM_CPAS_PATH_DATA_MAX];
struct device_node *tree_dev_node;
struct cam_cpas_tree_node *parent_node;
uint32_t pri_lut_low_offset;
uint32_t pri_lut_high_offset;
uint32_t niu_size;
uint32_t curr_priority_low;
uint32_t curr_priority_high;
uint32_t applied_priority_low;
uint32_t applied_priority_high;
};
/**
* struct cam_cpas_feature_info : CPAS fuse feature info
* @feature: Identifier for feature
* @type: Type of feature
* @value: Fuse value
* @enable: Feature enable or disable
* @hw_map: Each bit position indicates if the hw_id for the feature
*/
struct cam_cpas_feature_info {
uint32_t feature;
uint32_t type;
uint32_t value;
bool enable;
uint32_t hw_map;
};
/**
* struct cam_sys_cache_local_info : camera cache info saving locally
*
* @type: cache type small/large etc.
* @staling_distance: staling_distance
* @mode: camera llc's stalling mode
* @op_type: cache operation type EVICT, FORGET
*/
struct cam_sys_cache_local_info {
enum cam_sys_cache_config_types type;
uint32_t staling_distance;
enum cam_sys_cache_llcc_staling_mode mode;
enum cam_sys_cache_llcc_staling_op_type op_type;
};
/**
* struct cam_sys_cache_info : Last level camera cache info
*
* @ref_cnt: Ref cnt activate/deactivate cache
* @type: cache type small/large etc.
* @uid: Client user ID
* @size: Cache size
* @scid: Slice ID
* @slic_desc: Slice descriptor
* @staling_distance: staling_distance
* @mode: camera llc's stalling mode
* @op_type: cache operation type EVICT, FORGET
*/
struct cam_sys_cache_info {
uint32_t ref_cnt;
enum cam_sys_cache_config_types type;
uint32_t uid;
size_t size;
int32_t scid;
const char *name;
struct llcc_slice_desc *slic_desc;
uint32_t staling_distance;
enum cam_sys_cache_llcc_staling_mode mode;
enum cam_sys_cache_llcc_staling_op_type op_type;
};
/**
* struct cam_cpas_smart_qos_info : Smart QOS info
*
* @rt_wr_priority_min: Minimum priority value for rt write nius
* @rt_wr_priority_max: Maximum priority value for rt write nius
* @rt_wr_priority_clamp: Clamp priority value for rt write nius
* @rt_wr_slope_factor: Slope factor value for rt write nius
* @leaststressed_clamp_th: Leaststressed clamp threshold value for rt write nius
* @moststressed_clamp_th: Moststressed clamp threshold value for rt write nius
* @highstress_indicator_th: Highstress indicator threshold value for rt write nius
* @lowstress_indicator_th: Lowstress indicator threshold value for rt write nius
* @bw_ratio_scale_factor: BW ratio scale factor value for rt write nius
* @num_rt_wr_nius: Number of rt write nius
* @rt_wr_niu_node: List of level1 nodes representing rt write nius
*/
struct cam_cpas_smart_qos_info {
uint8_t rt_wr_priority_min;
uint8_t rt_wr_priority_max;
uint8_t rt_wr_priority_clamp;
uint8_t rt_wr_slope_factor;
uint8_t leaststressed_clamp_th;
uint8_t moststressed_clamp_th;
uint8_t highstress_indicator_th;
uint8_t lowstress_indicator_th;
uint8_t bw_ratio_scale_factor;
uint8_t num_rt_wr_nius;
struct cam_cpas_tree_node *rt_wr_niu_node[CAM_CPAS_MAX_RT_WR_NIU_NODES];
};
/**
* struct cam_cpas_domain_id_mapping : Domain id mapping
*
* @domain_type: Domain type, currently defined as two,
* secure/non-secure. This will be expanded
* later to more types, and correspnding ID
* @mapping_id: ID of domain type
*/
struct cam_cpas_domain_id_mapping {
uint32_t domain_type;
uint32_t mapping_id;
};
/**
* struct cam_cpas_domain_id_info : Stores all information related
* to domain-id support
* @domain_id_entries: Stores mapping between domain types and their IDs
* @num_domain_ids: Num of domain id types found from dtsi
* @domain_id_supported: Whether domain id is supported
*/
struct cam_cpas_domain_id_info {
struct cam_cpas_domain_id_mapping *domain_id_entries;
uint32_t num_domain_ids;
bool domain_id_supported;
};
/**
* struct cam_cpas_domain_id_support_clks : Stores all information
* related to clocks
* needed to turn on SWIs
* for domain id programming
* @clk_names: Clock names as declared in DT
* @clk_idx: Corresponding clk index as declared in DT
* @number_clks: Number of clocks declared to turn all CSIDs
*/
struct cam_cpas_domain_id_support_clks {
const char *clk_names[CAM_SOC_MAX_OPT_CLK];
int32_t clk_idx[CAM_SOC_MAX_OPT_CLK];
int number_clks;
};
/**
* struct cam_cpas_soc_irq_data: irq data to be passed in irq handler from ISR
*
* @cpas_hw: cpas hw info
* @camnoc_type: type of camnoc associated with the irq
*
*/
struct cam_cpas_soc_irq_data {
struct cam_hw_info *cpas_hw;
enum cam_camnoc_hw_type camnoc_type;
};
/**
* struct cam_cpas_sysfs_info - cpas sysfs info
*
* @kobj: Kobj for camera directory
* @num_ifes: Number of available and functional IFEs
* @num_ife_lites: Number of available and functional IFE-LITEs
* @num_sfes: Number of available and functional SFEs
* @num_custom: Number of available and functional CUSTOM
*/
struct cam_cpas_sysfs_info {
struct kobject *kobj;
uint32_t num_ifes[CAM_CPAS_NUM_SUBPARTS_MAX_TYPES];
uint32_t num_ife_lites[CAM_CPAS_NUM_SUBPARTS_MAX_TYPES];
uint32_t num_sfes[CAM_CPAS_NUM_SUBPARTS_MAX_TYPES];
uint32_t num_custom[CAM_CPAS_NUM_SUBPARTS_MAX_TYPES];
};
/**
* struct cam_cpas_private_soc : CPAS private DT info
*
* @arch_compat: ARCH compatible string
* @client_id_based: Whether clients are id based
* @bus_icc_based: Interconnect based bus interaction
* @num_clients: Number of clients supported
* @client_name: Client names
* @tree_node: Array of pointers to all tree nodes required to calculate
* axi bw, arranged with help of cell index in device tree
* @camera_bus_node: Device tree node from cpas node
* @level_node: Device tree node for each level in camera_bus_node
* @num_vdd_ahb_mapping : Number of vdd to ahb level mapping supported
* @vdd_ahb : AHB level mapping info for the supported vdd levels
* @control_camnoc_axi_clk : Whether CPAS driver need to set camnoc axi clk freq
* @camnoc_bus_width : CAMNOC Bus width
* @camnoc_axi_clk_bw_margin : BW Margin in percentage to add while calculating
* camnoc axi clock
* @camnoc_axi_min_ib_bw: Min camnoc BW which varies based on target
* @fuse_info: fuse information
* @sysfs_info: Camera subparts sysfs information
* @rpmh_info: RPMH BCM info
* @num_feature_info: number of feature_info entries
* @feature_info: Structure for storing feature information
* @num_caches: Number of last level caches
* @part_info: Camera Hw subpart info
* @llcc_info: Cache info
* @enable_secure_qos_update: whether to program QoS securely on current chipset
* @enable_smart_qos: Whether to enable Smart QoS mechanism on current chipset
* @enable_cam_ddr_drv: Whether to enable Camera DDR DRV on current chipset
* @enable_cam_clk_drv: Whether to enable Camera Clk DRV on current chipset
* @smart_qos_info: Pointer to smart qos info
* @icp_clk_index: Index of optional icp clk
* @domain_id_info: Stores all information related to domain id support
* @domain_id_clks: All clock related information for domain id support
* @irq_data: array of data for each irq line to be passed in irq handler
*/
struct cam_cpas_private_soc {
const char *arch_compat;
bool client_id_based;
bool bus_icc_based;
uint32_t num_clients;
const char *client_name[CAM_CPAS_MAX_CLIENTS];
struct cam_cpas_tree_node *tree_node[CAM_CPAS_MAX_TREE_NODES];
struct device_node *camera_bus_node;
struct device_node *level_node[CAM_CPAS_MAX_TREE_LEVELS];
uint32_t num_vdd_ahb_mapping;
struct cam_cpas_vdd_ahb_mapping vdd_ahb[CAM_REGULATOR_LEVEL_MAX];
bool control_camnoc_axi_clk;
uint32_t camnoc_bus_width;
uint32_t camnoc_axi_clk_bw_margin;
uint64_t camnoc_axi_min_ib_bw;
struct cam_cpas_fuse_info fuse_info;
struct cam_cpas_sysfs_info sysfs_info;
uint32_t rpmh_info[CAM_RPMH_BCM_INFO_MAX];
uint32_t num_feature_info;
struct cam_cpas_feature_info feature_info[CAM_CPAS_MAX_FUSE_FEATURE];
uint32_t num_caches;
uint32_t part_info;
struct cam_sys_cache_info *llcc_info;
bool enable_smart_qos;
bool enable_cam_ddr_drv;
bool enable_cam_clk_drv;
bool enable_secure_qos_update;
struct cam_cpas_smart_qos_info *smart_qos_info;
int32_t icp_clk_index;
struct cam_cpas_domain_id_info domain_id_info;
struct cam_cpas_domain_id_support_clks *domain_id_clks;
struct cam_cpas_soc_irq_data *irq_data;
};
void cam_cpas_dump_tree_vote_info(struct cam_hw_info *cpas_hw,
const struct cam_cpas_tree_node *tree_node,
const char *identifier, int ddr_drv_idx, int cesta_drv_idx);
void cam_cpas_dump_full_tree_state(struct cam_hw_info *cpas_hw, const char *identifier);
void cam_cpas_util_debug_parse_data(struct cam_cpas_private_soc *soc_private);
void cam_cpas_dump_axi_vote_info(
const struct cam_cpas_client *cpas_client,
const char *identifier,
struct cam_axi_vote *axi_vote);
int cam_cpas_node_tree_cleanup(struct cam_cpas *cpas_core,
struct cam_cpas_private_soc *soc_private);
int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info,
irq_handler_t vfe_irq_handler, struct cam_hw_info *cpas_hw);
int cam_cpas_soc_deinit_resources(struct cam_hw_soc_info *soc_info);
int cam_cpas_soc_enable_resources(struct cam_hw_soc_info *soc_info,
enum cam_vote_level default_level);
int cam_cpas_soc_disable_resources(struct cam_hw_soc_info *soc_info,
bool disable_clocks, bool disable_irq);
int cam_cpas_soc_disable_irq(struct cam_hw_soc_info *soc_info);
#endif /* _CAM_CPAS_SOC_H_ */

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_cpas_hw_intf.h"
#include "cam_cpas_hw.h"
#include "cam_cpas_soc.h"
int cam_camsstop_get_hw_info(struct cam_hw_info *cpas_hw,
struct cam_cpas_hw_caps *hw_caps)
{
struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
int32_t reg_indx = cpas_core->regbase_index[CAM_CPAS_REG_CAMSS];
uint32_t reg_value;
if (reg_indx == -1)
return -EINVAL;
hw_caps->camera_family = CAM_FAMILY_CAMERA_SS;
reg_value = cam_io_r_mb(soc_info->reg_map[reg_indx].mem_base + 0x0);
hw_caps->camera_version.major =
CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1c);
hw_caps->camera_version.minor =
CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10);
hw_caps->camera_version.incr =
CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0);
CAM_DBG(CAM_FD, "Family %d, version %d.%d.%d",
hw_caps->camera_family, hw_caps->camera_version.major,
hw_caps->camera_version.minor, hw_caps->camera_version.incr);
return 0;
}
int cam_camsstop_setup_regbase_indices(struct cam_hw_soc_info *soc_info,
int32_t regbase_index[], int32_t num_reg_map)
{
uint32_t index;
int rc;
if (num_reg_map > CAM_CPAS_REG_MAX) {
CAM_ERR(CAM_CPAS, "invalid num_reg_map=%d", num_reg_map);
return -EINVAL;
}
if (soc_info->num_mem_block > CAM_SOC_MAX_BLOCK) {
CAM_ERR(CAM_CPAS, "invalid num_mem_block=%d",
soc_info->num_mem_block);
return -EINVAL;
}
rc = cam_common_util_get_string_index(soc_info->mem_block_name,
soc_info->num_mem_block, "cam_camss", &index);
if ((rc == 0) && (index < num_reg_map)) {
regbase_index[CAM_CPAS_REG_CAMSS] = index;
} else {
CAM_ERR(CAM_CPAS, "regbase not found for CAM_CPAS_REG_CAMSS");
return -EINVAL;
}
return 0;
}
int cam_camsstop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops)
{
if (!internal_ops) {
CAM_ERR(CAM_CPAS, "invalid NULL param");
return -EINVAL;
}
internal_ops->get_hw_info = cam_camsstop_get_hw_info;
internal_ops->init_hw_version = NULL;
internal_ops->handle_irq = NULL;
internal_ops->setup_regbase = cam_camsstop_setup_regbase_indices;
internal_ops->power_on = NULL;
internal_ops->power_off = NULL;
internal_ops->setup_qos_settings = NULL;
internal_ops->print_poweron_settings = NULL;
internal_ops->qchannel_handshake = NULL;
internal_ops->set_tpg_mux_sel = NULL;
return 0;
}

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CPASTOP_HW_H_
#define _CAM_CPASTOP_HW_H_
#include "cam_cpas_api.h"
#include "cam_cpas_hw.h"
/* Camera Hw parts array indices */
#define CAM_CPAS_PART_MAX_FUSE_BITS 8
#define CAM_CPAS_PART_MAX_FUSE_BIT_INFO 2
/**
* enum cam_camnoc_hw_irq_type - Enum for camnoc error types
*
* @CAM_CAMNOC_HW_IRQ_SLAVE_ERROR : Each slave port in CAMNOC
* (3 QSB ports and 1 QHB port)
* has an error logger. The
* error observed at any slave
* port is logged into the
* error logger register and
* an IRQ is triggered
* @CAM_CAMNOC_HW_IRQ_IFE_UBWC_ENCODE_ERROR : Triggered if any error
* detected in the IFE UBWC
* encoder instance
* @CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR : Triggered if any error
* detected in the IFE UBWC-
* Stats encoder instance
* @CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_1_ENCODE_ERROR: Triggered if any error
* detected in the IFE UBWC-
* Stats 1 encoder instance
* @CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR : Triggered if any error
* detected in the IFE0 UBWC
* encoder instance
* @CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR : Triggered if any error
* detected in the IFE1 or
* IFE3 UBWC encoder instance
* @CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR : Triggered if any UBWC error
* is detected in IFE0 write
* path
* @CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR : Triggered if any UBWC error
* is detected in IFE1 write
* path slave times out after
* 4000 AHB cycles
* @CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR : Triggered if any error
* detected in the IPE
* UBWC encoder instance
* @CAM_CAMNOC_HW_IRQ_BPS_UBWC_ENCODE_ERROR : Triggered if any error
* detected in the BPS
* UBWC encoder instance
* @CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR : Triggered if any error
* detected in the IPE1/BPS
* read path decoder instance
* @CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR : Triggered if any error
* detected in the IPE0 read
* path decoder instance
* @CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR : Triggered if any error
* detected in the IPE1 read
* path decoder instance
* @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR : Triggered if any error
* detected in the IPE/BPS
* UBWC decoder instance
* @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR : Triggered if any error
* detected in the IPE/BPS
* UBWC encoder instance
* @CAM_CAMNOC_HW_IRQ_OFE_UBWC_WRITE_ENCODE_ERROR : Triggered if any error
* detected in the OFE write
* path enconder instance
* @CAM_CAMNOC_HW_IRQ_OFE_UBWC_READ_DECODE_ERROR : Triggered if any error
* detected in the OFE read
* path enconder instance
* @CAM_CAMNOC_HW_IRQ_TFE_UBWC_ENCODE_ERROR : Triggered if any error
* detected in the TFE
* UBWC enconder instance
* @CAM_CAMNOC_HW_IRQ_RESERVED1 : Reserved
* @CAM_CAMNOC_HW_IRQ_RESERVED2 : Reserved
* @CAM_CAMNOC_HW_IRQ_CAMNOC_TEST : To test the IRQ logic
*/
enum cam_camnoc_hw_irq_type {
CAM_CAMNOC_HW_IRQ_SLAVE_ERROR =
CAM_CAMNOC_IRQ_SLAVE_ERROR,
CAM_CAMNOC_HW_IRQ_IFE_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IFE_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_1_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IFE_UBWC_STATS_1_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IPE_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_BPS_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_BPS_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR =
CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR,
CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR =
CAM_CAMNOC_IRQ_IPE0_UBWC_DECODE_ERROR,
CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR =
CAM_CAMNOC_IRQ_IPE1_UBWC_DECODE_ERROR,
CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR =
CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_OFE_UBWC_WRITE_ENCODE_ERROR =
CAM_CAMNOC_IRQ_OFE_WR_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_OFE_UBWC_READ_DECODE_ERROR =
CAM_CAMNOC_IRQ_OFE_RD_UBWC_DECODE_ERROR,
CAM_CAMNOC_HW_IRQ_TFE_UBWC_ENCODE_ERROR =
CAM_CAMNOC_IRQ_TFE_UBWC_ENCODE_ERROR,
CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT =
CAM_CAMNOC_IRQ_AHB_TIMEOUT,
CAM_CAMNOC_HW_IRQ_RESERVED1,
CAM_CAMNOC_HW_IRQ_RESERVED2,
CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
};
/**
* enum cam_camnoc_port_type - Enum for different camnoc hw ports. All CAMNOC
* settings like QoS, LUT mappings need to be configured for
* each of these ports.
*
* @CAM_CAMNOC_CDM: Indicates CDM HW connection to camnoc
* @CAM_CAMNOC_SFE_RD: Indicates read data from all SFEs to cammnoc
* @CAM_CAMNOC_IFE02: Indicates IFE0, IFE2 HW connection to camnoc
* @CAM_CAMNOC_IFE13: Indicates IFE1, IFE3 HW connection to camnoc
* @CAM_CAMNOC_IFE_LITE: Indicates all IFE lites connection to camnoc
* @CAM_CAMNOC_IFE_LINEAR: Indicates linear data from all IFEs to cammnoc
* @CAM_CAMNOC_IFE_LINEAR_STATS: Indicates linear and stats data from certan
* IFEs to cammnoc
* @CAM_CAMNOC_IFE_LINEAR_STATS_1: Indicates linear and stats data from certan
* IFEs to cammnoc
* @CAM_CAMNOC_IFE_PDAF: Indicates pdaf data from all IFEs to cammnoc
* @CAM_CAMNOC_IFE_UBWC: Indicates ubwc from all IFEs to cammnoc
* @CAM_CAMNOC_IFE_UBWC_STATS: Indicates ubwc+stats from certain IFEs to cammnoc
* @CAM_CAMNOC_IFE_UBWC_STATS_1: Indicates ubwc+stats from certain
* IFEs to cammnoc
* @CAM_CAMNOC_IFE_RDI_WR: Indicates RDI write data from certain IFEs to cammnoc
* @CAM_CAMNOC_IFE_RDI_WR_1: Indicates RDI write data from certain
* IFEs to cammnoc
* @CAM_CAMNOC_IFE_RDI_RD: Indicates RDI read data from all IFEs to cammnoc
* @CAM_CAMNOC_IFE0123_RDI_WRITE: RDI write only for all IFEx
* @CAM_CAMNOC_IFE0_NRDI_WRITE: IFE0 non-RDI write
* @CAM_CAMNOC_IFE01_RDI_READ: IFE0/1 RDI READ
* @CAM_CAMNOC_IFE1_NRDI_WRITE: IFE1 non-RDI write
* @CAM_CAMNOC_IPE_BPS_LRME_READ: Indicates IPE, BPS, LRME Read HW
* connection to camnoc
* @CAM_CAMNOC_IPE_BPS_LRME_WRITE: Indicates IPE, BPS, LRME Write HW
* connection to camnoc
* @CAM_CAMNOC_IPE_VID_DISP_WRITE: Indicates IPE's VID/DISP Wrire HW
* connection to camnoc
* @CAM_CAMNOC_IPE_WR: Indicates IPE HW's write connection to camnoc
* @CAM_CAMNOC_IPE0_RD: Indicates IPE's Read0 HW connection to camnoc
* @CAM_CAMNOC_IPE1_RD: Indicates IPE's Read1 HW connection to camnoc
* @CAM_CAMNOC_IPE1_BPS_RD: Indicates IPE's Read1 + BPS Read HW connection
* to camnoc
* @CAM_CAMNOC_IPE_BPS_WR: Indicates IPE+BPS Write HW connection to camnoc
* @CAM_CAMNOC_BPS_WR: Indicates BPS HW's write connection to camnoc
* @CAM_CAMNOC_BPS_RD: Indicates BPS HW's read connection to camnoc
* @CAM_CAMNOC_JPEG: Indicates JPEG HW connection to camnoc
* @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc
* @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc
* @CAM_CAMNOC_TFE: Indicates TFE0 HW connection to camnoc
* @CAM_CAMNOC_TFE_1: Indicates TFE1 HW connection to camnoc
* @CAM_CAMNOC_TFE_2: Indicates TFE2 HW connection to camnoc
* @CAM_CAMNOC_OPE: Indicates OPE HW connection to camnoc
*/
/* Deprecated, do not use this anymore. port_name serves the purpose instead of this */
enum cam_camnoc_port_type {
CAM_CAMNOC_CDM,
CAM_CAMNOC_SFE_RD,
CAM_CAMNOC_IFE02,
CAM_CAMNOC_IFE13,
CAM_CAMNOC_IFE_LITE,
CAM_CAMNOC_IFE_LINEAR,
CAM_CAMNOC_IFE_LINEAR_STATS,
CAM_CAMNOC_IFE_LINEAR_STATS_1,
CAM_CAMNOC_IFE_PDAF,
CAM_CAMNOC_IFE_UBWC,
CAM_CAMNOC_IFE_UBWC_STATS,
CAM_CAMNOC_IFE_UBWC_STATS_1,
CAM_CAMNOC_IFE_RDI_WR,
CAM_CAMNOC_IFE_RDI_WR_1,
CAM_CAMNOC_IFE_RDI_RD,
CAM_CAMNOC_IFE0123_RDI_WRITE,
CAM_CAMNOC_IFE0_NRDI_WRITE,
CAM_CAMNOC_IFE01_RDI_READ,
CAM_CAMNOC_IFE1_NRDI_WRITE,
CAM_CAMNOC_IPE_BPS_LRME_READ,
CAM_CAMNOC_IPE_BPS_LRME_WRITE,
CAM_CAMNOC_IPE_VID_DISP_WRITE,
CAM_CAMNOC_IPE_WR,
CAM_CAMNOC_IPE0_RD,
CAM_CAMNOC_IPE1_RD,
CAM_CAMNOC_IPE1_BPS_RD,
CAM_CAMNOC_IPE_BPS_WR,
CAM_CAMNOC_BPS_WR,
CAM_CAMNOC_BPS_RD,
CAM_CAMNOC_JPEG,
CAM_CAMNOC_FD,
CAM_CAMNOC_ICP,
CAM_CAMNOC_TFE_BAYER_STATS,
CAM_CAMNOC_TFE_BAYER_STATS_1,
CAM_CAMNOC_TFE_BAYER_STATS_2,
CAM_CAMNOC_TFE_RAW,
CAM_CAMNOC_TFE_RAW_1,
CAM_CAMNOC_TFE_RAW_2,
CAM_CAMNOC_TFE,
CAM_CAMNOC_TFE_1,
CAM_CAMNOC_TFE_2,
CAM_CAMNOC_OPE,
CAM_CAMNOC_OPE_BPS_WR,
CAM_CAMNOC_OPE_BPS_CDM_RD,
CAM_CAMNOC_CRE,
CAM_CAMNOC_IFE01234_RDI_WRITE,
CAM_CAMNOC_IFE01_NRDI_WRITE,
CAM_CAMNOC_IFE2_NRDI_WRITE,
};
/**
* struct cam_camnoc_specific : CPAS camnoc specific settings
*
* @port_type: Port type
* @port_name: Port name
* @enable: Whether to enable settings for this connection
* @priority_lut_low: Priority Low LUT mapping for this connection
* @priority_lut_high: Priority High LUT mapping for this connection
* @urgency: Urgency (QoS) settings for this connection
* @danger_lut: Danger LUT mapping for this connection
* @safe_lut: Safe LUT mapping for this connection
* @ubwc_ctl: UBWC control settings for this connection
* @qosgen_mainctl: qosgen shaping control configuration for this connection
* @qosgen_shaping_low: qosgen shaping low configuration for this connection
* @qosgen_shaping_high: qosgen shaping high configuration for this connection
* @maxwr_low: maxwr low configuration for this connection
* @dynattr_mainctl: Dynamic attribute main control register for this connection
*
*/
struct cam_camnoc_specific {
enum cam_camnoc_port_type port_type;
const char *port_name;
bool enable;
struct cam_cpas_reg priority_lut_low;
struct cam_cpas_reg priority_lut_high;
struct cam_cpas_reg urgency;
struct cam_cpas_reg danger_lut;
struct cam_cpas_reg safe_lut;
struct cam_cpas_reg ubwc_ctl;
struct cam_cpas_reg flag_out_set0_low;
struct cam_cpas_reg qosgen_mainctl;
struct cam_cpas_reg qosgen_shaping_low;
struct cam_cpas_reg qosgen_shaping_high;
struct cam_cpas_reg maxwr_low;
struct cam_cpas_reg dynattr_mainctl;
};
/**
* struct cam_camnoc_irq_sbm : Sideband manager settings for all CAMNOC IRQs
*
* @sbm_enable: SBM settings for IRQ enable
* @sbm_status: SBM settings for IRQ status
* @sbm_clear: SBM settings for IRQ clear
*
*/
struct cam_camnoc_irq_sbm {
struct cam_cpas_reg sbm_enable;
struct cam_cpas_reg sbm_status;
struct cam_cpas_reg sbm_clear;
};
/**
* struct cam_camnoc_irq_err : Error settings specific to each CAMNOC IRQ
*
* @irq_type: Type of IRQ
* @enable: Whether to enable error settings for this IRQ
* @sbm_port: Corresponding SBM port for this IRQ
* @err_enable: Error enable settings for this IRQ
* @err_status: Error status settings for this IRQ
* @err_clear: Error clear settings for this IRQ
*
*/
struct cam_camnoc_irq_err {
enum cam_camnoc_hw_irq_type irq_type;
bool enable;
uint32_t sbm_port;
struct cam_cpas_reg err_enable;
struct cam_cpas_reg err_status;
struct cam_cpas_reg err_clear;
};
/**
* struct cam_cpas_hw_errata_wa : Struct for HW errata workaround info
*
* @enable: Whether to enable this errata workround
* @data: HW Errata workaround data
*
*/
struct cam_cpas_hw_errata_wa {
bool enable;
union {
struct cam_cpas_reg reg_info;
} data;
};
/**
* struct cam_cpas_subpart_info : Struct for camera Hw parts info
*
* @num_bits: Number of entries in hw_bitmap_mask
* @hw_bitmap_mask: Contains Fuse flag and hw_map info
*
*/
struct cam_cpas_subpart_info {
uint32_t num_bits;
uint32_t hw_bitmap_mask[CAM_CPAS_PART_MAX_FUSE_BITS][CAM_CPAS_PART_MAX_FUSE_BIT_INFO];
};
/**
* struct cam_cpas_hw_errata_wa_list : List of HW Errata workaround info
*
* @camnoc_flush_slave_pending_trans: Errata workaround info for flushing
* camnoc slave pending transactions before turning off CPAS_TOP gdsc
* @tcsr_camera_hf_sf_ares_glitch: Errata workaround info from ignoring
* erroneous signals at camera start
* @enable_icp_clk_for_qchannel: Need to enable ICP clk while qchannel handshake
*/
struct cam_cpas_hw_errata_wa_list {
struct cam_cpas_hw_errata_wa camnoc_flush_slave_pending_trans;
struct cam_cpas_hw_errata_wa tcsr_camera_hf_sf_ares_glitch;
struct cam_cpas_hw_errata_wa enable_icp_clk_for_qchannel;
};
/**
* struct cam_camnoc_err_logger_info : CAMNOC error logger register offsets
*
* @mainctrl: Register offset for mainctrl
* @errvld: Register offset for errvld
* @errlog0_low: Register offset for errlog0_low
* @errlog0_high: Register offset for errlog0_high
* @errlog1_low: Register offset for errlog1_low
* @errlog1_high: Register offset for errlog1_high
* @errlog2_low: Register offset for errlog2_low
* @errlog2_high: Register offset for errlog2_high
* @errlog3_low: Register offset for errlog3_low
* @errlog3_high: Register offset for errlog3_high
*
*/
struct cam_camnoc_err_logger_info {
uint32_t mainctrl;
uint32_t errvld;
uint32_t errlog0_low;
uint32_t errlog0_high;
uint32_t errlog1_low;
uint32_t errlog1_high;
uint32_t errlog2_low;
uint32_t errlog2_high;
uint32_t errlog3_low;
uint32_t errlog3_high;
};
/**
* struct cam_cpas_test_irq_info : CAMNOC Test IRQ mask information
*
* @sbm_enable_mask: sbm mask to enable camnoc test irq
* @sbm_clear_mask: sbm mask to clear camnoc test irq
*
*/
struct cam_cpas_test_irq_info {
uint32_t sbm_enable_mask;
uint32_t sbm_clear_mask;
};
/**
* struct cam_cpas_cesta_crm_type : CESTA crm type information
*
* @CAM_CESTA_CRMB: CRM for bandwidth
* @CAM_CESTA_CRMC: CRM for clocks
*
*/
enum cam_cpas_cesta_crm_type {
CAM_CESTA_CRMB = 0,
CAM_CESTA_CRMC,
};
/**
* struct cam_vcd_info : cpas vcd(virtual clk domain) information
*
* @vcd_index: vcd number of each clk
* @type: type of clk domain CESTA_CRMB, CESTA_CRMC
* @clk_name: name of each vcd clk, exmp: cam_cc_ife_0_clk_src
*
*/
struct cam_cpas_vcd_info {
uint8_t index;
enum cam_cpas_cesta_crm_type type;
const char *clk;
};
/**
* struct cam_cpas_cesta_vcd_curr_lvl : cesta vcd operating level information
*
* @reg_offset: register offset
* @vcd_base_inc: each vcd base addr offset
* @num_vcds: number of vcds
*
*/
struct cam_cpas_cesta_vcd_curr_lvl {
uint32_t reg_offset;
uint32_t vcd_base_inc;
uint8_t num_vcds;
};
/**
* struct cam_cpas_cesta_vcd_reg_info : to hold all cesta register information
*
* @vcd_currol: vcd current perf level reg info
*
*/
struct cam_cpas_cesta_vcd_reg_info {
struct cam_cpas_cesta_vcd_curr_lvl vcd_currol;
};
/**
* struct cam_cpas_cesta_info : to hold all cesta register information
*
* @vcd_info: vcd info
* @num_vcds: number of vcds
* @cesta_reg_info: cesta vcds reg info
*
*/
struct cam_cpas_cesta_info {
struct cam_cpas_vcd_info *vcd_info;
int num_vcds;
struct cam_cpas_cesta_vcd_reg_info *cesta_reg_info;
};
/**
* struct cam_cpas_hw_cap_info : CPAS Hardware capability information
*
* @num_caps_registers: number of hw capability registers
* @hw_caps_offsets: array of hw cap register offsets
*
*/
struct cam_cpas_hw_cap_info {
uint32_t num_caps_registers;
uint32_t hw_caps_offsets[CAM_CPAS_MAX_CAPS_REGS];
};
/**
* struct cam_camnoc_info : Overall CAMNOC settings info
*
* @camnoc_type: type of camnoc (RT/NRT/COMBINED)
* @camnoc_name: name of camnoc (CAMNOC_RT/CAMNOC_NRT/CAMNOC_COMBINED)
* @reg_base: register base for camnoc RT/NRT/COMBINED register space
* @specific: Pointer to CAMNOC SPECIFICTONTTPTR settings
* @specific_size: Array size of SPECIFICTONTTPTR settings
* @irq_sbm: Pointer to CAMNOC IRQ SBM settings
* @irq_err: Pointer to CAMNOC IRQ Error settings
* @irq_err_size: Array size of IRQ Error settings
* @err_logger: Pointer to CAMNOC IRQ Error logger read registers
* @errata_wa_list: HW Errata workaround info
* @test_irq_info: CAMNOC Test IRQ info
* @cesta_info: cpas cesta reg info
*
*/
struct cam_camnoc_info {
/* Below fields populated at probe on camera version */
enum cam_camnoc_hw_type camnoc_type;
char *camnoc_name;
enum cam_cpas_reg_base reg_base;
/* Below fields populated from the cpas header */
struct cam_camnoc_specific *specific;
int specific_size;
struct cam_camnoc_irq_sbm *irq_sbm;
struct cam_camnoc_irq_err *irq_err;
int irq_err_size;
struct cam_camnoc_err_logger_info *err_logger;
struct cam_cpas_hw_errata_wa_list *errata_wa_list;
struct cam_cpas_test_irq_info test_irq_info;
struct cam_cpas_cesta_info *cesta_info;
};
/**
* struct cam_cpas_work_payload : Struct for cpas work payload data
*
* @camnoc_idx: index to camnoc info array
* @hw: Pointer to HW info
* @irq_status: IRQ status value
* @irq_data: IRQ data
* @workq_scheduled_ts: workqueue scheduled timestamp
* @work: Work handle
*
*/
struct cam_cpas_work_payload {
int8_t camnoc_idx;
struct cam_hw_info *hw;
uint32_t irq_status;
uint32_t irq_data;
ktime_t workq_scheduled_ts;
struct work_struct work;
};
/**
* struct cam_cpas_camnoc_qchannel : Cpas camnoc qchannel info
*
* @qchannel_ctrl: offset to configure to control camnoc qchannel interface
* @qchannel_status: offset to read camnoc qchannel interface status
*
*/
struct cam_cpas_camnoc_qchannel {
uint32_t qchannel_ctrl;
uint32_t qchannel_status;
};
/**
* struct cam_cpas_info: CPAS information
*
* @qchannel_info: CPAS qchannel info
* @hw_cap_info: CPAS Hardware capability information
* @num_qchannel: Number of qchannel
*/
struct cam_cpas_info {
struct cam_cpas_camnoc_qchannel *qchannel_info[CAM_CAMNOC_HW_TYPE_MAX];
struct cam_cpas_hw_cap_info hw_caps_info;
uint8_t num_qchannel;
};
/**
* struct cam_cpas_top_regs : CPAS Top registers
* @tpg_mux_sel_shift: TPG mux select shift value
* @tpg_mux_sel: For selecting TPG
* @tpg_mux_sel_enabled: TPG mux select enabled or not
*
*/
struct cam_cpas_top_regs {
uint32_t tpg_mux_sel_shift;
uint32_t tpg_mux_sel;
bool tpg_mux_sel_enabled;
};
#endif /* _CAM_CPASTOP_HW_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop100.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP100_H_
#define _CPASTOP100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2040, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1190,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE02,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
.value = 0x3,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IFE13,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
.value = 0x3,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.enable = false,
},
{
.port_type = CAM_CAMNOC_ICP,
.enable = false,
}
};
static struct cam_camnoc_err_logger_info cam170_cpas100_err_logger_offsets = {
.mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam170_cpas100_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = true,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
struct cam_camnoc_info cam170_cpas100_camnoc_info = {
.specific = &cam_cpas100_camnoc_specific[0],
.specific_size = sizeof(cam_cpas100_camnoc_specific) /
sizeof(cam_cpas100_camnoc_specific[0]),
.irq_sbm = &cam_cpas100_irq_sbm,
.irq_err = &cam_cpas100_irq_err[0],
.irq_err_size = sizeof(cam_cpas100_irq_err) /
sizeof(cam_cpas100_irq_err[0]),
.err_logger = &cam170_cpas100_err_logger_offsets,
.errata_wa_list = &cam170_cpas100_errata_wa_list,
};
static struct cam_cpas_info cam170_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP100_H_ */

538
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v150_100.h Normal file
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@ -0,0 +1,538 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V150_100_H_
#define _CPASTOP_V150_100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v150_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2040, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v150_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1190,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v150_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x2,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE02,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE13,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 0x5,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.enable = false,
},
{
.port_type = CAM_CAMNOC_ICP,
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2088,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam150_cpas100_err_logger_offsets = {
.mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam150_cpas100_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam150_cpas100_camnoc_info = {
.specific = &cam_cpas_v150_100_camnoc_specific[0],
.specific_size = sizeof(cam_cpas_v150_100_camnoc_specific) /
sizeof(cam_cpas_v150_100_camnoc_specific[0]),
.irq_sbm = &cam_cpas_v150_100_irq_sbm,
.irq_err = &cam_cpas_v150_100_irq_err[0],
.irq_err_size = sizeof(cam_cpas_v150_100_irq_err) /
sizeof(cam_cpas_v150_100_irq_err[0]),
.err_logger = &cam150_cpas100_err_logger_offsets,
.errata_wa_list = &cam150_cpas100_errata_wa_list,
};
static struct cam_cpas_info cam150_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V150_100_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v165_100.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V165_100_H_
#define _CPASTOP_V165_100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v165_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2240, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2248, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2280, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v165_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x4F08, /* ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x4F10, /* ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x4F18, /* ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3BA0, /* SPECIFIC_IFE0_MAIN_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3B90,
/* SPECIFIC_IFE0_MAIN_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x3B98, /* SPECIFIC_IFE0_MAIN_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x55A0, /* SPECIFIC_IFE1_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x5590, /* SPECIFIC_IFE1_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x5598, /* SPECIFIC_IFE1_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2F20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2F10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2F18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2BA0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2B90,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2B98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v165_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4230, /* CDM_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4234, /* CDM_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0, /* CDM_Urgency_Low */
.offset = 0x4238,
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4240, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4248, /* CDM_SAFELUT_LOW */
.value = 0xFFFF,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE01234_RDI_WRITE,
.port_name = "IFE01234_RDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3630, /* IFE01234_RDI_PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3634, /* IFE01234_RDI_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3638, /* IFE01234_RDI_LINEAR_URGENCY_LOW */
.mask = 0x1FF0,
.shift = 0x4,
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3640, /* IFE01234_RDI_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3648, /* IFE01234_RDI_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x3620, /* IFE01234_RDI_MAXWR_LOW */
.value = 0x0,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4808, /* IFE01234_RDI_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4820, /* IFE01234_RDI_QOSGEN_SHAPING_LOW */
.value = 0x07070707,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4824, /* IFE01234_RDI_QOSGEN_SHAPING_HIGH */
.value = 0x07070707,
},
},
{
.port_type = CAM_CAMNOC_IFE01_NRDI_WRITE,
.port_name = "IFE01_NRDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3A30, /* IFE01_NRDI_PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3A34, /* IFE01_NRDI_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x3A38, /* IFE01_NRDI_URGENCY_LOW */
/* IFE01_NRDI_URGENCY_LOW_WRITE_MASK */
.mask = 0x1FF0,
/* IFE01_NRDI_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3A40, /* IFE01_NRDI_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3A48, /* IFE01_NRDI_SAFELUT_LOW */
.value = 0xF,
},
/* no reg for this */
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3B88, /* IFE01_NRDI_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x3A20, /* IFE01_MAXWR_LOW */
.value = 0x0,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4708, /* IFE01_NRDI_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4720, /* IFE01_NRDI_QOSGEN_SHAPING_LOW */
.value = 0x07070707,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4724, /* IFE01_NRDI_QOSGEN_SHAPING_HIGH */
.value = 0x07070707,
},
},
{
.port_type = CAM_CAMNOC_IFE2_NRDI_WRITE,
.port_name = "IFE2_NRDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5430, /* IFE2_NDRI_PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* IFE2_NRDI_PRIORITYLUT_HIGH */
.offset = 0x5434,
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x5438, /* IFE2_NRDI_URGENCY_LOW */
/* IFE2_NRDI_URGENCY_LOW_WRITE_MASK */
.mask = 0x1FF0,
/* IFE2_NRDI_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5440, /* IFE2_NRDI_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5448, /* IFE2_NRDI_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5588, /* IFE2_NRDI_ENCCTL_LOW */
.value = 0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5420, /* IFE2_MAXWR_LOW */
.value = 0x0,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5188, /* IFE2_NRDI_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x51A0, /* IFE2_NRDI_QOSGEN_SHAPING_LOW */
.value = 0x07070707,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x51A4, /* IFE2_NRDI_QOSGEN_SHAPING_HIGH */
.value = 0x07070707,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.port_name = "IPE_BPS_LRME_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E30, /* IPE_BPS_LRME_RD_PRIORITYLUT_LOW */
.value = 0x33333333, /*Value is 0 in excel sheet */
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E34, /* IPE_BPS_LRME_RD_PRIORITYLUT_HIGH */
.value = 0x33333333, /*Value is 0 in excel sheet */
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x2E38, /* IPE_BPS_LRME_RD_URGENCY_LOW */
/* IPE_BPS_LRME_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* IPE_BPS_LRME_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E40, /* IPE_BPS_LRME_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E48, /* IPE_BPS_LRME_RD_SAFELUT_LOW */
.value = 0xFFFF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2F08, /* IPE_BPS_LRME_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.port_name = "IPE_BPS_LRME_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A30, /* IPE_BPS_LRME_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A34, /* IPE_BPS_LRME_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x2A38, /* IPE_BPS_LRME_WR_URGENCY_LOW */
/* IPE_BPS_LRME_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* IPE_BPS_LRME_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 0x30,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A40, /* IPE_BPS_LRME_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A48, /* IPE_BPS_LRME_WR_SAFELUT_LOW */
.value = 0xFFFF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2B88, /* IPE_BPS_LRME_WR_ENCCTL_LOW */
.value = 0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2A20, /* IBL_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.port_name = "JPEG",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2630, /* JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2634, /* JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x2638, /* JPEG_URGENCY_LOW */
.mask = 0x3F,
.shift = 0x0,
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2640, /* JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2648, /* JPEG_SAFELUT_LOW */
.value = 0xFFFF,
},
.ubwc_ctl = {
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2620, /* JPEG_MAXWR_LOW */
.value = 0x0,
},
},
{
/*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x5088,
.value = 0x50,
},
},
};
static struct cam_camnoc_err_logger_info cam165_cpas100_err_logger_offsets = {
.mainctrl = 0x4F08, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x4F10, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x4F20, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x4F24, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x4F28, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x4F2C, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x4F30, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x4F34, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x4F38, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x4F3C, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam165_cpas100_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2300, /* sbm_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam165_cpas100_camnoc_info = {
.specific = &cam_cpas_v165_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v165_100_camnoc_specific),
.irq_sbm = &cam_cpas_v165_100_irq_sbm,
.irq_err = &cam_cpas_v165_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v165_100_irq_err),
.err_logger = &cam165_cpas100_err_logger_offsets,
.errata_wa_list = &cam165_cpas100_errata_wa_list,
};
static struct cam_cpas_info cam165_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V165_100_H_ */

546
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v170_110.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V170_110_H_
#define _CPASTOP_V170_110_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas110_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2040, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas110_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1190,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas110_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x2,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE02,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IFE13,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.enable = false,
},
{
.port_type = CAM_CAMNOC_ICP,
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2088,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam170_cpas110_err_logger_offsets = {
.mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam170_cpas110_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam170_cpas110_camnoc_info = {
.specific = &cam_cpas110_camnoc_specific[0],
.specific_size = sizeof(cam_cpas110_camnoc_specific) /
sizeof(cam_cpas110_camnoc_specific[0]),
.irq_sbm = &cam_cpas110_irq_sbm,
.irq_err = &cam_cpas110_irq_err[0],
.irq_err_size = sizeof(cam_cpas110_irq_err) /
sizeof(cam_cpas110_irq_err[0]),
.err_logger = &cam170_cpas110_err_logger_offsets,
.errata_wa_list = &cam170_cpas110_errata_wa_list,
};
static struct cam_cpas_info cam170_cpas110_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V170_110_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v170_200.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V170_200_H_
#define _CPASTOP_V170_200_H_
#define TEST_IRQ_ENABLE 0
#define TCSR_CONN_RESET 0x0
#define TCSR_CONN_SET 0x3
static struct cam_camnoc_irq_sbm cam_cpas_v170_200_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2040, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v170_200_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1190,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v170_200_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x2,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE02,
.port_name = "IFE02",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2420, /* IFE02_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE13,
.port_name = "IFE13",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2620, /* IFE13_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.port_name = "IPE_BPS_LRME_RD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.port_name = "IPE_BPS_LRME_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2A20, /* IPE_BPS_LRME_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.port_name = "JPEG",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2C20, /* IPE_BPS_LRME_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_FD,
.port_name = "FD",
.enable = false,
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2088,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam170_cpas200_err_logger_offsets = {
.mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam170_cpas200_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam170_cpas200_camnoc_info = {
.specific = &cam_cpas_v170_200_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v170_200_camnoc_specific),
.irq_sbm = &cam_cpas_v170_200_irq_sbm,
.irq_err = &cam_cpas_v170_200_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v170_200_irq_err),
.err_logger = &cam170_cpas200_err_logger_offsets,
.errata_wa_list = &cam170_cpas200_errata_wa_list,
};
static struct cam_cpas_info cam170_cpas200_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V170_200_H_ */

566
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v175_100.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V175_100_H_
#define _CPASTOP_V175_100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v175_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2040, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v175_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1190,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v175_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x2,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE02,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IFE13,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.enable = false,
},
{
.port_type = CAM_CAMNOC_ICP,
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2088,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam175_cpas100_err_logger_offsets = {
.mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam175_cpas100_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam175_cpas100_camnoc_info = {
.specific = &cam_cpas_v175_100_camnoc_specific[0],
.specific_size = sizeof(cam_cpas_v175_100_camnoc_specific) /
sizeof(cam_cpas_v175_100_camnoc_specific[0]),
.irq_sbm = &cam_cpas_v175_100_irq_sbm,
.irq_err = &cam_cpas_v175_100_irq_err[0],
.irq_err_size = sizeof(cam_cpas_v175_100_irq_err) /
sizeof(cam_cpas_v175_100_irq_err[0]),
.err_logger = &cam175_cpas100_err_logger_offsets,
.errata_wa_list = &cam175_cpas100_errata_wa_list,
};
static struct cam_cpas_info cam175_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V175_100_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v175_101.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V175_101_H_
#define _CPASTOP_V175_101_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v175_101_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2040, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v175_101_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1190,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v175_101_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x2,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE02,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IFE13,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
.value = 0x66666543,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.enable = false,
},
{
.port_type = CAM_CAMNOC_ICP,
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2088,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam175_cpas101_err_logger_offsets = {
.mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam175_cpas101_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam175_cpas101_camnoc_info = {
.specific = &cam_cpas_v175_101_camnoc_specific[0],
.specific_size = sizeof(cam_cpas_v175_101_camnoc_specific) /
sizeof(cam_cpas_v175_101_camnoc_specific[0]),
.irq_sbm = &cam_cpas_v175_101_irq_sbm,
.irq_err = &cam_cpas_v175_101_irq_err[0],
.irq_err_size = sizeof(cam_cpas_v175_101_irq_err) /
sizeof(cam_cpas_v175_101_irq_err[0]),
.err_logger = &cam175_cpas101_err_logger_offsets,
.errata_wa_list = &cam175_cpas101_errata_wa_list,
};
static struct cam_cpas_info cam175_cpas101_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V175_101_H_ */

768
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v175_120.h Normal file
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@ -0,0 +1,768 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V175_120_H_
#define _CPASTOP_V175_120_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v175_120_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2240, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2248, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2280, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v175_120_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x4F08, /* ERRORLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x4F10, /* ERRORLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x4F18, /* ERRORLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3BA0, /* SPECIFIC_IFE02_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3B90, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x3B98, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x55a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x5590, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x5598, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2F20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2F10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2F18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2Ba0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2B90,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2B98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v175_120_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4230, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4234, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
/* cdm_main_SpecificToNttpTr_Urgency_Low */
.offset = 0x4238,
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x2,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4240, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4248, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE0123_RDI_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IFE0123_PRIORITYLUT_LOW */
.offset = 0x3630,
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IFE0123_PRIORITYLUT_HIGH */
.offset = 0x3634,
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x3638, /* SPECIFIC_IFE0123_URGENCY_LOW */
/* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3640, /* SPECIFIC_IFE0123_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3648, /* SPECIFIC_IFE0123_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE0_NRDI_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3A30, /* SPECIFIC_IFE0_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3A34, /* SPECIFIC_IFE0_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x3A38, /* SPECIFIC_IFE0_URGENCY_LOW */
/* SPECIFIC_IFE0_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE0_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3A40, /* SPECIFIC_IFE0_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3A48, /* SPECIFIC_IFE0_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3B88, /* SPECIFIC_IFE0_ENCCTL_LOW */
.value = 1,
},
},
{
/* IFE0/1 RDI READ PATH */
.port_type = CAM_CAMNOC_IFE01_RDI_READ,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3230, /* SPECIFIC_IFE1_PRIORITYLUT_LOW */
.value = 0x44443333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3234, /* SPECIFIC_IFE1_PRIORITYLUT_HIGH */
.value = 0x66665555,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x3238, /* SPECIFIC_IFE1_URGENCY_LOW */
/* SPECIFIC_IFE1_URGENCY_LOW_WRITE_MASK */
.mask = 0x7,
/* SPECIFIC_IFE1_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3240, /* SPECIFIC_IFE1_DANGERLUT_LOW */
.value = 0x00000000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3248, /* SPECIFIC_IFE1_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE1_NRDI_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5430, /* SPECIFIC_IFE1_WR_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IFE1_WR_PRIORITYLUT_HIGH */
.offset = 0x5434,
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x5438, /* SPECIFIC_IFE1_WR_URGENCY_LOW */
/* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5440, /* SPECIFIC_IFE1_WR_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5448, /* SPECIFIC_IFE1_WR_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5588, /* SPECIFIC_IFE1_WR_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x2E38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2F08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A30, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A34, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x2A38, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A40, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A48, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 0,
},
},
{
.port_type = CAM_CAMNOC_IPE_VID_DISP_WRITE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_LOW */
.offset = 0x5E30,
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_HIGH */
.offset = 0x5E34,
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW */
.offset = 0x5E38,
/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_MASK */
.mask = 0x70,
/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC__IPE_VID_DISP_DANGERLUT_LOW */
.offset = 0x5E40,
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IPE_VID_DISP_SAFELUT_LOW */
.offset = 0x5E48,
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5F88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2630, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2634, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2638, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2640, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2648, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E30, /* SPECIFIC_FD_PRIORITYLUT_LOW */
.value = 0x44444444,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E34, /* SPECIFIC_FD_PRIORITYLUT_HIGH */
.value = 0x44444444,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E38, /* SPECIFIC_FD_URGENCY_LOW */
.value = 0x44,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E40, /* SPECIFIC_FD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E48, /* SPECIFIC_FD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
/*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/
.port_type = CAM_CAMNOC_ICP,
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2288,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam175_cpas120_err_logger_offsets = {
.mainctrl = 0x4F08, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x4F10, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x4F20, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x4F24, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x4F28, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x4F2c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x4F30, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x4F34, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x4F38, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x4F3c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam175_cpas120_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2300, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam175_cpas120_camnoc_info = {
.specific = &cam_cpas_v175_120_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v175_120_camnoc_specific),
.irq_sbm = &cam_cpas_v175_120_irq_sbm,
.irq_err = &cam_cpas_v175_120_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v175_120_irq_err),
.err_logger = &cam175_cpas120_err_logger_offsets,
.errata_wa_list = &cam175_cpas120_errata_wa_list,
};
static struct cam_cpas_info cam175_cpas120_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V175_120_H_ */

840
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v175_130.h Normal file
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@ -0,0 +1,840 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V175_130_H_
#define _CPASTOP_V175_130_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v175_130_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2240, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2248, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2280, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v175_130_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x4F08, /* ERRORLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x4F10, /* ERRORLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x4F18, /* ERRORLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3BA0, /* SPECIFIC_IFE0_MAIN_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
/* SPECIFIC_IFE0_MAIN_ENCERRSTATUS_LOW */
.offset = 0x3B90,
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x3B98, /* SPECIFIC_IFE0_MAIN_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x55A0, /* SPECIFIC_IFE1_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
/* SPECIFIC_IFE1_WR_ENCERRSTATUS_LOW */
.offset = 0x5590,
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x5598, /* SPECIFIC_IFE1_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2F20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2F10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2F18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2BA0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2B90,
/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2B98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = true,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v175_130_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4230, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4234, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
/* cdm_main_SpecificToNttpTr_Urgency_Low */
.offset = 0x4238,
.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
.value = 0x2,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4240, /* SPECIFIC_CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4248, /* SPECIFIC_CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE0123_RDI_WRITE,
.port_name = "IFE0123_RDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IFE0123_PRIORITYLUT_LOW */
.offset = 0x3630,
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IFE0123_PRIORITYLUT_HIGH */
.offset = 0x3634,
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x3638, /* SPECIFIC_IFE0123_URGENCY_LOW */
/* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3640, /* SPECIFIC_IFE0123_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3648, /* SPECIFIC_IFE0123_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x3620, /* IFE0123_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE0_NRDI_WRITE,
.port_name = "IFE0_NRDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3A30, /* SPECIFIC_IFE0_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3A34, /* SPECIFIC_IFE0_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x3A38, /* SPECIFIC_IFE0_URGENCY_LOW */
/* SPECIFIC_IFE0_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE0_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3A40, /* SPECIFIC_IFE0_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3A48, /* SPECIFIC_IFE0_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3B88, /* SPECIFIC_IFE0_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x3A20, /* IFE0_MAXWR_LOW */
.value = 0x0,
},
},
{
/* IFE0/1 RDI READ PATH */
.port_type = CAM_CAMNOC_IFE01_RDI_READ,
.port_name = "IFE01_RDI_RD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3230, /* SPECIFIC_IFE1_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3234, /* SPECIFIC_IFE1_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x3238, /* SPECIFIC_IFE1_URGENCY_LOW */
/* SPECIFIC_IFE1_URGENCY_LOW_WRITE_MASK */
.mask = 0x7,
/* SPECIFIC_IFE1_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x0,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3240, /* SPECIFIC_IFE1_DANGERLUT_LOW */
.value = 0x00000000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x3248, /* SPECIFIC_IFE1_SAFELUT_LOW */
.value = 0xFFFFFFFF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE1_NRDI_WRITE,
.port_name = "IFE1_NRDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5430, /* SPECIFIC_IFE1_WR_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IFE1_WR_PRIORITYLUT_HIGH */
.offset = 0x5434,
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x5438, /* SPECIFIC_IFE1_WR_URGENCY_LOW */
/* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5440, /* SPECIFIC_IFE1_WR_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5448, /* SPECIFIC_IFE1_WR_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5588, /* SPECIFIC_IFE1_WR_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5420, /* IFE1_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
.port_name = "IPE_BPS_LRME_RD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x2E38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
.mask = 0x7,
/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
.shift = 0x0,
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2F08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
.port_name = "IPE_BPS_LRME_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A30, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A34, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
.offset = 0x2A38, /* SPECIFIC_IBL_WR_URGENCY_LOW */
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
.mask = 0x70,
/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
.shift = 0x4,
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A40, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2A48, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2A20, /* IBL_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE_VID_DISP_WRITE,
.port_name = "IPE_VID_DISP_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_LOW */
.offset = 0x5E30,
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_HIGH */
.offset = 0x5E34,
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 1,
/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW */
.offset = 0x5E38,
/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_MASK */
.mask = 0x70,
/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_SHIFT */
.shift = 0x4,
.value = 3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC__IPE_VID_DISP_DANGERLUT_LOW */
.offset = 0x5E40,
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* SPECIFIC_IPE_VID_DISP_SAFELUT_LOW */
.offset = 0x5E48,
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5F88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5E20, /* IPE_VID_DISP_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.port_name = "JPEG",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2630, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2634, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2638, /* SPECIFIC_JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2640, /* SPECIFIC_JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2648, /* SPECIFIC_JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2620, /* JPEG_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_FD,
.port_name = "FD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E30, /* SPECIFIC_FD_PRIORITYLUT_LOW */
.value = 0x44444444,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E34, /* SPECIFIC_FD_PRIORITYLUT_HIGH */
.value = 0x44444444,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E38, /* SPECIFIC_FD_URGENCY_LOW */
.value = 0x44,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E40, /* SPECIFIC_FD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3E48, /* SPECIFIC_FD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x3E20, /* FD_MAXWR_LOW */
.value = 0x0,
},
},
{
/*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = true,
.flag_out_set0_low = {
.enable = true,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2288,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam175_cpas130_err_logger_offsets = {
.mainctrl = 0x4F08, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x4F10, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x4F20, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x4F24, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x4F28, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x4F2c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x4F30, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x4F34, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x4F38, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x4F3c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam175_cpas130_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2300, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
/* TZ owned register */
.tcsr_camera_hf_sf_ares_glitch = {
.enable = true,
.data.reg_info = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
/* TCSR_CAMERA_HF_SF_ARES_GLITCH_MASK */
.offset = 0x01FCA08C,
.value = 0x4, /* set bit[2] to 1 */
},
},
};
static struct cam_camnoc_info cam175_cpas130_camnoc_info = {
.specific = &cam_cpas_v175_130_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v175_130_camnoc_specific),
.irq_sbm = &cam_cpas_v175_130_irq_sbm,
.irq_err = &cam_cpas_v175_130_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v175_130_irq_err),
.err_logger = &cam175_cpas130_err_logger_offsets,
.errata_wa_list = &cam175_cpas130_errata_wa_list,
};
static struct cam_cpas_info cam175_cpas130_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V175_130_H_ */

772
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v480_100.h Normal file
View File

@ -0,0 +1,772 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V480_100_H_
#define _CPASTOP_V480_100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v480_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3840, /* SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
(TEST_IRQ_ENABLE ?
0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3848, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v480_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x7008, /* ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x7010, /* ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x7018, /* ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x1BA0, /* IFE_UBWC_STATS_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1B90, /* IFE_UBWC_STATS_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1B98, /* IFE_UBWC_STATS_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2520, /* IPE1_BPS_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2510, /* IPE1_BPS_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2518, /* IPE1_BPS_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x1F20, /* IPE0_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1F10, /* IPE0_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1F18, /* IPE0_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x29A0, /* IPE_BPS_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2990,
/* IPE_BPS_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2998, /* IPE_BPS_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v480_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* CDM_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* CDM_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x38, /* CDM_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.port_name = "FD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x630, /* FD_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x634, /* FD_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x638, /* FD_URGENCY_LOW */
.value = 0x33,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x640, /* FD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x648, /* FD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x620, /* FD_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_LINEAR,
.port_name = "IFE_LINEAR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA30, /* IFE_LINEAR_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA34, /* IFE_LINEAR_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA38, /* IFE_LINEAR_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0xA40, /* IFE_LINEAR_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0xA48, /* IFE_LINEAR_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0xA20, /* IFE_LINEAR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_RD,
.port_name = "IFE_RDI_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* IFE_RDI_RD_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* IFE_RDI_RD_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1038, /* IFE_RDI_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1040, /* IFE_RDI_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1048, /* IFE_RDI_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR,
.port_name = "IFE_RDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* IFE_RDI_WR_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* IFE_RDI_WR_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* IFE_RDI_WR_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1440, /* IFE_RDI_WR_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1448, /* IFE_RDI_WR_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x1420, /* IFE_RDI_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
.port_name = "IFE_UBWC_STATS",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A30, /* IFE_UBWC_STATS_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A34, /* IFE_UBWC_STATS_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A38, /* IFE_UBWC_STATS_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1A40, /* IFE_UBWC_STATS_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1A48, /* IFE_UBWC_STATS_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1B88, /* IFE_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x1A20, /* IFE_UBWC_STATS_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE0_RD,
.port_name = "IPE0_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E30, /* IPE0_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E34, /* IPE0_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E38, /* IPE0_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E40, /* IPE0_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E48, /* IPE0_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE1_BPS_RD,
.port_name = "IPE1_BPS_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2430, /* IPE1_BPS_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2434, /* IPE1_BPS_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2438, /* IPE1_BPS_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2440, /* IPE1_BPS_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2448, /* IPE1_BPS_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_WR,
.port_name = "IPE_BPS_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2830, /* IPE_BPS_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2834, /* IPE_BPS_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2838, /* IPE_BPS_WR_URGENCY_LOW */
.value = 0x30,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2840, /* IPE_BPS_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2848, /* IPE_BPS_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
.value = 1,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2820, /* IPE_BPS_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.port_name = "JPEG",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E30, /* JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E34, /* JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E38, /* JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E40, /* JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E48, /* JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2E20, /* JPEG_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = true,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2088,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam480_cpas100_err_logger_offsets = {
.mainctrl = 0x7008, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x7010, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x7020, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x7024, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x7028, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x702c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x7030, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x7034, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x7038, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x703c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam480_cpas100_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam480_cpas100_camnoc_info = {
.specific = &cam_cpas_v480_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v480_100_camnoc_specific),
.irq_sbm = &cam_cpas_v480_100_irq_sbm,
.irq_err = &cam_cpas_v480_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v480_100_irq_err),
.err_logger = &cam480_cpas100_err_logger_offsets,
.errata_wa_list = &cam480_cpas100_errata_wa_list,
};
static struct cam_cpas_info cam480_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V480_100_H_ */

719
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v480_custom.h Normal file
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@ -0,0 +1,719 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V480_CUSTOM_H_
#define _CPASTOP_V480_CUSTOM_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v480_custom_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3840, /* SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
(TEST_IRQ_ENABLE ?
0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3848, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v480_custom_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x7008, /* ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x7010, /* ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x7018, /* ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x1BA0, /* IFE_UBWC_STATS_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1B90, /* IFE_UBWC_STATS_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1B98, /* IFE_UBWC_STATS_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2520, /* IPE1_BPS_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2510, /* IPE1_BPS_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2518, /* IPE1_BPS_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x1F20, /* IPE0_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1F10, /* IPE0_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1F18, /* IPE0_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x29A0, /* IPE_BPS_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2990,
/* IPE_BPS_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2998, /* IPE_BPS_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v480_custom_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* CDM_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* CDM_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x38, /* CDM_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_FD,
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x630, /* FD_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x634, /* FD_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x638, /* FD_URGENCY_LOW */
.value = 0x33,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x640, /* FD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x648, /* FD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE_LINEAR,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA30, /* IFE_LINEAR_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA34, /* IFE_LINEAR_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA38, /* IFE_LINEAR_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0xA40, /* IFE_LINEAR_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0xA48, /* IFE_LINEAR_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_RD,
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* IFE_RDI_RD_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* IFE_RDI_RD_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1038, /* IFE_RDI_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1040, /* IFE_RDI_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1048, /* IFE_RDI_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* IFE_RDI_WR_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* IFE_RDI_WR_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* IFE_RDI_WR_URGENCY_LOW */
.value = 0x1070,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1440, /* IFE_RDI_WR_DANGERLUT_LOW */
.value = 0xFFFFFFF0,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1448, /* IFE_RDI_WR_SAFELUT_LOW */
.value = 0x1,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A30, /* IFE_UBWC_STATS_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A34, /* IFE_UBWC_STATS_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A38, /* IFE_UBWC_STATS_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1A40, /* IFE_UBWC_STATS_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1A48, /* IFE_UBWC_STATS_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1B88, /* IFE_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE0_RD,
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E30, /* IPE0_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E34, /* IPE0_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E38, /* IPE0_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E40, /* IPE0_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E48, /* IPE0_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE1_BPS_RD,
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2430, /* IPE1_BPS_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2434, /* IPE1_BPS_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2438, /* IPE1_BPS_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2440, /* IPE1_BPS_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2448, /* IPE1_BPS_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_WR,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2830, /* IPE_BPS_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2834, /* IPE_BPS_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2838, /* IPE_BPS_WR_URGENCY_LOW */
.value = 0x30,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2840, /* IPE_BPS_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2848, /* IPE_BPS_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
.value = 1,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E30, /* JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E34, /* JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E38, /* JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E40, /* JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E48, /* JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.enable = true,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x2088,
.value = 0x100000,
},
},
};
static struct cam_camnoc_err_logger_info cam480_custom_err_logger_offsets = {
.mainctrl = 0x7008, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x7010, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x7020, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x7024, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x7028, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x702c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x7030, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x7034, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x7038, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x703c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam480_custom_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x2100, /* SidebandManager_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam480_custom_camnoc_info = {
.specific = &cam_cpas_v480_custom_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v480_custom_camnoc_specific),
.irq_sbm = &cam_cpas_v480_custom_irq_sbm,
.irq_err = &cam_cpas_v480_custom_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v480_custom_irq_err),
.err_logger = &cam480_custom_err_logger_offsets,
.errata_wa_list = &cam480_cpas100_errata_wa_list,
};
static struct cam_cpas_info cam480_custom_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
};
#endif /* _CPASTOP_V480_CUSTOM_H_ */

271
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v520_100.h Normal file
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@ -0,0 +1,271 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V520_100_H_
#define _CPASTOP_V520_100_H_
static struct cam_camnoc_irq_sbm cam_cpas_v520_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA40, /* SBM_FAULTINEN0_LOW */
.value = 0x1, /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */
.value = 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v520_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = false,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v520_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE30, /* CDM_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE38, /* CDM_URGENCY_LOW */
.value = 0x00000003,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE40, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE48, /* CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_TFE,
.port_name = "TFE",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_LOW */
.offset = 0x30,
.value = 0x44443333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_HIGH */
.offset = 0x34,
.value = 0x66665555,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x38, /* TFE_URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x40, /* TFE_DANGERLUT_LOW */
.value = 0xffff0000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x48, /* TFE_SAFELUT_LOW */
.value = 0x00000003,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x20, /* TFE_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE,
.port_name = "OPE",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* OPE_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* OPE_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x438, /* OPE_URGENCY_LOW */
.value = 0x00000033,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* OPE_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* OPE_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x420, /* OPE_MAXWR_LOW */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam520_cpas100_err_logger_offsets = {
.mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_camnoc_info cam520_cpas100_camnoc_info = {
.specific = &cam_cpas_v520_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v520_100_camnoc_specific),
.irq_sbm = &cam_cpas_v520_100_irq_sbm,
.irq_err = &cam_cpas_v520_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v520_100_irq_err),
.err_logger = &cam520_cpas100_err_logger_offsets,
.errata_wa_list = NULL,
.test_irq_info = {
.sbm_enable_mask = 0x2,
.sbm_clear_mask = 0x2,
}
};
static struct cam_cpas_camnoc_qchannel cam520_cpas100_qchannel_info = {
.qchannel_ctrl = 0x14,
.qchannel_status = 0x18,
};
static struct cam_cpas_info cam520_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam520_cpas100_qchannel_info},
.num_qchannel = 1,
};
#endif /* _CPASTOP_V520_100_H_ */

272
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v540_100.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V540_100_H_
#define _CPASTOP_V540_100_H_
static struct cam_camnoc_irq_sbm cam_cpas_v540_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA40, /* SBM_FAULTINEN0_LOW */
.value = 0x1, /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */
.value = 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v540_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = false,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
// TODO: Need to update cam_cpas_v540_100_camnoc_specific values based on QoS
static struct cam_camnoc_specific
cam_cpas_v540_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE30, /* CDM_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE38, /* CDM_URGENCY_LOW */
.value = 0x00000003,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE40, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE48, /* CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_TFE,
.port_name = "TFE",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_LOW */
.offset = 0x30,
.value = 0x44443333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_HIGH */
.offset = 0x34,
.value = 0x66665555,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x38, /* TFE_URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x40, /* TFE_DANGERLUT_LOW */
.value = 0xffff0000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x48, /* TFE_SAFELUT_LOW */
.value = 0x00000003,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x20, /* TFE_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE,
.port_name = "OPE",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* OPE_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* OPE_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x438, /* OPE_URGENCY_LOW */
.value = 0x00000033,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* OPE_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* OPE_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x420, /* OPE_MAXWR_LOW */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam540_cpas100_err_logger_offsets = {
.mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_camnoc_info cam540_cpas100_camnoc_info = {
.specific = &cam_cpas_v540_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v540_100_camnoc_specific),
.irq_sbm = &cam_cpas_v540_100_irq_sbm,
.irq_err = &cam_cpas_v540_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v540_100_irq_err),
.err_logger = &cam540_cpas100_err_logger_offsets,
.errata_wa_list = NULL,
.test_irq_info = {
.sbm_enable_mask = 0x2,
.sbm_clear_mask = 0x2,
}
};
static struct cam_cpas_camnoc_qchannel cam540_cpas100_qchannel_info = {
.qchannel_ctrl = 0x14,
.qchannel_status = 0x18,
};
static struct cam_cpas_info cam540_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam540_cpas100_qchannel_info},
.num_qchannel = 1,
};
#endif /* _CPASTOP_V540_100_H_ */

365
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v545_100.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V545_100_H_
#define _CPASTOP_V545_100_H_
static struct cam_camnoc_irq_sbm cam_cpas_v545_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA40, /* SBM_FAULTINEN0_LOW */
.value = 0x1, /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */
.value = 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v545_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = false,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v545_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE30, /* CDM_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE38, /* CDM_URGENCY_LOW */
.value = 0x00000003,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE40, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE48, /* CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_TFE,
.port_name = "TFE",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_LOW */
.offset = 0x30,
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_HIGH */
.offset = 0x34,
.value = 0x66666655,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x38, /* TFE_URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x40, /* TFE_DANGERLUT_LOW */
.value = 0xffff0000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x48, /* TFE_SAFELUT_LOW */
.value = 0x00000003,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x20, /* TFE_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_TFE_1,
.port_name = "TFE_1",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_LOW */
.offset = 0x4030,
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_HIGH */
.offset = 0x4034,
.value = 0x66666655,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4038, /* TFE_URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x4040, /* TFE_DANGERLUT_LOW */
.value = 0xffff0000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x4048, /* TFE_SAFELUT_LOW */
.value = 0x00000003,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x4020, /* TFE_1_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_TFE_2,
.port_name = "TFE_2",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_LOW */
.offset = 0x5030,
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_HIGH */
.offset = 0x5034,
.value = 0x66666655,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5038, /* TFE_URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5040, /* TFE_DANGERLUT_LOW */
.value = 0xffff0000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x5048, /* TFE_SAFELUT_LOW */
.value = 0x00000003,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5020, /* TFE_2_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE,
.port_name = "OPE",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* OPE_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* OPE_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x438, /* OPE_URGENCY_LOW */
.value = 0x00000033,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* OPE_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* OPE_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x420, /* OPE_MAXWR_LOW */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam545_cpas100_err_logger_offsets = {
.mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_camnoc_info cam545_cpas100_camnoc_info = {
.specific = &cam_cpas_v545_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v545_100_camnoc_specific),
.irq_sbm = &cam_cpas_v545_100_irq_sbm,
.irq_err = &cam_cpas_v545_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v545_100_irq_err),
.err_logger = &cam545_cpas100_err_logger_offsets,
.errata_wa_list = NULL,
.test_irq_info = {
.sbm_enable_mask = 0x2,
.sbm_clear_mask = 0x2,
}
};
static struct cam_cpas_camnoc_qchannel cam545_cpas100_qchannel_info = {
.qchannel_ctrl = 0x14,
.qchannel_status = 0x18,
};
static struct cam_cpas_info cam545_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam545_cpas100_qchannel_info},
.num_qchannel = 1,
};
#endif /* _CPASTOP_V545_100_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v570_100.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V570_100_H_
#define _CPASTOP_V570_100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v570_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x7A40, /* SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x1000 | /* SBM_FAULTINEN0_LOW_PORT12_MASK */
(TEST_IRQ_ENABLE ?
0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x7A48, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x7A80, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v570_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x7908, /* ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x7910, /* ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x7918, /* ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x63A0, /* IFE_NIU_0_NIU_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6390,
/* IFE_NIU_0_NIU_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6398, /* IFE_NIU_0_NIU_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6B20, /* NRT_NIU_0_NIU_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6B10, /* NRT_NIU_0_NIU_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6B18, /* NRT_NIU_0_NIU_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6F20, /* NRT_NIU_2_NIU_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6F10, /* NRT_NIU_2_NIU_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6F18, /* NRT_NIU_2_NIU_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6DA0, /* NRT_NIU_1_NIU_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6D90,
/* NRT_NIU_1_NIU_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6D98, /* NRT_NIU_1_NIU_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x7A88, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x7A90, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x7A88, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x7A90, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v570_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6030, /* CDM_NIU_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6034, /* CDM_NIU_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6038, /* CDM_NIU_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6040, /* CDM_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6048, /* CDM_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5008, /* CDM_QOSGEN_MAINCTL_LOW */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5020, /* CDM_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5024, /* CDM_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_LINEAR,
.port_name = "IFE_LINEAR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6430, /* IFE_NIU_1_NIU_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6434, /* IFE_NIU_1_NIU_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6438, /* IFE_NIU_1_NIU_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6440, /* IFE_NIU_1_NIU_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6448, /* IFE_NIU_1_NIU_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5108, /* IFE_NIU_1_NIU_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5120, /* IFE_NIU_1_NIU_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5124, /* IFE_NIU_1_NIU_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x6420, /* IFE_NIU_1_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_RD,
.port_name = "IFE_RDI_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6630, /* IFE_NIU_2_NIU_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6634, /* IFE_NIU_2_NIU_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6638, /* IFE_NIU_2_NIU_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6640, /* IFE_NIU_2_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6648, /* IFE_NIU_2_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5188, /* IFE_NIU_2_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x51A0, /* IFE_NIU_2_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x51A4, /* IFE_NIU_2_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR,
.port_name = "IFE_RDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6830, /* IFE_NIU_3_NIU_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6834, /* IFE_NIU_3_NIU_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6838, /* IFE_NIU_3_NIU_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6840, /* IFE_NIU_3_NIU_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6848, /* IFE_NIU_3_NIU_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5208, /* IFE_NIU_3_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5220, /* IFE_NIU_3_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5224, /* IFE_NIU_3_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x6820, /* IFE_NIU_3_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
.port_name = "IFE_UBWC_STATS",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6230, /* IFE_NIU_0_NIU_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6234,
/* IFE_NIU_0_NIU_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6238, /* IFE_NIU_0_NIU_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6240, /* IFE_NIU_0_NIU_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x6248, /*IFE_NIU_0_NIU_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6388, /* IFE_NIU_0_NIU_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5088, /* IFE_NIU_0_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x50A0,
/* IFE_NIU_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x50A4,
/* IFE_NIU_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x6220, /* IFE_NIU_0_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE0_RD,
.port_name = "IPE0_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6E30, /* NRT_NIU_2_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6E34, /* NRT_NIU_2_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6E38, /* NRT_NIU_2_NIU_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6E40, /* NRT_NIU_2_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6E48, /* NRT_NIU_2_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6F08, /* NRT_NIU_2_NIU_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5388, /* NRT_NIU_2_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x53A0, /* NRT_NIU_2_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x53A4, /* NRT_NIU_2_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE1_BPS_RD,
.port_name = "IPE1_BPS_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6A30, /* NRT_NIU_0_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6A34, /* NRT_NIU_0_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6A38, /* NRT_NIU_0_NIU_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6A40, /* NRT_NIU_0_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6A48, /* NRT_NIU_0_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6B08, /* NRT_NIU_0_NIU_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5288, /* NRT_NIU_0_QOSGEN_MAINCTL */
.value = 0x0,
},
// TITAN_A_CAMNOC_cam_noc_amm_NRT_NIU_0_qosgen_Shaping_Low
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x52A0, /* NRT_NIU_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x52A4, /* NRT_NIU_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_WR,
.port_name = "IPE_BPS_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6C30, /* NRT_NIU_1_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6C34, /* NRT_NIU_1_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6C38, /* NRT_NIU_1_NIU_URGENCY_LOW */
.value = 0x30,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6C40, /* NRT_NIU_1_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6C48, /* NRT_NIU_1_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6D88, /* NRT_NIU_1_NIU_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5308, /* NRT_NIU_1_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5320, /* NRT_NIU_1_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5324, /* NRT_NIU_1_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x6C20, /* NRT_NIU_1_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.port_name = "JPEG",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7030, /* NRT_NIU_3_NIU_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7034, /* NRT_NIU_3_NIU_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7038, /* NRT_NIU_3_NIU_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7040, /* NRT_NIU_3_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7048, /* NRT_NIU_3_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5408, /* NRT_NIU_3_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5420, /* NRT_NIU_3_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5424, /* NRT_NIU_3_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x7020, /* NRT_NIU_3_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = true,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x7A88, /* SBM_FLAGOUTSET0_LOW */
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5488, /* ICP_QOSGEN_MAINCTL_LOW */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x54A0, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x54A4, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam570_cpas100_err_logger_offsets = {
.mainctrl = 0x7908, /* ERL_MAINCTL_LOW */
.errvld = 0x7910, /* ERL_ERRVLD_LOW */
.errlog0_low = 0x7920, /* ERL_ERRLOG0_LOW */
.errlog0_high = 0x7924, /* ERL_ERRLOG0_HIGH */
.errlog1_low = 0x7928, /* ERL_ERRLOG1_LOW */
.errlog1_high = 0x792c, /* ERL_ERRLOG1_HIGH */
.errlog2_low = 0x7930, /* ERL_ERRLOG2_LOW */
.errlog2_high = 0x7934, /* ERL_ERRLOG2_HIGH */
.errlog3_low = 0x7938, /* ERL_ERRLOG3_LOW */
.errlog3_high = 0x793c, /* ERL_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam570_cpas100_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
},
};
static struct cam_camnoc_info cam570_cpas100_camnoc_info = {
.specific = &cam_cpas_v570_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v570_100_camnoc_specific),
.irq_sbm = &cam_cpas_v570_100_irq_sbm,
.irq_err = &cam_cpas_v570_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v570_100_irq_err),
.err_logger = &cam570_cpas100_err_logger_offsets,
.errata_wa_list = &cam570_cpas100_errata_wa_list,
};
static struct cam_cpas_camnoc_qchannel cam570_cpas100_qchannel_info = {
.qchannel_ctrl = 0x5C,
.qchannel_status = 0x60,
};
static struct cam_cpas_info cam570_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam570_cpas100_qchannel_info},
.num_qchannel = 1,
};
#endif /* _CPASTOP_V570_100_H_ */

944
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v570_200.h Normal file
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@ -0,0 +1,944 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V570_200_H_
#define _CPASTOP_V570_200_H_
static struct cam_camnoc_irq_sbm cam_cpas_v570_200_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3840, /* SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x1000, /* SBM_FAULTINEN0_LOW_PORT12_MASK */
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3848, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
.value = 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v570_200_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x7008, /* ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x7010, /* ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x7018, /* ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x1BA0, /* IFE_UBWC_STATS_0_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1B90,
/* IFE_UBWC_STATS_0_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1B98, /* IFE_UBWC_STATS_0_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x2520, /* IPE1_BPS_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2510, /* IPE1_BPS_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2518, /* IPE1_BPS_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x1F20, /* IPE0_RD_DECERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x1F10, /* IPE0_RD_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x1F18, /* IPE0_RD_DECERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x29A0, /* IPE_BPS_WR_ENCERREN_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x2990,
/* IPE_BPS_WR_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x2998, /* IPE_BPS_WR_ENCERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
.value = 0x5,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v570_200_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x30, /* CDM_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34, /* CDM_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x38, /* CDM_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x40, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x48, /* CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x408, /* CDM_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x420, /* CDM_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x424, /* CDM_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_LINEAR,
.port_name = "IFE_LINEAR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA30, /* IFE_LINEAR_PRIORITYLUT_LOW */
.value = 0x66666666,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA34, /* IFE_LINEAR_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xA38, /* IFE_LINEAR_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0xA40, /* IFE_LINEAR_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0xA48, /* IFE_LINEAR_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE08, /* IFE_LINEAR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE20, /* IFE_LINEAR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE24, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0xA20, /* IFE_LINEAR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_RD,
.port_name = "IFE_RDI_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1030, /* IFE_RDI_RD_PRIORITYLUT_LOW */
.value = 0x0,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1034, /* IFE_RDI_RD_PRIORITYLUT_HIGH */
.value = 0x0,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1038, /* IFE_RDI_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1040, /* IFE_RDI_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1048, /* IFE_RDI_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF08, /* IFE_RDI_RD_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF20, /* IFE_RDI_RD_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF24, /* IFE_RDI_RD_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR,
.port_name = "IFE_RDI_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1430, /* IFE_RDI_WR_0_PRIORITYLUT_LOW */
.value = 0x66666666,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1434, /* IFE_RDI_WR_0_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1438, /* IFE_RDI_WR_0_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1440, /* IFE_RDI_WR_0_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1448, /* IFE_RDI_WR_0_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1808, /* IFE_RDI_WR_0_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1820, /* IFE_RDI_WR_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1824, /* IFE_RDI_WR_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x1420, /* IFE_RDI_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
.port_name = "IFE_UBWC_STATS",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A30, /* IFE_UBWC_STATS_0_PRIORITYLUT_LOW */
.value = 0x66666666,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A34,
/* IFE_UBWC_STATS_0_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1A38, /* IFE_UBWC_STATS_0_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1A40, /* IFE_UBWC_STATS_0_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1A48, /* IFE_UBWC_STATS_0_SAFELUT_LOW */
.value = 0x000F,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1B88, /* IFE_UBWC_STATS_0_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1908, /* IFE_UBWC_STATS_0_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1920,
/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1924,
/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x1A20, /* IFE_UBWC_STATS_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE0_RD,
.port_name = "IPE0_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E30, /* IPE0_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E34, /* IPE0_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E38, /* IPE0_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E40, /* IPE0_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1E48, /* IPE0_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2208, /* IPE0_RD_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2220, /* IPE0_RD_QOSGEN_SHAPING_LOW */
.value = 0x12121212,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2224, /* IPE0_RD_QOSGEN_SHAPING_HIGH */
.value = 0x12121212,
},
},
{
.port_type = CAM_CAMNOC_IPE1_BPS_RD,
.port_name = "IPE1_BPS_RD",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2430, /* IPE1_BPS_RD_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2434, /* IPE1_BPS_RD_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2438, /* IPE1_BPS_RD_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2440, /* IPE1_BPS_RD_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2448, /* IPE1_BPS_RD_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2308, /* IPE1_BPS_RD_QOSGEN_MAINCTL */
.value = 0x2,
},
// TITAN_A_CAMNOC_cam_noc_amm_nrt_niu_0_qosgen_Shaping_Low
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2320, /* IPE1_BPS_RD_QOSGEN_SHAPING_LOW */
.value = 0x23232323,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2324, /* IPE1_BPS_RD_QOSGEN_SHAPING_HIGH */
.value = 0x23232323,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_WR,
.port_name = "IPE_BPS_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2830, /* IPE_BPS_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2834, /* IPE_BPS_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2838, /* IPE_BPS_WR_URGENCY_LOW */
.value = 0x30,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2840, /* IPE_BPS_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2848, /* IPE_BPS_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C08, /* IPE_BPS_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C20, /* IPE_BPS_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C24, /* IPE_BPS_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2820, /* IFE_IPE_BPS_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.port_name = "JPEG",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E30, /* JPEG_PRIORITYLUT_LOW */
.value = 0x22222222,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E34, /* JPEG_PRIORITYLUT_HIGH */
.value = 0x22222222,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E38, /* JPEG_URGENCY_LOW */
.value = 0x22,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E40, /* JPEG_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2E48, /* JPEG_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D08, /* JPEG_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D20, /* JPEG_QOSGEN_SHAPING_LOW */
.value = 0xA0A0A0A,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D24, /* JPEG_QOSGEN_SHAPING_HIGH */
.value = 0xA0A0A0A,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x2E20, /* IFE_JPEG_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = true,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x3888,
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3488, /* ICP_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34A0, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34A4, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam570_cpas200_err_logger_offsets = {
.mainctrl = 0x7008, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x7010, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x7020, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x7024, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x7028, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x702c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x7030, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x7034, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x7038, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x703c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam570_cpas200_errata_wa_list = {
.camnoc_flush_slave_pending_trans = {
.enable = false,
.data.reg_info = {
.access_type = CAM_REG_TYPE_READ,
.offset = 0x3900, /* sbm_SenseIn0_Low */
.mask = 0xE0000, /* Bits 17, 18, 19 */
.value = 0, /* expected to be 0 */
},
},
};
static struct cam_camnoc_info cam570_cpas200_camnoc_info = {
.specific = &cam_cpas_v570_200_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v570_200_camnoc_specific),
.irq_sbm = &cam_cpas_v570_200_irq_sbm,
.irq_err = &cam_cpas_v570_200_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v570_200_irq_err),
.err_logger = &cam570_cpas200_err_logger_offsets,
.errata_wa_list = &cam570_cpas200_errata_wa_list,
.test_irq_info = {
.sbm_enable_mask = 0x40,
.sbm_clear_mask = 0x4,
}
};
static struct cam_cpas_camnoc_qchannel cam570_cpas200_qchannel_info = {
.qchannel_ctrl = 0x5C,
.qchannel_status = 0x60,
};
static struct cam_cpas_info cam570_cpas200_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam570_cpas200_qchannel_info},
.num_qchannel = 1,
};
#endif /* _CPASTOP_V570_200_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v580_100.h Normal file
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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v580_custom.h Normal file
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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_200.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V640_200_H_
#define _CPASTOP_V640_200_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v640_200_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6840, /* CAM_NOC_SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6848, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6880, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v640_200_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6608, /* CAM_NOC_ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6610, /* CAM_NOC_ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6618, /* CAM_NOC_ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5DA0, /* WR_NIU_ENCERREN_LOW */
.value = 0XF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x5D90, /* WR_NIU_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x5D98, /* WR_NIU_ENCERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5F20, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */
.value = 0xFF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x5F10, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x5F18, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6888, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6890, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
};
static struct cam_camnoc_specific
cam_cpas_v640_200_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_TFE_BAYER_STATS,
.port_name = "TFE_BAYER",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5830, /*PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5834, /* PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5838, /* URGENCY_LOW */
.value = 0x00000030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5840, /* DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5848, /* SAFELUT_LOW */
.value = 0x0000000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4208, /* QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4220, /* QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4224, /* QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5820, /* UBWC_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_TFE_RAW,
.port_name = "TFE_RDI_RAW",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A30, /* PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A34, /* PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A38, /* URGENCY_LOW */
.value = 0x00000003,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A40, /* DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A48, /* SAFELUT_LOW */
.value = 0x000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4408, /* QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4420, /* QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4424, /* QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5A20, /* STATS_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_WR,
.port_name = "OPE_BPS_WR",
.enable = true,
.priority_lut_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C30, /* PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C34, /* PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C38, /* URGENCY_LOW */
.value = 0x00000030,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C40, /* DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C48, /* SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4608, /* QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4620, /* QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4624, /* QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5C20, /* MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_CDM_RD,
.port_name = "OPE_BPS_CDM_RD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E30, /* IPE_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E34, /* IPE_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E38, /* IPE_WR_URGENCY_LOW */
.value = 0x30,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E40, /* IPE_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E48, /* IPE_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4808, /* IPE_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4820, /* IPE_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4824, /* IPE_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_CRE,
.port_name = "CRE_RD_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6030, /* BPS_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6034, /* BPS_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6038, /* BPS_WR_URGENCY_LOW */
.value = 0x03,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6040, /* BPS_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6048, /* BPS_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4A08, /* BPS_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4A20, /* BPS_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4A24, /* BPS_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x6020, /* BPS_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = true,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x6888,
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4008, /* ICP_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4020, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4024, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam640_cpas200_err_logger_offsets = {
.mainctrl = 0x6608, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x6610, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x6620, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x6624, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x6628, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x662c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x6630, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x6634, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x6638, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x663c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam640_cpas200_errata_wa_list = {
.enable_icp_clk_for_qchannel = {
.enable = true,
},
};
static struct cam_camnoc_info cam640_cpas200_camnoc_info = {
.specific = &cam_cpas_v640_200_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v640_200_camnoc_specific),
.irq_sbm = &cam_cpas_v640_200_irq_sbm,
.irq_err = &cam_cpas_v640_200_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v640_200_irq_err),
.err_logger = &cam640_cpas200_err_logger_offsets,
.errata_wa_list = &cam640_cpas200_errata_wa_list,
};
static struct cam_cpas_camnoc_qchannel cam640_cpas200_qchannel_info = {
.qchannel_ctrl = 0x5C,
.qchannel_status = 0x60,
};
static struct cam_cpas_info cam640_cpas200_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam640_cpas200_qchannel_info},
.num_qchannel = 1,
};
static struct cam_cpas_top_regs cam640_cpas200_cpas_top_info = {
.tpg_mux_sel_enabled = true,
.tpg_mux_sel_shift = 0x0,
.tpg_mux_sel = 0x1C,
};
#endif /* _CPASTOP_V640_200_H_ */

583
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v640_210.h Normal file
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@ -0,0 +1,583 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V640_210_H_
#define _CPASTOP_V640_210_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v640_210_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6840, /* CAM_NOC_SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6848, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6880, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v640_210_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6608, /* CAM_NOC_ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6610, /* CAM_NOC_ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x6618, /* CAM_NOC_ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5DA0, /* WR_NIU_ENCERREN_LOW */
.value = 0XF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x5D90, /* WR_NIU_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x5D98, /* WR_NIU_ENCERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x5F20, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */
.value = 0xFF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x5F10, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x5F18, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x6888, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x6890, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
};
static struct cam_camnoc_specific
cam_cpas_v640_210_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_TFE_BAYER_STATS,
.port_name = "TFE_BAYER",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5830, /*PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5834, /* PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5838, /* URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5840, /* DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5848, /* SAFELUT_LOW */
.value = 0x0000000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4208, /* QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4220, /* QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4224, /* QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5820, /* UBWC_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_TFE_RAW,
.port_name = "TFE_RDI_RAW",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A30, /* PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A34, /* PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A38, /* URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A40, /* DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5A48, /* SAFELUT_LOW */
.value = 0x000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4408, /* QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4420, /* QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4424, /* QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5A20, /* STATS_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_WR,
.port_name = "OPE_BPS_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C30, /* PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C34, /* PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C38, /* URGENCY_LOW */
.value = 0x00000030,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C40, /* DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5C48, /* SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4608, /* QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4620, /* QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4624, /* QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x5C20, /* MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_CDM_RD,
.port_name = "OPE_BPS_CDM_RD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E30, /* IPE_WR_PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E34, /* IPE_WR_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E38, /* IPE_WR_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E40, /* IPE_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x5E48, /* IPE_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4808, /* IPE_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4820, /* IPE_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4824, /* IPE_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_CRE,
.port_name = "CRE_RD_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6030, /* BPS_WR_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6034, /* BPS_WR_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6038, /* BPS_WR_URGENCY_LOW */
.value = 0x03,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6040, /* BPS_WR_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x6048, /* BPS_WR_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4A08, /* BPS_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4A20, /* BPS_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4A24, /* BPS_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x6020, /* BPS_WR_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = false,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x6888,
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4008, /* ICP_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4020, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x4024, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam640_cpas210_err_logger_offsets = {
.mainctrl = 0x6608, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0x6610, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0x6620, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0x6624, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0x6628, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0x662c, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0x6630, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0x6634, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0x6638, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0x663c, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam640_cpas210_errata_wa_list = {
};
static struct cam_camnoc_info cam640_cpas210_camnoc_info = {
.specific = &cam_cpas_v640_210_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v640_210_camnoc_specific),
.irq_sbm = &cam_cpas_v640_210_irq_sbm,
.irq_err = &cam_cpas_v640_210_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v640_210_irq_err),
.err_logger = &cam640_cpas210_err_logger_offsets,
.errata_wa_list = &cam640_cpas210_errata_wa_list,
};
static struct cam_cpas_camnoc_qchannel cam640_cpas210_qchannel_info = {
.qchannel_ctrl = 0x14,
.qchannel_status = 0x18,
};
static struct cam_cpas_info cam640_cpas210_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam640_cpas210_qchannel_info},
.num_qchannel = 1,
};
static struct cam_cpas_top_regs cam640_cpas210_cpas_top_info = {
.tpg_mux_sel_enabled = true,
.tpg_mux_sel_shift = 0x0,
.tpg_mux_sel = 0x1C,
};
#endif /* _CPASTOP_V640_210_H_ */

649
qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v665_100.h Normal file
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@ -0,0 +1,649 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V665_100_H_
#define _CPASTOP_V665_100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v665_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v665_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x8, /* CAM_NOC_ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x10, /* CAM_NOC_ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x18, /* CAM_NOC_ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x89A0, /* WR_NIU_ENCERREN_LOW */
.value = 0XF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x8990, /* WR_NIU_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x8998, /* WR_NIU_ENCERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x8720, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */
.value = 0xFF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x8710, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x8718, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
};
static struct cam_camnoc_specific
cam_cpas_v665_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_TFE_BAYER_STATS,
.port_name = "TFE_BAYER",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A30, /* TFE_BAYER_NIU_PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A34, /* TFE_BAYER_NIU_PRIORITYLUT_HIGH */
.value = 0x66555555,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A38, /* TFE_BAYER_NIU_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A40, /* TFE_BAYER_NIU_DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A48, /* TFE_BAYER_NIU_SAFELUT_LOW */
.value = 0x0000000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9008, /* TFE_BAYER_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9020, /* TFE_BAYER_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9024, /* TFE_BAYER_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8A20, /* TFE_BAYER_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_TFE_RAW,
.port_name = "TFE_RDI_RAW",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C30, /* TFE_RDI_NIU_PRIORITYLUT_LOW */
.value = 0x55554433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C34, /* TFE_RDI_NIU_PRIORITYLUT_HIGH */
.value = 0x66555555,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C38, /* TFE_RDI_RAW_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C40, /* TFE_RDI_NIU_DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C48, /* TFE_RDI_NIU_SAFELUT_LOW */
.value = 0x0000000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9088, /* TFE_RDI_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x90A0, /* TFE_RDI_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x90A4, /* TFE_RDI_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8C20, /* TFE_RDI_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_WR,
.port_name = "OPE_BPS_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8830, /* OFFLINE_WR_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8834, /* OFFLINE_WR_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8838, /* OFFLINE_WR_NIU_URGENCY_LOW */
.value = 0x030,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8840, /* OFFLINE_WR_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8848, /* OFFLINE_WR_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F88, /* OFFLINE_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8FA0, /* OFFLINE_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8FA4, /* OFFLINE_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8820, /* OFFLINE_WR_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_CDM_RD,
.port_name = "OPE_BPS_CDM_RD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8630, /* OFFLINE_RD_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8634, /* OFFLINE_RD_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8638, /* OFFLINE_RD_NIU_URGENCY_LOW */
.value = 0x003,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8640, /* OFFLINE_RD_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8648, /* OFFLINE_RD_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F08, /* OFFLINE_RD_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F20, /* OFFLINE_RD_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F24, /* OFFLINE_RD_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_CRE,
.port_name = "CRE_RD_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8230, /* CRE_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8234, /* CRE_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8238, /* CRE_NIU_URGENCY_LOW */
.value = 0x033,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8240, /* CRE_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8248, /* CRE_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E88, /* CRE_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8EA0, /* CRE_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8EA4, /* CRE_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8220, /* CRE_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8030, /* CDM_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8034, /* CDM_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8038, /* CDM_NIU_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8040, /* CDM_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8048, /* CDM_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E08, /* CDM_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E20, /* CDM_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E24, /* CDM_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = false,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x288,
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9108, /* ICP_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9120, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9124, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam665_cpas100_err_logger_offsets = {
.mainctrl = 0x8, /* ERL_MAINCTL_LOW */
.errvld = 0x10, /* ERl_ERRVLD_LOW */
.errlog0_low = 0x20, /* ERL_ERRLOG0_LOW */
.errlog0_high = 0x24, /* ERL_ERRLOG0_HIGH */
.errlog1_low = 0x28, /* ERL_ERRLOG1_LOW */
.errlog1_high = 0x2C, /* ERL_ERRLOG1_HIGH */
.errlog2_low = 0x30, /* ERL_ERRLOG2_LOW */
.errlog2_high = 0x34, /* ERL_ERRLOG2_HIGH */
.errlog3_low = 0x38, /* ERL_ERRLOG3_LOW */
.errlog3_high = 0x3C, /* ERL_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam665_cpas100_errata_wa_list = {
.enable_icp_clk_for_qchannel = {
.enable = true,
},
};
static struct cam_camnoc_info cam665_cpas100_camnoc_info = {
.specific = &cam_cpas_v665_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v665_100_camnoc_specific),
.irq_sbm = &cam_cpas_v665_100_irq_sbm,
.irq_err = &cam_cpas_v665_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v665_100_irq_err),
.err_logger = &cam665_cpas100_err_logger_offsets,
.errata_wa_list = &cam665_cpas100_errata_wa_list,
};
static struct cam_cpas_camnoc_qchannel cam665_cpas100_qchannel_info = {
.qchannel_ctrl = 0x14,
.qchannel_status = 0x18,
};
static struct cam_cpas_info cam665_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam665_cpas100_qchannel_info},
.num_qchannel = 1,
};
static struct cam_cpas_top_regs cam665_cpas100_cpas_top_info = {
.tpg_mux_sel_enabled = true,
.tpg_mux_sel_shift = 0x0,
.tpg_mux_sel = 0x1C,
};
#endif /* _CPASTOP_V665_100_H_ */

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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v680_100.h Normal file
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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v680_110.h Normal file
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qcom/opensource/camera-kernel/drivers/cam_cpas/cpas_top/cpastop_v770_100.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CPASTOP_V770_100_H_
#define _CPASTOP_V770_100_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v770_100_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
(TEST_IRQ_ENABLE ?
0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */
0x0),
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v770_100_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = false,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x8, /* CAM_NOC_ERL_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x10, /* CAM_NOC_ERL_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x18, /* CAM_NOC_ERL_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
.enable = true,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x89A0, /* WR_NIU_ENCERREN_LOW */
.value = 0XF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x8990, /* WR_NIU_ENCERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x8998, /* WR_NIU_ENCERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
.enable = true,
.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x8720, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */
.value = 0xFF,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x8710, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0x8718, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */
.value = 0X1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
.enable = false,
.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0x290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
.enable = false,
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
.enable = false,
},
};
static struct cam_camnoc_specific
cam_cpas_v770_100_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_TFE_BAYER_STATS,
.port_name = "TFE_BAYER",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A30, /* TFE_BAYER_NIU_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A34, /* TFE_BAYER_NIU_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A38, /* TFE_BAYER_NIU_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A40, /* TFE_BAYER_NIU_DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8A48, /* TFE_BAYER_NIU_SAFELUT_LOW */
.value = 0x0000000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9008, /* TFE_BAYER_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9020, /* TFE_BAYER_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9024, /* TFE_BAYER_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8A20, /* TFE_BAYER_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_TFE_RAW,
.port_name = "TFE_RDI_RAW",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C30, /* TFE_RDI_NIU_PRIORITYLUT_LOW */
.value = 0x66665433,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C34, /* TFE_RDI_NIU_PRIORITYLUT_HIGH */
.value = 0x66666666,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C38, /* TFE_RDI_RAW_URGENCY_LOW */
.value = 0x1030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C40, /* TFE_RDI_NIU_DANGERLUT_LOW */
.value = 0xffffff00,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8C48, /* TFE_RDI_NIU_SAFELUT_LOW */
.value = 0x0000000f,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9088, /* TFE_RDI_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x90A0, /* TFE_RDI_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x90A4, /* TFE_RDI_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8C20, /* TFE_RDI_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_WR,
.port_name = "OPE_BPS_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8830, /* OFFLINE_WR_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8834, /* OFFLINE_WR_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8838, /* OFFLINE_WR_NIU_URGENCY_LOW */
.value = 0x030,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8840, /* OFFLINE_WR_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8848, /* OFFLINE_WR_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F88, /* OFFLINE_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8FA0, /* OFFLINE_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8FA4, /* OFFLINE_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8820, /* OFFLINE_WR_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_OPE_BPS_CDM_RD,
.port_name = "OPE_BPS_CDM_RD",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8630, /* OFFLINE_RD_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8634, /* OFFLINE_RD_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8638, /* OFFLINE_RD_NIU_URGENCY_LOW */
.value = 0x003,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8640, /* OFFLINE_RD_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8648, /* OFFLINE_RD_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F08, /* OFFLINE_RD_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F20, /* OFFLINE_RD_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8F24, /* OFFLINE_RD_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_CRE,
.port_name = "CRE_RD_WR",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8230, /* CRE_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8234, /* CRE_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8238, /* CRE_NIU_URGENCY_LOW */
.value = 0x033,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8240, /* CRE_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8248, /* CRE_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E88, /* CRE_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8EA0, /* CRE_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8EA4, /* CRE_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
.maxwr_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ,
.masked_value = 0,
.offset = 0x8220, /* CRE_NIU_MAXWR_LOW */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
.port_name = "JPEG",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8430, /* JPEG_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8434, /* JPEG_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8438, /* JPEG_NIU_URGENCY_LOW */
.value = 0x33,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8440, /* JPEG_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8448, /* JPEG_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_CDM,
.port_name = "CDM",
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8030, /* CDM_NIU_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8034, /* CDM_NIU_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8038, /* CDM_NIU_URGENCY_LOW */
.value = 0x3,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8040, /* CDM_NIU_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8048, /* CDM_NIU_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E08, /* CDM_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E20, /* CDM_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x8E24, /* CDM_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
.port_name = "ICP",
.enable = false,
.flag_out_set0_low = {
.enable = false,
.access_type = CAM_REG_TYPE_WRITE,
.masked_value = 0,
.offset = 0x288,
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9108, /* ICP_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9120, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x9124, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};
static struct cam_camnoc_err_logger_info cam770_cpas100_err_logger_offsets = {
.mainctrl = 0x8, /* ERL_MAINCTL_LOW */
.errvld = 0x10, /* ERl_ERRVLD_LOW */
.errlog0_low = 0x20, /* ERL_ERRLOG0_LOW */
.errlog0_high = 0x24, /* ERL_ERRLOG0_HIGH */
.errlog1_low = 0x28, /* ERL_ERRLOG1_LOW */
.errlog1_high = 0x2C, /* ERL_ERRLOG1_HIGH */
.errlog2_low = 0x30, /* ERL_ERRLOG2_LOW */
.errlog2_high = 0x34, /* ERL_ERRLOG2_HIGH */
.errlog3_low = 0x38, /* ERL_ERRLOG3_LOW */
.errlog3_high = 0x3C, /* ERL_ERRLOG3_HIGH */
};
static struct cam_cpas_hw_errata_wa_list cam770_cpas100_errata_wa_list = {
.enable_icp_clk_for_qchannel = {
.enable = true,
},
};
static struct cam_camnoc_info cam770_cpas100_camnoc_info = {
.specific = &cam_cpas_v770_100_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v770_100_camnoc_specific),
.irq_sbm = &cam_cpas_v770_100_irq_sbm,
.irq_err = &cam_cpas_v770_100_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v770_100_irq_err),
.err_logger = &cam770_cpas100_err_logger_offsets,
.errata_wa_list = &cam770_cpas100_errata_wa_list,
};
static struct cam_cpas_camnoc_qchannel cam770_cpas100_qchannel_info = {
.qchannel_ctrl = 0x14,
.qchannel_status = 0x18,
};
static struct cam_cpas_info cam770_cpas100_cpas_info = {
.hw_caps_info = {
.num_caps_registers = 1,
.hw_caps_offsets = {0x8},
},
.qchannel_info = {&cam770_cpas100_qchannel_info},
.num_qchannel = 1,
};
static struct cam_cpas_top_regs cam770_cpas100_cpas_top_info = {
.tpg_mux_sel_enabled = true,
.tpg_mux_sel_shift = 0x0,
.tpg_mux_sel = 0x1C,
};
#endif /* _CPASTOP_V770_100_H_ */

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/debugfs.h>
#include <linux/videodev2.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include "cam_trace.h"
#include "cam_mem_mgr.h"
#include "cam_cre_context.h"
#include "cam_context_utils.h"
#include "cam_debug_util.h"
#include "cam_packet_util.h"
#include "cam_context.h"
static const char cre_dev_name[] = "cam-cre";
static int __cam_cre_start_dev_in_acquired(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd)
{
int rc;
rc = cam_context_start_dev_to_hw(ctx, cmd);
if (!rc) {
ctx->state = CAM_CTX_READY;
trace_cam_context_state("CRE", ctx);
}
return rc;
}
static int __cam_cre_ctx_flush_dev_in_ready(struct cam_context *ctx,
struct cam_flush_dev_cmd *cmd)
{
int rc;
struct cam_context_utils_flush_args flush_args;
flush_args.cmd = cmd;
flush_args.flush_active_req = false;
rc = cam_context_flush_dev_to_hw(ctx, &flush_args);
if (rc)
CAM_ERR(CAM_CRE, "Failed to flush device");
return rc;
}
static int __cam_cre_ctx_dump_dev_in_ready(struct cam_context *ctx,
struct cam_dump_req_cmd *cmd)
{
int rc;
rc = cam_context_dump_dev_to_hw(ctx, cmd);
if (rc)
CAM_ERR(CAM_CRE, "Failed to dump device");
return rc;
}
static int __cam_cre_ctx_config_dev_in_ready(struct cam_context *ctx,
struct cam_config_dev_cmd *cmd)
{
int rc;
size_t len;
uintptr_t packet_addr;
rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle,
&packet_addr, &len);
if (rc) {
CAM_ERR(CAM_CRE, "[%s][%d] Can not get packet address",
ctx->dev_name, ctx->ctx_id);
rc = -EINVAL;
return rc;
}
rc = cam_context_prepare_dev_to_hw(ctx, cmd);
if (rc)
CAM_ERR(CAM_CRE, "Failed to prepare device");
cam_mem_put_cpu_buf((int32_t) cmd->packet_handle);
return rc;
}
static int __cam_cre_ctx_stop_dev_in_ready(struct cam_context *ctx,
struct cam_start_stop_dev_cmd *cmd)
{
int rc;
rc = cam_context_stop_dev_to_hw(ctx);
if (rc)
CAM_ERR(CAM_CRE, "Failed to stop device");
ctx->state = CAM_CTX_ACQUIRED;
trace_cam_context_state("CRE", ctx);
return rc;
}
static int __cam_cre_ctx_release_dev_in_acquired(struct cam_context *ctx,
struct cam_release_dev_cmd *cmd)
{
int rc;
rc = cam_context_release_dev_to_hw(ctx, cmd);
if (rc)
CAM_ERR(CAM_CRE, "Unable to release device %d", rc);
ctx->state = CAM_CTX_AVAILABLE;
return rc;
}
static int __cam_cre_ctx_release_dev_in_ready(struct cam_context *ctx,
struct cam_release_dev_cmd *cmd)
{
int rc;
rc = __cam_cre_ctx_stop_dev_in_ready(ctx, NULL);
if (rc)
CAM_ERR(CAM_CRE, "Failed to stop device");
rc = __cam_cre_ctx_release_dev_in_acquired(ctx, cmd);
if (rc)
CAM_ERR(CAM_CRE, "Failed to release device");
return rc;
}
static int __cam_cre_ctx_handle_buf_done_in_ready(void *ctx,
uint32_t evt_id, void *done)
{
return cam_context_buf_done_from_hw(ctx, done, evt_id);
}
static int cam_cre_context_dump_active_request(void *data, void *args)
{
struct cam_context *ctx = (struct cam_context *)data;
struct cam_ctx_request *req = NULL;
struct cam_ctx_request *req_temp = NULL;
struct cam_hw_dump_pf_args *pf_args = (struct cam_hw_dump_pf_args *)args;
int rc = 0;
if (!ctx || !pf_args) {
CAM_ERR(CAM_CRE, "Invalid ctx %pK or pf arguments %pK",
ctx, pf_args);
return -EINVAL;
}
CAM_INFO(CAM_CRE, "iommu fault for cre ctx %d state %d",
ctx->ctx_id, ctx->state);
list_for_each_entry_safe(req, req_temp,
&ctx->active_req_list, list) {
CAM_INFO(CAM_CRE, "Active req_id: %llu ctx_id: %u",
req->request_id, ctx->ctx_id);
rc = cam_context_dump_pf_info_to_hw(ctx, pf_args, &req->pf_data);
if (rc)
CAM_ERR(CAM_CRE, "Failed to dump pf info ctx_id: %u state: %d",
ctx->ctx_id, ctx->state);
}
if (pf_args->pf_context_info.ctx_found) {
/* Send PF notification to UMD if PF found on current CTX */
rc = cam_context_send_pf_evt(ctx, pf_args);
if (rc)
CAM_ERR(CAM_CRE,
"Failed to notify PF event to userspace rc: %d", rc);
}
return rc;
}
static int __cam_cre_ctx_acquire_dev_in_available(struct cam_context *ctx,
struct cam_acquire_dev_cmd *cmd)
{
int rc;
rc = cam_context_acquire_dev_to_hw(ctx, cmd);
if (rc)
CAM_ERR(CAM_CRE, "Unable to Acquire device %d", rc);
else
ctx->state = CAM_CTX_ACQUIRED;
return rc;
}
/* top state machine */
static struct cam_ctx_ops
cam_cre_ctx_state_machine[CAM_CTX_STATE_MAX] = {
/* Uninit */
{
.ioctl_ops = { },
.crm_ops = { },
.irq_ops = NULL,
},
/* Available */
{
.ioctl_ops = {
.acquire_dev = __cam_cre_ctx_acquire_dev_in_available,
},
.crm_ops = { },
.irq_ops = NULL,
},
/* Acquired */
{
.ioctl_ops = {
.release_dev = __cam_cre_ctx_release_dev_in_acquired,
.start_dev = __cam_cre_start_dev_in_acquired,
.config_dev = __cam_cre_ctx_config_dev_in_ready,
.flush_dev = __cam_cre_ctx_flush_dev_in_ready,
.dump_dev = __cam_cre_ctx_dump_dev_in_ready,
},
.crm_ops = { },
.irq_ops = __cam_cre_ctx_handle_buf_done_in_ready,
.pagefault_ops = cam_cre_context_dump_active_request,
},
/* Ready */
{
.ioctl_ops = {
.stop_dev = __cam_cre_ctx_stop_dev_in_ready,
.release_dev = __cam_cre_ctx_release_dev_in_ready,
.config_dev = __cam_cre_ctx_config_dev_in_ready,
.flush_dev = __cam_cre_ctx_flush_dev_in_ready,
.dump_dev = __cam_cre_ctx_dump_dev_in_ready,
},
.crm_ops = {},
.irq_ops = __cam_cre_ctx_handle_buf_done_in_ready,
.pagefault_ops = cam_cre_context_dump_active_request,
},
/* Activated */
{
.ioctl_ops = {},
.crm_ops = {},
.irq_ops = NULL,
.pagefault_ops = cam_cre_context_dump_active_request,
},
};
int cam_cre_context_init(struct cam_cre_context *ctx,
struct cam_hw_mgr_intf *hw_intf,
uint32_t ctx_id, int img_iommu_hdl)
{
int rc;
int i;
if (!ctx || !ctx->base) {
CAM_ERR(CAM_CRE, "Invalid Context");
rc = -EFAULT;
goto err;
}
for (i = 0; i < CAM_CTX_REQ_MAX; i++)
ctx->req_base[i].req_priv = ctx;
rc = cam_context_init(ctx->base, cre_dev_name, CAM_CRE, ctx_id,
NULL, hw_intf, ctx->req_base, CAM_CTX_REQ_MAX, img_iommu_hdl);
if (rc) {
CAM_ERR(CAM_CRE, "Camera Context Base init failed");
goto err;
}
ctx->base->state_machine = cam_cre_ctx_state_machine;
ctx->base->ctx_priv = ctx;
ctx->base->max_hw_update_entries = CAM_CTX_CFG_MAX;
ctx->base->max_in_map_entries = CAM_CTX_CFG_MAX;
ctx->base->max_out_map_entries = CAM_CTX_CFG_MAX;
err:
return rc;
}
int cam_cre_context_deinit(struct cam_cre_context *ctx)
{
if (!ctx || !ctx->base) {
CAM_ERR(CAM_CRE, "Invalid params: %pK", ctx);
return -EINVAL;
}
cam_context_deinit(ctx->base);
memset(ctx, 0, sizeof(*ctx));
return 0;
}

67
qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_context.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_CRE_CONTEXT_H_
#define _CAM_CRE_CONTEXT_H_
#include <media/cam_cre.h>
#include "cam_context.h"
#include "cam_cre_hw_mgr_intf.h"
#define CAM_CRE_HW_EVENT_MAX 20
/**
* struct cam_cre_context - CRE context
* @base: Base cre cam context object
* @req_base: Common request structure
*/
struct cam_cre_context {
struct cam_context *base;
struct cam_ctx_request req_base[CAM_CTX_REQ_MAX];
};
/* cam cre context irq handling function type */
typedef int (*cam_cre_hw_event_cb_func)(
struct cam_cre_context *ctx_cre,
void *evt_data);
/**
* struct cam_cre_ctx_irq_ops - Function table for handling IRQ callbacks
*
* @irq_ops: Array of handle function pointers.
*
*/
struct cam_cre_ctx_irq_ops {
cam_cre_hw_event_cb_func irq_ops[CAM_CRE_HW_EVENT_MAX];
};
/**
* cam_cre_context_init()
*
* @brief: Initialization function for the CRE context
*
* @ctx: CRE context obj to be initialized
* @hw_intf: CRE hw manager interface
* @ctx_id: ID for this context
* @img_iommu_hdl: IOMMU HDL for image buffers
*
*/
int cam_cre_context_init(struct cam_cre_context *ctx,
struct cam_hw_mgr_intf *hw_intf,
uint32_t ctx_id,
int img_iommu_hdl);
/**
* cam_cre_context_deinit()
*
* @brief: Deinitialize function for the CRE context
*
* @ctx: CRE context obj to be deinitialized
*
*/
int cam_cre_context_deinit(struct cam_cre_context *ctx);
#endif /* __CAM_CRE_CONTEXT_H__ */

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qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_dev.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include "cam_node.h"
#include "cam_hw_mgr_intf.h"
#include "cam_cre_hw_mgr.h"
#include "cam_cre_dev.h"
#include "cam_debug_util.h"
#include "cam_smmu_api.h"
#include "camera_main.h"
#include "cam_context_utils.h"
#define CAM_CRE_DEV_NAME "cam-cre"
struct cam_cre_subdev {
struct cam_subdev sd;
struct cam_node *node;
struct cam_context ctx[CRE_CTX_MAX];
struct cam_cre_context ctx_cre[CRE_CTX_MAX];
struct mutex cre_lock;
int32_t open_cnt;
int32_t reserved;
};
static struct cam_cre_subdev g_cre_dev;
static void cam_cre_dev_iommu_fault_handler(
struct cam_smmu_pf_info *pf_smmu_info)
{
int i, rc;
struct cam_node *node = NULL;
struct cam_hw_dump_pf_args pf_args = {0};
if (!pf_smmu_info || !pf_smmu_info->token) {
CAM_ERR(CAM_CRE, "invalid token in page handler cb");
return;
}
node = (struct cam_node *)pf_smmu_info->token;
pf_args.pf_smmu_info = pf_smmu_info;
for (i = 0; i < node->ctx_size; i++) {
cam_context_dump_pf_info(&(node->ctx_list[i]), &pf_args);
if (pf_args.pf_context_info.ctx_found)
/* found ctx and packet of the faulted address */
break;
}
if (i == node->ctx_size) {
/* Faulted ctx not found. Report PF to userspace */
rc = cam_context_send_pf_evt(NULL, &pf_args);
if (rc)
CAM_ERR(CAM_CRE,
"Failed to notify PF event to userspace rc: %d", rc);
}
}
static int cam_cre_subdev_open(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh)
{
mutex_lock(&g_cre_dev.cre_lock);
g_cre_dev.open_cnt++;
mutex_unlock(&g_cre_dev.cre_lock);
return 0;
}
static int cam_cre_subdev_close_internal(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh)
{
int rc = 0;
struct cam_node *node = v4l2_get_subdevdata(sd);
mutex_lock(&g_cre_dev.cre_lock);
if (g_cre_dev.open_cnt <= 0) {
CAM_DBG(CAM_CRE, "CRE subdev is already closed");
rc = -EINVAL;
goto end;
}
g_cre_dev.open_cnt--;
if (!node) {
CAM_ERR(CAM_CRE, "Node ptr is NULL");
rc = -EINVAL;
goto end;
}
if (g_cre_dev.open_cnt == 0)
cam_node_shutdown(node);
end:
mutex_unlock(&g_cre_dev.cre_lock);
return rc;
}
static int cam_cre_subdev_close(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh)
{
bool crm_active = cam_req_mgr_is_open();
if (crm_active) {
CAM_DBG(CAM_ICP, "CRM is ACTIVE, close should be from CRM");
return 0;
}
return cam_cre_subdev_close_internal(sd, fh);
}
static const struct v4l2_subdev_internal_ops cam_cre_subdev_internal_ops = {
.close = cam_cre_subdev_close,
.open = cam_cre_subdev_open,
};
static int cam_cre_subdev_component_bind(struct device *dev,
struct device *master_dev, void *data)
{
int i;
int rc = 0;
struct cam_hw_mgr_intf *hw_mgr_intf;
struct cam_node *node;
int iommu_hdl = -1;
struct platform_device *pdev = to_platform_device(dev);
g_cre_dev.sd.pdev = pdev;
g_cre_dev.sd.internal_ops = &cam_cre_subdev_internal_ops;
rc = cam_subdev_probe(&g_cre_dev.sd, pdev, CAM_CRE_DEV_NAME,
CAM_CRE_DEVICE_TYPE);
if (rc) {
CAM_ERR(CAM_CRE, "CRE cam_subdev_probe failed %d", rc);
goto err;
}
node = (struct cam_node *)g_cre_dev.sd.token;
hw_mgr_intf = kzalloc(sizeof(*hw_mgr_intf), GFP_KERNEL);
if (!hw_mgr_intf) {
CAM_ERR(CAM_CRE, "Error allocating memory");
rc = -ENOMEM;
goto hw_alloc_fail;
}
rc = cam_cre_hw_mgr_init(pdev->dev.of_node, hw_mgr_intf,
&iommu_hdl);
if (rc) {
CAM_ERR(CAM_CRE, "Can not initialize CRE HWmanager %d", rc);
goto hw_init_fail;
}
memset(g_cre_dev.ctx_cre, 0, sizeof(g_cre_dev.ctx_cre));
for (i = 0; i < CAM_CRE_CTX_MAX; i++) {
g_cre_dev.ctx_cre[i].base = &g_cre_dev.ctx[i];
rc = cam_cre_context_init(&g_cre_dev.ctx_cre[i],
hw_mgr_intf, i, iommu_hdl);
if (rc) {
CAM_ERR(CAM_CRE, "CRE context init failed %d %d",
i, rc);
goto ctx_init_fail;
}
}
rc = cam_node_init(node, hw_mgr_intf, g_cre_dev.ctx,
CAM_CRE_CTX_MAX, CAM_CRE_DEV_NAME);
if (rc) {
CAM_ERR(CAM_CRE, "CRE node init failed %d", rc);
goto ctx_init_fail;
}
node->sd_handler = cam_cre_subdev_close_internal;
cam_smmu_set_client_page_fault_handler(iommu_hdl,
cam_cre_dev_iommu_fault_handler, node);
g_cre_dev.open_cnt = 0;
mutex_init(&g_cre_dev.cre_lock);
CAM_DBG(CAM_CRE, "Component bound successfully");
return rc;
ctx_init_fail:
for (--i; i >= 0; i--)
if (cam_cre_context_deinit(&g_cre_dev.ctx_cre[i]))
CAM_ERR(CAM_CRE, "deinit fail %d %d", i, rc);
hw_init_fail:
kfree(hw_mgr_intf);
hw_alloc_fail:
if (cam_subdev_remove(&g_cre_dev.sd))
CAM_ERR(CAM_CRE, "remove fail %d", rc);
err:
return rc;
}
static void cam_cre_subdev_component_unbind(struct device *dev,
struct device *master_dev, void *data)
{
int i;
for (i = 0; i < CRE_CTX_MAX; i++)
cam_cre_context_deinit(&g_cre_dev.ctx_cre[i]);
cam_node_deinit(g_cre_dev.node);
cam_subdev_remove(&g_cre_dev.sd);
mutex_destroy(&g_cre_dev.cre_lock);
}
const static struct component_ops cam_cre_subdev_component_ops = {
.bind = cam_cre_subdev_component_bind,
.unbind = cam_cre_subdev_component_unbind,
};
static int cam_cre_subdev_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &cam_cre_subdev_component_ops);
return 0;
}
static int cam_cre_subdev_probe(struct platform_device *pdev)
{
int rc = 0;
CAM_DBG(CAM_CRE, "Adding CRE sub component");
rc = component_add(&pdev->dev, &cam_cre_subdev_component_ops);
if (rc)
CAM_ERR(CAM_CRE, "failed to add component rc: %d", rc);
return rc;
}
static const struct of_device_id cam_cre_subdev_dt_match[] = {
{
.compatible = "qcom,cam-cre",
},
{}
};
MODULE_DEVICE_TABLE(of, cam_cre_subdev_dt_match);
struct platform_driver cam_cre_subdev_driver = {
.probe = cam_cre_subdev_probe,
.remove = cam_cre_subdev_remove,
.driver = {
.name = "cam_cre",
.of_match_table = cam_cre_subdev_dt_match,
.suppress_bind_attrs = true,
},
};
int cam_cre_subdev_init_module(void)
{
return platform_driver_register(&cam_cre_subdev_driver);
}
void cam_cre_subdev_exit_module(void)
{
platform_driver_unregister(&cam_cre_subdev_driver);
}
MODULE_DESCRIPTION("MSM CRE driver");
MODULE_LICENSE("GPL v2");

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qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_dev.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_CRE_DEV_H_
#define _CAM_CRE_DEV_H_
#include "cam_subdev.h"
#include "cam_hw_mgr_intf.h"
#include "cam_context.h"
#include "cam_cre_context.h"
/**
* struct cam_cre_dev - Camera CRE V4l2 device node
*
* @sd: Commone camera subdevice node
* @node: Pointer to cre subdevice
* @ctx: CRE base context storage
* @ctx_cre: CRE private context storage
* @cre_mutex: CRE dev mutex
* @open_cnt: Open device count
*/
struct cam_cre_dev {
struct cam_subdev sd;
struct cam_node *node;
struct cam_context ctx[CAM_CRE_CTX_MAX];
struct cam_cre_context ctx_cre[CAM_CRE_CTX_MAX];
struct mutex cre_mutex;
int32_t open_cnt;
};
/**
* @brief : API to register CRE dev to platform framework.
* @return struct platform_device pointer on success, or ERR_PTR() on error.
*/
int cam_cre_dev_init_module(void);
/**
* @brief : API to remove CRE dev from platform framework.
*/
void cam_cre_dev_exit_module(void);
#endif /* __CAM_CRE_DEV_H__ */

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qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef CAM_CRE_HW_MGR_H
#define CAM_CRE_HW_MGR_H
#include <linux/types.h>
#include <linux/completion.h>
#include <media/cam_cre.h>
#include "cam_cre_hw_intf.h"
#include "cam_hw_mgr_intf.h"
#include "cam_hw_intf.h"
#include "cam_req_mgr_workq.h"
#include "cam_mem_mgr.h"
#include "cam_context.h"
#include "cre_top.h"
#define CRE_CTX_MAX 32
#define CRE_WORKQ_NUM_TASK 64
#define CRE_WORKQ_TASK_CMD_TYPE 1
#define CRE_WORKQ_TASK_MSG_TYPE 2
#define CRE_PACKET_MAX_CMD_BUFS 1
#define CRE_CTX_STATE_FREE 0
#define CRE_CTX_STATE_IN_USE 1
#define CRE_CTX_STATE_ACQUIRED 2
#define CRE_CTX_STATE_RELEASE 3
#define CRE_MAX_IN_RES 2
#define CRE_MAX_OUT_RES 2
#define CRE_MAX_IO_BUFS 3
#define CAM_CRE_BW_CONFIG_UNKNOWN 0
#define CAM_CRE_BW_CONFIG_V2 2
#define CRE_DEVICE_IDLE_TIMEOUT 400
#define CRE_REQUEST_TIMEOUT 200
#define CAM_CRE_MAX_PER_PATH_VOTES 2
#define CAM_CRE_MAX_REG_SET 32
#define CAM_CRE_MAX_ACTIVE 8
/*
* Response time threshold in ms beyond which a request is not expected
* to be with CRE hw
*/
#define CAM_CRE_RESPONSE_TIME_THRESHOLD 300
/*
* struct cam_cre_irq_data
*
* @error: IRQ error
* @top_irq_status: CRE top irq status
* @wr_buf_done: write engine buf done
*/
struct cam_cre_irq_data {
uint32_t error;
uint32_t top_irq_status;
uint32_t wr_buf_done;
};
/**
* struct cam_cre_hw_intf_data - CRE hw intf data
*
* @Brief: cre hw intf pointer and pid list data
*
* @devices: cre hw intf pointer
* @num_devices: Number of CRE devices
* @num_hw_pid: Number of pids for this hw
* @hw_pid: cre hw pid values
*
*/
struct cam_cre_hw_intf_data {
struct cam_hw_intf *hw_intf;
uint32_t num_hw_pid;
uint32_t hw_pid[CRE_DEV_MAX];
};
/**
* struct cam_cre_ctx_clk_info
* @curr_fc: Context latest request frame cycles
* @rt_flag: Flag to indicate real time request
* @base_clk: Base clock to process the request
* @reserved: Reserved field
* @clk_rate: Supported clock rates for the context
* @num_paths: Number of valid AXI paths
* @axi_path: ctx based per path bw vote
*/
struct cam_cre_ctx_clk_info {
uint32_t curr_fc;
uint32_t rt_flag;
uint32_t base_clk;
uint32_t reserved;
int32_t clk_rate[CAM_MAX_VOTE];
uint32_t num_paths;
struct cam_cpas_axi_per_path_bw_vote axi_path[CAM_CRE_MAX_PER_PATH_VOTES];
};
/**
* struct cre_cmd_generic_blob
* @ctx: Current context info
* @req_info_idx: Index used for request
* @io_buf_addr: pointer to io buffer address
*/
struct cre_cmd_generic_blob {
struct cam_cre_ctx *ctx;
uint32_t req_idx;
uint64_t *io_buf_addr;
};
/**
* struct cam_cre_clk_info
* @base_clk: Base clock to process request
* @curr_clk: Current clock of hadrware
* @threshold: Threshold for overclk count
* @over_clked: Over clock count
* @num_paths: Number of AXI vote paths
* @axi_path: Current per path bw vote info
* @hw_type: IPE/BPS device type
* @watch_dog: watchdog timer handle
* @watch_dog_reset_counter: Counter for watch dog reset
* @uncompressed_bw: uncompressed BW
* @compressed_bw: compressed BW
*/
struct cam_cre_clk_info {
uint32_t base_clk;
uint32_t curr_clk;
uint32_t threshold;
uint32_t over_clked;
uint32_t num_paths;
struct cam_cpas_axi_per_path_bw_vote axi_path[CAM_CRE_MAX_PER_PATH_VOTES];
uint32_t hw_type;
struct cam_req_mgr_timer *watch_dog;
uint32_t watch_dog_reset_counter;
uint64_t uncompressed_bw;
uint64_t compressed_bw;
};
/**
* struct cre_cmd_work_data
*
* @type: Type of work data
* @data: Private data
* @req_idx: Request Idx
* @request_id: Request id
*/
struct cre_cmd_work_data {
uint32_t type;
void *data;
int64_t req_idx;
uint64_t request_id;
};
/**
* struct cre_msg_work_data
*
* @type: Type of work data
* @data: Private data
* @irq_status: IRQ status
*/
struct cre_msg_work_data {
uint32_t type;
void *data;
struct cam_cre_irq_data irq_data;
};
/**
* struct cre_clk_work_data
*
* @type: Type of work data
* @data: Private data
*/
struct cre_clk_work_data {
uint32_t type;
void *data;
};
struct plane_info {
uintptr_t cpu_addr;
dma_addr_t iova_addr;
uint32_t width;
uint32_t height;
uint32_t stride;
uint32_t format;
uint32_t alignment;
uint32_t offset;
size_t len;
};
/**
* struct cre_io_buf
*
* @direction: Direction of a buffer
* @resource_type: Resource type of IO Buffer
* @format: Format
* @fence: Fence
* @num_planes: Number of planes
* p_info: per plane info
*/
struct cre_io_buf {
uint32_t direction;
uint32_t resource_type;
uint32_t format;
uint32_t fence;
uint32_t num_planes;
struct plane_info p_info[CAM_CRE_MAX_PLANES];
};
struct cre_reg_set {
uint32_t offset;
uint32_t value;
};
struct cre_reg_buffer {
uint32_t num_rd_reg_set;
uint32_t num_wr_reg_set;
struct cre_reg_set rd_reg_set[CAM_CRE_MAX_REG_SET];
struct cre_reg_set wr_reg_set[CAM_CRE_MAX_REG_SET];
};
/**
* struct cam_cre_clk_bw_request
* @budget_ns: Time required to process frame
* @frame_cycles: Frame cycles needed to process the frame
* @rt_flag: Flag to indicate real time stream
* @uncompressed_bw: Bandwidth required to process frame
* @compressed_bw: Compressed bandwidth to process frame
*/
struct cam_cre_clk_bw_request {
uint64_t budget_ns;
uint32_t frame_cycles;
uint32_t rt_flag;
uint64_t uncompressed_bw;
uint64_t compressed_bw;
};
/**
* struct cam_cre_clk_bw_req_internal_v2
* @budget_ns: Time required to process frame
* @frame_cycles: Frame cycles needed to process the frame
* @rt_flag: Flag to indicate real time stream
* @reserved: Reserved for future use
* @num_paths: Number of paths for per path bw vote
* @axi_path: Per path vote info for CRE
*/
struct cam_cre_clk_bw_req_internal_v2 {
uint64_t budget_ns;
uint32_t frame_cycles;
uint32_t rt_flag;
uint32_t reserved;
uint32_t num_paths;
struct cam_cpas_axi_per_path_bw_vote axi_path[CAM_CRE_MAX_PER_PATH_VOTES];
};
/**
* struct cam_cre_request
*
* @request_id: Request Id
* @req_idx: Index in request list
* @state: Request state
* @num_batch: Number of batches
* @num_frame_bufs: Number of frame buffers
* @num_pass_bufs: Number of pass Buffers
* @num_io_bufs: Number of IO Buffers
* @in_resource: Input resource
* @cre_debug_buf: Debug buffer
* @io_buf: IO config info of a request
* @clk_info: Clock Info V1
* @clk_info_v2: Clock Info V2
* @hang_data: Debug data for HW error
* @submit_timestamp: Submit timestamp to hw
*/
struct cam_cre_request {
uint64_t request_id;
uint32_t req_idx;
uint32_t state;
uint32_t num_batch;
uint32_t frames_done;
uint32_t num_frame_bufs;
uint32_t num_pass_bufs;
uint32_t num_io_bufs[CRE_MAX_BATCH_SIZE];
uint32_t in_resource;
struct cre_reg_buffer cre_reg_buf[CRE_MAX_BATCH_SIZE];
struct cre_io_buf *io_buf[CRE_MAX_BATCH_SIZE][CRE_MAX_IO_BUFS];
struct cam_cre_clk_bw_request clk_info;
struct cam_cre_clk_bw_req_internal_v2 clk_info_v2;
struct cam_hw_mgr_pf_request_info hang_data;
ktime_t submit_timestamp;
};
/**
* struct cam_cre_ctx
*
* @ctx_id: Context ID
* @ctx_state: State of a context
* @req_cnt: Requests count
* @last_flush_req: last flush req for this ctx
* @last_req_time: Timestamp of last request
* @last_req_idx: Last submitted req index
* @last_done_req_idx: Last done req index
* @bitmap: Context bit map
* @bitmap_size: Context bit map size
* @bits: Context bit map bits
* @context_priv: Private data of context
* @iommu_hdl: smmu handle
* @ctx_mutex: Mutex for context
* @acquire_dev_cmd: Cam acquire command
* @cre_acquire: CRE acquire command
* @clk_info: CRE Ctx clock info
* @packet: Current packet to process
* @cre_top: Pointer to CRE top data structure
* @req_list: Request List
* @ctxt_event_cb: Callback of a context
*/
struct cam_cre_ctx {
uint32_t ctx_id;
uint32_t ctx_state;
uint32_t req_cnt;
uint64_t last_flush_req;
uint64_t last_req_time;
uint64_t last_req_idx;
uint64_t last_done_req_idx;
void *bitmap;
size_t bitmap_size;
size_t bits;
void *context_priv;
int iommu_hdl;
struct mutex ctx_mutex;
struct cam_acquire_dev_cmd acquire_dev_cmd;
struct cam_cre_acquire_dev_info cre_acquire;
struct cam_cre_ctx_clk_info clk_info;
struct cre_top *cre_top;
struct cam_packet *packet;
struct cam_cre_request *req_list[CAM_CTX_REQ_MAX];
cam_hw_event_cb_func ctxt_event_cb;
};
/**
* struct cam_cre_hw_cfg_req
*
* @list: Requests submiited to HW
* @req_id: Request id
* ctx_id: Ctx id
*
*/
struct cam_cre_hw_cfg_req {
struct list_head list;
uint64_t req_id;
uint32_t ctx_id;
};
/**
* struct cam_cre_hw_mgr
*
* @cre_ctx_cnt: Open context count
* @hw_mgr_mutex: Mutex for HW manager
* @hw_mgr_lock: Spinlock for HW manager
* @iommu_hdl: CRE Handle
* @iommu_sec_hdl: CRE Handle for secure
* @num_cre: Number of CRE
* @secure_mode: Mode of CRE creration
* @ctx_bitmap: Context bit map
* @ctx_bitmap_size: Context bit map size
* @ctx_bits: Context bit map bits
* @ctx: CRE context
* @devices: CRE devices
* @cre_caps: CRE capabilities
* @cmd_work: Command work
* @msg_work: Message work
* @timer_work: Timer work
* @cmd_work_data: Command work data
* @msg_work_data: Message work data
* @timer_work_data: Timer work data
* @cre_dev_intf: CRE device interface
* @clk_info: CRE clock Info for HW manager
* @dentry: Pointer to CRE debugfs directory
* @dump_req_data_enable: CRE hang dump enablement
* @hw_config_req_list: Requests submitted to HW
* @free_req_list: Requests that are free
* @req_list: Request list which is applied
*/
struct cam_cre_hw_mgr {
uint32_t cre_ctx_cnt;
struct mutex hw_mgr_mutex;
spinlock_t hw_mgr_lock;
int32_t iommu_hdl;
int32_t iommu_sec_hdl;
uint32_t num_cre;
uint64_t cre_debug_clk;
bool secure_mode;
void *ctx_bitmap;
size_t ctx_bitmap_size;
size_t ctx_bits;
struct cam_cre_ctx ctx[CRE_CTX_MAX];
struct cam_hw_intf **devices[CRE_DEV_MAX];
struct cam_cre_query_cap_cmd cre_caps;
struct cam_req_mgr_core_workq *cmd_work;
struct cam_req_mgr_core_workq *msg_work;
struct cam_req_mgr_core_workq *timer_work;
struct cre_cmd_work_data *cmd_work_data;
struct cre_msg_work_data *msg_work_data;
struct cre_clk_work_data *timer_work_data;
struct cam_hw_intf *cre_dev_intf[CRE_DEV_MAX];
struct cam_soc_reg_map *reg_map[CRE_DEV_MAX][CRE_BASE_MAX];
struct cam_cre_clk_info clk_info;
struct dentry *dentry;
bool dump_req_data_enable;
struct list_head hw_config_req_list;
struct list_head free_req_list;
struct cam_cre_hw_cfg_req req_list[CAM_CRE_HW_CFG_Q_MAX];
};
/**
* struct cam_cre_hw_ctx_data
*
* @context_priv: Context private data, cam_context from
* acquire.
* @ctx_mutex: Mutex for context
* @cre_dev_acquire_info: Acquire device info
* @ctxt_event_cb: Context callback function
* @in_use: Flag for context usage
* @wait_complete: Completion info
* @last_flush_req: req id which was flushed last.
*/
struct cam_cre_hw_ctx_data {
void *context_priv;
struct mutex ctx_mutex;
struct cam_cre_acquire_dev_info cre_dev_acquire_info;
cam_hw_event_cb_func ctxt_event_cb;
bool in_use;
struct completion wait_complete;
uint64_t last_flush_req;
};
#endif /* CAM_CRE_HW_MGR_H */

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qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
#include "cam_hw.h"
#include "cam_hw_intf.h"
#include "cam_io_util.h"
#include "cam_debug_util.h"
#include "cam_common_util.h"
#include "cre_core.h"
#include "cre_hw.h"
#include "cre_dev_intf.h"
#include "cre_bus_rd.h"
#include <media/cam_cre.h>
static struct cre_bus_rd *bus_rd;
#define update_cre_reg_set(cre_reg_buf, off, val) \
do { \
cre_reg_buf->rd_reg_set[cre_reg_buf->num_rd_reg_set].offset = (off); \
cre_reg_buf->rd_reg_set[cre_reg_buf->num_rd_reg_set].value = (val); \
cre_reg_buf->num_rd_reg_set++; \
} while (0)
static int cam_cre_bus_rd_in_port_idx(uint32_t input_port_id)
{
int i;
for (i = 0; i < CRE_MAX_IN_RES; i++)
if (bus_rd->in_port_to_rm[i].input_port_id ==
input_port_id)
return i;
return -EINVAL;
}
static void cam_cre_update_read_reg_val(struct plane_info p_info,
struct cam_cre_bus_rd_client_reg_val *rd_client_reg_val)
{
switch (p_info.format) {
case CAM_FORMAT_MIPI_RAW_10:
rd_client_reg_val->format = 0xd;
break;
case CAM_FORMAT_MIPI_RAW_12:
rd_client_reg_val->format = 0xe;
break;
case CAM_FORMAT_MIPI_RAW_14:
rd_client_reg_val->format = 0xf;
break;
case CAM_FORMAT_MIPI_RAW_20:
rd_client_reg_val->format = 0x13;
break;
case CAM_FORMAT_PLAIN128:
rd_client_reg_val->format = 0x0;
break;
default:
CAM_ERR(CAM_CRE, "Unsupported read format");
return;
}
CAM_DBG(CAM_CRE,
"format %d width(in bytes) %d height %d stride(in byte) %d",
p_info.format, p_info.width, p_info.height, p_info.stride);
CAM_DBG(CAM_CRE, "alignment 0x%x",
p_info.alignment);
/* Fetch engine width has to be updated in number of bytes */
rd_client_reg_val->img_width = p_info.width;
rd_client_reg_val->stride = p_info.stride;
rd_client_reg_val->img_height = p_info.height;
rd_client_reg_val->alignment = p_info.alignment;
}
static int cam_cre_bus_rd_release(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
if (ctx_id < 0 || ctx_id >= CRE_CTX_MAX) {
CAM_ERR(CAM_CRE, "Invalid data: %d", ctx_id);
return -EINVAL;
}
vfree(bus_rd->bus_rd_ctx[ctx_id]);
bus_rd->bus_rd_ctx[ctx_id] = NULL;
return 0;
}
static int cam_cre_bus_rd_update(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, struct cre_reg_buffer *cre_reg_buf, int batch_idx,
int io_idx, struct cam_cre_dev_prepare_req *prepare)
{
int k, in_port_idx;
uint32_t req_idx, val;
uint32_t iova_base, iova_offset;
struct cam_hw_prepare_update_args *prepare_args;
struct cam_cre_ctx *ctx_data;
struct cam_cre_request *cre_request;
struct cre_io_buf *io_buf;
struct cam_cre_bus_rd_reg *rd_reg;
struct cam_cre_bus_rd_client_reg *rd_reg_client;
struct cam_cre_bus_rd_reg_val *rd_reg_val;
struct cam_cre_bus_rd_client_reg_val *rd_client_reg_val;
if (ctx_id < 0 || !prepare) {
CAM_ERR(CAM_CRE, "Invalid data: %d %x", ctx_id, prepare);
return -EINVAL;
}
if (batch_idx >= CRE_MAX_BATCH_SIZE) {
CAM_ERR(CAM_CRE, "Invalid batch idx: %d", batch_idx);
return -EINVAL;
}
if (io_idx >= CRE_MAX_IO_BUFS) {
CAM_ERR(CAM_CRE, "Invalid IO idx: %d", io_idx);
return -EINVAL;
}
prepare_args = prepare->prepare_args;
ctx_data = prepare->ctx_data;
req_idx = prepare->req_idx;
cre_request = ctx_data->req_list[req_idx];
CAM_DBG(CAM_CRE, "req_idx = %d req_id = %lld",
req_idx, cre_request->request_id);
rd_reg = cam_cre_hw_info->bus_rd_reg_offset;
rd_reg_val = cam_cre_hw_info->bus_rd_reg_val;
io_buf = cre_request->io_buf[batch_idx][io_idx];
CAM_DBG(CAM_CRE,
"req_idx = %d req_id = %lld rsc %d",
req_idx, cre_request->request_id,
io_buf->resource_type);
CAM_DBG(CAM_CRE, "batch:%d iobuf:%d direction:%d",
batch_idx, io_idx, io_buf->direction);
in_port_idx =
cam_cre_bus_rd_in_port_idx(io_buf->resource_type);
if (in_port_idx < 0) {
CAM_ERR(CAM_CRE, "Invalid in_port_idx for resource %d", io_buf->resource_type);
return -EINVAL;
}
CAM_DBG(CAM_CRE, "in_port_idx %d", in_port_idx);
for (k = 0; k < io_buf->num_planes; k++) {
rd_reg_client = &rd_reg->rd_clients[in_port_idx];
rd_client_reg_val = &rd_reg_val->rd_clients[in_port_idx];
/* security cfg */
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg->security_cfg,
ctx_data->cre_acquire.secure_mode & 0x1);
/* enable client */
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->core_cfg,
1);
/* ccif meta data */
update_cre_reg_set(cre_reg_buf,
(rd_reg->offset + rd_reg_client->ccif_meta_data),
0);
/*
* As CRE have 36 Bit addressing support Image Address
* register will have 28 bit MSB of 36 bit iova.
* and addr_config will have 8 bit byte offset.
*/
iova_base = CAM_36BIT_INTF_GET_IOVA_BASE(
io_buf->p_info[k].iova_addr);
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->img_addr,
iova_base);
iova_offset = CAM_36BIT_INTF_GET_IOVA_OFFSET(
io_buf->p_info[k].iova_addr);
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->addr_cfg,
iova_offset);
cam_cre_update_read_reg_val(io_buf->p_info[k],
rd_client_reg_val);
/* Buffer size */
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->rd_width,
ctx_data->cre_acquire.in_res[in_port_idx].width);
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->rd_height,
rd_client_reg_val->img_height);
/* stride */
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->rd_stride,
rd_client_reg_val->stride);
val = 0;
val |= (rd_client_reg_val->format &
rd_client_reg_val->format_mask) <<
rd_client_reg_val->format_shift;
val |= (rd_client_reg_val->alignment &
rd_client_reg_val->alignment_mask) <<
rd_client_reg_val->alignment_shift;
/* unpacker cfg : format and alignment */
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->unpacker_cfg,
val);
/* Enable Debug cfg */
val = 0xFFFF;
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg_client->debug_status_cfg,
val);
}
return 0;
}
static int cam_cre_bus_rd_prepare(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int rc = 0;
int i, j;
uint32_t req_idx;
struct cam_cre_dev_prepare_req *prepare;
struct cam_cre_ctx *ctx_data;
struct cam_cre_request *cre_request;
struct cre_io_buf *io_buf;
struct cam_cre_bus_rd_reg *rd_reg;
struct cam_cre_bus_rd_reg_val *rd_reg_val;
struct cre_reg_buffer *cre_reg_buf = NULL;
int val;
if (ctx_id < 0 || !data) {
CAM_ERR(CAM_CRE, "Invalid data: %d %x", ctx_id, data);
return -EINVAL;
}
prepare = data;
ctx_data = prepare->ctx_data;
req_idx = prepare->req_idx;
cre_request = ctx_data->req_list[req_idx];
CAM_DBG(CAM_CRE, "req_idx = %d req_id = %lld",
req_idx, cre_request->request_id);
rd_reg = cam_cre_hw_info->bus_rd_reg_offset;
rd_reg_val = cam_cre_hw_info->bus_rd_reg_val;
for (i = 0; i < cre_request->num_batch; i++) {
cre_reg_buf = &cre_request->cre_reg_buf[i];
for (j = 0; j < cre_request->num_io_bufs[i]; j++) {
io_buf = cre_request->io_buf[i][j];
if (io_buf->direction != CAM_BUF_INPUT)
continue;
CAM_DBG(CAM_CRE, "batch:%d iobuf:%d direction:%d",
i, j, io_buf->direction);
rc = cam_cre_bus_rd_update(cam_cre_hw_info,
ctx_id, cre_reg_buf, i, j, prepare);
if (rc)
goto end;
}
/* Go command */
val = 0;
val |= rd_reg_val->go_cmd;
val |= rd_reg_val->static_prg & rd_reg_val->static_prg_mask;
update_cre_reg_set(cre_reg_buf,
rd_reg->offset + rd_reg->input_if_cmd,
val);
}
if (cre_reg_buf) {
for (i = 0; i < cre_reg_buf->num_rd_reg_set; i++) {
CAM_DBG(CAM_CRE, "CRE value 0x%x offset 0x%x",
cre_reg_buf->rd_reg_set[i].value,
cre_reg_buf->rd_reg_set[i].offset);
}
}
end:
return 0;
}
static int cam_cre_bus_rd_acquire(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int rc = 0, i;
struct cam_cre_acquire_dev_info *in_acquire;
struct cre_bus_rd_ctx *bus_rd_ctx;
struct cre_bus_in_port_to_rm *in_port_to_rm;
struct cam_cre_bus_rd_reg_val *bus_rd_reg_val;
int in_port_idx;
if (ctx_id < 0 || !data || !cam_cre_hw_info || ctx_id >= CRE_CTX_MAX) {
CAM_ERR(CAM_CRE, "Invalid data: %d %x %x",
ctx_id, data, cam_cre_hw_info);
return -EINVAL;
}
bus_rd->bus_rd_ctx[ctx_id] = vzalloc(sizeof(struct cre_bus_rd_ctx));
if (!bus_rd->bus_rd_ctx[ctx_id]) {
CAM_ERR(CAM_CRE, "Out of memory");
return -ENOMEM;
}
bus_rd->bus_rd_ctx[ctx_id]->cre_acquire = data;
in_acquire = data;
bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id];
bus_rd_ctx->num_in_ports = in_acquire->num_in_res;
bus_rd_ctx->security_flag = in_acquire->secure_mode;
bus_rd_reg_val = cam_cre_hw_info->bus_rd_reg_val;
for (i = 0; i < in_acquire->num_in_res; i++) {
if (!in_acquire->in_res[i].width)
continue;
CAM_DBG(CAM_CRE, "i = %d format = %u width = 0x%x height = 0x%x res id %d",
i, in_acquire->in_res[i].format,
in_acquire->in_res[i].width,
in_acquire->in_res[i].height,
in_acquire->in_res[i].res_id);
in_port_idx =
cam_cre_bus_rd_in_port_idx(in_acquire->in_res[i].res_id);
if (in_port_idx < 0) {
CAM_ERR(CAM_CRE, "Invalid in_port_idx: %d", i + 1);
rc = -EINVAL;
goto end;
}
in_port_to_rm = &bus_rd->in_port_to_rm[in_port_idx];
if (!in_port_to_rm->num_rm) {
CAM_ERR(CAM_CRE, "Invalid format for Input port");
rc = -EINVAL;
goto end;
}
CAM_DBG(CAM_CRE, "i:%d port_id = %u format %u",
i, in_acquire->in_res[i].res_id,
in_acquire->in_res[i].format);
}
end:
return rc;
}
static int cam_cre_bus_rd_reg_set_update(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int i;
uint32_t num_reg_set;
struct cre_reg_set *rd_reg_set;
struct cam_cre_dev_reg_set_update *reg_set_upd_cmd =
(struct cam_cre_dev_reg_set_update *)data;
num_reg_set = reg_set_upd_cmd->cre_reg_buf.num_rd_reg_set;
rd_reg_set = reg_set_upd_cmd->cre_reg_buf.rd_reg_set;
for (i = 0; i < num_reg_set; i++) {
CAM_DBG(CAM_CRE, "base 0x%x CRE value 0x%x offset 0x%x",
cam_cre_hw_info->bus_rd_reg_offset->base,
rd_reg_set[i].value, rd_reg_set[i].offset);
cam_io_w_mb(rd_reg_set[i].value,
cam_cre_hw_info->bus_rd_reg_offset->base + rd_reg_set[i].offset);
}
return 0;
}
static int cam_cre_bus_rd_init(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
struct cam_cre_bus_rd_reg_val *bus_rd_reg_val;
struct cam_cre_bus_rd_reg *bus_rd_reg;
struct cam_cre_dev_init *dev_init = data;
if (!cam_cre_hw_info) {
CAM_ERR(CAM_CRE, "Invalid cam_cre_hw_info");
return -EINVAL;
}
bus_rd_reg_val = cam_cre_hw_info->bus_rd_reg_val;
bus_rd_reg = cam_cre_hw_info->bus_rd_reg_offset;
bus_rd_reg->base =
dev_init->core_info->cre_hw_info->cre_hw->bus_rd_reg_offset->base;
/* enable interrupt mask */
cam_io_w_mb(bus_rd_reg_val->irq_mask,
cam_cre_hw_info->bus_rd_reg_offset->base + bus_rd_reg->irq_mask);
return 0;
}
static int cam_cre_bus_rd_probe(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int i, k, rm_idx;
struct cam_cre_bus_rd_reg_val *bus_rd_reg_val;
struct cam_cre_bus_rd_reg *bus_rd_reg;
struct cre_bus_in_port_to_rm *in_port_to_rm;
uint32_t input_port_idx;
if (!cam_cre_hw_info) {
CAM_ERR(CAM_CRE, "Invalid cam_cre_hw_info");
return -EINVAL;
}
bus_rd = kzalloc(sizeof(struct cre_bus_rd), GFP_KERNEL);
if (!bus_rd) {
CAM_ERR(CAM_CRE, "Out of memory");
return -ENOMEM;
}
bus_rd->cre_hw_info = cam_cre_hw_info;
bus_rd_reg_val = cam_cre_hw_info->bus_rd_reg_val;
bus_rd_reg = cam_cre_hw_info->bus_rd_reg_offset;
for (i = 0; i < bus_rd_reg_val->num_clients; i++) {
input_port_idx =
bus_rd_reg_val->rd_clients[i].rm_port_id;
in_port_to_rm = &bus_rd->in_port_to_rm[input_port_idx];
rm_idx = in_port_to_rm->num_rm;
in_port_to_rm->input_port_id =
bus_rd_reg_val->rd_clients[i].input_port_id;
in_port_to_rm->rm_port_id[rm_idx] =
bus_rd_reg_val->rd_clients[i].rm_port_id;
in_port_to_rm->num_rm++;
}
for (i = 0; i < CRE_MAX_IN_RES; i++) {
in_port_to_rm = &bus_rd->in_port_to_rm[i];
CAM_DBG(CAM_CRE, "input port id = %d",
in_port_to_rm->input_port_id);
CAM_DBG(CAM_CRE, "num_rms = %d",
in_port_to_rm->num_rm);
for (k = 0; k < in_port_to_rm->num_rm; k++) {
CAM_DBG(CAM_CRE, "rm port id = %d",
in_port_to_rm->rm_port_id[k]);
}
}
return 0;
}
static int cam_cre_bus_rd_isr(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
uint32_t irq_status;
uint32_t const_violation_status;
uint32_t ccif_violation_status;
uint32_t debug_status_0;
uint32_t debug_status_1;
struct cam_cre_bus_rd_reg *bus_rd_reg;
struct cam_cre_bus_rd_reg_val *bus_rd_reg_val;
struct cam_cre_irq_data *irq_data = data;
if (!cam_cre_hw_info) {
CAM_ERR(CAM_CRE, "Invalid cam_cre_hw_info");
return -EINVAL;
}
bus_rd_reg = cam_cre_hw_info->bus_rd_reg_offset;
bus_rd_reg_val = cam_cre_hw_info->bus_rd_reg_val;
/* Read and Clear Top Interrupt status */
irq_status = cam_io_r_mb(bus_rd_reg->base + bus_rd_reg->irq_status);
cam_io_w_mb(irq_status,
bus_rd_reg->base + bus_rd_reg->irq_clear);
cam_io_w_mb(bus_rd_reg_val->irq_cmd_clear,
bus_rd_reg->base + bus_rd_reg->irq_cmd);
CAM_DBG(CAM_CRE, "BUS irq_status 0x%x", irq_status);
if (irq_status & bus_rd_reg_val->rup_done)
CAM_DBG(CAM_CRE, "CRE Read Bus RUP done");
if (irq_status & bus_rd_reg_val->rd_buf_done)
CAM_DBG(CAM_CRE, "CRE Read Bus Buff done");
if ((irq_status & bus_rd_reg_val->cons_violation) ||
(irq_status & bus_rd_reg_val->ccif_violation)) {
irq_data->error = 1;
const_violation_status = cam_io_r_mb(bus_rd_reg->base +
bus_rd_reg->cons_violation);
ccif_violation_status = cam_io_r_mb(bus_rd_reg->base +
bus_rd_reg->ccif_violation);
debug_status_0 = cam_io_r_mb(bus_rd_reg->base +
bus_rd_reg->rd_clients[0].debug_status_0);
debug_status_1 = cam_io_r_mb(bus_rd_reg->base +
bus_rd_reg->rd_clients[0].debug_status_1);
CAM_DBG(CAM_CRE, "CRE Read Bus Violation");
CAM_DBG(CAM_CRE,
"violation status 0x%x 0x%x debug status 0/1 0x%x/0x%x",
const_violation_status, ccif_violation_status,
debug_status_0, debug_status_1);
}
return 0;
}
int cam_cre_bus_rd_process(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, uint32_t cmd_id, void *data)
{
int rc = -EINVAL;
switch (cmd_id) {
case CRE_HW_PROBE:
CAM_DBG(CAM_CRE, "CRE_HW_PROBE: E");
rc = cam_cre_bus_rd_probe(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_PROBE: X");
break;
case CRE_HW_INIT:
CAM_DBG(CAM_CRE, "CRE_HW_INIT: E");
rc = cam_cre_bus_rd_init(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_INIT: X");
break;
case CRE_HW_ACQUIRE:
CAM_DBG(CAM_CRE, "CRE_HW_ACQUIRE: E");
rc = cam_cre_bus_rd_acquire(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_ACQUIRE: X");
break;
case CRE_HW_RELEASE:
CAM_DBG(CAM_CRE, "CRE_HW_RELEASE: E");
rc = cam_cre_bus_rd_release(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_RELEASE: X");
break;
case CRE_HW_PREPARE:
CAM_DBG(CAM_CRE, "CRE_HW_PREPARE: E");
rc = cam_cre_bus_rd_prepare(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_PREPARE: X");
break;
case CRE_HW_ISR:
rc = cam_cre_bus_rd_isr(cam_cre_hw_info, 0, data);
break;
case CRE_HW_REG_SET_UPDATE:
rc = cam_cre_bus_rd_reg_set_update(cam_cre_hw_info, 0, data);
break;
case CRE_HW_DEINIT:
case CRE_HW_START:
case CRE_HW_STOP:
case CRE_HW_FLUSH:
case CRE_HW_CLK_UPDATE:
case CRE_HW_BW_UPDATE:
case CRE_HW_RESET:
case CRE_HW_SET_IRQ_CB:
rc = 0;
CAM_DBG(CAM_CRE, "Unhandled cmds: %d", cmd_id);
break;
default:
CAM_ERR(CAM_CRE, "Unsupported cmd: %d", cmd_id);
break;
}
return rc;
}

57
qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.h Normal file
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@ -0,0 +1,57 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef CRE_BUS_RD_H
#define CRE_BUS_RD_H
#include <linux/types.h>
#include <linux/completion.h>
#include <media/cam_cre.h>
#include "cre_hw.h"
#include "cam_hw_mgr_intf.h"
#include "cam_hw_intf.h"
#include "cam_soc_util.h"
#include "cam_cre_hw_mgr.h"
/**
* struct cre_bus_rd_ctx
*
* @cre_acquire: CRE acquire structure
* @security_flag: security flag
* @num_in_ports: Number of in ports
*/
struct cre_bus_rd_ctx {
struct cam_cre_acquire_dev_info *cre_acquire;
bool security_flag;
uint32_t num_in_ports;
};
/**
* struct cre_bus_in_port_to_rm
*
* @input_port_id: Intput port ID
* @num_rm: Number of RMs
* @rm_port_id: RM port Id
*/
struct cre_bus_in_port_to_rm {
uint32_t input_port_id;
uint32_t num_rm;
uint32_t rm_port_id[CRE_MAX_IN_RES];
};
/**
* struct cre_bus_rd
*
* @cre_hw_info: CRE hardware info
* @in_port_to_rm: IO port to RM mapping
* @bus_rd_ctx: RM context
*/
struct cre_bus_rd {
struct cam_cre_hw *cre_hw_info;
struct cre_bus_in_port_to_rm in_port_to_rm[CRE_MAX_IN_RES];
struct cre_bus_rd_ctx *bus_rd_ctx[CRE_CTX_MAX];
struct completion reset_complete;
};
#endif /* CRE_BUS_RD_H */

595
qcom/opensource/camera-kernel/drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
#include "cam_io_util.h"
#include "cam_hw_intf.h"
#include "cam_debug_util.h"
#include "cam_common_util.h"
#include "cre_core.h"
#include "cre_hw.h"
#include "cre_dev_intf.h"
#include "cre_bus_wr.h"
#include <media/cam_cre.h>
static struct cre_bus_wr *wr_info;
#define update_cre_reg_set(cre_reg_buf, off, val) \
do { \
cre_reg_buf->wr_reg_set[cre_reg_buf->num_wr_reg_set].offset = (off); \
cre_reg_buf->wr_reg_set[cre_reg_buf->num_wr_reg_set].value = (val); \
cre_reg_buf->num_wr_reg_set++; \
} while (0)
static uint32_t cam_cre_bus_wr_format_idx(uint32_t format)
{
uint32_t format_idx = 0;
switch(format) {
case CAM_FORMAT_PLAIN128:
format_idx = 0x0;
break;
case CAM_FORMAT_PLAIN8:
format_idx = 0x1;
break;
case CAM_FORMAT_PLAIN8_SWAP:
format_idx = 0x2;
break;
case CAM_FORMAT_PLAIN8_10:
format_idx = 0x3;
break;
case CAM_FORMAT_PLAIN8_10_SWAP:
format_idx = 0x4;
break;
case CAM_FORMAT_PLAIN16_10:
format_idx = 0x5;
break;
case CAM_FORMAT_PLAIN16_12:
format_idx = 0x6;
break;
case CAM_FORMAT_PLAIN16_14:
format_idx = 0x7;
break;
case CAM_FORMAT_PLAIN16_16:
format_idx = 0x8;
break;
case CAM_FORMAT_PLAIN32:
format_idx = 0x9;
break;
case CAM_FORMAT_PLAIN64:
format_idx = 0xA;
break;
case CAM_FORMAT_PD10:
format_idx = 0xB;
break;
case CAM_FORMAT_MIPI_RAW_10:
format_idx = 0xC;
break;
case CAM_FORMAT_MIPI_RAW_12:
format_idx = 0xD;
break;
case CAM_FORMAT_MIPI_RAW_14:
format_idx = 0xE;
break;
case CAM_FORMAT_MIPI_RAW_20:
format_idx = 0xF;
break;
case CAM_FORMAT_PLAIN32_20:
format_idx = 0x10;
break;
default:
CAM_WARN(CAM_CRE, "Invalid format %d", format);
break;
}
return format_idx;
}
static int cam_cre_translate_write_format(struct plane_info p_info,
struct cam_cre_bus_wr_client_reg_val *wr_client_reg_val)
{
CAM_DBG(CAM_CRE, "width 0x%x, height 0x%x stride 0x%x alignment 0x%x",
p_info.width, p_info.height, p_info.stride, p_info.alignment);
/* Number of output pixels */
wr_client_reg_val->width = p_info.width;
/* Number of output bytes */
wr_client_reg_val->stride = p_info.stride;
/* Number of output lines */
wr_client_reg_val->height = p_info.height;
wr_client_reg_val->alignment = p_info.alignment;
wr_client_reg_val->format = p_info.format;
return 0;
}
static int cam_cre_bus_wr_out_port_idx(uint32_t output_port_id)
{
int i;
for (i = 0; i < CRE_MAX_OUT_RES; i++)
if (wr_info->out_port_to_wm[i].output_port_id == output_port_id)
return i;
return -EINVAL;
}
static int cam_cre_bus_wr_reg_set_update(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int i;
uint32_t num_reg_set;
struct cre_reg_set *wr_reg_set;
struct cam_cre_dev_reg_set_update *reg_set_upd_cmd =
(struct cam_cre_dev_reg_set_update *)data;
num_reg_set = reg_set_upd_cmd->cre_reg_buf.num_wr_reg_set;
wr_reg_set = reg_set_upd_cmd->cre_reg_buf.wr_reg_set;
for (i = 0; i < num_reg_set; i++) {
CAM_DBG(CAM_CRE, "base 0x%x CRE value 0x%x offset 0x%x",
cam_cre_hw_info->bus_wr_reg_offset->base,
wr_reg_set[i].value, wr_reg_set[i].offset);
cam_io_w_mb(wr_reg_set[i].value,
cam_cre_hw_info->bus_wr_reg_offset->base + wr_reg_set[i].offset);
}
return 0;
}
static int cam_cre_bus_wr_release(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
if (ctx_id < 0 || ctx_id >= CRE_CTX_MAX) {
CAM_ERR(CAM_CRE, "Invalid data: %d", ctx_id);
return -EINVAL;
}
vfree(wr_info->bus_wr_ctx[ctx_id]);
wr_info->bus_wr_ctx[ctx_id] = NULL;
return 0;
}
static int cam_cre_bus_wr_update(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, struct cam_cre_dev_prepare_req *prepare,
int batch_idx, int io_idx,
struct cre_reg_buffer *cre_reg_buf)
{
int rc, k, out_port_idx;
uint32_t req_idx;
uint32_t val = 0;
uint32_t format_idx = 0;
uint32_t iova_base, iova_offset;
struct cam_hw_prepare_update_args *prepare_args;
struct cam_cre_ctx *ctx_data;
struct cam_cre_request *cre_request;
struct cre_io_buf *io_buf;
struct cam_cre_bus_wr_reg *wr_reg;
struct cam_cre_bus_wr_client_reg *wr_reg_client;
struct cam_cre_bus_wr_reg_val *wr_reg_val;
struct cam_cre_bus_wr_client_reg_val *wr_client_reg_val;
if (ctx_id < 0 || !prepare) {
CAM_ERR(CAM_CRE, "Invalid data: %d %x", ctx_id, prepare);
return -EINVAL;
}
if (batch_idx >= CRE_MAX_BATCH_SIZE) {
CAM_ERR(CAM_CRE, "Invalid batch idx: %d", batch_idx);
return -EINVAL;
}
if (io_idx >= CRE_MAX_IO_BUFS) {
CAM_ERR(CAM_CRE, "Invalid IO idx: %d", io_idx);
return -EINVAL;
}
prepare_args = prepare->prepare_args;
ctx_data = prepare->ctx_data;
req_idx = prepare->req_idx;
cre_request = ctx_data->req_list[req_idx];
wr_reg = cam_cre_hw_info->bus_wr_reg_offset;
wr_reg_val = cam_cre_hw_info->bus_wr_reg_val;
CAM_DBG(CAM_CRE, "req_idx = %d req_id = %lld",
req_idx, cre_request->request_id);
io_buf = cre_request->io_buf[batch_idx][io_idx];
CAM_DBG(CAM_CRE, "batch = %d io buf num = %d dir = %d rsc %d",
batch_idx, io_idx, io_buf->direction, io_buf->resource_type);
out_port_idx =
cam_cre_bus_wr_out_port_idx(io_buf->resource_type);
if (out_port_idx < 0) {
CAM_ERR(CAM_CRE, "Invalid idx for rsc type: %d",
io_buf->resource_type);
return -EINVAL;
}
CAM_DBG(CAM_CRE, "out_port_idx = %d", out_port_idx);
for (k = 0; k < io_buf->num_planes; k++) {
wr_reg_client = &wr_reg->wr_clients[out_port_idx];
wr_client_reg_val = &wr_reg_val->wr_clients[out_port_idx];
CAM_DBG(CAM_CRE, "wr_reg_client %x wr_client_reg_val %x",
wr_reg_client, wr_client_reg_val, wr_client_reg_val);
/* Core cfg: enable, Mode */
val = 0;
val |= ((wr_client_reg_val->mode &
wr_client_reg_val->mode_mask) <<
wr_client_reg_val->mode_shift);
val |= wr_client_reg_val->client_en;
update_cre_reg_set(cre_reg_buf,
wr_reg->offset + wr_reg_client->client_cfg,
val);
/*
* As CRE have 36 Bit addressing support Image Address
* register will have 28 bit MSB of 36 bit iova.
* and addr_config will have 8 bit byte offset.
*/
iova_base = CAM_36BIT_INTF_GET_IOVA_BASE(io_buf->p_info[k].iova_addr);
update_cre_reg_set(cre_reg_buf,
wr_reg->offset + wr_reg_client->img_addr,
iova_base);
iova_offset = CAM_36BIT_INTF_GET_IOVA_OFFSET(io_buf->p_info[k].iova_addr);
update_cre_reg_set(cre_reg_buf,
wr_reg->offset + wr_reg_client->addr_cfg,
iova_offset);
rc = cam_cre_translate_write_format(io_buf->p_info[k],
wr_client_reg_val);
if (rc < 0)
return -EINVAL;
/* Buffer size */
val = 0;
val = wr_client_reg_val->width;
val |= (wr_client_reg_val->height &
wr_client_reg_val->height_mask) <<
wr_client_reg_val->height_shift;
update_cre_reg_set(cre_reg_buf,
wr_reg->offset + wr_reg_client->img_cfg_0,
val);
/* stride */
update_cre_reg_set(cre_reg_buf,
wr_reg->offset + wr_reg_client->img_cfg_2,
wr_client_reg_val->stride);
val = 0;
format_idx = cam_cre_bus_wr_format_idx(wr_client_reg_val->format);
val |= ((format_idx & wr_client_reg_val->format_mask) <<
wr_client_reg_val->format_shift);
/* Update alignment as LSB by default*/
val |= (0x1 << wr_client_reg_val->alignment_shift);
/* pack cfg : Format and alignment */
update_cre_reg_set(cre_reg_buf,
wr_reg->offset + wr_reg_client->packer_cfg,
val);
/* Upadte debug status CFG*/
val = 0xFFFF;
update_cre_reg_set(cre_reg_buf,
wr_reg->offset + wr_reg_client->debug_status_cfg,
val);
}
return 0;
}
static int cam_cre_bus_wr_prepare(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int rc = 0;
int i, j = 0;
uint32_t req_idx;
struct cam_cre_dev_prepare_req *prepare;
struct cam_cre_ctx *ctx_data;
struct cam_cre_request *cre_request;
struct cre_io_buf *io_buf;
struct cre_reg_buffer *cre_reg_buf;
if (ctx_id < 0 || !data) {
CAM_ERR(CAM_CRE, "Invalid data: %d %x", ctx_id, data);
return -EINVAL;
}
prepare = data;
ctx_data = prepare->ctx_data;
req_idx = prepare->req_idx;
cre_request = ctx_data->req_list[req_idx];
CAM_DBG(CAM_CRE, "req_idx = %d req_id = %lld num_io_bufs = %d",
req_idx, cre_request->request_id, cre_request->num_io_bufs[0]);
for (i = 0; i < cre_request->num_batch; i++) {
cre_reg_buf = &cre_request->cre_reg_buf[i];
for (j = 0; j < cre_request->num_io_bufs[i]; j++) {
io_buf = cre_request->io_buf[i][j];
CAM_DBG(CAM_CRE, "batch = %d io buf num = %d",
i, j);
if (io_buf->direction != CAM_BUF_OUTPUT)
continue;
rc = cam_cre_bus_wr_update(cam_cre_hw_info,
ctx_id, prepare, i, j,
cre_reg_buf);
if (rc)
goto end;
}
}
end:
return rc;
}
static int cam_cre_bus_wr_acquire(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int rc = 0, i;
struct cam_cre_acquire_dev_info *in_acquire;
struct cre_bus_wr_ctx *bus_wr_ctx;
struct cre_bus_out_port_to_wm *out_port_to_wr;
int out_port_idx;
if (ctx_id < 0 || !data || ctx_id >= CRE_CTX_MAX) {
CAM_ERR(CAM_CRE, "Invalid data: %d %x", ctx_id, data);
return -EINVAL;
}
wr_info->bus_wr_ctx[ctx_id] = vzalloc(sizeof(struct cre_bus_wr_ctx));
if (!wr_info->bus_wr_ctx[ctx_id]) {
CAM_ERR(CAM_CRE, "Out of memory");
return -ENOMEM;
}
wr_info->bus_wr_ctx[ctx_id]->cre_acquire = data;
in_acquire = data;
bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id];
bus_wr_ctx->num_out_ports = in_acquire->num_out_res;
bus_wr_ctx->security_flag = in_acquire->secure_mode;
for (i = 0; i < in_acquire->num_out_res; i++) {
if (!in_acquire->out_res[i].width)
continue;
CAM_DBG(CAM_CRE, "i = %d format = %u width = 0x%x height = 0x%x res_id %d",
i, in_acquire->out_res[i].format,
in_acquire->out_res[i].width,
in_acquire->out_res[i].height,
in_acquire->in_res[i].res_id);
out_port_idx =
cam_cre_bus_wr_out_port_idx(in_acquire->out_res[i].res_id);
if (out_port_idx < 0) {
CAM_DBG(CAM_CRE, "Invalid out_port_idx: %d",
in_acquire->out_res[i].res_id);
rc = -EINVAL;
goto end;
}
CAM_DBG(CAM_CRE, "out_port_idx %d", out_port_idx);
out_port_to_wr = &wr_info->out_port_to_wm[out_port_idx];
if (!out_port_to_wr->num_wm) {
CAM_DBG(CAM_CRE, "Invalid format for Input port");
rc = -EINVAL;
goto end;
}
}
end:
return rc;
}
static int cam_cre_bus_wr_init(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
struct cam_cre_bus_wr_reg_val *bus_wr_reg_val;
struct cam_cre_bus_wr_reg *bus_wr_reg;
struct cam_cre_dev_init *dev_init = data;
if (!cam_cre_hw_info) {
CAM_ERR(CAM_CRE, "Invalid cam_cre_hw_info");
return -EINVAL;
}
wr_info->cre_hw_info = cam_cre_hw_info;
bus_wr_reg_val = cam_cre_hw_info->bus_wr_reg_val;
bus_wr_reg = cam_cre_hw_info->bus_wr_reg_offset;
bus_wr_reg->base = dev_init->core_info->cre_hw_info->cre_bus_wr_base;
CAM_DBG(CAM_CRE, "bus_wr_reg->base 0x%x", bus_wr_reg->base);
cam_io_w_mb(bus_wr_reg_val->irq_mask_0,
bus_wr_reg->base + bus_wr_reg->irq_mask_0);
cam_io_w_mb(bus_wr_reg_val->irq_mask_1,
bus_wr_reg->base + bus_wr_reg->irq_mask_1);
return 0;
}
static int cam_cre_bus_wr_probe(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
int i, k;
struct cam_cre_bus_wr_reg_val *bus_wr_reg_val;
struct cre_bus_out_port_to_wm *out_port_to_wm;
uint32_t output_port_idx;
uint32_t wm_idx;
if (!cam_cre_hw_info) {
CAM_ERR(CAM_CRE, "Invalid cam_cre_hw_info");
return -EINVAL;
}
wr_info = kzalloc(sizeof(struct cre_bus_wr), GFP_KERNEL);
if (!wr_info) {
CAM_ERR(CAM_CRE, "Out of memory");
return -ENOMEM;
}
wr_info->cre_hw_info = cam_cre_hw_info;
bus_wr_reg_val = cam_cre_hw_info->bus_wr_reg_val;
for (i = 0; i < bus_wr_reg_val->num_clients; i++) {
output_port_idx =
bus_wr_reg_val->wr_clients[i].wm_port_id;
out_port_to_wm = &wr_info->out_port_to_wm[output_port_idx];
wm_idx = out_port_to_wm->num_wm;
out_port_to_wm->output_port_id =
bus_wr_reg_val->wr_clients[i].output_port_id;
out_port_to_wm->wm_port_id[wm_idx] =
bus_wr_reg_val->wr_clients[i].wm_port_id;
out_port_to_wm->num_wm++;
}
for (i = 0; i < CRE_MAX_OUT_RES; i++) {
out_port_to_wm = &wr_info->out_port_to_wm[i];
CAM_DBG(CAM_CRE, "output port id = %d",
out_port_to_wm->output_port_id);
CAM_DBG(CAM_CRE, "num_wms = %d",
out_port_to_wm->num_wm);
for (k = 0; k < out_port_to_wm->num_wm; k++) {
CAM_DBG(CAM_CRE, "wm port id = %d",
out_port_to_wm->wm_port_id[k]);
}
}
return 0;
}
static int cam_cre_bus_wr_isr(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, void *data)
{
uint32_t irq_status_0, irq_status_1;
struct cam_cre_bus_wr_reg *bus_wr_reg;
struct cam_cre_bus_wr_reg_val *bus_wr_reg_val;
struct cam_cre_irq_data *irq_data = data;
uint32_t debug_status_0;
uint32_t debug_status_1;
uint32_t img_violation_status;
uint32_t violation_status;
int i;
if (!cam_cre_hw_info || !irq_data) {
CAM_ERR(CAM_CRE, "Invalid cam_cre_hw_info");
return -EINVAL;
}
bus_wr_reg = cam_cre_hw_info->bus_wr_reg_offset;
bus_wr_reg_val = cam_cre_hw_info->bus_wr_reg_val;
/* Read and Clear Top Interrupt status */
irq_status_0 = cam_io_r_mb(bus_wr_reg->base + bus_wr_reg->irq_status_0);
irq_status_1 = cam_io_r_mb(bus_wr_reg->base + bus_wr_reg->irq_status_1);
CAM_DBG(CAM_CRE, "BUS irq_status_0 0x%x irq_status_1 0x%x",
irq_status_0, irq_status_1);
cam_io_w_mb(irq_status_0,
bus_wr_reg->base + bus_wr_reg->irq_clear_0);
cam_io_w_mb(irq_status_1,
bus_wr_reg->base + bus_wr_reg->irq_clear_1);
cam_io_w_mb(bus_wr_reg_val->irq_cmd_clear,
bus_wr_reg->base + bus_wr_reg->irq_cmd);
if (irq_status_0 & bus_wr_reg_val->cons_violation) {
irq_data->error = 1;
CAM_ERR(CAM_CRE, "cre bus wr cons_violation");
}
if ((irq_status_0 & bus_wr_reg_val->violation) ||
(irq_status_0 & bus_wr_reg_val->img_size_violation) ||
(irq_status_0 & bus_wr_reg_val->cons_violation)) {
irq_data->error = 1;
img_violation_status = cam_io_r_mb(bus_wr_reg->base +
bus_wr_reg->image_size_violation_status);
violation_status = cam_io_r_mb(bus_wr_reg->base +
bus_wr_reg->violation_status);
debug_status_0 = cam_io_r_mb(bus_wr_reg->base +
bus_wr_reg->wr_clients[0].debug_status_0);
debug_status_1 = cam_io_r_mb(bus_wr_reg->base +
bus_wr_reg->wr_clients[0].debug_status_1);
CAM_ERR(CAM_CRE,
"violation status 0x%x 0x%x debug status 0/1 0x%x/0x%x",
violation_status, img_violation_status,
debug_status_0, debug_status_1);
}
if (irq_status_0 & bus_wr_reg_val->comp_buf_done) {
for (i = 0; i < bus_wr_reg_val->num_clients; i++) {
if (irq_status_1 & bus_wr_reg_val->
wr_clients[i].client_buf_done)
CAM_INFO(CAM_CRE, "Cleint %d Buff done", i);
irq_data->wr_buf_done = 1 << i;
}
}
return 0;
}
int cam_cre_bus_wr_process(struct cam_cre_hw *cam_cre_hw_info,
int32_t ctx_id, uint32_t cmd_id, void *data)
{
int rc = 0;
switch (cmd_id) {
case CRE_HW_PROBE:
CAM_DBG(CAM_CRE, "CRE_HW_PROBE: E");
rc = cam_cre_bus_wr_probe(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_PROBE: X");
break;
case CRE_HW_INIT:
CAM_DBG(CAM_CRE, "CRE_HW_INIT: E");
rc = cam_cre_bus_wr_init(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_INIT: X");
break;
case CRE_HW_ACQUIRE:
CAM_DBG(CAM_CRE, "CRE_HW_ACQUIRE: E");
rc = cam_cre_bus_wr_acquire(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_ACQUIRE: X");
break;
case CRE_HW_RELEASE:
CAM_DBG(CAM_CRE, "CRE_HW_RELEASE: E");
rc = cam_cre_bus_wr_release(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_RELEASE: X");
break;
case CRE_HW_PREPARE:
CAM_DBG(CAM_CRE, "CRE_HW_PREPARE: E");
rc = cam_cre_bus_wr_prepare(cam_cre_hw_info, ctx_id, data);
CAM_DBG(CAM_CRE, "CRE_HW_PREPARE: X");
break;
case CRE_HW_REG_SET_UPDATE:
rc = cam_cre_bus_wr_reg_set_update(cam_cre_hw_info, 0, data);
break;
case CRE_HW_DEINIT:
case CRE_HW_START:
case CRE_HW_STOP:
case CRE_HW_FLUSH:
case CRE_HW_CLK_UPDATE:
case CRE_HW_BW_UPDATE:
case CRE_HW_RESET:
case CRE_HW_SET_IRQ_CB:
rc = 0;
CAM_DBG(CAM_CRE, "Unhandled cmds: %d", cmd_id);
break;
case CRE_HW_ISR:
rc = cam_cre_bus_wr_isr(cam_cre_hw_info, 0, data);
break;
default:
CAM_ERR(CAM_CRE, "Unsupported cmd: %d", cmd_id);
break;
}
return rc;
}

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