qcacmn: add HAL files for peach
Add HAL files for peach. Change-Id: If38aa7767bee700e414c82e8bf9aa2acee450250 CRs-Fixed: 3674686
This commit is contained in:
Jinwei Chen
Ravindra Konda
parent
ecbe06079f
commit
390062031e
@ -1687,6 +1687,7 @@ void hal_qca8074_attach(struct hal_soc *hal_soc);
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* @hal_soc: HAL soc
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*/
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void hal_kiwi_attach(struct hal_soc *hal_soc);
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void hal_peach_attach(struct hal_soc *hal_soc);
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void hal_qcn9224v2_attach(struct hal_soc *hal_soc);
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void hal_wcn6450_attach(struct hal_soc *hal_soc);
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@ -65,9 +65,12 @@ void hal_qca5018_attach(struct hal_soc *hal);
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#ifdef QCA_WIFI_QCA5332
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void hal_qca5332_attach(struct hal_soc *hal);
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#endif
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#ifdef QCA_WIFI_KIWI
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#ifdef INCLUDE_HAL_KIWI
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void hal_kiwi_attach(struct hal_soc *hal);
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#endif
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#ifdef INCLUDE_HAL_PEACH
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void hal_peach_attach(struct hal_soc *hal);
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#endif
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#ifdef ENABLE_VERBOSE_DEBUG
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bool is_hal_verbose_debug_enabled;
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@ -443,14 +446,19 @@ static void hal_target_based_configure(struct hal_soc *hal)
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hal_qca6750_attach(hal);
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break;
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#endif
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#ifdef QCA_WIFI_KIWI
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#ifdef INCLUDE_HAL_KIWI
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case TARGET_TYPE_KIWI:
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case TARGET_TYPE_MANGO:
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case TARGET_TYPE_PEACH:
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hal->use_register_windowing = true;
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hal_kiwi_attach(hal);
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break;
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#endif
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#ifdef INCLUDE_HAL_PEACH
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case TARGET_TYPE_PEACH:
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hal->use_register_windowing = true;
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hal_peach_attach(hal);
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break;
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#endif
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#if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0)
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case TARGET_TYPE_QCA8074:
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hal_qca8074_attach(hal);
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2554
hal/wifi3.0/peach/hal_peach.c
Normal file
2554
hal/wifi3.0/peach/hal_peach.c
Normal file
File diff suppressed because it is too large
Load Diff
207
hal/wifi3.0/peach/hal_peach_rx.h
Normal file
207
hal/wifi3.0/peach/hal_peach_rx.h
Normal file
@ -0,0 +1,207 @@
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_PEACH_RX_H_
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#define _HAL_PEACH_RX_H_
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#include "qdf_util.h"
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#include "qdf_types.h"
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#include "qdf_lock.h"
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#include "qdf_mem.h"
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#include "qdf_nbuf.h"
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#include "tcl_data_cmd.h"
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//#include "mac_tcl_reg_seq_hwioreg.h"
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#include "phyrx_rssi_legacy.h"
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#include "rx_msdu_start.h"
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#include "tlv_tag_def.h"
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#include "hal_hw_headers.h"
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#include "hal_internal.h"
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#include "cdp_txrx_mon_struct.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "dp_types.h"
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#include "hal_api_mon.h"
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#include "phyrx_other_receive_info_ru_details.h"
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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(uint8_t *)(link_desc_va) + \
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RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
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#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
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(uint8_t *)(msdu0) + \
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RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
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#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
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(uint8_t *)(ent_ring_desc) + \
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RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
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#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
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(uint8_t *)(dst_ring_desc) + \
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REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
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#define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
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#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
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#define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_PEER_ID)
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#define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
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do { \
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reg_val &= \
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~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
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HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
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reg_val |= \
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
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AGING_LIST_ENABLE, 1) |\
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
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AGING_FLUSH_ENABLE, 1);\
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HAL_REG_WRITE((soc), \
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HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
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REO_REG_REG_BASE), \
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(reg_val)); \
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reg_val = \
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HAL_REG_READ((soc), \
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HWIO_REO_R0_MISC_CTL_ADDR( \
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REO_REG_REG_BASE)); \
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reg_val &= \
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~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
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reg_val |= \
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HAL_SM(HWIO_REO_R0_MISC_CTL, \
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FRAGMENT_DEST_RING, \
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(reo_params)->frag_dst_ring); \
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reg_val &= \
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(~HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK |\
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(REO_REMAP_TCL << HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT)); \
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HAL_REG_WRITE((soc), \
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HWIO_REO_R0_MISC_CTL_ADDR( \
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REO_REG_REG_BASE), \
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(reg_val)); \
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} while (0)
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#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
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((struct rx_msdu_desc_info *) \
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_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
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RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
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#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
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((struct rx_msdu_details *) \
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_OFFSET_TO_BYTE_PTR((link_desc),\
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RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
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#if defined(QCA_WIFI_PEACH) && defined(WLAN_CFR_ENABLE) && \
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defined(WLAN_ENH_CFR_ENABLE)
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#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006
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#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1
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#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2
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#define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \
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((HAL_RX_GET_64((rx_tlv), \
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \
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RTT_CFR_STATUS) & \
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB)
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static inline
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void hal_rx_get_bb_info_peach(void *rx_tlv,
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void *ppdu_info_hdl)
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{
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struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
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ppdu_info->cfr_info.bb_captured_channel =
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HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
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ppdu_info->cfr_info.bb_captured_timeout =
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HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
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ppdu_info->cfr_info.bb_captured_reason =
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HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
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}
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static inline
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void hal_rx_get_rtt_info_peach(void *rx_tlv,
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void *ppdu_info_hdl)
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{
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struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
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ppdu_info->cfr_info.rx_location_info_valid =
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HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RX_LOCATION_INFO_VALID);
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ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_CHE_BUFFER_POINTER_LOW32);
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ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_CHE_BUFFER_POINTER_HIGH8);
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ppdu_info->cfr_info.chan_capture_status =
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HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
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ppdu_info->cfr_info.rx_start_ts =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RX_START_TS);
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ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_CFO_MEASUREMENT);
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ppdu_info->cfr_info.agc_gain_info0 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN0);
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ppdu_info->cfr_info.agc_gain_info0 |=
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(((uint32_t)HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN1)) << 16);
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ppdu_info->cfr_info.agc_gain_info1 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN2);
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ppdu_info->cfr_info.agc_gain_info1 |=
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(((uint32_t)HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN3)) << 16);
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ppdu_info->cfr_info.agc_gain_info2 = 0;
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ppdu_info->cfr_info.agc_gain_info3 = 0;
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ppdu_info->cfr_info.mcs_rate =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_MCS_RATE);
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ppdu_info->cfr_info.gi_type =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_GI_TYPE);
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}
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#endif
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#endif
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209
hal/wifi3.0/peach/hal_peach_tx.h
Normal file
209
hal/wifi3.0/peach/hal_peach_tx.h
Normal file
@ -0,0 +1,209 @@
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "tcl_data_cmd.h"
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//#include "mac_tcl_reg_seq_hwioreg.h"
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#include "phyrx_rssi_legacy.h"
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#include "hal_be_hw_headers.h"
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#include "hal_internal.h"
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#include "cdp_txrx_mon_struct.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "dp_types.h"
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#include "hal_api_mon.h"
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#define DSCP_TID_TABLE_SIZE 24
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#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
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/**
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* hal_tx_set_dscp_tid_map_peach() - Configure default DSCP to TID map table
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* @hal_soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0-31
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*
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* DSCP are mapped to 8 TID values using TID values programmed
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* in any of the 32 DSCP_TID_MAPS (id = 0-31).
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*
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* Return: none
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*/
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static void hal_tx_set_dscp_tid_map_peach(struct hal_soc *hal_soc, uint8_t *map,
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uint8_t id)
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{
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int i;
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uint32_t addr, cmn_reg_addr;
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uint32_t value = 0, regval;
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uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX)
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return;
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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MAC_TCL_REG_REG_BASE);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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MAC_TCL_REG_REG_BASE,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 <<
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HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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/* Write 8 (24 bits) DSCP-TID mappings in each iteration */
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for (i = 0; i < 64; i += 8) {
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value = (map[i] |
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(map[i + 1] << 0x3) |
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(map[i + 2] << 0x6) |
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(map[i + 3] << 0x9) |
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(map[i + 4] << 0xc) |
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(map[i + 5] << 0xf) |
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(map[i + 6] << 0x12) |
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(map[i + 7] << 0x15));
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qdf_mem_copy(&val[cnt], (void *)&value, 3);
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cnt += 3;
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}
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for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
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regval = *(uint32_t *)(val + i);
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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addr += 4;
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}
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/* Disable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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/**
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* hal_tx_update_dscp_tid_peach() - Update the dscp tid map table as updated
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* by the user
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* @hal_soc: HAL SoC context
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* @tid: TID
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* @id : MAP ID
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* @dscp: DSCP_TID map index
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*
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* Return: void
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*/
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static void hal_tx_update_dscp_tid_peach(struct hal_soc *hal_soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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{
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int index;
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uint32_t addr;
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uint32_t value;
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uint32_t regval;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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MAC_TCL_REG_REG_BASE, id);
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index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
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addr += 4 * (dscp / HAL_TX_NUM_DSCP_PER_REGISTER);
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value = tid << (HAL_TX_BITS_PER_TID * index);
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|
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regval = HAL_REG_READ(soc, addr);
|
||||
regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
|
||||
regval |= value;
|
||||
|
||||
HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_init_cmd_credit_ring_peach() - Initialize command/credit SRNG
|
||||
* @hal_soc_hdl: Handle to HAL SoC structure
|
||||
* @hal_ring_hdl: Handle to HAL SRNG structure
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
static inline void
|
||||
hal_tx_init_cmd_credit_ring_peach(hal_soc_handle_t hal_soc_hdl,
|
||||
hal_ring_handle_t hal_ring_hdl)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef DP_TX_IMPLICIT_RBM_MAPPING
|
||||
|
||||
#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
|
||||
#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
|
||||
|
||||
#define RBM_PPE2TCL_OFFSET \
|
||||
(HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2)
|
||||
#define RBM_TCL_CMD_CREDIT_OFFSET \
|
||||
(HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
|
||||
|
||||
/**
|
||||
* hal_tx_config_rbm_mapping_be_peach() - Update return buffer manager ring id
|
||||
* @hal_soc_hdl: HAL SoC context
|
||||
* @hal_ring_hdl: Source ring pointer
|
||||
* @rbm_id: return buffer manager ring id
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline void
|
||||
hal_tx_config_rbm_mapping_be_peach(hal_soc_handle_t hal_soc_hdl,
|
||||
hal_ring_handle_t hal_ring_hdl,
|
||||
uint8_t rbm_id)
|
||||
{
|
||||
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
|
||||
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr = 0;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t val = 0;
|
||||
uint8_t ring_num;
|
||||
enum hal_ring_type ring_type;
|
||||
|
||||
ring_type = srng->ring_type;
|
||||
ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
|
||||
ring_num = srng->ring_id - ring_num;
|
||||
|
||||
reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
|
||||
if (ring_type == PPE2TCL)
|
||||
ring_num = ring_num + RBM_PPE2TCL_OFFSET;
|
||||
else if (ring_type == TCL_CMD_CREDIT)
|
||||
ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
|
||||
|
||||
/* get current value stored in register address */
|
||||
val = HAL_REG_READ(hal_soc, reg_addr);
|
||||
|
||||
/* mask out other stored value */
|
||||
val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
|
||||
|
||||
reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
|
||||
(RBM_MAPPING_SHFT * ring_num));
|
||||
|
||||
/* write rbm mapped value to register address */
|
||||
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
|
||||
}
|
||||
#else
|
||||
static inline void
|
||||
hal_tx_config_rbm_mapping_be_peach(hal_soc_handle_t hal_soc_hdl,
|
||||
hal_ring_handle_t hal_ring_hdl,
|
||||
uint8_t rbm_id)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user