From 856ef8009f4a9f3f90d6e6552b955914f17aca4b Mon Sep 17 00:00:00 2001 From: Soutrik Mukhopadhyay Date: Wed, 5 Jun 2024 11:11:46 +0530 Subject: [PATCH 1/3] disp: msm: Check for hdr properties of connected receiver This change checks for hdr capability of connected receiver based on vsc support of the same. If vsc support is not present, the parsing of hdr extented block is avoided. Change-Id: I5db5d1fe3e287123241ade10b698bb32f430ec43 Signed-off-by: Soutrik Mukhopadhyay --- msm/dp/dp_panel.c | 7 ++++++- msm/sde_edid_parser.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/msm/dp/dp_panel.c b/msm/dp/dp_panel.c index cc95dc0988..cee530f488 100644 --- a/msm/dp/dp_panel.c +++ b/msm/dp/dp_panel.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ @@ -1576,6 +1576,8 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) struct dp_panel_private *panel; struct drm_dp_link *link_info; struct drm_dp_aux *drm_aux; + struct drm_connector *connector; + struct sde_connector *sde_conn; u8 *dpcd, rx_feature, temp; u32 dfp_count = 0, offset = DP_DPCD_REV; @@ -1596,6 +1598,8 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) panel->vscext_supported = false; panel->vscext_chaining_supported = false; + connector = dp_panel->connector; + sde_conn = to_sde_connector(connector); rlen = drm_dp_dpcd_read(drm_aux, DP_TRAINING_AUX_RD_INTERVAL, &temp, 1); if (rlen != 1) { DP_ERR("error reading DP_TRAINING_AUX_RD_INTERVAL\n"); @@ -1637,6 +1641,7 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) panel->vscext_chaining_supported = !!(rx_feature & VSC_EXT_VESA_SDP_CHAINING_SUPPORTED); + sde_conn->hdr_supported = panel->vsc_supported; DP_DEBUG("vsc=%d, vscext=%d, vscext_chaining=%d\n", panel->vsc_supported, panel->vscext_supported, panel->vscext_chaining_supported); diff --git a/msm/sde_edid_parser.c b/msm/sde_edid_parser.c index 5a82e81257..0f76961206 100644 --- a/msm/sde_edid_parser.c +++ b/msm/sde_edid_parser.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ @@ -255,6 +255,11 @@ sde_edid_parse_hdr_db(struct drm_connector *connector, const u8 *db) if (!db) return; + if (!c_conn->hdr_supported) { + SDE_INFO("connected receiver does not support HDR\n"); + return; + } + len = db[0] & 0x1f; /* Byte 3: Electro-Optical Transfer Functions */ c_conn->hdr_eotf = db[2] & 0x3F; From 0d9d979c760c20e4c0ca0cb541b7290b6c6784c3 Mon Sep 17 00:00:00 2001 From: Anjaneya Prasad Musunuri Date: Tue, 25 Jun 2024 14:47:15 +0530 Subject: [PATCH 2/3] disp: msm: sde: flush reg dma during encoder disable Color features are disabled during encoder disable, but reg dma flush is not triggered. This change does reg dma flush for the features to be disabled during encoder disable. Change-Id: Ia74d4c43ad7b699f0097b49d86ad59529c0b3230 Signed-off-by: Anjaneya Prasad Musunuri --- msm/sde/sde_encoder.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/msm/sde/sde_encoder.c b/msm/sde/sde_encoder.c index f312ddeb29..d49fb9d860 100644 --- a/msm/sde/sde_encoder.c +++ b/msm/sde/sde_encoder.c @@ -3874,6 +3874,7 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc, struct sde_ctl_flush_cfg cfg; struct sde_hw_dsc *hw_dsc = NULL; int i; + bool is_regdma_blocking = false, is_vid_mode = false; ctl->ops.reset(ctl); sde_encoder_helper_reset_mixers(phys_enc, NULL); @@ -3950,6 +3951,12 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc, _trigger_encoder_hw_fences_override(phys_enc->sde_kms, ctl); sde_crtc_disable_cp_features(sde_enc->base.crtc); + + if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE)) + is_vid_mode = true; + is_regdma_blocking = (is_vid_mode || + _sde_encoder_is_autorefresh_enabled(sde_enc)); + ctl->ops.reg_dma_flush(ctl, is_regdma_blocking); ctl->ops.get_pending_flush(ctl, &cfg); SDE_EVT32(DRMID(phys_enc->parent), cfg.pending_flush_mask); ctl->ops.trigger_flush(ctl); From a1f1fcfb67949dbd1e04d00f07ab9072105a827f Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Thu, 21 Mar 2024 16:45:15 +0530 Subject: [PATCH 3/3] disp: msm: sde: print sgl entries in case of mismatch detected Print sgl entries to aid debugging if sgl validation fails due to mismatch of assigned and expected resources entry. Change-Id: I63c7ad3a716d3fa37c886f29fa0ac7af6f960aaf Signed-off-by: Akash Gajjar --- msm/sde/sde_vm_trusted.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/msm/sde/sde_vm_trusted.c b/msm/sde/sde_vm_trusted.c index 22fcb00c73..3fb913d999 100644 --- a/msm/sde/sde_vm_trusted.c +++ b/msm/sde/sde_vm_trusted.c @@ -33,22 +33,39 @@ int _sde_vm_validate_sgl(struct gh_sgl_desc *expected, { u32 idx; + sort(assigned->sgl_entries, assigned->n_sgl_entries, + sizeof(assigned->sgl_entries[0]), __sgl_cmp, NULL); + /* * fragmented address spaces are not supported. * So the number of sgl entries is expected to be the same. */ - if (expected->n_sgl_entries != assigned->n_sgl_entries) - return -E2BIG; + if (expected->n_sgl_entries != assigned->n_sgl_entries) { + SDE_ERROR("expected sgl entries = %d, assigned sgl entries = %d\n", + expected->n_sgl_entries, assigned->n_sgl_entries); - sort(assigned->sgl_entries, assigned->n_sgl_entries, - sizeof(assigned->sgl_entries[0]), __sgl_cmp, NULL); + for (idx = 0; idx < expected->n_sgl_entries; idx++) { + struct gh_sgl_entry *e = &expected->sgl_entries[idx]; + + SDE_ERROR("expected sgl entry: (0x%llx - %llx)\n", + e->ipa_base, e->size); + } + + for (idx = 0; idx < assigned->n_sgl_entries; idx++) { + struct gh_sgl_entry *a = &assigned->sgl_entries[idx]; + + SDE_ERROR("assigned sgl entry: (0x%llx - %llx)\n", + a->ipa_base, a->size); + } + return -E2BIG; + } for (idx = 0; idx < expected->n_sgl_entries; idx++) { struct gh_sgl_entry *e = &expected->sgl_entries[idx]; struct gh_sgl_entry *a = &assigned->sgl_entries[idx]; if ((e->ipa_base != a->ipa_base) || (e->size != a->size)) { - SDE_DEBUG("sgl mismatch: (%llu - %llu) vs (%llu - %llu)\n", + SDE_ERROR("sgl mismatch: (%llu - %llu) vs (%llu - %llu)\n", e->ipa_base, e->size, a->ipa_base, a->size); return -EINVAL; }