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video-driver changes

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Change-Id: I916797e7df81416be6e8766cadf351bf9834dd7f
This commit is contained in:
David Wronek 2025-01-12 17:09:30 +01:00 committed by j7b3y
parent 652f28aeda
commit 0dcceff803
29 changed files with 216 additions and 629 deletions
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10
qcom/opensource/video-driver/driver/platform/cliffs/src/cliffs.c
View File

@ -1657,6 +1657,16 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_clif
NULL, NULL,
msm_vidc_set_stage}, msm_vidc_set_stage},
{STAGE, ENC, H264 | HEVC,
{0},
NULL,
msm_vidc_set_stage},
{STAGE, DEC, H264 | HEVC | VP9,
{0},
NULL,
msm_vidc_set_stage},
{PIPE, DEC | ENC, CODECS_ALL, {PIPE, DEC | ENC, CODECS_ALL,
{0}, {0},
NULL, NULL,

140
qcom/opensource/video-driver/driver/platform/cliffs/src/msm_vidc_cliffs.c
View File

@ -316,11 +316,11 @@ static struct msm_platform_core_capability core_data_cliffs_v0[] = {
{MAX_NUM_4K_SESSIONS, 4}, {MAX_NUM_4K_SESSIONS, 4},
{MAX_NUM_8K_SESSIONS, 1}, {MAX_NUM_8K_SESSIONS, 1},
{MAX_SECURE_SESSION_COUNT, 3}, {MAX_SECURE_SESSION_COUNT, 3},
{MAX_RT_MBPF, 129600}, /* ((7680*4320)/256)) */ {MAX_RT_MBPF, 138240}, /* ((8192x4320)/256) */
{MAX_MBPF, 139264}, /* (4 * ((4096*2176)/256)) */ {MAX_MBPF, 173056}, /* (8192x4320)/256 + (4096*2176)/256*/
/* max_load 1920x1080@480fps which is greater than 7680x4320@30fps */ /* max_load 4096x2176@120fps which is greater than 8192x4320@30fps */
/* Concurrency: UHD@30 decode + uhd@30 encode */ /* Concurrency: UHD@30 decode + uhd@30 encode */
{MAX_MBPS, 3916800}, {MAX_MBPS, 4177920},
{MAX_IMAGE_MBPF, 1048576}, /* (16384x16384)/256 */ {MAX_IMAGE_MBPF, 1048576}, /* (16384x16384)/256 */
{MAX_MBPF_HQ, 8160}, /* ((1920x1088)/256) */ {MAX_MBPF_HQ, 8160}, /* ((1920x1088)/256) */
{MAX_MBPS_HQ, 244800}, /* ((1920x1088)/256)@30fps */ {MAX_MBPS_HQ, 244800}, /* ((1920x1088)/256)@30fps */
@ -352,7 +352,7 @@ static struct msm_platform_core_capability core_data_cliffs_v0[] = {
static struct msm_platform_core_capability core_data_cliffs_v1[] = { static struct msm_platform_core_capability core_data_cliffs_v1[] = {
/* {type, value} */ /* {type, value} */
{ENC_CODECS, H264 | HEVC | HEIC}, {ENC_CODECS, H264 | HEVC | HEIC},
{DEC_CODECS, H264 | HEVC | VP9 | HEIC}, {DEC_CODECS, H264 | HEVC | VP9 | AV1 | HEIC},
{MAX_SESSION_COUNT, 16}, {MAX_SESSION_COUNT, 16},
{MAX_NUM_720P_SESSIONS, 16}, {MAX_NUM_720P_SESSIONS, 16},
{MAX_NUM_1080P_SESSIONS, 8}, {MAX_NUM_1080P_SESSIONS, 8},
@ -401,9 +401,9 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
0, INT_MAX, 1, DRIVER_VERSION, 0, INT_MAX, 1, DRIVER_VERSION,
V4L2_CID_MPEG_VIDC_DRIVER_VERSION}, V4L2_CID_MPEG_VIDC_DRIVER_VERSION},
{FRAME_WIDTH, DEC, CODECS_ALL_V0, 96, 7680, 1, 1920}, {FRAME_WIDTH, DEC, CODECS_ALL_V0, 96, 8192, 1, 1920},
{FRAME_WIDTH, DEC, VP9 | AV1, 96, 4096, 1, 1920}, {FRAME_WIDTH, DEC, VP9, 96, 4096, 1, 1920},
{FRAME_WIDTH, ENC, CODECS_ALL_V0, 128, 4096, 1, 1920}, {FRAME_WIDTH, ENC, CODECS_ALL_V0, 128, 4096, 1, 1920},
@ -421,9 +421,9 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
{SECURE_FRAME_WIDTH, ENC, HEVC, 96, 4096, 1, 1920}, {SECURE_FRAME_WIDTH, ENC, HEVC, 96, 4096, 1, 1920},
{FRAME_HEIGHT, DEC, CODECS_ALL_V0, 96, 7680, 1, 1080}, {FRAME_HEIGHT, DEC, CODECS_ALL_V0, 96, 8192, 1, 1080},
{FRAME_HEIGHT, DEC, VP9 | AV1, 96, 4096, 1, 1080}, {FRAME_HEIGHT, DEC, VP9, 96, 4096, 1, 1080},
{FRAME_HEIGHT, ENC, CODECS_ALL_V0, 128, 4096, 1, 1080}, {FRAME_HEIGHT, ENC, CODECS_ALL_V0, 128, 4096, 1, 1080},
@ -491,11 +491,11 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
/* ((16384x16384)/256) */ /* ((16384x16384)/256) */
{MBPF, ENC, HEIC, 36, 1048576, 1, 1048576}, {MBPF, ENC, HEIC, 36, 1048576, 1, 1048576},
/* (4 * ((4096 * 2176)/256) */ /* (8192 * 4320) / 256 */
{MBPF, DEC, CODECS_ALL_V0, 36, 139264, 1, 139264}, {MBPF, DEC, CODECS_ALL_V0, 36, 138240, 1, 138240},
/* (4096 * 2160) / 256 */ /* (4096 * 2176) / 256 */
{MBPF, DEC, VP9 | AV1, 36, 34560, 1, 34560}, {MBPF, DEC, VP9, 36, 34816, 1, 34816},
/* ((8192x8192)/256) */ /* ((8192x8192)/256) */
{MBPF, DEC, HEIC, 64, 262144, 1, 262144 }, {MBPF, DEC, HEIC, 64, 262144, 1, 262144 },
@ -807,10 +807,10 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
160000000, 1, 160000000}, 160000000, 1, 160000000},
{CAVLC_MAX_BITRATE, ENC, H264, 0, {CAVLC_MAX_BITRATE, ENC, H264, 0,
160000000, 1, 160000000}, 220000000, 1, 220000000},
{ALLINTRA_MAX_BITRATE, ENC, H264 | HEVC, 0, {ALLINTRA_MAX_BITRATE, ENC, H264 | HEVC, 0,
160000000, 1, 160000000}, 245000000, 1, 245000000},
{LOWLATENCY_MAX_BITRATE, ENC, H264 | HEVC, 0, {LOWLATENCY_MAX_BITRATE, ENC, H264 | HEVC, 0,
70000000, 1, 70000000}, 70000000, 1, 70000000},
@ -1339,7 +1339,7 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
{LEVEL, ENC, H264, {LEVEL, ENC, H264,
V4L2_MPEG_VIDEO_H264_LEVEL_1_0, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_2, V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
@ -1356,15 +1356,16 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2), BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
V4L2_MPEG_VIDEO_H264_LEVEL_5_2, BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
V4L2_CID_MPEG_VIDEO_H264_LEVEL, V4L2_CID_MPEG_VIDEO_H264_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{LEVEL, ENC, HEVC | HEIC, {LEVEL, ENC, HEVC | HEIC,
V4L2_MPEG_VIDEO_HEVC_LEVEL_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2,
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
@ -1373,8 +1374,9 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1), BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2),
V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
@ -1426,7 +1428,7 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
{LEVEL, DEC, VP9, {LEVEL, DEC, VP9,
V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, V4L2_MPEG_VIDEO_VP9_LEVEL_5_2,
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
@ -1436,15 +1438,16 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1), BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2),
V4L2_MPEG_VIDEO_VP9_LEVEL_5_2,
V4L2_CID_MPEG_VIDEO_VP9_LEVEL, V4L2_CID_MPEG_VIDEO_VP9_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{LEVEL, DEC, AV1, {LEVEL, DEC, AV1,
V4L2_MPEG_VIDC_AV1_LEVEL_2_0, V4L2_MPEG_VIDC_AV1_LEVEL_2_0,
V4L2_MPEG_VIDC_AV1_LEVEL_5_1, V4L2_MPEG_VIDC_AV1_LEVEL_5_3,
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_0) | BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_0) |
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_1) | BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_1) |
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_2) | BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_2) |
@ -1458,8 +1461,10 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v0[] = {
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_2) | BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_2) |
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_3) | BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_3) |
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_0) | BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_0) |
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_1), BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_1) |
V4L2_MPEG_VIDC_AV1_LEVEL_5_1, BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_2) |
BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_3),
V4L2_MPEG_VIDC_AV1_LEVEL_5_3,
V4L2_CID_MPEG_VIDC_AV1_LEVEL, V4L2_CID_MPEG_VIDC_AV1_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
@ -3073,10 +3078,10 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v1[] = {
160000000, 1, 160000000}, 160000000, 1, 160000000},
{CAVLC_MAX_BITRATE, ENC, H264, 0, {CAVLC_MAX_BITRATE, ENC, H264, 0,
160000000, 1, 160000000}, 220000000, 1, 220000000},
{ALLINTRA_MAX_BITRATE, ENC, H264 | HEVC, 0, {ALLINTRA_MAX_BITRATE, ENC, H264 | HEVC, 0,
160000000, 1, 160000000}, 245000000, 1, 245000000},
{LOWLATENCY_MAX_BITRATE, ENC, H264 | HEVC, 0, {LOWLATENCY_MAX_BITRATE, ENC, H264 | HEVC, 0,
70000000, 1, 70000000}, 70000000, 1, 70000000},
@ -3590,7 +3595,7 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v1[] = {
{LEVEL, ENC, H264, {LEVEL, ENC, H264,
V4L2_MPEG_VIDEO_H264_LEVEL_1_0, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_2, V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
@ -3607,15 +3612,16 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v1[] = {
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2), BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
V4L2_MPEG_VIDEO_H264_LEVEL_5_2, BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
V4L2_CID_MPEG_VIDEO_H264_LEVEL, V4L2_CID_MPEG_VIDEO_H264_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{LEVEL, ENC, HEVC | HEIC, {LEVEL, ENC, HEVC | HEIC,
V4L2_MPEG_VIDEO_HEVC_LEVEL_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2,
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
@ -3624,15 +3630,16 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v1[] = {
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1), BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2),
V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{LEVEL, DEC, H264, {LEVEL, DEC, H264,
V4L2_MPEG_VIDEO_H264_LEVEL_1_0, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_2, V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
@ -3649,15 +3656,16 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v1[] = {
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2), BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
V4L2_MPEG_VIDEO_H264_LEVEL_5_2, BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
V4L2_CID_MPEG_VIDEO_H264_LEVEL, V4L2_CID_MPEG_VIDEO_H264_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{LEVEL, DEC, HEVC | HEIC, {LEVEL, DEC, HEVC | HEIC,
V4L2_MPEG_VIDEO_HEVC_LEVEL_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2,
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
@ -3666,15 +3674,16 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v1[] = {
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1), BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2),
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2,
V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{LEVEL, DEC, VP9, {LEVEL, DEC, VP9,
V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, V4L2_MPEG_VIDEO_VP9_LEVEL_5_2,
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
@ -3684,8 +3693,9 @@ static struct msm_platform_inst_capability instance_cap_data_cliffs_v1[] = {
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1), BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2),
V4L2_MPEG_VIDEO_VP9_LEVEL_5_2,
V4L2_CID_MPEG_VIDEO_VP9_LEVEL, V4L2_CID_MPEG_VIDEO_VP9_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
@ -4909,7 +4919,6 @@ static const struct clk_rst_table cliffs_clk_reset_table[] = {
{ "video_axi_reset", 0 }, { "video_axi_reset", 0 },
{ "video_xo_reset", 1 }, { "video_xo_reset", 1 },
{ "video_mvs0c_reset", 0 }, { "video_mvs0c_reset", 0 },
{ "video_mvs0_reset", 0 },
}; };
/* name, llcc_id */ /* name, llcc_id */
@ -4932,21 +4941,13 @@ const struct context_bank_table cliffs_context_bank_table[] = {
}; };
/* freq */ /* freq */
static struct freq_table cliffs_freq_table_sku0[] = { static struct freq_table cliffs_freq_table[] = {
{533333333}, {444000000}, {366000000}, {338000000}, {240000000}, {192000000} {533333333}, {444000000}, {366000000}, {338000000}, {240000000}, {192000000}
}; };
static struct freq_table cliffs_freq_table_sku1[] = {
{366000000}, {338000000}, {240000000}, {192000000}
};
/* register, value, mask */ /* register, value, mask */
static const struct reg_preset_table cliffs_reg_preset_table[] = { static const struct reg_preset_table cliffs_reg_preset_table[] = {
{ 0xB0088, 0x0, 0x11 }, { 0xB0088, 0x0, 0x11},
{ 0x10830, 0x33332222, 0xFFFFFFFF},
{ 0x10834, 0x44444444, 0xFFFFFFFF},
{ 0x10838, 0x00001022, 0xFFFFFFFF},
{ 0xA013C, 0x99, 0xFFFFFFFF},
}; };
/* name, phys_addr, size, device_addr, device region type */ /* name, phys_addr, size, device_addr, device region type */
@ -5070,16 +5071,9 @@ static const u32 cliffs_vdec_output_properties_av1[] = {
HFI_PROP_FENCE, HFI_PROP_FENCE,
}; };
static const u32 cliffs_msm_vidc_ssr_type[] = {
HFI_SSR_TYPE_SW_ERR_FATAL,
HFI_SSR_TYPE_SW_DIV_BY_ZERO,
HFI_SSR_TYPE_CPU_WDOG_IRQ,
HFI_SSR_TYPE_NOC_ERROR,
};
static struct msm_vidc_efuse_data efuse_data_cliffs[] = { static struct msm_vidc_efuse_data efuse_data_cliffs[] = {
/* IRIS_DISABLE_AV1, SKU VERSION: 1 */ EFUSE_ENTRY(0x221C8118, 4, 0x1000, 0xB, SKU_VERSION),
EFUSE_ENTRY(0x221C8118, 4, 0x2000, 0xD, SKU_VERSION), EFUSE_ENTRY(0x221C812C, 4, 0x40, 0x6, SKU_VERSION),
}; };
static const struct msm_vidc_platform_data cliffs_data_v0 = { static const struct msm_vidc_platform_data cliffs_data_v0 = {
@ -5100,15 +5094,15 @@ static const struct msm_vidc_platform_data cliffs_data_v0 = {
.context_bank_tbl_size = ARRAY_SIZE(cliffs_context_bank_table), .context_bank_tbl_size = ARRAY_SIZE(cliffs_context_bank_table),
/* platform specific resources */ /* platform specific resources */
.freq_tbl = cliffs_freq_table_sku0, .freq_tbl = cliffs_freq_table,
.freq_tbl_size = ARRAY_SIZE(cliffs_freq_table_sku0), .freq_tbl_size = ARRAY_SIZE(cliffs_freq_table),
.reg_prst_tbl = cliffs_reg_preset_table, .reg_prst_tbl = cliffs_reg_preset_table,
.reg_prst_tbl_size = ARRAY_SIZE(cliffs_reg_preset_table), .reg_prst_tbl_size = ARRAY_SIZE(cliffs_reg_preset_table),
.dev_reg_tbl = cliffs_device_region_table, .dev_reg_tbl = cliffs_device_region_table,
.dev_reg_tbl_size = ARRAY_SIZE(cliffs_device_region_table), .dev_reg_tbl_size = ARRAY_SIZE(cliffs_device_region_table),
.fwname = "vpu30_2v", .fwname = "vpu30_2v",
.pas_id = 9, .pas_id = 9,
.supports_mmrm = 0, .supports_mmrm = 1,
.vpu_ver = VPU_VERSION_IRIS33_2P, .vpu_ver = VPU_VERSION_IRIS33_2P,
/* caps related resorces */ /* caps related resorces */
@ -5150,9 +5144,6 @@ static const struct msm_vidc_platform_data cliffs_data_v0 = {
.dec_output_prop_size_vp9 = ARRAY_SIZE(cliffs_vdec_output_properties_vp9), .dec_output_prop_size_vp9 = ARRAY_SIZE(cliffs_vdec_output_properties_vp9),
.dec_output_prop_size_av1 = ARRAY_SIZE(cliffs_vdec_output_properties_av1), .dec_output_prop_size_av1 = ARRAY_SIZE(cliffs_vdec_output_properties_av1),
.msm_vidc_ssr_type = cliffs_msm_vidc_ssr_type,
.msm_vidc_ssr_type_size = ARRAY_SIZE(cliffs_msm_vidc_ssr_type),
/* Fuse specific resources */ /* Fuse specific resources */
.efuse_data = efuse_data_cliffs, .efuse_data = efuse_data_cliffs,
.efuse_data_size = ARRAY_SIZE(efuse_data_cliffs), .efuse_data_size = ARRAY_SIZE(efuse_data_cliffs),
@ -5177,15 +5168,15 @@ static const struct msm_vidc_platform_data cliffs_data_v1 = {
.context_bank_tbl_size = ARRAY_SIZE(cliffs_context_bank_table), .context_bank_tbl_size = ARRAY_SIZE(cliffs_context_bank_table),
/* platform specific resources */ /* platform specific resources */
.freq_tbl = cliffs_freq_table_sku1, .freq_tbl = cliffs_freq_table,
.freq_tbl_size = ARRAY_SIZE(cliffs_freq_table_sku1), .freq_tbl_size = ARRAY_SIZE(cliffs_freq_table),
.reg_prst_tbl = cliffs_reg_preset_table, .reg_prst_tbl = cliffs_reg_preset_table,
.reg_prst_tbl_size = ARRAY_SIZE(cliffs_reg_preset_table), .reg_prst_tbl_size = ARRAY_SIZE(cliffs_reg_preset_table),
.dev_reg_tbl = cliffs_device_region_table, .dev_reg_tbl = cliffs_device_region_table,
.dev_reg_tbl_size = ARRAY_SIZE(cliffs_device_region_table), .dev_reg_tbl_size = ARRAY_SIZE(cliffs_device_region_table),
.fwname = "vpu30_2v", .fwname = "vpu30_2v",
.pas_id = 9, .pas_id = 9,
.supports_mmrm = 0, .supports_mmrm = 1,
/* caps related resorces */ /* caps related resorces */
.core_data = core_data_cliffs_v1, .core_data = core_data_cliffs_v1,
@ -5221,9 +5212,6 @@ static const struct msm_vidc_platform_data cliffs_data_v1 = {
.dec_output_prop_size_hevc = ARRAY_SIZE(cliffs_vdec_output_properties_hevc), .dec_output_prop_size_hevc = ARRAY_SIZE(cliffs_vdec_output_properties_hevc),
.dec_output_prop_size_vp9 = ARRAY_SIZE(cliffs_vdec_output_properties_vp9), .dec_output_prop_size_vp9 = ARRAY_SIZE(cliffs_vdec_output_properties_vp9),
.msm_vidc_ssr_type = cliffs_msm_vidc_ssr_type,
.msm_vidc_ssr_type_size = ARRAY_SIZE(cliffs_msm_vidc_ssr_type),
/* Fuse specific resources */ /* Fuse specific resources */
.efuse_data = efuse_data_cliffs, .efuse_data = efuse_data_cliffs,
.efuse_data_size = ARRAY_SIZE(efuse_data_cliffs), .efuse_data_size = ARRAY_SIZE(efuse_data_cliffs),

4
qcom/opensource/video-driver/driver/platform/common/inc/msm_vidc_platform.h
View File

@ -201,7 +201,6 @@ struct msm_vidc_format_capability {
enum vpu_version { enum vpu_version {
VPU_VERSION_IRIS33 = 1, VPU_VERSION_IRIS33 = 1,
VPU_VERSION_IRIS33_2P, // IRIS3 2 PIPE VPU_VERSION_IRIS33_2P, // IRIS3 2 PIPE
VPU_VERSION_IRIS2_2P, // IRIS2 2 PIPE
}; };
struct msm_vidc_platform_data { struct msm_vidc_platform_data {
@ -267,9 +266,6 @@ struct msm_vidc_platform_data {
unsigned int dec_output_prop_size_vp9; unsigned int dec_output_prop_size_vp9;
const u32 *dec_output_prop_av1; const u32 *dec_output_prop_av1;
unsigned int dec_output_prop_size_av1; unsigned int dec_output_prop_size_av1;
const u32 *msm_vidc_ssr_type;
unsigned int msm_vidc_ssr_type_size;
}; };
struct msm_vidc_platform { struct msm_vidc_platform {

3
qcom/opensource/video-driver/driver/platform/common/inc/perf_static_model.h
View File

@ -148,9 +148,6 @@ struct api_calculation_input {
/* used in aurora for depth map decode */ /* used in aurora for depth map decode */
u32 lumaonly_decode; u32 lumaonly_decode;
/* used in freq and bitrate table selection*/
u32 vpu_ver;
}; };
struct corner_voting { struct corner_voting {

15
qcom/opensource/video-driver/driver/platform/common/src/msm_vidc_platform.c
View File

@ -22,10 +22,6 @@
#include "hfi_property.h" #include "hfi_property.h"
#include "venus_hfi.h" #include "venus_hfi.h"
#if defined(CONFIG_MSM_VIDC_VOLCANO)
#include "msm_vidc_volcano.h"
#include "msm_vidc_iris2.h"
#endif
#if defined(CONFIG_MSM_VIDC_PINEAPPLE) #if defined(CONFIG_MSM_VIDC_PINEAPPLE)
#include "../../pineapple/inc/msm_vidc_pineapple.h" #include "../../pineapple/inc/msm_vidc_pineapple.h"
#include "../../cliffs/inc/msm_vidc_cliffs.h" #include "../../cliffs/inc/msm_vidc_cliffs.h"
@ -69,12 +65,12 @@
* 3x3 transformation matrix coefficients in s4.9 fixed point format * 3x3 transformation matrix coefficients in s4.9 fixed point format
*/ */
u32 vpe_csc_custom_matrix_coeff[MAX_MATRIX_COEFFS] = { u32 vpe_csc_custom_matrix_coeff[MAX_MATRIX_COEFFS] = {
440, 8140, 8098, 0, 460, 52, 0, 34, 463 0x1BE, 0x1FCC, 0x1FA1, 0, 0x1CC, 0x34, 0, 0x22, 0x1CF
}; };
/* offset coefficients in s9 fixed point format */ /* offset coefficients in s9 fixed point format */
u32 vpe_csc_custom_bias_coeff[MAX_BIAS_COEFFS] = { u32 vpe_csc_custom_bias_coeff[MAX_BIAS_COEFFS] = {
53, 0, 4 0x32, 0, 0x4
}; };
/* clamping value for Y/U/V([min,max] for Y/U/V) */ /* clamping value for Y/U/V([min,max] for Y/U/V) */
@ -247,13 +243,6 @@ static const struct msm_vidc_compat_handle compat_handle[] = {
.init_iris = msm_vidc_init_iris2, .init_iris = msm_vidc_init_iris2,
}, },
#endif #endif
#if defined(CONFIG_MSM_VIDC_VOLCANO)
{
.compat = "qcom,volcano-vidc",
.init_platform = msm_vidc_init_platform_volcano,
.init_iris = msm_vidc_init_iris2,
},
#endif
}; };
static int msm_vidc_init_ops(struct msm_vidc_core *core) static int msm_vidc_init_ops(struct msm_vidc_core *core)

38
qcom/opensource/video-driver/driver/platform/kalama/src/msm_vidc_kalama.c
View File

@ -2091,7 +2091,12 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_kala
NULL, NULL,
msm_vidc_set_req_sync_frame}, msm_vidc_set_req_sync_frame},
{BIT_RATE, ENC, H264 | HEVC, {BIT_RATE, ENC, H264,
{PEAK_BITRATE, BITRATE_BOOST, L0_BR},
msm_vidc_adjust_bitrate,
msm_vidc_set_bitrate},
{BIT_RATE, ENC, HEVC,
{PEAK_BITRATE, BITRATE_BOOST, L0_BR}, {PEAK_BITRATE, BITRATE_BOOST, L0_BR},
msm_vidc_adjust_bitrate, msm_vidc_adjust_bitrate,
msm_vidc_set_bitrate}, msm_vidc_set_bitrate},
@ -2421,11 +2426,21 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_kala
msm_vidc_adjust_input_buf_host_max_count, msm_vidc_adjust_input_buf_host_max_count,
msm_vidc_set_u32}, msm_vidc_set_u32},
{INPUT_BUF_HOST_MAX_COUNT, ENC, H264 | HEVC,
{0},
msm_vidc_adjust_input_buf_host_max_count,
msm_vidc_set_u32},
{OUTPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, {OUTPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL,
{0}, {0},
msm_vidc_adjust_output_buf_host_max_count, msm_vidc_adjust_output_buf_host_max_count,
msm_vidc_set_u32}, msm_vidc_set_u32},
{OUTPUT_BUF_HOST_MAX_COUNT, ENC, H264 | HEVC,
{0},
msm_vidc_adjust_output_buf_host_max_count,
msm_vidc_set_u32},
{CONCEAL_COLOR_8BIT, DEC, CODECS_ALL, {CONCEAL_COLOR_8BIT, DEC, CODECS_ALL,
{0}, {0},
NULL, NULL,
@ -2441,6 +2456,16 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_kala
NULL, NULL,
msm_vidc_set_stage}, msm_vidc_set_stage},
{STAGE, ENC, H264 | HEVC,
{0},
NULL,
msm_vidc_set_stage},
{STAGE, DEC, H264 | HEVC | VP9 | AV1,
{0},
NULL,
msm_vidc_set_stage},
{PIPE, DEC | ENC, CODECS_ALL, {PIPE, DEC | ENC, CODECS_ALL,
{0}, {0},
NULL, NULL,
@ -2696,13 +2721,6 @@ static const u32 kalama_vdec_output_properties_av1[] = {
HFI_PROP_FENCE, HFI_PROP_FENCE,
}; };
static const u32 kalama_msm_vidc_ssr_type[] = {
HFI_SSR_TYPE_SW_ERR_FATAL,
HFI_SSR_TYPE_SW_DIV_BY_ZERO,
HFI_SSR_TYPE_CPU_WDOG_IRQ,
HFI_SSR_TYPE_NOC_ERROR,
};
static const struct msm_vidc_platform_data kalama_data = { static const struct msm_vidc_platform_data kalama_data = {
/* resources dependent on other module */ /* resources dependent on other module */
.bw_tbl = kalama_bw_table, .bw_tbl = kalama_bw_table,
@ -2767,10 +2785,6 @@ static const struct msm_vidc_platform_data kalama_data = {
.dec_output_prop_size_hevc = ARRAY_SIZE(kalama_vdec_output_properties_hevc), .dec_output_prop_size_hevc = ARRAY_SIZE(kalama_vdec_output_properties_hevc),
.dec_output_prop_size_vp9 = ARRAY_SIZE(kalama_vdec_output_properties_vp9), .dec_output_prop_size_vp9 = ARRAY_SIZE(kalama_vdec_output_properties_vp9),
.dec_output_prop_size_av1 = ARRAY_SIZE(kalama_vdec_output_properties_av1), .dec_output_prop_size_av1 = ARRAY_SIZE(kalama_vdec_output_properties_av1),
.msm_vidc_ssr_type = kalama_msm_vidc_ssr_type,
.msm_vidc_ssr_type_size = ARRAY_SIZE(kalama_msm_vidc_ssr_type),
}; };
static const struct msm_vidc_platform_data kalama_data_v2 = { static const struct msm_vidc_platform_data kalama_data_v2 = {

13
qcom/opensource/video-driver/driver/platform/pineapple/src/msm_vidc_pineapple.c
View File

@ -290,7 +290,7 @@ static struct msm_platform_core_capability core_data_pineapple[] = {
{MAX_NUM_4K_SESSIONS, 8}, {MAX_NUM_4K_SESSIONS, 8},
{MAX_NUM_8K_SESSIONS, 2}, {MAX_NUM_8K_SESSIONS, 2},
{MAX_SECURE_SESSION_COUNT, 3}, {MAX_SECURE_SESSION_COUNT, 3},
{MAX_RT_MBPF, 259200}, /* ((7680x4320)/256) * 2)*/ {MAX_RT_MBPF, 259200}, /* ((7680x4320)/256) * 2)*/
{MAX_MBPF, 278528}, /* ((8192x4352)/256) * 2 */ {MAX_MBPF, 278528}, /* ((8192x4352)/256) * 2 */
{MAX_MBPS, 7833600}, {MAX_MBPS, 7833600},
/* max_load /* max_load
@ -2879,13 +2879,6 @@ static const u32 pineapple_vdec_output_properties_av1[] = {
HFI_PROP_FENCE, HFI_PROP_FENCE,
}; };
static const u32 pineapple_msm_vidc_ssr_type[] = {
HFI_SSR_TYPE_SW_ERR_FATAL,
HFI_SSR_TYPE_SW_DIV_BY_ZERO,
HFI_SSR_TYPE_CPU_WDOG_IRQ,
HFI_SSR_TYPE_NOC_ERROR,
};
static const struct msm_vidc_platform_data pineapple_data = { static const struct msm_vidc_platform_data pineapple_data = {
/* resources dependent on other module */ /* resources dependent on other module */
.bw_tbl = pineapple_bw_table, .bw_tbl = pineapple_bw_table,
@ -2953,10 +2946,6 @@ static const struct msm_vidc_platform_data pineapple_data = {
.dec_output_prop_size_hevc = ARRAY_SIZE(pineapple_vdec_output_properties_hevc), .dec_output_prop_size_hevc = ARRAY_SIZE(pineapple_vdec_output_properties_hevc),
.dec_output_prop_size_vp9 = ARRAY_SIZE(pineapple_vdec_output_properties_vp9), .dec_output_prop_size_vp9 = ARRAY_SIZE(pineapple_vdec_output_properties_vp9),
.dec_output_prop_size_av1 = ARRAY_SIZE(pineapple_vdec_output_properties_av1), .dec_output_prop_size_av1 = ARRAY_SIZE(pineapple_vdec_output_properties_av1),
.msm_vidc_ssr_type = pineapple_msm_vidc_ssr_type,
.msm_vidc_ssr_type_size = ARRAY_SIZE(pineapple_msm_vidc_ssr_type),
}; };
int msm_vidc_pineapple_check_ddr_type(void) int msm_vidc_pineapple_check_ddr_type(void)

10
qcom/opensource/video-driver/driver/platform/pineapple/src/pineapple.c
View File

@ -1657,6 +1657,16 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_pine
NULL, NULL,
msm_vidc_set_stage}, msm_vidc_set_stage},
{STAGE, ENC, H264 | HEVC,
{0},
NULL,
msm_vidc_set_stage},
{STAGE, DEC, H264 | HEVC | VP9,
{0},
NULL,
msm_vidc_set_stage},
{PIPE, DEC | ENC, CODECS_ALL, {PIPE, DEC | ENC, CODECS_ALL,
{0}, {0},
NULL, NULL,

2
qcom/opensource/video-driver/driver/variant/iris2/inc/msm_vidc_iris2.h
View File

@ -9,7 +9,7 @@
#include "msm_vidc_core.h" #include "msm_vidc_core.h"
#if defined(CONFIG_MSM_VIDC_VOLCANO) #if defined(CONFIG_MSM_VIDC_WAIPIO)
int msm_vidc_init_iris2(struct msm_vidc_core *core); int msm_vidc_init_iris2(struct msm_vidc_core *core);
int msm_vidc_adjust_blur_type_iris2(void *instance, struct v4l2_ctrl *ctrl); int msm_vidc_adjust_blur_type_iris2(void *instance, struct v4l2_ctrl *ctrl);
#else #else

7
qcom/opensource/video-driver/driver/variant/iris2/src/msm_vidc_buffer_iris2.c
View File

@ -514,10 +514,9 @@ static int msm_buffer_dpb_count(struct msm_vidc_inst *inst)
/* decoder dpb buffer count */ /* decoder dpb buffer count */
if (is_decode_session(inst)) { if (is_decode_session(inst)) {
color_fmt = inst->capabilities[PIX_FMTS].value; color_fmt = inst->capabilities[PIX_FMTS].value;
if (is_linear_colorformat(color_fmt)) { if (is_linear_colorformat(color_fmt))
count = inst->fw_min_count ? count = inst->buffers.output.min_count;
inst->fw_min_count : inst->buffers.output.min_count;
}
return count; return count;
} }

26
qcom/opensource/video-driver/driver/variant/iris2/src/msm_vidc_iris2.c
View File

@ -315,9 +315,9 @@ disable_power:
d_vpr_e("%s: disable regulator vcodec failed\n", __func__); d_vpr_e("%s: disable regulator vcodec failed\n", __func__);
rc = 0; rc = 0;
} }
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk"); rc = call_res_op(core, clk_disable, core, "vcodec_clk");
if (rc) { if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__); d_vpr_e("%s: disable unprepare vcodec_clk failed\n", __func__);
rc = 0; rc = 0;
} }
@ -368,16 +368,16 @@ static int __power_off_iris2_controller(struct msm_vidc_core *core)
d_vpr_h("%s: debug bridge release failed\n", __func__); d_vpr_h("%s: debug bridge release failed\n", __func__);
/* Turn off MVP MVS0C core clock */ /* Turn off MVP MVS0C core clock */
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0c_clk"); rc = call_res_op(core, clk_disable, core, "core_clk");
if (rc) { if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0c_clk failed\n", __func__); d_vpr_e("%s: disable unprepare core_clk failed\n", __func__);
rc = 0; rc = 0;
} }
/* Disable gcc_video_axi0_clk clock */ /* Disable GCC_VIDEO_AXI0_CLK clock */
rc = call_res_op(core, clk_disable, core, "gcc_video_axi0_clk"); rc = call_res_op(core, clk_disable, core, "gcc_video_axi0");
if (rc) { if (rc) {
d_vpr_e("%s: disable unprepare gcc_video_axi0_clk failed\n", __func__); d_vpr_e("%s: disable unprepare gcc_video_axi0 failed\n", __func__);
rc = 0; rc = 0;
} }
@ -442,18 +442,18 @@ static int __power_on_iris2_controller(struct msm_vidc_core *core)
if (rc) if (rc)
goto fail_reset_ahb2axi; goto fail_reset_ahb2axi;
rc = call_res_op(core, clk_enable, core, "gcc_video_axi0_clk"); rc = call_res_op(core, clk_enable, core, "gcc_video_axi0");
if (rc) if (rc)
goto fail_clk_axi; goto fail_clk_axi;
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0c_clk"); rc = call_res_op(core, clk_enable, core, "core_clk");
if (rc) if (rc)
goto fail_clk_controller; goto fail_clk_controller;
return 0; return 0;
fail_clk_controller: fail_clk_controller:
call_res_op(core, clk_disable, core, "gcc_video_axi0_clk"); call_res_op(core, clk_disable, core, "gcc_video_axi0");
fail_clk_axi: fail_clk_axi:
fail_reset_ahb2axi: fail_reset_ahb2axi:
call_res_op(core, gdsc_off, core, "iris-ctl"); call_res_op(core, gdsc_off, core, "iris-ctl");
@ -469,7 +469,7 @@ static int __power_on_iris2_hardware(struct msm_vidc_core *core)
if (rc) if (rc)
goto fail_regulator; goto fail_regulator;
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0_clk"); rc = call_res_op(core, clk_enable, core, "vcodec_clk");
if (rc) if (rc)
goto fail_clk_controller; goto fail_clk_controller;
@ -788,10 +788,6 @@ int msm_vidc_decide_work_mode_iris2(struct msm_vidc_inst *inst)
(inst->capabilities[LOWLATENCY_MODE].value)) { (inst->capabilities[LOWLATENCY_MODE].value)) {
work_mode = MSM_VIDC_STAGE_1; work_mode = MSM_VIDC_STAGE_1;
} }
if (inst->capabilities[SLICE_MODE].value ==
V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {
work_mode = MSM_VIDC_STAGE_1;
}
if (inst->capabilities[LOSSLESS].value) if (inst->capabilities[LOSSLESS].value)
work_mode = MSM_VIDC_STAGE_2; work_mode = MSM_VIDC_STAGE_2;

21
qcom/opensource/video-driver/driver/variant/iris3/inc/hfi_buffer_iris3.h
View File

@ -1168,21 +1168,10 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
} while (0) } while (0)
#define HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \ #define HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \
frame_width_coded, codec_standard, num_vpp_pipes) \ frame_width_coded, codec_standard) \
do { \ do { \
HFI_U32 without_tile_enc_width, min_tile_size, fixed_tile_width; \ HFI_U32 without_tile_enc_width; \
if (num_vpp_pipes == 4) { \ HFI_U32 min_tile_size = 352, fixed_tile_width = 960; \
min_tile_size = 352; \
fixed_tile_width = 960; \
} \
else if (num_vpp_pipes == 2) { \
min_tile_size = 256; \
fixed_tile_width = 768; \
} \
else { \
min_tile_size = 256; \
fixed_tile_width = 672; \
} \
without_tile_enc_width = min_tile_size + fixed_tile_width; \ without_tile_enc_width = min_tile_size + fixed_tile_width; \
if ((codec_standard == HFI_CODEC_ENCODE_HEVC) && \ if ((codec_standard == HFI_CODEC_ENCODE_HEVC) && \
(frame_width_coded > without_tile_enc_width)) { \ (frame_width_coded > without_tile_enc_width)) { \
@ -1201,7 +1190,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
} while (0) } while (0)
#define HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_slice_count, frame_width, frame_height, \ #define HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_slice_count, frame_width, frame_height, \
codec_standard, multi_slice_max_mb_count, num_vpp_pipes) \ codec_standard, multi_slice_max_mb_count) \
do { \ do { \
HFI_U32 tile_size, tile_count, last_tile_size, \ HFI_U32 tile_size, tile_count, last_tile_size, \
slice_count_per_tile, slice_count_in_last_tile; \ slice_count_per_tile, slice_count_in_last_tile; \
@ -1211,7 +1200,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
frame_width_coded = HFI_ALIGN(frame_width, lcu_size); \ frame_width_coded = HFI_ALIGN(frame_width, lcu_size); \
frame_height_coded = HFI_ALIGN(frame_height, lcu_size); \ frame_height_coded = HFI_ALIGN(frame_height, lcu_size); \
HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \ HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \
frame_width_coded, codec_standard, num_vpp_pipes); \ frame_width_coded, codec_standard); \
mbs_in_one_tile = (tile_size * frame_height_coded) / (lcu_size * lcu_size); \ mbs_in_one_tile = (tile_size * frame_height_coded) / (lcu_size * lcu_size); \
slice_count_per_tile = \ slice_count_per_tile = \
(mbs_in_one_tile + multi_slice_max_mb_count - 1) / \ (mbs_in_one_tile + multi_slice_max_mb_count - 1) / \

7
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_buffer_iris3.c
View File

@ -642,13 +642,11 @@ static int msm_buffer_delivery_mode_based_min_count_iris3(struct msm_vidc_inst *
uint32_t count) uint32_t count)
{ {
struct v4l2_format *f; struct v4l2_format *f;
struct msm_vidc_core *core = NULL;
u32 width, height, total_num_slices = 1; u32 width, height, total_num_slices = 1;
u32 hfi_codec = 0; u32 hfi_codec = 0;
u32 max_mbs_per_slice = 0; u32 max_mbs_per_slice = 0;
u32 slice_mode = 0; u32 slice_mode = 0;
u32 delivery_mode = 0; u32 delivery_mode = 0;
u32 num_vpp_pipes;
slice_mode = inst->capabilities[SLICE_MODE].value; slice_mode = inst->capabilities[SLICE_MODE].value;
delivery_mode = inst->capabilities[DELIVERY_MODE].value; delivery_mode = inst->capabilities[DELIVERY_MODE].value;
@ -668,11 +666,8 @@ static int msm_buffer_delivery_mode_based_min_count_iris3(struct msm_vidc_inst *
else if (inst->codec == MSM_VIDC_HEVC) else if (inst->codec == MSM_VIDC_HEVC)
hfi_codec = HFI_CODEC_ENCODE_HEVC; hfi_codec = HFI_CODEC_ENCODE_HEVC;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_num_slices, width, height, HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_num_slices, width, height,
hfi_codec, max_mbs_per_slice, num_vpp_pipes); hfi_codec, max_mbs_per_slice);
return (total_num_slices * count); return (total_num_slices * count);
} }

54
qcom/opensource/video-driver/driver/variant/iris33/inc/hfi_buffer_iris33.h
View File

@ -1168,21 +1168,10 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
} while (0) } while (0)
#define HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \ #define HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \
frame_width_coded, codec_standard, num_vpp_pipes) \ frame_width_coded, codec_standard) \
do { \ do { \
HFI_U32 without_tile_enc_width, min_tile_size, fixed_tile_width; \ HFI_U32 without_tile_enc_width; \
if (num_vpp_pipes == 4) { \ HFI_U32 min_tile_size = 352, fixed_tile_width = 960; \
min_tile_size = 352; \
fixed_tile_width = 960; \
} \
else if (num_vpp_pipes == 2) { \
min_tile_size = 256; \
fixed_tile_width = 768; \
} \
else { \
min_tile_size = 256; \
fixed_tile_width = 672; \
} \
without_tile_enc_width = min_tile_size + fixed_tile_width; \ without_tile_enc_width = min_tile_size + fixed_tile_width; \
if ((codec_standard == HFI_CODEC_ENCODE_HEVC) && \ if ((codec_standard == HFI_CODEC_ENCODE_HEVC) && \
(frame_width_coded > without_tile_enc_width)) { \ (frame_width_coded > without_tile_enc_width)) { \
@ -1201,7 +1190,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
} while (0) } while (0)
#define HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_slice_count, frame_width, frame_height, \ #define HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_slice_count, frame_width, frame_height, \
codec_standard, multi_slice_max_mb_count, num_vpp_pipes) \ codec_standard, multi_slice_max_mb_count) \
do { \ do { \
HFI_U32 tile_size, tile_count, last_tile_size, \ HFI_U32 tile_size, tile_count, last_tile_size, \
slice_count_per_tile, slice_count_in_last_tile; \ slice_count_per_tile, slice_count_in_last_tile; \
@ -1211,7 +1200,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
frame_width_coded = HFI_ALIGN(frame_width, lcu_size); \ frame_width_coded = HFI_ALIGN(frame_width, lcu_size); \
frame_height_coded = HFI_ALIGN(frame_height, lcu_size); \ frame_height_coded = HFI_ALIGN(frame_height, lcu_size); \
HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \ HFI_IRIS3_ENC_TILE_SIZE_INFO(tile_size, tile_count, last_tile_size, \
frame_width_coded, codec_standard, num_vpp_pipes); \ frame_width_coded, codec_standard); \
mbs_in_one_tile = (tile_size * frame_height_coded) / (lcu_size * lcu_size); \ mbs_in_one_tile = (tile_size * frame_height_coded) / (lcu_size * lcu_size); \
slice_count_per_tile = \ slice_count_per_tile = \
(mbs_in_one_tile + multi_slice_max_mb_count - 1) / \ (mbs_in_one_tile + multi_slice_max_mb_count - 1) / \
@ -1546,27 +1535,11 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
#define SIZE_IR_BUF(num_lcu_in_frame) HFI_ALIGN((((((num_lcu_in_frame) << 1) + 7) &\ #define SIZE_IR_BUF(num_lcu_in_frame) HFI_ALIGN((((((num_lcu_in_frame) << 1) + 7) &\
(~7)) * 3), VENUS_DMA_ALIGNMENT) (~7)) * 3), VENUS_DMA_ALIGNMENT)
#define SIZE_VPSS_LINE_BUF(_size, num_vpp_pipes_enc, frame_height_coded, \ #define SIZE_VPSS_LINE_BUF(num_vpp_pipes_enc, frame_height_coded, \
frame_width_coded) \ frame_width_coded) \
do { \ (HFI_ALIGN(((((((8192) >> 2) << 5) * (num_vpp_pipes_enc)) + 64) + \
HFI_U32 vpss_4tap_top = 0, vpss_4tap_left = 0, vpss_div2_top = 0, \ (((((MAX((frame_width_coded), (frame_height_coded)) + 3) >> 2) << 5) +\
vpss_div2_left = 0, vpss_top_lb = 0, vpss_left_lb = 0, \ 256) * 16)), VENUS_DMA_ALIGNMENT))
size_left = 0, size_top = 0, color_comp = 2; \
vpss_4tap_top = (((((MAX((frame_width_coded), (frame_height_coded)) \
* 2) + 3) >> 2) << 4) + 256); \
vpss_4tap_left = ((((8192 + 3) >> 2) << 5) + 64);\
vpss_div2_top = ((((MAX((frame_width_coded), (frame_height_coded)) \
+ 3) >> 2) << 4) + 256); \
vpss_div2_left = (((((MAX((frame_width_coded), (frame_height_coded)) \
* 2) + 3) >> 2) << 5) + 64); \
vpss_top_lb = (((frame_width_coded) + 1) << 3); \
vpss_left_lb = (((frame_height_coded) << 3) * (num_vpp_pipes_enc)); \
size_left = (((vpss_4tap_left) + (vpss_div2_left)) * (color_comp) \
* (num_vpp_pipes_enc)); \
size_top = (((vpss_4tap_top) + (vpss_div2_top)) * (color_comp)); \
_size = ((size_left) + (size_top) + (vpss_top_lb) + (vpss_left_lb)); \
_size = (HFI_ALIGN(_size, VENUS_DMA_ALIGNMENT)); \
} while (0)
#define SIZE_TOP_LINE_BUF_FIRST_STG_SAO(frame_width_coded) \ #define SIZE_TOP_LINE_BUF_FIRST_STG_SAO(frame_width_coded) \
HFI_ALIGN((16 * ((frame_width_coded) >> 5)), VENUS_DMA_ALIGNMENT) HFI_ALIGN((16 * ((frame_width_coded) >> 5)), VENUS_DMA_ALIGNMENT)
@ -1581,7 +1554,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
top_line_buff_ctrl_fe_size = 0; \ top_line_buff_ctrl_fe_size = 0; \
HFI_U32 left_line_buff_metadata_recon__y__size = 0, \ HFI_U32 left_line_buff_metadata_recon__y__size = 0, \
left_line_buff_metadata_recon__uv__size = 0, \ left_line_buff_metadata_recon__uv__size = 0, \
line_buff_recon_pix_size = 0, vpss_line_buff_size = 0; \ line_buff_recon_pix_size = 0; \
width_in_lcus = ((frame_width) + (lcu_size)-1) / (lcu_size); \ width_in_lcus = ((frame_width) + (lcu_size)-1) / (lcu_size); \
height_in_lcus = ((frame_height) + (lcu_size)-1) / (lcu_size); \ height_in_lcus = ((frame_height) + (lcu_size)-1) / (lcu_size); \
frame_width_coded = width_in_lcus * (lcu_size); \ frame_width_coded = width_in_lcus * (lcu_size); \
@ -1602,8 +1575,6 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
frame_height_coded, is_ten_bit, num_vpp_pipes_enc); \ frame_height_coded, is_ten_bit, num_vpp_pipes_enc); \
SIZE_LINEBUFF_RECON_PIX(line_buff_recon_pix_size, is_ten_bit,\ SIZE_LINEBUFF_RECON_PIX(line_buff_recon_pix_size, is_ten_bit,\
frame_width_coded); \ frame_width_coded); \
SIZE_VPSS_LINE_BUF(vpss_line_buff_size, num_vpp_pipes_enc, \
frame_height_coded, frame_width_coded); \
_size = SIZE_LINE_BUF_CTRL(frame_width_coded) + \ _size = SIZE_LINE_BUF_CTRL(frame_width_coded) + \
SIZE_LINE_BUF_CTRL_ID2(frame_width_coded) + \ SIZE_LINE_BUF_CTRL_ID2(frame_width_coded) + \
line_buff_data_size + \ line_buff_data_size + \
@ -1613,9 +1584,10 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
left_line_buff_metadata_recon__y__size + \ left_line_buff_metadata_recon__y__size + \
left_line_buff_metadata_recon__uv__size + \ left_line_buff_metadata_recon__uv__size + \
line_buff_recon_pix_size + \ line_buff_recon_pix_size + \
vpss_line_buff_size + \
SIZE_LEFT_LINEBUFF_CTRL_FE(frame_height_coded, \ SIZE_LEFT_LINEBUFF_CTRL_FE(frame_height_coded, \
num_vpp_pipes_enc) + SIZE_LINE_BUF_SDE(frame_width_coded) + \ num_vpp_pipes_enc) + SIZE_LINE_BUF_SDE(frame_width_coded) + \
SIZE_VPSS_LINE_BUF(num_vpp_pipes_enc, frame_height_coded, \
frame_width_coded) + \
SIZE_TOP_LINE_BUF_FIRST_STG_SAO(frame_width_coded); \ SIZE_TOP_LINE_BUF_FIRST_STG_SAO(frame_width_coded); \
} while (0) } while (0)

7
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_buffer_iris33.c
View File

@ -649,13 +649,11 @@ static int msm_buffer_delivery_mode_based_min_count_iris33(struct msm_vidc_inst
uint32_t count) uint32_t count)
{ {
struct v4l2_format *f; struct v4l2_format *f;
struct msm_vidc_core *core = NULL;
u32 width, height, total_num_slices = 1; u32 width, height, total_num_slices = 1;
u32 hfi_codec = 0; u32 hfi_codec = 0;
u32 max_mbs_per_slice = 0; u32 max_mbs_per_slice = 0;
u32 slice_mode = 0; u32 slice_mode = 0;
u32 delivery_mode = 0; u32 delivery_mode = 0;
u32 num_vpp_pipes;
slice_mode = inst->capabilities[SLICE_MODE].value; slice_mode = inst->capabilities[SLICE_MODE].value;
delivery_mode = inst->capabilities[DELIVERY_MODE].value; delivery_mode = inst->capabilities[DELIVERY_MODE].value;
@ -675,11 +673,8 @@ static int msm_buffer_delivery_mode_based_min_count_iris33(struct msm_vidc_inst
else if (inst->codec == MSM_VIDC_HEVC) else if (inst->codec == MSM_VIDC_HEVC)
hfi_codec = HFI_CODEC_ENCODE_HEVC; hfi_codec = HFI_CODEC_ENCODE_HEVC;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_num_slices, width, height, HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_num_slices, width, height,
hfi_codec, max_mbs_per_slice, num_vpp_pipes); hfi_codec, max_mbs_per_slice);
return (total_num_slices * count); return (total_num_slices * count);
} }

33
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_bus_iris33.c
View File

@ -243,10 +243,9 @@ static int calculate_bandwidth_decoder_iris33(
u32 dpb_to_opb_ratios_ds = 1; u32 dpb_to_opb_ratios_ds = 1;
u8 llc_enabled_ref_y_rd; u8 llc_enabled_ref_y_rd = 1;
u8 llc_enable_ref_crcb_rd; u8 llc_enable_ref_crcb_rd = 1;
u8 llc_enabled_bse_tlb; u8 llc_enabled_bse_tlb = 1;
/* this is for 2pipe and 1pipe LLC */ /* this is for 2pipe and 1pipe LLC */
u8 llc_enable_probtable_av1d_21pipe = 0; u8 llc_enable_probtable_av1d_21pipe = 0;
@ -266,16 +265,6 @@ static int calculate_bandwidth_decoder_iris33(
u32 large_bw_calculation_fp = 0; u32 large_bw_calculation_fp = 0;
if (codec_input.pipe_num == 4) {
llc_enabled_ref_y_rd = 1;
llc_enable_ref_crcb_rd = 1;
llc_enabled_bse_tlb = 1;
} else if (codec_input.pipe_num == 2) {
llc_enabled_ref_y_rd = 0; // llc 128kb for palawan
llc_enable_ref_crcb_rd = 0;
llc_enabled_bse_tlb = (codec_input.status_llc_onoff == 1) ? 1 : 0;
}
llc_enabled_ref_y_rd = (codec_input.status_llc_onoff) ? 1 : 0; llc_enabled_ref_y_rd = (codec_input.status_llc_onoff) ? 1 : 0;
llc_enable_ref_crcb_rd = (codec_input.status_llc_onoff) ? 1 : 0; llc_enable_ref_crcb_rd = (codec_input.status_llc_onoff) ? 1 : 0;
/* H265D BSE tlb in LLC will be pored in Kailua */ /* H265D BSE tlb in LLC will be pored in Kailua */
@ -672,8 +661,8 @@ static int calculate_bandwidth_encoder_iris33(
u32 reference_y_read_bw_factor; u32 reference_y_read_bw_factor;
u32 reference_crcb_read_bw_factor; u32 reference_crcb_read_bw_factor;
/* encoder control parameters */
u32 en_vertical_tiles_width = 960; u32 en_vertical_tiles_width = 960;
u32 en_search_windows_size_horizontal = 96;
u8 en_rotation_90_270 = 0; u8 en_rotation_90_270 = 0;
/* TODO Can we use (codec_input.status_llc_onoff) for enc_llc_*? */ /* TODO Can we use (codec_input.status_llc_onoff) for enc_llc_*? */
@ -682,6 +671,7 @@ static int calculate_bandwidth_encoder_iris33(
u8 en_llc_enable_ref_rd_y_overlap = 0; u8 en_llc_enable_ref_rd_y_overlap = 0;
u32 en_bins_to_bits_factor = 4; u32 en_bins_to_bits_factor = 4;
u32 en_search_windows_size_horizontal = 96;
u32 en_tile_number; u32 en_tile_number;
u32 ipb_compression_factor_y; u32 ipb_compression_factor_y;
@ -696,17 +686,6 @@ static int calculate_bandwidth_encoder_iris33(
/*H265D BSE tlb in LLC will be pored in Kailua */ /*H265D BSE tlb in LLC will be pored in Kailua */
llc_enabled_bse_tlb = (codec_input.status_llc_onoff) ? 1 : 0; llc_enabled_bse_tlb = (codec_input.status_llc_onoff) ? 1 : 0;
/* encoder control parameters
* iris3 2pipe uses 768 vertical tile width for IPP GoP
*/
if (codec_input.pipe_num == 2) {
en_vertical_tiles_width =
(codec_input.hierachical_layer == CODEC_GOP_IPP) ? 768 : 576;
// search ranges for iris3 2pipe
en_search_windows_size_horizontal =
(codec_input.hierachical_layer == CODEC_GOP_IPP) ? 192 : 96;
}
frame_width = codec_input.frame_width; frame_width = codec_input.frame_width;
frame_height = codec_input.frame_height; frame_height = codec_input.frame_height;
if ((codec_input.codec == CODEC_H264) || if ((codec_input.codec == CODEC_H264) ||
@ -740,7 +719,7 @@ static int calculate_bandwidth_encoder_iris33(
} else { /* RGBA */ } else { /* RGBA */
frame420_y_bw_linear_8bpp = frame420_y_bw_linear_8bpp =
((calculate_number_ubwctiles_iris33(frame_width, frame_height, ((calculate_number_ubwctiles_iris33(frame_width, frame_height,
16, 4) * 256 * codec_input.frame_rate + 999) / 1000 + 999) / 1000; 6, 4) * 256 * codec_input.frame_rate + 999) / 1000 + 999) / 1000;
} }
frame420_y_bw_no_ubwc_tile_10bpp = frame420_y_bw_no_ubwc_tile_10bpp =

78
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_clock_iris33.c
View File

@ -5,7 +5,6 @@
#include "perf_static_model.h" #include "perf_static_model.h"
#include "msm_vidc_debug.h" #include "msm_vidc_debug.h"
#include "msm_vidc_platform.h"
#define ENABLE_FINEBITRATE_SUBUHD60 0 #define ENABLE_FINEBITRATE_SUBUHD60 0
@ -23,11 +22,6 @@ static u32 frequency_table_iris33[2][6] = {
{840, 720, 652, 570, 450, 294}, {840, 720, 652, 570, 450, 294},
}; };
static u32 frequency_table_iris33_2p[2][6] = {
/* //make lowsvs_D1 as invalid; */
{ 533, 444, 366, 338, 240, 192 },
{ 800, 666, 549, 507, 360, 288 },
};
/* /*
* TODO Move to pineapple.c * TODO Move to pineapple.c
@ -74,15 +68,6 @@ static u32 pipe_penalty_iris33[3][3] = {
{2039, 2464, 1191}, {2039, 2464, 1191},
}; };
static u32 pipe_penalty_iris33_2p[3][3] = {
/* NON AV1 */
{ 1059, 1059, 1059 },
/* AV1 RECOMMENDED TILE 1080P_V2XH1, UHD_V2X2, 8KUHD_V8X2 */
{ 1123, 1079, 1079 },
/* AV1 YOUTUBE/NETFLIX TILE 1080P_V4XH2_V4X1, UHD_V8X4_V8X1, 8KUHD_V8X8_V8X1 */
{ 1197, 1287, 1051 },
};
/* /*
* Video IP Core Technology: bitrate constraint * Video IP Core Technology: bitrate constraint
* HW limit bitrate table (these values are measured end to end fw/sw impacts are also considered) * HW limit bitrate table (these values are measured end to end fw/sw impacts are also considered)
@ -101,18 +86,6 @@ static u32 bitrate_table_iris33_2stage_fp[5][10] = {
{130, 130, 120, 120, 120, 120, 120, 120, 120, 120}, {130, 130, 120, 120, 120, 120, 120, 120, 120, 120},
}; };
static u32 bitrate_table_iris33_2p_2stage_fp[5][10] = {
/* h264 cavlc */
{ 0, 220, 220, 220, 220, 220, 220, 220, 220, 220 },
/* h264 cabac */
{ 0, 140, 150, 160, 160, 160, 160, 160, 160, 160 },
/* h265 */
{ 90, 140, 160, 160, 160, 160, 160, 160, 160, 160 },
/*vp9 */
{ 90, 90, 90, 90, 90, 90, 90, 90, 90, 90 },
{ 130, 130, 120, 120, 120, 120, 120, 120, 120, 120 },
};
/* /*
* HW limit bitrate table (these values are measured * HW limit bitrate table (these values are measured
* end to end fw/sw impacts are also considered) * end to end fw/sw impacts are also considered)
@ -323,8 +296,6 @@ u32 get_bitrate_entry(u32 pixle_count)
static int calculate_vsp_min_freq(struct api_calculation_input codec_input, static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output) struct api_calculation_freq_output *codec_output)
{ {
u32 (*frequency_table_value)[6];
u32 (*bitrate_table_2stage_value)[10];
/* /*
* VSP calculation * VSP calculation
* different methodology from Lahaina * different methodology from Lahaina
@ -346,14 +317,6 @@ static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
input_bitrate_fp = ((u32)(codec_input.bitrate_mbps * 100 + 99)) / 100; input_bitrate_fp = ((u32)(codec_input.bitrate_mbps * 100 + 99)) / 100;
if (codec_input.vpu_ver == VPU_VERSION_IRIS33) {
frequency_table_value = frequency_table_iris33;
bitrate_table_2stage_value = bitrate_table_iris33_2stage_fp;
} else if (codec_input.vpu_ver == VPU_VERSION_IRIS33_2P) {
frequency_table_value = frequency_table_iris33_2p;
bitrate_table_2stage_value = bitrate_table_iris33_2p_2stage_fp;
}
/* 8KUHD60fps with B frame */ /* 8KUHD60fps with B frame */
if ((pixle_count >= fp_pixel_count_bar0) && if ((pixle_count >= fp_pixel_count_bar0) &&
(codec_input.hierachical_layer != CODEC_GOP_IPP)) { (codec_input.hierachical_layer != CODEC_GOP_IPP)) {
@ -371,26 +334,26 @@ static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
* TODO : Reduce these conditions by removing the zero entries from Bitrate table. * TODO : Reduce these conditions by removing the zero entries from Bitrate table.
*/ */
vsp_hw_min_frequency = frequency_table_value[0][2] * vsp_hw_min_frequency = frequency_table_iris33[0][2] *
input_bitrate_fp * 1000; input_bitrate_fp * 1000;
if (codec_input.codec == CODEC_AV1) if (codec_input.codec == CODEC_AV1)
vsp_hw_min_frequency = frequency_table_value[0][1] * vsp_hw_min_frequency = frequency_table_iris33[0][1] *
input_bitrate_fp * 1000; input_bitrate_fp * 1000;
if ((codec_input.codec == CODEC_H264) || if ((codec_input.codec == CODEC_H264) ||
(codec_input.codec == CODEC_H264_CAVLC)) { (codec_input.codec == CODEC_H264_CAVLC)) {
vsp_hw_min_frequency = (frequency_table_value[0][2] * 1000 + vsp_hw_min_frequency = (frequency_table_iris33[0][2] * 1000 +
(fw_sw_vsp_offset - 1)); (fw_sw_vsp_offset - 1));
vsp_hw_min_frequency = vsp_hw_min_frequency =
DIV_ROUND_UP(vsp_hw_min_frequency, fw_sw_vsp_offset); DIV_ROUND_UP(vsp_hw_min_frequency, fw_sw_vsp_offset);
} else { } else {
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) { if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
vsp_hw_min_frequency = vsp_hw_min_frequency + vsp_hw_min_frequency = vsp_hw_min_frequency +
(bitrate_table_2stage_value[codec][0] * (bitrate_table_iris33_2stage_fp[codec][0] *
fw_sw_vsp_offset - 1); fw_sw_vsp_offset - 1);
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency, vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_2stage_value[codec][0]) * (bitrate_table_iris33_2stage_fp[codec][0]) *
fw_sw_vsp_offset); fw_sw_vsp_offset);
} else { } else {
vsp_hw_min_frequency = vsp_hw_min_frequency + vsp_hw_min_frequency = vsp_hw_min_frequency +
@ -402,19 +365,19 @@ static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
} }
} }
} else { } else {
vsp_hw_min_frequency = frequency_table_value[0][2] * vsp_hw_min_frequency = frequency_table_iris33[0][2] *
input_bitrate_fp * 1000; input_bitrate_fp * 1000;
if (codec_input.codec == CODEC_AV1 && bitrate_entry == 1) if (codec_input.codec == CODEC_AV1 && bitrate_entry == 1)
vsp_hw_min_frequency = frequency_table_value[0][1] * vsp_hw_min_frequency = frequency_table_iris33[0][1] *
input_bitrate_fp * 1000; input_bitrate_fp * 1000;
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) { if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
vsp_hw_min_frequency = vsp_hw_min_frequency + vsp_hw_min_frequency = vsp_hw_min_frequency +
(bitrate_table_2stage_value[codec][bitrate_entry] * (bitrate_table_iris33_2stage_fp[codec][bitrate_entry] *
fw_sw_vsp_offset - 1); fw_sw_vsp_offset - 1);
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency, vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_2stage_value[codec][bitrate_entry]) * (bitrate_table_iris33_2stage_fp[codec][bitrate_entry]) *
fw_sw_vsp_offset); fw_sw_vsp_offset);
} else { } else {
vsp_hw_min_frequency = vsp_hw_min_frequency + vsp_hw_min_frequency = vsp_hw_min_frequency +
@ -435,37 +398,31 @@ static u32 calculate_pipe_penalty(struct api_calculation_input codec_input)
u32 pipe_penalty_codec = 0; u32 pipe_penalty_codec = 0;
u8 avid_commercial_content = 0; u8 avid_commercial_content = 0;
u32 pixel_count = 0; u32 pixel_count = 0;
u32 (*pipe_penalty_value)[3];
if (codec_input.vpu_ver == VPU_VERSION_IRIS33)
pipe_penalty_value = pipe_penalty_iris33;
else if (codec_input.vpu_ver == VPU_VERSION_IRIS33_2P)
pipe_penalty_value = pipe_penalty_iris33_2p;
/* decoder */ /* decoder */
if (codec_input.decoder_or_encoder == CODEC_DECODER) { if (codec_input.decoder_or_encoder == CODEC_DECODER) {
pipe_penalty_codec = pipe_penalty_value[0][0]; pipe_penalty_codec = pipe_penalty_iris33[0][0];
avid_commercial_content = codec_input.av1d_commer_tile_enable; avid_commercial_content = codec_input.av1d_commer_tile_enable;
if (codec_input.codec == CODEC_AV1) { if (codec_input.codec == CODEC_AV1) {
pixel_count = codec_input.frame_width * codec_input.frame_height; pixel_count = codec_input.frame_width * codec_input.frame_height;
if (pixel_count <= 1920 * 1080) if (pixel_count <= 1920 * 1080)
pipe_penalty_codec = pipe_penalty_codec =
pipe_penalty_value[avid_commercial_content + 1][0]; pipe_penalty_iris33[avid_commercial_content + 1][0];
else if (pixel_count < 3840 * 2160) else if (pixel_count < 3840 * 2160)
pipe_penalty_codec = pipe_penalty_codec =
(pipe_penalty_value[avid_commercial_content + 1][0] + (pipe_penalty_iris33[avid_commercial_content + 1][0] +
pipe_penalty_value[avid_commercial_content + 1][1]) / 2; pipe_penalty_iris33[avid_commercial_content + 1][1]) / 2;
else if ((pixel_count == 3840 * 2160) || else if ((pixel_count == 3840 * 2160) ||
(pixel_count == 4096 * 2160) || (pixel_count == 4096 * 2304)) (pixel_count == 4096 * 2160) || (pixel_count == 4096 * 2304))
pipe_penalty_codec = pipe_penalty_codec =
pipe_penalty_value[avid_commercial_content + 1][1]; pipe_penalty_iris33[avid_commercial_content + 1][1];
else if (pixel_count < 7680 * 4320) else if (pixel_count < 7680 * 4320)
pipe_penalty_codec = pipe_penalty_codec =
(pipe_penalty_value[avid_commercial_content + 1][1] + (pipe_penalty_iris33[avid_commercial_content + 1][1] +
pipe_penalty_value[avid_commercial_content + 1][2]) / 2; pipe_penalty_iris33[avid_commercial_content + 1][2]) / 2;
else else
pipe_penalty_codec = pipe_penalty_codec =
pipe_penalty_value[avid_commercial_content + 1][2]; pipe_penalty_iris33[avid_commercial_content + 1][2];
} }
} else { } else {
pipe_penalty_codec = 101; pipe_penalty_codec = 101;
@ -518,6 +475,7 @@ static int calculate_vpp_min_freq(struct api_calculation_input codec_input,
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) { if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
/* FW overhead, convert FW cycles to impact to one pipe */ /* FW overhead, convert FW cycles to impact to one pipe */
u64 decoder_vpp_fw_overhead = 0;
decoder_vpp_fw_overhead = decoder_vpp_fw_overhead =
DIV_ROUND_UP((decoder_vpp_fw_overhead * 10 * DIV_ROUND_UP((decoder_vpp_fw_overhead * 10 *

255
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_iris33.c
View File

@ -134,10 +134,6 @@ typedef enum {
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33 (NOC_BASE_OFFS + 0xA038) #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33 (NOC_BASE_OFFS + 0xA038)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33 (NOC_BASE_OFFS + 0xA03C) #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33 (NOC_BASE_OFFS + 0xA03C)
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33 (NOC_BASE_OFFS + 0x7040) #define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33 (NOC_BASE_OFFS + 0x7040)
#define VCODEC_NOC_SidebandManager_SenseIn0_Low (NOC_BASE_OFFS + 0x7100)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH (NOC_BASE_OFFS + 0x7104)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH (NOC_BASE_OFFS + 0x710C)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW (NOC_BASE_OFFS + 0x7110)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_MAINCTL_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3508) #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_MAINCTL_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3508)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRCLR_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3518) #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRCLR_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3518)
@ -150,12 +146,6 @@ typedef enum {
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3538) #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3538)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33_2P (NOC_BASE_OFFS + 0x353C) #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33_2P (NOC_BASE_OFFS + 0x353C)
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3240) #define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3240)
#define VCODEC_NOC_SidebandManager_SenseIn0_Low_2P (NOC_BASE_OFFS + 0x3300)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P (NOC_BASE_OFFS + 0x3304)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P (NOC_BASE_OFFS + 0x330C)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P (NOC_BASE_OFFS + 0x3310)
#define VCODEC_DMA_SPARE_3 0x87B8
static int __interrupt_init_iris33(struct msm_vidc_core *core) static int __interrupt_init_iris33(struct msm_vidc_core *core)
{ {
@ -292,9 +282,8 @@ static bool is_iris33_hw_power_collapsed(struct msm_vidc_core *core)
static int __power_off_iris33_hardware(struct msm_vidc_core *core) static int __power_off_iris33_hardware(struct msm_vidc_core *core)
{ {
int rc = 0, i; int rc = 0, i;
u32 value = 0, count = 0; u32 value = 0;
bool pwr_collapsed = false; bool pwr_collapsed = false;
u32 sense0_low, sense0_high, sense1_high, sense2_low;
/* /*
* Incase hw power control is enabled, for any error case * Incase hw power control is enabled, for any error case
@ -315,10 +304,6 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
} }
} }
rc = call_res_op(core, gdsc_sw_ctrl, core);
if (rc)
return rc;
/* /*
* check to make sure core clock branch enabled else * check to make sure core clock branch enabled else
* we cannot read vcodec top idle register * we cannot read vcodec top idle register
@ -335,10 +320,6 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
return rc; return rc;
} }
rc = __write_register_masked(core, VCODEC_DMA_SPARE_3, 0x1, BIT(0));
if (rc)
return rc;
/* /*
* add MNoC idle check before collapsing MVS0 per HPG update * add MNoC idle check before collapsing MVS0 per HPG update
* poll for NoC DMA idle -> HPG 6.1.1 * poll for NoC DMA idle -> HPG 6.1.1
@ -357,84 +338,15 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
if (rc) if (rc)
return rc; return rc;
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value); rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_LPI_STATUS,
if (rc) 0x1, 0x1, 200, 2000);
return rc; if (rc)
d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
while ((!(value & BIT(0))) && (value & BIT(1) || value & BIT(2))) { rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x0, BIT(0));
0x0, BIT(0)); if (rc)
if (rc) return rc;
return rc;
usleep_range(10, 20);
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x1, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value);
if (rc)
return rc;
++count;
if (count >= 1000) {
d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
break;
}
}
if (count < 1000) {
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
}
i = 0;
do {
value = 0;
if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33) {
__read_register(core,
VCODEC_NOC_SidebandManager_SenseIn0_Low,
&sense0_low);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH,
&sense0_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH,
&sense1_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW,
&sense2_low);
} else if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33_2P) {
__read_register(core,
VCODEC_NOC_SidebandManager_SenseIn0_Low_2P,
&sense0_low);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P,
&sense0_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P,
&sense1_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P,
&sense2_low);
}
value = ((sense0_low & 0x00008000) ||
(sense0_high & 0x00000800) ||
(sense1_high & 0x00800000) ||
(sense2_low & 0x00002000));
usleep_range(10, 20);
i++;
} while ((value) && (i <= 100));
d_vpr_h("%s: sideband register value = %d\n", __func__, value);
/* /*
* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ) * Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ)
@ -458,13 +370,19 @@ disable_power:
rc = 0; rc = 0;
} }
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
rc = 0;
}
return rc; return rc;
} }
static int __power_off_iris33_controller(struct msm_vidc_core *core) static int __power_off_iris33_controller(struct msm_vidc_core *core)
{ {
int noc_lpi_status = 0, count = 0; int rc = 0;
int rc = 0, value = 0; int value = 0;
/* /*
* mask fal10_veto QLPAC error since fal10_veto can go 1 * mask fal10_veto QLPAC error since fal10_veto can go 1
@ -583,7 +501,7 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core)
d_vpr_e("%s: MVP_NOC_CORE_SW_RESET failed\n", __func__); d_vpr_e("%s: MVP_NOC_CORE_SW_RESET failed\n", __func__);
/* De-assert video_cc XO reset */ /* De-assert video_cc XO reset */
usleep_range(80, 100); usleep_range(200, 300);
rc = call_res_op(core, reset_control_deassert, core, "video_xo_reset"); rc = call_res_op(core, reset_control_deassert, core, "video_xo_reset");
if (rc) if (rc)
d_vpr_e("%s: deassert video_xo_reset failed\n", __func__); d_vpr_e("%s: deassert video_xo_reset failed\n", __func__);
@ -605,12 +523,6 @@ skip_video_xo_reset:
if (rc) if (rc)
return rc; return rc;
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
rc = 0;
}
/* remove retain mem and retain peripheral */ /* remove retain mem and retain peripheral */
rc = call_res_op(core, clk_set_flag, core, rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH); "video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
@ -629,129 +541,6 @@ skip_video_xo_reset:
rc = 0; rc = 0;
} }
if (!is_core_state(core, MSM_VIDC_CORE_ERROR))
goto power_down;
/* power cycle process to recover from NoC error */
rc = call_res_op(core, gdsc_off, core, "iris-ctl");
if (rc) {
d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
rc = 0;
}
call_res_op(core, gdsc_on, core, "iris-ctl");
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0c_clk");
/* assert and deassert axi and mvs0c resets */
rc = call_res_op(core, reset_control_assert, core, "video_axi_reset");
if (rc)
d_vpr_e("%s: assert video_axi_reset failed\n", __func__);
/* set retain mem and peripheral before asset mvs0c reset */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_MEM);
if (rc)
d_vpr_e("%s: set retain mem failed\n", __func__);
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_PERIPH);
if (rc)
d_vpr_e("%s: set retain peripheral failed\n", __func__);
rc = call_res_op(core, reset_control_assert, core, "video_mvs0c_reset");
if (rc)
d_vpr_e("%s: assert video_mvs0c_reset failed\n", __func__);
usleep_range(400, 500);
rc = call_res_op(core, reset_control_deassert, core, "video_axi_reset");
if (rc)
d_vpr_e("%s: de-assert video_axi_reset failed\n", __func__);
rc = call_res_op(core, reset_control_deassert, core, "video_mvs0c_reset");
if (rc)
d_vpr_e("%s: de-assert video_mvs0c_reset failed\n", __func__);
rc = call_res_op(core, gdsc_on, core, "vcodec");
if (rc)
return rc;
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0_clk");
if (rc)
return rc;
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x1, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &noc_lpi_status);
if (rc)
return rc;
while ((!(noc_lpi_status & BIT(0))) &&
(noc_lpi_status & BIT(1) || noc_lpi_status & BIT(2))) {
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x1, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &noc_lpi_status);
if (rc)
return rc;
++count;
if (count >= 1000) {
d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
break;
}
}
if (count < 1000) {
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
}
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
rc = 0;
}
rc = call_res_op(core, gdsc_off, core, "vcodec");
if (rc) {
d_vpr_e("%s: disable regulator vcodec failed\n", __func__);
rc = 0;
}
/* remove retain mem and retain peripheral */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
if (rc)
d_vpr_e("%s: set noretain peripheral failed\n", __func__);
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_MEM);
if (rc)
d_vpr_e("%s: set noretain mem failed\n", __func__);
/* Turn off MVP MVS0C core clock */
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0c_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0c_clk failed\n", __func__);
rc = 0;
}
power_down:
/* power down process */ /* power down process */
rc = call_res_op(core, gdsc_off, core, "iris-ctl"); rc = call_res_op(core, gdsc_off, core, "iris-ctl");
if (rc) { if (rc) {
@ -1278,6 +1067,7 @@ static int __noc_error_info_iris33(struct msm_vidc_core *core)
fail_deassert_xo_reset: fail_deassert_xo_reset:
fail_assert_xo_reset: fail_assert_xo_reset:
MSM_VIDC_FATAL(true);
return rc; return rc;
} }
@ -1330,10 +1120,6 @@ static int __boot_firmware_iris33(struct msm_vidc_core *core)
if (rc) if (rc)
return rc; return rc;
rc = __read_register(core, HFI_CTRL_INIT_IRIS33, &ctrl_init_val);
if (rc)
return rc;
if ((ctrl_status & HFI_CTRL_ERROR_FATAL) || if ((ctrl_status & HFI_CTRL_ERROR_FATAL) ||
(ctrl_status & HFI_CTRL_ERROR_UC_REGION_NOT_SET) || (ctrl_status & HFI_CTRL_ERROR_UC_REGION_NOT_SET) ||
(ctrl_status & HFI_CTRL_ERROR_HW_FENCE_QUEUE)) { (ctrl_status & HFI_CTRL_ERROR_HW_FENCE_QUEUE)) {
@ -1351,8 +1137,7 @@ static int __boot_firmware_iris33(struct msm_vidc_core *core)
} }
if (count >= max_tries) { if (count >= max_tries) {
d_vpr_e(FMT_STRING_BOOT_FIRMWARE_ERROR, d_vpr_e("Error booting up vidc firmware, ctrl status %#x\n", ctrl_status);
ctrl_status, ctrl_init_val);
return -ETIME; return -ETIME;
} }

10
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_power_iris33.c
View File

@ -8,7 +8,6 @@
#include "msm_vidc_driver.h" #include "msm_vidc_driver.h"
#include "msm_vidc_inst.h" #include "msm_vidc_inst.h"
#include "msm_vidc_core.h" #include "msm_vidc_core.h"
#include "msm_vidc_platform.h"
#include "msm_vidc_debug.h" #include "msm_vidc_debug.h"
#include "perf_static_model.h" #include "perf_static_model.h"
#include "msm_vidc_power.h" #include "msm_vidc_power.h"
@ -51,7 +50,6 @@ static int msm_vidc_init_codec_input_freq(struct msm_vidc_inst *inst, u32 data_s
{ {
enum msm_vidc_port_type port; enum msm_vidc_port_type port;
u32 color_fmt, tile_rows_columns = 0; u32 color_fmt, tile_rows_columns = 0;
struct msm_vidc_core *core;
if (is_encode_session(inst)) { if (is_encode_session(inst)) {
codec_input->decoder_or_encoder = CODEC_ENCODER; codec_input->decoder_or_encoder = CODEC_ENCODER;
@ -159,9 +157,6 @@ static int msm_vidc_init_codec_input_freq(struct msm_vidc_inst *inst, u32 data_s
/* set as sanity mode, this regression mode has no effect on power calculations */ /* set as sanity mode, this regression mode has no effect on power calculations */
codec_input->regression_mode = REGRESSION_MODE_SANITY; codec_input->regression_mode = REGRESSION_MODE_SANITY;
core = inst->core;
codec_input->vpu_ver = core->platform->data.vpu_ver;
return 0; return 0;
} }
@ -170,7 +165,6 @@ static int msm_vidc_init_codec_input_bus(struct msm_vidc_inst *inst, struct vidc
{ {
u32 complexity_factor_int = 0, complexity_factor_frac = 0, tile_rows_columns = 0; u32 complexity_factor_int = 0, complexity_factor_frac = 0, tile_rows_columns = 0;
bool opb_compression_enabled = false; bool opb_compression_enabled = false;
struct msm_vidc_core *core;
if (!d) if (!d)
return -EINVAL; return -EINVAL;
@ -327,9 +321,6 @@ static int msm_vidc_init_codec_input_bus(struct msm_vidc_inst *inst, struct vidc
codec_input->av1d_commer_tile_enable = 0; codec_input->av1d_commer_tile_enable = 0;
} }
core = inst->core;
codec_input->vpu_ver = core->platform->data.vpu_ver;
/* Dump all the variables for easier debugging */ /* Dump all the variables for easier debugging */
if (msm_vidc_debug & VIDC_BUS) { if (msm_vidc_debug & VIDC_BUS) {
struct dump dump[] = { struct dump dump[] = {
@ -363,7 +354,6 @@ static int msm_vidc_init_codec_input_bus(struct msm_vidc_inst *inst, struct vidc
{"lumaonly_decode", "%d", codec_input->lumaonly_decode}, {"lumaonly_decode", "%d", codec_input->lumaonly_decode},
{"av1d_commer_tile_enable", "%d", codec_input->av1d_commer_tile_enable}, {"av1d_commer_tile_enable", "%d", codec_input->av1d_commer_tile_enable},
{"regression_mode", "%d", codec_input->regression_mode}, {"regression_mode", "%d", codec_input->regression_mode},
{"vpu_ver", "%d", codec_input->vpu_ver},
}; };
__dump(dump, ARRAY_SIZE(dump)); __dump(dump, ARRAY_SIZE(dump));
} }

4
qcom/opensource/video-driver/driver/vidc/inc/msm_vidc_debug.h
View File

@ -56,10 +56,6 @@ extern bool msm_vidc_synx_fence_enable;
"%s: faulting address: %lx\n" "%s: faulting address: %lx\n"
#define FMT_STRING_SET_CAP \ #define FMT_STRING_SET_CAP \
"set cap: name: %24s, cap value: %#10x, hfi: %#10llx\n" "set cap: name: %24s, cap value: %#10x, hfi: %#10llx\n"
#define FMT_STRING_SYSTEM_ERROR \
"%s: system error received\n"
#define FMT_STRING_BOOT_FIRMWARE_ERROR \
"Error booting up vidc firmware, ctrl status %#x, ctrl init %#x\n"
/* To enable messages OR these values and /* To enable messages OR these values and
* echo the result to debugfs file. * echo the result to debugfs file.

1
qcom/opensource/video-driver/driver/vidc/inc/msm_vidc_driver.h
View File

@ -617,7 +617,6 @@ int msm_vidc_get_frame_rate(struct msm_vidc_inst *inst);
int msm_vidc_get_operating_rate(struct msm_vidc_inst *inst); int msm_vidc_get_operating_rate(struct msm_vidc_inst *inst);
int msm_vidc_alloc_and_queue_input_internal_buffers(struct msm_vidc_inst *inst); int msm_vidc_alloc_and_queue_input_internal_buffers(struct msm_vidc_inst *inst);
int vb2_buffer_to_driver(struct vb2_buffer *vb2, struct msm_vidc_buffer *buf); int vb2_buffer_to_driver(struct vb2_buffer *vb2, struct msm_vidc_buffer *buf);
bool is_ssr_type_allowed(struct msm_vidc_core *core, u32 type);
struct msm_vidc_buffer *msm_vidc_fetch_buffer(struct msm_vidc_inst *inst, struct msm_vidc_buffer *msm_vidc_fetch_buffer(struct msm_vidc_inst *inst,
struct vb2_buffer *vb2); struct vb2_buffer *vb2);
struct context_bank_info struct context_bank_info

1
qcom/opensource/video-driver/driver/vidc/inc/msm_vidc_internal.h
View File

@ -644,7 +644,6 @@ enum msm_vidc_core_capability_type {
DEVICE_CAPS, DEVICE_CAPS,
SUPPORTS_REQUESTS, SUPPORTS_REQUESTS,
SUPPORTS_SYNX_FENCE, SUPPORTS_SYNX_FENCE,
SSR_TYPE,
CORE_CAP_MAX, CORE_CAP_MAX,
}; };

31
qcom/opensource/video-driver/driver/vidc/src/msm_vidc_driver.c
View File

@ -1060,8 +1060,7 @@ int msm_vidc_process_resume(struct msm_vidc_inst *inst)
return rc; return rc;
clear_sub_state |= MSM_VIDC_INPUT_PAUSE; clear_sub_state |= MSM_VIDC_INPUT_PAUSE;
} }
if (is_sub_state(inst, MSM_VIDC_OUTPUT_PAUSE) && if (is_sub_state(inst, MSM_VIDC_OUTPUT_PAUSE)) {
!is_encode_session(inst)) {
rc = venus_hfi_session_resume(inst, OUTPUT_PORT, rc = venus_hfi_session_resume(inst, OUTPUT_PORT,
HFI_CMD_SETTINGS_CHANGE); HFI_CMD_SETTINGS_CHANGE);
if (rc) if (rc)
@ -1078,8 +1077,7 @@ int msm_vidc_process_resume(struct msm_vidc_inst *inst)
return rc; return rc;
clear_sub_state |= MSM_VIDC_INPUT_PAUSE; clear_sub_state |= MSM_VIDC_INPUT_PAUSE;
} }
if (is_sub_state(inst, MSM_VIDC_OUTPUT_PAUSE) && if (is_sub_state(inst, MSM_VIDC_OUTPUT_PAUSE)) {
!is_encode_session(inst)) {
rc = venus_hfi_session_resume(inst, OUTPUT_PORT, HFI_CMD_DRAIN); rc = venus_hfi_session_resume(inst, OUTPUT_PORT, HFI_CMD_DRAIN);
if (rc) if (rc)
return rc; return rc;
@ -1647,11 +1645,6 @@ int msm_vidc_set_auto_framerate(struct msm_vidc_inst *inst, u64 timestamp)
if (counter < ENC_FPS_WINDOW) if (counter < ENC_FPS_WINDOW)
goto exit; goto exit;
if (curr_fr > inst->capabilities[FRAME_RATE].value) {
i_vpr_l(inst, "%s: fps: %u limitted to client fps.\n", __func__, curr_fr >> 16);
curr_fr = inst->capabilities[FRAME_RATE].value;
}
/* if framerate changed and stable for 2 frames, set to firmware */ /* if framerate changed and stable for 2 frames, set to firmware */
if (curr_fr == prev_fr && curr_fr != inst->auto_framerate) { if (curr_fr == prev_fr && curr_fr != inst->auto_framerate) {
i_vpr_l(inst, "%s: updated fps: %u -> %u\n", __func__, i_vpr_l(inst, "%s: updated fps: %u -> %u\n", __func__,
@ -4066,19 +4059,6 @@ int msm_vidc_smmu_fault_handler(struct iommu_domain *domain,
return -ENOSYS; return -ENOSYS;
} }
bool is_ssr_type_allowed(struct msm_vidc_core *core, u32 type)
{
u32 i;
const u32 *ssr_type = core->platform->data.msm_vidc_ssr_type;
u32 ssr_type_size = core->platform->data.msm_vidc_ssr_type_size;
for (i = 0; i < ssr_type_size; i++) {
if (type == ssr_type[i])
return true;
}
return false;
}
int msm_vidc_trigger_ssr(struct msm_vidc_core *core, int msm_vidc_trigger_ssr(struct msm_vidc_core *core,
u64 trigger_ssr_val) u64 trigger_ssr_val)
{ {
@ -4094,15 +4074,8 @@ int msm_vidc_trigger_ssr(struct msm_vidc_core *core,
*/ */
d_vpr_e("%s: trigger ssr is called. trigger ssr val: %#llx\n", d_vpr_e("%s: trigger ssr is called. trigger ssr val: %#llx\n",
__func__, trigger_ssr_val); __func__, trigger_ssr_val);
ssr->ssr_type = (trigger_ssr_val & ssr->ssr_type = (trigger_ssr_val &
(unsigned long)SSR_TYPE) >> SSR_TYPE_SHIFT; (unsigned long)SSR_TYPE) >> SSR_TYPE_SHIFT;
if (!is_ssr_type_allowed(core, ssr->ssr_type)) {
d_vpr_h("SSR Type %#llx is not allowed\n", ssr->ssr_type);
return 0;
}
ssr->sub_client_id = (trigger_ssr_val & ssr->sub_client_id = (trigger_ssr_val &
(unsigned long)SSR_SUB_CLIENT_ID) >> SSR_SUB_CLIENT_ID_SHIFT; (unsigned long)SSR_SUB_CLIENT_ID) >> SSR_SUB_CLIENT_ID_SHIFT;
ssr->test_addr = (trigger_ssr_val & ssr->test_addr = (trigger_ssr_val &

4
qcom/opensource/video-driver/driver/vidc/src/msm_vidc_probe.c
View File

@ -45,8 +45,7 @@ static inline bool is_video_device(struct device *dev)
of_device_is_compatible(dev->of_node, "qcom,sm8550-vidc-v2") || of_device_is_compatible(dev->of_node, "qcom,sm8550-vidc-v2") ||
of_device_is_compatible(dev->of_node, "qcom,sm8650-vidc") || of_device_is_compatible(dev->of_node, "qcom,sm8650-vidc") ||
of_device_is_compatible(dev->of_node, "qcom,sm8650-vidc-v2") || of_device_is_compatible(dev->of_node, "qcom,sm8650-vidc-v2") ||
of_device_is_compatible(dev->of_node, "qcom,cliffs-vidc") || of_device_is_compatible(dev->of_node, "qcom,cliffs-vidc"));
of_device_is_compatible(dev->of_node, "qcom,volcano-vidc"));
} }
static inline bool is_video_context_bank_device_node(struct device_node *of_node) static inline bool is_video_context_bank_device_node(struct device_node *of_node)
@ -124,7 +123,6 @@ static const struct of_device_id msm_vidc_dt_match[] = {
{.compatible = "qcom,sm8650-vidc"}, {.compatible = "qcom,sm8650-vidc"},
{.compatible = "qcom,sm8650-vidc-v2"}, {.compatible = "qcom,sm8650-vidc-v2"},
{.compatible = "qcom,cliffs-vidc"}, {.compatible = "qcom,cliffs-vidc"},
{.compatible = "qcom,volcano-vidc"},
{.compatible = "qcom,vidc,cb-ns-pxl"}, {.compatible = "qcom,vidc,cb-ns-pxl"},
{.compatible = "qcom,vidc,cb-ns"}, {.compatible = "qcom,vidc,cb-ns"},
{.compatible = "qcom,vidc,cb-sec-non-pxl"}, {.compatible = "qcom,vidc,cb-sec-non-pxl"},

30
qcom/opensource/video-driver/driver/vidc/src/resources.c
View File

@ -1464,13 +1464,15 @@ static int __reset_control_acquire_name(struct msm_vidc_core *core,
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0))
do { do {
rc = reset_control_acquire(rcinfo->rst); rc = reset_control_acquire(rcinfo->rst);
if (!rc) if (!rc) {
break; break;
} else {
d_vpr_e("%s: failed to acquire video_xo_reset control, count %d\n", d_vpr_e(
__func__, count); "%s: failed to acquire video_xo_reset control, count %d\n",
count++; __func__, count);
usleep_range(1000, 1500); count++;
usleep_range(1000, 1000);
}
} while (count < 1000); } while (count < 1000);
if (count >= 1000) { if (count >= 1000) {
@ -1489,13 +1491,9 @@ static int __reset_control_acquire_name(struct msm_vidc_core *core,
__func__, rcinfo->name); __func__, rcinfo->name);
break; break;
} }
/* Faced this issue for volcano which doesn't support xo_reset
* skip this check and return success
*/
if (!found) { if (!found) {
d_vpr_h("%s: reset control (%s) not found but returning success\n", d_vpr_e("%s: reset control (%s) not found\n", __func__, name);
__func__, name); rc = -EINVAL;
rc = 0;
} }
return rc; return rc;
@ -1534,13 +1532,9 @@ static int __reset_control_release_name(struct msm_vidc_core *core,
__func__, rcinfo->name); __func__, rcinfo->name);
break; break;
} }
/* Faced this issue for volcano which doesn't support xo_reset
* skip this check and return success
*/
if (!found) { if (!found) {
d_vpr_h("%s: reset control (%s) not found but returning success\n", d_vpr_e("%s: reset control (%s) not found\n", __func__, name);
__func__, name); rc = -EINVAL;
rc = 0;
} }
return rc; return rc;

6
qcom/opensource/video-driver/driver/vidc/src/venus_hfi.c
View File

@ -928,6 +928,12 @@ int venus_hfi_trigger_ssr(struct msm_vidc_core *core, u32 type,
int rc = 0; int rc = 0;
u32 payload[2]; u32 payload[2];
// WA for CR: 3584248
if (type != HFI_SSR_TYPE_SW_ERR_FATAL) {
d_vpr_h("SSR Type 0x1 is only allowed for pineapple\n");
return rc;
}
/* /*
* call resume before preparing ssr hfi packet in core->packet * call resume before preparing ssr hfi packet in core->packet
* otherwise ssr hfi packet in core->packet will be overwritten * otherwise ssr hfi packet in core->packet will be overwritten

7
qcom/opensource/video-driver/driver/vidc/src/venus_hfi_response.c
View File

@ -387,7 +387,7 @@ int handle_system_error(struct msm_vidc_core *core,
{ {
bool bug_on = false; bool bug_on = false;
d_vpr_e(FMT_STRING_SYSTEM_ERROR, __func__); d_vpr_e("%s: system error received\n", __func__);
print_sfr_message(core); print_sfr_message(core);
if (pkt) { if (pkt) {
@ -406,10 +406,7 @@ int handle_system_error(struct msm_vidc_core *core,
} }
} }
core_lock(core, __func__); msm_vidc_core_deinit(core, true);
msm_vidc_change_core_state(core, MSM_VIDC_CORE_ERROR, __func__);
msm_vidc_core_deinit_locked(core, true);
core_unlock(core, __func__);
return 0; return 0;
} }

15
qcom/opensource/video-driver/msm_video/Kbuild
View File

@ -9,11 +9,6 @@ include $(VIDEO_ROOT)/config/pineapple_video.conf
LINUXINCLUDE += -include $(VIDEO_ROOT)/config/pineapple_video.h LINUXINCLUDE += -include $(VIDEO_ROOT)/config/pineapple_video.h
endif endif
ifeq ($(CONFIG_ARCH_VOLCANO), y)
include $(VIDEO_ROOT)/config/volcano_video.conf
LINUXINCLUDE += -include $(VIDEO_ROOT)/config/volcano_video.h
endif
ifeq ($(CONFIG_ARCH_KALAMA), y) ifeq ($(CONFIG_ARCH_KALAMA), y)
include $(VIDEO_ROOT)/config/kalama_video.conf include $(VIDEO_ROOT)/config/kalama_video.conf
LINUXINCLUDE += -include $(VIDEO_ROOT)/config/kalama_video.h LINUXINCLUDE += -include $(VIDEO_ROOT)/config/kalama_video.h
@ -28,10 +23,6 @@ ifeq ($(CONFIG_MSM_VIDC_KALAMA), y)
LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/kalama/inc \ LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/kalama/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/variant/iris3/inc -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris3/inc
endif endif
ifeq ($(CONFIG_MSM_VIDC_VOLCANO), y)
LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/volcano/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/variant/iris2/inc
endif
LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/common/inc \ LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/common/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/variant/common/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/common/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/vidc/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/vidc/inc \
@ -62,12 +53,6 @@ msm_video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/kalama/src/msm_vidc_kalama.o
$(VIDEO_DRIVER_REL_PATH)/variant/iris3/src/msm_vidc_clock_iris3.o \ $(VIDEO_DRIVER_REL_PATH)/variant/iris3/src/msm_vidc_clock_iris3.o \
$(VIDEO_DRIVER_REL_PATH)/variant/iris3/src/msm_vidc_iris3.o $(VIDEO_DRIVER_REL_PATH)/variant/iris3/src/msm_vidc_iris3.o
endif endif
ifeq ($(CONFIG_MSM_VIDC_VOLCANO), y)
msm_video-objs += $(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_buffer_iris2.o \
$(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_iris2.o \
$(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_power_iris2.o \
$(VIDEO_DRIVER_REL_PATH)/platform/volcano/src/msm_vidc_volcano.o
endif
msm_video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform.o \ msm_video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform.o \
$(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform_ext.o \ $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform_ext.o \
$(VIDEO_DRIVER_REL_PATH)/variant/common/src/msm_vidc_variant.o \ $(VIDEO_DRIVER_REL_PATH)/variant/common/src/msm_vidc_variant.o \

13
qcom/opensource/video-driver/video/Kbuild
View File

@ -10,15 +10,10 @@ endif
ifeq ($(CONFIG_MSM_VIDC_PINEAPPLE), y) ifeq ($(CONFIG_MSM_VIDC_PINEAPPLE), y)
LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/pineapple/inc \ LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/pineapple/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/platform/cliffs/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/platform/cliffs/inc
-I$(VIDEO_DRIVER_ABS_PATH)/variant/iris33/inc -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris33/inc
endif endif
ifeq ($(CONFIG_MSM_VIDC_VOLCANO), y)
LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/volcano/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/variant/iris2/inc
endif
LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/common/inc \ LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/common/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/variant/common/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/common/inc \
-I$(VIDEO_DRIVER_ABS_PATH)/vidc/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/vidc/inc \
@ -38,12 +33,6 @@ video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/pineapple/src/pineapple.o \
$(VIDEO_DRIVER_REL_PATH)/variant/iris33/src/msm_vidc_clock_iris33.o \ $(VIDEO_DRIVER_REL_PATH)/variant/iris33/src/msm_vidc_clock_iris33.o \
$(VIDEO_DRIVER_REL_PATH)/variant/iris33/src/msm_vidc_iris33.o $(VIDEO_DRIVER_REL_PATH)/variant/iris33/src/msm_vidc_iris33.o
endif endif
ifeq ($(CONFIG_MSM_VIDC_VOLCANO), y)
video-objs += $(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_buffer_iris2.o \
$(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_iris2.o \
$(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_power_iris2.o \
$(VIDEO_DRIVER_REL_PATH)/platform/volcano/src/volcano.o
endif
video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform.o \ video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform.o \
$(VIDEO_DRIVER_REL_PATH)/variant/common/src/msm_vidc_variant.o \ $(VIDEO_DRIVER_REL_PATH)/variant/common/src/msm_vidc_variant.o \
$(VIDEO_DRIVER_REL_PATH)/vidc/src/msm_vidc_v4l2.o \ $(VIDEO_DRIVER_REL_PATH)/vidc/src/msm_vidc_v4l2.o \