21809 lines
642 KiB
Plaintext
21809 lines
642 KiB
Plaintext
/dts-v1/;
|
|
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. Pineapple v2 SoC";
|
|
compatible = "qcom,pineapple";
|
|
qcom,msm-id = <0x22d 0x20000>;
|
|
interrupt-parent = <0x01>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
qcom,board-id = <0x00 0x00>;
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "loglevel=6 kpti=0 log_buf_len=256K swiotlb=noforce kernel.panic_on_rcu_stall=1 fw_devlink.strict=1 service_locator.enable=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-1 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc cgroup.memory=nokmem,nosocket printk.console_no_auto_verbose=1 kasan=off service_locator.enable=1 loop.max_part=7 no-steal-acc can.stats_timer=0 ufs_qcom.crash_on_ber=n ftrace_dump_on_oops firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware_mnt/image/kiwi,/vendor/vm-system/oemvm/boot,/vendor/vm-system/trustedvm/boot,/vendor/firmware,/vendor/firmware/wlan/qca_cld/kiwi_v2 pcie_ports=compat disable_dma32=on pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x2 transparent_hugepage=never";
|
|
stdout-path = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000:115200n8";
|
|
phandle = <0x2eb>;
|
|
};
|
|
|
|
aliases {
|
|
swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000/wsa2_swr_master";
|
|
swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@6D44000/va_swr_master";
|
|
swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
|
|
swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
|
|
serial0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000";
|
|
hsuart0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000";
|
|
mmc1 = "/soc/sdhci@8804000";
|
|
ufshc1 = "/soc/ufshc@1d84000";
|
|
phandle = <0x2ec>;
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
phandle = <0x2ed>;
|
|
|
|
gunyah_hyp_region@80000000 {
|
|
no-map;
|
|
reg = <0x00 0x80000000 0x00 0xe00000>;
|
|
phandle = <0x2ee>;
|
|
};
|
|
|
|
cpusys_vm_region@80e00000 {
|
|
no-map;
|
|
reg = <0x00 0x80e00000 0x00 0x400000>;
|
|
phandle = <0xcb>;
|
|
};
|
|
|
|
xbl_aop_merged_region@81a00000 {
|
|
no-map;
|
|
reg = <0x00 0x81a00000 0x00 0x260000>;
|
|
phandle = <0x2ef>;
|
|
};
|
|
|
|
aop_cmd_db_region@81c60000 {
|
|
compatible = "qcom,cmd-db";
|
|
no-map;
|
|
reg = <0x00 0x81c60000 0x00 0x20000>;
|
|
phandle = <0x2f0>;
|
|
};
|
|
|
|
aop_tme_uefi_merged_region@81c80000 {
|
|
no-map;
|
|
reg = <0x00 0x81c80000 0x00 0x74000>;
|
|
phandle = <0x2f1>;
|
|
};
|
|
|
|
chipinfo_region@81cf4000 {
|
|
no-map;
|
|
reg = <0x00 0x81cf4000 0x00 0x1000>;
|
|
phandle = <0x2f2>;
|
|
};
|
|
|
|
smem_region@81d00000 {
|
|
compatible = "qcom,smem";
|
|
reg = <0x00 0x81d00000 0x00 0x200000>;
|
|
hwlocks = <0x02 0x03>;
|
|
no-map;
|
|
phandle = <0x2f3>;
|
|
};
|
|
|
|
adsp_mhi_region@81f00000 {
|
|
no-map;
|
|
reg = <0x00 0x81f00000 0x00 0x20000>;
|
|
phandle = <0x2f4>;
|
|
};
|
|
|
|
pvmfw_region@0x824a0000 {
|
|
no-map;
|
|
reg = <0x00 0x824a0000 0x00 0x100000>;
|
|
phandle = <0x2f5>;
|
|
};
|
|
|
|
global_sync_region@82600000 {
|
|
no-map;
|
|
reg = <0x00 0x82600000 0x00 0x100000>;
|
|
phandle = <0xbd>;
|
|
};
|
|
|
|
tz_stat_region@82700000 {
|
|
no-map;
|
|
reg = <0x00 0x82700000 0x00 0x100000>;
|
|
phandle = <0x2f6>;
|
|
};
|
|
|
|
qdss_region@82800000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0x82800000 0x00 0x2000000>;
|
|
reusable;
|
|
phandle = <0x2bb>;
|
|
};
|
|
|
|
qlink_logging_region@84800000 {
|
|
no-map;
|
|
reg = <0x00 0x84800000 0x00 0x200000>;
|
|
phandle = <0xb7>;
|
|
};
|
|
|
|
mpss_dsm_region@86b00000 {
|
|
no-map;
|
|
reg = <0x00 0x86b00000 0x00 0x4900000>;
|
|
phandle = <0xb5>;
|
|
};
|
|
|
|
mpss_dsm_region_2@8b400000 {
|
|
no-map;
|
|
reg = <0x00 0x8b400000 0x00 0x800000>;
|
|
phandle = <0xb6>;
|
|
};
|
|
|
|
mpss_region@8bc00000 {
|
|
no-map;
|
|
reg = <0x00 0x8bc00000 0x00 0xf400000>;
|
|
phandle = <0xb2>;
|
|
};
|
|
|
|
q6_mpss_dtb_region@9b000000 {
|
|
no-map;
|
|
reg = <0x00 0x9b000000 0x00 0x80000>;
|
|
phandle = <0xb3>;
|
|
};
|
|
|
|
ipa_fw_region@9b080000 {
|
|
no-map;
|
|
reg = <0x00 0x9b080000 0x00 0x10000>;
|
|
phandle = <0x2f7>;
|
|
};
|
|
|
|
ipa_gsi_region@9b090000 {
|
|
no-map;
|
|
reg = <0x00 0x9b090000 0x00 0xa000>;
|
|
phandle = <0x2f8>;
|
|
};
|
|
|
|
qseecom_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x1400000>;
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
qseecom_ta_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x1000000>;
|
|
phandle = <0xa5>;
|
|
};
|
|
|
|
qmc_dma_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x1000000>;
|
|
phandle = <0x41>;
|
|
};
|
|
|
|
non_secure_display_region {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
size = <0x00 0xa400000>;
|
|
alignment = <0x00 0x400000>;
|
|
phandle = <0xf7>;
|
|
};
|
|
|
|
gpu_microcode_region@9b09a000 {
|
|
no-map;
|
|
reg = <0x00 0x9b09a000 0x00 0x2000>;
|
|
phandle = <0x2f9>;
|
|
};
|
|
|
|
lost_reg_mem {
|
|
no-map;
|
|
reg = <0x00 0x9b09c000 0x00 0x4000>;
|
|
};
|
|
|
|
spss_region_region@9b0a0000 {
|
|
no-map;
|
|
reg = <0x00 0x9b0a0000 0x00 0x1e0000>;
|
|
phandle = <0x3b>;
|
|
};
|
|
|
|
spu_secure_shared_memory_region@9b280000 {
|
|
no-map;
|
|
reg = <0x00 0x9b280000 0x00 0x60000>;
|
|
phandle = <0xfb>;
|
|
};
|
|
|
|
spu_secure_shared_memory_region@9b2e0000 {
|
|
no-map;
|
|
reg = <0x00 0x9b2e0000 0x00 0x20000>;
|
|
phandle = <0xf9>;
|
|
};
|
|
|
|
camera_region@9b300000 {
|
|
no-map;
|
|
reg = <0x00 0x9b300000 0x00 0x800000>;
|
|
phandle = <0x2fa>;
|
|
};
|
|
|
|
video_region@9bb00000 {
|
|
no-map;
|
|
reg = <0x00 0x9bb00000 0x00 0x800000>;
|
|
phandle = <0x2fb>;
|
|
};
|
|
|
|
cvp_region@9c300000 {
|
|
no-map;
|
|
reg = <0x00 0x9c300000 0x00 0x700000>;
|
|
phandle = <0x2fc>;
|
|
};
|
|
|
|
cdsp_region@9ca00000 {
|
|
no-map;
|
|
reg = <0x00 0x9ca00000 0x00 0x1400000>;
|
|
phandle = <0xbb>;
|
|
};
|
|
|
|
q6_cdsp_dtb_region@9de00000 {
|
|
no-map;
|
|
reg = <0x00 0x9de00000 0x00 0x80000>;
|
|
phandle = <0xbc>;
|
|
};
|
|
|
|
q6_adsp_dtb_region@9de80000 {
|
|
no-map;
|
|
reg = <0x00 0x9de80000 0x00 0x80000>;
|
|
phandle = <0xae>;
|
|
};
|
|
|
|
adspslpi_region@9df00000 {
|
|
no-map;
|
|
reg = <0x00 0x9df00000 0x00 0x4080000>;
|
|
phandle = <0xad>;
|
|
};
|
|
|
|
tz_merged_region@d8000000 {
|
|
no-map;
|
|
reg = <0x00 0xd8000000 0x00 0x800000>;
|
|
phandle = <0x2fd>;
|
|
};
|
|
|
|
hwfence-shmem {
|
|
no-map;
|
|
reg = <0x00 0xd4e23000 0x00 0x2dd000>;
|
|
phandle = <0xc2>;
|
|
};
|
|
|
|
vm_comm_mem_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x400000>;
|
|
phandle = <0xc8>;
|
|
};
|
|
|
|
trust_ui_vm_dump@0xf37ff000 {
|
|
no-map;
|
|
reg = <0x00 0xf37ff000 0x00 0x1000>;
|
|
phandle = <0xdf>;
|
|
};
|
|
|
|
trust_ui_vm_region@f3800000 {
|
|
reg = <0x00 0xf3800000 0x00 0x4400000>;
|
|
no-map;
|
|
phandle = <0xc7>;
|
|
};
|
|
|
|
llcc_lpi_region@ff800000 {
|
|
no-map;
|
|
reg = <0x00 0xff800000 0x00 0x600000>;
|
|
phandle = <0x2fe>;
|
|
};
|
|
|
|
va_md_mem_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
size = <0x00 0x1000000>;
|
|
phandle = <0x2f>;
|
|
};
|
|
|
|
sp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x1000000>;
|
|
phandle = <0xf8>;
|
|
};
|
|
|
|
cdsp_eva_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0xc00000>;
|
|
phandle = <0x2ff>;
|
|
};
|
|
|
|
adsp_heap_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0xc00000>;
|
|
phandle = <0xcd>;
|
|
};
|
|
|
|
linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x2000000>;
|
|
linux,cma-default;
|
|
phandle = <0xb4>;
|
|
};
|
|
|
|
secure_cdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x4800000>;
|
|
phandle = <0xfa>;
|
|
};
|
|
|
|
debug_kinfo_region {
|
|
alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>;
|
|
size = <0x00 0x1000>;
|
|
no-map;
|
|
phandle = <0xde>;
|
|
};
|
|
|
|
ramoops_region {
|
|
compatible = "ramoops";
|
|
alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>;
|
|
size = <0x00 0x200000>;
|
|
pmsg-size = <0x200000>;
|
|
mem-type = <0x02>;
|
|
phandle = <0x300>;
|
|
};
|
|
|
|
mem_dump_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x01 0x00 0xfffffffe 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x1800000>;
|
|
phandle = <0xf6>;
|
|
};
|
|
};
|
|
|
|
firmware {
|
|
phandle = <0x301>;
|
|
|
|
qcom_scm {
|
|
compatible = "qcom,scm";
|
|
qcom,dload-mode = <0x03 0x19000>;
|
|
};
|
|
|
|
qcom_smcinvoke {
|
|
compatible = "qcom,smcinvoke";
|
|
};
|
|
|
|
qtee_shmbridge {
|
|
compatible = "qcom,tee-shared-memory-bridge";
|
|
};
|
|
|
|
android {
|
|
compatible = "android,firmware";
|
|
|
|
vbmeta {
|
|
compatible = "android,vbmeta";
|
|
parts = "vbmeta,boot,system,vendor,dtbo,recovery";
|
|
};
|
|
|
|
fstab {
|
|
compatible = "android,fstab";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x00>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x04>;
|
|
power-domains = <0x05>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <0x06 0x00>;
|
|
#cooling-cells = <0x02>;
|
|
capacity-dmips-mhz = <0x400>;
|
|
dynamic-power-coefficient = <0x64>;
|
|
next-level-cache = <0x07>;
|
|
phandle = <0x19>;
|
|
|
|
l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x02>;
|
|
next-level-cache = <0x08>;
|
|
phandle = <0x07>;
|
|
|
|
l3-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x03>;
|
|
phandle = <0x08>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x100>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x04>;
|
|
power-domains = <0x09>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <0x06 0x00>;
|
|
#cooling-cells = <0x02>;
|
|
capacity-dmips-mhz = <0x400>;
|
|
dynamic-power-coefficient = <0x64>;
|
|
next-level-cache = <0x07>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
cpu@200 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x200>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x0a>;
|
|
power-domains = <0x0b>;
|
|
power-domain-names = "psci";
|
|
next-level-cache = <0x0c>;
|
|
#cooling-cells = <0x02>;
|
|
qcom,freq-domain = <0x06 0x03>;
|
|
capacity-dmips-mhz = <0x700>;
|
|
dynamic-power-coefficient = <0xee>;
|
|
phandle = <0x1b>;
|
|
|
|
l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x02>;
|
|
next-level-cache = <0x08>;
|
|
phandle = <0x0c>;
|
|
};
|
|
};
|
|
|
|
cpu@300 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x300>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x0a>;
|
|
power-domains = <0x0d>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <0x06 0x03>;
|
|
#cooling-cells = <0x02>;
|
|
capacity-dmips-mhz = <0x700>;
|
|
dynamic-power-coefficient = <0xee>;
|
|
next-level-cache = <0x0e>;
|
|
phandle = <0x1c>;
|
|
|
|
l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x02>;
|
|
next-level-cache = <0x08>;
|
|
phandle = <0x0e>;
|
|
};
|
|
};
|
|
|
|
cpu@400 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x400>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x0a>;
|
|
power-domains = <0x0f>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <0x06 0x03>;
|
|
#cooling-cells = <0x02>;
|
|
capacity-dmips-mhz = <0x700>;
|
|
dynamic-power-coefficient = <0xee>;
|
|
next-level-cache = <0x10>;
|
|
phandle = <0x1d>;
|
|
|
|
l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x02>;
|
|
next-level-cache = <0x08>;
|
|
phandle = <0x10>;
|
|
};
|
|
};
|
|
|
|
cpu@500 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x500>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x11>;
|
|
power-domains = <0x12>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <0x06 0x01>;
|
|
#cooling-cells = <0x02>;
|
|
capacity-dmips-mhz = <0x700>;
|
|
dynamic-power-coefficient = <0xee>;
|
|
next-level-cache = <0x13>;
|
|
phandle = <0x1e>;
|
|
|
|
l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x02>;
|
|
next-level-cache = <0x08>;
|
|
phandle = <0x13>;
|
|
};
|
|
};
|
|
|
|
cpu@600 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x600>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x11>;
|
|
power-domains = <0x14>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <0x06 0x01>;
|
|
#cooling-cells = <0x02>;
|
|
capacity-dmips-mhz = <0x700>;
|
|
dynamic-power-coefficient = <0xee>;
|
|
next-level-cache = <0x15>;
|
|
phandle = <0x1f>;
|
|
|
|
l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x02>;
|
|
next-level-cache = <0x08>;
|
|
phandle = <0x15>;
|
|
};
|
|
};
|
|
|
|
cpu@700 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x00 0x700>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x16>;
|
|
power-domains = <0x17>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <0x06 0x02>;
|
|
#cooling-cells = <0x02>;
|
|
capacity-dmips-mhz = <0x766>;
|
|
dynamic-power-coefficient = <0x24c>;
|
|
next-level-cache = <0x18>;
|
|
phandle = <0x20>;
|
|
|
|
l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <0x02>;
|
|
next-level-cache = <0x08>;
|
|
phandle = <0x18>;
|
|
};
|
|
};
|
|
|
|
cpu-map {
|
|
|
|
cluster0 {
|
|
|
|
core0 {
|
|
cpu = <0x19>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x1a>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
|
|
core0 {
|
|
cpu = <0x1b>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x1c>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0x1d>;
|
|
};
|
|
};
|
|
|
|
cluster2 {
|
|
|
|
core0 {
|
|
cpu = <0x1e>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x1f>;
|
|
};
|
|
};
|
|
|
|
cluster3 {
|
|
|
|
core0 {
|
|
cpu = <0x20>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "psci";
|
|
|
|
silver-cluster0-c4 {
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "rail-pc";
|
|
entry-latency-us = <0x226>;
|
|
exit-latency-us = <0x2ee>;
|
|
min-residency-us = <0x1a2c>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
phandle = <0x04>;
|
|
};
|
|
|
|
gold-cluster1-c4 {
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "rail-pc";
|
|
entry-latency-us = <0x226>;
|
|
exit-latency-us = <0x41a>;
|
|
min-residency-us = <0x1f0f>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
phandle = <0x0a>;
|
|
};
|
|
|
|
gold-cluster2-c4 {
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "rail-pc";
|
|
entry-latency-us = <0x226>;
|
|
exit-latency-us = <0x41a>;
|
|
min-residency-us = <0x1f0f>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
phandle = <0x11>;
|
|
};
|
|
|
|
gold-plus-cluster3-c4 {
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "rail-pc";
|
|
entry-latency-us = <0x1f4>;
|
|
exit-latency-us = <0x546>;
|
|
min-residency-us = <0x1d38>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
phandle = <0x16>;
|
|
};
|
|
|
|
cluster-d4 {
|
|
compatible = "domain-idle-state";
|
|
idle-state-name = "l3-off";
|
|
entry-latency-us = <0x2ee>;
|
|
exit-latency-us = <0x92e>;
|
|
min-residency-us = <0x23b8>;
|
|
arm,psci-suspend-param = <0x41000044>;
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
cluster-e3 {
|
|
compatible = "domain-idle-state";
|
|
idle-state-name = "llcc-off";
|
|
entry-latency-us = <0xaf0>;
|
|
exit-latency-us = <0x1130>;
|
|
min-residency-us = <0x27a6>;
|
|
arm,psci-suspend-param = <0x4100c344>;
|
|
phandle = <0x23>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
interrupt-parent = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
phandle = <0x302>;
|
|
|
|
disp_rdump_region@d5100000 {
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
|
|
cpu-pd0 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x05>;
|
|
};
|
|
|
|
cpu-pd1 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x09>;
|
|
};
|
|
|
|
cpu-pd2 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x0b>;
|
|
};
|
|
|
|
cpu-pd3 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x0d>;
|
|
};
|
|
|
|
cpu-pd4 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x0f>;
|
|
};
|
|
|
|
cpu-pd5 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x12>;
|
|
};
|
|
|
|
cpu-pd6 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x14>;
|
|
};
|
|
|
|
cpu-pd7 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x17>;
|
|
};
|
|
|
|
cluster-pd {
|
|
#power-domain-cells = <0x00>;
|
|
domain-idle-states = <0x22 0x23>;
|
|
phandle = <0x21>;
|
|
};
|
|
};
|
|
|
|
bamdma@6C04000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
qcom,controlled-remotely;
|
|
reg = <0x6c04000 0x20000 0x6c8f000 0x1000>;
|
|
reg-names = "bam", "bam_remote_mem";
|
|
num-channels = <0x1f>;
|
|
interrupts = <0x00 0xa4 0x04>;
|
|
#dma-cells = <0x01>;
|
|
qcom,ee = <0x01>;
|
|
qcom,num-ees = <0x02>;
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
slim@6C40000 {
|
|
compatible = "qcom,slim-ngd-v1.5.0";
|
|
reg = <0x6c40000 0x2c000 0x6c8e000 0x1000>;
|
|
reg-names = "ctrl", "slimbus_remote_mem";
|
|
interrupts = <0x00 0xa3 0x04>;
|
|
qcom,apps-ch-pipes = <0x00>;
|
|
qcom,ea-pc = <0x490>;
|
|
dmas = <0x24 0x03 0x24 0x04>;
|
|
dma-names = "rx", "tx";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x303>;
|
|
};
|
|
|
|
interrupt-controller@17100000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-controller;
|
|
ranges;
|
|
#redistributor-regions = <0x01>;
|
|
redistributor-stride = <0x00 0x40000>;
|
|
reg = <0x17100000 0x10000 0x17180000 0x200000>;
|
|
interrupts = <0x01 0x09 0x04>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
phandle = <0x01>;
|
|
|
|
msi-controller@17140000 {
|
|
compatible = "arm,gic-v3-its";
|
|
msi-controller;
|
|
#msi-cells = <0x01>;
|
|
reg = <0x17140000 0x20000>;
|
|
phandle = <0x58>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>;
|
|
clock-frequency = <0x124f800>;
|
|
phandle = <0x304>;
|
|
};
|
|
|
|
timer@17420000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17420000 0x1000>;
|
|
clock-frequency = <0x124f800>;
|
|
phandle = <0x305>;
|
|
|
|
frame@17421000 {
|
|
frame-number = <0x00>;
|
|
interrupts = <0x00 0x08 0x04 0x00 0x06 0x04>;
|
|
reg = <0x17421000 0x1000 0x17422000 0x1000>;
|
|
};
|
|
|
|
frame@17423000 {
|
|
frame-number = <0x01>;
|
|
interrupts = <0x00 0x09 0x04>;
|
|
reg = <0x17423000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17425000 {
|
|
frame-number = <0x02>;
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
reg = <0x17425000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17427000 {
|
|
frame-number = <0x03>;
|
|
interrupts = <0x00 0x0b 0x04>;
|
|
reg = <0x17427000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17429000 {
|
|
frame-number = <0x04>;
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
reg = <0x17429000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742b000 {
|
|
frame-number = <0x05>;
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
reg = <0x1742b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742d000 {
|
|
frame-number = <0x06>;
|
|
interrupts = <0x00 0x0e 0x04>;
|
|
reg = <0x1742d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <0x01 0x07 0x04>;
|
|
phandle = <0x306>;
|
|
};
|
|
|
|
bcm_voter@0 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "pcie_crm";
|
|
qcom,crm-client-idx = <0x00>;
|
|
qcom,crm-pwr-states = <0x05>;
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
bcm_voter@1 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "pcie_crm";
|
|
qcom,crm-client-idx = <0x01>;
|
|
qcom,crm-pwr-states = <0x05>;
|
|
phandle = <0x27>;
|
|
};
|
|
|
|
interconnect@0 {
|
|
compatible = "qcom,pineapple-clk_virt";
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1";
|
|
qcom,bcm-voters = <0x25 0x26 0x27>;
|
|
phandle = <0xfc>;
|
|
};
|
|
|
|
interconnect@1 {
|
|
compatible = "qcom,pineapple-mc_virt";
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1";
|
|
qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>;
|
|
phandle = <0x3e>;
|
|
};
|
|
|
|
interconnect@1600000 {
|
|
compatible = "qcom,pineapple-cnoc_cfg";
|
|
reg = <0x1600000 0x6200>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0x51>;
|
|
};
|
|
|
|
interconnect@1500000 {
|
|
compatible = "qcom,pineapple-cnoc_main";
|
|
reg = <0x1500000 0x14080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0x307>;
|
|
};
|
|
|
|
interconnect@1680000 {
|
|
compatible = "qcom,pineapple-system_noc";
|
|
reg = <0x1680000 0x1d080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0xf3>;
|
|
};
|
|
|
|
interconnect@16c0000 {
|
|
compatible = "qcom,pineapple-pcie_anoc";
|
|
reg = <0x16c0000 0x12200>;
|
|
#interconnect-cells = <0x01>;
|
|
clocks = <0x2c 0x00 0x2c 0x09>;
|
|
qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1";
|
|
qcom,bcm-voters = <0x25 0x26 0x27>;
|
|
phandle = <0xf4>;
|
|
};
|
|
|
|
interconnect@16e0000 {
|
|
compatible = "qcom,pineapple-aggre1_noc";
|
|
reg = <0x16e0000 0x16400>;
|
|
#interconnect-cells = <0x01>;
|
|
clocks = <0x2c 0x01 0x2c 0x03>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0x56>;
|
|
};
|
|
|
|
interconnect@1700000 {
|
|
compatible = "qcom,pineapple-aggre2_noc";
|
|
reg = <0x1700000 0x1e400>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
clocks = <0x2d 0x0c>;
|
|
phandle = <0x3d>;
|
|
};
|
|
|
|
interconnect@1780000 {
|
|
compatible = "qcom,pineapple-mmss_noc";
|
|
reg = <0x1780000 0x5b800>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2";
|
|
qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b>;
|
|
phandle = <0xe2>;
|
|
};
|
|
|
|
interconnect@24100000 {
|
|
compatible = "qcom,pineapple-gem_noc";
|
|
reg = <0x24100000 0xc5080>;
|
|
#interconnect-cells = <0x01>;
|
|
clocks = <0x2c 0x0d>;
|
|
clock-names = "gcc_ddrss_ubwcp_clk";
|
|
qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1";
|
|
qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>;
|
|
phandle = <0x50>;
|
|
};
|
|
|
|
interconnect@320c0000 {
|
|
compatible = "qcom,pineapple-nsp_noc";
|
|
reg = <0x320c0000 0xf080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0xbe>;
|
|
};
|
|
|
|
interconnect@7e40000 {
|
|
compatible = "qcom,pineapple-lpass_ag_noc";
|
|
reg = <0x7e40000 0xe080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0x308>;
|
|
};
|
|
|
|
interconnect@7400000 {
|
|
compatible = "qcom,pineapple-lpass_lpiaon_noc";
|
|
reg = <0x7400000 0x19080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0x309>;
|
|
};
|
|
|
|
interconnect@7430000 {
|
|
compatible = "qcom,pineapple-lpass_lpicx_noc";
|
|
reg = <0x7430000 0x3a200>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x25>;
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
interrupt-controller@b220000 {
|
|
compatible = "qcom,pineapple-pdc", "qcom,pdc";
|
|
reg = <0xb220000 0x10000 0x174000f0 0x64>;
|
|
qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c 0x8a 0xfb 0x05 0x8f 0xf4 0x04>;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupt-controller;
|
|
phandle = <0x2e>;
|
|
};
|
|
|
|
pdc@b350000 {
|
|
compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc";
|
|
reg = <0xb350000 0x20000>;
|
|
phandle = <0x30a>;
|
|
};
|
|
|
|
pinctrl@f000000 {
|
|
compatible = "qcom,pineapple-pinctrl";
|
|
reg = <0xf000000 0x1000000>;
|
|
interrupts = <0x00 0xd0 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
wakeup-parent = <0x2e>;
|
|
qcom,gpios-reserved = <0x24 0x25 0x26 0x27 0x4a>;
|
|
phandle = <0xc1>;
|
|
|
|
qupv3_se15_2uart_pins {
|
|
phandle = <0x30b>;
|
|
|
|
qupv3_se15_2uart_tx_active {
|
|
phandle = <0x19a>;
|
|
|
|
mux {
|
|
pins = "gpio30";
|
|
function = "qup2_se7_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio30";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_2uart_rx_active {
|
|
phandle = <0x19b>;
|
|
|
|
mux {
|
|
pins = "gpio31";
|
|
function = "qup2_se7_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio31";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_2uart_sleep {
|
|
phandle = <0x19c>;
|
|
|
|
mux {
|
|
pins = "gpio30", "gpio31";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio30", "gpio31";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
trigout_a {
|
|
phandle = <0x2d8>;
|
|
|
|
mux {
|
|
pins = "gpio78";
|
|
function = "qdss_cti";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio78";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie0 {
|
|
|
|
pcie0_perst_default {
|
|
phandle = <0x2d9>;
|
|
|
|
mux {
|
|
pins = "gpio94";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio94";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_default {
|
|
phandle = <0x2da>;
|
|
|
|
mux {
|
|
pins = "gpio95";
|
|
function = "pcie0_clk_req_n";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio95";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_wake_default {
|
|
phandle = <0x2db>;
|
|
|
|
mux {
|
|
pins = "gpio96";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio96";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_sleep {
|
|
phandle = <0x2dc>;
|
|
|
|
mux {
|
|
pins = "gpio95";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio95";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie1 {
|
|
|
|
pcie1_perst_default {
|
|
phandle = <0x2de>;
|
|
|
|
mux {
|
|
pins = "gpio97";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio97";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie1_clkreq_default {
|
|
phandle = <0x2df>;
|
|
|
|
mux {
|
|
pins = "gpio98";
|
|
function = "pcie1_clk_req_n";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio98";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie1_wake_default {
|
|
phandle = <0x2e0>;
|
|
|
|
mux {
|
|
pins = "gpio99";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio99";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie1_clkreq_sleep {
|
|
phandle = <0x2e1>;
|
|
|
|
mux {
|
|
pins = "gpio98";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio98";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se14_4uart_pins {
|
|
phandle = <0x30c>;
|
|
|
|
qupv3_se14_default_cts {
|
|
phandle = <0x192>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_default_rts {
|
|
phandle = <0x193>;
|
|
|
|
mux {
|
|
pins = "gpio25";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio25";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_default_tx {
|
|
phandle = <0x194>;
|
|
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_default_rx {
|
|
phandle = <0x195>;
|
|
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_cts {
|
|
phandle = <0x196>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "qup2_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_rts {
|
|
phandle = <0x197>;
|
|
|
|
mux {
|
|
pins = "gpio25";
|
|
function = "qup2_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio25";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_tx {
|
|
phandle = <0x198>;
|
|
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "qup2_se6_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_rx {
|
|
phandle = <0x199>;
|
|
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "qup2_se6_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_pins {
|
|
phandle = <0x30d>;
|
|
|
|
qupv3_se0_i2c_sda_active {
|
|
phandle = <0xfd>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "qup1_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_scl_active {
|
|
phandle = <0xfe>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "qup1_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_sleep {
|
|
phandle = <0xff>;
|
|
|
|
mux {
|
|
pins = "gpio32", "gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32", "gpio33";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_pins {
|
|
phandle = <0x30e>;
|
|
|
|
qupv3_se0_i3c_sda_active {
|
|
phandle = <0x106>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_scl_active {
|
|
phandle = <0x107>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_sda_sleep {
|
|
phandle = <0x108>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_scl_sleep {
|
|
phandle = <0x109>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_disable {
|
|
phandle = <0x10a>;
|
|
|
|
mux {
|
|
pins = "gpio32", "gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32", "gpio33";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_pins {
|
|
phandle = <0x30f>;
|
|
|
|
qupv3_se0_spi_miso_active {
|
|
phandle = <0x102>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "qup1_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_mosi_active {
|
|
phandle = <0x101>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "qup1_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_clk_active {
|
|
phandle = <0x103>;
|
|
|
|
mux {
|
|
pins = "gpio34";
|
|
function = "qup1_se0_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio34";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_cs_active {
|
|
phandle = <0x104>;
|
|
|
|
mux {
|
|
pins = "gpio35";
|
|
function = "qup1_se0_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio35";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_sleep {
|
|
phandle = <0x105>;
|
|
|
|
mux {
|
|
pins = "gpio32", "gpio33", "gpio34", "gpio35";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32", "gpio33", "gpio34", "gpio35";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_pins {
|
|
phandle = <0x310>;
|
|
|
|
qupv3_se1_i2c_sda_active {
|
|
phandle = <0x10b>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "qup1_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_scl_active {
|
|
phandle = <0x10c>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "qup1_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_sleep {
|
|
phandle = <0x10d>;
|
|
|
|
mux {
|
|
pins = "gpio36", "gpio37";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36", "gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_pins {
|
|
phandle = <0x311>;
|
|
|
|
qupv3_se1_spi_miso_active {
|
|
phandle = <0x10f>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "qup1_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_mosi_active {
|
|
phandle = <0x10e>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "qup1_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_clk_active {
|
|
phandle = <0x110>;
|
|
|
|
mux {
|
|
pins = "gpio38";
|
|
function = "qup1_se1_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio38";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_cs_active {
|
|
phandle = <0x111>;
|
|
|
|
mux {
|
|
pins = "gpio39";
|
|
function = "qup1_se1_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio39";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_sleep {
|
|
phandle = <0x112>;
|
|
|
|
mux {
|
|
pins = "gpio36", "gpio37", "gpio38", "gpio39";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36", "gpio37", "gpio38", "gpio39";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_pins {
|
|
phandle = <0x312>;
|
|
|
|
qupv3_se2_i2c_sda_active {
|
|
phandle = <0x113>;
|
|
|
|
mux {
|
|
pins = "gpio40";
|
|
function = "qup1_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_scl_active {
|
|
phandle = <0x114>;
|
|
|
|
mux {
|
|
pins = "gpio41";
|
|
function = "qup1_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio41";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_sleep {
|
|
phandle = <0x115>;
|
|
|
|
mux {
|
|
pins = "gpio40", "gpio41";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40", "gpio41";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_pins {
|
|
phandle = <0x313>;
|
|
|
|
qupv3_se2_spi_miso_active {
|
|
phandle = <0x117>;
|
|
|
|
mux {
|
|
pins = "gpio40";
|
|
function = "qup1_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_mosi_active {
|
|
phandle = <0x116>;
|
|
|
|
mux {
|
|
pins = "gpio41";
|
|
function = "qup1_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio41";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_clk_active {
|
|
phandle = <0x118>;
|
|
|
|
mux {
|
|
pins = "gpio42";
|
|
function = "qup1_se2_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_cs_active {
|
|
phandle = <0x119>;
|
|
|
|
mux {
|
|
pins = "gpio43";
|
|
function = "qup1_se2_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio43";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_sleep {
|
|
phandle = <0x11a>;
|
|
|
|
mux {
|
|
pins = "gpio40", "gpio41", "gpio42", "gpio43";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40", "gpio41", "gpio42", "gpio43";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_pins {
|
|
phandle = <0x314>;
|
|
|
|
qupv3_se3_i2c_sda_active {
|
|
phandle = <0x11b>;
|
|
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "qup1_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_scl_active {
|
|
phandle = <0x11c>;
|
|
|
|
mux {
|
|
pins = "gpio45";
|
|
function = "qup1_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio45";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_sleep {
|
|
phandle = <0x11d>;
|
|
|
|
mux {
|
|
pins = "gpio44", "gpio45";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44", "gpio45";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_pins {
|
|
phandle = <0x315>;
|
|
|
|
qupv3_se3_spi_miso_active {
|
|
phandle = <0x120>;
|
|
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "qup1_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_mosi_active {
|
|
phandle = <0x11f>;
|
|
|
|
mux {
|
|
pins = "gpio45";
|
|
function = "qup1_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio45";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_clk_active {
|
|
phandle = <0x121>;
|
|
|
|
mux {
|
|
pins = "gpio46";
|
|
function = "qup1_se3_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio46";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_cs_active {
|
|
phandle = <0x122>;
|
|
|
|
mux {
|
|
pins = "gpio47";
|
|
function = "qup1_se3_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio47";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_sleep {
|
|
phandle = <0x123>;
|
|
|
|
mux {
|
|
pins = "gpio44", "gpio45", "gpio46", "gpio47";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44", "gpio45", "gpio46", "gpio47";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_pins {
|
|
phandle = <0x316>;
|
|
|
|
qupv3_se4_i2c_sda_active {
|
|
phandle = <0x124>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "qup1_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_scl_active {
|
|
phandle = <0x125>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "qup1_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_sleep {
|
|
phandle = <0x126>;
|
|
|
|
mux {
|
|
pins = "gpio48", "gpio49";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48", "gpio49";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_pins {
|
|
phandle = <0x317>;
|
|
|
|
qupv3_se4_i3c_sda_active {
|
|
phandle = <0x12c>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_scl_active {
|
|
phandle = <0x12d>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_sda_sleep {
|
|
phandle = <0x12e>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_scl_sleep {
|
|
phandle = <0x12f>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_disable {
|
|
phandle = <0x130>;
|
|
|
|
mux {
|
|
pins = "gpio48", "gpio49";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48", "gpio49";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_pins {
|
|
phandle = <0x318>;
|
|
|
|
qupv3_se4_spi_miso_active {
|
|
phandle = <0x128>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "qup1_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_mosi_active {
|
|
phandle = <0x127>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "qup1_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_clk_active {
|
|
phandle = <0x129>;
|
|
|
|
mux {
|
|
pins = "gpio50";
|
|
function = "qup1_se4_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio50";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_cs_active {
|
|
phandle = <0x12a>;
|
|
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "qup1_se4_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_sleep {
|
|
phandle = <0x12b>;
|
|
|
|
mux {
|
|
pins = "gpio48", "gpio49", "gpio50", "gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48", "gpio49", "gpio50", "gpio51";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_pins {
|
|
phandle = <0x319>;
|
|
|
|
qupv3_se5_i2c_sda_active {
|
|
phandle = <0x131>;
|
|
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "qup1_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_scl_active {
|
|
phandle = <0x132>;
|
|
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "qup1_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_sleep {
|
|
phandle = <0x133>;
|
|
|
|
mux {
|
|
pins = "gpio52", "gpio53";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52", "gpio53";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_pins {
|
|
phandle = <0x31a>;
|
|
|
|
qupv3_se5_spi_miso_active {
|
|
phandle = <0x135>;
|
|
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "qup1_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_mosi_active {
|
|
phandle = <0x134>;
|
|
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "qup1_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_clk_active {
|
|
phandle = <0x136>;
|
|
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "qup1_se5_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_cs_active {
|
|
phandle = <0x137>;
|
|
|
|
mux {
|
|
pins = "gpio55";
|
|
function = "qup1_se5_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio55";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_sleep {
|
|
phandle = <0x138>;
|
|
|
|
mux {
|
|
pins = "gpio52", "gpio53", "gpio54", "gpio55";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52", "gpio53", "gpio54", "gpio55";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_pins {
|
|
phandle = <0x31b>;
|
|
|
|
qupv3_se6_i2c_sda_active {
|
|
phandle = <0x139>;
|
|
|
|
mux {
|
|
pins = "gpio56";
|
|
function = "qup1_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_scl_active {
|
|
phandle = <0x13a>;
|
|
|
|
mux {
|
|
pins = "gpio57";
|
|
function = "qup1_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio57";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_sleep {
|
|
phandle = <0x13b>;
|
|
|
|
mux {
|
|
pins = "gpio56", "gpio57";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56", "gpio57";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_pins {
|
|
phandle = <0x31c>;
|
|
|
|
qupv3_se6_spi_miso_active {
|
|
phandle = <0x13d>;
|
|
|
|
mux {
|
|
pins = "gpio56";
|
|
function = "qup1_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_mosi_active {
|
|
phandle = <0x13c>;
|
|
|
|
mux {
|
|
pins = "gpio57";
|
|
function = "qup1_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio57";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_clk_active {
|
|
phandle = <0x13e>;
|
|
|
|
mux {
|
|
pins = "gpio58";
|
|
function = "qup1_se6_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio58";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_cs_active {
|
|
phandle = <0x13f>;
|
|
|
|
mux {
|
|
pins = "gpio59";
|
|
function = "qup1_se6_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio59";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_sleep {
|
|
phandle = <0x140>;
|
|
|
|
mux {
|
|
pins = "gpio56", "gpio57", "gpio58", "gpio59";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56", "gpio57", "gpio58", "gpio59";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_pins {
|
|
phandle = <0x31d>;
|
|
|
|
qupv3_se7_i2c_sda_active {
|
|
phandle = <0x141>;
|
|
|
|
mux {
|
|
pins = "gpio60";
|
|
function = "qup1_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio60";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_scl_active {
|
|
phandle = <0x142>;
|
|
|
|
mux {
|
|
pins = "gpio61";
|
|
function = "qup1_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio61";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_sleep {
|
|
phandle = <0x143>;
|
|
|
|
mux {
|
|
pins = "gpio60", "gpio61";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio60", "gpio61";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_pins {
|
|
phandle = <0x31e>;
|
|
|
|
qupv3_se7_spi_miso_active {
|
|
phandle = <0x145>;
|
|
|
|
mux {
|
|
pins = "gpio60";
|
|
function = "qup1_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio60";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_mosi_active {
|
|
phandle = <0x144>;
|
|
|
|
mux {
|
|
pins = "gpio61";
|
|
function = "qup1_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio61";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_clk_active {
|
|
phandle = <0x146>;
|
|
|
|
mux {
|
|
pins = "gpio62";
|
|
function = "qup1_se7_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio62";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_cs_active {
|
|
phandle = <0x147>;
|
|
|
|
mux {
|
|
pins = "gpio63";
|
|
function = "qup1_se7_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio63";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_sleep {
|
|
phandle = <0x148>;
|
|
|
|
mux {
|
|
pins = "gpio60", "gpio61", "gpio62", "gpio63";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio60", "gpio61", "gpio62", "gpio63";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_pins {
|
|
phandle = <0x31f>;
|
|
|
|
qupv3_se8_i2c_sda_active {
|
|
phandle = <0x149>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "qup2_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_scl_active {
|
|
phandle = <0x14a>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "qup2_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_sleep {
|
|
phandle = <0x14b>;
|
|
|
|
mux {
|
|
pins = "gpio0", "gpio1";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_pins {
|
|
phandle = <0x320>;
|
|
|
|
qupv3_se8_spi_miso_active {
|
|
phandle = <0x14e>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "qup2_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_mosi_active {
|
|
phandle = <0x14d>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "qup2_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_clk_active {
|
|
phandle = <0x14f>;
|
|
|
|
mux {
|
|
pins = "gpio2";
|
|
function = "qup2_se0_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio2";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_cs_active {
|
|
phandle = <0x150>;
|
|
|
|
mux {
|
|
pins = "gpio3";
|
|
function = "qup2_se0_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio3";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_sleep {
|
|
phandle = <0x151>;
|
|
|
|
mux {
|
|
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_pins {
|
|
phandle = <0x321>;
|
|
|
|
qupv3_se8_i3c_sda_active {
|
|
phandle = <0x152>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,apps;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_scl_active {
|
|
phandle = <0x153>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,apps;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_sda_sleep {
|
|
phandle = <0x154>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,remote;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_scl_sleep {
|
|
phandle = <0x155>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,remote;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_disable {
|
|
phandle = <0x156>;
|
|
|
|
mux {
|
|
pins = "gpio0", "gpio1";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_pins {
|
|
phandle = <0x322>;
|
|
|
|
qupv3_se9_i2c_sda_active {
|
|
phandle = <0x158>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "qup2_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,apps;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_scl_active {
|
|
phandle = <0x159>;
|
|
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "qup2_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,apps;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_sleep {
|
|
phandle = <0x15a>;
|
|
|
|
mux {
|
|
pins = "gpio4", "gpio5";
|
|
function = "qup2_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
qcom,remote;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_pins {
|
|
phandle = <0x323>;
|
|
|
|
qupv3_se9_spi_miso_active {
|
|
phandle = <0x15c>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "qup2_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_mosi_active {
|
|
phandle = <0x15b>;
|
|
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "qup2_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_clk_active {
|
|
phandle = <0x15d>;
|
|
|
|
mux {
|
|
pins = "gpio6";
|
|
function = "qup2_se1_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_cs_active {
|
|
phandle = <0x15e>;
|
|
|
|
mux {
|
|
pins = "gpio7";
|
|
function = "qup2_se1_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio7";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_sleep {
|
|
phandle = <0x15f>;
|
|
|
|
mux {
|
|
pins = "gpio4", "gpio5", "gpio6", "gpio7";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5", "gpio6", "gpio7";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_pins {
|
|
phandle = <0x324>;
|
|
|
|
qupv3_se10_i2c_sda_active {
|
|
phandle = <0x160>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup2_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_scl_active {
|
|
phandle = <0x161>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup2_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_sleep {
|
|
phandle = <0x162>;
|
|
|
|
mux {
|
|
pins = "gpio8", "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_pins {
|
|
phandle = <0x325>;
|
|
|
|
qupv3_se10_spi_miso_active {
|
|
phandle = <0x164>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup2_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_mosi_active {
|
|
phandle = <0x163>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup2_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_clk_active {
|
|
phandle = <0x165>;
|
|
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "qup2_se2_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_cs_active {
|
|
phandle = <0x166>;
|
|
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "qup2_se2_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_sleep {
|
|
phandle = <0x167>;
|
|
|
|
mux {
|
|
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_pins {
|
|
phandle = <0x326>;
|
|
|
|
qupv3_se10_i3c_sda_active {
|
|
phandle = <0x168>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_scl_active {
|
|
phandle = <0x169>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_sda_sleep {
|
|
phandle = <0x16a>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_scl_sleep {
|
|
phandle = <0x16b>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_disable {
|
|
phandle = <0x16c>;
|
|
|
|
mux {
|
|
pins = "gpio8", "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_pins {
|
|
phandle = <0x327>;
|
|
|
|
qupv3_se11_i2c_sda_active {
|
|
phandle = <0x172>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup2_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_scl_active {
|
|
phandle = <0x173>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup2_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_sleep {
|
|
phandle = <0x174>;
|
|
|
|
mux {
|
|
pins = "gpio12", "gpio13";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_pins {
|
|
phandle = <0x328>;
|
|
|
|
qupv3_se11_spi_miso_active {
|
|
phandle = <0x176>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup2_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_mosi_active {
|
|
phandle = <0x175>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup2_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_clk_active {
|
|
phandle = <0x177>;
|
|
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "qup2_se3_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_cs_active {
|
|
phandle = <0x178>;
|
|
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "qup2_se3_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_sleep {
|
|
phandle = <0x179>;
|
|
|
|
mux {
|
|
pins = "gpio12", "gpio13", "gpio14", "gpio15";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13", "gpio14", "gpio15";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_pins {
|
|
phandle = <0x329>;
|
|
|
|
qupv3_se11_i3c_sda_active {
|
|
phandle = <0x16d>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_scl_active {
|
|
phandle = <0x16e>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_sda_sleep {
|
|
phandle = <0x16f>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_scl_sleep {
|
|
phandle = <0x170>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_disable {
|
|
phandle = <0x171>;
|
|
|
|
mux {
|
|
pins = "gpio12", "gpio13";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_pins {
|
|
phandle = <0x32a>;
|
|
|
|
qupv3_se12_i2c_sda_active {
|
|
phandle = <0x17a>;
|
|
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "qup2_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_scl_active {
|
|
phandle = <0x17b>;
|
|
|
|
mux {
|
|
pins = "gpio17";
|
|
function = "qup2_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_sleep {
|
|
phandle = <0x17c>;
|
|
|
|
mux {
|
|
pins = "gpio16", "gpio17";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16", "gpio17";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_pins {
|
|
phandle = <0x32b>;
|
|
|
|
qupv3_se12_spi_miso_active {
|
|
phandle = <0x17e>;
|
|
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "qup2_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_mosi_active {
|
|
phandle = <0x17d>;
|
|
|
|
mux {
|
|
pins = "gpio17";
|
|
function = "qup2_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_clk_active {
|
|
phandle = <0x17f>;
|
|
|
|
mux {
|
|
pins = "gpio18";
|
|
function = "qup2_se4_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_cs_active {
|
|
phandle = <0x180>;
|
|
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "qup2_se4_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_sleep {
|
|
phandle = <0x181>;
|
|
|
|
mux {
|
|
pins = "gpio16", "gpio17", "gpio18", "gpio19";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16", "gpio17", "gpio18", "gpio19";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se13_i2c_pins {
|
|
phandle = <0x32c>;
|
|
|
|
qupv3_se13_i2c_sda_active {
|
|
phandle = <0x182>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_i2c_scl_active {
|
|
phandle = <0x183>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_i2c_sleep {
|
|
phandle = <0x184>;
|
|
|
|
mux {
|
|
pins = "gpio20", "gpio21";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20", "gpio21";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_pins {
|
|
phandle = <0x32d>;
|
|
|
|
qupv3_se13_spi_miso_active {
|
|
phandle = <0x186>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_mosi_active {
|
|
phandle = <0x185>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_clk_active {
|
|
phandle = <0x187>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "qup2_se5_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_cs_active {
|
|
phandle = <0x188>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "qup2_se5_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_sleep {
|
|
phandle = <0x189>;
|
|
|
|
mux {
|
|
pins = "gpio20", "gpio21", "gpio22", "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20", "gpio21", "gpio22", "gpio23";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_pins {
|
|
phandle = <0x32e>;
|
|
|
|
qupv3_se13_q2spi_default {
|
|
phandle = <0x18b>;
|
|
|
|
mux {
|
|
pins = "gpio21", "gpio22", "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21", "gpio22", "gpio23";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_miso_default {
|
|
phandle = <0x18a>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_miso_active {
|
|
phandle = <0x18d>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_mosi_active {
|
|
phandle = <0x18c>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_clk_active {
|
|
phandle = <0x18e>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "qup2_se5_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_doorbell_active {
|
|
phandle = <0x18f>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "qup2_se5_l6";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_doorbell_sleep {
|
|
phandle = <0x191>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_miso_sleep {
|
|
phandle = <0x190>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c0_pins {
|
|
phandle = <0x32f>;
|
|
|
|
qupv3_hub_i2c0_sda_active {
|
|
phandle = <0x19d>;
|
|
|
|
mux {
|
|
pins = "gpio64";
|
|
function = "i2chub0_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c0_scl_active {
|
|
phandle = <0x19e>;
|
|
|
|
mux {
|
|
pins = "gpio65";
|
|
function = "i2chub0_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio65";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c0_sleep {
|
|
phandle = <0x19f>;
|
|
|
|
mux {
|
|
pins = "gpio64", "gpio65";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64", "gpio65";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c1_pins {
|
|
phandle = <0x330>;
|
|
|
|
qupv3_hub_i2c1_sda_active {
|
|
phandle = <0x1a0>;
|
|
|
|
mux {
|
|
pins = "gpio66";
|
|
function = "i2chub0_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c1_scl_active {
|
|
phandle = <0x1a1>;
|
|
|
|
mux {
|
|
pins = "gpio67";
|
|
function = "i2chub0_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio67";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c1_sleep {
|
|
phandle = <0x1a2>;
|
|
|
|
mux {
|
|
pins = "gpio66", "gpio67";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66", "gpio67";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c2_pins {
|
|
phandle = <0x331>;
|
|
|
|
qupv3_hub_i2c2_sda_active {
|
|
phandle = <0x1a3>;
|
|
|
|
mux {
|
|
pins = "gpio68";
|
|
function = "i2chub0_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio68";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c2_scl_active {
|
|
phandle = <0x1a4>;
|
|
|
|
mux {
|
|
pins = "gpio69";
|
|
function = "i2chub0_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c2_sleep {
|
|
phandle = <0x1a5>;
|
|
|
|
mux {
|
|
pins = "gpio68", "gpio69";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio68", "gpio69";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c3_pins {
|
|
phandle = <0x332>;
|
|
|
|
qupv3_hub_i2c3_sda_active {
|
|
phandle = <0x1a6>;
|
|
|
|
mux {
|
|
pins = "gpio70";
|
|
function = "i2chub0_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio70";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c3_scl_active {
|
|
phandle = <0x1a7>;
|
|
|
|
mux {
|
|
pins = "gpio71";
|
|
function = "i2chub0_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio71";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c3_sleep {
|
|
phandle = <0x1a8>;
|
|
|
|
mux {
|
|
pins = "gpio70", "gpio71";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio70", "gpio71";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c4_pins {
|
|
phandle = <0x333>;
|
|
|
|
qupv3_hub_i2c4_sda_active {
|
|
phandle = <0x1a9>;
|
|
|
|
mux {
|
|
pins = "gpio72";
|
|
function = "i2chub0_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio72";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c4_scl_active {
|
|
phandle = <0x1aa>;
|
|
|
|
mux {
|
|
pins = "gpio73";
|
|
function = "i2chub0_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio73";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c4_sleep {
|
|
phandle = <0x1ab>;
|
|
|
|
mux {
|
|
pins = "gpio72", "gpio73";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio72", "gpio73";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c5_pins {
|
|
phandle = <0x334>;
|
|
|
|
qupv3_hub_i2c5_sda_active {
|
|
phandle = <0x1ac>;
|
|
|
|
mux {
|
|
pins = "gpio74";
|
|
function = "i2chub0_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio74";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c5_scl_active {
|
|
phandle = <0x1ad>;
|
|
|
|
mux {
|
|
pins = "gpio75";
|
|
function = "i2chub0_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio75";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c5_sleep {
|
|
phandle = <0x1ae>;
|
|
|
|
mux {
|
|
pins = "gpio74", "gpio75";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio74", "gpio75";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c6_pins {
|
|
phandle = <0x335>;
|
|
|
|
qupv3_hub_i2c6_sda_active {
|
|
phandle = <0x1af>;
|
|
|
|
mux {
|
|
pins = "gpio76";
|
|
function = "i2chub0_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio76";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c6_scl_active {
|
|
phandle = <0x1b0>;
|
|
|
|
mux {
|
|
pins = "gpio77";
|
|
function = "i2chub0_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio77";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c6_sleep {
|
|
phandle = <0x1b1>;
|
|
|
|
mux {
|
|
pins = "gpio76", "gpio77";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio76", "gpio77";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c7_pins {
|
|
phandle = <0x336>;
|
|
|
|
qupv3_hub_i2c7_sda_active {
|
|
phandle = <0x1b2>;
|
|
|
|
mux {
|
|
pins = "gpio78";
|
|
function = "i2chub0_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio78";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c7_scl_active {
|
|
phandle = <0x1b3>;
|
|
|
|
mux {
|
|
pins = "gpio79";
|
|
function = "i2chub0_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio79";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c7_sleep {
|
|
phandle = <0x1b4>;
|
|
|
|
mux {
|
|
pins = "gpio78", "gpio79";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio78", "gpio79";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c8_pins {
|
|
phandle = <0x337>;
|
|
|
|
qupv3_hub_i2c8_sda_active {
|
|
phandle = <0x1b5>;
|
|
|
|
mux {
|
|
pins = "gpio206";
|
|
function = "i2chub0_se8_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio206";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c8_scl_active {
|
|
phandle = <0x1b6>;
|
|
|
|
mux {
|
|
pins = "gpio207";
|
|
function = "i2chub0_se8_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio207";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c8_sleep {
|
|
phandle = <0x1b7>;
|
|
|
|
mux {
|
|
pins = "gpio206", "gpio207";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio206", "gpio207";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c9_pins {
|
|
phandle = <0x338>;
|
|
|
|
qupv3_hub_i2c9_sda_active {
|
|
phandle = <0x1b8>;
|
|
|
|
mux {
|
|
pins = "gpio80";
|
|
function = "i2chub0_se9_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c9_scl_active {
|
|
phandle = <0x1b9>;
|
|
|
|
mux {
|
|
pins = "gpio81";
|
|
function = "i2chub0_se9_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c9_sleep {
|
|
phandle = <0x1ba>;
|
|
|
|
mux {
|
|
pins = "gpio80", "gpio81";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80", "gpio81";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux0_pcm_clk {
|
|
|
|
aux0_pcm_clk_sleep {
|
|
phandle = <0x339>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux0_pcm_clk_active {
|
|
phandle = <0x33a>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "i2s0_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux0_pcm_ws {
|
|
|
|
aux0_pcm_ws_sleep {
|
|
phandle = <0x33b>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux0_pcm_ws_active {
|
|
phandle = <0x33c>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "i2s0_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux0_pcm_din {
|
|
|
|
aux0_pcm_din_sleep {
|
|
phandle = <0x33d>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux0_pcm_din_active {
|
|
phandle = <0x33e>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "i2s0_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux0_pcm_dout {
|
|
|
|
aux0_pcm_dout_sleep {
|
|
phandle = <0x33f>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux0_pcm_dout_active {
|
|
phandle = <0x340>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "i2s0_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux1_pcm_clk {
|
|
|
|
aux1_pcm_clk_sleep {
|
|
phandle = <0x341>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux1_pcm_clk_active {
|
|
phandle = <0x342>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "i2s1_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux1_pcm_ws {
|
|
|
|
aux1_pcm_ws_sleep {
|
|
phandle = <0x343>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux1_pcm_ws_active {
|
|
phandle = <0x344>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "i2s1_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux1_pcm_din {
|
|
|
|
aux1_pcm_din_sleep {
|
|
phandle = <0x345>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux1_pcm_din_active {
|
|
phandle = <0x346>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "i2s1_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
aux1_pcm_dout {
|
|
|
|
aux1_pcm_dout_sleep {
|
|
phandle = <0x347>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
aux1_pcm_dout_active {
|
|
phandle = <0x348>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "i2s1_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_clk {
|
|
|
|
tdm0_clk_sleep {
|
|
phandle = <0x349>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_clk_active {
|
|
phandle = <0x34a>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "i2s0_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_ws {
|
|
|
|
tdm0_ws_sleep {
|
|
phandle = <0x34b>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_ws_active {
|
|
phandle = <0x34c>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "i2s0_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_din {
|
|
|
|
tdm0_din_sleep {
|
|
phandle = <0x34d>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_din_active {
|
|
phandle = <0x34e>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "i2s0_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_dout {
|
|
|
|
tdm0_dout_sleep {
|
|
phandle = <0x34f>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_dout_active {
|
|
phandle = <0x350>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "i2s0_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_clk {
|
|
|
|
tdm1_clk_sleep {
|
|
phandle = <0x351>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_clk_active {
|
|
phandle = <0x352>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "i2s1_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_ws {
|
|
|
|
tdm1_ws_sleep {
|
|
phandle = <0x353>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_ws_active {
|
|
phandle = <0x354>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "i2s1_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_din {
|
|
|
|
tdm1_din_sleep {
|
|
phandle = <0x355>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_din_active {
|
|
phandle = <0x356>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "i2s1_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_dout {
|
|
|
|
tdm1_dout_sleep {
|
|
phandle = <0x357>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_dout_active {
|
|
phandle = <0x358>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "i2s1_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s0_sck {
|
|
|
|
i2s0_sck_sleep {
|
|
phandle = <0x359>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_sck_active {
|
|
phandle = <0x35a>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "i2s0_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s0_ws {
|
|
|
|
i2s0_ws_sleep {
|
|
phandle = <0x35b>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_ws_active {
|
|
phandle = <0x35c>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "i2s0_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s0_sd0 {
|
|
|
|
i2s0_sd0_sleep {
|
|
phandle = <0x35d>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_sd0_active {
|
|
phandle = <0x35e>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "i2s0_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s0_sd1 {
|
|
|
|
i2s0_sd1_sleep {
|
|
phandle = <0x35f>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_sd1_active {
|
|
phandle = <0x360>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "i2s0_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_sck {
|
|
|
|
i2s1_sck_sleep {
|
|
phandle = <0x361>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_sck_active {
|
|
phandle = <0x362>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "i2s1_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_ws {
|
|
|
|
i2s1_ws_sleep {
|
|
phandle = <0x363>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_ws_active {
|
|
phandle = <0x364>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "i2s1_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_sd0 {
|
|
|
|
i2s1_sd0_sleep {
|
|
phandle = <0x365>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_sd0_active {
|
|
phandle = <0x366>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "i2s1_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_sd1 {
|
|
|
|
i2s1_sd1_sleep {
|
|
phandle = <0x367>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_sd1_active {
|
|
phandle = <0x368>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "i2s1_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
sdc2_on {
|
|
phandle = <0x369>;
|
|
|
|
clk {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc2_off {
|
|
phandle = <0x36a>;
|
|
|
|
clk {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
wcd939x_reset_active {
|
|
phandle = <0x36b>;
|
|
|
|
mux {
|
|
pins = "gpio107";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio107";
|
|
drive-strength = <0x10>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
wcd939x_reset_sleep {
|
|
phandle = <0x36c>;
|
|
|
|
mux {
|
|
pins = "gpio107";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio107";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
spkr_13_sd_n {
|
|
|
|
spkr_13_sd_n_sleep {
|
|
phandle = <0x36d>;
|
|
|
|
mux {
|
|
pins = "gpio77";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio77";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_13_sd_n_active {
|
|
phandle = <0x36e>;
|
|
|
|
mux {
|
|
pins = "gpio77";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio77";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
usb_phy_ps {
|
|
phandle = <0x36f>;
|
|
|
|
usb3phy_portselect_default {
|
|
phandle = <0x1bf>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "usb_phy";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
usb3phy_portselect_gpio {
|
|
phandle = <0x370>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_active {
|
|
|
|
ts_active {
|
|
phandle = <0x371>;
|
|
|
|
mux {
|
|
pins = "gpio161", "gpio162";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio161", "gpio162";
|
|
drive-strength = <0x08>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_reset_suspend {
|
|
|
|
ts_reset_suspend {
|
|
phandle = <0x372>;
|
|
|
|
mux {
|
|
pins = "gpio161";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio161";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_int_suspend {
|
|
|
|
ts_int_suspend {
|
|
phandle = <0x373>;
|
|
|
|
mux {
|
|
pins = "gpio162";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio162";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_release {
|
|
|
|
ts_release {
|
|
phandle = <0x374>;
|
|
|
|
mux {
|
|
pins = "gpio161", "gpio162";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio161", "gpio162";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qps615_intn_wol {
|
|
|
|
qca_intn_wol_sig {
|
|
phandle = <0x375>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
show_resume_irqs@17100000 {
|
|
compatible = "qcom,show-resume-irqs";
|
|
reg = <0x17100000 0x290000>;
|
|
};
|
|
|
|
dload_mode {
|
|
compatible = "qcom,dload-mode";
|
|
};
|
|
|
|
mini_dump_mode {
|
|
compatible = "qcom,minidump";
|
|
status = "ok";
|
|
};
|
|
|
|
va_mini_dump {
|
|
compatible = "qcom,va-minidump";
|
|
memory-region = <0x2f>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cpu-vendor-hooks {
|
|
compatible = "qcom,cpu-vendor-hooks";
|
|
phandle = <0x376>;
|
|
};
|
|
|
|
qcom,logbuf-vendor-hooks {
|
|
compatible = "qcom,logbuf-vendor-hooks";
|
|
phandle = <0x377>;
|
|
};
|
|
|
|
rsc@17a00000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x17a00000 0x10000 0x17a10000 0x10000 0x17a20000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <0x03>;
|
|
interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>;
|
|
power-domains = <0x21>;
|
|
phandle = <0x378>;
|
|
|
|
drv@2 {
|
|
qcom,drv-id = <0x02>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
phandle = <0x379>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x04 0x01>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
clock-controller {
|
|
compatible = "qcom,pineapple-rpmh-clk";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
qcom,dcvs-fp {
|
|
compatible = "qcom,dcvs-fp";
|
|
qcom,ddr-bcm-name = "MC4";
|
|
qcom,llcc-bcm-name = "SH5";
|
|
phandle = <0xd2>;
|
|
};
|
|
|
|
rpmh-regulator-lcxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "lcx.lvl";
|
|
|
|
regulator-pm-v6d-s4-level {
|
|
regulator-name = "pm_v6d_s4_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0xaa>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-gfxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "gfx.lvl";
|
|
|
|
regulator-pm-v6d-s5-level {
|
|
regulator-name = "pm_v6d_s5_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x35>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-lmxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "lmx.lvl";
|
|
|
|
regulator-pm-v6d-l2-level {
|
|
regulator-name = "pm_v6d_l2_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0xab>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-nsp2lvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "nsp2.lvl";
|
|
|
|
regulator-pm-v6g-s1-level {
|
|
regulator-name = "pm_v6g_s1_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x37a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ebilvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "ebi.lvl";
|
|
|
|
regulator-pm-v6g-s4-level {
|
|
regulator-name = "pm_v6g_s4_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x37b>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-msslvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mss.lvl";
|
|
|
|
regulator-pm-v6g-s5-level {
|
|
regulator-name = "pm_v6g_s5_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0xb1>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-cxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "cx.lvl";
|
|
proxy-supply = <0x30>;
|
|
|
|
regulator-pm-v8-s8-level {
|
|
regulator-name = "pm_v8_s8_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x30>;
|
|
};
|
|
|
|
regulator-pm-v8-s8-level-ao {
|
|
regulator-name = "pm_v8_s8_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x44>;
|
|
};
|
|
|
|
regulator-pm-v8-s8-mmcx-sup-level {
|
|
regulator-name = "pm_v8_s8_mmcx_sup_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x30>;
|
|
phandle = <0x32>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-mmcxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mmcx.lvl";
|
|
proxy-supply = <0x31>;
|
|
|
|
regulator-pm-v8-s1-level {
|
|
regulator-name = "pm_v8_s1_level";
|
|
qcom,set = <0x03>;
|
|
pm_v8_s1_level-parent-supply = <0x32>;
|
|
regulator-min-microvolt = <0x38>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x31>;
|
|
};
|
|
|
|
regulator-pm-v8-s1-level-ao {
|
|
regulator-name = "pm_v8_s1_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x38>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x38>;
|
|
phandle = <0x37c>;
|
|
};
|
|
|
|
regulator-pm-v8-s1-level-so {
|
|
regulator-name = "pm_v8_s1_level_so";
|
|
qcom,set = <0x02>;
|
|
regulator-min-microvolt = <0x38>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x38>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-mxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mx.lvl";
|
|
proxy-supply = <0x33>;
|
|
|
|
regulator-pm-v8-s3-level {
|
|
regulator-name = "pm_v8_s3_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x33>;
|
|
};
|
|
|
|
regulator-pm-v8-s3-level-ao {
|
|
regulator-name = "pm_v8_s3_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x37d>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-mxclvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mxc.lvl";
|
|
proxy-supply = <0x34>;
|
|
|
|
regulator-pm-v6d-s3-level {
|
|
regulator-name = "pm_v6d_s3_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x34>;
|
|
};
|
|
|
|
regulator-pm-v6d-s3-level-ao {
|
|
regulator-name = "pm_v6d_s3_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x37e>;
|
|
};
|
|
|
|
regulator-pm-v6d-s3-mmcx-voter-level {
|
|
regulator-name = "pm_v6d_s3_mmcx_voter_level";
|
|
pm_v6d_s3_mmcx_voter_level-parent-supply = <0x31>;
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x30>;
|
|
phandle = <0xe3>;
|
|
};
|
|
|
|
regulator-pm-v6d-s3-gfx-voter-level {
|
|
regulator-name = "pm_v6d_s3_gfx_voter_level";
|
|
pm_v6d_s3_gfx_voter_level-parent-supply = <0x35>;
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x30>;
|
|
phandle = <0xee>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-nsplvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "nsp.lvl";
|
|
|
|
regulator-pm-v8-s6-level {
|
|
regulator-name = "pm_v8_s6_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0xba>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l1 {
|
|
regulator-name = "pm_humu_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x37f>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l2 {
|
|
regulator-name = "pm_humu_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2de600>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x2de600>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x380>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob4";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l4 {
|
|
regulator-name = "pm_humu_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x381>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob5";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l5 {
|
|
regulator-name = "pm_humu_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = "", "/]";
|
|
regulator-max-microvolt = "", "/]";
|
|
qcom,init-voltage = "", "/]";
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x382>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob6";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l6 {
|
|
regulator-name = "pm_humu_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x383>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob7";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l7 {
|
|
regulator-name = "pm_humu_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x384>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob8 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob8";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l8 {
|
|
regulator-name = "pm_humu_l8";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x385>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob9 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob9";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l9 {
|
|
regulator-name = "pm_humu_l9";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2d2a80>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x2d2a80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x386>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob10 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob10";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l10 {
|
|
regulator-name = "pm_humu_l10";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x387>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob11 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob11";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l11 {
|
|
regulator-name = "pm_humu_l11";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x388>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob12 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob12";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l12 {
|
|
regulator-name = "pm_humu_l12";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x389>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob13 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob13";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l13 {
|
|
regulator-name = "pm_humu_l13";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2dc6c0>;
|
|
regulator-max-microvolt = <0x2dc6c0>;
|
|
qcom,init-voltage = <0x2dc6c0>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x38a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob14 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob14";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l14 {
|
|
regulator-name = "pm_humu_l14";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30d400>;
|
|
regulator-max-microvolt = <0x30d400>;
|
|
qcom,init-voltage = <0x30d400>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x38b>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob15 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob15";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l15 {
|
|
regulator-name = "pm_humu_l15";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x11e>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob16 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob16";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l16 {
|
|
regulator-name = "pm_humu_l16";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x38c>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob17 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob17";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l17 {
|
|
regulator-name = "pm_humu_l17";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x263540>;
|
|
regulator-max-microvolt = <0x263540>;
|
|
qcom,init-voltage = <0x263540>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x38d>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-bobb1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "bobb1";
|
|
|
|
regulator-pm-humu-bob1 {
|
|
regulator-name = "pm_humu_bob1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2de600>;
|
|
regulator-max-microvolt = <0x3c6cc0>;
|
|
qcom,init-voltage = "", "2K";
|
|
phandle = <0x38e>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-bobb2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "bobb2";
|
|
|
|
regulator-pm-humu-bob2 {
|
|
regulator-name = "pm_humu_bob2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x294280>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x298100>;
|
|
phandle = <0x38f>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpc1";
|
|
qcom,regulator-type = "pmic5-ftsmps";
|
|
qcom,supported-modes = <0x01 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x30d40>;
|
|
|
|
regulator-pm-v6c-s1 {
|
|
regulator-name = "pm_v6c_s1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x12ad40>;
|
|
regulator-max-microvolt = <0x1491a0>;
|
|
qcom,init-voltage = <0x132a40>;
|
|
qcom,init-mode = <0x01>;
|
|
phandle = <0x390>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpc2";
|
|
|
|
regulator-pm-v6c-s2 {
|
|
regulator-name = "pm_v6c_s2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0xfcee0>;
|
|
qcom,init-voltage = <0xd0020>;
|
|
phandle = <0x391>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpc3";
|
|
|
|
regulator-pm-v6c-s3 {
|
|
regulator-name = "pm_v6c_s3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xdcb40>;
|
|
regulator-max-microvolt = <0x103c40>;
|
|
qcom,init-voltage = <0xee480>;
|
|
phandle = <0x392>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpc4";
|
|
|
|
regulator-pm-v6c-s4 {
|
|
regulator-name = "pm_v6c_s4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x138800>;
|
|
qcom,init-voltage = <0x12ad40>;
|
|
phandle = <0x393>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpc5";
|
|
|
|
regulator-pm-v6c-s5 {
|
|
regulator-name = "pm_v6c_s5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x493e0>;
|
|
regulator-max-microvolt = <0xdbba0>;
|
|
qcom,init-voltage = <0xb7980>;
|
|
phandle = <0x394>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpc6";
|
|
|
|
regulator-pm-v6c-s6 {
|
|
regulator-name = "pm_v6c_s6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1c5200>;
|
|
regulator-max-microvolt = <0x1e8480>;
|
|
qcom,init-voltage = <0x1c5200>;
|
|
phandle = <0x395>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoc1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6c-l1 {
|
|
regulator-name = "pm_v6c_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10c8e0>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x396>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoc2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6c-l2 {
|
|
regulator-name = "pm_v6c_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x397>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoc3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x01 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6c-l3 {
|
|
regulator-name = "pm_v6c_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x398>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldod1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldod1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6d-l1 {
|
|
regulator-name = "pm_v6d_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xdea80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x399>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldod3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldod3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6d-l3 {
|
|
regulator-name = "pm_v6d_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = "", "\f5";
|
|
regulator-max-microvolt = <0xdbba0>;
|
|
qcom,init-voltage = <0xcb200>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x39a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoe1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoe1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6e-l1 {
|
|
regulator-name = "pm_v6e_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x39b>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoe2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoe2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6e-l2 {
|
|
regulator-name = "pm_v6e_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = "", "\r/";
|
|
regulator-max-microvolt = <0xed4e0>;
|
|
qcom,init-voltage = <0xdcb40>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x39c>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoe3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoe3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6e-l3 {
|
|
regulator-name = "pm_v6e_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x2e4>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpg3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpg3";
|
|
|
|
regulator-pm-v6g-s3 {
|
|
regulator-name = "pm_v6g_s3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xf4240>;
|
|
regulator-max-microvolt = <0x10c8e0>;
|
|
qcom,init-voltage = <0x107ac0>;
|
|
phandle = <0x39d>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldog1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldog1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6g-l1 {
|
|
regulator-name = "pm_v6g_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xdea80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xdea80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x39e>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldog2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldog2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6g-l2 {
|
|
regulator-name = "pm_v6g_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x39f>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldog3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldog3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6g-l3 {
|
|
regulator-name = "pm_v6g_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x1be>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpi4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpi4";
|
|
|
|
regulator-pm-v8-s4 {
|
|
regulator-name = "pm_v8_s4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x493e0>;
|
|
regulator-max-microvolt = <0xf51e0>;
|
|
qcom,init-voltage = <0xd0020>;
|
|
phandle = <0x3a0>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpi5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpi5";
|
|
|
|
regulator-pm-v8-s5 {
|
|
regulator-name = "pm_v8_s5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x493e0>;
|
|
regulator-max-microvolt = <0xaae60>;
|
|
qcom,init-voltage = <0x7a120>;
|
|
phandle = <0x3a1>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoi1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoi1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
proxy-supply = <0x36>;
|
|
|
|
regulator-pm-v8-l1 {
|
|
regulator-name = "pm_v8_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
qcom,proxy-consumer-enable;
|
|
phandle = <0x36>;
|
|
};
|
|
|
|
regulator-pm-v8-l1-ao {
|
|
regulator-name = "pm_v8_l1_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x2e9>;
|
|
};
|
|
|
|
regulator-pm-v8-l1-so {
|
|
regulator-name = "pm_v8_l1_so";
|
|
qcom,set = <0x02>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x02>;
|
|
qcom,init-enable = <0x00>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoi2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoi2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8-l2 {
|
|
regulator-name = "pm_v8_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a2>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoi3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoi3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
proxy-supply = <0x37>;
|
|
|
|
regulator-pm-v8-l3 {
|
|
regulator-name = "pm_v8_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
qcom,proxy-consumer-enable;
|
|
phandle = <0x37>;
|
|
};
|
|
|
|
regulator-pm-v8-l3-ao {
|
|
regulator-name = "pm_v8_l3_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x2ea>;
|
|
};
|
|
|
|
regulator-pm-v8-l3-so {
|
|
regulator-name = "pm_v8_l3_so";
|
|
qcom,set = <0x02>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x02>;
|
|
qcom,init-enable = <0x00>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l1 {
|
|
regulator-name = "pmr_nalojr_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x61a80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xd0fc0>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a3>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l2 {
|
|
regulator-name = "pmr_nalojr_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xdea80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xdea80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a4>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l3 {
|
|
regulator-name = "pmr_nalojr_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a5>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok4";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l4 {
|
|
regulator-name = "pmr_nalojr_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a6>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok5";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l5 {
|
|
regulator-name = "pmr_nalojr_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xe86c0>;
|
|
regulator-max-microvolt = <0xee480>;
|
|
qcom,init-voltage = <0xe86c0>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a7>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok6";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l6 {
|
|
regulator-name = "pmr_nalojr_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b1980>;
|
|
regulator-max-microvolt = <0x1c61a0>;
|
|
qcom,init-voltage = <0x1b1980>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a8>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok7";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l7 {
|
|
regulator-name = "pmr_nalojr_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = "", "\f5";
|
|
regulator-max-microvolt = "", "\f5";
|
|
qcom,init-voltage = "", "\f5";
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3a9>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010m-l1 {
|
|
regulator-name = "pm8010m_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10d880>;
|
|
regulator-max-microvolt = <0x10d880>;
|
|
qcom,init-voltage = <0x10d880>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3aa>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010m-l2 {
|
|
regulator-name = "pm8010m_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x101d00>;
|
|
regulator-max-microvolt = <0x101d00>;
|
|
qcom,init-voltage = <0x101d00>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3ab>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom3";
|
|
|
|
regulator-pm8010m-l3 {
|
|
regulator-name = "pm8010m_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x3ac>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom4";
|
|
|
|
regulator-pm8010m-l4 {
|
|
regulator-name = "pm8010m_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x3ad>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom5";
|
|
|
|
regulator-pm8010m-l5 {
|
|
regulator-name = "pm8010m_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
phandle = <0x3ae>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom6";
|
|
|
|
regulator-pm8010m-l6 {
|
|
regulator-name = "pm8010m_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x3af>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom7";
|
|
|
|
regulator-pm8010m-l7 {
|
|
regulator-name = "pm8010m_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2d2a80>;
|
|
regulator-max-microvolt = <0x2d2a80>;
|
|
qcom,init-voltage = <0x2d2a80>;
|
|
phandle = <0x3b0>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010n-l1 {
|
|
regulator-name = "pm8010n_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10d880>;
|
|
regulator-max-microvolt = <0x10d880>;
|
|
qcom,init-voltage = <0x10d880>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3b1>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010n-l2 {
|
|
regulator-name = "pm8010n_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x101d00>;
|
|
regulator-max-microvolt = <0x101d00>;
|
|
qcom,init-voltage = <0x101d00>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3b2>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon3";
|
|
|
|
regulator-pm8010n-l3 {
|
|
regulator-name = "pm8010n_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
phandle = <0x157>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon4";
|
|
|
|
regulator-pm8010n-l4 {
|
|
regulator-name = "pm8010n_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
phandle = <0x3b3>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon5";
|
|
|
|
regulator-pm8010n-l5 {
|
|
regulator-name = "pm8010n_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x3b4>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon6";
|
|
|
|
regulator-pm8010n-l6 {
|
|
regulator-name = "pm8010n_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x3b5>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon7";
|
|
|
|
regulator-pm8010n-l7 {
|
|
regulator-name = "pm8010n_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x326a40>;
|
|
regulator-max-microvolt = <0x326a40>;
|
|
qcom,init-voltage = <0x326a40>;
|
|
phandle = <0x3b6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rsc@add9000 {
|
|
label = "cam_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xadd4000 0x1000 0xadd5000 0x1000 0xadd6000 0x1000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <0x03>;
|
|
qcom,hw-channel;
|
|
interrupts = <0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04>;
|
|
clocks = <0x38 0x3d>;
|
|
phandle = <0x3b7>;
|
|
|
|
drv@0 {
|
|
qcom,drv-id = <0x00>;
|
|
qcom,tcs-offset = <0x520>;
|
|
phandle = <0x3b8>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
channel@1 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,no-amc;
|
|
phandle = <0x29>;
|
|
};
|
|
};
|
|
|
|
drv@1 {
|
|
qcom,drv-id = <0x01>;
|
|
qcom,tcs-offset = <0x520>;
|
|
phandle = <0x3b9>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
channel@1 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,no-amc;
|
|
phandle = <0x2a>;
|
|
};
|
|
};
|
|
|
|
drv@2 {
|
|
qcom,drv-id = <0x02>;
|
|
qcom,tcs-offset = <0x520>;
|
|
phandle = <0x3ba>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
channel@1 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,no-amc;
|
|
phandle = <0x2b>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <0x01>;
|
|
interrupts = <0x00 0x81 0x04>;
|
|
clocks = <0x39 0x46>;
|
|
phandle = <0x3bb>;
|
|
|
|
drv@0 {
|
|
qcom,drv-id = <0x00>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
phandle = <0x3bc>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,tcs-wait = <0x01>;
|
|
phandle = <0x28>;
|
|
};
|
|
};
|
|
};
|
|
|
|
crm@add7000 {
|
|
label = "cam_crm";
|
|
compatible = "qcom,cam-crm";
|
|
reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000 0xadd9000 0x800>;
|
|
reg-names = "base", "crm_b", "crm_c", "crm_v";
|
|
interrupts = <0x00 0x79 0x01>;
|
|
interrupt-names = "cam_crm";
|
|
clocks = <0x38 0x3d>;
|
|
qcom,hw-drv-ids = <0x00 0x01 0x02>;
|
|
qcom,sw-drv-ids = <0x00>;
|
|
phandle = <0x3bd>;
|
|
};
|
|
|
|
crm@1d01000 {
|
|
label = "pcie_crm";
|
|
compatible = "qcom,pcie-crm";
|
|
reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000 0x1d04000 0x800>;
|
|
reg-names = "base", "crm_b", "crm_c", "crm_v";
|
|
interrupts = <0x00 0xf8 0x01>;
|
|
interrupt-names = "pcie_crm";
|
|
clocks = <0x3a>;
|
|
qcom,hw-drv-ids = <0x00 0x01>;
|
|
qcom,sw-drv-ids = <0x00>;
|
|
phandle = <0x3be>;
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
qcom,msm-imem@14680000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x14680000 0x1000>;
|
|
ranges = <0x00 0x14680000 0x1000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x08>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x04>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0x0c>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
pil@6dc {
|
|
compatible = "qcom,msm-imem-pil-disable-timeout";
|
|
reg = <0x6dc 0x04>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
|
|
modem_dsm@c98 {
|
|
compatible = "qcom,msm-imem-mss-dsm";
|
|
reg = <0xc98 0x10>;
|
|
};
|
|
|
|
sys_dbg@af8 {
|
|
compatible = "qcom,msm-imem-gpu-dump-skip";
|
|
reg = <0xb0c 0x04>;
|
|
};
|
|
};
|
|
|
|
remoteproc-spss@1880000 {
|
|
compatible = "qcom,pineapple-spss-pas";
|
|
ranges;
|
|
reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1881100 0x04 0x1882014 0x04>;
|
|
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err", "rmb_general_purpose", "rmb_err_spare2";
|
|
interrupts = <0x00 0x160 0x01>;
|
|
cx-supply = <0x30>;
|
|
cx-uV-uA = <0x180 0x186a0>;
|
|
clocks = <0x2d 0x00>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
status = "ok";
|
|
memory-region = <0x3b>;
|
|
qcom,signal-aop;
|
|
qcom,qmp = <0x3c>;
|
|
qcom,spss-scsr-bits = <0x18 0x19>;
|
|
qcom,extra-size = <0x1000>;
|
|
interconnects = <0x3d 0x29 0x3e 0x200>;
|
|
interconnect-names = "crypto_ddr";
|
|
phandle = <0x40>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x08>;
|
|
mboxes = <0x3f 0x10 0x00>;
|
|
mbox-names = "spss_spss";
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x10 0x00 0x01>;
|
|
reg = <0x1885008 0x08 0x1885010 0x04>;
|
|
reg-names = "qcom,spss-addr", "qcom,spss-size";
|
|
label = "spss";
|
|
qcom,glink-label = "spss";
|
|
};
|
|
};
|
|
|
|
qcom,spcom {
|
|
compatible = "qcom,spcom";
|
|
qcom,rproc-handle = <0x40>;
|
|
qcom,boot-enabled;
|
|
qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
|
|
qcom,spcom-sp2soc-rmb-reg-addr = <0x1881020>;
|
|
qcom,spcom-sp2soc-rmb-initdone-bit = <0x18>;
|
|
qcom,spcom-sp2soc-rmb-pbldone-bit = <0x19>;
|
|
qcom,spcom-soc2sp-rmb-reg-addr = <0x1881030>;
|
|
qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0x00>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,spss_utils {
|
|
compatible = "qcom,spss-utils";
|
|
qcom,rproc-handle = <0x40>;
|
|
qcom,spss-fuse1-addr = <0x221c8214>;
|
|
qcom,spss-fuse1-bit = <0x08>;
|
|
qcom,spss-fuse2-addr = <0x221c8214>;
|
|
qcom,spss-fuse2-bit = <0x07>;
|
|
qcom,spss-dev-firmware-name = "spss1d.mdt";
|
|
qcom,spss-test-firmware-name = "spss1t.mdt";
|
|
qcom,spss-prod-firmware-name = "spss1p.mdt";
|
|
qcom,spss-debug-reg-addr = <0x1886020>;
|
|
qcom,spss-debug-reg-addr1 = <0x1888020>;
|
|
qcom,spss-debug-reg-addr3 = <0x188c020>;
|
|
qcom,spss-emul-type-reg-addr = <0x1fc8004>;
|
|
pil-mem = <0x3b>;
|
|
qcom,pil-size = <0xf0000>;
|
|
status = "ok";
|
|
phandle = <0x3bf>;
|
|
};
|
|
|
|
cluster-device {
|
|
compatible = "qcom,lpm-cluster-dev";
|
|
power-domains = <0x21>;
|
|
};
|
|
|
|
qcom,memshare {
|
|
compatible = "qcom,memshare";
|
|
|
|
qcom,client_1 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x00>;
|
|
qcom,client-id = <0x00>;
|
|
qcom,allocate-boot-time;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_2 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x00>;
|
|
qcom,client-id = <0x02>;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_3 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x500000>;
|
|
qcom,client-id = <0x01>;
|
|
qcom,allocate-on-request;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_4 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x1000000>;
|
|
qcom,client-id = <0x05>;
|
|
qcom,allocate-on-request;
|
|
qcom,shared;
|
|
memory-region = <0x41>;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_5 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x400000>;
|
|
qcom,client-id = <0x06>;
|
|
qcom,allocate-on-request;
|
|
qcom,shared;
|
|
label = "modem";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
|
|
xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x493e000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x3c0>;
|
|
};
|
|
|
|
sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x7d00>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x42>;
|
|
};
|
|
|
|
pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x3a>;
|
|
};
|
|
|
|
pcie_1_phy_aux_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "pcie_1_phy_aux_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x45>;
|
|
};
|
|
|
|
pcie_1_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x46>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x47>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x48>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x49>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x4a>;
|
|
};
|
|
};
|
|
|
|
cpuss-sleep-stats@17800054 {
|
|
compatible = "qcom,cpuss-sleep-stats";
|
|
reg = <0x17800054 0x04 0x17810054 0x04 0x17820054 0x04 0x17830054 0x04 0x17840054 0x04 0x17850054 0x04 0x17860054 0x04 0x17870054 0x04 0x178a0098 0x04 0x178c0000 0x10000>;
|
|
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
|
|
num-cpus = <0x08>;
|
|
};
|
|
|
|
sram@c3f0000 {
|
|
compatible = "qcom,rpmh-stats-v4";
|
|
reg = <0xc3f0000 0x400>;
|
|
qcom,qmp = <0x3c>;
|
|
ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss";
|
|
};
|
|
|
|
syscon@adda000 {
|
|
compatible = "syscon";
|
|
reg = <0xadda000 0x2000>;
|
|
phandle = <0x43>;
|
|
};
|
|
|
|
clock-controller@ade0000 {
|
|
compatible = "qcom,pineapple-camcc-v2", "syscon";
|
|
reg = <0xade0000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <0x31>;
|
|
vdd_mxa-supply = <0x33>;
|
|
vdd_mxc-supply = <0x34>;
|
|
clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0x05>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
|
|
qcom,cam_crm-crmc = <0x43>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x38>;
|
|
};
|
|
|
|
clock-controller@af00000 {
|
|
compatible = "qcom,pineapple-dispcc", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <0x31>;
|
|
vdd_mxa-supply = <0x33>;
|
|
clocks = <0x2d 0x00 0x42 0x2c 0x11>;
|
|
clock-names = "bi_tcxo", "sleep_clk", "iface";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x39>;
|
|
};
|
|
|
|
clock-controller@100000 {
|
|
compatible = "qcom,pineapple-gcc", "syscon";
|
|
reg = <0x100000 0x1f4200>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <0x30>;
|
|
vdd_mxa-supply = <0x33>;
|
|
vdd_cx_ao-supply = <0x44>;
|
|
clocks = <0x2d 0x00 0x2d 0x01 0x3a 0x45 0x46 0x42 0x47 0x48 0x49 0x4a>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "pcie_0_pipe_clk", "pcie_1_phy_aux_clk", "pcie_1_pipe_clk", "sleep_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x2c>;
|
|
};
|
|
|
|
clock-controller@3d90000 {
|
|
compatible = "qcom,pineapple-gpucc", "syscon";
|
|
reg = <0x3d90000 0x9800>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <0x30>;
|
|
vdd_mx-supply = <0x33>;
|
|
vdd_mxc-supply = <0x34>;
|
|
clocks = <0x2d 0x00 0x2c 0x23 0x2c 0x24>;
|
|
clock-names = "bi_tcxo", "gpll0_out_main", "gpll0_out_main_div";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x4b>;
|
|
};
|
|
|
|
clock-controller@1f40000 {
|
|
compatible = "qcom,pineapple-tcsrcc", "syscon";
|
|
reg = <0x1f40000 0xc0000>;
|
|
reg-name = "cc_base";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x53>;
|
|
};
|
|
|
|
clock-controller@aaf0000 {
|
|
compatible = "qcom,pineapple-videocc-v2", "syscon";
|
|
reg = <0xaaf0000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <0x31>;
|
|
vdd_mxc-supply = <0x34>;
|
|
clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0xbb>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x4c>;
|
|
};
|
|
|
|
syscon@17a80000 {
|
|
compatible = "syscon";
|
|
reg = <0x17a80000 0x21000>;
|
|
phandle = <0x4d>;
|
|
};
|
|
|
|
syscon@240ba000 {
|
|
compatible = "syscon";
|
|
reg = <0x240ba000 0x54>;
|
|
phandle = <0x4e>;
|
|
};
|
|
|
|
qcom,cc-debug {
|
|
compatible = "qcom,pineapple-debugcc";
|
|
qcom,gcc = <0x2c>;
|
|
qcom,gpucc = <0x4b>;
|
|
qcom,videocc = <0x4c>;
|
|
qcom,dispcc = <0x39>;
|
|
qcom,camcc = <0x38>;
|
|
qcom,apsscc = <0x4d>;
|
|
qcom,mccc = <0x4e>;
|
|
clock-names = "xo_clk_src";
|
|
clocks = <0x2d 0x00>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x3c1>;
|
|
};
|
|
|
|
qcom,cpufreq-hw {
|
|
compatible = "qcom,cpufreq-epss";
|
|
reg = <0x17d91000 0x1000 0x17d92000 0x1000 0x17d93000 0x1000 0x17d94000 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1", "freq-domain2", "freq-domain3";
|
|
clocks = <0x2d 0x00 0x2c 0x1a>;
|
|
clock-names = "xo", "alternate";
|
|
interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x13 0x04 0x00 0x2e2 0x04>;
|
|
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int", "dcvsh3_int";
|
|
#freq-domain-cells = <0x01>;
|
|
phandle = <0x06>;
|
|
};
|
|
|
|
qcom,cpufreq-hw-debug {
|
|
compatible = "qcom,cpufreq-hw-epss-debug";
|
|
qcom,freq-hw-domain = <0x06 0x00 0x06 0x01 0x06 0x02 0x06 0x03>;
|
|
};
|
|
|
|
sdhc2-opp-table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0x52>;
|
|
|
|
opp-100000000 {
|
|
opp-hz = <0x00 0x5f5e100>;
|
|
opp-peak-kBps = <0x27100 0x186a0>;
|
|
opp-avg-kBps = <0xc350 0x00>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = <0x00 0xc0a4680>;
|
|
opp-peak-kBps = <0x30d40 0x1d4c0>;
|
|
opp-avg-kBps = <0x19640 0x00>;
|
|
};
|
|
};
|
|
|
|
sdhci@8804000 {
|
|
status = "disabled";
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x8804000 0x1000>;
|
|
reg-names = "hc";
|
|
interrupts = <0x00 0xcf 0x04 0x00 0xdf 0x04>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
bus-width = <0x04>;
|
|
no-sdio;
|
|
no-mmc;
|
|
qcom,restore-after-cx-collapse;
|
|
clocks = <0x2c 0x97 0x2c 0x98>;
|
|
clock-names = "iface", "core";
|
|
qcom,dll-hsr-list = <0x7442c 0x00 0x10 0x90106c0 0x80040868>;
|
|
iommus = <0x4f 0x540 0x00>;
|
|
dma-coherent;
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
interconnects = <0x3d 0x33 0x3e 0x200 0x50 0x03 0x51 0x223>;
|
|
interconnect-names = "sdhc-ddr", "cpu-sdhc";
|
|
operating-points-v2 = <0x52>;
|
|
phandle = <0x3c2>;
|
|
|
|
qos0 {
|
|
mask = <0xf0>;
|
|
vote = <0x2c>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x0f>;
|
|
vote = <0x2c>;
|
|
};
|
|
};
|
|
|
|
ufsphy_mem@1d80000 {
|
|
reg = <0x1d80000 0x2000>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0x00>;
|
|
lanes-per-direction = <0x02>;
|
|
clock-names = "ref_clk_src", "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
|
|
clocks = <0x2d 0x1b 0x2c 0xa4 0x53 0x02 0x2c 0xa8 0x2c 0xaa 0x2c 0xac 0x2c 0xa7 0x2c 0xa9 0x2c 0xab>;
|
|
resets = <0x54 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x55>;
|
|
};
|
|
|
|
shared_ice {
|
|
phandle = <0x57>;
|
|
|
|
alg1 {
|
|
alg-name = "alg1";
|
|
rx-alloc-percent = <0x3c>;
|
|
status = "disabled";
|
|
};
|
|
|
|
alg2 {
|
|
alg-name = "alg2";
|
|
status = "disabled";
|
|
};
|
|
|
|
alg3 {
|
|
alg-name = "alg3";
|
|
num-core = <0x1c 0x1c 0x0f 0x0d>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
|
|
ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000 0x1d88000 0x8000 0x1d90000 0x9000 0x1da5000 0x2000 0x1da4000 0x10>;
|
|
reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm", "mcq_sqd", "mcq_vs";
|
|
interrupts = <0x00 0x109 0x04>;
|
|
phys = <0x55>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <0x01>;
|
|
qcom,prime-mask = <0x80>;
|
|
qcom,silver-mask = <0x0f>;
|
|
lanes-per-direction = <0x02>;
|
|
dev-ref-clk-freq = <0x00>;
|
|
clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk";
|
|
clocks = <0x2c 0x9e 0x2c 0x01 0x2c 0x9d 0x2c 0xad 0x2c 0xa1 0x2d 0x04 0x2c 0xab 0x2c 0xa7 0x2c 0xa9>;
|
|
freq-table-hz = <0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x5f5e100 0x18054ac0 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
interconnects = <0x56 0x35 0x3e 0x200 0x50 0x03 0x51 0x229>;
|
|
interconnect-names = "ufs-ddr", "cpu-ufs";
|
|
qcom,ufs-bus-bw,name = "ufshc_mem";
|
|
qcom,ufs-bus-bw,num-cases = <0x1e>;
|
|
qcom,ufs-bus-bw,num-paths = <0x02>;
|
|
qcom,ufs-bus-bw,vectors-KBps = <0x00 0x00 0x00 0x00 0x39a 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x7340 0x00 0x3e8 0x00 0x1f334 0x00 0x3e8 0x00 0x3e667 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x3e667 0x00 0x3e8 0x00 0x7cccd 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x00 0x2c7b80 0x00 0x64000 0x00 0x247ae 0x00 0x3e8 0x00 0x48ccd 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x48ccd 0x00 0x3e8 0x00 0x9199a 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x64000 0x2c7b80 0x00 0x64000 0x64000 0x591000 0x00 0xc8000 0x00 0x591000 0x00 0xc8000 0x00 0x74a000 0x00 0xc8000 0x00>;
|
|
qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "HS_RA_G5_L2", "HS_RB_G5_L2", "MAX";
|
|
iommus = <0x4f 0x60 0x00>;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-dma-addr-pool = <0x1000 0xfffff000>;
|
|
qcom,iommu-msi-size = <0x1000>;
|
|
shared-ice-cfg = <0x57>;
|
|
dma-coherent;
|
|
qcom,bypass-pbl-rst-wa;
|
|
msi-parent = <0x58 0x60>;
|
|
qcom,broken-ahit-wa;
|
|
status = "disabled";
|
|
phandle = <0x54>;
|
|
|
|
qos0 {
|
|
mask = <0xfc>;
|
|
vote = <0x2c>;
|
|
perf;
|
|
cpu_freq_vote = <0x02 0x05 0x07>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x03>;
|
|
vote = <0x2c>;
|
|
cpu_freq_vote = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x00 0x400000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x01>;
|
|
};
|
|
|
|
thermal-zones {
|
|
phandle = <0x3c3>;
|
|
|
|
pa {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pa1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x01>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
bcl_warn {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x1f>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdr0_pa {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x48>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdr0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x26>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x2e>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x2f>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x30>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x31>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw_pa1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x1a>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw_pa2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x1b>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw_pa3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x1c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw_ific0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x32>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x40>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x41>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x42>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x43>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm4 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x44>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm5 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x45>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm6 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x46>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
epm7 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x47>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdr_mmw_therm {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x1d>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sub1_modem_cfg {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x33>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sub1_lte_cc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x34>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sub1_mcg_fr1_cc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x35>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sub1_mcg_fr2_cc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x36>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sub1_scg_fr1_cc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x37>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sub1_scg_fr2_cc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x38>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pa-therm2-sys3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x4c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x01>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x02>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x03>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x04>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-2-0-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x05>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu2-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x5b>;
|
|
};
|
|
|
|
cpu2-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x5d>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu200_cdev {
|
|
trip = <0x5b>;
|
|
cooling-device = <0x5c 0x01 0x01>;
|
|
};
|
|
|
|
cpu200_cdev1 {
|
|
trip = <0x5d>;
|
|
cooling-device = <0x5e 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-2-0-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x06>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu2-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x5f>;
|
|
};
|
|
|
|
cpu2-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x60>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu201_cdev {
|
|
trip = <0x5f>;
|
|
cooling-device = <0x5c 0x01 0x01>;
|
|
};
|
|
|
|
cpu201_cdev1 {
|
|
trip = <0x60>;
|
|
cooling-device = <0x5e 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-2-1-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x07>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu3-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x61>;
|
|
};
|
|
|
|
cpu3-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu210_cdev {
|
|
trip = <0x61>;
|
|
cooling-device = <0x62 0x01 0x01>;
|
|
};
|
|
|
|
cpu210_cdev1 {
|
|
trip = <0x63>;
|
|
cooling-device = <0x64 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-2-1-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x08>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu3-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x65>;
|
|
};
|
|
|
|
cpu3-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x66>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu211_cdev {
|
|
trip = <0x65>;
|
|
cooling-device = <0x62 0x01 0x01>;
|
|
};
|
|
|
|
cpu211_cdev1 {
|
|
trip = <0x66>;
|
|
cooling-device = <0x64 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-2-2-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x09>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x67>;
|
|
};
|
|
|
|
cpu4-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x69>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu220_cdev {
|
|
trip = <0x67>;
|
|
cooling-device = <0x68 0x01 0x01>;
|
|
};
|
|
|
|
cpu220_cdev1 {
|
|
trip = <0x69>;
|
|
cooling-device = <0x6a 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-2-2-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x0a>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x6b>;
|
|
};
|
|
|
|
cpu4-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x6c>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu221_cdev {
|
|
trip = <0x6b>;
|
|
cooling-device = <0x68 0x01 0x01>;
|
|
};
|
|
|
|
cpu221_cdev1 {
|
|
trip = <0x6c>;
|
|
cooling-device = <0x6a 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x0b>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x6d>;
|
|
};
|
|
|
|
cpu5-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x6f>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu100_cdev {
|
|
trip = <0x6d>;
|
|
cooling-device = <0x6e 0x01 0x01>;
|
|
};
|
|
|
|
cpu100_cdev1 {
|
|
trip = <0x6f>;
|
|
cooling-device = <0x70 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x0c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x71>;
|
|
};
|
|
|
|
cpu5-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x72>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu101_cdev {
|
|
trip = <0x71>;
|
|
cooling-device = <0x6e 0x01 0x01>;
|
|
};
|
|
|
|
cpu101_cdev1 {
|
|
trip = <0x72>;
|
|
cooling-device = <0x70 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x0d>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x73>;
|
|
};
|
|
|
|
cpu6-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x75>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu110_cdev {
|
|
trip = <0x73>;
|
|
cooling-device = <0x74 0x01 0x01>;
|
|
};
|
|
|
|
cpu110_cdev1 {
|
|
trip = <0x75>;
|
|
cooling-device = <0x76 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x0e>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x77>;
|
|
};
|
|
|
|
cpu6-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x78>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu111_cdev {
|
|
trip = <0x77>;
|
|
cooling-device = <0x74 0x01 0x01>;
|
|
};
|
|
|
|
cpu111_cdev1 {
|
|
trip = <0x78>;
|
|
cooling-device = <0x76 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x01>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x7a>;
|
|
};
|
|
|
|
cpu7-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x7c>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu120_cdev {
|
|
trip = <0x7a>;
|
|
cooling-device = <0x7b 0x01 0x01>;
|
|
};
|
|
|
|
cpu120_cdev1 {
|
|
trip = <0x7c>;
|
|
cooling-device = <0x7d 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-1 {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x02>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7-mon-trip {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x80>;
|
|
};
|
|
|
|
cpu7-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x7e>;
|
|
};
|
|
|
|
cpu7-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x7f>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu121_cdev {
|
|
trip = <0x7e>;
|
|
cooling-device = <0x7b 0x01 0x01>;
|
|
};
|
|
|
|
cpu121_cdev1 {
|
|
trip = <0x7f>;
|
|
cooling-device = <0x7d 0x01 0x01>;
|
|
};
|
|
|
|
cpu121_cdev2 {
|
|
trip = <0x80>;
|
|
cooling-device = <0x20 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-2 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x03>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7-emerg2-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x81>;
|
|
};
|
|
|
|
cpu7-emerg2-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x82>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu122_cdev {
|
|
trip = <0x81>;
|
|
cooling-device = <0x7b 0x01 0x01>;
|
|
};
|
|
|
|
cpu122_cdev1 {
|
|
trip = <0x82>;
|
|
cooling-device = <0x7d 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x04>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu0-emerg-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x83>;
|
|
};
|
|
|
|
cpu0-emerg1-cfg {
|
|
temperature = <0x1b580>;
|
|
hysteresis = <0x2ee0>;
|
|
type = "passive";
|
|
phandle = <0x85>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu000_cdev {
|
|
trip = <0x83>;
|
|
cooling-device = <0x84 0x01 0x01>;
|
|
};
|
|
|
|
cpu000_cdev1 {
|
|
trip = <0x85>;
|
|
cooling-device = <0x86 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x05>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu1-emerg-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x87>;
|
|
};
|
|
|
|
cpu1-emerg1-cfg {
|
|
temperature = <0x1b580>;
|
|
hysteresis = <0x2ee0>;
|
|
type = "passive";
|
|
phandle = <0x89>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu010_cdev {
|
|
trip = <0x87>;
|
|
cooling-device = <0x88 0x01 0x01>;
|
|
};
|
|
|
|
cpu010_cdev1 {
|
|
trip = <0x89>;
|
|
cooling-device = <0x8a 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x06>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x07>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x08>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x09>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-2 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x0a>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-3 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x0b>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
video {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x0c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x0d>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
ddr0-config {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x8b>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gold_cdev0 {
|
|
trip = <0x8b>;
|
|
cooling-device = <0x1b 0xffffffff 0xffffffff>;
|
|
};
|
|
|
|
gold_cdev1 {
|
|
trip = <0x8b>;
|
|
cooling-device = <0x1c 0xffffffff 0xffffffff>;
|
|
};
|
|
|
|
gold_cdev2 {
|
|
trip = <0x8b>;
|
|
cooling-device = <0x1d 0xffffffff 0xffffffff>;
|
|
};
|
|
|
|
gold_plus_cdev {
|
|
trip = <0x8b>;
|
|
cooling-device = <0x20 0xffffffff 0xffffffff>;
|
|
};
|
|
|
|
ddr_cdev {
|
|
trip = <0x8b>;
|
|
cooling-device = <0x8c 0x05 0x05>;
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x0e>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x79 0x0f>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-0 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x01>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x8e>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu0_cdev {
|
|
trip = <0x8e>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-1 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x02>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x90>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu1_cdev {
|
|
trip = <0x90>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-2 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x03>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x91>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu2_cdev {
|
|
trip = <0x91>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-3 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x04>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x92>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu3_cdev {
|
|
trip = <0x92>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-4 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x05>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x93>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu4_cdev {
|
|
trip = <0x93>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-5 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x06>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x94>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu5_cdev {
|
|
trip = <0x94>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-6 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x07>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x95>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu6_cdev {
|
|
trip = <0x95>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-7 {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x08>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu7_cdev {
|
|
trip = <0x96>;
|
|
cooling-device = <0x8f 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x09>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss0-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
mdmss0-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0x9b>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0x97>;
|
|
cooling-device = <0x98 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0x97>;
|
|
cooling-device = <0x99 0x0c 0x0c>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0x97>;
|
|
cooling-device = <0x9a 0x08 0x08>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0x9b>;
|
|
cooling-device = <0x98 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0x9b>;
|
|
cooling-device = <0x9a 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x0a>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss1-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
mdmss1-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0x9d>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0x9c>;
|
|
cooling-device = <0x98 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0x9c>;
|
|
cooling-device = <0x99 0x0c 0x0c>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0x9c>;
|
|
cooling-device = <0x9a 0x08 0x08>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0x9d>;
|
|
cooling-device = <0x98 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0x9d>;
|
|
cooling-device = <0x9a 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x0b>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss2-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
mdmss2-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0x9e>;
|
|
cooling-device = <0x98 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0x9e>;
|
|
cooling-device = <0x99 0x0c 0x0c>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0x9e>;
|
|
cooling-device = <0x9a 0x08 0x08>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0x9f>;
|
|
cooling-device = <0x98 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0x9f>;
|
|
cooling-device = <0x9a 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x8d 0x0c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss3-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xa0>;
|
|
};
|
|
|
|
mdmss3-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0xa0>;
|
|
cooling-device = <0x98 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0xa0>;
|
|
cooling-device = <0x99 0x0c 0x0c>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0xa0>;
|
|
cooling-device = <0x9a 0x08 0x08>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0xa1>;
|
|
cooling-device = <0x98 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0xa1>;
|
|
cooling-device = <0x9a 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,spmi@c42d000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>;
|
|
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
|
|
interrupts-extended = <0x2e 0x01 0x04>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x04>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
cell-index = <0x00>;
|
|
qcom,channel = <0x00>;
|
|
qcom,ee = <0x00>;
|
|
qcom,bus-id = <0x00>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
qcom,spmi@c432000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc432000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4d0000 0x10000>;
|
|
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
|
|
interrupts-extended = <0x2e 0x03 0x04>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x04>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
cell-index = <0x00>;
|
|
qcom,channel = <0x00>;
|
|
qcom,ee = <0x00>;
|
|
qcom,bus-id = <0x01>;
|
|
depends-on-supply = <0xa2>;
|
|
status = "disabled";
|
|
phandle = <0xce>;
|
|
};
|
|
|
|
qcom,spmi-debug@10b14000 {
|
|
compatible = "qcom,spmi-pmic-arb-debug";
|
|
reg = <0x10b14000 0x60 0x221c8784 0x04>;
|
|
reg-names = "core", "fuse";
|
|
clocks = <0x3c>;
|
|
clock-names = "core_clk";
|
|
qcom,fuse-enable-bit = <0x12>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
depends-on-supply = <0xa2>;
|
|
phandle = <0x3c4>;
|
|
|
|
qcom,pmk8550-debug@0 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x00 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8550-debug@1 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x01 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8550vs-debug@2 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x02 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8550vs-debug@3 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x03 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8550vs-debug@4 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x04 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8550vs-debug@6 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x06 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8550ve-debug@8 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x08 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pmr735d-debug@a {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0a 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8010-debug@c {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0c 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
qcom,pm8010-debug@d {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0d 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
};
|
|
|
|
syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <0xa3 0x00 0x1000>;
|
|
#hwlock-cells = <0x01>;
|
|
phandle = <0x02>;
|
|
};
|
|
|
|
syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
phandle = <0x03>;
|
|
};
|
|
|
|
tz-log@14680720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x14680720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
tmecrashdump-address-offset = <0x81ca0000>;
|
|
phandle = <0x3c5>;
|
|
};
|
|
|
|
qseecom@c1700000 {
|
|
compatible = "qcom,qseecom";
|
|
memory-region = <0xa4>;
|
|
qseecom_mem = <0xa4>;
|
|
qseecom_ta_mem = <0xa5>;
|
|
qcom,no-user-contig-mem-support;
|
|
qcom,hlos-num-ce-hw-instances = <0x01>;
|
|
qcom,hlos-ce-hw-instance = <0x00>;
|
|
qcom,qsee-ce-hw-instance = <0x00>;
|
|
qcom,disk-encrypt-pipe-pair = <0x02>;
|
|
qcom,no-clock-support;
|
|
qcom,appsbl-qseecom-support;
|
|
qcom,commonlib64-loaded-by-uefi;
|
|
qcom,qsee-reentrancy-support = <0x02>;
|
|
phandle = <0x3c6>;
|
|
};
|
|
|
|
qcedev@1de0000 {
|
|
compatible = "qcom,qcedev";
|
|
reg = <0x1de0000 0x20000 0x1dc4000 0x28000>;
|
|
reg-names = "crypto-base", "crypto-bam-base";
|
|
interrupts = <0x00 0x110 0x04>;
|
|
qcom,bam-pipe-pair = <0x02>;
|
|
qcom,offload-ops-support;
|
|
qcom,bam-pipe-offload-cpb-hlos = <0x01>;
|
|
qcom,bam-pipe-offload-hlos-cpb = <0x03>;
|
|
qcom,bam-pipe-offload-hlos-cpb-1 = <0x08>;
|
|
qcom,bam-pipe-offload-hlos-hlos = <0x04>;
|
|
qcom,bam-pipe-offload-hlos-hlos-1 = <0x09>;
|
|
qcom,ce-hw-instance = <0x00>;
|
|
qcom,ce-device = <0x00>;
|
|
qcom,ce-hw-shared;
|
|
qcom,bam-ee = <0x00>;
|
|
qcom,smmu-s1-enable;
|
|
qcom,no-clock-support;
|
|
interconnect-names = "data_path";
|
|
interconnects = <0x3d 0x29 0x3e 0x200>;
|
|
iommus = <0x4f 0x480 0x00 0x4f 0x481 0x00>;
|
|
qcom,iommu-dma = "atomic";
|
|
dma-coherent;
|
|
phandle = <0x3c7>;
|
|
|
|
qcom_cedev_ns_cb {
|
|
compatible = "qcom,qcedev,context-bank";
|
|
label = "ns_context";
|
|
iommus = <0x4f 0x481 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom_cedev_s_cb {
|
|
compatible = "qcom,qcedev,context-bank";
|
|
label = "secure_context";
|
|
iommus = <0x4f 0x483 0x00>;
|
|
qcom,iommu-vmid = <0x09>;
|
|
qcom,secure-context-bank;
|
|
dma-noncoherent;
|
|
};
|
|
};
|
|
|
|
qrng@10c3000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0x10c3000 0x1000>;
|
|
qcom,no-qrng-config;
|
|
qcom,no-clock-support;
|
|
phandle = <0x3c8>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <0x8000>;
|
|
};
|
|
|
|
cache-controller@25000000 {
|
|
compatible = "qcom,pineapple-llcc", "qcom,llcc-v50";
|
|
reg = <0x25000000 0x800000 0x25800000 0x200000>;
|
|
reg-names = "llcc_base", "llcc_broadcast_base";
|
|
interrupts = <0x00 0x10a 0x04>;
|
|
cap-based-alloc-and-pwr-collapse;
|
|
|
|
llcc-perfmon {
|
|
compatible = "qcom,llcc-perfmon";
|
|
clocks = <0x3c 0x00>;
|
|
clock-names = "qdss_clk";
|
|
};
|
|
};
|
|
|
|
qcom,msm-eud@88e0000 {
|
|
compatible = "qcom,msm-eud";
|
|
interrupt-names = "eud_irq";
|
|
interrupt-parent = <0x2e>;
|
|
interrupts = <0x0b 0x04>;
|
|
reg = <0x88e0000 0x2000 0x88e2000 0x1000>;
|
|
reg-names = "eud_base", "eud_mode_mgr2";
|
|
qcom,secure-eud-en;
|
|
qcom,eud-utmi-delay = [00 ff];
|
|
status = "ok";
|
|
phandle = <0x1bb>;
|
|
};
|
|
|
|
qcom,ipcc@406000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0x406000 0x1000>;
|
|
interrupts = <0x00 0xe5 0x04>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
#mbox-cells = <0x02>;
|
|
phandle = <0x3f>;
|
|
};
|
|
|
|
power-controller@c300000 {
|
|
compatible = "qcom,aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x00 0x00 0x01>;
|
|
mboxes = <0x3f 0x00 0x00>;
|
|
#power-domain-cells = <0x01>;
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x3c>;
|
|
};
|
|
|
|
qcom,qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <0x3c>;
|
|
label = "aop";
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x3c9>;
|
|
};
|
|
|
|
qcom,qmp-tme {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,remote-pid = <0x0e>;
|
|
mboxes = <0x3f 0x17 0x00>;
|
|
mbox-names = "tme_qmp";
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x17 0x00 0x01>;
|
|
label = "tme";
|
|
qcom,early-boot;
|
|
priority = <0x00>;
|
|
mbox-desc-offset = <0x00>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
qcom,tmecom-qmp-client {
|
|
compatible = "qcom,tmecom-qmp-client";
|
|
mboxes = <0xa6 0x00>;
|
|
mbox-names = "tmecom";
|
|
label = "tmecom";
|
|
depends-on-supply = <0xa6>;
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1bb 0x1ad>;
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x03 0x02 0x01>;
|
|
mboxes = <0x3f 0x03 0x02>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x02>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xb0>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xaf>;
|
|
};
|
|
|
|
sleepstate-out {
|
|
qcom,entry-name = "sleepstate";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
qcom,sleepstate-in {
|
|
qcom,entry-name = "sleepstate_see";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg2-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x2e5>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg2-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x2e6>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x5e 0x1b0>;
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x06 0x02 0x01>;
|
|
mboxes = <0x3f 0x06 0x02>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x05>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xc0>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xbf>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg5-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x2e7>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg5-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x2e8>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1b3 0x1ac>;
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x02 0x02 0x01>;
|
|
mboxes = <0x3f 0x02 0x02>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x01>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xb9>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xb8>;
|
|
};
|
|
|
|
qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x3ca>;
|
|
};
|
|
|
|
qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x3cb>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <0xa7 0x00>;
|
|
interrupt-parent = <0xa8>;
|
|
interrupts = <0x00 0x00>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-ctrl-cdsp {
|
|
qcom,glinkpkt-edge = "cdsp";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_CTL_CDSP";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_ctrl_cdsp";
|
|
};
|
|
|
|
qcom,glinkpkt-data-cdsp {
|
|
qcom,glinkpkt-edge = "cdsp";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_DATA_CDSP";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_data_cdsp";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
qcom,glinkpkt-qmc-dma {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
|
|
qcom,glinkpkt-dev-name = "qmc_dma";
|
|
qcom,glinkpkt-enable-ch-close;
|
|
};
|
|
|
|
qcom,glinkpkt-qmc-cma {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
|
|
qcom,glinkpkt-dev-name = "qmc_cma";
|
|
qcom,glinkpkt-enable-ch-close;
|
|
};
|
|
|
|
qcom,glinkpkt-xpan_control {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "bt_cp_ctrl";
|
|
qcom,glinkpkt-dev-name = "bt_cp_ctrl";
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
};
|
|
|
|
qcom,qsee_ipc_irq_bridge {
|
|
compatible = "qcom,qsee-ipc-irq-bridge";
|
|
|
|
qcom,qsee-ipc-irq-spss {
|
|
qcom,dev-name = "qsee_ipc_irq_spss";
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x10 0x01 0x01>;
|
|
label = "spss";
|
|
};
|
|
};
|
|
|
|
sys-pm-vx@c320000 {
|
|
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-pineapple";
|
|
reg = <0xc320000 0x400>;
|
|
qcom,qmp = <0x3c>;
|
|
};
|
|
|
|
adsp-sleepmon {
|
|
compatible = "qcom,adsp-sleepmon";
|
|
qcom,rproc-handle = <0xa9>;
|
|
phandle = <0x3cc>;
|
|
};
|
|
|
|
qcom,chd {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "core";
|
|
qcom,chd-percpu-info = <0x19 0x17800058 0x17800060 0x1a 0x17810058 0x17810060 0x1b 0x17820058 0x17820060 0x1c 0x17830058 0x17830060 0x1d 0x17840058 0x17840060 0x1e 0x17850058 0x17850060 0x1f 0x17860058 0x17860060 0x20 0x17870058 0x17870060>;
|
|
};
|
|
|
|
remoteproc-adsp@03000000 {
|
|
compatible = "qcom,pineapple-adsp-pas";
|
|
reg = <0x3000000 0x10000>;
|
|
status = "ok";
|
|
cx-supply = <0xaa>;
|
|
cx-uV-uA = <0x180 0x00>;
|
|
mx-supply = <0xab>;
|
|
mx-uV-uA = <0x180 0x00>;
|
|
reg-names = "cx", "mx";
|
|
clocks = <0x2d 0x00>;
|
|
clock-names = "xo";
|
|
qcom,signal-aop;
|
|
qcom,qmp = <0x3c>;
|
|
interconnects = <0xac 0x2b 0x3e 0x200 0x3d 0x29 0x3e 0x200>;
|
|
interconnect-names = "rproc_ddr", "crypto_ddr";
|
|
memory-region = <0xad 0xae>;
|
|
interrupts-extended = <0x2e 0x06 0x01 0xaf 0x00 0x00 0xaf 0x02 0x00 0xaf 0x01 0x00 0xaf 0x03 0x00>;
|
|
interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack";
|
|
qcom,smem-states = <0xb0 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
phandle = <0xa9>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x02>;
|
|
transport = "smem";
|
|
mboxes = <0x3f 0x03 0x00>;
|
|
mbox-names = "adsp_smem";
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x03 0x00 0x01>;
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
phandle = <0x3cd>;
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,net-id = <0x02>;
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
qcom,no-wake-svc = <0x190>;
|
|
};
|
|
|
|
qcom,pmic_glink_rpmsg {
|
|
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
|
|
};
|
|
|
|
qcom,pmic_glink_log_rpmsg {
|
|
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
|
|
qcom,intents = <0x800 0x05 0xc00 0x03 0x2000 0x01>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 0x40>;
|
|
};
|
|
|
|
qcom,gpr {
|
|
phandle = <0x52c>;
|
|
reg = <0x02>;
|
|
qcom,intents = <0x200 0x14>;
|
|
qcom,glink-channels = "adsp_apps";
|
|
compatible = "qcom,gpr";
|
|
|
|
spf_core {
|
|
reg = <0x03>;
|
|
compatible = "qcom,spf_core";
|
|
};
|
|
|
|
audio-pkt {
|
|
reg = <0x17>;
|
|
qcom,audiopkt-ch-name = "apr_audio_svc";
|
|
compatible = "qcom,audio-pkt";
|
|
};
|
|
|
|
q6prm {
|
|
phandle = <0x52d>;
|
|
reg = <0x07>;
|
|
qcom,sleep-api-supported = <0x01>;
|
|
compatible = "qcom,audio_prm";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc-mss@04080000 {
|
|
compatible = "qcom,pineapple-modem-pas";
|
|
reg = <0x4080000 0x10000>;
|
|
status = "ok";
|
|
clocks = <0x2d 0x00>;
|
|
clock-names = "xo";
|
|
cx-supply = <0x30>;
|
|
cx-uV-uA = <0x180 0x186a0>;
|
|
mx-supply = <0xb1>;
|
|
mx-uV-uA = <0x140 0x186a0>;
|
|
reg-names = "cx", "mx";
|
|
qcom,signal-aop;
|
|
qcom,qmp = <0x3c>;
|
|
interconnects = <0x3e 0x04 0x3e 0x200 0x3d 0x29 0x3e 0x200>;
|
|
interconnect-names = "rproc_ddr", "crypto_ddr";
|
|
memory-region = <0xb2 0xb3 0xb4>;
|
|
mpss_dsm_mem_reg = <0xb5 0xb6 0xb7>;
|
|
interrupts-extended = <0x01 0x00 0x108 0x01 0xb8 0x00 0x00 0xb8 0x02 0x00 0xb8 0x01 0x00 0xb8 0x03 0x00 0xb8 0x07 0x00>;
|
|
interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack", "shutdown-ack";
|
|
qcom,smem-states = <0xb9 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
phandle = <0xe0>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x01>;
|
|
transport = "smem";
|
|
mboxes = <0x3f 0x02 0x00>;
|
|
mbox-names = "mpss_smem";
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x02 0x00 0x01>;
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
};
|
|
|
|
qcom,modem_ds {
|
|
qcom,glink-channels = "DS";
|
|
qcom,intents = <0x4000 0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc-cdsp@32300000 {
|
|
compatible = "qcom,pineapple-cdsp-pas";
|
|
reg = <0x32300000 0x10000>;
|
|
status = "ok";
|
|
cx-supply = <0x30>;
|
|
cx-uV-uA = <0x180 0x186a0>;
|
|
mx-supply = <0x34>;
|
|
mx-uV-uA = <0x180 0x186a0>;
|
|
nsp-supply = <0xba>;
|
|
nsp-uV-uA = <0x180 0x186a0>;
|
|
reg-names = "cx", "mx", "nsp";
|
|
memory-region = <0xbb 0xbc>;
|
|
global-sync-mem-reg = <0xbd>;
|
|
clocks = <0x2d 0x00>;
|
|
clock-names = "xo";
|
|
qcom,signal-aop;
|
|
qcom,qmp = <0x3c>;
|
|
interconnects = <0xbe 0x19 0x3e 0x200 0x3d 0x29 0x3e 0x200>;
|
|
interconnect-names = "rproc_ddr", "crypto_ddr";
|
|
interrupts-extended = <0x01 0x00 0x242 0x01 0xbf 0x00 0x00 0xbf 0x02 0x00 0xbf 0x01 0x00 0xbf 0x03 0x00>;
|
|
interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack";
|
|
qcom,smem-states = <0xc0 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
phandle = <0xcc>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x05>;
|
|
transport = "smem";
|
|
mboxes = <0x3f 0x06 0x00>;
|
|
mbox-names = "cdsp_smem";
|
|
interrupt-parent = <0x3f>;
|
|
interrupts = <0x06 0x00 0x01>;
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
};
|
|
|
|
qcom,msm_cdsprm_rpmsg {
|
|
compatible = "qcom,msm-cdsprm-rpmsg";
|
|
qcom,glink-channels = "cdsprmglink-apps-dsp";
|
|
qcom,intents = <0x20 0x0c 0xf00 0x0c>;
|
|
|
|
qcom,msm_cdsp_rm {
|
|
compatible = "qcom,msm-cdsp-rm";
|
|
qcom,qos-cores = <0x00 0x01>;
|
|
qcom,qos-latency-us = <0x46>;
|
|
qcom,qos-maxhold-ms = <0x14>;
|
|
phandle = <0x3ce>;
|
|
};
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 0x40>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gic-interrupt-router {
|
|
compatible = "qcom,gic-intr-routing";
|
|
qcom,gic-class0-cpus = <0x00 0x01>;
|
|
qcom,gic-class1-cpus = <0x02 0x03 0x04 0x05 0x06 0x07>;
|
|
};
|
|
|
|
qcom,secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
qcom,vmid-cp-camera-preview-ro;
|
|
};
|
|
|
|
qcom,mem-buf {
|
|
compatible = "qcom,mem-buf";
|
|
qcom,mem-buf-capabilities = "supplier";
|
|
qcom,vmid = <0x03>;
|
|
};
|
|
|
|
qcom,hdcp {
|
|
compatible = "qcom,hdcp";
|
|
qcom,use-smcinvoke = <0x01>;
|
|
};
|
|
|
|
qcom,mem-buf-msgq {
|
|
compatible = "qcom,mem-buf-msgq";
|
|
};
|
|
|
|
qti,smmu-proxy {
|
|
compatible = "smmu-proxy-sender";
|
|
};
|
|
|
|
tlmm-vm-mem-access {
|
|
compatible = "qcom,tlmm-vm-mem-access";
|
|
qcom,master;
|
|
tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>;
|
|
};
|
|
|
|
tlmm-vm-test {
|
|
compatible = "qcom,tlmm-vm-test";
|
|
qcom,master;
|
|
tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>;
|
|
};
|
|
|
|
cpusys-vm-shmem-access {
|
|
compatible = "qcom,cpusys-vm-shmem-access";
|
|
gunyah-label = <0x05>;
|
|
peer-name = <0x03>;
|
|
shared-buffer = <0xc2>;
|
|
};
|
|
|
|
trust_ui_vm_vblk0_ring {
|
|
size = <0x4000>;
|
|
gunyah-label = <0x11>;
|
|
phandle = <0xc3>;
|
|
};
|
|
|
|
trust_ui_vm_vblk1_ring {
|
|
size = <0x4000>;
|
|
gunyah-label = <0x10>;
|
|
phandle = <0xc4>;
|
|
};
|
|
|
|
trust_ui_vm_swiotlb {
|
|
size = <0x100000>;
|
|
gunyah-label = <0x12>;
|
|
phandle = <0xc5>;
|
|
};
|
|
|
|
qcom,trust_ui_vm {
|
|
vm_name = "trustedvm";
|
|
shared-buffers-size = <0x108000>;
|
|
shared-buffers = <0xc3 0xc4 0xc5>;
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
trust_ui_vm_virt_be0@11 {
|
|
qcom,vm = <0xc6>;
|
|
qcom,label = <0x11>;
|
|
phandle = <0xc9>;
|
|
};
|
|
|
|
trust_ui_vm_virt_be1@10 {
|
|
qcom,vm = <0xc6>;
|
|
qcom,label = <0x10>;
|
|
phandle = <0xca>;
|
|
};
|
|
|
|
gh-rm-booster {
|
|
compatible = "qcom,gh-rm-booster";
|
|
qcom,rm-vmid = <0xff>;
|
|
qcom,rm-affinity-default = <0x00>;
|
|
};
|
|
|
|
gh-secure-vm-loader@0 {
|
|
compatible = "qcom,gh-secure-vm-loader";
|
|
qcom,pas-id = <0x1c>;
|
|
qcom,vmid = <0x2d>;
|
|
qcom,firmware-name = "trustedvm";
|
|
qcom,keep-running;
|
|
memory-region = <0xc7 0xc8>;
|
|
virtio-backends = <0xc9 0xca>;
|
|
phandle = <0x3cf>;
|
|
};
|
|
|
|
gh-secure-vm-loader@2 {
|
|
compatible = "qcom,gh-secure-vm-loader";
|
|
qcom,pas-id = <0x23>;
|
|
qcom,vmid = <0x32>;
|
|
qcom,firmware-name = "cpusys_vm";
|
|
memory-region = <0xcb>;
|
|
};
|
|
|
|
qcom,msm-cdsp-loader {
|
|
compatible = "qcom,cdsp-loader";
|
|
qcom,proc-img-to-load = "cdsp";
|
|
qcom,rproc-handle = <0xcc>;
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <0xcd>;
|
|
restrict-access;
|
|
};
|
|
|
|
qcom,test-dbl-tuivm {
|
|
compatible = "qcom,gh-dbl";
|
|
qcom,label = <0x04>;
|
|
};
|
|
|
|
qcom,pmic_glink {
|
|
compatible = "qcom,pmic-glink";
|
|
qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
|
|
qcom,subsys-name = "lpass";
|
|
qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
|
|
depends-on-supply = <0x3f>;
|
|
|
|
qcom,battery_charger {
|
|
compatible = "qcom,battery-charger";
|
|
phandle = <0x3d0>;
|
|
};
|
|
|
|
qcom,ucsi {
|
|
compatible = "qcom,ucsi-glink";
|
|
phandle = <0x3d1>;
|
|
};
|
|
|
|
qcom,altmode {
|
|
compatible = "qcom,altmode-glink";
|
|
#altmode-cells = <0x01>;
|
|
phandle = <0x3d2>;
|
|
};
|
|
};
|
|
|
|
qcom,pmic_glink_log {
|
|
compatible = "qcom,pmic-glink";
|
|
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
|
|
|
|
qcom,battery_debug {
|
|
compatible = "qcom,battery-debug";
|
|
};
|
|
|
|
qcom,charger_ulog_glink {
|
|
compatible = "qcom,charger-ulog-glink";
|
|
};
|
|
|
|
qcom,pmic_glink_debug {
|
|
compatible = "qcom,pmic-glink-debug";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
depends-on-supply = <0xce>;
|
|
phandle = <0x3d3>;
|
|
|
|
spmi@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,pm8550b-debug@7 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x07 0x00>;
|
|
qcom,can-sleep;
|
|
phandle = <0x3d4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glink-adc {
|
|
compatible = "qcom,glink-adc";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#io-channel-cells = <0x01>;
|
|
status = "disabled";
|
|
phandle = <0x3d5>;
|
|
};
|
|
};
|
|
|
|
qcom,test-msgq-tuivm {
|
|
compatible = "qcom,gh-msgq-test";
|
|
gunyah-label = <0x04>;
|
|
qcom,primary;
|
|
};
|
|
|
|
qcom,gh-qtimer@17425000 {
|
|
compatible = "qcom,gh-qtmr";
|
|
reg = <0x17425000 0x1000>;
|
|
reg-names = "qtmr-base";
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
interrupt-names = "qcom,qtmr-intr";
|
|
qcom,primary;
|
|
};
|
|
|
|
qcom,kgsl-3d0@3d00000 {
|
|
nvmem-cell-names = "speed_bin";
|
|
nvmem-cells = <0x3ed>;
|
|
qcom,bus-table-ddr = <0x00 0x209a8e 0x2dc6c0 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbdf5c2 0xdbb3e5 0xfbc520>;
|
|
qcom,bus-table-cnoc = <0x00 0x64>;
|
|
interconnect-names = "gpu_icc_path";
|
|
interconnects = <0x50 0x11 0x3e 0x200>;
|
|
qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
|
|
qcom,gpu-qdss-stm = <0x161c0000 0x40000>;
|
|
qcom,ubwc-mode = <0x04>;
|
|
qcom,min-access-length = <0x20>;
|
|
qcom,chipid = <0x43051401>;
|
|
qcom,gpu-model = "Adreno750v2";
|
|
clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk";
|
|
clocks = <0x2c 0x25 0x2c 0x26 0x4b 0x00 0x3c 0x00>;
|
|
interrupt-names = "kgsl_3d0_irq";
|
|
interrupts = <0x00 0x12c 0x04>;
|
|
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc";
|
|
reg = <0x3d00000 0x40000 0x3d61000 0x3000 0x3d50000 0x10000 0x3d9e000 0x2000 0x10900000 0x80000 0x10048000 0x8000 0x10b05000 0x1000>;
|
|
status = "ok";
|
|
compatible = "qcom,adreno-gpu-gen7-9-1", "qcom,kgsl-3d0";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x8f>;
|
|
|
|
zap-shader {
|
|
memory-region = <0x2f9>;
|
|
};
|
|
|
|
qcom,gpu-mempools {
|
|
compatible = "qcom,gpu-mempools";
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-mempool@0 {
|
|
qcom,mempool-reserved = <0x800>;
|
|
qcom,mempool-page-size = <0x1000>;
|
|
reg = <0x00>;
|
|
};
|
|
|
|
qcom,gpu-mempool@1 {
|
|
qcom,mempool-reserved = <0x400>;
|
|
qcom,mempool-page-size = <0x2000>;
|
|
reg = <0x01>;
|
|
};
|
|
|
|
qcom,gpu-mempool@2 {
|
|
qcom,mempool-reserved = <0x100>;
|
|
qcom,mempool-page-size = <0x10000>;
|
|
reg = <0x02>;
|
|
};
|
|
|
|
qcom,gpu-mempool@3 {
|
|
qcom,mempool-reserved = <0x80>;
|
|
qcom,mempool-page-size = <0x20000>;
|
|
reg = <0x03>;
|
|
};
|
|
|
|
qcom,gpu-mempool@4 {
|
|
qcom,mempool-reserved = <0x50>;
|
|
qcom,mempool-page-size = <0x40000>;
|
|
reg = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-mempool@5 {
|
|
qcom,mempool-reserved = <0x20>;
|
|
qcom,mempool-page-size = <0x100000>;
|
|
reg = <0x05>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevel-bins {
|
|
compatible = "qcom,gpu-pwrlevels-bins";
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-pwrlevels-0 {
|
|
qcom,initial-min-pwrlevel = <0x0d>;
|
|
qcom,initial-pwrlevel = <0x0d>;
|
|
qcom,sku-codes = <0x03 0x100f1 0x200f1 0x100f2>;
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x09>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,level = <0x1a0>;
|
|
qcom,gpu-freq = <0x3b9aca00>;
|
|
reg = <0x00>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,level = <0x1a0>;
|
|
qcom,gpu-freq = <0x389fd980>;
|
|
reg = <0x01>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,level = <0x180>;
|
|
qcom,gpu-freq = <0x35d2afc0>;
|
|
reg = <0x02>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,level = <0x140>;
|
|
qcom,gpu-freq = <0x31b5d480>;
|
|
reg = <0x03>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x06>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,level = <0x100>;
|
|
qcom,gpu-freq = <0x2de54480>;
|
|
reg = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x06>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,level = <0xe0>;
|
|
qcom,gpu-freq = <0x2aea5400>;
|
|
reg = <0x05>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x05>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,level = <0xc0>;
|
|
qcom,gpu-freq = <0x2887fa00>;
|
|
reg = <0x06>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x07>;
|
|
qcom,bus-min = <0x03>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,level = <0x90>;
|
|
qcom,gpu-freq = <0x257dc740>;
|
|
reg = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@8 {
|
|
qcom,acd-level = <0x882c5ffd>;
|
|
qcom,bus-max = <0x07>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x05>;
|
|
qcom,level = <0x80>;
|
|
qcom,gpu-freq = <0x22739480>;
|
|
reg = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@9 {
|
|
qcom,acd-level = <0xc02a5ffd>;
|
|
qcom,bus-max = <0x05>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x05>;
|
|
qcom,level = <0x50>;
|
|
qcom,gpu-freq = <0x1dcd6500>;
|
|
reg = <0x09>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@10 {
|
|
qcom,acd-level = <0xc02d5ffd>;
|
|
qcom,bus-max = <0x05>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x05>;
|
|
qcom,level = <0x40>;
|
|
qcom,gpu-freq = <0x19273580>;
|
|
reg = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@11 {
|
|
qcom,acd-level = <0xc02e5ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x03>;
|
|
qcom,level = <0x3c>;
|
|
qcom,gpu-freq = <0x15d0b780>;
|
|
reg = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@12 {
|
|
qcom,acd-level = <0xc82c5ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x38>;
|
|
qcom,gpu-freq = <0x127a3980>;
|
|
reg = <0x0c>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@13 {
|
|
qcom,acd-level = <0xc82f5ffd>;
|
|
qcom,bus-max = <0x01>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0xdc4c7c0>;
|
|
reg = <0x0d>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@14 {
|
|
qcom,bus-max = <0x01>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0x93d1cc0>;
|
|
reg = <0x0e>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@15 {
|
|
qcom,bus-max = <0x01>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0x4c4b400>;
|
|
reg = <0x0f>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-1 {
|
|
qcom,initial-min-pwrlevel = <0x0b>;
|
|
qcom,initial-pwrlevel = <0x0b>;
|
|
qcom,sku-codes = <0x00>;
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x09>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,level = <0x180>;
|
|
qcom,gpu-freq = <0x35d2afc0>;
|
|
reg = <0x00>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,level = <0x140>;
|
|
qcom,gpu-freq = <0x31b5d480>;
|
|
reg = <0x01>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x06>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,level = <0x100>;
|
|
qcom,gpu-freq = <0x2de54480>;
|
|
reg = <0x02>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x06>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,level = <0xe0>;
|
|
qcom,gpu-freq = <0x2aea5400>;
|
|
reg = <0x03>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x09>;
|
|
qcom,bus-min = <0x05>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,level = <0xc0>;
|
|
qcom,gpu-freq = <0x2887fa00>;
|
|
reg = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x07>;
|
|
qcom,bus-min = <0x03>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,level = <0x90>;
|
|
qcom,gpu-freq = <0x257dc740>;
|
|
reg = <0x05>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
qcom,acd-level = <0x882c5ffd>;
|
|
qcom,bus-max = <0x07>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x05>;
|
|
qcom,level = <0x80>;
|
|
qcom,gpu-freq = <0x22739480>;
|
|
reg = <0x06>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
qcom,acd-level = <0xc02a5ffd>;
|
|
qcom,bus-max = <0x05>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x05>;
|
|
qcom,level = <0x50>;
|
|
qcom,gpu-freq = <0x1dcd6500>;
|
|
reg = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@8 {
|
|
qcom,acd-level = <0xc02d5ffd>;
|
|
qcom,bus-max = <0x05>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x05>;
|
|
qcom,level = <0x40>;
|
|
qcom,gpu-freq = <0x19273580>;
|
|
reg = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@9 {
|
|
qcom,acd-level = <0xc02e5ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x03>;
|
|
qcom,level = <0x3c>;
|
|
qcom,gpu-freq = <0x15d0b780>;
|
|
reg = <0x09>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@10 {
|
|
qcom,acd-level = <0xc82c5ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x38>;
|
|
qcom,gpu-freq = <0x127a3980>;
|
|
reg = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@11 {
|
|
qcom,acd-level = <0xc82f5ffd>;
|
|
qcom,bus-max = <0x01>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0xdc4c7c0>;
|
|
reg = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@12 {
|
|
qcom,bus-max = <0x01>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0x93d1cc0>;
|
|
reg = <0x0c>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@13 {
|
|
qcom,bus-max = <0x01>;
|
|
qcom,bus-min = <0x01>;
|
|
qcom,bus-freq = <0x01>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0x4c4b400>;
|
|
reg = <0x0d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mmio-sram@17D09400 {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
compatible = "mmio-sram";
|
|
reg = <0x00 0x17d09400 0x00 0x400>;
|
|
ranges = <0x00 0x00 0x00 0x17d09400 0x00 0x400>;
|
|
phandle = <0x3d6>;
|
|
|
|
scmi-shmem@0 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x00 0x17d09400 0x00 0x400>;
|
|
phandle = <0xd0>;
|
|
};
|
|
};
|
|
|
|
qcom,cpucp@17400000 {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
compatible = "qcom,cpucp";
|
|
reg = <0x17400000 0x10 0x17d90000 0x2000>;
|
|
#mbox-cells = <0x01>;
|
|
interrupts = <0x00 0x3e 0x04>;
|
|
phandle = <0xcf>;
|
|
};
|
|
|
|
qcom,scmi {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "arm,scmi";
|
|
mboxes = <0xcf 0x00>;
|
|
mbox-names = "tx";
|
|
shmem = <0xd0>;
|
|
phandle = <0x3d7>;
|
|
|
|
protocol@80 {
|
|
reg = <0x80>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x3d8>;
|
|
};
|
|
|
|
protocol@81 {
|
|
reg = <0x81>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x3d9>;
|
|
};
|
|
|
|
protocol@86 {
|
|
reg = <0x86>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x3da>;
|
|
};
|
|
|
|
protocol@87 {
|
|
reg = <0x87>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x3db>;
|
|
};
|
|
};
|
|
|
|
qcom,cpucp_log@d8140000 {
|
|
compatible = "qcom,cpucp-log";
|
|
reg = <0xd8040000 0x10000 0xd8050000 0x10000>;
|
|
mboxes = <0xcf 0x01>;
|
|
phandle = <0x3dc>;
|
|
};
|
|
|
|
qcom,c1dcvs {
|
|
compatible = "qcom,c1dcvs-v2";
|
|
phandle = <0x3dd>;
|
|
};
|
|
|
|
qcom,mpam {
|
|
compatible = "qcom,mpam";
|
|
phandle = <0x3de>;
|
|
};
|
|
|
|
qcom,dynpf {
|
|
compatible = "qcom,dynpf";
|
|
phandle = <0x3df>;
|
|
};
|
|
|
|
qcom,cpufreq_stats {
|
|
compatible = "qcom,cpufreq-stats-v2";
|
|
phandle = <0x3e0>;
|
|
};
|
|
|
|
llcc-pmu@24095000 {
|
|
compatible = "qcom,llcc-pmu-ver2";
|
|
reg = <0x24095000 0x300>;
|
|
reg-names = "lagg-base";
|
|
phandle = <0x3e1>;
|
|
};
|
|
|
|
qcom,pmu {
|
|
compatible = "qcom,pmu";
|
|
qcom,long-counter;
|
|
reg = <0x17d09880 0x380>;
|
|
reg-names = "pmu-base";
|
|
qcom,pmu-events-tbl = <0x08 0xff 0x02 0x02 0x11 0xff 0x01 0x00 0x17 0xff 0xff 0x04 0x37 0xff 0xff 0x06 0x1000 0xff 0xff 0x08>;
|
|
phandle = <0x3e2>;
|
|
};
|
|
|
|
ddr-freq-table {
|
|
qcom,freq-tbl = <0x858b8 0xbb800 0x17ba38 0x1a0fe0 0x1febe0 0x29bf80 0x30a138 0x383e70 0x407400>;
|
|
phandle = <0xd1>;
|
|
};
|
|
|
|
llcc-freq-table {
|
|
qcom,freq-tbl = <0x493e0 0x71c50 0x927c0 0xc4c70 0xe3c88 0x104410>;
|
|
phandle = <0xd3>;
|
|
};
|
|
|
|
ddrqos-freq-table {
|
|
qcom,freq-tbl = <0x00 0x01>;
|
|
phandle = <0xd4>;
|
|
};
|
|
|
|
qcom,dcvs {
|
|
compatible = "qcom,dcvs";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x3e3>;
|
|
|
|
l3 {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0x02>;
|
|
qcom,bus-width = <0x20>;
|
|
reg = <0x17d90000 0x4000 0x17d90100 0xa0>;
|
|
reg-names = "l3-base", "l3tbl-base";
|
|
phandle = <0xd9>;
|
|
|
|
sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x00>;
|
|
qcom,shared-offset = <0x90>;
|
|
phandle = <0xda>;
|
|
};
|
|
};
|
|
|
|
ddr {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0x00>;
|
|
qcom,bus-width = <0x04>;
|
|
qcom,freq-tbl = <0xd1>;
|
|
phandle = <0xd5>;
|
|
|
|
sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x00>;
|
|
interconnects = <0x3e 0x04 0x3e 0x200>;
|
|
phandle = <0x3e4>;
|
|
};
|
|
|
|
fp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x01>;
|
|
qcom,fp-voter = <0xd2>;
|
|
phandle = <0xd6>;
|
|
};
|
|
};
|
|
|
|
llcc {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0x01>;
|
|
qcom,bus-width = <0x10>;
|
|
qcom,freq-tbl = <0xd3>;
|
|
phandle = <0xd7>;
|
|
|
|
sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x00>;
|
|
interconnects = <0x50 0x03 0x50 0x231>;
|
|
phandle = <0x3e5>;
|
|
};
|
|
|
|
fp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x01>;
|
|
qcom,fp-voter = <0xd2>;
|
|
phandle = <0xd8>;
|
|
};
|
|
};
|
|
|
|
ddrqos {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0x03>;
|
|
qcom,bus-width = <0x01>;
|
|
qcom,freq-tbl = <0xd4>;
|
|
phandle = <0xdb>;
|
|
|
|
sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x00>;
|
|
interconnects = <0x3e 0x04 0x3e 0x200>;
|
|
phandle = <0xdc>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,memlat {
|
|
compatible = "qcom,memlat";
|
|
phandle = <0x3e6>;
|
|
|
|
ddr {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <0xd5>;
|
|
qcom,sampling-path = <0xd6>;
|
|
qcom,miss-ev = <0x1000>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x19 0x1a>;
|
|
qcom,cpufreq-memfreq-tbl = <0x114900 0x858b8 0x180600 0xbb800 0x229200 0x17ba38>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x1b 0x1c 0x1d 0x1e 0x1f>;
|
|
qcom,cpufreq-memfreq-tbl = <0x96000 0x858b8 0xea600 0xbb800 0x122a00 0x17ba38 0x156300 0x1febe0 0x1d4c00 0x29bf80 0x2a3000 0x383e70 0x30a200 0x407400>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
prime {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x96000 0x858b8 0xea600 0xbb800 0x122a00 0x17ba38 0x156300 0x1febe0 0x1d4c00 0x29bf80 0x2a3000 0x383e70 0x30a200 0x407400>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x1b 0x1c 0x1d 0x1e 0x1f 0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x208500 0x858b8 0x30a200 0x1febe0>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
|
|
prime-latfloor {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x2a3000 0x858b8 0x30a200 0x407400>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
};
|
|
|
|
llcc {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <0xd7>;
|
|
qcom,sampling-path = <0xd8>;
|
|
qcom,miss-ev = <0x37>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x19 0x1a>;
|
|
qcom,cpufreq-memfreq-tbl = <0xdc500 0x493e0 0x180600 0x71c50 0x229200 0x927c0>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x1b 0x1c 0x1d 0x1e 0x1f 0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x96000 0x493e0 0x122a00 0x71c50 0x156300 0x927c0 0x1d4c00 0xc4c70 0x2a3000 0xe3c88 0x30a200 0x104410>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x1b 0x1c 0x1d 0x1e 0x1f 0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x208500 0x493e0 0x30a200 0x927c0>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
};
|
|
|
|
l3 {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <0xd9>;
|
|
qcom,sampling-path = <0xda>;
|
|
qcom,miss-ev = <0x17>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x19 0x1a>;
|
|
qcom,cpufreq-memfreq-tbl = <0x4b000 0x4b000 0x70800 0x5dc00 0x87f00 0x79e00 0xc0300 0xb2200 0xdc500 0xce400 0xf8700 0xe5b00 0x114900 0xfd200 0x130b00 0x114900 0x148200 0x130b00 0x180600 0x15f900 0x1b8a00 0x17bb00 0x1d4c00 0x193200 0x1f0e00 0x1c2000 0x229200 0x1f0e00>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x1b 0x1c 0x1d 0x1e 0x1f>;
|
|
qcom,cpufreq-memfreq-tbl = <0x79e00 0x4b000 0x96000 0x79e00 0xea600 0xce400 0x122a00 0xfd200 0x156300 0x130b00 0x1d4c00 0x15f900 0x274200 0x193200 0x2a3000 0x1c2000 0x30a200 0x1f0e00>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
prime {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x79e00 0x4b000 0x96000 0x79e00 0xea600 0xce400 0x122a00 0xfd200 0x156300 0x130b00 0x1d4c00 0x15f900 0x274200 0x193200 0x2a3000 0x1c2000 0x30a200 0x1f0e00>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
prime-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x208500 0x4b000 0x30a200 0x1f0e00>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
};
|
|
|
|
ddrqos {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <0xdb>;
|
|
qcom,sampling-path = <0xdc>;
|
|
qcom,miss-ev = <0x1000>;
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x1b 0x1c 0x1d 0x1e 0x1f 0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x1d4c00 0x00 0x30a200 0x01>;
|
|
qcom,sampling-enabled;
|
|
phandle = <0x3e7>;
|
|
};
|
|
|
|
prime {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x156300 0x00 0x30a200 0x01>;
|
|
qcom,sampling-enabled;
|
|
phandle = <0x3e8>;
|
|
};
|
|
|
|
prime-latfloor {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x20>;
|
|
qcom,cpufreq-memfreq-tbl = <0x208500 0x00 0x30a200 0x01>;
|
|
qcom,sampling-enabled;
|
|
phandle = <0x3e9>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,llcc-l3-vote {
|
|
qcom,target-dev = <0xd9>;
|
|
qcom,secondary-map = <0x493e0 0x493e0 0x71c50 0x79e00 0x927c0 0x96000 0xc4c70 0xb2200 0xe3c88 0xce400 0x104410 0xe5b00>;
|
|
phandle = <0xdd>;
|
|
};
|
|
|
|
qcom,bwmon-llcc@240B7300 {
|
|
compatible = "qcom,bwmon4";
|
|
reg = <0x240b7400 0x300 0x240b7300 0x200>;
|
|
reg-names = "base", "global_base";
|
|
interrupts = <0x00 0x245 0x04>;
|
|
qcom,mport = <0x00>;
|
|
qcom,hw-timer-hz = <0x124f800>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <0xd7>;
|
|
qcom,second-vote = <0xdd>;
|
|
phandle = <0x3ea>;
|
|
};
|
|
|
|
qcom,bwmon-ddr@24091000 {
|
|
compatible = "qcom,bwmon5";
|
|
reg = <0x24091000 0x1000>;
|
|
reg-names = "base";
|
|
interrupts = <0x00 0x51 0x04>;
|
|
qcom,hw-timer-hz = <0x124f800>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <0xd5>;
|
|
phandle = <0x3eb>;
|
|
};
|
|
|
|
google,debug-kinfo {
|
|
compatible = "google,debug-kinfo";
|
|
memory-region = <0xde>;
|
|
};
|
|
|
|
dmesg-dump {
|
|
compatible = "qcom,dmesg-dump";
|
|
qcom,primary-vm;
|
|
gunyah-label = <0x07>;
|
|
peer-name = <0x02>;
|
|
memory-region = <0xdf>;
|
|
};
|
|
|
|
qcom,qrtr-mhi-cnss {
|
|
compatible = "qcom,qrtr-mhi";
|
|
qcom,dev-id = <0x1107>;
|
|
qcom,net-id = <0x01>;
|
|
qcom,low-latency;
|
|
};
|
|
|
|
qcom,qrtr-gunyah-tuivm {
|
|
compatible = "qcom,qrtr-gunyah";
|
|
qcom,master;
|
|
gunyah-label = <0x03>;
|
|
peer-name = <0x02>;
|
|
};
|
|
|
|
qcom,health_monitor {
|
|
compatible = "qcom,system-health-monitor";
|
|
|
|
qcom,modem {
|
|
qcom,subsys-name = "msm_mpss";
|
|
qcom,ssrestart-string = "mpss";
|
|
qcom,rproc_phandle = <0xe0>;
|
|
};
|
|
};
|
|
|
|
qcom,gunyah-panic-notifier {
|
|
compatible = "qcom,gh-panic-notifier";
|
|
qcom,primary-vm;
|
|
gunyah-label = <0x09>;
|
|
peer-name = <0x02>;
|
|
memory-region = <0xc8>;
|
|
shared-buffer-size = <0x1000>;
|
|
};
|
|
|
|
qfprom@221c2000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x221c2000 0x2000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
read-only;
|
|
ranges;
|
|
phandle = <0x3ec>;
|
|
|
|
gpu_speed_bin@9b {
|
|
reg = <0x9b 0x01>;
|
|
bits = <0x04 0x03>;
|
|
phandle = <0x3ed>;
|
|
};
|
|
};
|
|
|
|
ipcc-self-ping-apss {
|
|
compatible = "qcom,ipcc-self-ping";
|
|
interrupts-extended = <0x3f 0x08 0x02 0x04>;
|
|
mboxes = <0x3f 0x08 0x02>;
|
|
phandle = <0x3ee>;
|
|
};
|
|
|
|
ipcc-self-ping-cdsp {
|
|
compatible = "qcom,ipcc-self-ping";
|
|
interrupts-extended = <0x3f 0x06 0x03 0x04>;
|
|
mboxes = <0x3f 0x06 0x03>;
|
|
phandle = <0x3ef>;
|
|
};
|
|
|
|
ipcc-self-ping-adsp {
|
|
compatible = "qcom,ipcc-self-ping";
|
|
interrupts-extended = <0x3f 0x03 0x03 0x04>;
|
|
mboxes = <0x3f 0x03 0x03>;
|
|
phandle = <0x3f0>;
|
|
};
|
|
|
|
ipcc-self-ping-slpi {
|
|
compatible = "qcom,ipcc-self-ping";
|
|
interrupts-extended = <0x3f 0x04 0x03 0x04>;
|
|
mboxes = <0x3f 0x04 0x03>;
|
|
phandle = <0x3f1>;
|
|
};
|
|
|
|
qcom,gdsc@adf0004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf0004 0x04>;
|
|
regulator-name = "cam_cc_bps_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3f2>;
|
|
};
|
|
|
|
qcom,gdsc@add5004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadd5004 0x04>;
|
|
regulator-name = "cam_cc_camss_top_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x3f3>;
|
|
};
|
|
|
|
qcom,gdsc@adf1004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf1004 0x04>;
|
|
regulator-name = "cam_cc_ife_0_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3f4>;
|
|
};
|
|
|
|
qcom,gdsc@adf2004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf2004 0x04>;
|
|
regulator-name = "cam_cc_ife_1_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3f5>;
|
|
};
|
|
|
|
qcom,gdsc@adf2054 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf2054 0x04>;
|
|
regulator-name = "cam_cc_ife_2_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3f6>;
|
|
};
|
|
|
|
qcom,gdsc@adf0080 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf0080 0x04>;
|
|
regulator-name = "cam_cc_ipe_0_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3f7>;
|
|
};
|
|
|
|
qcom,gdsc@adf00e4 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf00e4 0x04>;
|
|
regulator-name = "cam_cc_sbi_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3f8>;
|
|
};
|
|
|
|
qcom,gdsc@adf3058 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf3058 0x04>;
|
|
regulator-name = "cam_cc_sfe_0_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3f9>;
|
|
};
|
|
|
|
qcom,gdsc@adf30a8 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf30a8 0x04>;
|
|
regulator-name = "cam_cc_sfe_1_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3fa>;
|
|
};
|
|
|
|
qcom,gdsc@adf30f8 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf30f8 0x04>;
|
|
regulator-name = "cam_cc_sfe_2_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
parent-supply = <0xe1>;
|
|
phandle = <0x3fb>;
|
|
};
|
|
|
|
qcom,gdsc@adf32bc {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf32bc 0x04>;
|
|
regulator-name = "cam_cc_titan_top_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x05>;
|
|
interconnects = <0xe2 0x0c 0xe2 0x235>;
|
|
interconnect-names = "mmnoc";
|
|
parent-supply = <0xe3>;
|
|
phandle = <0xe1>;
|
|
};
|
|
|
|
qcom,gdsc@af09000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf09000 0x04>;
|
|
regulator-name = "disp_cc_mdss_core_gdsc";
|
|
proxy-supply = <0xe4>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x11>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <0x31>;
|
|
phandle = <0xe4>;
|
|
};
|
|
|
|
qcom,gdsc@af0b000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf0b000 0x04>;
|
|
regulator-name = "disp_cc_mdss_core_int2_gdsc";
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x11>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <0x31>;
|
|
phandle = <0x3fc>;
|
|
};
|
|
|
|
qcom,gdsc@a909000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xa909000 0x04>;
|
|
regulator-name = "mdss_1_disp_cc_mdss_core_gdsc";
|
|
proxy-supply = <0xe5>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0xe5>;
|
|
};
|
|
|
|
qcom,gdsc@a90b000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xa90b000 0x04>;
|
|
regulator-name = "mdss_1_disp_cc_mdss_core_int2_gdsc";
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x3fd>;
|
|
};
|
|
|
|
syscon@15214c {
|
|
compatible = "syscon";
|
|
reg = <0x15214c 0x04>;
|
|
phandle = <0xe6>;
|
|
};
|
|
|
|
syscon@152150 {
|
|
compatible = "syscon";
|
|
reg = <0x152150 0x04>;
|
|
phandle = <0x3fe>;
|
|
};
|
|
|
|
qcom,gdsc@17891000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17891000 0x04>;
|
|
regulator-name = "apss_ubwcp_pwr_ctrl";
|
|
qcom,no-status-check-on-disable;
|
|
status = "ok";
|
|
phandle = <0xf2>;
|
|
};
|
|
|
|
qcom,gdsc@16b004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16b004 0x04>;
|
|
regulator-name = "gcc_pcie_0_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0xe6 0x00>;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
parent-supply = <0x30>;
|
|
phandle = <0x3ff>;
|
|
};
|
|
|
|
qcom,gdsc@16c000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16c000 0x04>;
|
|
regulator-name = "gcc_pcie_0_phy_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0xe6 0x03>;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
parent-supply = <0x33>;
|
|
phandle = <0x2dd>;
|
|
};
|
|
|
|
qcom,gdsc@18d004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x18d004 0x04>;
|
|
regulator-name = "gcc_pcie_1_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0xe6 0x01>;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
parent-supply = <0x30>;
|
|
phandle = <0x2e2>;
|
|
};
|
|
|
|
qcom,gdsc@18e000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x18e000 0x04>;
|
|
regulator-name = "gcc_pcie_1_phy_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0xe6 0x04>;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
parent-supply = <0x33>;
|
|
phandle = <0x2e3>;
|
|
};
|
|
|
|
qcom,gdsc@117004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x117004 0x04>;
|
|
regulator-name = "gcc_pcie_2_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0xe6 0x05>;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x400>;
|
|
};
|
|
|
|
qcom,gdsc@1a3000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x1a3000 0x04>;
|
|
regulator-name = "gcc_pcie_2_phy_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0xe6 0x06>;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x401>;
|
|
};
|
|
|
|
qcom,gdsc@19e000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x19e000 0x04>;
|
|
regulator-name = "gcc_ufs_mem_phy_gdsc";
|
|
proxy-supply = <0xe7>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
parent-supply = <0x33>;
|
|
phandle = <0xe7>;
|
|
};
|
|
|
|
qcom,gdsc@177004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x177004 0x04>;
|
|
regulator-name = "gcc_ufs_phy_gdsc";
|
|
proxy-supply = <0xe8>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
parent-supply = <0x30>;
|
|
phandle = <0xe8>;
|
|
};
|
|
|
|
qcom,gdsc@139004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x139004 0x04>;
|
|
regulator-name = "gcc_usb30_prim_gdsc";
|
|
proxy-supply = <0xe9>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
phandle = <0xe9>;
|
|
};
|
|
|
|
qcom,gdsc@150018 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x150018 0x04>;
|
|
regulator-name = "gcc_usb3_phy_gdsc";
|
|
proxy-supply = <0xea>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
parent-supply = <0x33>;
|
|
phandle = <0xea>;
|
|
};
|
|
|
|
qcom,gdsc@1a5004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x1a5004 0x04>;
|
|
regulator-name = "gcc_usb30_sec_gdsc";
|
|
proxy-supply = <0xeb>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0xeb>;
|
|
};
|
|
|
|
qcom,gdsc@1a600c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x1a600c 0x04>;
|
|
regulator-name = "gcc_usb3_sec_phy_gdsc";
|
|
proxy-supply = <0xec>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0xec>;
|
|
};
|
|
|
|
syscon@3d99168 {
|
|
compatible = "syscon";
|
|
reg = <0x3d99168 0x04>;
|
|
phandle = <0xed>;
|
|
};
|
|
|
|
qcom,gdsc@3d99108 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d99108 0x04>;
|
|
regulator-name = "gpu_cc_cx_gdsc";
|
|
hw-ctrl-addr = <0xed>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,clk-dis-wait-val = <0x08>;
|
|
qcom,retain-regs;
|
|
status = "ok";
|
|
clocks = <0x2c 0x22>;
|
|
parent-supply = <0x30>;
|
|
phandle = <0xef>;
|
|
};
|
|
|
|
syscon@3d99504 {
|
|
compatible = "syscon";
|
|
reg = <0x3d99504 0x04>;
|
|
phandle = <0x402>;
|
|
};
|
|
|
|
syscon@3d99058 {
|
|
compatible = "syscon";
|
|
reg = <0x3d99058 0x04>;
|
|
phandle = <0x403>;
|
|
};
|
|
|
|
syscon@3d99358 {
|
|
compatible = "syscon";
|
|
reg = <0x3d99358 0x04>;
|
|
phandle = <0x404>;
|
|
};
|
|
|
|
syscon@3d9958c {
|
|
compatible = "syscon";
|
|
reg = <0x3d9958c 0x04>;
|
|
phandle = <0x405>;
|
|
};
|
|
|
|
qcom,gdsc@3d9905c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d9905c 0x04>;
|
|
regulator-name = "gpu_cc_gx_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0x22>;
|
|
parent-supply = <0xee>;
|
|
phandle = <0x406>;
|
|
};
|
|
|
|
qcom,gdsc@3d68024 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d68024 0x04>;
|
|
regulator-name = "gx_clkctl_gx_gdsc";
|
|
reg-supply = <0xef>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x407>;
|
|
};
|
|
|
|
qcom,gdsc@aaf80a4 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf80a4 0x04>;
|
|
regulator-name = "video_cc_mvs0_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0xbb>;
|
|
parent-supply = <0xf0>;
|
|
phandle = <0x408>;
|
|
};
|
|
|
|
qcom,gdsc@aaf804c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf804c 0x04>;
|
|
regulator-name = "video_cc_mvs0c_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0xbb>;
|
|
parent-supply = <0xe3>;
|
|
phandle = <0xf0>;
|
|
};
|
|
|
|
qcom,gdsc@aaf80cc {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf80cc 0x04>;
|
|
regulator-name = "video_cc_mvs1_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0xbb>;
|
|
parent-supply = <0xf1>;
|
|
phandle = <0x409>;
|
|
};
|
|
|
|
qcom,gdsc@aaf8078 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf8078 0x04>;
|
|
regulator-name = "video_cc_mvs1c_gdsc";
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "ok";
|
|
clocks = <0x2c 0xbb>;
|
|
parent-supply = <0xe3>;
|
|
phandle = <0xf1>;
|
|
};
|
|
|
|
kgsl-smmu@3da0000 {
|
|
compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
|
|
reg = <0x3da0000 0x40000 0x3de6000 0x40>;
|
|
reg-names = "base", "tcu-base";
|
|
#iommu-cells = <0x02>;
|
|
qcom,use-3-lvl-tables;
|
|
#global-interrupts = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
ranges;
|
|
dma-coherent;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0xef>;
|
|
clocks = <0x4b 0x12 0x2c 0x25 0x2c 0x26 0x4b 0x00>;
|
|
clock-names = "gpu_cc_hlos1_vote_gpu_smmu", "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb";
|
|
qcom,actlr = <0x00 0x3ff 0x32b>;
|
|
interrupts = <0x00 0x2a1 0x04 0x00 0x2a5 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04 0x00 0x2ae 0x04 0x00 0x2af 0x04 0x00 0x1a6 0x04 0x00 0x1dc 0x04 0x00 0x23e 0x04 0x00 0x23f 0x04 0x00 0x240 0x04 0x00 0x241 0x04 0x00 0x293 0x04 0x00 0x295 0x04 0x00 0x298 0x04 0x00 0x299 0x04 0x00 0x29a 0x04 0x00 0x29c 0x04 0x00 0x29d 0x04 0x00 0x2bb 0x04>;
|
|
phandle = <0xf5>;
|
|
|
|
gpu_qtb@3de8000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x3de8000 0x1000 0x3dec000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x00 0x400>;
|
|
qcom,iova-width = <0x31>;
|
|
interconnects = <0x50 0x00 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x40a>;
|
|
};
|
|
};
|
|
|
|
ubwcp-smmu@179a0000 {
|
|
compatible = "qcom,qsmmu-v500";
|
|
reg = <0x179a0000 0x10000>;
|
|
#iommu-cells = <0x02>;
|
|
qcom,use-3-lvl-tables;
|
|
#global-interrupts = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
ranges;
|
|
dma-coherent;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0xf2>;
|
|
qcom,actlr = <0x00 0x3ff 0x32b>;
|
|
qcom,ignore-numpagendxb;
|
|
interrupts = <0x00 0x2e6 0x04 0x00 0x2ea 0x04 0x00 0x2eb 0x04 0x00 0x2ec 0x04 0x00 0x2ed 0x04>;
|
|
phandle = <0x40b>;
|
|
|
|
ubwcp_qtb@179e8000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x179e8000 0x1000 0x179ec000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x00 0x02>;
|
|
qcom,iova-width = <0x24>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
phandle = <0x40c>;
|
|
};
|
|
};
|
|
|
|
apps-smmu@15000000 {
|
|
compatible = "qcom,qsmmu-v500";
|
|
reg = <0x15000000 0x100000 0x151fe000 0x40>;
|
|
reg-names = "base", "tcu-base";
|
|
#iommu-cells = <0x02>;
|
|
qcom,use-3-lvl-tables;
|
|
qcom,handoff-smrs = <0x1c00 0x02>;
|
|
#global-interrupts = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
ranges;
|
|
dma-coherent;
|
|
qcom,actlr = <0x800 0x20 0x01 0x840 0x00 0x103 0x1800 0x00 0x01 0x1820 0x00 0x01 0x1840 0x00 0x01 0x1860 0x00 0x01 0x1880 0x00 0x01 0x18c0 0x00 0x01 0x18a0 0x40 0x103 0xc01 0x20 0x303 0xc02 0x20 0x303 0xc03 0x20 0x303 0xc04 0x20 0x303 0xc05 0x20 0x303 0xc06 0x20 0x303 0xc07 0x20 0x303 0xc08 0x20 0x303 0xc09 0x20 0x303 0xc0c 0x20 0x303 0xc0d 0x20 0x303 0xc0e 0x20 0x303 0x1961 0x00 0x303 0x1962 0x00 0x303 0x1963 0x00 0x303 0x1964 0x00 0x303 0x1965 0x00 0x303 0x1966 0x00 0x303 0x1967 0x00 0x303 0x1968 0x00 0x303 0x1969 0x00 0x303 0x196c 0x00 0x303 0x196d 0x00 0x303 0x196e 0x00 0x303 0x19c1 0x00 0x303 0x19c2 0x00 0x303 0x19c3 0x00 0x303 0x19c4 0x00 0x303 0x19c5 0x00 0x303 0x19c6 0x00 0x303 0x19c7 0x00 0x303 0x19c8 0x00 0x303 0x19c9 0x00 0x303 0x19cc 0x00 0x303 0x19cd 0x00 0x303 0x19ce 0x00 0x303 0x1c00 0x02 0x01 0x1c01 0x00 0x01 0x1920 0x00 0x103 0x1923 0x00 0x103 0x1924 0x00 0x103 0x1940 0x00 0x103 0x1941 0x04 0x103 0x1943 0x00 0x103 0x1944 0x00 0x103 0x1947 0x00 0x103>;
|
|
interrupts = <0x00 0x41 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x158 0x04 0x00 0x159 0x04 0x00 0x18b 0x04 0x00 0x18c 0x04 0x00 0x18d 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x1a2 0x04 0x00 0x1a3 0x04 0x00 0x19c 0x04 0x00 0x1a5 0x04 0x00 0x2c2 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04 0x00 0x2b1 0x04 0x00 0x2b2 0x04 0x00 0x2b3 0x04 0x00 0x2b4 0x04 0x00 0x2b5 0x04 0x00 0x2b6 0x04 0x00 0x2b7 0x04 0x00 0x2b8 0x04>;
|
|
phandle = <0x4f>;
|
|
|
|
anoc_1_qtb@16f1000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x16f1000 0x1000 0x16e1100 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x00 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0xf3 0x09 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
phandle = <0x40d>;
|
|
};
|
|
|
|
anoc_2_qtb@171a000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x171a000 0x1000 0x1701000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x400 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0xf3 0x0a 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
phandle = <0x40e>;
|
|
};
|
|
|
|
cam_hf_qtb@17d2000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x17d2000 0x1000 0x1782000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x800 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0xe2 0x0c 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x40f>;
|
|
};
|
|
|
|
nsp_qtb@7d3000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x7d3000 0x1000 0x7df000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0xc00 0x400>;
|
|
qcom,iova-width = <0x22>;
|
|
interconnects = <0xbe 0x19 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x410>;
|
|
};
|
|
|
|
lpass_qtb@7b3000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x7b3000 0x1000 0x7be000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x1000 0x400>;
|
|
qcom,iova-width = <0x20>;
|
|
interconnects = <0xac 0x2b 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
phandle = <0x411>;
|
|
};
|
|
|
|
pcie_qtb@16cd000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x16cd000 0x1000 0x16c2000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x1400 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0xf4 0x2f 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
qcom,opt-out-tbu-halting;
|
|
phandle = <0x412>;
|
|
};
|
|
|
|
sf_qtb@17d1000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x17d1000 0x1000 0x1782000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x1800 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0xe2 0x1f 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x413>;
|
|
};
|
|
|
|
mdp_hf_qtb@17d0000 {
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
|
reg = <0x17d0000 0x1000 0x1782000 0x1000>;
|
|
reg-names = "base", "debugchain-base";
|
|
qcom,stream-id-range = <0x1c00 0x400>;
|
|
qcom,iova-width = <0x20>;
|
|
interconnects = <0xe2 0x15 0x3e 0x200>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x414>;
|
|
};
|
|
};
|
|
|
|
dma_dev {
|
|
compatible = "qcom,iommu-dma";
|
|
memory-region = <0xb4>;
|
|
};
|
|
|
|
iommu_test_device {
|
|
compatible = "qcom,iommu-debug-test";
|
|
|
|
usecase0_apps {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x4f 0x400 0x00>;
|
|
};
|
|
|
|
usecase1_apps_fastmap {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x4f 0x400 0x00>;
|
|
qcom,iommu-dma = "fastmap";
|
|
};
|
|
|
|
usecase2_apps_atomic {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x4f 0x400 0x00>;
|
|
qcom,iommu-dma = "atomic";
|
|
};
|
|
|
|
usecase3_apps_dma {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x4f 0x400 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
usecase4_apps_secure {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x4f 0x400 0x00>;
|
|
qcom,iommu-vmid = <0x0a>;
|
|
};
|
|
|
|
usecase5_kgsl {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0xf5 0x07 0x00>;
|
|
};
|
|
|
|
usecase6_kgsl_dma {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0xf5 0x07 0x00>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
dcc_v2@100ff000 {
|
|
compatible = "qcom,dcc-v2";
|
|
reg = <0x100ff000 0x1000 0x10080000 0x18000>;
|
|
qcom,transaction_timeout = <0x00>;
|
|
reg-names = "dcc-base", "dcc-ram-base";
|
|
dcc-ram-offset = <0x00>;
|
|
phandle = <0x415>;
|
|
|
|
link_list_0 {
|
|
qcom,curr-link-list = <0x06>;
|
|
qcom,data-sink = "sram";
|
|
qcom,ap-qad-override;
|
|
qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 0x7201ca8 0x01 0x00 0x00 0x7201cc0 0x01 0x00 0x00 0x7201cd8 0x01 0x00 0x00 0x7201cf0 0x01 0x00 0x00 0x7201d08 0x01 0x00 0x00 0x7201d20 0x01 0x00 0x00 0x7201d38 0x01 0x00 0x00 0x7201d50 0x01 0x00 0x00 0x7201d68 0x01 0x00 0x00 0x7201d80 0x01 0x00 0x00 0x7201d98 0x01 0x00 0x00 0x7201db0 0x01 0x00 0x00 0x7201ee8 0x01 0x00 0x00 0x7201f00 0x01 0x00 0x00 0x7201f18 0x01 0x00 0x00 0x7201f30 0x01 0x00 0x00 0x7201f48 0x01 0x00 0x00 0x7201f60 0x01 0x00 0x00 0x7201f78 0x01 0x00 0x00 0x7201f90 0x01 0x00 0x00 0x7201fa8 0x01 0x00 0x00 0x7201fc0 0x01 0x00 0x00 0x7201fd8 0x01 0x00 0x00 0x7201ff0 0x01 0x00 0x00 0x7202008 0x01 0x00 0x00 0x7202020 0x01 0x00 0x00 0x7202038 0x01 0x00 0x00 0x7202050 0x01 0x00 0x00 0x7202188 0x01 0x00 0x00 0x72021a0 0x01 0x00 0x00 0x72021b8 0x01 0x00 0x00 0x72021d0 0x01 0x00 0x00 0x72021e8 0x01 0x00 0x00 0x7202200 0x01 0x00 0x00 0x7202218 0x01 0x00 0x00 0x7202230 0x01 0x00 0x00 0x7202248 0x01 0x00 0x00 0x7202260 0x01 0x00 0x00 0x7202278 0x01 0x00 0x00 0x7202290 0x01 0x00 0x00 0x72022a8 0x01 0x00 0x00 0x72022c0 0x01 0x00 0x00 0x72022d8 0x01 0x00 0x00 0x72022f0 0x01 0x00 0x00 0x7202428 0x01 0x00 0x00 0x7202440 0x01 0x00 0x00 0x7202458 0x01 0x00 0x00 0x7202470 0x01 0x00 0x00 0x7202488 0x01 0x00 0x00 0x72024a0 0x01 0x00 0x00 0x72024b8 0x01 0x00 0x00 0x72024d0 0x01 0x00 0x00 0x72024e8 0x01 0x00 0x00 0x7202500 0x01 0x00 0x00 0x7202518 0x01 0x00 0x00 0x7202530 0x01 0x00 0x00 0x7202548 0x01 0x00 0x00 0x7202560 0x01 0x00 0x00 0x7202578 0x01 0x00 0x00 0x7202590 0x01 0x00 0x00 0x72026c8 0x01 0x00 0x00 0x72026e0 0x01 0x00 0x00 0x72026f8 0x01 0x00 0x00 0x7202710 0x01 0x00 0x00 0x7202728 0x01 0x00 0x00 0x7202740 0x01 0x00 0x00 0x7202758 0x01 0x00 0x00 0x7202770 0x01 0x00 0x00 0x7202788 0x01 0x00 0x00 0x72027a0 0x01 0x00 0x00 0x72027b8 0x01 0x00 0x00 0x72027d0 0x01 0x00 0x00 0x72027e8 0x01 0x00 0x00 0x7202800 0x01 0x00 0x00 0x7202818 0x01 0x00 0x00 0x7202830 0x01 0x00 0x00 0x7202968 0x01 0x00 0x00 0x7202980 0x01 0x00 0x00 0x7202998 0x01 0x00 0x00 0x72029b0 0x01 0x00 0x00 0x72029c8 0x01 0x00 0x00 0x72029e0 0x01 0x00 0x00 0x72029f8 0x01 0x00 0x00 0x7202a10 0x01 0x00 0x00 0x7202a28 0x01 0x00 0x00 0x7202a40 0x01 0x00 0x00 0x7202a58 0x01 0x00 0x00 0x7202a70 0x01 0x00 0x00 0x7202a88 0x01 0x00 0x00 0x7202aa0 0x01 0x00 0x00 0x7202ab8 0x01 0x00 0x00 0x7202ad0 0x01 0x00 0x00 0x7202c08 0x01 0x00 0x00 0x7202c20 0x01 0x00 0x00 0x7202c38 0x01 0x00 0x00 0x7202c50 0x01 0x00 0x00 0x7202c68 0x01 0x00 0x00 0x7202c80 0x01 0x00 0x00 0x7202c98 0x01 0x00 0x00 0x7202cb0 0x01 0x00 0x00 0x7202cc8 0x01 0x00 0x00 0x7202ce0 0x01 0x00 0x00 0x7202cf8 0x01 0x00 0x00 0x7202d10 0x01 0x00 0x00 0x7202d28 0x01 0x00 0x00 0x7202d40 0x01 0x00 0x00 0x7202d58 0x01 0x00 0x00 0x7202d70 0x01 0x00 0x00 0x7202ea8 0x01 0x00 0x00 0x7202ec0 0x01 0x00 0x00 0x7202ed8 0x01 0x00 0x00 0x7202ef0 0x01 0x00 0x00 0x7202f08 0x01 0x00 0x00 0x7202f20 0x01 0x00 0x00 0x7202f38 0x01 0x00 0x00 0x7202f50 0x01 0x00 0x00 0x7202f68 0x01 0x00 0x00 0x7202f80 0x01 0x00 0x00 0x7202f98 0x01 0x00 0x00 0x7202fb0 0x01 0x00 0x00 0x7202fc8 0x01 0x00 0x00 0x7202fe0 0x01 0x00 0x00 0x7202ff8 0x01 0x00 0x00 0x7203010 0x01 0x00 0x00 0x7203148 0x01 0x00 0x00 0x7203160 0x01 0x00 0x00 0x7203178 0x01 0x00 0x00 0x7203190 0x01 0x00 0x00 0x72031a8 0x01 0x00 0x00 0x72031c0 0x01 0x00 0x00 0x72031d8 0x01 0x00 0x00 0x72031f0 0x01 0x00 0x00 0x7203208 0x01 0x00 0x00 0x7203220 0x01 0x00 0x00 0x7203238 0x01 0x00 0x00 0x7203250 0x01 0x00 0x00 0x7203268 0x01 0x00 0x00 0x7203280 0x01 0x00 0x00 0x7203298 0x01 0x00 0x00 0x72032b0 0x01 0x00 0x00 0x72033e8 0x01 0x00 0x00 0x7203400 0x01 0x00 0x00 0x7203418 0x01 0x00 0x00 0x7203430 0x01 0x00 0x00 0x7203448 0x01 0x00 0x00 0x7203460 0x01 0x00 0x00 0x7203478 0x01 0x00 0x00 0x7203490 0x01 0x00 0x00 0x72034a8 0x01 0x00 0x00 0x72034c0 0x01 0x00 0x00 0x72034d8 0x01 0x00 0x00 0x72034f0 0x01 0x00 0x00 0x7203508 0x01 0x00 0x00 0x7203520 0x01 0x00 0x00 0x7203538 0x01 0x00 0x00 0x7203550 0x01 0x00 0x00 0x7203688 0x01 0x00 0x00 0x72036a0 0x01 0x00 0x00 0x72036b8 0x01 0x00 0x00 0x72036d0 0x01 0x00 0x00 0x72036e8 0x01 0x00 0x00 0x7203700 0x01 0x00 0x00 0x7203718 0x01 0x00 0x00 0x7203730 0x01 0x00 0x00 0x7203748 0x01 0x00 0x00 0x7203760 0x01 0x00 0x00 0x7203778 0x01 0x00 0x00 0x7203790 0x01 0x00 0x00 0x72037a8 0x01 0x00 0x00 0x72037c0 0x01 0x00 0x00 0x72037d8 0x01 0x00 0x00 0x72037f0 0x01 0x00 0x00 0x323c0404 0x02 0x00 0x00 0x323c0208 0x03 0x00 0x00 0x323c0228 0x03 0x00 0x00 0x323c0248 0x03 0x00 0x00 0x323c0268 0x03 0x00 0x00 0x323c040c 0x01 0x00 0x00 0x323c0110 0x02 0x00 0x00 0x323c011c 0x01 0x00 0x00 0x320a4404 0x02 0x00 0x00 0x320a4208 0x03 0x00 0x00 0x320a4228 0x03 0x00 0x00 0x320a4248 0x03 0x00 0x00 0x320a4268 0x03 0x00 0x00 0x320a440c 0x01 0x00 0x00 0x320a4110 0x02 0x00 0x00 0x320a411c 0x01 0x00 0x00 0x320a4d30 0x01 0x00 0x00 0x320a4fd0 0x01 0x00 0x00 0x320a5270 0x01 0x00 0x00 0x320a5510 0x01 0x00 0x00 0x320a57b0 0x01 0x00 0x00 0x320a5a50 0x01 0x00 0x00 0x320a5cf0 0x01 0x00 0x00 0x320a5f90 0x01 0x00 0x00 0x320a4d48 0x01 0x00 0x00 0x320a4d60 0x01 0x00 0x00 0x320a4d78 0x01 0x00 0x00 0x320a4d90 0x01 0x00 0x00 0x320a4da8 0x01 0x00 0x00 0x320a4dc0 0x01 0x00 0x00 0x320a4dd8 0x01 0x00 0x00 0x320a4df0 0x01 0x00 0x00 0x320a4e08 0x01 0x00 0x00 0x320a4e20 0x01 0x00 0x00 0x320a4e38 0x01 0x00 0x00 0x320a4e50 0x01 0x00 0x00 0x320a4e68 0x01 0x00 0x00 0x320a4e80 0x01 0x00 0x00 0x320a4e98 0x01 0x00 0x00 0x320a4eb0 0x01 0x00 0x00 0x320a4fe8 0x01 0x00 0x00 0x320a5000 0x01 0x00 0x00 0x320a5018 0x01 0x00 0x00 0x320a5030 0x01 0x00 0x00 0x320a5048 0x01 0x00 0x00 0x320a5060 0x01 0x00 0x00 0x320a5078 0x01 0x00 0x00 0x320a5090 0x01 0x00 0x00 0x320a50a8 0x01 0x00 0x00 0x320a50c0 0x01 0x00 0x00 0x320a50d8 0x01 0x00 0x00 0x320a50f0 0x01 0x00 0x00 0x320a5108 0x01 0x00 0x00 0x320a5120 0x01 0x00 0x00 0x320a5138 0x01 0x00 0x00 0x320a5150 0x01 0x00 0x00 0x320a5288 0x01 0x00 0x00 0x320a52a0 0x01 0x00 0x00 0x320a52b8 0x01 0x00 0x00 0x320a52d0 0x01 0x00 0x00 0x320a52e8 0x01 0x00 0x00 0x320a5300 0x01 0x00 0x00 0x320a5318 0x01 0x00 0x00 0x320a5330 0x01 0x00 0x00 0x320a5348 0x01 0x00 0x00 0x320a5360 0x01 0x00 0x00 0x320a5378 0x01 0x00 0x00 0x320a5390 0x01 0x00 0x00 0x320a53a8 0x01 0x00 0x00 0x320a53c0 0x01 0x00 0x00 0x320a53d8 0x01 0x00 0x00 0x320a53f0 0x01 0x00 0x00 0x320a5528 0x01 0x00 0x00 0x320a5540 0x01 0x00 0x00 0x320a5558 0x01 0x00 0x00 0x320a5570 0x01 0x00 0x00 0x320a5588 0x01 0x00 0x00 0x320a55a0 0x01 0x00 0x00 0x320a55b8 0x01 0x00 0x00 0x320a55d0 0x01 0x00 0x00 0x320a55e8 0x01 0x00 0x00 0x320a5600 0x01 0x00 0x00 0x320a5618 0x01 0x00 0x00 0x320a5630 0x01 0x00 0x00 0x320a5648 0x01 0x00 0x00 0x320a5660 0x01 0x00 0x00 0x320a5678 0x01 0x00 0x00 0x320a5690 0x01 0x00 0x00 0x320a57c8 0x01 0x00 0x00 0x320a57e0 0x01 0x00 0x00 0x320a57f8 0x01 0x00 0x00 0x320a5810 0x01 0x00 0x00 0x320a5828 0x01 0x00 0x00 0x320a5840 0x01 0x00 0x00 0x320a5858 0x01 0x00 0x00 0x320a5870 0x01 0x00 0x00 0x320a5888 0x01 0x00 0x00 0x320a58a0 0x01 0x00 0x00 0x320a58b8 0x01 0x00 0x00 0x320a58d0 0x01 0x00 0x00 0x320a58e8 0x01 0x00 0x00 0x320a5900 0x01 0x00 0x00 0x320a5918 0x01 0x00 0x00 0x320a5930 0x01 0x00 0x00 0x320a5a68 0x01 0x00 0x00 0x320a5a80 0x01 0x00 0x00 0x320a5a98 0x01 0x00 0x00 0x320a5ab0 0x01 0x00 0x00 0x320a5ac8 0x01 0x00 0x00 0x320a5ae0 0x01 0x00 0x00 0x320a5af8 0x01 0x00 0x00 0x320a5b10 0x01 0x00 0x00 0x320a5b28 0x01 0x00 0x00 0x320a5b40 0x01 0x00 0x00 0x320a5b58 0x01 0x00 0x00 0x320a5b70 0x01 0x00 0x00 0x320a5b88 0x01 0x00 0x00 0x320a5ba0 0x01 0x00 0x00 0x320a5bb8 0x01 0x00 0x00 0x320a5bd0 0x01 0x00 0x00 0x320a5d08 0x01 0x00 0x00 0x320a5d20 0x01 0x00 0x00 0x320a5d38 0x01 0x00 0x00 0x320a5d50 0x01 0x00 0x00 0x320a5d68 0x01 0x00 0x00 0x320a5d80 0x01 0x00 0x00 0x320a5d98 0x01 0x00 0x00 0x320a5db0 0x01 0x00 0x00 0x320a5dc8 0x01 0x00 0x00 0x320a5de0 0x01 0x00 0x00 0x320a5df8 0x01 0x00 0x00 0x320a5e10 0x01 0x00 0x00 0x320a5e28 0x01 0x00 0x00 0x320a5e40 0x01 0x00 0x00 0x320a5e58 0x01 0x00 0x00 0x320a5e70 0x01 0x00 0x00 0x320a5fa8 0x01 0x00 0x00 0x320a5fc0 0x01 0x00 0x00 0x320a5fd8 0x01 0x00 0x00 0x320a5ff0 0x01 0x00 0x00 0x320a6008 0x01 0x00 0x00 0x320a6020 0x01 0x00 0x00 0x320a6038 0x01 0x00 0x00 0x320a6050 0x01 0x00 0x00 0x320a6068 0x01 0x00 0x00 0x320a6080 0x01 0x00 0x00 0x320a6098 0x01 0x00 0x00 0x320a60b0 0x01 0x00 0x00 0x320a60c8 0x01 0x00 0x00 0x320a60e0 0x01 0x00 0x00 0x320a60f8 0x01 0x00 0x00 0x4082028 0x01 0x00 0x00 0x4140404 0x02 0x00 0x00 0x4140208 0x03 0x00 0x00 0x4140228 0x03 0x00 0x00 0x4140248 0x03 0x00 0x00 0x4140268 0x03 0x00 0x00 0x414040c 0x01 0x00 0x00 0x4140110 0x02 0x00 0x00 0x414011c 0x01 0x00 0x00 0x4200404 0x02 0x00 0x00 0x4200208 0x03 0x00 0x00 0x4200228 0x03 0x00 0x00 0x4200248 0x03 0x00 0x00 0x4200268 0x03 0x00 0x00 0x420040c 0x01 0x00 0x00 0x4200110 0x02 0x00 0x00 0x420011c 0x01 0x00 0x00 0x4200d30 0x01 0x00 0x00 0x4200fd0 0x01 0x00 0x00 0x4201270 0x01 0x00 0x00 0x4201510 0x01 0x00 0x00 0x42017b0 0x01 0x00 0x00 0x4201a50 0x01 0x00 0x00 0x4201cf0 0x01 0x00 0x00 0x4201f90 0x01 0x00 0x00 0x4202230 0x01 0x00 0x00 0x42024d0 0x01 0x00 0x00 0x4202770 0x01 0x00 0x00 0x4202a10 0x01 0x00 0x00 0x4202cb0 0x01 0x00 0x00 0x4202f50 0x01 0x00 0x00 0x4200d48 0x01 0x00 0x00 0x4200d60 0x01 0x00 0x00 0x4200d78 0x01 0x00 0x00 0x4200d90 0x01 0x00 0x00 0x4200da8 0x01 0x00 0x00 0x4200dc0 0x01 0x00 0x00 0x4200dd8 0x01 0x00 0x00 0x4200df0 0x01 0x00 0x00 0x4200e08 0x01 0x00 0x00 0x4200e20 0x01 0x00 0x00 0x4200e38 0x01 0x00 0x00 0x4200e50 0x01 0x00 0x00 0x4200e68 0x01 0x00 0x00 0x4200e80 0x01 0x00 0x00 0x4200e98 0x01 0x00 0x00 0x4200eb0 0x01 0x00 0x00 0x4200fe8 0x01 0x00 0x00 0x4201000 0x01 0x00 0x00 0x4201018 0x01 0x00 0x00 0x4201030 0x01 0x00 0x00 0x4201048 0x01 0x00 0x00 0x4201060 0x01 0x00 0x00 0x4201078 0x01 0x00 0x00 0x4201090 0x01 0x00 0x00 0x42010a8 0x01 0x00 0x00 0x42010c0 0x01 0x00 0x00 0x42010d8 0x01 0x00 0x00 0x42010f0 0x01 0x00 0x00 0x4201108 0x01 0x00 0x00 0x4201120 0x01 0x00 0x00 0x4201138 0x01 0x00 0x00 0x4201150 0x01 0x00 0x00 0x4201288 0x01 0x00 0x00 0x42012a0 0x01 0x00 0x00 0x42012b8 0x01 0x00 0x00 0x42012d0 0x01 0x00 0x00 0x42012e8 0x01 0x00 0x00 0x4201300 0x01 0x00 0x00 0x4201318 0x01 0x00 0x00 0x4201330 0x01 0x00 0x00 0x4201348 0x01 0x00 0x00 0x4201360 0x01 0x00 0x00 0x4201378 0x01 0x00 0x00 0x4201390 0x01 0x00 0x00 0x42013a8 0x01 0x00 0x00 0x42013c0 0x01 0x00 0x00 0x42013d8 0x01 0x00 0x00 0x42013f0 0x01 0x00 0x00 0x4201528 0x01 0x00 0x00 0x4201540 0x01 0x00 0x00 0x4201558 0x01 0x00 0x00 0x4201570 0x01 0x00 0x00 0x4201588 0x01 0x00 0x00 0x42015a0 0x01 0x00 0x00 0x42015b8 0x01 0x00 0x00 0x42015d0 0x01 0x00 0x00 0x42015e8 0x01 0x00 0x00 0x4201600 0x01 0x00 0x00 0x4201618 0x01 0x00 0x00 0x4201630 0x01 0x00 0x00 0x4201648 0x01 0x00 0x00 0x4201660 0x01 0x00 0x00 0x4201678 0x01 0x00 0x00 0x4201690 0x01 0x00 0x00 0x42017c8 0x01 0x00 0x00 0x42017e0 0x01 0x00 0x00 0x42017f8 0x01 0x00 0x00 0x4201810 0x01 0x00 0x00 0x4201828 0x01 0x00 0x00 0x4201840 0x01 0x00 0x00 0x4201858 0x01 0x00 0x00 0x4201870 0x01 0x00 0x00 0x4201888 0x01 0x00 0x00 0x42018a0 0x01 0x00 0x00 0x42018b8 0x01 0x00 0x00 0x42018d0 0x01 0x00 0x00 0x42018e8 0x01 0x00 0x00 0x4201900 0x01 0x00 0x00 0x4201918 0x01 0x00 0x00 0x4201930 0x01 0x00 0x00 0x4201a68 0x01 0x00 0x00 0x4201a80 0x01 0x00 0x00 0x4201a98 0x01 0x00 0x00 0x4201ab0 0x01 0x00 0x00 0x4201ac8 0x01 0x00 0x00 0x4201ae0 0x01 0x00 0x00 0x4201af8 0x01 0x00 0x00 0x4201b10 0x01 0x00 0x00 0x4201b28 0x01 0x00 0x00 0x4201b40 0x01 0x00 0x00 0x4201b58 0x01 0x00 0x00 0x4201b70 0x01 0x00 0x00 0x4201b88 0x01 0x00 0x00 0x4201ba0 0x01 0x00 0x00 0x4201bb8 0x01 0x00 0x00 0x4201bd0 0x01 0x00 0x00 0x4201d08 0x01 0x00 0x00 0x4201d20 0x01 0x00 0x00 0x4201d38 0x01 0x00 0x00 0x4201d50 0x01 0x00 0x00 0x4201d68 0x01 0x00 0x00 0x4201d80 0x01 0x00 0x00 0x4201d98 0x01 0x00 0x00 0x4201db0 0x01 0x00 0x00 0x4201dc8 0x01 0x00 0x00 0x4201de0 0x01 0x00 0x00 0x4201df8 0x01 0x00 0x00 0x4201e10 0x01 0x00 0x00 0x4201e28 0x01 0x00 0x00 0x4201e40 0x01 0x00 0x00 0x4201e58 0x01 0x00 0x00 0x4201e70 0x01 0x00 0x00 0x4201fa8 0x01 0x00 0x00 0x4201fc0 0x01 0x00 0x00 0x4201fd8 0x01 0x00 0x00 0x4201ff0 0x01 0x00 0x00 0x4202008 0x01 0x00 0x00 0x4202020 0x01 0x00 0x00 0x4202038 0x01 0x00 0x00 0x4202050 0x01 0x00 0x00 0x4202068 0x01 0x00 0x00 0x4202080 0x01 0x00 0x00 0x4202098 0x01 0x00 0x00 0x42020b0 0x01 0x00 0x00 0x42020c8 0x01 0x00 0x00 0x42020e0 0x01 0x00 0x00 0x42020f8 0x01 0x00 0x00 0x4202110 0x01 0x00 0x00 0x4202248 0x01 0x00 0x00 0x4202260 0x01 0x00 0x00 0x4202278 0x01 0x00 0x00 0x4202290 0x01 0x00 0x00 0x42022a8 0x01 0x00 0x00 0x42022c0 0x01 0x00 0x00 0x42022d8 0x01 0x00 0x00 0x42022f0 0x01 0x00 0x00 0x4202308 0x01 0x00 0x00 0x4202320 0x01 0x00 0x00 0x4202338 0x01 0x00 0x00 0x4202350 0x01 0x00 0x00 0x4202368 0x01 0x00 0x00 0x4202380 0x01 0x00 0x00 0x4202398 0x01 0x00 0x00 0x42023b0 0x01 0x00 0x00 0x42024e8 0x01 0x00 0x00 0x4202500 0x01 0x00 0x00 0x4202518 0x01 0x00 0x00 0x4202530 0x01 0x00 0x00 0x4202548 0x01 0x00 0x00 0x4202560 0x01 0x00 0x00 0x4202578 0x01 0x00 0x00 0x4202590 0x01 0x00 0x00 0x42025a8 0x01 0x00 0x00 0x42025c0 0x01 0x00 0x00 0x42025d8 0x01 0x00 0x00 0x42025f0 0x01 0x00 0x00 0x4202608 0x01 0x00 0x00 0x4202620 0x01 0x00 0x00 0x4202638 0x01 0x00 0x00 0x4202650 0x01 0x00 0x00 0x4202788 0x01 0x00 0x00 0x42027a0 0x01 0x00 0x00 0x42027b8 0x01 0x00 0x00 0x42027d0 0x01 0x00 0x00 0x42027e8 0x01 0x00 0x00 0x4202800 0x01 0x00 0x00 0x4202818 0x01 0x00 0x00 0x4202830 0x01 0x00 0x00 0x4202848 0x01 0x00 0x00 0x4202860 0x01 0x00 0x00 0x4202878 0x01 0x00 0x00 0x4202890 0x01 0x00 0x00 0x42028a8 0x01 0x00 0x00 0x42028c0 0x01 0x00 0x00 0x42028d8 0x01 0x00 0x00 0x42028f0 0x01 0x00 0x00 0x4202a28 0x01 0x00 0x00 0x4202a40 0x01 0x00 0x00 0x4202a58 0x01 0x00 0x00 0x4202a70 0x01 0x00 0x00 0x4202a88 0x01 0x00 0x00 0x4202aa0 0x01 0x00 0x00 0x4202ab8 0x01 0x00 0x00 0x4202ad0 0x01 0x00 0x00 0x4202ae8 0x01 0x00 0x00 0x4202b00 0x01 0x00 0x00 0x4202b18 0x01 0x00 0x00 0x4202b30 0x01 0x00 0x00 0x4202b48 0x01 0x00 0x00 0x4202b60 0x01 0x00 0x00 0x4202b78 0x01 0x00 0x00 0x4202b90 0x01 0x00 0x00 0x4202cc8 0x01 0x00 0x00 0x4202ce0 0x01 0x00 0x00 0x4202cf8 0x01 0x00 0x00 0x4202d10 0x01 0x00 0x00 0x4202d28 0x01 0x00 0x00 0x4202d40 0x01 0x00 0x00 0x4202d58 0x01 0x00 0x00 0x4202d70 0x01 0x00 0x00 0x4202d88 0x01 0x00 0x00 0x4202da0 0x01 0x00 0x00 0x4202db8 0x01 0x00 0x00 0x4202dd0 0x01 0x00 0x00 0x4202de8 0x01 0x00 0x00 0x4202e00 0x01 0x00 0x00 0x4202e18 0x01 0x00 0x00 0x4202e30 0x01 0x00 0x00 0x4202f68 0x01 0x00 0x00 0x4202f80 0x01 0x00 0x00 0x4202f98 0x01 0x00 0x00 0x4202fb0 0x01 0x00 0x00 0x4202fc8 0x01 0x00 0x00 0x4202fe0 0x01 0x00 0x00 0x4202ff8 0x01 0x00 0x00 0x4203010 0x01 0x00 0x00 0x4203028 0x01 0x00 0x00 0x4203040 0x01 0x00 0x00 0x4203058 0x01 0x00 0x00 0x4203070 0x01 0x00 0x00 0x4203088 0x01 0x00 0x00 0x42030a0 0x01 0x00 0x00 0x42030b8 0x01 0x00 0x00 0x42030d0 0x01 0x00 0x00 0x6e0a100 0x01 0x00 0x00 0x6e0a0ac 0x01 0x00 0x00 0x6e0a0b0 0x01 0x00 0x00 0x6e21104 0x01 0x00 0x00 0x6e21108 0x01 0x00 0x00 0x6e212ac 0x01 0x00 0x00 0x6e212b0 0x01 0x00 0x00 0x6e21300 0x01 0x00 0x00 0x6e0a000 0x01 0x00 0x00 0x7402048 0x01 0x00 0x00 0x7402040 0x01 0x00 0x00 0x25a01000 0x06 0x00 0x00 0x25a00000 0x06 0x00 0x00 0x25a03000 0x06 0x00 0x00 0x25a04000 0x06 0x00 0x00 0x25a02000 0x06 0x00 0x00 0x25a05000 0x06 0x00 0x00 0x25a06000 0x06 0x00 0x00 0x25a07000 0x06 0x00 0x00 0x25a08000 0x06 0x00 0x00 0x25a09000 0x06 0x00 0x00 0x25a0a000 0x06 0x00 0x00 0x25a0b000 0x06 0x00 0x00 0x25a0c000 0x06 0x00 0x00 0x25a0d000 0x06 0x00 0x00 0x25a0e000 0x06 0x00 0x00 0x25a0f000 0x06 0x00 0x00 0x25a10000 0x06 0x00 0x00 0x25a11000 0x06 0x00 0x00 0x25a12000 0x06 0x00 0x00 0x25a13000 0x06 0x00 0x00 0x25a14000 0x06 0x00 0x00 0x25a15000 0x06 0x00 0x00 0x25a16000 0x06 0x00 0x00 0x25a17000 0x06 0x00 0x00 0x25a18000 0x06 0x00 0x00 0x25a19000 0x06 0x00 0x00 0x25a1a000 0x06 0x00 0x00 0x25a1b000 0x06 0x00 0x00 0x25a1c000 0x06 0x00 0x00 0x25a1d000 0x06 0x00 0x00 0x25a1e000 0x06 0x00 0x00 0x25a1f000 0x06 0x00 0x00 0x25001000 0x06 0x00 0x00 0x25000000 0x06 0x00 0x00 0x25003000 0x06 0x00 0x00 0x25004000 0x06 0x00 0x00 0x25002000 0x06 0x00 0x00 0x25005000 0x06 0x00 0x00 0x25006000 0x06 0x00 0x00 0x25007000 0x06 0x00 0x00 0x25008000 0x06 0x00 0x00 0x25009000 0x06 0x00 0x00 0x2500a000 0x06 0x00 0x00 0x2500b000 0x06 0x00 0x00 0x2500c000 0x06 0x00 0x00 0x2500d000 0x06 0x00 0x00 0x2500e000 0x06 0x00 0x00 0x2500f000 0x06 0x00 0x00 0x25010000 0x06 0x00 0x00 0x25011000 0x06 0x00 0x00 0x25012000 0x06 0x00 0x00 0x25013000 0x06 0x00 0x00 0x25014000 0x06 0x00 0x00 0x25015000 0x06 0x00 0x00 0x25016000 0x06 0x00 0x00 0x25017000 0x06 0x00 0x00 0x25018000 0x06 0x00 0x00 0x25019000 0x06 0x00 0x00 0x2501a000 0x06 0x00 0x00 0x2501b000 0x06 0x00 0x00 0x2501c000 0x06 0x00 0x00 0x2501d000 0x06 0x00 0x00 0x2501e000 0x06 0x00 0x00 0x2501f000 0x06 0x00 0x00 0x25201000 0x06 0x00 0x00 0x25200000 0x06 0x00 0x00 0x25203000 0x06 0x00 0x00 0x25204000 0x06 0x00 0x00 0x25202000 0x06 0x00 0x00 0x25205000 0x06 0x00 0x00 0x25206000 0x06 0x00 0x00 0x25207000 0x06 0x00 0x00 0x25208000 0x06 0x00 0x00 0x25209000 0x06 0x00 0x00 0x2520a000 0x06 0x00 0x00 0x2520b000 0x06 0x00 0x00 0x2520c000 0x06 0x00 0x00 0x2520d000 0x06 0x00 0x00 0x2520e000 0x06 0x00 0x00 0x2520f000 0x06 0x00 0x00 0x25210000 0x06 0x00 0x00 0x25211000 0x06 0x00 0x00 0x25212000 0x06 0x00 0x00 0x25213000 0x06 0x00 0x00 0x25214000 0x06 0x00 0x00 0x25215000 0x06 0x00 0x00 0x25216000 0x06 0x00 0x00 0x25217000 0x06 0x00 0x00 0x25218000 0x06 0x00 0x00 0x25219000 0x06 0x00 0x00 0x2521a000 0x06 0x00 0x00 0x2521b000 0x06 0x00 0x00 0x2521c000 0x06 0x00 0x00 0x2521d000 0x06 0x00 0x00 0x2521e000 0x06 0x00 0x00 0x2521f000 0x06 0x00 0x00 0x25401000 0x06 0x00 0x00 0x25400000 0x06 0x00 0x00 0x25403000 0x06 0x00 0x00 0x25404000 0x06 0x00 0x00 0x25402000 0x06 0x00 0x00 0x25405000 0x06 0x00 0x00 0x25406000 0x06 0x00 0x00 0x25407000 0x06 0x00 0x00 0x25408000 0x06 0x00 0x00 0x25409000 0x06 0x00 0x00 0x2540a000 0x06 0x00 0x00 0x2540b000 0x06 0x00 0x00 0x2540c000 0x06 0x00 0x00 0x2540d000 0x06 0x00 0x00 0x2540e000 0x06 0x00 0x00 0x2540f000 0x06 0x00 0x00 0x25410000 0x06 0x00 0x00 0x25411000 0x06 0x00 0x00 0x25412000 0x06 0x00 0x00 0x25413000 0x06 0x00 0x00 0x25414000 0x06 0x00 0x00 0x25415000 0x06 0x00 0x00 0x25416000 0x06 0x00 0x00 0x25417000 0x06 0x00 0x00 0x25418000 0x06 0x00 0x00 0x25419000 0x06 0x00 0x00 0x2541a000 0x06 0x00 0x00 0x2541b000 0x06 0x00 0x00 0x2541c000 0x06 0x00 0x00 0x2541d000 0x06 0x00 0x00 0x2541e000 0x06 0x00 0x00 0x2541f000 0x06 0x00 0x00 0x25601000 0x06 0x00 0x00 0x25600000 0x06 0x00 0x00 0x25603000 0x06 0x00 0x00 0x25604000 0x06 0x00 0x00 0x25602000 0x06 0x00 0x00 0x25605000 0x06 0x00 0x00 0x25606000 0x06 0x00 0x00 0x25607000 0x06 0x00 0x00 0x25608000 0x06 0x00 0x00 0x25609000 0x06 0x00 0x00 0x2560a000 0x06 0x00 0x00 0x2560b000 0x06 0x00 0x00 0x2560c000 0x06 0x00 0x00 0x2560d000 0x06 0x00 0x00 0x2560e000 0x06 0x00 0x00 0x2560f000 0x06 0x00 0x00 0x25610000 0x06 0x00 0x00 0x25611000 0x06 0x00 0x00 0x25612000 0x06 0x00 0x00 0x25613000 0x06 0x00 0x00 0x25614000 0x06 0x00 0x00 0x25615000 0x06 0x00 0x00 0x25616000 0x06 0x00 0x00 0x25617000 0x06 0x00 0x00 0x25618000 0x06 0x00 0x00 0x25619000 0x06 0x00 0x00 0x2561a000 0x06 0x00 0x00 0x2561b000 0x06 0x00 0x00 0x2561c000 0x06 0x00 0x00 0x2561d000 0x06 0x00 0x00 0x2561e000 0x06 0x00 0x00 0x2561f000 0x06 0x00 0x00 0x25822870 0x04 0x00 0x00 0x25a22870 0x04 0x00 0x00 0x25823000 0x03 0x00 0x00 0x2582320c 0x15 0x00 0x00 0x25a23000 0x03 0x00 0x00 0x25a2320c 0x15 0x00 0x00 0x25023000 0x03 0x00 0x00 0x2502320c 0x15 0x00 0x00 0x25223000 0x03 0x00 0x00 0x2522320c 0x15 0x00 0x00 0x25423000 0x03 0x00 0x00 0x2542320c 0x15 0x00 0x00 0x25623000 0x03 0x00 0x00 0x2562320c 0x15 0x00 0x00 0x2587601c 0x03 0x00 0x00 0x25a7601c 0x03 0x00 0x00 0x2587603c 0x02 0x00 0x00 0x25a7603c 0x02 0x00 0x00 0x25876058 0x02 0x00 0x00 0x25a76058 0x02 0x00 0x00 0x25021000 0x40 0x00 0x00 0x25421000 0x40 0x00 0x00 0x25221000 0x40 0x00 0x00 0x25621000 0x40 0x00 0x00 0x1780005c 0x01 0x00 0x00 0x1781005c 0x01 0x00 0x00 0x1782005c 0x01 0x00 0x00 0x1783005c 0x01 0x00 0x00 0x1784005c 0x01 0x00 0x00 0x1785005c 0x01 0x00 0x00 0x1786005c 0x01 0x00 0x00 0x1787005c 0x01 0x00 0x00 0x1740003c 0x01 0x00 0x00 0x17600238 0x01 0x00 0x00 0x17600240 0x0b 0x00 0x00 0x17600530 0x01 0x00 0x00 0x1760051c 0x01 0x00 0x00 0x17600524 0x01 0x00 0x00 0x1760052c 0x01 0x00 0x00 0x17600518 0x01 0x00 0x00 0x17600520 0x01 0x00 0x00 0x17600528 0x01 0x00 0x00 0x17600404 0x03 0x00 0x00 0x1760041c 0x03 0x00 0x00 0x17600434 0x01 0x00 0x00 0x1760043c 0x01 0x00 0x00 0x17600440 0x01 0x00 0x00 0x17400438 0x01 0x00 0x00 0x17600044 0x01 0x00 0x00 0x17600500 0x01 0x00 0x00 0x17600504 0x05 0x00 0x00 0x17900908 0x01 0x00 0x00 0x17900c18 0x01 0x00 0x00 0x17901908 0x01 0x00 0x00 0x17901c18 0x01 0x00 0x00 0x17902908 0x01 0x00 0x00 0x17902c18 0x01 0x00 0x00 0x17b90810 0x01 0x00 0x00 0x17b90c50 0x01 0x00 0x00 0x17b90814 0x01 0x00 0x00 0x17b90c54 0x01 0x00 0x00 0x17b90818 0x01 0x00 0x00 0x17b90c58 0x01 0x00 0x00 0x17b93a04 0x02 0x00 0x00 0x17b94810 0x01 0x00 0x00 0x17b94814 0x01 0x00 0x00 0x17b94818 0x01 0x00 0x00 0x17b97a04 0x01 0x00 0x00 0x17ba0810 0x01 0x00 0x00 0x17ba0c50 0x01 0x00 0x00 0x17ba0814 0x01 0x00 0x00 0x17ba0c54 0x01 0x00 0x00 0x17ba0818 0x01 0x00 0x00 0x17ba0c58 0x01 0x00 0x00 0x17ba3a04 0x02 0x00 0x00 0x17b93000 0x50 0x00 0x00 0x17b97000 0x28 0x00 0x00 0x17ba3000 0x50 0x00 0x00 0xc201244 0x01 0x00 0x00 0xc202244 0x01 0x00 0x00 0x17b02000 0x01 0x00 0x00 0x17b00000 0x01 0x00 0x00 0x17a94030 0x01 0x00 0x00 0x17a9408c 0x01 0x00 0x01 0x17a9409c 0x78 0x00 0x01 0x17a9409c 0x00 0x00 0x01 0x17a94048 0x01 0x00 0x01 0x17a94090 0x00 0x00 0x01 0x17a94090 0x25 0x00 0x00 0x17a94098 0x01 0x00 0x01 0x17a94048 0x1d 0x00 0x01 0x17a94090 0x00 0x00 0x01 0x17a94090 0x25 0x00 0x00 0x17a94098 0x01 0x00 0x00 0x17a90030 0x01 0x00 0x00 0x17a9008c 0x01 0x00 0x01 0x17a9009c 0x78 0x00 0x01 0x17a9009c 0x00 0x00 0x01 0x17a90048 0x01 0x00 0x01 0x17a90090 0x00 0x00 0x01 0x17a90090 0x25 0x00 0x00 0x17a90098 0x01 0x00 0x01 0x17a90048 0x1d 0x00 0x01 0x17a90090 0x00 0x00 0x01 0x17a90090 0x25 0x00 0x00 0x17a90098 0x01 0x00 0x00 0x17a92030 0x01 0x00 0x00 0x17a9208c 0x01 0x00 0x01 0x17a9209c 0x78 0x00 0x01 0x17a9209c 0x00 0x00 0x01 0x17a92048 0x01 0x00 0x01 0x17a92090 0x00 0x00 0x01 0x17a92090 0x25 0x00 0x00 0x17a92098 0x01 0x00 0x01 0x17a92048 0x1d 0x00 0x01 0x17a92090 0x00 0x00 0x01 0x17a92090 0x25 0x00 0x00 0x17a92098 0x01 0x00 0x00 0x17a96030 0x01 0x00 0x00 0x17a9608c 0x01 0x00 0x01 0x17a9609c 0x78 0x00 0x01 0x17a9609c 0x00 0x00 0x01 0x17a96048 0x01 0x00 0x01 0x17a96090 0x00 0x00 0x01 0x17a96090 0x25 0x00 0x00 0x17a96098 0x01 0x00 0x01 0x17a96048 0x1d 0x00 0x01 0x17a96090 0x00 0x00 0x01 0x17a96090 0x25 0x00 0x00 0x17a96098 0x01 0x00 0x00 0x17d98024 0x01 0x00 0x00 0x13822000 0x01 0x01 0x00 0x221c20a4 0x01 0x00 0x00 0x1fc8000 0x01 0x00 0x00 0x17400038 0x01 0x00 0x00 0x17d91020 0x01 0x00 0x00 0x17d92020 0x01 0x00 0x00 0x17d93020 0x01 0x00 0x00 0x17d94020 0x01 0x00 0x00 0x17d90020 0x01 0x00 0x00 0x17d9134c 0x01 0x00 0x00 0x17d9234c 0x01 0x00 0x00 0x17d9334c 0x01 0x00 0x00 0x17d9434c 0x01 0x00 0x00 0x17d9034c 0x01 0x00 0x00 0x17d91300 0x01 0x00 0x00 0x17d92300 0x01 0x00 0x00 0x17d93300 0x01 0x00 0x00 0x17d94300 0x01 0x00 0x00 0x17d90300 0x01 0x00 0x00 0x24183040 0x01 0x00 0x00 0x24183048 0x01 0x00 0x00 0x24102010 0x01 0x00 0x00 0x24102020 0x06 0x00 0x00 0x24102410 0x01 0x00 0x00 0x24102420 0x06 0x00 0x00 0x24142010 0x01 0x00 0x00 0x24142020 0x06 0x00 0x00 0x24142410 0x01 0x00 0x00 0x24142420 0x06 0x00 0x00 0x24182010 0x01 0x00 0x00 0x24182020 0x06 0x00 0x00 0x24182410 0x01 0x00 0x00 0x24182420 0x06 0x00 0x00 0x24102810 0x01 0x00 0x00 0x24102820 0x01 0x00 0x00 0x24102828 0x02 0x00 0x00 0x24102c10 0x01 0x00 0x00 0x24102c20 0x01 0x00 0x00 0x24102c28 0x02 0x00 0x00 0x24142810 0x01 0x00 0x00 0x24142820 0x01 0x00 0x00 0x24142828 0x02 0x00 0x00 0x24142c10 0x01 0x00 0x00 0x24142c20 0x01 0x00 0x00 0x24142c28 0x02 0x00 0x00 0x24100810 0x01 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100808 0x02 0x00 0x00 0x24100c10 0x01 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c08 0x02 0x00 0x00 0x24140810 0x01 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140808 0x02 0x00 0x00 0x24140c10 0x01 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c08 0x02 0x00 0x00 0x24180010 0x01 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180008 0x02 0x00 0x00 0x24180410 0x01 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180408 0x02 0x00 0x00 0x24101018 0x01 0x00 0x00 0x24101008 0x01 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101098 0x01 0x00 0x00 0x24101088 0x01 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24141018 0x01 0x00 0x00 0x24141008 0x01 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141098 0x01 0x00 0x00 0x24141088 0x01 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24181018 0x01 0x00 0x00 0x24181008 0x01 0x00 0x00 0x24181010 0x02 0x00 0x00 0x24181010 0x02 0x00 0x00 0x24181010 0x02 0x00 0x00 0x24181098 0x01 0x00 0x00 0x24181088 0x01 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x17800010 0x01 0x00 0x00 0x17800024 0x01 0x00 0x00 0x17800038 0x01 0x00 0x00 0x1780003c 0x01 0x00 0x00 0x17800040 0x01 0x00 0x00 0x17800044 0x01 0x00 0x00 0x17800048 0x01 0x00 0x00 0x1780004c 0x01 0x00 0x00 0x17800058 0x01 0x00 0x00 0x1780005c 0x01 0x00 0x00 0x17800060 0x01 0x00 0x00 0x17800064 0x01 0x00 0x00 0x1780006c 0x01 0x00 0x00 0x178000f0 0x01 0x00 0x00 0x178000f4 0x01 0x00 0x00 0x17810010 0x01 0x00 0x00 0x17810024 0x01 0x00 0x00 0x17810038 0x01 0x00 0x00 0x1781003c 0x01 0x00 0x00 0x17810040 0x01 0x00 0x00 0x17810044 0x01 0x00 0x00 0x17810048 0x01 0x00 0x00 0x1781004c 0x01 0x00 0x00 0x17810058 0x01 0x00 0x00 0x1781005c 0x01 0x00 0x00 0x17810060 0x01 0x00 0x00 0x17810064 0x01 0x00 0x00 0x1781006c 0x01 0x00 0x00 0x178100f0 0x01 0x00 0x00 0x178100f4 0x01 0x00 0x00 0x17820010 0x01 0x00 0x00 0x17820024 0x01 0x00 0x00 0x17820038 0x01 0x00 0x00 0x1782003c 0x01 0x00 0x00 0x17820040 0x01 0x00 0x00 0x17820044 0x01 0x00 0x00 0x17820048 0x01 0x00 0x00 0x1782004c 0x01 0x00 0x00 0x17820058 0x01 0x00 0x00 0x1782005c 0x01 0x00 0x00 0x17820060 0x01 0x00 0x00 0x17820064 0x01 0x00 0x00 0x178200f0 0x01 0x00 0x00 0x178200f4 0x01 0x00 0x00 0x17830010 0x01 0x00 0x00 0x17830024 0x01 0x00 0x00 0x17830038 0x01 0x00 0x00 0x1783003c 0x01 0x00 0x00 0x17830040 0x01 0x00 0x00 0x17830044 0x01 0x00 0x00 0x17830048 0x01 0x00 0x00 0x1783004c 0x01 0x00 0x00 0x17830058 0x01 0x00 0x00 0x1783005c 0x01 0x00 0x00 0x17830060 0x01 0x00 0x00 0x17830064 0x01 0x00 0x00 0x178300f0 0x01 0x00 0x00 0x178300f4 0x01 0x00 0x00 0x17840010 0x01 0x00 0x00 0x17840024 0x01 0x00 0x00 0x17840038 0x01 0x00 0x00 0x1784003c 0x01 0x00 0x00 0x17840040 0x01 0x00 0x00 0x17840044 0x01 0x00 0x00 0x17840048 0x01 0x00 0x00 0x1784004c 0x01 0x00 0x00 0x17840058 0x01 0x00 0x00 0x1784005c 0x01 0x00 0x00 0x17840060 0x01 0x00 0x00 0x17840064 0x01 0x00 0x00 0x178400f0 0x01 0x00 0x00 0x178400f4 0x01 0x00 0x00 0x17850010 0x01 0x00 0x00 0x17850024 0x01 0x00 0x00 0x17850038 0x01 0x00 0x00 0x1785003c 0x01 0x00 0x00 0x17850040 0x01 0x00 0x00 0x17850044 0x01 0x00 0x00 0x17850048 0x01 0x00 0x00 0x1785004c 0x01 0x00 0x00 0x17850058 0x01 0x00 0x00 0x1785005c 0x01 0x00 0x00 0x17850060 0x01 0x00 0x00 0x17850064 0x01 0x00 0x00 0x178500f0 0x01 0x00 0x00 0x178500f4 0x01 0x00 0x00 0x17860010 0x01 0x00 0x00 0x17860024 0x01 0x00 0x00 0x17860038 0x01 0x00 0x00 0x1786003c 0x01 0x00 0x00 0x17860040 0x01 0x00 0x00 0x17860044 0x01 0x00 0x00 0x17860048 0x01 0x00 0x00 0x1786004c 0x01 0x00 0x00 0x17860058 0x01 0x00 0x00 0x1786005c 0x01 0x00 0x00 0x17860060 0x01 0x00 0x00 0x17860064 0x01 0x00 0x00 0x178600f0 0x01 0x00 0x00 0x178600f4 0x01 0x00 0x00 0x17870010 0x01 0x00 0x00 0x17870024 0x01 0x00 0x00 0x17870038 0x01 0x00 0x00 0x1787003c 0x01 0x00 0x00 0x17870040 0x01 0x00 0x00 0x17870044 0x01 0x00 0x00 0x17870048 0x01 0x00 0x00 0x1787004c 0x01 0x00 0x00 0x17870058 0x01 0x00 0x00 0x1787005c 0x01 0x00 0x00 0x17870060 0x01 0x00 0x00 0x17870064 0x01 0x00 0x00 0x178700f0 0x01 0x00 0x00 0x178700f4 0x01 0x00 0x00 0x178a0010 0x01 0x00 0x00 0x178a0024 0x01 0x00 0x00 0x178a0038 0x01 0x00 0x00 0x178a003c 0x01 0x00 0x00 0x178a0040 0x01 0x00 0x00 0x178a0044 0x01 0x00 0x00 0x178a0048 0x01 0x00 0x00 0x178a004c 0x01 0x00 0x00 0x178a006c 0x01 0x00 0x00 0x178a0070 0x01 0x00 0x00 0x178a0074 0x01 0x00 0x00 0x178a0078 0x01 0x00 0x00 0x178a007c 0x01 0x00 0x00 0x178a0084 0x01 0x00 0x00 0x178a00f4 0x01 0x00 0x00 0x178a00f8 0x01 0x00 0x00 0x178a00fc 0x01 0x00 0x00 0x178a0100 0x01 0x00 0x00 0x178a0104 0x01 0x00 0x00 0x178a0118 0x01 0x00 0x00 0x178a011c 0x01 0x00 0x00 0x178a0120 0x01 0x00 0x00 0x178a0124 0x01 0x00 0x00 0x178a0128 0x01 0x00 0x00 0x178a012c 0x01 0x00 0x00 0x178a0130 0x01 0x00 0x00 0x178a0134 0x01 0x00 0x00 0x178a0138 0x01 0x00 0x00 0x178a0158 0x01 0x00 0x00 0x178a015c 0x01 0x00 0x00 0x178a0160 0x01 0x00 0x00 0x178a0164 0x01 0x00 0x00 0x178a0168 0x01 0x00 0x00 0x178a0170 0x01 0x00 0x00 0x178a0174 0x01 0x00 0x00 0x178a0188 0x01 0x00 0x00 0x178a018c 0x01 0x00 0x00 0x178a0190 0x01 0x00 0x00 0x178a0194 0x01 0x00 0x00 0x178a0198 0x01 0x00 0x00 0x178a01ac 0x01 0x00 0x00 0x178a01b0 0x01 0x00 0x00 0x178a01b4 0x01 0x00 0x00 0x178a01b8 0x01 0x00 0x00 0x178a01bc 0x01 0x00 0x00 0x178a01c0 0x01 0x00 0x00 0x178a01c8 0x01 0x00 0x00 0x17880010 0x01 0x00 0x00 0x17880024 0x01 0x00 0x00 0x17880038 0x01 0x00 0x00 0x1788003c 0x01 0x00 0x00 0x17880040 0x01 0x00 0x00 0x17880044 0x01 0x00 0x00 0x17880048 0x01 0x00 0x00 0x1788004c 0x01 0x00 0x00 0x17890010 0x01 0x00 0x00 0x17890024 0x01 0x00 0x00 0x17890038 0x01 0x00 0x00 0x1789003c 0x01 0x00 0x00 0x17890040 0x01 0x00 0x00 0x17890044 0x01 0x00 0x00 0x17890048 0x01 0x00 0x00 0x1789004c 0x01 0x00 0x00 0x178a0290 0x01 0x00 0x00 0x178a0204 0x01 0x00 0x00 0x178a0244 0x01 0x00 0x00 0x17e30000 0x01 0x00 0x00 0x17e30008 0x01 0x00 0x00 0x17e30010 0x01 0x00 0x00 0x17e80000 0x01 0x00 0x00 0x17e80008 0x01 0x00 0x00 0x17e80010 0x01 0x00 0x00 0x17f80000 0x01 0x00 0x00 0x17f80008 0x01 0x00 0x00 0x17f80010 0x01 0x00 0x00 0x18080000 0x01 0x00 0x00 0x18080008 0x01 0x00 0x00 0x18080010 0x01 0x00 0x00 0x18180000 0x01 0x00 0x00 0x18180008 0x01 0x00 0x00 0x18180010 0x01 0x00 0x00 0x18280000 0x01 0x00 0x00 0x18280008 0x01 0x00 0x00 0x18280010 0x01 0x00 0x00 0x18380000 0x01 0x00 0x00 0x18380008 0x01 0x00 0x00 0x18380010 0x01 0x00 0x00 0x18480000 0x01 0x00 0x00 0x18480008 0x01 0x00 0x00 0x18480010 0x01 0x00 0x00 0x18580000 0x01 0x00 0x00 0x18580008 0x01 0x00 0x00 0x18580010 0x01 0x00 0x00 0x2407701c 0x01 0x00 0x00 0x24077030 0x01 0x00 0x00 0x2408005c 0x01 0x00 0x00 0x240800c8 0x01 0x00 0x00 0x240800d4 0x01 0x00 0x00 0x240800e0 0x01 0x00 0x00 0x240800ec 0x01 0x00 0x00 0x240800f8 0x01 0x00 0x00 0x240801b4 0x01 0x00 0x00 0x240a8120 0x01 0x00 0x00 0x240a8124 0x01 0x00 0x00 0x240a8128 0x01 0x00 0x00 0x240a812c 0x01 0x00 0x00 0x240a8130 0x01 0x00 0x00 0x240a8144 0x01 0x00 0x00 0x240a8148 0x01 0x00 0x00 0x240a81d0 0x01 0x00 0x00 0x240a81d4 0x01 0x00 0x00 0x240a81d8 0x01 0x00 0x00 0x240a81dc 0x01 0x00 0x00 0x240a81f0 0x01 0x00 0x00 0x240a81fc 0x01 0x00 0x00 0x240a8208 0x01 0x00 0x00 0x240a8214 0x01 0x00 0x00 0x240a8264 0x01 0x00 0x00 0x240a8284 0x01 0x00 0x00 0x240a82fc 0x01 0x00 0x00 0x240a8860 0x01 0x00 0x00 0x240a8864 0x01 0x00 0x00 0x240a8868 0x01 0x00 0x00 0x240ba28c 0x01 0x00 0x00 0x240ba294 0x01 0x00 0x00 0x240ba29c 0x01 0x00 0x00 0x24185100 0x01 0x00 0x00 0x24185104 0x01 0x00 0x00 0x24185108 0x01 0x00 0x00 0x2418510c 0x01 0x00 0x00 0x24187100 0x01 0x00 0x00 0x2418c100 0x01 0x00 0x00 0x24401e64 0x01 0x00 0x00 0x24401ea0 0x01 0x00 0x00 0x24403e64 0x01 0x00 0x00 0x24403ea0 0x01 0x00 0x00 0x2440527c 0x01 0x00 0x00 0x24405290 0x01 0x00 0x00 0x244054ec 0x01 0x00 0x00 0x244054f4 0x01 0x00 0x00 0x24405514 0x01 0x00 0x00 0x2440551c 0x01 0x00 0x00 0x24405524 0x01 0x00 0x00 0x24405548 0x01 0x00 0x00 0x24405550 0x01 0x00 0x00 0x24405558 0x01 0x00 0x00 0x244055b8 0x01 0x00 0x00 0x244055c0 0x01 0x00 0x00 0x244055ec 0x01 0x00 0x00 0x24405870 0x01 0x00 0x00 0x244058a0 0x01 0x00 0x00 0x244058a8 0x01 0x00 0x00 0x244058b0 0x01 0x00 0x00 0x244058b8 0x01 0x00 0x00 0x244058d8 0x01 0x00 0x00 0x244058dc 0x01 0x00 0x00 0x244058f4 0x01 0x00 0x00 0x244058fc 0x01 0x00 0x00 0x24405920 0x01 0x00 0x00 0x24405928 0x01 0x00 0x00 0x24405944 0x01 0x00 0x00 0x24406604 0x01 0x00 0x00 0x2440660c 0x01 0x00 0x00 0x24440310 0x01 0x00 0x00 0x24440400 0x01 0x00 0x00 0x24440404 0x01 0x00 0x00 0x24440410 0x01 0x00 0x00 0x24440414 0x01 0x00 0x00 0x24440418 0x01 0x00 0x00 0x24440428 0x01 0x00 0x00 0x24440430 0x01 0x00 0x00 0x24440440 0x01 0x00 0x00 0x24440448 0x01 0x00 0x00 0x244404a0 0x01 0x00 0x00 0x244404b0 0x01 0x00 0x00 0x244404b4 0x01 0x00 0x00 0x244404b8 0x01 0x00 0x00 0x244404d0 0x01 0x00 0x00 0x244404d4 0x01 0x00 0x00 0x2444341c 0x01 0x00 0x00 0x24445804 0x01 0x00 0x00 0x2444590c 0x01 0x00 0x00 0x24445a14 0x01 0x00 0x00 0x24445c1c 0x01 0x00 0x00 0x24445c38 0x01 0x00 0x00 0x24449100 0x01 0x00 0x00 0x24449110 0x01 0x00 0x00 0x24449120 0x01 0x00 0x00 0x24449180 0x01 0x00 0x00 0x24449184 0x01 0x00 0x00 0x24460618 0x01 0x00 0x00 0x24460684 0x01 0x00 0x00 0x2446068c 0x01 0x00 0x00 0x24481e64 0x01 0x00 0x00 0x24481ea0 0x01 0x00 0x00 0x24483e64 0x01 0x00 0x00 0x24483ea0 0x01 0x00 0x00 0x2448527c 0x01 0x00 0x00 0x24485290 0x01 0x00 0x00 0x244854ec 0x01 0x00 0x00 0x244854f4 0x01 0x00 0x00 0x24485514 0x01 0x00 0x00 0x2448551c 0x01 0x00 0x00 0x24485524 0x01 0x00 0x00 0x24485548 0x01 0x00 0x00 0x24485550 0x01 0x00 0x00 0x24485558 0x01 0x00 0x00 0x244855b8 0x01 0x00 0x00 0x244855c0 0x01 0x00 0x00 0x244855ec 0x01 0x00 0x00 0x24485870 0x01 0x00 0x00 0x244858a0 0x01 0x00 0x00 0x244858a8 0x01 0x00 0x00 0x244858b0 0x01 0x00 0x00 0x244858b8 0x01 0x00 0x00 0x244858d8 0x01 0x00 0x00 0x244858dc 0x01 0x00 0x00 0x244858f4 0x01 0x00 0x00 0x244858fc 0x01 0x00 0x00 0x24485920 0x01 0x00 0x00 0x24485928 0x01 0x00 0x00 0x24485944 0x01 0x00 0x00 0x24486604 0x01 0x00 0x00 0x2448660c 0x01 0x00 0x00 0x244c0310 0x01 0x00 0x00 0x244c0400 0x01 0x00 0x00 0x244c0404 0x01 0x00 0x00 0x244c0410 0x01 0x00 0x00 0x244c0414 0x01 0x00 0x00 0x244c0418 0x01 0x00 0x00 0x244c0428 0x01 0x00 0x00 0x244c0430 0x01 0x00 0x00 0x244c0440 0x01 0x00 0x00 0x244c0448 0x01 0x00 0x00 0x244c04a0 0x01 0x00 0x00 0x244c04b0 0x01 0x00 0x00 0x244c04b4 0x01 0x00 0x00 0x244c04b8 0x01 0x00 0x00 0x244c04d0 0x01 0x00 0x00 0x244c04d4 0x01 0x00 0x00 0x244c341c 0x01 0x00 0x00 0x244c5804 0x01 0x00 0x00 0x244c590c 0x01 0x00 0x00 0x244c5a14 0x01 0x00 0x00 0x244c5c1c 0x01 0x00 0x00 0x244c5c38 0x01 0x00 0x00 0x244c9100 0x01 0x00 0x00 0x244c9110 0x01 0x00 0x00 0x244c9120 0x01 0x00 0x00 0x244c9180 0x01 0x00 0x00 0x244c9184 0x01 0x00 0x00 0x244e0618 0x01 0x00 0x00 0x244e0684 0x01 0x00 0x00 0x244e068c 0x01 0x00 0x00 0x24601e64 0x01 0x00 0x00 0x24601ea0 0x01 0x00 0x00 0x24603e64 0x01 0x00 0x00 0x24603ea0 0x01 0x00 0x00 0x2460527c 0x01 0x00 0x00 0x24605290 0x01 0x00 0x00 0x246054ec 0x01 0x00 0x00 0x246054f4 0x01 0x00 0x00 0x24605514 0x01 0x00 0x00 0x2460551c 0x01 0x00 0x00 0x24605524 0x01 0x00 0x00 0x24605548 0x01 0x00 0x00 0x24605550 0x01 0x00 0x00 0x24605558 0x01 0x00 0x00 0x246055b8 0x01 0x00 0x00 0x246055c0 0x01 0x00 0x00 0x246055ec 0x01 0x00 0x00 0x24605870 0x01 0x00 0x00 0x246058a0 0x01 0x00 0x00 0x246058a8 0x01 0x00 0x00 0x246058b0 0x01 0x00 0x00 0x246058b8 0x01 0x00 0x00 0x246058d8 0x01 0x00 0x00 0x246058dc 0x01 0x00 0x00 0x246058f4 0x01 0x00 0x00 0x246058fc 0x01 0x00 0x00 0x24605920 0x01 0x00 0x00 0x24605928 0x01 0x00 0x00 0x24605944 0x01 0x00 0x00 0x24606604 0x01 0x00 0x00 0x2460660c 0x01 0x00 0x00 0x24640310 0x01 0x00 0x00 0x24640400 0x01 0x00 0x00 0x24640404 0x01 0x00 0x00 0x24640410 0x01 0x00 0x00 0x24640414 0x01 0x00 0x00 0x24640418 0x01 0x00 0x00 0x24640428 0x01 0x00 0x00 0x24640430 0x01 0x00 0x00 0x24640440 0x01 0x00 0x00 0x24640448 0x01 0x00 0x00 0x246404a0 0x01 0x00 0x00 0x246404b0 0x01 0x00 0x00 0x246404b4 0x01 0x00 0x00 0x246404b8 0x01 0x00 0x00 0x246404d0 0x01 0x00 0x00 0x246404d4 0x01 0x00 0x00 0x2464341c 0x01 0x00 0x00 0x24645804 0x01 0x00 0x00 0x2464590c 0x01 0x00 0x00 0x24645a14 0x01 0x00 0x00 0x24645c1c 0x01 0x00 0x00 0x24645c38 0x01 0x00 0x00 0x24649100 0x01 0x00 0x00 0x24649110 0x01 0x00 0x00 0x24649120 0x01 0x00 0x00 0x24649180 0x01 0x00 0x00 0x24649184 0x01 0x00 0x00 0x24660618 0x01 0x00 0x00 0x24660684 0x01 0x00 0x00 0x2466068c 0x01 0x00 0x00 0x24681e64 0x01 0x00 0x00 0x24681ea0 0x01 0x00 0x00 0x24683e64 0x01 0x00 0x00 0x24683ea0 0x01 0x00 0x00 0x2468527c 0x01 0x00 0x00 0x24685290 0x01 0x00 0x00 0x246854ec 0x01 0x00 0x00 0x246854f4 0x01 0x00 0x00 0x24685514 0x01 0x00 0x00 0x2468551c 0x01 0x00 0x00 0x24685524 0x01 0x00 0x00 0x24685548 0x01 0x00 0x00 0x24685550 0x01 0x00 0x00 0x24685558 0x01 0x00 0x00 0x246855b8 0x01 0x00 0x00 0x246855c0 0x01 0x00 0x00 0x246855ec 0x01 0x00 0x00 0x24685870 0x01 0x00 0x00 0x246858a0 0x01 0x00 0x00 0x246858a8 0x01 0x00 0x00 0x246858b0 0x01 0x00 0x00 0x246858b8 0x01 0x00 0x00 0x246858d8 0x01 0x00 0x00 0x246858dc 0x01 0x00 0x00 0x246858f4 0x01 0x00 0x00 0x246858fc 0x01 0x00 0x00 0x24685920 0x01 0x00 0x00 0x24685928 0x01 0x00 0x00 0x24685944 0x01 0x00 0x00 0x24686604 0x01 0x00 0x00 0x2468660c 0x01 0x00 0x00 0x246c0310 0x01 0x00 0x00 0x246c0400 0x01 0x00 0x00 0x246c0404 0x01 0x00 0x00 0x246c0410 0x01 0x00 0x00 0x246c0414 0x01 0x00 0x00 0x246c0418 0x01 0x00 0x00 0x246c0428 0x01 0x00 0x00 0x246c0430 0x01 0x00 0x00 0x246c0440 0x01 0x00 0x00 0x246c0448 0x01 0x00 0x00 0x246c04a0 0x01 0x00 0x00 0x246c04b0 0x01 0x00 0x00 0x246c04b4 0x01 0x00 0x00 0x246c04b8 0x01 0x00 0x00 0x246c04d0 0x01 0x00 0x00 0x246c04d4 0x01 0x00 0x00 0x246c341c 0x01 0x00 0x00 0x246c5804 0x01 0x00 0x00 0x246c590c 0x01 0x00 0x00 0x246c5a14 0x01 0x00 0x00 0x246c5c1c 0x01 0x00 0x00 0x246c5c38 0x01 0x00 0x00 0x246c9100 0x01 0x00 0x00 0x246c9110 0x01 0x00 0x00 0x246c9120 0x01 0x00 0x00 0x246c9180 0x01 0x00 0x00 0x246c9184 0x01 0x00 0x00 0x246e0618 0x01 0x00 0x00 0x246e0684 0x01 0x00 0x00 0x246e068c 0x01 0x00 0x00 0x24840310 0x01 0x00 0x00 0x24840400 0x01 0x00 0x00 0x24840404 0x01 0x00 0x00 0x24840410 0x01 0x00 0x00 0x24840414 0x01 0x00 0x00 0x24840418 0x01 0x00 0x00 0x24840428 0x01 0x00 0x00 0x24840430 0x01 0x00 0x00 0x24840440 0x01 0x00 0x00 0x24840448 0x01 0x00 0x00 0x248404a0 0x01 0x00 0x00 0x248404b0 0x01 0x00 0x00 0x248404b4 0x01 0x00 0x00 0x248404b8 0x01 0x00 0x00 0x248404d0 0x01 0x00 0x00 0x248404d4 0x01 0x00 0x00 0x2484341c 0x01 0x00 0x00 0x24845804 0x01 0x00 0x00 0x2484590c 0x01 0x00 0x00 0x24845a14 0x01 0x00 0x00 0x24845c1c 0x01 0x00 0x00 0x24845c38 0x01 0x00 0x00 0x24849100 0x01 0x00 0x00 0x24849110 0x01 0x00 0x00 0x24849120 0x01 0x00 0x00 0x24849180 0x01 0x00 0x00 0x24849184 0x01 0x00 0x00 0x24860618 0x01 0x00 0x00 0x24860684 0x01 0x00 0x00 0x2486068c 0x01 0x00 0x00 0x248c0310 0x01 0x00 0x00 0x248c0400 0x01 0x00 0x00 0x248c0404 0x01 0x00 0x00 0x248c0410 0x01 0x00 0x00 0x248c0414 0x01 0x00 0x00 0x248c0418 0x01 0x00 0x00 0x248c0428 0x01 0x00 0x00 0x248c0430 0x01 0x00 0x00 0x248c0440 0x01 0x00 0x00 0x248c0448 0x01 0x00 0x00 0x248c04a0 0x01 0x00 0x00 0x248c04b0 0x01 0x00 0x00 0x248c04b4 0x01 0x00 0x00 0x248c04b8 0x01 0x00 0x00 0x248c04d0 0x01 0x00 0x00 0x248c04d4 0x01 0x00 0x00 0x248c341c 0x01 0x00 0x00 0x248c5804 0x01 0x00 0x00 0x248c590c 0x01 0x00 0x00 0x248c5a14 0x01 0x00 0x00 0x248c5c1c 0x01 0x00 0x00 0x248c5c38 0x01 0x00 0x00 0x248c9100 0x01 0x00 0x00 0x248c9110 0x01 0x00 0x00 0x248c9120 0x01 0x00 0x00 0x248c9180 0x01 0x00 0x00 0x248c9184 0x01 0x00 0x00 0x248e0618 0x01 0x00 0x00 0x248e0684 0x01 0x00 0x00 0x248e068c 0x01 0x00 0x00 0x25020348 0x01 0x00 0x00 0x25020480 0x01 0x00 0x00 0x25022400 0x01 0x00 0x00 0x25023220 0x01 0x00 0x00 0x25023224 0x01 0x00 0x00 0x25023228 0x01 0x00 0x00 0x2502322c 0x01 0x00 0x00 0x25023258 0x01 0x00 0x00 0x2502325c 0x01 0x00 0x00 0x25023308 0x01 0x00 0x00 0x25023318 0x01 0x00 0x00 0x25038100 0x01 0x00 0x00 0x2503c030 0x01 0x00 0x00 0x25042044 0x01 0x00 0x00 0x25042048 0x01 0x00 0x00 0x2504204c 0x01 0x00 0x00 0x250420b0 0x01 0x00 0x00 0x25042104 0x01 0x00 0x00 0x25042114 0x01 0x00 0x00 0x25048004 0x01 0x00 0x00 0x25048008 0x01 0x00 0x00 0x2504800c 0x01 0x00 0x00 0x25048010 0x01 0x00 0x00 0x25048014 0x01 0x00 0x00 0x2504c030 0x01 0x00 0x00 0x25050020 0x01 0x00 0x00 0x2506004c 0x01 0x00 0x00 0x25060050 0x01 0x00 0x00 0x25060054 0x01 0x00 0x00 0x25060058 0x01 0x00 0x00 0x2506005c 0x01 0x00 0x00 0x25060060 0x01 0x00 0x00 0x25060064 0x01 0x00 0x00 0x25060068 0x01 0x00 0x00 0x25220348 0x01 0x00 0x00 0x25220480 0x01 0x00 0x00 0x25222400 0x01 0x00 0x00 0x25223220 0x01 0x00 0x00 0x25223224 0x01 0x00 0x00 0x25223228 0x01 0x00 0x00 0x2522322c 0x01 0x00 0x00 0x25223258 0x01 0x00 0x00 0x2522325c 0x01 0x00 0x00 0x25223308 0x01 0x00 0x00 0x25223318 0x01 0x00 0x00 0x25238100 0x01 0x00 0x00 0x2523c030 0x01 0x00 0x00 0x25242044 0x01 0x00 0x00 0x25242048 0x01 0x00 0x00 0x2524204c 0x01 0x00 0x00 0x252420b0 0x01 0x00 0x00 0x25242104 0x01 0x00 0x00 0x25242114 0x01 0x00 0x00 0x25248004 0x01 0x00 0x00 0x25248008 0x01 0x00 0x00 0x2524800c 0x01 0x00 0x00 0x25248010 0x01 0x00 0x00 0x25248014 0x01 0x00 0x00 0x2524c030 0x01 0x00 0x00 0x25250020 0x01 0x00 0x00 0x2526004c 0x01 0x00 0x00 0x25260050 0x01 0x00 0x00 0x25260054 0x01 0x00 0x00 0x25260058 0x01 0x00 0x00 0x2526005c 0x01 0x00 0x00 0x25260060 0x01 0x00 0x00 0x25260064 0x01 0x00 0x00 0x25260068 0x01 0x00 0x00 0x25420348 0x01 0x00 0x00 0x25420480 0x01 0x00 0x00 0x25422400 0x01 0x00 0x00 0x25423220 0x01 0x00 0x00 0x25423224 0x01 0x00 0x00 0x25423228 0x01 0x00 0x00 0x2542322c 0x01 0x00 0x00 0x25423258 0x01 0x00 0x00 0x2542325c 0x01 0x00 0x00 0x25423308 0x01 0x00 0x00 0x25423318 0x01 0x00 0x00 0x25438100 0x01 0x00 0x00 0x2543c030 0x01 0x00 0x00 0x25442044 0x01 0x00 0x00 0x25442048 0x01 0x00 0x00 0x2544204c 0x01 0x00 0x00 0x254420b0 0x01 0x00 0x00 0x25442104 0x01 0x00 0x00 0x25442114 0x01 0x00 0x00 0x25448004 0x01 0x00 0x00 0x25448008 0x01 0x00 0x00 0x2544800c 0x01 0x00 0x00 0x25448010 0x01 0x00 0x00 0x25448014 0x01 0x00 0x00 0x2544c030 0x01 0x00 0x00 0x25450020 0x01 0x00 0x00 0x2546004c 0x01 0x00 0x00 0x25460050 0x01 0x00 0x00 0x25460054 0x01 0x00 0x00 0x25460058 0x01 0x00 0x00 0x2546005c 0x01 0x00 0x00 0x25460060 0x01 0x00 0x00 0x25460064 0x01 0x00 0x00 0x25460068 0x01 0x00 0x00 0x25620348 0x01 0x00 0x00 0x25620480 0x01 0x00 0x00 0x25622400 0x01 0x00 0x00 0x25623220 0x01 0x00 0x00 0x25623224 0x01 0x00 0x00 0x25623228 0x01 0x00 0x00 0x2562322c 0x01 0x00 0x00 0x25623258 0x01 0x00 0x00 0x2562325c 0x01 0x00 0x00 0x25623308 0x01 0x00 0x00 0x25623318 0x01 0x00 0x00 0x25638100 0x01 0x00 0x00 0x2563c030 0x01 0x00 0x00 0x25642044 0x01 0x00 0x00 0x25642048 0x01 0x00 0x00 0x2564204c 0x01 0x00 0x00 0x256420b0 0x01 0x00 0x00 0x25642104 0x01 0x00 0x00 0x25642114 0x01 0x00 0x00 0x25648004 0x01 0x00 0x00 0x25648008 0x01 0x00 0x00 0x2564800c 0x01 0x00 0x00 0x25648010 0x01 0x00 0x00 0x25648014 0x01 0x00 0x00 0x2564c030 0x01 0x00 0x00 0x25650020 0x01 0x00 0x00 0x2566004c 0x01 0x00 0x00 0x25660050 0x01 0x00 0x00 0x25660054 0x01 0x00 0x00 0x25660058 0x01 0x00 0x00 0x2566005c 0x01 0x00 0x00 0x25660060 0x01 0x00 0x00 0x25660064 0x01 0x00 0x00 0x25660068 0x01 0x00 0x00 0x25820348 0x01 0x00 0x00 0x25820480 0x01 0x00 0x00 0x25822400 0x01 0x00 0x00 0x25823220 0x01 0x00 0x00 0x25823224 0x01 0x00 0x00 0x25823228 0x01 0x00 0x00 0x2582322c 0x01 0x00 0x00 0x25823258 0x01 0x00 0x00 0x2582325c 0x01 0x00 0x00 0x25823308 0x01 0x00 0x00 0x25823318 0x01 0x00 0x00 0x25838100 0x01 0x00 0x00 0x2583c030 0x01 0x00 0x00 0x25842044 0x01 0x00 0x00 0x25842048 0x01 0x00 0x00 0x2584204c 0x01 0x00 0x00 0x258420b0 0x01 0x00 0x00 0x25842104 0x01 0x00 0x00 0x25842114 0x01 0x00 0x00 0x25848004 0x01 0x00 0x00 0x25848008 0x01 0x00 0x00 0x2584800c 0x01 0x00 0x00 0x25848010 0x01 0x00 0x00 0x25848014 0x01 0x00 0x00 0x2584c030 0x01 0x00 0x00 0x25850020 0x01 0x00 0x00 0x2586004c 0x01 0x00 0x00 0x25860050 0x01 0x00 0x00 0x25860054 0x01 0x00 0x00 0x25860058 0x01 0x00 0x00 0x2586005c 0x01 0x00 0x00 0x25860060 0x01 0x00 0x00 0x25860064 0x01 0x00 0x00 0x25860068 0x01 0x00 0x00 0x25a20348 0x01 0x00 0x00 0x25a20480 0x01 0x00 0x00 0x25a22400 0x01 0x00 0x00 0x25a23220 0x01 0x00 0x00 0x25a23224 0x01 0x00 0x00 0x25a23228 0x01 0x00 0x00 0x25a2322c 0x01 0x00 0x00 0x25a23258 0x01 0x00 0x00 0x25a2325c 0x01 0x00 0x00 0x25a23308 0x01 0x00 0x00 0x25a23318 0x01 0x00 0x00 0x25a38100 0x01 0x00 0x00 0x25a3c030 0x01 0x00 0x00 0x25a42044 0x01 0x00 0x00 0x25a42048 0x01 0x00 0x00 0x25a4204c 0x01 0x00 0x00 0x25a420b0 0x01 0x00 0x00 0x25a42104 0x01 0x00 0x00 0x25a42114 0x01 0x00 0x00 0x25a48004 0x01 0x00 0x00 0x25a48008 0x01 0x00 0x00 0x25a4800c 0x01 0x00 0x00 0x25a48010 0x01 0x00 0x00 0x25a48014 0x01 0x00 0x00 0x25a4c030 0x01 0x00 0x00 0x25a50020 0x01 0x00 0x00 0x25a6004c 0x01 0x00 0x00 0x25a60050 0x01 0x00 0x00 0x25a60054 0x01 0x00 0x00 0x25a60058 0x01 0x00 0x00 0x25a6005c 0x01 0x00 0x00 0x25a60060 0x01 0x00 0x00 0x25a60064 0x01 0x00 0x00 0x25a60068 0x01 0x00 0x00 0x25a01004 0x01 0x00 0x00 0x25a00004 0x01 0x00 0x00 0x25a03004 0x01 0x00 0x00 0x25a04004 0x01 0x00 0x00 0x25a02004 0x01 0x00 0x00 0x25a05004 0x01 0x00 0x00 0x25a06004 0x01 0x00 0x00 0x25a07004 0x01 0x00 0x00 0x25a08004 0x01 0x00 0x00 0x25a09004 0x01 0x00 0x00 0x25a0a004 0x01 0x00 0x00 0x25a0b004 0x01 0x00 0x00 0x25a0c004 0x01 0x00 0x00 0x25a0d004 0x01 0x00 0x00 0x25a0e004 0x01 0x00 0x00 0x25a0f004 0x01 0x00 0x00 0x25a10004 0x01 0x00 0x00 0x25a11004 0x01 0x00 0x00 0x25a12004 0x01 0x00 0x00 0x25a13004 0x01 0x00 0x00 0x25a14004 0x01 0x00 0x00 0x25a15004 0x01 0x00 0x00 0x25a16004 0x01 0x00 0x00 0x25a17004 0x01 0x00 0x00 0x25a18004 0x01 0x00 0x00 0x25a19004 0x01 0x00 0x00 0x25a1a004 0x01 0x00 0x00 0x25a1b004 0x01 0x00 0x00 0x25a1c004 0x01 0x00 0x00 0x25a1d004 0x01 0x00 0x00 0x25a1e004 0x01 0x00 0x00 0x25a1f004 0x01 0x00 0x00 0x25001004 0x01 0x00 0x00 0x25000004 0x01 0x00 0x00 0x25003004 0x01 0x00 0x00 0x25004004 0x01 0x00 0x00 0x25002004 0x01 0x00 0x00 0x25005004 0x01 0x00 0x00 0x25006004 0x01 0x00 0x00 0x25007004 0x01 0x00 0x00 0x25008004 0x01 0x00 0x00 0x25009004 0x01 0x00 0x00 0x2500a004 0x01 0x00 0x00 0x2500b004 0x01 0x00 0x00 0x2500c004 0x01 0x00 0x00 0x2500d004 0x01 0x00 0x00 0x2500e004 0x01 0x00 0x00 0x2500f004 0x01 0x00 0x00 0x25010004 0x01 0x00 0x00 0x25011004 0x01 0x00 0x00 0x25012004 0x01 0x00 0x00 0x25013004 0x01 0x00 0x00 0x25014004 0x01 0x00 0x00 0x25015004 0x01 0x00 0x00 0x25016004 0x01 0x00 0x00 0x25017004 0x01 0x00 0x00 0x25018004 0x01 0x00 0x00 0x25019004 0x01 0x00 0x00 0x2501a004 0x01 0x00 0x00 0x2501b004 0x01 0x00 0x00 0x2501c004 0x01 0x00 0x00 0x2501d004 0x01 0x00 0x00 0x2501e004 0x01 0x00 0x00 0x2501f004 0x01 0x00 0x00 0x25201004 0x01 0x00 0x00 0x25200004 0x01 0x00 0x00 0x25203004 0x01 0x00 0x00 0x25204004 0x01 0x00 0x00 0x25202004 0x01 0x00 0x00 0x25205004 0x01 0x00 0x00 0x25206004 0x01 0x00 0x00 0x25207004 0x01 0x00 0x00 0x25208004 0x01 0x00 0x00 0x25209004 0x01 0x00 0x00 0x2520a004 0x01 0x00 0x00 0x2520b004 0x01 0x00 0x00 0x2520c004 0x01 0x00 0x00 0x2520d004 0x01 0x00 0x00 0x2520e004 0x01 0x00 0x00 0x2520f004 0x01 0x00 0x00 0x25210004 0x01 0x00 0x00 0x25211004 0x01 0x00 0x00 0x25212004 0x01 0x00 0x00 0x25213004 0x01 0x00 0x00 0x25214004 0x01 0x00 0x00 0x25215004 0x01 0x00 0x00 0x25216004 0x01 0x00 0x00 0x25217004 0x01 0x00 0x00 0x25218004 0x01 0x00 0x00 0x25219004 0x01 0x00 0x00 0x2521a004 0x01 0x00 0x00 0x2521b004 0x01 0x00 0x00 0x2521c004 0x01 0x00 0x00 0x2521d004 0x01 0x00 0x00 0x2521e004 0x01 0x00 0x00 0x2521f004 0x01 0x00 0x00 0x25401004 0x01 0x00 0x00 0x25400004 0x01 0x00 0x00 0x25403004 0x01 0x00 0x00 0x25404004 0x01 0x00 0x00 0x25402004 0x01 0x00 0x00 0x25405004 0x01 0x00 0x00 0x25406004 0x01 0x00 0x00 0x25407004 0x01 0x00 0x00 0x25408004 0x01 0x00 0x00 0x25409004 0x01 0x00 0x00 0x2540a004 0x01 0x00 0x00 0x2540b004 0x01 0x00 0x00 0x2540c004 0x01 0x00 0x00 0x2540d004 0x01 0x00 0x00 0x2540e004 0x01 0x00 0x00 0x2540f004 0x01 0x00 0x00 0x25410004 0x01 0x00 0x00 0x25411004 0x01 0x00 0x00 0x25412004 0x01 0x00 0x00 0x25413004 0x01 0x00 0x00 0x25414004 0x01 0x00 0x00 0x25415004 0x01 0x00 0x00 0x25416004 0x01 0x00 0x00 0x25417004 0x01 0x00 0x00 0x25418004 0x01 0x00 0x00 0x25419004 0x01 0x00 0x00 0x2541a004 0x01 0x00 0x00 0x2541b004 0x01 0x00 0x00 0x2541c004 0x01 0x00 0x00 0x2541d004 0x01 0x00 0x00 0x2541e004 0x01 0x00 0x00 0x2541f004 0x01 0x00 0x00 0x25601004 0x01 0x00 0x00 0x25600004 0x01 0x00 0x00 0x25603004 0x01 0x00 0x00 0x25604004 0x01 0x00 0x00 0x25602004 0x01 0x00 0x00 0x25605004 0x01 0x00 0x00 0x25606004 0x01 0x00 0x00 0x25607004 0x01 0x00 0x00 0x25608004 0x01 0x00 0x00 0x25609004 0x01 0x00 0x00 0x2560a004 0x01 0x00 0x00 0x2560b004 0x01 0x00 0x00 0x2560c004 0x01 0x00 0x00 0x2560d004 0x01 0x00 0x00 0x2560e004 0x01 0x00 0x00 0x2560f004 0x01 0x00 0x00 0x25610004 0x01 0x00 0x00 0x25611004 0x01 0x00 0x00 0x25612004 0x01 0x00 0x00 0x25613004 0x01 0x00 0x00 0x25614004 0x01 0x00 0x00 0x25615004 0x01 0x00 0x00 0x25616004 0x01 0x00 0x00 0x25617004 0x01 0x00 0x00 0x25618004 0x01 0x00 0x00 0x25619004 0x01 0x00 0x00 0x2561a004 0x01 0x00 0x00 0x2561b004 0x01 0x00 0x00 0x2561c004 0x01 0x00 0x00 0x2561d004 0x01 0x00 0x00 0x2561e004 0x01 0x00 0x00 0x2561f004 0x01 0x00 0x00 0x250a002c 0x01 0x00 0x00 0x250a009c 0x01 0x00 0x00 0x250a00a0 0x01 0x00 0x00 0x250a00a8 0x01 0x00 0x00 0x250a00ac 0x01 0x00 0x00 0x250a00b0 0x01 0x00 0x00 0x250a00b8 0x01 0x00 0x00 0x250a00c0 0x01 0x00 0x00 0x250a00c4 0x01 0x00 0x00 0x250a00cc 0x01 0x00 0x00 0x250a00d0 0x01 0x00 0x00 0x250a00d4 0x01 0x00 0x00 0x250a00d8 0x01 0x00 0x00 0x250a00e0 0x01 0x00 0x00 0x250a00e8 0x01 0x00 0x00 0x250a00f0 0x01 0x00 0x00 0x250a00f0 0x01 0x00 0x00 0x250a0100 0x01 0x00 0x00 0x250a0108 0x01 0x00 0x00 0x250a0110 0x01 0x00 0x00 0x250a0118 0x01 0x00 0x00 0x250a0120 0x01 0x00 0x00 0x250a0128 0x01 0x00 0x00 0x250a1010 0x01 0x00 0x00 0x250a1070 0x01 0x00 0x00 0x250a3004 0x01 0x00 0x00 0x254a002c 0x01 0x00 0x00 0x254a009c 0x01 0x00 0x00 0x254a00a0 0x01 0x00 0x00 0x254a00a8 0x01 0x00 0x00 0x254a00ac 0x01 0x00 0x00 0x254a00b0 0x01 0x00 0x00 0x254a00b8 0x01 0x00 0x00 0x254a00c0 0x01 0x00 0x00 0x254a00c4 0x01 0x00 0x00 0x254a00cc 0x01 0x00 0x00 0x254a00d0 0x01 0x00 0x00 0x254a00d4 0x01 0x00 0x00 0x254a00d8 0x01 0x00 0x00 0x254a00e0 0x01 0x00 0x00 0x254a00e8 0x01 0x00 0x00 0x254a00f0 0x01 0x00 0x00 0x254a00f0 0x01 0x00 0x00 0x254a0100 0x01 0x00 0x00 0x254a0108 0x01 0x00 0x00 0x254a0110 0x01 0x00 0x00 0x254a0118 0x01 0x00 0x00 0x254a0120 0x01 0x00 0x00 0x254a0128 0x01 0x00 0x00 0x254a1010 0x01 0x00 0x00 0x254a1070 0x01 0x00 0x00 0x254a3004 0x01 0x00 0x00 0x252a002c 0x01 0x00 0x00 0x252a009c 0x01 0x00 0x00 0x252a00a0 0x01 0x00 0x00 0x252a00a8 0x01 0x00 0x00 0x252a00ac 0x01 0x00 0x00 0x252a00b0 0x01 0x00 0x00 0x252a00b8 0x01 0x00 0x00 0x252a00c0 0x01 0x00 0x00 0x252a00c4 0x01 0x00 0x00 0x252a00cc 0x01 0x00 0x00 0x252a00d0 0x01 0x00 0x00 0x252a00d4 0x01 0x00 0x00 0x252a00d8 0x01 0x00 0x00 0x252a00e0 0x01 0x00 0x00 0x252a00e8 0x01 0x00 0x00 0x252a00f0 0x01 0x00 0x00 0x252a00f0 0x01 0x00 0x00 0x252a0100 0x01 0x00 0x00 0x252a0108 0x01 0x00 0x00 0x252a0110 0x01 0x00 0x00 0x252a0118 0x01 0x00 0x00 0x252a0120 0x01 0x00 0x00 0x252a0128 0x01 0x00 0x00 0x252a1010 0x01 0x00 0x00 0x252a1070 0x01 0x00 0x00 0x252a3004 0x01 0x00 0x00 0x256a002c 0x01 0x00 0x00 0x256a009c 0x01 0x00 0x00 0x256a00a0 0x01 0x00 0x00 0x256a00a8 0x01 0x00 0x00 0x256a00ac 0x01 0x00 0x00 0x256a00b0 0x01 0x00 0x00 0x256a00b8 0x01 0x00 0x00 0x256a00c0 0x01 0x00 0x00 0x256a00c4 0x01 0x00 0x00 0x256a00cc 0x01 0x00 0x00 0x256a00d0 0x01 0x00 0x00 0x256a00d4 0x01 0x00 0x00 0x256a00d8 0x01 0x00 0x00 0x256a00e0 0x01 0x00 0x00 0x256a00e8 0x01 0x00 0x00 0x256a00f0 0x01 0x00 0x00 0x256a00f0 0x01 0x00 0x00 0x256a0100 0x01 0x00 0x00 0x256a0108 0x01 0x00 0x00 0x256a0110 0x01 0x00 0x00 0x256a0118 0x01 0x00 0x00 0x256a0120 0x01 0x00 0x00 0x256a0128 0x01 0x00 0x00 0x256a1010 0x01 0x00 0x00 0x256a1070 0x01 0x00 0x00 0x256a3004 0x01 0x00 0x00 0x2507601c 0x01 0x00 0x00 0x25076020 0x01 0x00 0x00 0x25076024 0x01 0x00 0x00 0x25076028 0x01 0x00 0x00 0x25076034 0x01 0x00 0x00 0x25076038 0x01 0x00 0x00 0x2507603c 0x01 0x00 0x00 0x25076040 0x01 0x00 0x00 0x25076058 0x01 0x00 0x00 0x25076060 0x01 0x00 0x00 0x25076064 0x01 0x00 0x00 0x25076200 0x01 0x00 0x00 0x25077020 0x01 0x00 0x00 0x25077030 0x01 0x00 0x00 0x25077034 0x01 0x00 0x00 0x25077038 0x01 0x00 0x00 0x2507703c 0x01 0x00 0x00 0x25077040 0x01 0x00 0x00 0x25077044 0x01 0x00 0x00 0x25077048 0x01 0x00 0x00 0x2507704c 0x01 0x00 0x00 0x25077050 0x01 0x00 0x00 0x25077054 0x01 0x00 0x00 0x25077058 0x01 0x00 0x00 0x2507705c 0x01 0x00 0x00 0x25077060 0x01 0x00 0x00 0x25077064 0x01 0x00 0x00 0x25077068 0x01 0x00 0x00 0x2507706c 0x01 0x00 0x00 0x25077070 0x01 0x00 0x00 0x25077074 0x01 0x00 0x00 0x25077078 0x01 0x00 0x00 0x2507707c 0x01 0x00 0x00 0x25077084 0x01 0x00 0x00 0x25077090 0x01 0x00 0x00 0x25077094 0x01 0x00 0x00 0x25077098 0x01 0x00 0x00 0x2507709c 0x01 0x00 0x00 0x250770a0 0x01 0x00 0x00 0x25077218 0x01 0x00 0x00 0x2507721c 0x01 0x00 0x00 0x25077220 0x01 0x00 0x00 0x25077224 0x01 0x00 0x00 0x25077228 0x01 0x00 0x00 0x2507722c 0x01 0x00 0x00 0x25077230 0x01 0x00 0x00 0x25077234 0x01 0x00 0x00 0x2547601c 0x01 0x00 0x00 0x25476020 0x01 0x00 0x00 0x25476024 0x01 0x00 0x00 0x25476028 0x01 0x00 0x00 0x25476034 0x01 0x00 0x00 0x25476038 0x01 0x00 0x00 0x2547603c 0x01 0x00 0x00 0x25476040 0x01 0x00 0x00 0x25476058 0x01 0x00 0x00 0x25476060 0x01 0x00 0x00 0x25476064 0x01 0x00 0x00 0x25476200 0x01 0x00 0x00 0x25477020 0x01 0x00 0x00 0x25477030 0x01 0x00 0x00 0x25477034 0x01 0x00 0x00 0x25477038 0x01 0x00 0x00 0x2547703c 0x01 0x00 0x00 0x25477040 0x01 0x00 0x00 0x25477044 0x01 0x00 0x00 0x25477048 0x01 0x00 0x00 0x2547704c 0x01 0x00 0x00 0x25477050 0x01 0x00 0x00 0x25477054 0x01 0x00 0x00 0x25477058 0x01 0x00 0x00 0x2547705c 0x01 0x00 0x00 0x25477060 0x01 0x00 0x00 0x25477064 0x01 0x00 0x00 0x25477068 0x01 0x00 0x00 0x2547706c 0x01 0x00 0x00 0x25477070 0x01 0x00 0x00 0x25477074 0x01 0x00 0x00 0x25477078 0x01 0x00 0x00 0x2547707c 0x01 0x00 0x00 0x25477084 0x01 0x00 0x00 0x25477090 0x01 0x00 0x00 0x25477094 0x01 0x00 0x00 0x25477098 0x01 0x00 0x00 0x2547709c 0x01 0x00 0x00 0x254770a0 0x01 0x00 0x00 0x25477218 0x01 0x00 0x00 0x2547721c 0x01 0x00 0x00 0x25477220 0x01 0x00 0x00 0x25477224 0x01 0x00 0x00 0x25477228 0x01 0x00 0x00 0x2547722c 0x01 0x00 0x00 0x25477230 0x01 0x00 0x00 0x25477234 0x01 0x00 0x00 0x2527601c 0x01 0x00 0x00 0x25276020 0x01 0x00 0x00 0x25276024 0x01 0x00 0x00 0x25276028 0x01 0x00 0x00 0x25276034 0x01 0x00 0x00 0x25276038 0x01 0x00 0x00 0x2527603c 0x01 0x00 0x00 0x25276040 0x01 0x00 0x00 0x25276058 0x01 0x00 0x00 0x25276060 0x01 0x00 0x00 0x25276064 0x01 0x00 0x00 0x25276200 0x01 0x00 0x00 0x25277020 0x01 0x00 0x00 0x25277030 0x01 0x00 0x00 0x25277034 0x01 0x00 0x00 0x25277038 0x01 0x00 0x00 0x2527703c 0x01 0x00 0x00 0x25277040 0x01 0x00 0x00 0x25277044 0x01 0x00 0x00 0x25277048 0x01 0x00 0x00 0x2527704c 0x01 0x00 0x00 0x25277050 0x01 0x00 0x00 0x25277054 0x01 0x00 0x00 0x25277058 0x01 0x00 0x00 0x2527705c 0x01 0x00 0x00 0x25277060 0x01 0x00 0x00 0x25277064 0x01 0x00 0x00 0x25277068 0x01 0x00 0x00 0x2527706c 0x01 0x00 0x00 0x25277070 0x01 0x00 0x00 0x25277074 0x01 0x00 0x00 0x25277078 0x01 0x00 0x00 0x2527707c 0x01 0x00 0x00 0x25277084 0x01 0x00 0x00 0x25277090 0x01 0x00 0x00 0x25277094 0x01 0x00 0x00 0x25277098 0x01 0x00 0x00 0x2527709c 0x01 0x00 0x00 0x252770a0 0x01 0x00 0x00 0x25277218 0x01 0x00 0x00 0x2527721c 0x01 0x00 0x00 0x25277220 0x01 0x00 0x00 0x25277224 0x01 0x00 0x00 0x25277228 0x01 0x00 0x00 0x2527722c 0x01 0x00 0x00 0x25277230 0x01 0x00 0x00 0x25277234 0x01 0x00 0x00 0x2567601c 0x01 0x00 0x00 0x25676020 0x01 0x00 0x00 0x25676024 0x01 0x00 0x00 0x25676028 0x01 0x00 0x00 0x25676034 0x01 0x00 0x00 0x25676038 0x01 0x00 0x00 0x2567603c 0x01 0x00 0x00 0x25676040 0x01 0x00 0x00 0x25676058 0x01 0x00 0x00 0x25676060 0x01 0x00 0x00 0x25676064 0x01 0x00 0x00 0x25676200 0x01 0x00 0x00 0x25677020 0x01 0x00 0x00 0x25677030 0x01 0x00 0x00 0x25677034 0x01 0x00 0x00 0x25677038 0x01 0x00 0x00 0x2567703c 0x01 0x00 0x00 0x25677040 0x01 0x00 0x00 0x25677044 0x01 0x00 0x00 0x25677048 0x01 0x00 0x00 0x2567704c 0x01 0x00 0x00 0x25677050 0x01 0x00 0x00 0x25677054 0x01 0x00 0x00 0x25677058 0x01 0x00 0x00 0x2567705c 0x01 0x00 0x00 0x25677060 0x01 0x00 0x00 0x25677064 0x01 0x00 0x00 0x25677068 0x01 0x00 0x00 0x2567706c 0x01 0x00 0x00 0x25677070 0x01 0x00 0x00 0x25677074 0x01 0x00 0x00 0x25677078 0x01 0x00 0x00 0x2567707c 0x01 0x00 0x00 0x25677084 0x01 0x00 0x00 0x25677090 0x01 0x00 0x00 0x25677094 0x01 0x00 0x00 0x25677098 0x01 0x00 0x00 0x2567709c 0x01 0x00 0x00 0x256770a0 0x01 0x00 0x00 0x25677218 0x01 0x00 0x00 0x2567721c 0x01 0x00 0x00 0x25677220 0x01 0x00 0x00 0x25677224 0x01 0x00 0x00 0x25677228 0x01 0x00 0x00 0x2567722c 0x01 0x00 0x00 0x25677230 0x01 0x00 0x00 0x25677234 0x01 0x00 0x00 0x250a6008 0x01 0x00 0x00 0x250a600c 0x01 0x00 0x00 0x250a6010 0x01 0x00 0x00 0x250a7008 0x01 0x00 0x00 0x250a700c 0x01 0x00 0x00 0x250a7010 0x01 0x00 0x00 0x254a6008 0x01 0x00 0x00 0x254a600c 0x01 0x00 0x00 0x254a6010 0x01 0x00 0x00 0x254a7008 0x01 0x00 0x00 0x254a700c 0x01 0x00 0x00 0x254a7010 0x01 0x00 0x00 0x252a6008 0x01 0x00 0x00 0x252a600c 0x01 0x00 0x00 0x252a6010 0x01 0x00 0x00 0x252a7008 0x01 0x00 0x00 0x252a700c 0x01 0x00 0x00 0x252a7010 0x01 0x00 0x00 0x256a6008 0x01 0x00 0x00 0x256a600c 0x01 0x00 0x00 0x256a6010 0x01 0x00 0x00 0x256a7008 0x01 0x00 0x00 0x256a700c 0x01 0x00 0x00 0x256a7010 0x01 0x00 0x00 0x2507718c 0x01 0x00 0x00 0x250771b0 0x01 0x00 0x00 0x25077204 0x01 0x00 0x00 0x25077208 0x01 0x00 0x00 0x2507720c 0x01 0x00 0x00 0x25077210 0x01 0x00 0x00 0x25077214 0x01 0x00 0x00 0x25023210 0x01 0x00 0x00 0x25025010 0x01 0x00 0x00 0x25025000 0x01 0x00 0x00 0x25040064 0x01 0x00 0x00 0x25040070 0x01 0x00 0x00 0x25040074 0x01 0x00 0x00 0x25040078 0x01 0x00 0x00 0x2504007c 0x01 0x00 0x00 0x25040080 0x01 0x00 0x00 0x2504002c 0x01 0x00 0x00 0x25040030 0x01 0x00 0x00 0x25040034 0x01 0x00 0x00 0x25040038 0x01 0x00 0x00 0x25040048 0x01 0x00 0x00 0x2504004c 0x01 0x00 0x00 0x25040050 0x01 0x00 0x00 0x25040054 0x01 0x00 0x00 0x25040058 0x01 0x00 0x00 0x25040060 0x01 0x00 0x00 0x2547718c 0x01 0x00 0x00 0x254771b0 0x01 0x00 0x00 0x25477204 0x01 0x00 0x00 0x25477208 0x01 0x00 0x00 0x2547720c 0x01 0x00 0x00 0x25477210 0x01 0x00 0x00 0x25477214 0x01 0x00 0x00 0x25423210 0x01 0x00 0x00 0x25425010 0x01 0x00 0x00 0x25425000 0x01 0x00 0x00 0x25440064 0x01 0x00 0x00 0x25440070 0x01 0x00 0x00 0x25440074 0x01 0x00 0x00 0x25440078 0x01 0x00 0x00 0x2544007c 0x01 0x00 0x00 0x25440080 0x01 0x00 0x00 0x2544002c 0x01 0x00 0x00 0x25440030 0x01 0x00 0x00 0x25440034 0x01 0x00 0x00 0x25440038 0x01 0x00 0x00 0x25440048 0x01 0x00 0x00 0x2544004c 0x01 0x00 0x00 0x25440050 0x01 0x00 0x00 0x25440054 0x01 0x00 0x00 0x25440058 0x01 0x00 0x00 0x25440060 0x01 0x00 0x00 0x2527718c 0x01 0x00 0x00 0x252771b0 0x01 0x00 0x00 0x25277204 0x01 0x00 0x00 0x25277208 0x01 0x00 0x00 0x2527720c 0x01 0x00 0x00 0x25277210 0x01 0x00 0x00 0x25277214 0x01 0x00 0x00 0x25223210 0x01 0x00 0x00 0x25225010 0x01 0x00 0x00 0x25225000 0x01 0x00 0x00 0x25240064 0x01 0x00 0x00 0x25240070 0x01 0x00 0x00 0x25240074 0x01 0x00 0x00 0x25240078 0x01 0x00 0x00 0x2524007c 0x01 0x00 0x00 0x25240080 0x01 0x00 0x00 0x2524002c 0x01 0x00 0x00 0x25240030 0x01 0x00 0x00 0x25240034 0x01 0x00 0x00 0x25240038 0x01 0x00 0x00 0x25240048 0x01 0x00 0x00 0x2524004c 0x01 0x00 0x00 0x25240050 0x01 0x00 0x00 0x25240054 0x01 0x00 0x00 0x25240058 0x01 0x00 0x00 0x25240060 0x01 0x00 0x00 0x2567718c 0x01 0x00 0x00 0x256771b0 0x01 0x00 0x00 0x25677204 0x01 0x00 0x00 0x25677208 0x01 0x00 0x00 0x2567720c 0x01 0x00 0x00 0x25677210 0x01 0x00 0x00 0x25677214 0x01 0x00 0x00 0x25623210 0x01 0x00 0x00 0x25625010 0x01 0x00 0x00 0x25625000 0x01 0x00 0x00 0x25640064 0x01 0x00 0x00 0x25640070 0x01 0x00 0x00 0x25640074 0x01 0x00 0x00 0x25640078 0x01 0x00 0x00 0x2564007c 0x01 0x00 0x00 0x25640080 0x01 0x00 0x00 0x2564002c 0x01 0x00 0x00 0x25640030 0x01 0x00 0x00 0x25640034 0x01 0x00 0x00 0x25640038 0x01 0x00 0x00 0x25640048 0x01 0x00 0x00 0x2564004c 0x01 0x00 0x00 0x25640050 0x01 0x00 0x00 0x25640054 0x01 0x00 0x00 0x25640058 0x01 0x00 0x00 0x25640060 0x01 0x00 0x00 0x250a9004 0x01 0x00 0x00 0x250a9010 0x01 0x00 0x00 0x250a9014 0x01 0x00 0x00 0x250a9018 0x01 0x00 0x00 0x250a9020 0x01 0x00 0x00 0x250a9024 0x01 0x00 0x00 0x250a9028 0x01 0x00 0x00 0x250a9030 0x01 0x00 0x00 0x250a9034 0x01 0x00 0x00 0x250a9038 0x01 0x00 0x00 0x250a9040 0x01 0x00 0x00 0x250a9044 0x01 0x00 0x00 0x250a9048 0x01 0x00 0x00 0x250a9050 0x01 0x00 0x00 0x250a9054 0x01 0x00 0x00 0x250a9058 0x01 0x00 0x00 0x250aa004 0x01 0x00 0x00 0x250aa010 0x01 0x00 0x00 0x250aa014 0x01 0x00 0x00 0x250aa018 0x01 0x00 0x00 0x250aa020 0x01 0x00 0x00 0x250aa024 0x01 0x00 0x00 0x250aa028 0x01 0x00 0x00 0x250aa030 0x01 0x00 0x00 0x250aa034 0x01 0x00 0x00 0x250aa038 0x01 0x00 0x00 0x250aa040 0x01 0x00 0x00 0x250aa044 0x01 0x00 0x00 0x250aa048 0x01 0x00 0x00 0x250aa050 0x01 0x00 0x00 0x250aa054 0x01 0x00 0x00 0x250aa058 0x01 0x00 0x00 0x250b001c 0x01 0x00 0x00 0x250b101c 0x01 0x00 0x00 0x250b201c 0x01 0x00 0x00 0x250b301c 0x01 0x00 0x00 0x250b401c 0x01 0x00 0x00 0x250b501c 0x01 0x00 0x00 0x250b601c 0x01 0x00 0x00 0x250b701c 0x01 0x00 0x00 0x250b801c 0x01 0x00 0x00 0x250b901c 0x01 0x00 0x00 0x250ba01c 0x01 0x00 0x00 0x250bb01c 0x01 0x00 0x00 0x250bc01c 0x01 0x00 0x00 0x250bd01c 0x01 0x00 0x00 0x250be01c 0x01 0x00 0x00 0x250bf01c 0x01 0x00 0x00 0x254a9004 0x01 0x00 0x00 0x254a9010 0x01 0x00 0x00 0x254a9014 0x01 0x00 0x00 0x254a9018 0x01 0x00 0x00 0x254a9020 0x01 0x00 0x00 0x254a9024 0x01 0x00 0x00 0x254a9028 0x01 0x00 0x00 0x254a9030 0x01 0x00 0x00 0x254a9034 0x01 0x00 0x00 0x254a9038 0x01 0x00 0x00 0x254a9040 0x01 0x00 0x00 0x254a9044 0x01 0x00 0x00 0x254a9048 0x01 0x00 0x00 0x254a9050 0x01 0x00 0x00 0x254a9054 0x01 0x00 0x00 0x254a9058 0x01 0x00 0x00 0x254aa004 0x01 0x00 0x00 0x254aa010 0x01 0x00 0x00 0x254aa014 0x01 0x00 0x00 0x254aa018 0x01 0x00 0x00 0x254aa020 0x01 0x00 0x00 0x254aa024 0x01 0x00 0x00 0x254aa028 0x01 0x00 0x00 0x254aa030 0x01 0x00 0x00 0x254aa034 0x01 0x00 0x00 0x254aa038 0x01 0x00 0x00 0x254aa040 0x01 0x00 0x00 0x254aa044 0x01 0x00 0x00 0x254aa048 0x01 0x00 0x00 0x254aa050 0x01 0x00 0x00 0x254aa054 0x01 0x00 0x00 0x254aa058 0x01 0x00 0x00 0x254b001c 0x01 0x00 0x00 0x254b101c 0x01 0x00 0x00 0x254b201c 0x01 0x00 0x00 0x254b301c 0x01 0x00 0x00 0x254b401c 0x01 0x00 0x00 0x254b501c 0x01 0x00 0x00 0x254b601c 0x01 0x00 0x00 0x254b701c 0x01 0x00 0x00 0x254b801c 0x01 0x00 0x00 0x254b901c 0x01 0x00 0x00 0x254ba01c 0x01 0x00 0x00 0x254bb01c 0x01 0x00 0x00 0x254bc01c 0x01 0x00 0x00 0x254bd01c 0x01 0x00 0x00 0x254be01c 0x01 0x00 0x00 0x254bf01c 0x01 0x00 0x00 0x252a9004 0x01 0x00 0x00 0x252a9010 0x01 0x00 0x00 0x252a9014 0x01 0x00 0x00 0x252a9018 0x01 0x00 0x00 0x252a9020 0x01 0x00 0x00 0x252a9024 0x01 0x00 0x00 0x252a9028 0x01 0x00 0x00 0x252a9030 0x01 0x00 0x00 0x252a9034 0x01 0x00 0x00 0x252a9038 0x01 0x00 0x00 0x252a9040 0x01 0x00 0x00 0x252a9044 0x01 0x00 0x00 0x252a9048 0x01 0x00 0x00 0x252a9050 0x01 0x00 0x00 0x252a9054 0x01 0x00 0x00 0x252a9058 0x01 0x00 0x00 0x252aa004 0x01 0x00 0x00 0x252aa010 0x01 0x00 0x00 0x252aa014 0x01 0x00 0x00 0x252aa018 0x01 0x00 0x00 0x252aa020 0x01 0x00 0x00 0x252aa024 0x01 0x00 0x00 0x252aa028 0x01 0x00 0x00 0x252aa030 0x01 0x00 0x00 0x252aa034 0x01 0x00 0x00 0x252aa038 0x01 0x00 0x00 0x252aa040 0x01 0x00 0x00 0x252aa044 0x01 0x00 0x00 0x252aa048 0x01 0x00 0x00 0x252aa050 0x01 0x00 0x00 0x252aa054 0x01 0x00 0x00 0x252aa058 0x01 0x00 0x00 0x252b001c 0x01 0x00 0x00 0x252b101c 0x01 0x00 0x00 0x252b201c 0x01 0x00 0x00 0x252b301c 0x01 0x00 0x00 0x252b401c 0x01 0x00 0x00 0x252b501c 0x01 0x00 0x00 0x252b601c 0x01 0x00 0x00 0x252b701c 0x01 0x00 0x00 0x252b801c 0x01 0x00 0x00 0x252b901c 0x01 0x00 0x00 0x252ba01c 0x01 0x00 0x00 0x252bb01c 0x01 0x00 0x00 0x252bc01c 0x01 0x00 0x00 0x252bd01c 0x01 0x00 0x00 0x252be01c 0x01 0x00 0x00 0x252bf01c 0x01 0x00 0x00 0x256a9004 0x01 0x00 0x00 0x256a9010 0x01 0x00 0x00 0x256a9014 0x01 0x00 0x00 0x256a9018 0x01 0x00 0x00 0x256a9020 0x01 0x00 0x00 0x256a9024 0x01 0x00 0x00 0x256a9028 0x01 0x00 0x00 0x256a9030 0x01 0x00 0x00 0x256a9034 0x01 0x00 0x00 0x256a9038 0x01 0x00 0x00 0x256a9040 0x01 0x00 0x00 0x256a9044 0x01 0x00 0x00 0x256a9048 0x01 0x00 0x00 0x256a9050 0x01 0x00 0x00 0x256a9054 0x01 0x00 0x00 0x256a9058 0x01 0x00 0x00 0x256aa004 0x01 0x00 0x00 0x256aa010 0x01 0x00 0x00 0x256aa014 0x01 0x00 0x00 0x256aa018 0x01 0x00 0x00 0x256aa020 0x01 0x00 0x00 0x256aa024 0x01 0x00 0x00 0x256aa028 0x01 0x00 0x00 0x256aa030 0x01 0x00 0x00 0x256aa034 0x01 0x00 0x00 0x256aa038 0x01 0x00 0x00 0x256aa040 0x01 0x00 0x00 0x256aa044 0x01 0x00 0x00 0x256aa048 0x01 0x00 0x00 0x256aa050 0x01 0x00 0x00 0x256aa054 0x01 0x00 0x00 0x256aa058 0x01 0x00 0x00 0x256b001c 0x01 0x00 0x00 0x256b101c 0x01 0x00 0x00 0x256b201c 0x01 0x00 0x00 0x256b301c 0x01 0x00 0x00 0x256b401c 0x01 0x00 0x00 0x256b501c 0x01 0x00 0x00 0x256b601c 0x01 0x00 0x00 0x256b701c 0x01 0x00 0x00 0x256b801c 0x01 0x00 0x00 0x256b901c 0x01 0x00 0x00 0x256ba01c 0x01 0x00 0x00 0x256bb01c 0x01 0x00 0x00 0x256bc01c 0x01 0x00 0x00 0x256bd01c 0x01 0x00 0x00 0x256be01c 0x01 0x00 0x00 0x256bf01c 0x01 0x00 0x00 0x258a4040 0x01 0x00 0x00 0x258a4044 0x01 0x00 0x00 0x258a4048 0x01 0x00 0x00 0x258a404c 0x01 0x00 0x00 0x258a4050 0x01 0x00 0x00 0x258a4054 0x01 0x00 0x00 0x258a4058 0x01 0x00 0x00 0x258a405c 0x01 0x00 0x00 0x258a4060 0x01 0x00 0x00 0x258a4064 0x01 0x00 0x00 0x258a4068 0x01 0x00 0x00 0x258a406c 0x01 0x00 0x00 0x258a4070 0x01 0x00 0x00 0x258a4074 0x01 0x00 0x00 0x258a4078 0x01 0x00 0x00 0x258a407c 0x01 0x00 0x00 0x258a4080 0x01 0x00 0x00 0x258a4084 0x01 0x00 0x00 0x258a4088 0x01 0x00 0x00 0x258a408c 0x01 0x00 0x00 0x258a4090 0x01 0x00 0x00 0x258a4094 0x01 0x00 0x00 0x258a4098 0x01 0x00 0x00 0x258a409c 0x01 0x00 0x00 0x258a40a0 0x01 0x00 0x00 0x258a40a4 0x01 0x00 0x00 0x258a40a8 0x01 0x00 0x00 0x258a40ac 0x01 0x00 0x00 0x258a40b0 0x01 0x00 0x00 0x258a40b4 0x01 0x00 0x00 0x258a40b8 0x01 0x00 0x00 0x258a40bc 0x01 0x00 0x00 0x258a40c0 0x01 0x00 0x00 0x258a40c4 0x01 0x00 0x00 0x258a40c8 0x01 0x00 0x00 0x258a40cc 0x01 0x00 0x00 0x258a40d0 0x01 0x00 0x00 0x258a40d4 0x01 0x00 0x00 0x258a40d8 0x01 0x00 0x00 0x258a40dc 0x01 0x00 0x00 0x258a40e0 0x01 0x00 0x00 0x258a40e4 0x01 0x00 0x00 0x258a40e8 0x01 0x00 0x00 0x258a40ec 0x01 0x00 0x00 0x258a40f0 0x01 0x00 0x00 0x258a40f4 0x01 0x00 0x00 0x258a40f8 0x01 0x00 0x00 0x258a40fc 0x01 0x00 0x00 0x258b0000 0x01 0x00 0x00 0x258b1000 0x01 0x00 0x00 0x258b2000 0x01 0x00 0x00 0x258b3000 0x01 0x00 0x00 0x258b4000 0x01 0x00 0x00 0x258b5000 0x01 0x00 0x00 0x258b6000 0x01 0x00 0x00 0x258b7000 0x01 0x00 0x00 0x258b8000 0x01 0x00 0x00 0x258b9000 0x01 0x00 0x00 0x258ba000 0x01 0x00 0x00 0x258bb000 0x01 0x00 0x00 0x258bc000 0x01 0x00 0x00 0x258bd000 0x01 0x00 0x00 0x258be000 0x01 0x00 0x00 0x258bf000 0x01 0x00 0x00 0x258b005c 0x01 0x00 0x00 0x258b105c 0x01 0x00 0x00 0x258b205c 0x01 0x00 0x00 0x258b305c 0x01 0x00 0x00 0x258b405c 0x01 0x00 0x00 0x258b505c 0x01 0x00 0x00 0x258b605c 0x01 0x00 0x00 0x258b705c 0x01 0x00 0x00 0x258b805c 0x01 0x00 0x00 0x258b905c 0x01 0x00 0x00 0x258ba05c 0x01 0x00 0x00 0x258bb05c 0x01 0x00 0x00 0x258bc05c 0x01 0x00 0x00 0x258bd05c 0x01 0x00 0x00 0x258be05c 0x01 0x00 0x00 0x258bf05c 0x01 0x00 0x00 0x32302028 0x01 0x00 0x00 0x320a4404 0x02 0x00 0x00 0x323c0404 0x02 0x00>;
|
|
};
|
|
|
|
link_list_1 {
|
|
qcom,curr-link-list = <0x04>;
|
|
qcom,data-sink = "sram";
|
|
qcom,ap-qad-override;
|
|
qcom,link-list = <0x00 0x240e0010 0x01 0x00 0x00 0x240e0020 0x08 0x00 0x00 0x240e0248 0x01 0x00 0x00 0x245f0010 0x01 0x00 0x00 0x245f0020 0x08 0x00 0x00 0x245f0248 0x01 0x00 0x00 0x247f0010 0x01 0x00 0x00 0x247f0020 0x08 0x00 0x00 0x247f0248 0x01 0x00 0x00 0x24330010 0x01 0x00 0x00 0x24330020 0x08 0x00 0x00 0x24330248 0x01 0x00 0x00 0x240e1018 0x01 0x00 0x00 0x240e1008 0x01 0x00 0x02 0x09 0x00 0x00 0x00 0x240e1010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x245f2018 0x01 0x00 0x00 0x245f2008 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x245f2010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x247f2018 0x01 0x00 0x00 0x247f2008 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x247f2010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x24331018 0x01 0x00 0x00 0x24331008 0x01 0x00 0x02 0x08 0x00 0x00 0x00 0x24331010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x6802028 0x01 0x00 0x00 0x7200408 0x01 0x00 0x00 0x7200404 0x01 0x00 0x00 0x6800000 0x01 0x00 0x00 0x68c0404 0x01 0x00 0x00 0x68c0408 0x01 0x00 0x00 0x1780010 0x01 0x00 0x00 0x1780020 0x08 0x00 0x00 0x1780248 0x01 0x00 0x00 0x1782018 0x01 0x00 0x00 0x1782008 0x01 0x00 0x02 0x0c 0x00 0x00 0x00 0x1782010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1783018 0x01 0x00 0x00 0x1783008 0x01 0x00 0x02 0x11 0x00 0x00 0x00 0x1783010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1680010 0x01 0x00 0x00 0x1680020 0x08 0x00 0x00 0x1681048 0x01 0x00 0x00 0x1682018 0x01 0x00 0x00 0x1682008 0x01 0x00 0x02 0x06 0x00 0x00 0x00 0x1682010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e0010 0x01 0x00 0x00 0x16e0020 0x08 0x00 0x00 0x16e0248 0x01 0x00 0x00 0x16e1018 0x01 0x00 0x00 0x16e1008 0x01 0x00 0x02 0x04 0x00 0x00 0x00 0x16e1010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e1098 0x01 0x00 0x00 0x16e1088 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x16e1090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e1118 0x01 0x00 0x00 0x16e1108 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x16e1110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1700010 0x01 0x00 0x00 0x1700020 0x08 0x00 0x00 0x1700248 0x01 0x00 0x00 0x1701018 0x01 0x00 0x00 0x1701008 0x01 0x00 0x02 0x04 0x00 0x00 0x00 0x1701010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1701098 0x01 0x00 0x00 0x1701088 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1701090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1701118 0x01 0x00 0x00 0x1701108 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1701110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1600010 0x01 0x00 0x00 0x1600020 0x08 0x00 0x00 0x1600248 0x02 0x00 0x00 0x1600258 0x01 0x00 0x00 0x1602018 0x01 0x00 0x00 0x1602008 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1602010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602098 0x01 0x00 0x00 0x1602088 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602118 0x01 0x00 0x00 0x1602108 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1602110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602198 0x01 0x00 0x00 0x1602188 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1602190 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602218 0x01 0x00 0x00 0x1602208 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602210 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602298 0x01 0x00 0x00 0x1602288 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602290 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1500010 0x01 0x00 0x00 0x1500020 0x08 0x00 0x00 0x1500248 0x01 0x00 0x00 0x1500448 0x01 0x00 0x00 0x1502018 0x01 0x00 0x00 0x1502008 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1502010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1502098 0x01 0x00 0x00 0x1502088 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1502090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x17610010 0x01 0x00 0x00 0x17610020 0x08 0x00 0x00 0x17610248 0x01 0x00 0x00 0x17612018 0x01 0x00 0x00 0x17612008 0x01 0x00 0x02 0x06 0x00 0x00 0x00 0x17612010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x17100104 0x1d 0x00 0x00 0x17100204 0x1d 0x00 0x00 0x17100384 0x1d 0x00 0x00 0x178a0250 0x01 0x00 0x00 0x178a0254 0x01 0x00 0x00 0x178a025c 0x01 0x00 0x00 0xb281024 0x01 0x00 0x00 0xbde1034 0x01 0x00 0x00 0xb201020 0x02 0x00 0x00 0xb211020 0x02 0x00 0x00 0xb221020 0x02 0x00 0x00 0xb231020 0x02 0x00 0x00 0xb204520 0x01 0x00 0x00 0x17a00010 0x01 0x00 0x00 0x17a10010 0x01 0x00 0x00 0x17a20010 0x01 0x00 0x00 0x17a30010 0x01 0x00 0x00 0x17a00030 0x01 0x00 0x00 0x17a10030 0x01 0x00 0x00 0x17a20030 0x01 0x00 0x00 0x17a30030 0x01 0x00 0x00 0x17a00038 0x01 0x00 0x00 0x17a10038 0x01 0x00 0x00 0x17a20038 0x01 0x00 0x00 0x17a30038 0x01 0x00 0x00 0x17a00040 0x01 0x00 0x00 0x17a10040 0x01 0x00 0x00 0x17a20040 0x01 0x00 0x00 0x17a30040 0x01 0x00 0x00 0x17a00048 0x01 0x00 0x00 0x17a00400 0x03 0x00 0x00 0x17a10400 0x03 0x00 0x00 0x17a20400 0x03 0x00 0x00 0x17a30400 0x03 0x00 0x00 0xc234004 0x05 0x00 0x02 0x05 0x00 0x00 0x00 0x17410000 0x06 0x00 0x00 0x17411000 0x06 0x00 0x02 0x01 0x00 0x00 0x00 0x17d10200 0x140 0x00 0x00 0x17120000 0x01 0x00 0x00 0x17120008 0x01 0x00 0x00 0x17120010 0x01 0x00 0x00 0x17120018 0x01 0x00 0x00 0x17120020 0x01 0x00 0x00 0x17120028 0x01 0x00 0x00 0x17120040 0x01 0x00 0x00 0x17120048 0x01 0x00 0x00 0x17120050 0x01 0x00 0x00 0x17120058 0x01 0x00 0x00 0x17120060 0x01 0x00 0x00 0x17120068 0x01 0x00 0x00 0x17120080 0x01 0x00 0x00 0x17120088 0x01 0x00 0x00 0x17120090 0x01 0x00 0x00 0x17120098 0x01 0x00 0x00 0x171200a0 0x01 0x00 0x00 0x171200a8 0x01 0x00 0x00 0x171200c0 0x01 0x00 0x00 0x171200c8 0x01 0x00 0x00 0x171200d0 0x01 0x00 0x00 0x171200d8 0x01 0x00 0x00 0x171200e0 0x01 0x00 0x00 0x171200e8 0x01 0x00 0x00 0x17120100 0x01 0x00 0x00 0x17120108 0x01 0x00 0x00 0x17120110 0x01 0x00 0x00 0x17120118 0x01 0x00 0x00 0x17120120 0x01 0x00 0x00 0x17120128 0x01 0x00 0x00 0x17120140 0x01 0x00 0x00 0x17120148 0x01 0x00 0x00 0x17120150 0x01 0x00 0x00 0x17120158 0x01 0x00 0x00 0x17120160 0x01 0x00 0x00 0x17120168 0x01 0x00 0x00 0x17120180 0x01 0x00 0x00 0x17120188 0x01 0x00 0x00 0x17120190 0x01 0x00 0x00 0x17120198 0x01 0x00 0x00 0x171201a0 0x01 0x00 0x00 0x171201a8 0x01 0x00 0x00 0x171201c0 0x01 0x00 0x00 0x171201c8 0x01 0x00 0x00 0x171201d0 0x01 0x00 0x00 0x171201d8 0x01 0x00 0x00 0x171201e0 0x01 0x00 0x00 0x171201e8 0x01 0x00 0x00 0x17120200 0x01 0x00 0x00 0x17120208 0x01 0x00 0x00 0x17120210 0x01 0x00 0x00 0x17120218 0x01 0x00 0x00 0x17120220 0x01 0x00 0x00 0x17120228 0x01 0x00 0x00 0x17120240 0x01 0x00 0x00 0x17120248 0x01 0x00 0x00 0x17120250 0x01 0x00 0x00 0x17120258 0x01 0x00 0x00 0x17120260 0x01 0x00 0x00 0x17120268 0x01 0x00 0x00 0x17120280 0x01 0x00 0x00 0x17120288 0x01 0x00 0x00 0x17120290 0x01 0x00 0x00 0x17120298 0x01 0x00 0x00 0x171202a0 0x01 0x00 0x00 0x171202a8 0x01 0x00 0x00 0x171202c0 0x01 0x00 0x00 0x171202c8 0x01 0x00 0x00 0x171202d0 0x01 0x00 0x00 0x171202d8 0x01 0x00 0x00 0x171202e0 0x01 0x00 0x00 0x171202e8 0x01 0x00 0x00 0x17120300 0x01 0x00 0x00 0x17120308 0x01 0x00 0x00 0x17120310 0x01 0x00 0x00 0x17120318 0x01 0x00 0x00 0x17120320 0x01 0x00 0x00 0x17120328 0x01 0x00 0x00 0x17120340 0x01 0x00 0x00 0x17120348 0x01 0x00 0x00 0x17120350 0x01 0x00 0x00 0x17120358 0x01 0x00 0x00 0x17120360 0x01 0x00 0x00 0x17120368 0x01 0x00 0x00 0x17120380 0x01 0x00 0x00 0x17120388 0x01 0x00 0x00 0x17120390 0x01 0x00 0x00 0x17120398 0x01 0x00 0x00 0x171203a0 0x01 0x00 0x00 0x171203a8 0x01 0x00 0x00 0x171203c0 0x01 0x00 0x00 0x171203c8 0x01 0x00 0x00 0x171203d0 0x01 0x00 0x00 0x171203d8 0x01 0x00 0x00 0x171203e0 0x01 0x00 0x00 0x171203e8 0x01 0x00 0x00 0x17120400 0x01 0x00 0x00 0x17120408 0x01 0x00 0x00 0x17120410 0x01 0x00 0x00 0x17120418 0x01 0x00 0x00 0x17120420 0x01 0x00 0x00 0x17120428 0x01 0x00 0x00 0x17120440 0x01 0x00 0x00 0x17120448 0x01 0x00 0x00 0x17120450 0x01 0x00 0x00 0x17120458 0x01 0x00 0x00 0x17120460 0x01 0x00 0x00 0x17120468 0x01 0x00 0x00 0x17120480 0x01 0x00 0x00 0x17120488 0x01 0x00 0x00 0x17120490 0x01 0x00 0x00 0x17120498 0x01 0x00 0x00 0x171204a0 0x01 0x00 0x00 0x171204a8 0x01 0x00 0x00 0x171204c0 0x01 0x00 0x00 0x171204c8 0x01 0x00 0x00 0x171204d0 0x01 0x00 0x00 0x171204d8 0x01 0x00 0x00 0x171204e0 0x01 0x00 0x00 0x171204e8 0x01 0x00 0x00 0x17120500 0x01 0x00 0x00 0x17120508 0x01 0x00 0x00 0x17120510 0x01 0x00 0x00 0x17120518 0x01 0x00 0x00 0x17120520 0x01 0x00 0x00 0x17120528 0x01 0x00 0x00 0x17120540 0x01 0x00 0x00 0x17120548 0x01 0x00 0x00 0x17120550 0x01 0x00 0x00 0x17120558 0x01 0x00 0x00 0x17120560 0x01 0x00 0x00 0x17120568 0x01 0x00 0x00 0x17120580 0x01 0x00 0x00 0x17120588 0x01 0x00 0x00 0x17120590 0x01 0x00 0x00 0x17120598 0x01 0x00 0x00 0x171205a0 0x01 0x00 0x00 0x171205a8 0x01 0x00 0x00 0x171205c0 0x01 0x00 0x00 0x171205c8 0x01 0x00 0x00 0x171205d0 0x01 0x00 0x00 0x171205d8 0x01 0x00 0x00 0x171205e0 0x01 0x00 0x00 0x171205e8 0x01 0x00 0x00 0x17120600 0x01 0x00 0x00 0x17120608 0x01 0x00 0x00 0x17120610 0x01 0x00 0x00 0x17120618 0x01 0x00 0x00 0x17120620 0x01 0x00 0x00 0x17120628 0x01 0x00 0x00 0x17120640 0x01 0x00 0x00 0x17120648 0x01 0x00 0x00 0x17120650 0x01 0x00 0x00 0x17120658 0x01 0x00 0x00 0x17120660 0x01 0x00 0x00 0x17120668 0x01 0x00 0x00 0x17120680 0x01 0x00 0x00 0x17120688 0x01 0x00 0x00 0x17120690 0x01 0x00 0x00 0x17120698 0x01 0x00 0x00 0x171206a0 0x01 0x00 0x00 0x171206a8 0x01 0x00 0x00 0x171206c0 0x01 0x00 0x00 0x171206c8 0x01 0x00 0x00 0x171206d0 0x01 0x00 0x00 0x171206d8 0x01 0x00 0x00 0x171206e0 0x01 0x00 0x00 0x171206e8 0x01 0x00 0x00 0x1712e000 0x01 0x00 0x00 0x110004 0x01 0x00 0x00 0x110008 0x01 0x00 0x00 0x11003c 0x01 0x00 0x00 0x110040 0x01 0x00 0x00 0x110044 0x01 0x00 0x00 0x17603c 0x01 0x00 0x00 0x17890000 0x01 0x00 0x00 0x17890008 0x01 0x00 0x00 0x1789000c 0x01 0x00 0x00 0x17890010 0x01 0x00 0x00 0x17890014 0x01 0x00 0x00 0x17890018 0x01 0x00 0x00 0x1789001c 0x01 0x00 0x00 0x17890020 0x01 0x00 0x00 0x17890024 0x01 0x00 0x00 0x17890028 0x01 0x00 0x00 0x1789002c 0x01 0x00 0x00 0x17890030 0x01 0x00 0x00 0x17890034 0x01 0x00 0x00 0x17890038 0x01 0x00 0x00 0x1789003c 0x01 0x00 0x00 0x17890040 0x01 0x00 0x00 0x17890044 0x01 0x00 0x00 0x17890048 0x01 0x00 0x00 0x1789004c 0x01 0x00 0x00 0x17890068 0x01 0x00 0x00 0x1789006c 0x01 0x00 0x00 0x178900f0 0x01 0x00 0x00 0x178900f4 0x01 0x00 0x00 0x178900f8 0x01 0x00 0x00 0x178900fc 0x01 0x00 0x00 0x17890100 0x01 0x00 0x00 0x17890104 0x01 0x00 0x00 0x17891000 0x01 0x00 0x00 0x17892000 0x01 0x00 0x00 0x17893000 0x01 0x00 0x00 0x17893004 0x01 0x00 0x00 0x17898000 0x01 0x00 0x00 0x17898004 0x01 0x00 0x00 0x17898008 0x01 0x00 0x00 0x1789800c 0x01 0x00 0x00 0x17898010 0x01 0x00 0x00 0x17898014 0x01 0x00 0x01 0x17891000 0x00 0x00 0x01 0x17892000 0x00 0x00 0x01 0x17893000 0x00 0x00 0x01 0x17893004 0x00 0x00 0x00 0x17891000 0x01 0x00 0x00 0x17892000 0x01 0x00 0x00 0x17893000 0x01 0x00 0x00 0x17893004 0x01 0x00 0x00 0x17980000 0x100 0x00 0x00 0x17980800 0x100 0x00 0x00 0x17981000 0x10 0x00 0x00 0x17981060 0x08 0x00 0x00 0x179810a0 0x01 0x00 0x00 0x179810a4 0x01 0x00 0x00 0x179810b0 0x01 0x00 0x00 0x179810c0 0x01 0x00 0x00 0x179810c4 0x01 0x00 0x00 0x179810c8 0x01 0x00 0x00 0x179810cc 0x01 0x00 0x00 0x17981100 0x01 0x00 0x00 0x17981104 0x01 0x00 0x00 0x17981108 0x01 0x00 0x00 0x1798110c 0x01 0x00 0x00 0x17981110 0x01 0x00 0x00 0x17981114 0x01 0x00 0x00 0x17981118 0x01 0x00 0x00 0x1798111c 0x01 0x00 0x00 0x17981120 0x01 0x00 0x00 0x17981124 0x01 0x00 0x00 0x17981128 0x01 0x00 0x00 0x1798112c 0x01 0x00 0x00 0x17981130 0x01 0x00 0x00 0x17981134 0x01 0x00 0x00 0x17981138 0x01 0x00 0x00 0x1798113c 0x01 0x00 0x00 0x17981140 0x01 0x00 0x00 0x17981144 0x01 0x00 0x00 0x17981148 0x01 0x00 0x00 0x1798114c 0x01 0x00 0x00 0x17981150 0x01 0x00 0x00 0x17981154 0x01 0x00 0x00 0x17981158 0x01 0x00 0x00 0x1798115c 0x01 0x00 0x00 0x17981160 0x01 0x00 0x00 0x17981164 0x01 0x00 0x00 0x17981168 0x01 0x00 0x00 0x1798116c 0x01 0x00 0x00 0x17981170 0x01 0x00 0x00 0x17981174 0x01 0x00 0x00 0x17981178 0x01 0x00 0x00 0x1798117c 0x01 0x00 0x00 0x17981180 0x01 0x00 0x00 0x17981184 0x01 0x00 0x00 0x17981188 0x01 0x00 0x00 0x1798118c 0x01 0x00 0x00 0x17981190 0x01 0x00 0x00 0x17981194 0x01 0x00 0x00 0x17981198 0x01 0x00 0x00 0x1798119c 0x01 0x00 0x00 0x179811a0 0x01 0x00 0x00 0x179811a4 0x01 0x00 0x00 0x179811a8 0x01 0x00 0x00 0x179811ac 0x01 0x00 0x00 0x179811b0 0x01 0x00 0x00 0x179811b4 0x01 0x00 0x00 0x179811b8 0x01 0x00 0x00 0x179811bc 0x01 0x00 0x00 0x179811c0 0x01 0x00 0x00 0x179811c4 0x01 0x00 0x00 0x179811c8 0x01 0x00 0x00 0x179811cc 0x01 0x00 0x00 0x179811d0 0x01 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x00 0x17981ffc 0x01 0x00 0x01 0x179811d4 0x00 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x01 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x02 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x03 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x04 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x05 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x06 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x07 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x08 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x09 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x0a 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x0b 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x0c 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x0d 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x0e 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x0f 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x10 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x11 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x12 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x01 0x179811d4 0x13 0x00 0x00 0x179811d4 0x01 0x00 0x00 0x179811d8 0x01 0x00 0x00 0x1740003c 0x01 0x00 0x00 0x17600238 0x01 0x00 0x00 0x1760043c 0x01 0x00 0x00 0x17600440 0x01 0x00 0x00 0x17600240 0x01 0x00 0x00 0x17600244 0x01 0x00 0x00 0x17600248 0x01 0x00 0x00 0x1760024c 0x01 0x00 0x00 0x17600250 0x01 0x00 0x00 0x17600254 0x01 0x00 0x00 0x17600258 0x01 0x00 0x00 0x1760025c 0x01 0x00 0x00 0x17600260 0x01 0x00 0x00 0x17600264 0x01 0x00 0x00 0x17600268 0x01 0x00 0x00 0x17600270 0x01 0x00 0x00 0x17600274 0x01 0x00 0x00 0x17600518 0x01 0x00 0x00 0x1760051c 0x01 0x00 0x00 0x17600520 0x01 0x00 0x00 0x17600524 0x01 0x00 0x00 0x17600528 0x01 0x00 0x00 0x1760052c 0x01 0x00 0x00 0x17600530 0x01 0x00 0x00 0xadf0004 0x01 0x00 0x00 0xadf1004 0x01 0x00 0x00 0xadf2004 0x01 0x00 0x00 0xadf2054 0x01 0x00 0x00 0xadf0080 0x01 0x00 0x00 0xadf00e4 0x01 0x00 0x00 0xadf3058 0x01 0x00 0x00 0xadf30a8 0x01 0x00 0x00 0xadf30f8 0x01 0x00 0x00 0xadf32bc 0x01 0x00 0x00 0xaf09000 0x01 0x00 0x00 0xaf0b000 0x01 0x00 0x00 0x15214c 0x01 0x00 0x00 0x178910 0x01 0x00 0x00 0x16b004 0x01 0x00 0x00 0x16c000 0x01 0x00 0x00 0x18d004 0x01 0x00 0x00 0x18e000 0x01 0x00 0x00 0x177004 0x01 0x00 0x00 0x139004 0x01 0x00 0x00 0x150018 0x01 0x00 0x00 0x3d99168 0x01 0x00 0x00 0x3d99108 0x01 0x00 0x00 0x3d99504 0x01 0x00 0x00 0x3d99058 0x01 0x00 0x00 0x3d99358 0x01 0x00 0x00 0x3d9958c 0x01 0x00 0x00 0x3d9905c 0x01 0x00 0x00 0xaaf804c 0x01 0x00 0x00 0xaaf8078 0x01 0x00 0x00 0xaaf80a4 0x01 0x00 0x00 0xaaf80cc 0x01 0x00 0x00 0x126004 0x01 0x00 0x00 0x126028 0x01 0x00 0x00 0x163020 0x01 0x00 0x00 0x127004 0x01 0x00 0x00 0x127018 0x01 0x00 0x00 0x171004 0x01 0x00 0x00 0x132004 0x01 0x00 0x00 0x132030 0x01 0x00 0x00 0x3d99004 0x01 0x00 0x00 0x3d9900c 0x01 0x00 0x00 0xaf0e054 0x01 0x00 0x00 0xadf32ec 0x01 0x00 0x00 0xaaf80f4 0x01 0x00 0x00 0xaaf8150 0x01 0x00 0x00 0xaaf8124 0x01 0x00 0x00 0x3d94000 0x01 0x00 0x00 0x3d94004 0x01 0x00 0x00 0x3d94008 0x01 0x00 0x00 0x3d95000 0x01 0x00 0x00 0x3d95004 0x01 0x00 0x00 0x3d95008 0x01 0x00 0x00 0x3d9500c 0x01 0x00 0x00 0x3d95010 0x01 0x00 0x00 0x3d96000 0x01 0x00 0x00 0x3d96004 0x01 0x00 0x00 0x3d96008 0x01 0x00 0x00 0x3d9600c 0x01 0x00 0x00 0x3d96010 0x01 0x00 0x00 0x3d97000 0x01 0x00 0x00 0x3d97004 0x01 0x00 0x00 0x3d97008 0x01 0x00 0x00 0x3d9700c 0x01 0x00 0x00 0x3d97010 0x01 0x00 0x00 0x3d98000 0x01 0x00 0x00 0x3d98004 0x01 0x00 0x00 0x3d98008 0x01 0x00 0x00 0x3d9800c 0x01 0x00 0x00 0x3d98010 0x01 0x00 0x00 0x3d99000 0x01 0x00 0x00 0x3d99004 0x01 0x00 0x00 0x3d99008 0x01 0x00 0x00 0x3d9900c 0x01 0x00 0x00 0x3d99010 0x01 0x00 0x00 0x3d99014 0x01 0x00 0x00 0x3d99050 0x01 0x00 0x00 0x3d99054 0x01 0x00 0x00 0x3d99060 0x01 0x00 0x00 0x3d99064 0x01 0x00 0x00 0x3d99068 0x01 0x00 0x00 0x3d9906c 0x01 0x00 0x00 0x3d99070 0x01 0x00 0x00 0x3d99074 0x01 0x00 0x00 0x3d990a8 0x01 0x00 0x00 0x3d990ac 0x01 0x00 0x00 0x3d990b0 0x01 0x00 0x00 0x3d990b4 0x01 0x00 0x00 0x3d990b8 0x01 0x00 0x00 0x3d990bc 0x01 0x00 0x00 0x3d990c0 0x01 0x00 0x00 0x3d990c8 0x01 0x00 0x00 0x3d990cc 0x01 0x00 0x00 0x3d990d0 0x01 0x00 0x00 0x3d99104 0x01 0x00 0x00 0x3d9910c 0x01 0x00 0x00 0x3d99110 0x01 0x00 0x00 0x3d99114 0x01 0x00 0x00 0x3d99118 0x01 0x00 0x00 0x3d9911c 0x01 0x00 0x00 0x3d99120 0x01 0x00 0x00 0x3d99124 0x01 0x00 0x00 0x3d99128 0x01 0x00 0x00 0x3d9912c 0x01 0x00 0x00 0x3d99134 0x01 0x00 0x00 0x3d99138 0x01 0x00 0x00 0x3d9913c 0x01 0x00 0x00 0x3d99140 0x01 0x00 0x00 0x3d99144 0x01 0x00 0x00 0x3d99148 0x01 0x00 0x00 0x3d9914c 0x01 0x00 0x00 0x3d99150 0x01 0x00 0x00 0x3d99154 0x01 0x00 0x00 0x3d99158 0x01 0x00 0x00 0x3d9915c 0x01 0x00 0x00 0x3d99160 0x01 0x00 0x00 0x3d99164 0x01 0x00 0x00 0x3d9916c 0x01 0x00 0x00 0x3d99170 0x01 0x00 0x00 0x3d99174 0x01 0x00 0x00 0x3d99178 0x01 0x00 0x00 0x3d9917c 0x01 0x00 0x00 0x3d99180 0x01 0x00 0x00 0x3d99184 0x01 0x00 0x00 0x3d99188 0x01 0x00 0x00 0x3d9918c 0x01 0x00 0x00 0x3d99198 0x01 0x00 0x00 0x3d9919c 0x01 0x00 0x00 0x3d991a0 0x01 0x00 0x00 0x3d991e0 0x01 0x00 0x00 0x3d991e4 0x01 0x00 0x00 0x3d991e8 0x01 0x00 0x00 0x3d99224 0x01 0x00 0x00 0x3d99228 0x01 0x00 0x00 0x3d99270 0x01 0x00 0x00 0x3d99274 0x01 0x00 0x00 0x3d99278 0x01 0x00 0x00 0x3d99280 0x01 0x00 0x00 0x3d99284 0x01 0x00 0x00 0x3d99288 0x01 0x00 0x00 0x3d9928c 0x01 0x00 0x00 0x3d99290 0x01 0x00 0x00 0x3d99294 0x01 0x00 0x00 0x3d99298 0x01 0x00 0x00 0x3d99314 0x01 0x00 0x00 0x3d99318 0x01 0x00 0x00 0x3d9931c 0x01 0x00 0x00 0x3d9935c 0x01 0x00 0x00 0x3d99360 0x01 0x00 0x00 0x3d993a0 0x01 0x00 0x00 0x3d993a4 0x01 0x00 0x00 0x3d993e4 0x01 0x00 0x00 0x3d993e8 0x01 0x00 0x00 0x3d993ec 0x01 0x00 0x00 0x3d993f0 0x01 0x00 0x00 0x3d9942c 0x01 0x00 0x00 0x3d99470 0x01 0x00 0x00 0x3d99474 0x01 0x00 0x00 0x3d99478 0x01 0x00 0x00 0x3d99500 0x01 0x00 0x00 0x3d99508 0x01 0x00 0x00 0x3d9950c 0x01 0x00 0x00 0x3d99510 0x01 0x00 0x00 0x3d99514 0x01 0x00 0x00 0x3d99518 0x01 0x00 0x00 0x3d9951c 0x01 0x00 0x00 0x3d99520 0x01 0x00 0x00 0x3d99524 0x01 0x00 0x00 0x3d99528 0x01 0x00 0x00 0x3d9952c 0x01 0x00 0x00 0x3d99530 0x01 0x00 0x00 0x3d99534 0x01 0x00 0x00 0x3d99538 0x01 0x00 0x00 0x3d99550 0x01 0x00 0x00 0x3d99554 0x01 0x00 0x00 0x3d99558 0x01 0x00 0x00 0x3d9955c 0x01 0x00 0x00 0x3d99560 0x01 0x00 0x00 0x3d99564 0x01 0x00 0x00 0x3d99568 0x01 0x00 0x00 0x3d9956c 0x01 0x00 0x00 0x3d99570 0x01 0x00 0x00 0x3d99574 0x01 0x00 0x00 0x3d99578 0x01 0x00 0x00 0x3d9957c 0x01 0x00 0x00 0x3d99580 0x01 0x00 0x00 0x3d99584 0x01 0x00 0x00 0x3d99588 0x01 0x00 0x00 0x3d99590 0x01 0x00 0x00 0x3d99594 0x01 0x00 0x00 0x3d99598 0x01 0x00 0x00 0x3d9959c 0x01 0x00 0x00 0x3d995a0 0x01 0x00 0x00 0x3d995a4 0x01 0x00 0x00 0x3d995a8 0x01 0x00 0x00 0x3d995ac 0x01 0x00 0x00 0x3d995b0 0x01 0x00 0x00 0x3d995b4 0x01 0x00 0x00 0x3d995b8 0x01 0x00 0x00 0x3d995bc 0x01 0x00 0x00 0x3d995c0 0x01 0x00 0x00 0x3d995c4 0x01 0x00 0x00 0x3d995c8 0x01 0x00 0x00 0x3d995cc 0x01 0x00 0x00 0x3d995d8 0x01 0x00 0x00 0x3d995dc 0x01 0x00 0x00 0x3d995e0 0x01 0x00 0x00 0x3d995e4 0x01 0x00 0x00 0x3d995e8 0x01 0x00 0x00 0x3d40000 0x01 0x00 0x00 0x3d40004 0x01 0x00 0x00 0x3d40008 0x01 0x00 0x00 0x3d4000c 0x01 0x00 0x00 0x3d41000 0x01 0x00 0x00 0x3d41004 0x01 0x00 0x00 0x3d41008 0x01 0x00 0x00 0x3d4100c 0x01 0x00 0x00 0x3d42000 0x01 0x00 0x00 0x3d42004 0x01 0x00 0x00 0x3d42008 0x01 0x00 0x00 0x3d4200c 0x01 0x00 0x00 0x3d43000 0x01 0x00 0x00 0x3d43004 0x01 0x00 0x00 0x3d43008 0x01 0x00 0x00 0x3d4300c 0x01 0x00 0x00 0x3d44000 0x01 0x00 0x00 0x3d44004 0x01 0x00 0x00 0x3d44008 0x01 0x00 0x00 0x3d4400c 0x01 0x00 0x00 0x3d45000 0x01 0x00 0x00 0x3d45004 0x01 0x00 0x00 0x3d45008 0x01 0x00 0x00 0x3d4500c 0x01 0x00 0x00 0x3d46000 0x01 0x00 0x00 0x3d46004 0x01 0x00 0x00 0x3d46008 0x01 0x00 0x00 0x3d4600c 0x01 0x00 0x00 0x3d47000 0x01 0x00 0x00 0x3d47004 0x01 0x00 0x00 0x3d47008 0x01 0x00 0x00 0x3d4700c 0x01 0x00 0x00 0x3d48000 0x01 0x00 0x00 0x3d49000 0x01 0x00 0x00 0x3d4a000 0x01 0x00 0x00 0x3d4b000 0x01 0x00 0x00 0x3d4c000 0x01 0x00 0x00 0x3d4d000 0x01 0x00 0x00 0x3d4e000 0x01 0x00 0x00 0x3d4f000 0x01 0x00 0x00 0x3d8e000 0x01 0x00 0x00 0x3d8e004 0x01 0x00 0x00 0x3d8e008 0x01 0x00 0x00 0x3d8e00c 0x01 0x00 0x00 0x3d8e010 0x01 0x00 0x00 0x3d8e014 0x01 0x00 0x00 0x3d8e018 0x01 0x00 0x00 0x3d8e01c 0x01 0x00 0x00 0x3d8e020 0x01 0x00 0x00 0x3d8e024 0x01 0x00 0x00 0x3d8e028 0x01 0x00 0x00 0x3d8e02c 0x01 0x00 0x00 0x3d8e030 0x01 0x00 0x00 0x3d8e034 0x01 0x00 0x00 0x3d8e038 0x01 0x00 0x00 0x3d8e03c 0x01 0x00 0x00 0x3d8e040 0x01 0x00 0x00 0x3d8e044 0x01 0x00 0x00 0x3d8e048 0x01 0x00 0x00 0x3d8e04c 0x01 0x00 0x00 0x3d8e050 0x01 0x00 0x00 0x3d8e054 0x01 0x00 0x00 0x3d8e058 0x01 0x00 0x00 0x3d8e05c 0x01 0x00 0x00 0x3d8e060 0x01 0x00 0x00 0x3d8e064 0x01 0x00 0x00 0x3d8e068 0x01 0x00 0x00 0x3d8e06c 0x01 0x00 0x00 0x3d8e070 0x01 0x00 0x00 0x3d8e074 0x01 0x00 0x00 0x3d8e078 0x01 0x00 0x00 0x3d8e07c 0x01 0x00 0x00 0x3d8e080 0x01 0x00 0x00 0x3d8e084 0x01 0x00 0x00 0x3d8e088 0x01 0x00 0x00 0x3d8e090 0x01 0x00 0x00 0x3d8e094 0x01 0x00 0x00 0x3d8e098 0x01 0x00 0x00 0x3d8e0a0 0x01 0x00 0x00 0x3d8e0a4 0x01 0x00 0x00 0x3d8e0a8 0x01 0x00 0x00 0x3d8e0b0 0x01 0x00 0x00 0x3d8e0b4 0x01 0x00 0x00 0x3d8e0b8 0x01 0x00 0x00 0x3d8e0c0 0x01 0x00 0x00 0x3d8e0c4 0x01 0x00 0x00 0x3d8e0c8 0x01 0x00 0x00 0x3d8e0d0 0x01 0x00 0x00 0x3d8e0d4 0x01 0x00 0x00 0x3d8e0d8 0x01 0x00 0x00 0x3d8e0e0 0x01 0x00 0x00 0x3d8e0e4 0x01 0x00 0x00 0x3d8e0e8 0x01 0x00 0x00 0x3d8e0f0 0x01 0x00 0x00 0x3d8e0f4 0x01 0x00 0x00 0x3d8e0f8 0x01 0x00 0x00 0x3d8e100 0x01 0x00 0x00 0x3d8e104 0x01 0x00 0x00 0x3d8e108 0x01 0x00 0x00 0x3d8e10c 0x01 0x00 0x00 0x3d8e110 0x01 0x00 0x00 0x3d8e114 0x01 0x00 0x00 0x3d8e118 0x01 0x00 0x00 0x3d8e11c 0x01 0x00 0x00 0x3d8ec00 0x01 0x00 0x00 0x3d8ec04 0x01 0x00 0x00 0x3d8ec08 0x01 0x00 0x00 0x3d8ec0c 0x01 0x00 0x00 0x3d8ec10 0x01 0x00 0x00 0x3d8ec14 0x01 0x00 0x00 0x3d8ec18 0x01 0x00 0x00 0x3d8ec1c 0x01 0x00 0x00 0x3d8ec20 0x01 0x00 0x00 0x3d8ec24 0x01 0x00 0x00 0x3d8ec28 0x01 0x00 0x00 0x3d8ec2c 0x01 0x00 0x00 0x3d8ec30 0x01 0x00 0x00 0x3d8ec34 0x01 0x00 0x00 0x3d8ec38 0x01 0x00 0x00 0x3d8ec40 0x01 0x00 0x00 0x3d8ec44 0x01 0x00 0x00 0x3d8ec48 0x01 0x00 0x00 0x3d8ec4c 0x01 0x00 0x00 0x3d8ec50 0x01 0x00 0x00 0x3d8ec54 0x01 0x00 0x00 0x3d8ec58 0x01 0x00 0x00 0x3d8eca0 0x01 0x00 0x00 0x3d8ecc0 0x01 0x00 0x00 0x3d8eff0 0x01 0x00 0x00 0x3d8eff4 0x01 0x00 0x00 0x3d8f000 0x01 0x00 0x00 0x3d7d000 0x01 0x00 0x00 0x3d7d004 0x01 0x00 0x00 0x3d7d008 0x01 0x00 0x00 0x3d7d00c 0x01 0x00 0x00 0x3d7d010 0x01 0x00 0x00 0x3d7d014 0x01 0x00 0x00 0x3d7d018 0x01 0x00 0x00 0x3d7d01c 0x01 0x00 0x00 0x3d7d020 0x01 0x00 0x00 0x3d7d024 0x01 0x00 0x00 0x3d7d028 0x01 0x00 0x00 0x3d7d02c 0x01 0x00 0x00 0x3d7d03c 0x01 0x00 0x00 0x3d7d040 0x01 0x00 0x00 0x3d7d044 0x01 0x00 0x00 0x3d7d048 0x01 0x00 0x00 0x3d7d400 0x01 0x00 0x00 0x3d7d41c 0x01 0x00 0x00 0x3d7d420 0x01 0x00 0x00 0x3d7d424 0x01 0x00 0x00 0x3d7d428 0x01 0x00 0x00 0x3d7d42c 0x01 0x00 0x00 0x3d7dc00 0x01 0x00 0x00 0x3d7dc04 0x01 0x00 0x00 0x3d7dc10 0x01 0x00 0x00 0x3d7dc14 0x01 0x00 0x00 0x3d7dc18 0x01 0x00 0x00 0x3d7dc20 0x01 0x00 0x00 0x3d7dc24 0x01 0x00 0x00 0x3d7dc30 0x01 0x00 0x00 0x3d7dc34 0x01 0x00 0x00 0x3d7dc40 0x01 0x00 0x00 0x3d7dc44 0x01 0x00 0x00 0x3d7dc4c 0x01 0x00 0x00 0x3d7dc50 0x01 0x00 0x00 0x3d7dc54 0x01 0x00 0x00 0x3d7dc58 0x01 0x00 0x00 0x3d7dc60 0x01 0x00 0x00 0x3d7dc64 0x01 0x00 0x00 0x3d7dc68 0x01 0x00 0x00 0x3d7dc6c 0x01 0x00 0x00 0x3d7dc70 0x01 0x00 0x00 0x3d7dc74 0x01 0x00 0x00 0x3d7dc80 0x01 0x00 0x00 0x3d7dc84 0x01 0x00 0x00 0x3d7dc88 0x01 0x00 0x00 0x3d7dc8c 0x01 0x00 0x00 0x3d7dc90 0x01 0x00 0x00 0x3d7dca4 0x01 0x00 0x00 0x3d7dcc0 0x01 0x00 0x00 0x3d7dcc4 0x01 0x00 0x00 0x3d7dcc8 0x01 0x00 0x00 0x3d7dccc 0x01 0x00 0x00 0x3d7dcd0 0x01 0x00 0x00 0x3d7dcd4 0x01 0x00 0x00 0x3d7dcd8 0x01 0x00 0x00 0x3d7dcdc 0x01 0x00 0x00 0x3d7dce0 0x01 0x00 0x00 0x3d7dce4 0x01 0x00 0x00 0x3d7dce8 0x01 0x00 0x00 0x3d7dcec 0x01 0x00 0x00 0x3d7dcf0 0x01 0x00 0x00 0x3d7dcf4 0x01 0x00 0x00 0x3d7dcf8 0x01 0x00 0x00 0x3d7dcfc 0x01 0x00 0x00 0x3d7dd00 0x01 0x00 0x00 0x3d7dd04 0x01 0x00 0x00 0x3d7dd08 0x01 0x00 0x00 0x3d7dd0c 0x01 0x00 0x00 0x3d7dd10 0x01 0x00 0x00 0x3d7dd14 0x01 0x00 0x00 0x3d7dd18 0x01 0x00 0x00 0x3d7dd1c 0x01 0x00 0x00 0x3d7dd40 0x01 0x00 0x00 0x3d7dd44 0x01 0x00 0x00 0x3d7dd48 0x01 0x00 0x00 0x3d7dd4c 0x01 0x00 0x00 0x3d7dd50 0x01 0x00 0x00 0x3d7dd54 0x01 0x00 0x00 0x3d7dd58 0x01 0x00 0x00 0x3d7dd60 0x01 0x00 0x00 0x3d7dd64 0x01 0x00 0x00 0x3d7dd70 0x01 0x00 0x00 0x3d7dd80 0x01 0x00 0x00 0x3d7dd84 0x01 0x00 0x00 0x3d7dd90 0x01 0x00 0x00 0x3d7dd94 0x01 0x00 0x00 0x3d7dd98 0x01 0x00 0x00 0x3d7dd9c 0x01 0x00 0x00 0x3d7dda0 0x01 0x00 0x00 0x3d7dda4 0x01 0x00 0x00 0x3d7dda8 0x01 0x00 0x00 0x3d7ddac 0x01 0x00 0x00 0x3d7ddc0 0x01 0x00 0x00 0x3d7ddc4 0x01 0x00 0x00 0x3d7ddc8 0x01 0x00 0x00 0x3d7ddcc 0x01 0x00 0x00 0x3d7ddd0 0x01 0x00 0x00 0x3d7ddd4 0x01 0x00 0x00 0x3d7de00 0x01 0x00 0x00 0x3d7de04 0x01 0x00 0x00 0x3d7de08 0x01 0x00 0x00 0x3d7de0c 0x01 0x00 0x00 0x3d7de10 0x01 0x00 0x00 0x3d7de14 0x01 0x00 0x00 0x3d7de40 0x01 0x00 0x00 0x3d7de44 0x01 0x00 0x00 0x3d7de48 0x01 0x00 0x00 0x3d7de4c 0x01 0x00 0x00 0x3d7de50 0x01 0x00 0x00 0x3d7de54 0x01 0x00 0x00 0x3d7de58 0x01 0x00 0x00 0x3d7de5c 0x01 0x00 0x00 0x3d7de60 0x01 0x00 0x00 0x3d7de80 0x01 0x00 0x00 0x3d7de84 0x01 0x00 0x00 0x3d7de88 0x01 0x00 0x00 0x3d7de8c 0x01 0x00 0x00 0x3d7de90 0x01 0x00 0x00 0x3d7de94 0x01 0x00 0x00 0x3d7de98 0x01 0x00 0x00 0x3d7de9c 0x01 0x00 0x00 0x3d7dea0 0x01 0x00 0x00 0x3d7dec0 0x01 0x00 0x00 0x3d7dec4 0x01 0x00 0x00 0x3d7dec8 0x01 0x00 0x00 0x3d7decc 0x01 0x00 0x00 0x3d7e000 0x01 0x00 0x00 0x3d7e004 0x01 0x00 0x00 0x3d7e008 0x01 0x00 0x00 0x3d7e00c 0x01 0x00 0x00 0x3d7e010 0x01 0x00 0x00 0x3d7e01c 0x01 0x00 0x00 0x3d7e020 0x01 0x00 0x00 0x3d7e02c 0x01 0x00 0x00 0x3d7e030 0x01 0x00 0x00 0x3d7e03c 0x01 0x00 0x00 0x3d7e040 0x01 0x00 0x00 0x3d7e044 0x01 0x00 0x00 0x3d7e048 0x01 0x00 0x00 0x3d7e04c 0x01 0x00 0x00 0x3d7e050 0x01 0x00 0x00 0x3d7e054 0x01 0x00 0x00 0x3d7e058 0x01 0x00 0x00 0x3d7e05c 0x01 0x00 0x00 0x3d7e060 0x01 0x00 0x00 0x3d7e064 0x01 0x00 0x00 0x3d7e068 0x01 0x00 0x00 0x3d7e06c 0x01 0x00 0x00 0x3d7e070 0x01 0x00 0x00 0x3d7e090 0x01 0x00 0x00 0x3d7e094 0x01 0x00 0x00 0x3d7e098 0x01 0x00 0x00 0x3d7e09c 0x01 0x00 0x00 0x3d7e0a0 0x01 0x00 0x00 0x3d7e0a4 0x01 0x00 0x00 0x3d7e0a8 0x01 0x00 0x00 0x3d7e0b4 0x01 0x00 0x00 0x3d7e0b8 0x01 0x00 0x00 0x3d7e0bc 0x01 0x00 0x00 0x3d7e0c0 0x01 0x00 0x00 0x3d7e100 0x01 0x00 0x00 0x3d7e104 0x01 0x00 0x00 0x3d7e108 0x01 0x00 0x00 0x3d7e10c 0x01 0x00 0x00 0x3d7e110 0x01 0x00 0x00 0x3d7e114 0x01 0x00 0x00 0x3d7e118 0x01 0x00 0x00 0x3d7e11c 0x01 0x00 0x00 0x3d7e120 0x01 0x00 0x00 0x3d7e124 0x01 0x00 0x00 0x3d7e128 0x01 0x00 0x00 0x3d7e12c 0x01 0x00 0x00 0x3d7e130 0x01 0x00 0x00 0x3d7e134 0x01 0x00 0x00 0x3d7e138 0x01 0x00 0x00 0x3d7e13c 0x01 0x00 0x00 0x3d7e140 0x01 0x00 0x00 0x3d7e144 0x01 0x00 0x00 0x3d7e148 0x01 0x00 0x00 0x3d7e14c 0x01 0x00 0x00 0x3d7e180 0x01 0x00 0x00 0x3d7e188 0x01 0x00 0x00 0x3d7e18c 0x01 0x00 0x00 0x3d7e190 0x01 0x00 0x00 0x3d7e194 0x01 0x00 0x00 0x3d7e198 0x01 0x00 0x00 0x3d7e1a0 0x01 0x00 0x00 0x3d7e1a4 0x01 0x00 0x00 0x3d7e1c0 0x01 0x00 0x00 0x3d7e1c4 0x01 0x00 0x00 0x3d7e1c8 0x01 0x00 0x00 0x3d7e1cc 0x01 0x00 0x00 0x3d7e1d0 0x01 0x00 0x00 0x3d7e1d4 0x01 0x00 0x00 0x3d7e1d8 0x01 0x00 0x00 0x3d7e1dc 0x01 0x00 0x00 0x3d7e1e0 0x01 0x00 0x00 0x3d7e1e4 0x01 0x00 0x00 0x3d7e1fc 0x01 0x00 0x00 0x3d7e200 0x01 0x00 0x00 0x3d7e204 0x01 0x00 0x00 0x3d7e240 0x01 0x00 0x00 0x3d7e244 0x01 0x00 0x00 0x3d7e248 0x01 0x00 0x00 0x3d7e24c 0x01 0x00 0x00 0x3d7e250 0x01 0x00 0x00 0x3d7e254 0x01 0x00 0x00 0x3d7e258 0x01 0x00 0x00 0x3d7e280 0x01 0x00 0x00 0x3d7e284 0x01 0x00 0x00 0x3d7e288 0x01 0x00 0x00 0x3d7e290 0x01 0x00 0x00 0x3d7e294 0x01 0x00 0x00 0x3d7e298 0x01 0x00 0x00 0x3d7e29c 0x01 0x00 0x00 0x3d7e2a0 0x01 0x00 0x00 0x3d7e2a4 0x01 0x00 0x00 0x3d7e2a8 0x01 0x00 0x00 0x3d7e2ac 0x01 0x00 0x00 0x3d7e2b0 0x01 0x00 0x00 0x3d7e2b4 0x01 0x00 0x00 0x3d7e2b8 0x01 0x00 0x00 0x3d7e2bc 0x01 0x00 0x00 0x3d7e2e0 0x01 0x00 0x00 0x3d7e2e4 0x01 0x00 0x00 0x3d7e300 0x01 0x00 0x00 0x3d7e304 0x01 0x00 0x00 0x3d7e30c 0x01 0x00 0x00 0x3d7e310 0x01 0x00 0x00 0x3d7e340 0x01 0x00 0x00 0x3d7e3b0 0x01 0x00 0x00 0x3d7e3c0 0x01 0x00 0x00 0x3d7e3c4 0x01 0x00 0x00 0x3d7e440 0x01 0x00 0x00 0x3d7e444 0x01 0x00 0x00 0x3d7e448 0x01 0x00 0x00 0x3d7e44c 0x01 0x00 0x00 0x3d7e450 0x01 0x00 0x00 0x3d7e454 0x01 0x00 0x00 0x3d7e458 0x01 0x00 0x00 0x3d7e45c 0x01 0x00 0x00 0x3d7e480 0x01 0x00 0x00 0x3d7e484 0x01 0x00 0x00 0x3d7e488 0x01 0x00 0x00 0x3d7e490 0x01 0x00 0x00 0x3d7e494 0x01 0x00 0x00 0x3d7e498 0x01 0x00 0x00 0x3d7e4a0 0x01 0x00 0x00 0x3d7e4a4 0x01 0x00 0x00 0x3d7e4a8 0x01 0x00 0x00 0x3d7e4b0 0x01 0x00 0x00 0x3d7e4b4 0x01 0x00 0x00 0x3d7e4b8 0x01 0x00 0x00 0x3d7e508 0x01 0x00 0x00 0x3d7e50c 0x01 0x00 0x00 0x3d7e510 0x01 0x00 0x00 0x3d7e520 0x01 0x00 0x00 0x3d7e524 0x01 0x00 0x00 0x3d7e528 0x01 0x00 0x00 0x3d7e53c 0x01 0x00 0x00 0x3d7e540 0x01 0x00 0x00 0x3d7e544 0x01 0x00 0x00 0x3d7e550 0x01 0x00 0x00 0x3d7e554 0x01 0x00 0x00 0x3d7e574 0x01 0x00 0x00 0x3d7e588 0x01 0x00 0x00 0x3d7e58c 0x01 0x00 0x00 0x3d7e590 0x01 0x00 0x00 0x3d7e594 0x01 0x00 0x00 0x3d7e598 0x01 0x00 0x00 0x3d7e59c 0x01 0x00 0x00 0x3d7e5a0 0x01 0x00 0x00 0x3d7e5a4 0x01 0x00 0x00 0x3d7e5a8 0x01 0x00 0x00 0x3d7e5ac 0x01 0x00 0x00 0x3d7e5c0 0x01 0x00 0x00 0x3d7e5c4 0x01 0x00 0x00 0x3d7e5cc 0x01 0x00 0x00 0x3d7e5d0 0x01 0x00 0x00 0x3d7e5d4 0x01 0x00 0x00 0x3d7e5d8 0x01 0x00 0x00 0x3d7e5dc 0x01 0x00 0x00 0x3d7e5f0 0x01 0x00 0x00 0x3d7e600 0x01 0x00 0x00 0x3d7e604 0x01 0x00 0x00 0x3d7e610 0x01 0x00 0x00 0x3d7e614 0x01 0x00 0x00 0x3d7e618 0x01 0x00 0x00 0x3d7e640 0x01 0x00 0x00 0x3d7e644 0x01 0x00 0x00 0x3d7e648 0x01 0x00 0x00 0x3d7e64c 0x01 0x00 0x00 0x3d7e650 0x01 0x00 0x00 0x3d7e654 0x01 0x00 0x00 0x3d7e658 0x01 0x00 0x00 0x3d7e65c 0x01 0x00 0x00 0x3d7e660 0x01 0x00 0x00 0x3d7e664 0x01 0x00 0x00 0x3d7e668 0x01 0x00 0x00 0x3d7e66c 0x01 0x00 0x00 0x3d7e670 0x01 0x00 0x00 0x3d7e674 0x01 0x00 0x00 0x3d7e678 0x01 0x00 0x00 0x3d7e714 0x01 0x00 0x00 0x3d7e718 0x01 0x00 0x00 0x3d7e71c 0x01 0x00 0x00 0x3d7e720 0x01 0x00 0x00 0x3d7e724 0x01 0x00 0x00 0x3d7e728 0x01 0x00 0x00 0x3d7e72c 0x01 0x00 0x00 0x3d7e730 0x01 0x00 0x00 0x3d7e734 0x01 0x00 0x00 0x3d7e738 0x01 0x00 0x00 0x3d7e73c 0x01 0x00 0x00 0x3d7e740 0x01 0x00 0x00 0x3d7e744 0x01 0x00 0x00 0x3d7e748 0x01 0x00 0x00 0x3d7e74c 0x01 0x00 0x00 0x3d7e750 0x01 0x00 0x00 0x3d7e7c0 0x01 0x00 0x00 0x3d7e7c4 0x01 0x00 0x00 0x3d7e7e0 0x01 0x00 0x00 0x3d7e7e4 0x01 0x00 0x00 0x3d7e7e8 0x01 0x00 0x00 0x3d7e7f0 0x01 0x00 0x00 0x3d7e800 0x01 0x00 0x00 0x3d7e804 0x01 0x00 0x00 0x3d7e808 0x01 0x00 0x00 0x3d7e80c 0x01 0x00 0x00 0x3d80000 0x01 0x00 0x00 0x3d80004 0x01 0x00 0x00 0x3d80008 0x01 0x00 0x00 0x3d8000c 0x01 0x00 0x00 0x3d80010 0x01 0x00 0x00 0x3d80014 0x01 0x00 0x00 0x3d80018 0x01 0x00 0x00 0x3d8001c 0x01 0x00 0x00 0x3d80020 0x01 0x00 0x00 0x3d80024 0x01 0x00 0x00 0x3d80028 0x01 0x00 0x00 0x3d8002c 0x01 0x00 0x00 0x3d80030 0x01 0x00 0x00 0x3d80034 0x01 0x00 0x00 0x3d80038 0x01 0x00 0x00 0x3d8003c 0x01 0x00 0x00 0x3d80040 0x01 0x00 0x00 0x3d80044 0x01 0x00 0x00 0x3d80048 0x01 0x00 0x00 0x3d8004c 0x01 0x00 0x00 0x3d80060 0x01 0x00 0x00 0x3d80064 0x01 0x00 0x00 0x3d80068 0x01 0x00 0x00 0x3d80080 0x01 0x00 0x00 0x3d80084 0x01 0x00 0x00 0x3d80090 0x01 0x00 0x00 0x3d80094 0x01 0x00 0x00 0x3d800a8 0x01 0x00 0x00 0x3d800ac 0x01 0x00 0x00 0x3d800b0 0x01 0x00 0x00 0x3d800c0 0x01 0x00 0x00 0x3d800c4 0x01 0x00 0x00 0x3d800d0 0x01 0x00 0x00 0x3d800d4 0x01 0x00 0x00 0x3d800d8 0x01 0x00 0x00 0x3d81000 0x01 0x00 0x00 0x3d81010 0x01 0x00 0x00 0x3d81020 0x01 0x00 0x00 0x3d81024 0x01 0x00 0x00 0x3d81028 0x01 0x00 0x00 0x3d8102c 0x01 0x00 0x00 0x3d81030 0x01 0x00 0x00 0x3d81034 0x01 0x00 0x00 0x3d81038 0x01 0x00 0x00 0x3d8103c 0x01 0x00 0x00 0x3d81040 0x01 0x00 0x00 0x3d81044 0x01 0x00 0x00 0x3d81048 0x01 0x00 0x00 0x3d8104c 0x01 0x00 0x00 0x3d69000 0x01 0x00 0x00 0x3d69004 0x01 0x00 0x00 0x3d69008 0x01 0x00 0x00 0x3d6900c 0x01 0x00 0x00 0x3d69010 0x01 0x00 0x00 0x3d69014 0x01 0x00 0x00 0x3d69018 0x01 0x00 0x00 0x3d6901c 0x01 0x00 0x00 0x3d69020 0x01 0x00 0x00 0x3d69024 0x01 0x00 0x00 0x3d69028 0x01 0x00 0x00 0x3d6902c 0x01 0x00 0x00 0x3d69030 0x01 0x00 0x00 0x3d69034 0x01 0x00 0x00 0x3d69038 0x01 0x00 0x00 0x3d6903c 0x01 0x00 0x00 0x3d69040 0x01 0x00 0x00 0x3d69044 0x01 0x00 0x00 0x3d69048 0x01 0x00 0x00 0x3d6904c 0x01 0x00 0x00 0x3d69050 0x01 0x00 0x00 0x3d69054 0x01 0x00 0x00 0x3d69058 0x01 0x00 0x00 0x3d6905c 0x01 0x00 0x00 0x3d69060 0x01 0x00 0x00 0x3d69064 0x01 0x00 0x00 0x3d69068 0x01 0x00 0x00 0x3d6906c 0x01 0x00 0x00 0x3d69070 0x01 0x00 0x00 0x3d69074 0x01 0x00 0x00 0x3d69078 0x01 0x00 0x00 0x3d6907c 0x01 0x00 0x00 0x3d69100 0x01 0x00 0x00 0x3d69104 0x01 0x00 0x00 0x3d69108 0x01 0x00 0x00 0x3d6910c 0x01 0x00 0x00 0x3d69110 0x01 0x00 0x00 0x3d69114 0x01 0x00 0x00 0x3d69118 0x01 0x00 0x00 0x3d6911c 0x01 0x00 0x00 0x3d69120 0x01 0x00 0x00 0x3d69124 0x01 0x00 0x00 0x3d69128 0x01 0x00 0x00 0x3d6912c 0x01 0x00 0x00 0x3d69130 0x01 0x00 0x00 0x3d69134 0x01 0x00 0x00 0x3d69138 0x01 0x00 0x00 0x3d6913c 0x01 0x00 0x00 0x3d69140 0x01 0x00 0x00 0x3d69144 0x01 0x00 0x00 0x3d69148 0x01 0x00 0x00 0x3d6914c 0x01 0x00 0x00 0x3d69150 0x01 0x00 0x00 0x3d69154 0x01 0x00 0x00 0x3d69158 0x01 0x00 0x00 0x3d6915c 0x01 0x00 0x00 0x3d69160 0x01 0x00 0x00 0x3d69164 0x01 0x00 0x00 0x3d69168 0x01 0x00 0x00 0x3d6916c 0x01 0x00 0x00 0x3d69170 0x01 0x00 0x00 0x3d69174 0x01 0x00 0x00 0x3d69178 0x01 0x00 0x00 0x3d6917c 0x01 0x00 0x00 0x3d69200 0x01 0x00 0x00 0x3d69204 0x01 0x00 0x00 0x3d69208 0x01 0x00 0x00 0x3d6920c 0x01 0x00 0x00 0x3d69210 0x01 0x00 0x00 0x3d69214 0x01 0x00 0x00 0x3d69218 0x01 0x00 0x00 0x3d6921c 0x01 0x00 0x00 0x3d69220 0x01 0x00 0x00 0x3d69224 0x01 0x00 0x00 0x3d69228 0x01 0x00 0x00 0x3d6922c 0x01 0x00 0x00 0x3d69230 0x01 0x00 0x00 0x3d69234 0x01 0x00 0x00 0x3d69238 0x01 0x00 0x00 0x3d6923c 0x01 0x00 0x00 0x3d69240 0x01 0x00 0x00 0x3d69244 0x01 0x00 0x00 0x3d69248 0x01 0x00 0x00 0x3d6924c 0x01 0x00 0x00 0x3d69250 0x01 0x00 0x00 0x3d69254 0x01 0x00 0x00 0x3d69258 0x01 0x00 0x00 0x3d6925c 0x01 0x00 0x00 0x3d69260 0x01 0x00 0x00 0x3d69264 0x01 0x00 0x00 0x3d69268 0x01 0x00 0x00 0x3d6926c 0x01 0x00 0x00 0x3d69270 0x01 0x00 0x00 0x3d69274 0x01 0x00 0x00 0x3d69278 0x01 0x00 0x00 0x3d6927c 0x01 0x00 0x00 0x3d69300 0x01 0x00 0x00 0x3d69304 0x01 0x00 0x00 0x3d69308 0x01 0x00 0x00 0x3d6930c 0x01 0x00 0x00 0x3d69310 0x01 0x00 0x00 0x3d69314 0x01 0x00 0x00 0x3d69318 0x01 0x00 0x00 0x3d6931c 0x01 0x00 0x00 0x3d69320 0x01 0x00 0x00 0x3d69324 0x01 0x00 0x00 0x3d69328 0x01 0x00 0x00 0x3d6932c 0x01 0x00 0x00 0x3d69330 0x01 0x00 0x00 0x3d69334 0x01 0x00 0x00 0x3d69338 0x01 0x00 0x00 0x3d6933c 0x01 0x00 0x00 0x3d69340 0x01 0x00 0x00 0x3d69344 0x01 0x00 0x00 0x3d69348 0x01 0x00 0x00 0x3d6934c 0x01 0x00 0x00 0x3d69350 0x01 0x00 0x00 0x3d69354 0x01 0x00 0x00 0x3d69358 0x01 0x00 0x00 0x3d6935c 0x01 0x00 0x00 0x3d69360 0x01 0x00 0x00 0x3d69364 0x01 0x00 0x00 0x3d69368 0x01 0x00 0x00 0x3d6936c 0x01 0x00 0x00 0x3d69370 0x01 0x00 0x00 0x3d69374 0x01 0x00 0x00 0x3d69378 0x01 0x00 0x00 0x3d6937c 0x01 0x00 0x00 0x3d69400 0x01 0x00 0x00 0x3d69404 0x01 0x00 0x00 0x3d69408 0x01 0x00 0x00 0x3d6940c 0x01 0x00 0x00 0x3d69410 0x01 0x00 0x00 0x3d69414 0x01 0x00 0x00 0x3d69418 0x01 0x00 0x00 0x3d6941c 0x01 0x00 0x00 0x3d69420 0x01 0x00 0x00 0x3d69424 0x01 0x00 0x00 0x3d69428 0x01 0x00 0x00 0x3d6942c 0x01 0x00 0x00 0x3d69430 0x01 0x00 0x00 0x3d69434 0x01 0x00 0x00 0x3d69438 0x01 0x00 0x00 0x3d6943c 0x01 0x00 0x00 0x3d69440 0x01 0x00 0x00 0x3d69444 0x01 0x00 0x00 0x3d69448 0x01 0x00 0x00 0x3d6944c 0x01 0x00 0x00 0x3d69450 0x01 0x00 0x00 0x3d69454 0x01 0x00 0x00 0x3d69458 0x01 0x00 0x00 0x3d6945c 0x01 0x00 0x00 0x3d69460 0x01 0x00 0x00 0x3d69464 0x01 0x00 0x00 0x3d69468 0x01 0x00 0x00 0x3d6946c 0x01 0x00 0x00 0x3d69470 0x01 0x00 0x00 0x3d69474 0x01 0x00 0x00 0x3d69478 0x01 0x00 0x00 0x3d6947c 0x01 0x00 0x00 0x3d69500 0x01 0x00 0x00 0x3d69504 0x01 0x00 0x00 0x3d69508 0x01 0x00 0x00 0x3d6950c 0x01 0x00 0x00 0x3d69510 0x01 0x00 0x00 0x3d69514 0x01 0x00 0x00 0x3d69518 0x01 0x00 0x00 0x3d6951c 0x01 0x00 0x00 0x3d69520 0x01 0x00 0x00 0x3d69524 0x01 0x00 0x00 0x3d69528 0x01 0x00 0x00 0x3d6952c 0x01 0x00 0x00 0x3d69530 0x01 0x00 0x00 0x3d69534 0x01 0x00 0x00 0x3d69538 0x01 0x00 0x00 0x3d6953c 0x01 0x00 0x00 0x3d69540 0x01 0x00 0x00 0x3d69544 0x01 0x00 0x00 0x3d69548 0x01 0x00 0x00 0x3d6954c 0x01 0x00 0x00 0x3d69550 0x01 0x00 0x00 0x3d69554 0x01 0x00 0x00 0x3d69558 0x01 0x00 0x00 0x3d6955c 0x01 0x00 0x00 0x3d69560 0x01 0x00 0x00 0x3d69564 0x01 0x00 0x00 0x3d69568 0x01 0x00 0x00 0x3d6956c 0x01 0x00 0x00 0x3d69570 0x01 0x00 0x00 0x3d69574 0x01 0x00 0x00 0x3d69578 0x01 0x00 0x00 0x3d6957c 0x01 0x00 0x00 0x3d69600 0x01 0x00 0x00 0x3d69604 0x01 0x00 0x00 0x3d69608 0x01 0x00 0x00 0x3d6960c 0x01 0x00 0x00 0x3d69610 0x01 0x00 0x00 0x3d69614 0x01 0x00 0x00 0x3d69618 0x01 0x00 0x00 0x3d6961c 0x01 0x00 0x00 0x3d69620 0x01 0x00 0x00 0x3d69624 0x01 0x00 0x00 0x3d69628 0x01 0x00 0x00 0x3d6962c 0x01 0x00 0x00 0x3d69630 0x01 0x00 0x00 0x3d69634 0x01 0x00 0x00 0x3d69638 0x01 0x00 0x00 0x3d6963c 0x01 0x00 0x00 0x3d69640 0x01 0x00 0x00 0x3d69644 0x01 0x00 0x00 0x3d69648 0x01 0x00 0x00 0x3d6964c 0x01 0x00 0x00 0x3d69650 0x01 0x00 0x00 0x3d69654 0x01 0x00 0x00 0x3d69658 0x01 0x00 0x00 0x3d6965c 0x01 0x00 0x00 0x3d69660 0x01 0x00 0x00 0x3d69664 0x01 0x00 0x00 0x3d69668 0x01 0x00 0x00 0x3d6966c 0x01 0x00 0x00 0x3d69670 0x01 0x00 0x00 0x3d69674 0x01 0x00 0x00 0x3d69678 0x01 0x00 0x00 0x3d6967c 0x01 0x00 0x00 0x3d69800 0x01 0x00 0x00 0x3d69804 0x01 0x00 0x00 0x3d69808 0x01 0x00 0x00 0x3d6980c 0x01 0x00 0x00 0x3d69810 0x01 0x00 0x00 0x3d69814 0x01 0x00 0x00 0x3d69818 0x01 0x00 0x00 0x3d6981c 0x01 0x00 0x00 0x3d69820 0x01 0x00 0x00 0x3d69824 0x01 0x00 0x00 0x3d69828 0x01 0x00 0x00 0x3d6982c 0x01 0x00 0x00 0x3d69830 0x01 0x00 0x00 0x3d69834 0x01 0x00 0x00 0x3d69838 0x01 0x00 0x00 0x3d6983c 0x01 0x00 0x00 0x3d69840 0x01 0x00 0x00 0x3d69844 0x01 0x00 0x00 0x3d69848 0x01 0x00 0x00 0x3d6984c 0x01 0x00 0x00 0x3d69850 0x01 0x00 0x00 0x3d69854 0x01 0x00 0x00 0x3d69858 0x01 0x00 0x00 0x3d6985c 0x01 0x00 0x00 0x3d69860 0x01 0x00 0x00 0x3d69864 0x01 0x00 0x00 0x3d69868 0x01 0x00 0x00 0x3d6986c 0x01 0x00 0x00 0x3d69870 0x01 0x00 0x00 0x3d69874 0x01 0x00 0x00 0x3d69878 0x01 0x00 0x00 0x3d6987c 0x01 0x00 0x00 0x3d69900 0x01 0x00 0x00 0x3d69904 0x01 0x00 0x00 0x3d69908 0x01 0x00 0x00 0x3d6990c 0x01 0x00 0x00 0x3d69910 0x01 0x00 0x00 0x3d69914 0x01 0x00 0x00 0x3d69918 0x01 0x00 0x00 0x3d6991c 0x01 0x00 0x00 0x3d69920 0x01 0x00 0x00 0x3d69924 0x01 0x00 0x00 0x3d69928 0x01 0x00 0x00 0x3d6992c 0x01 0x00 0x00 0x3d69930 0x01 0x00 0x00 0x3d69934 0x01 0x00 0x00 0x3d69938 0x01 0x00 0x00 0x3d6993c 0x01 0x00 0x00 0x3d69940 0x01 0x00 0x00 0x3d69944 0x01 0x00 0x00 0x3d69948 0x01 0x00 0x00 0x3d6994c 0x01 0x00 0x00 0x3d69950 0x01 0x00 0x00 0x3d69954 0x01 0x00 0x00 0x3d69958 0x01 0x00 0x00 0x3d6995c 0x01 0x00 0x00 0x3d69960 0x01 0x00 0x00 0x3d69964 0x01 0x00 0x00 0x3d69968 0x01 0x00 0x00 0x3d6996c 0x01 0x00 0x00 0x3d69970 0x01 0x00 0x00 0x3d69974 0x01 0x00 0x00 0x3d69978 0x01 0x00 0x00 0x3d6997c 0x01 0x00 0x00 0x3d69e00 0x01 0x00 0x00 0x3d69e04 0x01 0x00 0x00 0x3d69e0c 0x01 0x00 0x00 0x3d69e10 0x01 0x00 0x00 0x3d69e14 0x01 0x00 0x00 0x3d69e1c 0x01 0x00 0x00 0x3d69e20 0x01 0x00 0x00 0x3d69e24 0x01 0x00 0x00 0x3d69e2c 0x01 0x00 0x00 0x3d69e30 0x01 0x00 0x00 0x3d69e34 0x01 0x00 0x00 0x3d69e3c 0x01 0x00 0x00 0x3d69e40 0x01 0x00 0x00 0x3d69e44 0x01 0x00 0x00 0x3d69e4c 0x01 0x00 0x00 0x3d69e50 0x01 0x00 0x00 0x3d69e54 0x01 0x00 0x00 0x3d69e5c 0x01 0x00 0x00 0x3d69e60 0x01 0x00 0x00 0x3d69e64 0x01 0x00 0x00 0x3d69e6c 0x01 0x00 0x00 0x3d69e70 0x01 0x00 0x00 0x3d69e74 0x01 0x00 0x00 0x3d69e7c 0x01 0x00 0x00 0x3d69e80 0x01 0x00 0x00 0x3d69e84 0x01 0x00 0x00 0x3d69e8c 0x01 0x00 0x00 0x3d69ea0 0x01 0x00 0x00 0x3d69ea4 0x01 0x00 0x00 0x3d69ea8 0x01 0x00 0x00 0x3d69eac 0x01 0x00 0x00 0x3d69eb0 0x01 0x00 0x00 0x3d69eb4 0x01 0x00 0x00 0x3d69eb8 0x01 0x00 0x00 0x3d69ebc 0x01 0x00 0x00 0x3d69ec0 0x01 0x00 0x00 0x3d69ec4 0x01 0x00 0x00 0x3d69ec8 0x01 0x00 0x00 0x3d69ecc 0x01 0x00 0x00 0x3d69ed0 0x01 0x00 0x00 0x3d69ed4 0x01 0x00 0x00 0x3d69ed8 0x01 0x00 0x00 0x3d69edc 0x01 0x00 0x00 0x3d69ee0 0x01 0x00 0x00 0x3d69ee4 0x01 0x00 0x00 0x3d69f00 0x01 0x00 0x00 0x3d69f04 0x01 0x00 0x00 0x3d69f10 0x01 0x00 0x00 0x3d69f14 0x01 0x00 0x00 0x3d69f20 0x01 0x00 0x00 0x3d69f24 0x01 0x00 0x00 0x3d69f30 0x01 0x00 0x00 0x3d69f34 0x01 0x00 0x00 0x3d69f40 0x01 0x00 0x00 0x3d69f44 0x01 0x00 0x00 0x3d69f50 0x01 0x00 0x00 0x3d69f54 0x01 0x00 0x00 0x3d69f60 0x01 0x00 0x00 0x3d69f64 0x01 0x00 0x00 0x3d69f70 0x01 0x00 0x00 0x3d69f74 0x01 0x00 0x00 0x3d69f80 0x01 0x00 0x00 0x3d69f84 0x01 0x00 0x00 0x3d69ff0 0x01 0x00 0x00 0x3d69ff4 0x01 0x00 0x00 0x3d6a000 0x01 0x00 0x00 0x3d6a004 0x01 0x00 0x00 0x3d6a008 0x01 0x00 0x00 0x3d6a00c 0x01 0x00 0x00 0x3d6a010 0x01 0x00 0x00 0x3d6a014 0x01 0x00 0x00 0x3d6a018 0x01 0x00 0x00 0x3d6a01c 0x01 0x00 0x00 0x3d6a020 0x01 0x00 0x00 0x3d6a058 0x01 0x00 0x00 0x3d6a078 0x01 0x00 0x00 0x3d6a098 0x01 0x00 0x00 0x3d6a0b8 0x01 0x00 0x00 0x3d6a0d8 0x01 0x00 0x00 0x3d6a0f8 0x01 0x00 0x00 0x3d6a118 0x01 0x00 0x00 0x3d6a138 0x01 0x00 0x00 0x3d6a158 0x01 0x00 0x00 0x3d6a20c 0x01 0x00 0x00 0x3d6a210 0x01 0x00 0x00 0x3d6a240 0x01 0x00 0x00 0x3d6a244 0x01 0x00 0x00 0x3d6a248 0x01 0x00 0x00 0x3d6a24c 0x01 0x00 0x00 0x3d6a250 0x01 0x00 0x00 0x3d6a254 0x01 0x00 0x00 0x3d6a258 0x01 0x00 0x00 0x3d6a25c 0x01 0x00 0x00 0x3d6a260 0x01 0x00 0x00 0x3d6a264 0x01 0x00 0x00 0x3d6a268 0x01 0x00 0x00 0x3d6a26c 0x01 0x00 0x00 0x3d6a270 0x01 0x00 0x00 0x3d6a274 0x01 0x00 0x00 0x3d6a278 0x01 0x00 0x00 0x3d6a27c 0x01 0x00 0x00 0x3d6a280 0x01 0x00 0x00 0x3d6a284 0x01 0x00 0x00 0x3d6a288 0x01 0x00 0x00 0x3d6a28c 0x01 0x00 0x00 0x3d6a290 0x01 0x00 0x00 0x3d6a294 0x01 0x00 0x00 0x3d6a298 0x01 0x00 0x00 0x3d6a29c 0x01 0x00 0x00 0x3d6a2a0 0x01 0x00 0x00 0x3d6a2a4 0x01 0x00 0x00 0x3d6a2a8 0x01 0x00 0x00 0x3d6a2ac 0x01 0x00 0x00 0x3d6a2b0 0x01 0x00 0x00 0x3d6a2b4 0x01 0x00 0x00 0x3d6a2b8 0x01 0x00 0x00 0x3d6a2bc 0x01 0x00 0x00 0x3d6a2c0 0x01 0x00 0x00 0x3d6a2c4 0x01 0x00 0x00 0x3d6a2c8 0x01 0x00 0x00 0x3d6a2cc 0x01 0x00 0x00 0x3d6a400 0x01 0x00 0x00 0x3d6a404 0x01 0x00 0x00 0x3d6a408 0x01 0x00 0x00 0x3d6a40c 0x01 0x00 0x00 0x3d6a410 0x01 0x00 0x00 0x3d6a414 0x01 0x00 0x00 0x3d6a418 0x01 0x00 0x00 0x3d6a41c 0x01 0x00 0x00 0x3d6a420 0x01 0x00 0x00 0x3d6a424 0x01 0x00 0x00 0x3d6a428 0x01 0x00 0x00 0x3d6a42c 0x01 0x00 0x00 0x3d6a430 0x01 0x00 0x00 0x3d6a434 0x01 0x00 0x00 0x3d6a438 0x01 0x00 0x00 0x3d6a43c 0x01 0x00 0x00 0x3d6a440 0x01 0x00 0x00 0x3d6a444 0x01 0x00 0x00 0x3d6a448 0x01 0x00 0x00 0x3d6a44c 0x01 0x00 0x00 0x3d6a450 0x01 0x00 0x00 0x3d6a454 0x01 0x00 0x00 0x3d6a458 0x01 0x00 0x00 0x3d6a45c 0x01 0x00 0x00 0x3d6a460 0x01 0x00 0x00 0x3d6a464 0x01 0x00 0x00 0x3d6a468 0x01 0x00 0x00 0x3d6a46c 0x01 0x00 0x00 0x3d6a470 0x01 0x00 0x00 0x3d6a474 0x01 0x00 0x00 0x3d6a478 0x01 0x00 0x00 0x3d6a47c 0x01 0x00 0x00 0x3d6a480 0x01 0x00 0x00 0x3d6a484 0x01 0x00 0x00 0x3d6a488 0x01 0x00 0x00 0x3d6a48c 0x01 0x00 0x00 0x3d6a490 0x01 0x00 0x00 0x3d6a494 0x01 0x00 0x00 0x3d6a498 0x01 0x00 0x00 0x3d6a49c 0x01 0x00 0x00 0x3d6a4a0 0x01 0x00 0x00 0x3d6a4a4 0x01 0x00 0x00 0x3d6a4a8 0x01 0x00 0x00 0x3d6a4ac 0x01 0x00 0x00 0x3d6a500 0x01 0x00 0x00 0x3d90000 0x01 0x00 0x00 0x3d90004 0x01 0x00 0x00 0x3d90008 0x01 0x00 0x00 0x3d9000c 0x01 0x00 0x00 0x3d90010 0x01 0x00 0x00 0x3d90014 0x01 0x00 0x00 0x3d90018 0x01 0x00 0x00 0x3d9001c 0x01 0x00 0x00 0x3d90020 0x01 0x00 0x00 0x3d90024 0x01 0x00 0x00 0x3d90028 0x01 0x00 0x00 0x3d9002c 0x01 0x00 0x00 0x3d90030 0x01 0x00 0x00 0x3d90034 0x01 0x00 0x00 0x3d90038 0x01 0x00 0x00 0x3d9003c 0x01 0x00 0x00 0x3d91000 0x01 0x00 0x00 0x3d91004 0x01 0x00 0x00 0x3d91008 0x01 0x00 0x00 0x3d9100c 0x01 0x00 0x00 0x3d91010 0x01 0x00 0x00 0x3d91014 0x01 0x00 0x00 0x3d91018 0x01 0x00 0x00 0x3d9101c 0x01 0x00 0x00 0x3d91020 0x01 0x00 0x00 0x3d91024 0x01 0x00 0x00 0x3d91028 0x01 0x00 0x00 0x3d9102c 0x01 0x00 0x00 0x3d91030 0x01 0x00 0x00 0x3d91034 0x01 0x00 0x00 0x3d91038 0x01 0x00 0x00 0x3d9103c 0x01 0x00 0x00 0x3d9e0c8 0x01 0x00 0x00 0xabe0028 0x01 0x00 0x00 0xaae0028 0x01 0x00>;
|
|
};
|
|
};
|
|
|
|
mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <0xf6>;
|
|
|
|
c0_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x00>;
|
|
};
|
|
|
|
c100_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x01>;
|
|
};
|
|
|
|
c200_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x02>;
|
|
};
|
|
|
|
c300_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x03>;
|
|
};
|
|
|
|
c400_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x04>;
|
|
};
|
|
|
|
c500_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x05>;
|
|
};
|
|
|
|
c600_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x06>;
|
|
};
|
|
|
|
c700_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x07>;
|
|
};
|
|
|
|
l1_icache0 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x60>;
|
|
};
|
|
|
|
l1_icache100 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x61>;
|
|
};
|
|
|
|
l1_icache200 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x62>;
|
|
};
|
|
|
|
l1_icache300 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x63>;
|
|
};
|
|
|
|
l1_icache400 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x64>;
|
|
};
|
|
|
|
l1_icache500 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x65>;
|
|
};
|
|
|
|
l1_icache600 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x66>;
|
|
};
|
|
|
|
l1_icache700 {
|
|
qcom,dump-size = <0x22100>;
|
|
qcom,dump-id = <0x67>;
|
|
};
|
|
|
|
l1_dcache0 {
|
|
qcom,dump-size = <0x12100>;
|
|
qcom,dump-id = <0x80>;
|
|
};
|
|
|
|
l1_dcache100 {
|
|
qcom,dump-size = <0x12100>;
|
|
qcom,dump-id = <0x81>;
|
|
};
|
|
|
|
l1_dcache200 {
|
|
qcom,dump-size = <0x1a100>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
l1_dcache300 {
|
|
qcom,dump-size = <0x1a100>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
l1_dcache400 {
|
|
qcom,dump-size = <0x1a100>;
|
|
qcom,dump-id = <0x84>;
|
|
};
|
|
|
|
l1_dcache500 {
|
|
qcom,dump-size = <0x1a100>;
|
|
qcom,dump-id = <0x85>;
|
|
};
|
|
|
|
l1_dcache600 {
|
|
qcom,dump-size = <0x1a100>;
|
|
qcom,dump-id = <0x86>;
|
|
};
|
|
|
|
l1_dcache700 {
|
|
qcom,dump-size = <0x1a100>;
|
|
qcom,dump-id = <0x87>;
|
|
};
|
|
|
|
l1_itlb700 {
|
|
qcom,dump-size = <0x600>;
|
|
qcom,dump-id = <0x27>;
|
|
};
|
|
|
|
l1_dtlb700 {
|
|
qcom,dump-size = <0xa00>;
|
|
qcom,dump-id = <0x47>;
|
|
};
|
|
|
|
l2_cache0 {
|
|
qcom,dump-size = <0x90100>;
|
|
qcom,dump-id = <0xc0>;
|
|
};
|
|
|
|
l2_cache100 {
|
|
qcom,dump-size = <0x90100>;
|
|
qcom,dump-id = <0xc1>;
|
|
};
|
|
|
|
l2_cache200 {
|
|
qcom,dump-size = <0xd0100>;
|
|
qcom,dump-id = <0xc2>;
|
|
};
|
|
|
|
l2_cache300 {
|
|
qcom,dump-size = <0xd0100>;
|
|
qcom,dump-id = <0xc3>;
|
|
};
|
|
|
|
l2_cache400 {
|
|
qcom,dump-size = <0xd0100>;
|
|
qcom,dump-id = <0xc4>;
|
|
};
|
|
|
|
l2_cache500 {
|
|
qcom,dump-size = <0xd0100>;
|
|
qcom,dump-id = <0xc5>;
|
|
};
|
|
|
|
l2_cache600 {
|
|
qcom,dump-size = <0xd0100>;
|
|
qcom,dump-id = <0xc6>;
|
|
};
|
|
|
|
l2_cache700 {
|
|
qcom,dump-size = <0x340100>;
|
|
qcom,dump-id = <0xc7>;
|
|
};
|
|
|
|
l2_tlb0 {
|
|
qcom,dump-size = <0xf700>;
|
|
qcom,dump-id = <0x120>;
|
|
};
|
|
|
|
l2_tlb100 {
|
|
qcom,dump-size = <0xf700>;
|
|
qcom,dump-id = <0x121>;
|
|
};
|
|
|
|
l2_tlb700 {
|
|
qcom,dump-size = <0xa900>;
|
|
qcom,dump-id = <0x127>;
|
|
};
|
|
|
|
l1dcdirty0 {
|
|
qcom,dump-size = <0x2100>;
|
|
qcom,dump-id = <0x170>;
|
|
};
|
|
|
|
l1dcdirty100 {
|
|
qcom,dump-size = <0x2100>;
|
|
qcom,dump-id = <0x171>;
|
|
};
|
|
|
|
l1dcmte0 {
|
|
qcom,dump-size = <0x2100>;
|
|
qcom,dump-id = <0x180>;
|
|
};
|
|
|
|
l1dcmte100 {
|
|
qcom,dump-size = <0x2100>;
|
|
qcom,dump-id = <0x181>;
|
|
};
|
|
|
|
l2dcmte0 {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x190>;
|
|
};
|
|
|
|
l2dcmte100 {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x191>;
|
|
};
|
|
|
|
l0mopca700 {
|
|
qcom,dump-size = <0x4100>;
|
|
qcom,dump-id = <0x1a7>;
|
|
};
|
|
|
|
l2victim700 {
|
|
qcom,dump-size = <0x2100>;
|
|
qcom,dump-id = <0x1e7>;
|
|
};
|
|
|
|
l2tldtcsp200 {
|
|
qcom,dump-size = <0x7900>;
|
|
qcom,dump-id = <0x202>;
|
|
};
|
|
|
|
l2tldtcsp300 {
|
|
qcom,dump-size = <0x7900>;
|
|
qcom,dump-id = <0x203>;
|
|
};
|
|
|
|
l2tldtcsp400 {
|
|
qcom,dump-size = <0x7900>;
|
|
qcom,dump-id = <0x204>;
|
|
};
|
|
|
|
l2tldtcsp500 {
|
|
qcom,dump-size = <0x7900>;
|
|
qcom,dump-id = <0x205>;
|
|
};
|
|
|
|
l2tldtcsp600 {
|
|
qcom,dump-size = <0x7900>;
|
|
qcom,dump-id = <0x206>;
|
|
};
|
|
|
|
l2tldtcmp200 {
|
|
qcom,dump-size = <0x1300>;
|
|
qcom,dump-id = <0x212>;
|
|
};
|
|
|
|
l2tldtcmp300 {
|
|
qcom,dump-size = <0x1300>;
|
|
qcom,dump-id = <0x213>;
|
|
};
|
|
|
|
l2tldtcmp400 {
|
|
qcom,dump-size = <0x1300>;
|
|
qcom,dump-id = <0x214>;
|
|
};
|
|
|
|
l2tldtcmp500 {
|
|
qcom,dump-size = <0x1300>;
|
|
qcom,dump-id = <0x215>;
|
|
};
|
|
|
|
l2tldtcmp600 {
|
|
qcom,dump-size = <0x1300>;
|
|
qcom,dump-id = <0x216>;
|
|
};
|
|
|
|
cpuss_reg {
|
|
qcom,dump-size = <0x36000>;
|
|
qcom,dump-id = <0xef>;
|
|
};
|
|
|
|
rpmh {
|
|
qcom,dump-size = <0x400000>;
|
|
qcom,dump-id = <0xec>;
|
|
};
|
|
|
|
rpm_sw {
|
|
qcom,dump-size = <0x28000>;
|
|
qcom,dump-id = <0xea>;
|
|
};
|
|
|
|
pmic {
|
|
qcom,dump-size = <0x200000>;
|
|
qcom,dump-id = <0xe4>;
|
|
};
|
|
|
|
fcm {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xee>;
|
|
};
|
|
|
|
etf_swao {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xf1>;
|
|
};
|
|
|
|
etr_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x100>;
|
|
};
|
|
|
|
etfswao_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x102>;
|
|
};
|
|
|
|
etr1_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x105>;
|
|
};
|
|
|
|
misc_data {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0xe8>;
|
|
};
|
|
|
|
etf_slpi {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf3>;
|
|
};
|
|
|
|
etfslpi_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x103>;
|
|
};
|
|
|
|
etf_lpass {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf4>;
|
|
};
|
|
|
|
etflpass_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x104>;
|
|
};
|
|
|
|
osm_reg {
|
|
qcom,dump-size = <0x400>;
|
|
qcom,dump-id = <0x163>;
|
|
};
|
|
|
|
pcu_reg {
|
|
qcom,dump-size = <0x400>;
|
|
qcom,dump-id = <0x164>;
|
|
};
|
|
|
|
fsm_data {
|
|
qcom,dump-size = <0x400>;
|
|
qcom,dump-id = <0x165>;
|
|
};
|
|
|
|
spr_cpu0 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f0>;
|
|
};
|
|
|
|
spr_cpu1 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f1>;
|
|
};
|
|
|
|
spr_cpu2 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f2>;
|
|
};
|
|
|
|
spr_cpu3 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f3>;
|
|
};
|
|
|
|
spr_cpu4 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f4>;
|
|
};
|
|
|
|
spr_cpu5 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f5>;
|
|
};
|
|
|
|
spr_cpu6 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f6>;
|
|
};
|
|
|
|
spr_cpu7 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f7>;
|
|
};
|
|
|
|
scandump_smmu {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x220>;
|
|
};
|
|
|
|
scandump_gpu {
|
|
qcom,dump-size = <0x300000>;
|
|
qcom,dump-id = <0x221>;
|
|
};
|
|
};
|
|
|
|
qcom,dma-heaps {
|
|
compatible = "qcom,dma-heaps";
|
|
|
|
qcom,display {
|
|
qcom,dma-heap-name = "qcom,display";
|
|
qcom,dma-heap-type = <0x02>;
|
|
qcom,max-align = <0x09>;
|
|
memory-region = <0xf7>;
|
|
};
|
|
|
|
qcom,qseecom {
|
|
qcom,dma-heap-name = "qcom,qseecom";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xa4>;
|
|
};
|
|
|
|
qcom,qseecom_ta {
|
|
qcom,dma-heap-name = "qcom,qseecom-ta";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xa5>;
|
|
};
|
|
|
|
qcom,sp_hlos {
|
|
qcom,dma-heap-name = "qcom,sp-hlos";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xf8>;
|
|
};
|
|
|
|
qcom,secure_sp_modem {
|
|
qcom,dma-heap-name = "qcom,secure-sp-modem";
|
|
qcom,dma-heap-type = <0x00>;
|
|
memory-region = <0xf9>;
|
|
qcom,token = <0x10800000>;
|
|
};
|
|
|
|
qcom,secure_cdsp {
|
|
qcom,dma-heap-name = "qcom,cma-secure-cdsp";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xfa>;
|
|
};
|
|
|
|
qcom,secure_sp_tz {
|
|
qcom,dma-heap-name = "qcom,secure-sp-tz";
|
|
qcom,dma-heap-type = <0x00>;
|
|
memory-region = <0xfb>;
|
|
qcom,token = <0x1000000>;
|
|
};
|
|
};
|
|
|
|
qcom,gpi-dma@a00000 {
|
|
compatible = "qcom,gpi-dma";
|
|
#dma-cells = <0x05>;
|
|
reg = <0xa00000 0x60000>;
|
|
reg-names = "gpi-top";
|
|
iommus = <0x4f 0xb6 0x00>;
|
|
qcom,max-num-gpii = <0x0c>;
|
|
interrupts = <0x00 0x117 0x04 0x00 0x118 0x04 0x00 0x119 0x04 0x00 0x11a 0x04 0x00 0x11b 0x04 0x00 0x11c 0x04 0x00 0x125 0x04 0x00 0x126 0x04 0x00 0x127 0x04 0x00 0x128 0x04 0x00 0x129 0x04 0x00 0x12a 0x04>;
|
|
qcom,static-gpii-mask = <0x03>;
|
|
qcom,gpii-mask = <0x0c>;
|
|
qcom,ev-factor = <0x01>;
|
|
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
|
qcom,gpi-ee-offset = <0x10000>;
|
|
dma-coherent;
|
|
status = "ok";
|
|
phandle = <0x100>;
|
|
};
|
|
|
|
qcom,qupv3_1_geni_se@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0xac0000 0x2000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <0x2c 0x8f 0x2c 0x90>;
|
|
iommus = <0x4f 0xa3 0x00>;
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
ranges;
|
|
status = "ok";
|
|
phandle = <0x416>;
|
|
|
|
i2c@a80000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x161 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x64>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0xfd 0xfe>;
|
|
pinctrl-1 = <0xff>;
|
|
dmas = <0x100 0x00 0x00 0x03 0x40 0x00 0x100 0x01 0x00 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x417>;
|
|
};
|
|
|
|
spi@a80000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x161 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x64>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x101 0x102 0x103 0x104>;
|
|
pinctrl-1 = <0x105>;
|
|
dmas = <0x100 0x00 0x00 0x01 0x40 0x00 0x100 0x01 0x00 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x418>;
|
|
};
|
|
|
|
i3c-master@a80000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0xa80000 0x4000 0xec90000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x64>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep", "disable";
|
|
pinctrl-0 = <0x106 0x107>;
|
|
pinctrl-1 = <0x108 0x109>;
|
|
pinctrl-2 = <0x10a>;
|
|
interrupts-extended = <0x01 0x00 0x161 0x04 0x2e 0x1f 0x04 0x2e 0x1e 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x00>;
|
|
dmas = <0x100 0x00 0x00 0x04 0x40 0x00 0x100 0x01 0x00 0x04 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x419>;
|
|
};
|
|
|
|
i2c@a84000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x162 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x66>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x10b 0x10c>;
|
|
pinctrl-1 = <0x10d>;
|
|
dmas = <0x100 0x00 0x01 0x03 0x40 0x00 0x100 0x01 0x01 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x41a>;
|
|
};
|
|
|
|
spi@a84000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x162 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x66>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x10e 0x10f 0x110 0x111>;
|
|
pinctrl-1 = <0x112>;
|
|
dmas = <0x100 0x00 0x01 0x01 0x40 0x00 0x100 0x01 0x01 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x41b>;
|
|
};
|
|
|
|
i2c@a88000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x163 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x68>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x113 0x114>;
|
|
pinctrl-1 = <0x115>;
|
|
dmas = <0x100 0x00 0x02 0x03 0x40 0x00 0x100 0x01 0x02 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x41c>;
|
|
};
|
|
|
|
spi@a88000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x163 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x68>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x116 0x117 0x118 0x119>;
|
|
pinctrl-1 = <0x11a>;
|
|
dmas = <0x100 0x00 0x02 0x01 0x40 0x00 0x100 0x01 0x02 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x41d>;
|
|
};
|
|
|
|
i2c@a8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x164 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x6a>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x11b 0x11c>;
|
|
pinctrl-1 = <0x11d>;
|
|
dmas = <0x100 0x00 0x03 0x03 0x40 0x00 0x100 0x01 0x03 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "ok";
|
|
phandle = <0x41e>;
|
|
|
|
wcd939x_i2c@e {
|
|
compatible = "qcom,wcd939x-i2c";
|
|
reg = <0x0e>;
|
|
vdd-usb-cp-supply = <0x11e>;
|
|
phandle = <0x41f>;
|
|
};
|
|
};
|
|
|
|
spi@a8c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x164 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x6a>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x11f 0x120 0x121 0x122>;
|
|
pinctrl-1 = <0x123>;
|
|
dmas = <0x100 0x00 0x03 0x01 0x40 0x00 0x100 0x01 0x03 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x420>;
|
|
};
|
|
|
|
i2c@a90000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x165 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x6c>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x124 0x125>;
|
|
pinctrl-1 = <0x126>;
|
|
dmas = <0x100 0x00 0x04 0x03 0x40 0x02 0x100 0x01 0x04 0x03 0x40 0x02>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x421>;
|
|
};
|
|
|
|
spi@a90000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x165 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x6c>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x127 0x128 0x129 0x12a>;
|
|
pinctrl-1 = <0x12b>;
|
|
dmas = <0x100 0x00 0x04 0x01 0x40 0x02 0x100 0x01 0x04 0x01 0x40 0x02>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x422>;
|
|
};
|
|
|
|
i3c-master@a90000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0xa90000 0x4000 0xecb0000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x6c>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep", "disable";
|
|
pinctrl-0 = <0x12c 0x12d>;
|
|
pinctrl-1 = <0x12e 0x12f>;
|
|
pinctrl-2 = <0x130>;
|
|
interrupts-extended = <0x01 0x00 0x165 0x04 0x2e 0x23 0x04 0x2e 0x22 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x04>;
|
|
dmas = <0x100 0x00 0x04 0x04 0x40 0x00 0x100 0x01 0x04 0x04 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x423>;
|
|
};
|
|
|
|
i2c@a94000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x166 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x6e>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x131 0x132>;
|
|
pinctrl-1 = <0x133>;
|
|
dmas = <0x100 0x00 0x05 0x03 0x40 0x00 0x100 0x01 0x05 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x424>;
|
|
};
|
|
|
|
spi@a94000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x166 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x6e>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x134 0x135 0x136 0x137>;
|
|
pinctrl-1 = <0x138>;
|
|
dmas = <0x100 0x00 0x05 0x01 0x40 0x00 0x100 0x01 0x05 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x425>;
|
|
};
|
|
|
|
i2c@a98000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa98000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x16b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x70>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x139 0x13a>;
|
|
pinctrl-1 = <0x13b>;
|
|
dmas = <0x100 0x00 0x06 0x03 0x40 0x00 0x100 0x01 0x06 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
qcom,shared;
|
|
status = "disabled";
|
|
phandle = <0x426>;
|
|
};
|
|
|
|
spi@a98000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa98000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x16b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x70>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x13c 0x13d 0x13e 0x13f>;
|
|
pinctrl-1 = <0x140>;
|
|
dmas = <0x100 0x00 0x06 0x01 0x40 0x00 0x100 0x01 0x06 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x427>;
|
|
};
|
|
|
|
i2c@a9c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa9c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x243 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x72>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x141 0x142>;
|
|
pinctrl-1 = <0x143>;
|
|
dmas = <0x100 0x00 0x07 0x03 0x40 0x04 0x100 0x01 0x07 0x03 0x40 0x04>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x428>;
|
|
};
|
|
|
|
spi@a9c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa9c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x243 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x72>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x144 0x145 0x146 0x147>;
|
|
pinctrl-1 = <0x148>;
|
|
dmas = <0x100 0x00 0x07 0x01 0x40 0x04 0x100 0x01 0x07 0x01 0x40 0x04>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x429>;
|
|
};
|
|
};
|
|
|
|
qcom,gpi-dma@800000 {
|
|
compatible = "qcom,gpi-dma";
|
|
#dma-cells = <0x05>;
|
|
reg = <0x800000 0x60000>;
|
|
reg-names = "gpi-top";
|
|
iommus = <0x4f 0x436 0x00>;
|
|
qcom,max-num-gpii = <0x0c>;
|
|
interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04 0x00 0x256 0x04 0x00 0x257 0x04>;
|
|
qcom,static-gpii-mask = <0x01>;
|
|
qcom,gpii-mask = <0x3e>;
|
|
qcom,ev-factor = <0x01>;
|
|
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
|
qcom,gpi-ee-offset = <0x10000>;
|
|
dma-coherent;
|
|
status = "ok";
|
|
phandle = <0x14c>;
|
|
};
|
|
|
|
qcom,qupv3_2_geni_se@8c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x8c0000 0x2000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <0x2c 0x93 0x2c 0x94>;
|
|
iommus = <0x4f 0x423 0x00>;
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
ranges;
|
|
status = "ok";
|
|
phandle = <0x42a>;
|
|
|
|
i2c@880000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x880000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x175 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x79>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x149 0x14a>;
|
|
pinctrl-1 = <0x14b>;
|
|
dmas = <0x14c 0x00 0x00 0x03 0x40 0x02 0x14c 0x01 0x00 0x03 0x40 0x02>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x42b>;
|
|
};
|
|
|
|
spi@880000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x880000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x175 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x79>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x14d 0x14e 0x14f 0x150>;
|
|
pinctrl-1 = <0x151>;
|
|
dmas = <0x14c 0x00 0x00 0x01 0x40 0x00 0x14c 0x01 0x00 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x42c>;
|
|
};
|
|
|
|
i3c-master@880000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x880000 0x4000 0xecd0000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x79>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep", "disable";
|
|
pinctrl-0 = <0x152 0x153>;
|
|
pinctrl-1 = <0x154 0x155>;
|
|
pinctrl-2 = <0x156>;
|
|
interrupts-extended = <0x01 0x00 0x175 0x04 0x2e 0x30 0x04 0x2e 0x2f 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x00>;
|
|
i3c_rgltr1-supply = <0x157>;
|
|
dmas = <0x14c 0x00 0x00 0x04 0x400 0x00 0x14c 0x01 0x00 0x04 0x400 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x42d>;
|
|
};
|
|
|
|
i2c@884000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x884000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x247 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x7b>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x158 0x159>;
|
|
pinctrl-1 = <0x15a>;
|
|
dmas = <0x14c 0x00 0x01 0x03 0x400 0x02 0x14c 0x01 0x01 0x03 0x400 0x02>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x42e>;
|
|
};
|
|
|
|
spi@884000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x884000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x247 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x7b>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x15b 0x15c 0x15d 0x15e>;
|
|
pinctrl-1 = <0x15f>;
|
|
dmas = <0x14c 0x00 0x01 0x01 0x40 0x02 0x14c 0x01 0x01 0x01 0x40 0x02>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x42f>;
|
|
};
|
|
|
|
i2c@888000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x888000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x248 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x7d>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x160 0x161>;
|
|
pinctrl-1 = <0x162>;
|
|
dmas = <0x14c 0x00 0x02 0x03 0x40 0x00 0x14c 0x01 0x02 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x430>;
|
|
};
|
|
|
|
spi@888000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x888000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x248 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x7d>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x163 0x164 0x165 0x166>;
|
|
pinctrl-1 = <0x167>;
|
|
dmas = <0x14c 0x00 0x02 0x01 0x40 0x00 0x14c 0x01 0x02 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x431>;
|
|
};
|
|
|
|
i3c-master@888000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x888000 0x4000 0xb00000 0x10000>;
|
|
clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk";
|
|
clocks = <0x2c 0x7d 0x2c 0x77 0x2c 0x91 0x2c 0x76>;
|
|
qcom,ibic-naon;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep", "disable";
|
|
pinctrl-0 = <0x168 0x169>;
|
|
pinctrl-1 = <0x16a 0x16b>;
|
|
pinctrl-2 = <0x16c>;
|
|
interrupts = <0x00 0x248 0x04 0x00 0xef 0x04 0x00 0xee 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x07>;
|
|
dmas = <0x14c 0x00 0x02 0x04 0x40 0x00 0x14c 0x01 0x02 0x04 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x432>;
|
|
};
|
|
|
|
i3c-master@88c000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x888c00 0x4000 0xb10000 0x10000>;
|
|
clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk";
|
|
clocks = <0x2c 0x7f 0x2c 0x78 0x2c 0x92 0x2c 0x76>;
|
|
qcom,ibic-naon;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep", "disable";
|
|
pinctrl-0 = <0x16d 0x16e>;
|
|
pinctrl-1 = <0x16f 0x170>;
|
|
pinctrl-2 = <0x171>;
|
|
interrupts = <0x00 0x249 0x04 0x00 0xf1 0x04 0x00 0xf0 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x08>;
|
|
dmas = <0x14c 0x00 0x03 0x04 0x40 0x00 0x14c 0x01 0x03 0x04 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x433>;
|
|
};
|
|
|
|
i2c@88c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x88c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x249 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x7f>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x172 0x173>;
|
|
pinctrl-1 = <0x174>;
|
|
dmas = <0x14c 0x00 0x03 0x03 0x40 0x00 0x14c 0x01 0x03 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x434>;
|
|
};
|
|
|
|
spi@88c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x88c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x249 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x7f>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x175 0x176 0x177 0x178>;
|
|
pinctrl-1 = <0x179>;
|
|
dmas = <0x14c 0x00 0x03 0x01 0x40 0x00 0x14c 0x01 0x03 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x435>;
|
|
};
|
|
|
|
i2c@890000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x890000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x24a 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x81>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x17a 0x17b>;
|
|
pinctrl-1 = <0x17c>;
|
|
dmas = <0x14c 0x00 0x04 0x03 0x40 0x00 0x14c 0x01 0x04 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x436>;
|
|
};
|
|
|
|
spi@890000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x890000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x24a 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x81>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x17d 0x17e 0x17f 0x180>;
|
|
pinctrl-1 = <0x181>;
|
|
dmas = <0x14c 0x00 0x04 0x01 0x40 0x00 0x14c 0x01 0x04 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x437>;
|
|
};
|
|
|
|
i2c@894000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x894000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x24b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x83>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x182 0x183>;
|
|
pinctrl-1 = <0x184>;
|
|
dmas = <0x14c 0x00 0x05 0x03 0x40 0x00 0x14c 0x01 0x05 0x03 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x438>;
|
|
};
|
|
|
|
spi@894000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x894000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x24b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x83>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x185 0x186 0x187 0x188>;
|
|
pinctrl-1 = <0x189>;
|
|
dmas = <0x14c 0x00 0x05 0x01 0x40 0x00 0x14c 0x01 0x05 0x01 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x439>;
|
|
};
|
|
|
|
q2spi@894000 {
|
|
compatible = "qcom,q2spi-msm-geni";
|
|
reg = <0x894000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts-extended = <0x01 0x00 0x24b 0x04 0xc1 0x17 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x83>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
mosi-pin = <0xc1 0x15 0x00>;
|
|
clk-pin = <0xc1 0x16 0x00>;
|
|
pinctrl-names = "default", "active", "sleep", "shutdown";
|
|
pinctrl-0 = <0x18a 0x18b>;
|
|
pinctrl-1 = <0x18c 0x18d 0x18e 0x18f>;
|
|
pinctrl-2 = <0x18c 0x190 0x18e 0x191>;
|
|
pinctrl-3 = <0x18a 0x18b>;
|
|
dmas = <0x14c 0x00 0x05 0x0e 0x40 0x00 0x14c 0x01 0x05 0x0e 0x40 0x00>;
|
|
dma-names = "tx", "rx";
|
|
q2spi-max-frequency = <0x1e84800>;
|
|
status = "disabled";
|
|
phandle = <0x43a>;
|
|
};
|
|
|
|
qcom,qup_uart@898000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0x898000 0x4000>;
|
|
reg-names = "se_phys";
|
|
interrupts-extended = <0x01 0x00 0x1cd 0x04 0xc1 0x1b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x2c 0x85>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "active", "sleep", "shutdown";
|
|
pinctrl-0 = <0x192 0x193 0x194 0x195>;
|
|
pinctrl-1 = <0x196 0x197 0x198 0x199>;
|
|
pinctrl-2 = <0x196 0x197 0x198 0x195>;
|
|
pinctrl-3 = <0x192 0x193 0x194 0x195>;
|
|
qcom,wakeup-byte = <0xfd>;
|
|
status = "disabled";
|
|
phandle = <0x43b>;
|
|
};
|
|
|
|
qcom,qup_uart@89c000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0x89c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x1ce 0x04>;
|
|
clock-names = "se";
|
|
clocks = <0x2c 0x87>;
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
|
interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x19a 0x19b>;
|
|
pinctrl-1 = <0x19c>;
|
|
status = "ok";
|
|
phandle = <0x43c>;
|
|
};
|
|
};
|
|
|
|
qcom,qupv3_i2c_geni_se@9c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x9c0000 0x2000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <0x2c 0x5f 0x2c 0x5f>;
|
|
ranges;
|
|
status = "ok";
|
|
phandle = <0x43d>;
|
|
|
|
i2c@980000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x980000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d0 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x4b 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x19d 0x19e>;
|
|
pinctrl-1 = <0x19f>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x43e>;
|
|
};
|
|
|
|
i2c@984000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x984000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d1 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x4d 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1a0 0x1a1>;
|
|
pinctrl-1 = <0x1a2>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x43f>;
|
|
};
|
|
|
|
i2c@988000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x988000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d2 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x4f 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1a3 0x1a4>;
|
|
pinctrl-1 = <0x1a5>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x440>;
|
|
};
|
|
|
|
i2c@98c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x98c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d3 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x51 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1a6 0x1a7>;
|
|
pinctrl-1 = <0x1a8>;
|
|
qcom,i2c-hub;
|
|
status = "ok";
|
|
phandle = <0x441>;
|
|
};
|
|
|
|
i2c@990000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x990000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d4 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x53 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1a9 0x1aa>;
|
|
pinctrl-1 = <0x1ab>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x442>;
|
|
};
|
|
|
|
i2c@994000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x994000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d5 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x55 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1ac 0x1ad>;
|
|
pinctrl-1 = <0x1ae>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x443>;
|
|
};
|
|
|
|
i2c@998000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x998000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d6 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x57 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1af 0x1b0>;
|
|
pinctrl-1 = <0x1b1>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x444>;
|
|
};
|
|
|
|
i2c@99c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x99c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d7 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x59 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1b2 0x1b3>;
|
|
pinctrl-1 = <0x1b4>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x445>;
|
|
};
|
|
|
|
i2c@9a0000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x9a0000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d8 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x5b 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1b5 0x1b6>;
|
|
pinctrl-1 = <0x1b7>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x446>;
|
|
};
|
|
|
|
i2c@9a4000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x9a4000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d9 0x04>;
|
|
clock-names = "se-clk", "core-clk";
|
|
clocks = <0x2c 0x5d 0x2c 0x4a>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x1b8 0x1b9>;
|
|
pinctrl-1 = <0x1ba>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x447>;
|
|
};
|
|
};
|
|
|
|
ssusb@a600000 {
|
|
compatible = "qcom,dwc-usb3-msm";
|
|
reg = <0xa600000 0x100000 0x1fc6000 0x04>;
|
|
reg-names = "core_base", "tcsr_dyn_en_dis";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
USB3_GDSC-supply = <0xe9>;
|
|
clocks = <0x2c 0xb0 0x2c 0x0a 0x2c 0x03 0x2c 0xb2 0x2c 0xb5>;
|
|
clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk";
|
|
resets = <0x2c 0x1a>;
|
|
reset-names = "core_reset";
|
|
interrupts-extended = <0x01 0x00 0x82 0x04 0x2e 0x0e 0x01 0x2e 0x0f 0x01 0x2e 0x11 0x04>;
|
|
interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
|
|
qcom,use-pdc-interrupts;
|
|
qcom,use-eusb2-phy;
|
|
qcom,dis-sending-cm-l1-quirk;
|
|
qcom,core-clk-rate = <0xbebc200>;
|
|
qcom,core-clk-rate-hs = <0x3f940ab>;
|
|
qcom,core-clk-rate-disconnected = <0x7f28155>;
|
|
qcom,pm-qos-latency = <0x02>;
|
|
extcon = <0x1bb>;
|
|
qcom,num-gsi-evt-buffs = <0x03>;
|
|
qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>;
|
|
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
|
|
interconnects = <0x56 0x36 0x3e 0x200 0x56 0x36 0x51 0x214 0x50 0x03 0x51 0x22a>;
|
|
dummy-supply = <0x4f>;
|
|
phandle = <0x448>;
|
|
|
|
dwc3@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0xa600000 0xd93c>;
|
|
iommus = <0x4f 0x40 0x00>;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
|
dma-coherent;
|
|
interrupts = <0x00 0x85 0x04>;
|
|
usb-phy = <0x1bc 0x1bd>;
|
|
snps,disable-clk-gating;
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = [00];
|
|
snps,is-utmi-l1-suspend;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,ssp-u3-u0-quirk;
|
|
tx-fifo-resize;
|
|
dr_mode = "otg";
|
|
maximum-speed = "super-speed-plus";
|
|
usb-role-switch;
|
|
};
|
|
};
|
|
|
|
hsphy@88e3000 {
|
|
compatible = "qcom,usb-snps-eusb2-phy";
|
|
reg = <0x88e3000 0x154 0x88e2000 0x04 0xc278000 0x04>;
|
|
reg-names = "eusb2_phy_base", "eud_enable_reg", "eud_detect_reg";
|
|
vdd-supply = <0x36>;
|
|
qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;
|
|
vdda12-supply = <0x37>;
|
|
clocks = <0x2d 0x1b 0x53 0x04>;
|
|
clock-names = "ref_clk_src", "ref_clk";
|
|
resets = <0x2c 0x15>;
|
|
reset-names = "phy_reset";
|
|
phandle = <0x1bc>;
|
|
};
|
|
|
|
ssphy@88e8000 {
|
|
compatible = "qcom,usb-ssphy-qmp-dp-combo";
|
|
reg = <0x88e8000 0x3000>;
|
|
reg-names = "qmp_phy_base";
|
|
vdd-supply = <0x1be>;
|
|
qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;
|
|
qcom,vdd-max-load-uA = <0xb798>;
|
|
core-supply = <0x37>;
|
|
usb3_dp_phy_gdsc-supply = <0xea>;
|
|
clocks = <0x2c 0xb6 0x2c 0xb9 0x2c 0xba 0x4a 0x2d 0x1b 0x53 0x05 0x2c 0xb8>;
|
|
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk";
|
|
resets = <0x2c 0x1b 0x2c 0x1d>;
|
|
reset-names = "global_phy_reset", "phy_reset";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1bf>;
|
|
qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x1e00>;
|
|
qcom,qmp-phy-init-seq = <0x1000 0xc0 0x1004 0x01 0x1010 0x02 0x1014 0x16 0x1018 0x36 0x101c 0x04 0x1020 0x16 0x1024 0x41 0x1028 0x41 0x102c 0x00 0x1030 0x55 0x1034 0x75 0x1038 0x01 0x103c 0x01 0x1048 0x25 0x104c 0x02 0x1050 0x5c 0x1054 0x0f 0x1058 0x5c 0x105c 0x0f 0x1060 0xc0 0x1064 0x01 0x1070 0x02 0x1074 0x16 0x1078 0x36 0x1080 0x08 0x1084 0x1a 0x1088 0x41 0x108c 0x00 0x1090 0x55 0x1094 0x75 0x1098 0x01 0x10a8 0x25 0x10ac 0x02 0x10bc 0x0a 0x10c0 0x01 0x10cc 0x62 0x10d0 0x02 0x10e8 0x0c 0x1110 0x1a 0x1124 0x14 0x1140 0x04 0x1170 0x20 0x1174 0x16 0x11a4 0xb6 0x11a8 0x4b 0x11ac 0x37 0x11b4 0x0c 0x1234 0x00 0x1238 0x00 0x123c 0x1f 0x1240 0x09 0x1284 0xf5 0x128c 0x3f 0x1290 0x3f 0x1294 0x5f 0x12a4 0x12 0x12e4 0x21 0x1408 0x0a 0x1414 0x06 0x1430 0x2f 0x1434 0x7f 0x143c 0xff 0x1440 0x0f 0x1444 0x99 0x144c 0x08 0x1450 0x08 0x1454 0x00 0x1458 0x0a 0x1460 0xa0 0x14d4 0x54 0x14d8 0x0f 0x14dc 0x13 0x14ec 0x0f 0x14f0 0x4a 0x14f4 0x0a 0x14f8 0x07 0x14fc 0x00 0x1510 0x47 0x151c 0x04 0x1524 0x0e 0x155c 0x3f 0x1560 0xbf 0x1564 0xff 0x1568 0xdf 0x156c 0xed 0x1570 0xdc 0x1574 0x5c 0x1578 0x9f 0x157c 0x1d 0x1580 0x3d 0x15a0 0x04 0x15a4 0x38 0x15a8 0x0c 0x15b0 0x10 0x15e4 0x14 0x15f8 0x08 0x1634 0x00 0x1638 0x00 0x163c 0x1f 0x1640 0x09 0x1684 0xf5 0x168c 0x3f 0x1690 0x3f 0x1694 0x5f 0x16a4 0x12 0x16e4 0x05 0x1808 0x0a 0x1814 0x06 0x1830 0x2f 0x1834 0x7f 0x183c 0xff 0x1840 0x0f 0x1844 0x99 0x184c 0x08 0x1850 0x08 0x1854 0x00 0x1858 0x0a 0x1860 0xa0 0x18d4 0x54 0x18d8 0x0f 0x18dc 0x13 0x18ec 0x0f 0x18f0 0x4a 0x18f4 0x0a 0x18f8 0x07 0x18fc 0x00 0x1910 0x47 0x191c 0x04 0x1924 0x0e 0x195c 0xbf 0x1960 0xbf 0x1964 0xbf 0x1968 0xdf 0x196c 0xfd 0x1970 0xdc 0x1974 0x5c 0x1978 0x9f 0x197c 0x1d 0x1980 0x3d 0x19a0 0x04 0x19a4 0x38 0x19a8 0x0c 0x19b0 0x10 0x19e4 0x14 0x19f8 0x08 0x1cc4 0xc4 0x1cc8 0x89 0x1ccc 0x20 0x1cd8 0x13 0x1cdc 0x21 0x1d88 0x99 0x1d90 0xe7 0x1d94 0x03 0x1db0 0x0a 0x1dc0 0x88 0x1dc4 0x13 0x1dd0 0x0c 0x1ddc 0x4b 0x1dec 0x10 0x1f00 0x68 0x1f18 0xf8 0x1f3c 0x07 0x1f40 0x40 0x1f44 0x00>;
|
|
phandle = <0x1bd>;
|
|
};
|
|
|
|
usb_audio_qmi_dev {
|
|
compatible = "qcom,usb-audio-qmi-dev";
|
|
iommus = <0x4f 0x100b 0x00>;
|
|
qcom,iommu-dma = "disabled";
|
|
qcom,usb-audio-stream-id = <0x0b>;
|
|
qcom,usb-audio-intr-num = <0x02>;
|
|
};
|
|
|
|
stm@10002000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb962>;
|
|
reg = <0x10002000 0x1000 0x16280000 0x180000>;
|
|
reg-names = "stm-base", "stm-stimulus-base";
|
|
atid = <0x10>;
|
|
coresight-name = "coresight-stm";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x449>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c0>;
|
|
phandle = <0x29e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
audio_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-audio-etm0";
|
|
qcom,inst-id = <0x05>;
|
|
atid = <0x28 0x29>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c1>;
|
|
phandle = <0x1c8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b30000 {
|
|
compatible = "qcom,coresight-dummy";
|
|
qcom,dummy-source;
|
|
atid = <0x1b>;
|
|
coresight-name = "coresight-tpdm-ddr-lpi";
|
|
phandle = <0x44a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c2>;
|
|
phandle = <0x205>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b46000 {
|
|
compatible = "qcom,coresight-dummy";
|
|
qcom,dummy-source;
|
|
coresight-name = "coresight-tpdm-lpass-lpi";
|
|
atid = <0x1a>;
|
|
phandle = <0x44b>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c3>;
|
|
phandle = <0x1c6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lpass_stm {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-lpass-stm";
|
|
qcom,dummy-source;
|
|
atid = <0x19>;
|
|
phandle = <0x44c>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c4>;
|
|
phandle = <0x1c5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b50000 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-lpass_lpi_1";
|
|
phandle = <0x44d>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c5>;
|
|
phandle = <0x1c4>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c6>;
|
|
phandle = <0x1c3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c7>;
|
|
phandle = <0x1c9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b44000 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-lpass_lpi_0";
|
|
phandle = <0x44e>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c8>;
|
|
phandle = <0x1c1>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c9>;
|
|
phandle = <0x1c7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ca>;
|
|
phandle = <0x2aa>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b09000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b09000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-0";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x47>;
|
|
phandle = <0x44f>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cb>;
|
|
phandle = <0x2a3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0a000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x47>;
|
|
phandle = <0x450>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cc>;
|
|
phandle = <0x2a4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0b000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0b000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-2";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x47>;
|
|
phandle = <0x451>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cd>;
|
|
phandle = <0x2a5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0c000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-3";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x47>;
|
|
phandle = <0x452>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ce>;
|
|
phandle = <0x2a6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0d000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x47>;
|
|
phandle = <0x453>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cf>;
|
|
phandle = <0x2a7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10844000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10844000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-lpass";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x454>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d0>;
|
|
phandle = <0x21f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d20000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d20000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-ch02";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x234>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d1>;
|
|
phandle = <0x221>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d30000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d30000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-ch13";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x236>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d2>;
|
|
phandle = <0x223>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d00000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d00000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr0";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x238>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d3>;
|
|
phandle = <0x230>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d01000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d01000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr1";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x23a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d4>;
|
|
phandle = <0x231>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10830000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10830000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-video";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x24e>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d5>;
|
|
phandle = <0x20d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c60000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c60000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-mdss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x250>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d6>;
|
|
phandle = <0x21a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c08000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dl-mm";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x252>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d7>;
|
|
phandle = <0x21b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c38000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c38000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-rdpm-cx";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x254>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d8>;
|
|
phandle = <0x249>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c39000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c39000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-rdpm-mxc";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x256>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d9>;
|
|
phandle = <0x24a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c3a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c3a000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-rdpm-mxa";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x258>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1da>;
|
|
phandle = <0x24b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c3b000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c3b000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-spare";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x25a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1db>;
|
|
phandle = <0x24c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10900000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10900000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-gpu";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x20b>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1dc>;
|
|
phandle = <0x208>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10841000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10841000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-prng";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x455>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1dd>;
|
|
phandle = <0x28c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109d0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109d0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-qm";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x456>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1de>;
|
|
phandle = <0x28d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10ac0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10ac0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-trace-noc";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x61>;
|
|
phandle = <0x457>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1df>;
|
|
phandle = <0x203>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1082c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1082c000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-gcc";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x458>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e0>;
|
|
phandle = <0x28e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10840000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10840000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-tpdm-vsense";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x459>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e1>;
|
|
phandle = <0x28f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c22000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c22000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-tpdm-ipa";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x45a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e2>;
|
|
phandle = <0x290>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c28000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c28000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dlct";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x45b>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e3>;
|
|
phandle = <0x291>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c29000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c29000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ipcc";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4e>;
|
|
phandle = <0x45c>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e4>;
|
|
phandle = <0x292>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10003000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10003000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
atid = <0x41>;
|
|
coresight-name = "coresight-tpdm-dcc";
|
|
qcom,hw-enable-check;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x45d>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e5>;
|
|
phandle = <0x29a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1000f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1000f000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-spdm";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x41>;
|
|
phandle = <0x45e>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e6>;
|
|
phandle = <0x29b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d40000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d40000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddrss-llcc0";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x50>;
|
|
phandle = <0x45f>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e7>;
|
|
phandle = <0x225>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d41000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d41000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddrss-llcc1";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x50>;
|
|
phandle = <0x460>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e8>;
|
|
phandle = <0x226>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d42000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d42000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddrss-llcc2";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x50>;
|
|
phandle = <0x461>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e9>;
|
|
phandle = <0x227>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d43000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d43000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-tpdm-ddrss-llcc3";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x50>;
|
|
phandle = <0x462>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ea>;
|
|
phandle = <0x228>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c16000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c16000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-titan";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x56>;
|
|
phandle = <0x463>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1eb>;
|
|
phandle = <0x20f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10cc9000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10cc9000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-tpdm-tmess-prng";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x64>;
|
|
phandle = <0x464>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ec>;
|
|
phandle = <0x213>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10cc1000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10cc1000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-tmess0";
|
|
clocks = <0x3c>;
|
|
status = "disabled";
|
|
clock-names = "apb_pclk";
|
|
qcom,hw-enable-check;
|
|
atid = <0x64>;
|
|
phandle = <0x465>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ed>;
|
|
phandle = <0x214>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10cc0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10cc0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-tmess1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x64>;
|
|
qcom,hw-enable-check;
|
|
phandle = <0x466>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ee>;
|
|
phandle = <0x215>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10980000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10980000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-turing";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x57>;
|
|
phandle = <0x467>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ef>;
|
|
phandle = <0x23c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10981000 {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-tpdm-turing-llm";
|
|
qcom,dummy-source;
|
|
atid = <0x57>;
|
|
phandle = <0x468>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f0>;
|
|
phandle = <0x23d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10982000 {
|
|
compatible = "qcom,coresight-dummy";
|
|
atid = <0x57>;
|
|
coresight-name = "coresight-tpdm-turing-llm2";
|
|
qcom,dummy-source;
|
|
phandle = <0x469>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f1>;
|
|
phandle = <0x23e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10983000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10983000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dpm1";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x57>;
|
|
phandle = <0x46a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f2>;
|
|
phandle = <0x23f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10984000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10984000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dmp2";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x57>;
|
|
phandle = <0x46b>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f3>;
|
|
phandle = <0x240>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c21000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c21000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-tpdm-sdcc4";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4b>;
|
|
phandle = <0x46c>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f4>;
|
|
phandle = <0x25c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c23000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c23000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ufs";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4b>;
|
|
phandle = <0x46d>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f5>;
|
|
phandle = <0x25d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109c0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109c0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dl-south";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x4b>;
|
|
phandle = <0x46e>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f6>;
|
|
phandle = <0x25e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@138a0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x138a0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-silver";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x46f>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f7>;
|
|
phandle = <0x272>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@138b0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x138b0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-gold";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x470>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f8>;
|
|
phandle = <0x273>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@138c0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x138c0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-ext";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x471>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f9>;
|
|
phandle = <0x274>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@13880000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x13880000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-gold-apc";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x472>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fa>;
|
|
phandle = <0x275>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@138d0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x138d0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-apss-ubwcp";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x473>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fb>;
|
|
phandle = <0x276>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@13890000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x13890000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-apss-apc2";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x474>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fc>;
|
|
phandle = <0x277>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@13860000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x13860000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-actpm";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x475>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fd>;
|
|
phandle = <0x278>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@13861000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x13861000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-apss1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x476>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fe>;
|
|
phandle = <0x279>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@13862000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x13862000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-apss2";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x42>;
|
|
phandle = <0x477>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ff>;
|
|
phandle = <0x27a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10800000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10800000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-modem-0";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
atid = <0x43>;
|
|
phandle = <0x478>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x200>;
|
|
phandle = <0x265>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10801000 {
|
|
compatible = "qcom,coresight-dummy";
|
|
qcom,dummy-source;
|
|
coresight-name = "coresight-tpdm-modem-1";
|
|
atid = <0x43>;
|
|
phandle = <0x479>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x201>;
|
|
phandle = <0x266>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1080d000 {
|
|
compatible = "qcom,coresight-dummy";
|
|
qcom,dummy-source;
|
|
coresight-name = "coresight-tpdm-modem-rscc";
|
|
atid = <0x62>;
|
|
phandle = <0x47a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x202>;
|
|
phandle = <0x26c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
traceNoc@10ac1000 {
|
|
compatible = "arm,primecell", "qcom,coresight-traceNoc";
|
|
arm,primecell-periphid = <0xf0c00>;
|
|
reg = <0x10ac1000 0x1000>;
|
|
reg-names = "traceNoc-base";
|
|
coresight-name = "coresight-traceNoc";
|
|
atid = <0x61>;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x47b>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x203>;
|
|
phandle = <0x1df>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x204>;
|
|
phandle = <0x2d3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b33000 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-ddr_lpi";
|
|
phandle = <0x47c>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x205>;
|
|
phandle = <0x1c2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x206>;
|
|
phandle = <0x2a9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10963000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10963000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-gfx";
|
|
status = "ok";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x47d>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x207>;
|
|
phandle = <0x209>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
phandle = <0x50c>;
|
|
remote-endpoint = <0x50d>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
phandle = <0x50b>;
|
|
remote-endpoint = <0x50e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10902000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10902000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-gfx_dl";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x47e>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x208>;
|
|
phandle = <0x1dc>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x209>;
|
|
phandle = <0x207>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20a>;
|
|
source = <0x20b>;
|
|
phandle = <0x28b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20c>;
|
|
phandle = <0x297>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10832000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10832000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-video";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x47f>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20d>;
|
|
phandle = <0x1d5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20e>;
|
|
phandle = <0x219>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10c17000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10c17000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x56>;
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
coresight-name = "coresight-tpda-titan";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x480>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20f>;
|
|
phandle = <0x1eb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x210>;
|
|
phandle = <0x211>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10c14000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10c14000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-funnel-titan";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x481>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x211>;
|
|
phandle = <0x210>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x212>;
|
|
phandle = <0x21c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10cc4000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10cc4000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x64>;
|
|
qcom,cmb-elem-size = <0x00 0x40 0x01 0x20 0x02 0x40>;
|
|
coresight-name = "coresight-tpda-tmess";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x482>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x213>;
|
|
phandle = <0x1ec>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x214>;
|
|
phandle = <0x1ed>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x215>;
|
|
phandle = <0x1ee>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x216>;
|
|
phandle = <0x217>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10cc5000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10cc5000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-tmess";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x483>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x217>;
|
|
phandle = <0x216>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x218>;
|
|
phandle = <0x21d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10c0a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10c0a000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-multimedia";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x484>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x219>;
|
|
phandle = <0x20e>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21a>;
|
|
phandle = <0x1d6>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21b>;
|
|
phandle = <0x1d7>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21c>;
|
|
phandle = <0x212>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21d>;
|
|
phandle = <0x218>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21e>;
|
|
phandle = <0x248>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10846000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10846000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-lpass";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x485>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21f>;
|
|
phandle = <0x1d0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x220>;
|
|
phandle = <0x27f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10d22000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10d22000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ddr_ch02";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x486>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x221>;
|
|
phandle = <0x1d1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x222>;
|
|
phandle = <0x22e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10d32000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10d32000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ddr_ch13";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x487>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x223>;
|
|
phandle = <0x1d2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x224>;
|
|
phandle = <0x22f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10d09000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
qcom,tpda-atid = <0x50>;
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>;
|
|
reg = <0x10d09000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-ddr";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x488>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x225>;
|
|
phandle = <0x1e7>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x226>;
|
|
phandle = <0x1e8>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x227>;
|
|
phandle = <0x1e9>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x228>;
|
|
phandle = <0x1ea>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x229>;
|
|
phandle = <0x22b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gladiator {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-gladiator";
|
|
qcom,dummy-source;
|
|
atid = <0x60>;
|
|
phandle = <0x489>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22a>;
|
|
phandle = <0x22c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10d0a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10d0a000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ddr_dl1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48a>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22b>;
|
|
phandle = <0x229>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22c>;
|
|
phandle = <0x22a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22d>;
|
|
phandle = <0x232>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10d03000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10d03000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ddr_dl0";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48b>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22e>;
|
|
phandle = <0x222>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22f>;
|
|
phandle = <0x224>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x230>;
|
|
phandle = <0x1d3>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x231>;
|
|
phandle = <0x1d4>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x232>;
|
|
phandle = <0x22d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x233>;
|
|
source = <0x234>;
|
|
phandle = <0x280>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x235>;
|
|
source = <0x236>;
|
|
phandle = <0x281>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x237>;
|
|
source = <0x238>;
|
|
phandle = <0x282>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x239>;
|
|
source = <0x23a>;
|
|
phandle = <0x283>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23b>;
|
|
phandle = <0x295>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10986000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10986000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x57>;
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
qcom,cmb-elem-size = <0x01 0x20 0x02 0x20 0x03 0x40 0x04 0x40>;
|
|
coresight-name = "coresight-tpda-turing";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48c>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23c>;
|
|
phandle = <0x1ef>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23d>;
|
|
phandle = <0x1f0>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23e>;
|
|
phandle = <0x1f1>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23f>;
|
|
phandle = <0x1f2>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x240>;
|
|
phandle = <0x1f3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x241>;
|
|
phandle = <0x245>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
turing_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-turing-etm0";
|
|
qcom,inst-id = <0x0d>;
|
|
atid = <0x26 0x27>;
|
|
phandle = <0x48d>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x242>;
|
|
phandle = <0x243>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10940000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10940000 0x1000 0x10987000 0x1000>;
|
|
reg-names = "funnel-base-dummy", "funnel-base-real";
|
|
coresight-name = "coresight-funnel-turing_dup";
|
|
qcom,duplicate-funnel;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48e>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@4 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x243>;
|
|
phandle = <0x242>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x244>;
|
|
phandle = <0x246>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10987000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10987000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-turing";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48f>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x245>;
|
|
phandle = <0x241>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x246>;
|
|
phandle = <0x244>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x247>;
|
|
phandle = <0x298>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10c3c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10c3c000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dl_west";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x490>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x248>;
|
|
phandle = <0x21e>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x249>;
|
|
phandle = <0x1d8>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24a>;
|
|
phandle = <0x1d9>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24b>;
|
|
phandle = <0x1da>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24c>;
|
|
phandle = <0x1db>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24d>;
|
|
source = <0x24e>;
|
|
phandle = <0x284>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24f>;
|
|
source = <0x250>;
|
|
phandle = <0x285>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x251>;
|
|
source = <0x252>;
|
|
phandle = <0x286>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x253>;
|
|
source = <0x254>;
|
|
phandle = <0x287>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x255>;
|
|
source = <0x256>;
|
|
phandle = <0x288>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x257>;
|
|
source = <0x258>;
|
|
phandle = <0x289>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x259>;
|
|
source = <0x25a>;
|
|
phandle = <0x28a>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25b>;
|
|
phandle = <0x296>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@109c1000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x109c1000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x4b>;
|
|
qcom,dsb-elem-size = <0x04 0x20>;
|
|
qcom,cmb-elem-size = <0x01 0x20 0x02 0x20>;
|
|
coresight-name = "coresight-tpda-dl_south";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x491>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25c>;
|
|
phandle = <0x1f4>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25d>;
|
|
phandle = <0x1f5>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25e>;
|
|
phandle = <0x1f6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25f>;
|
|
phandle = <0x260>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@109c2000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x109c2000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dl_south";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x492>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x260>;
|
|
phandle = <0x25f>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x261>;
|
|
phandle = <0x2d2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-modem-etm0";
|
|
qcom,inst-id = <0x02>;
|
|
qcom,secure-component;
|
|
atid = <0x24 0x25>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x262>;
|
|
phandle = <0x268>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem2_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-modem2-etm0";
|
|
qcom,inst-id = <0x0b>;
|
|
atid = <0x27>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x263>;
|
|
phandle = <0x26f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem_diag {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-modem-diag";
|
|
qcom,dummy-source;
|
|
atid = <0x32>;
|
|
phandle = <0x493>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x264>;
|
|
phandle = <0x26b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10803000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10803000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x43>;
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
coresight-name = "coresight-tpda-modem";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x494>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x265>;
|
|
phandle = <0x200>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x266>;
|
|
phandle = <0x201>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x267>;
|
|
phandle = <0x26e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@1080d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x1080d000 0x1000 0x1080c000 0x1000>;
|
|
reg-names = "funnel-base-dummy", "funnel-base-real";
|
|
coresight-name = "coresight-funnel-modem_q6_dup";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
qcom,duplicate-funnel;
|
|
phandle = <0x495>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x268>;
|
|
phandle = <0x262>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x269>;
|
|
phandle = <0x26a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@1080c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x1080c000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-modem_q6";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x496>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x26a>;
|
|
phandle = <0x269>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x26b>;
|
|
phandle = <0x264>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x26c>;
|
|
phandle = <0x202>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x26d>;
|
|
phandle = <0x270>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10804000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10804000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-modem_dl";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x497>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x26e>;
|
|
phandle = <0x267>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x26f>;
|
|
phandle = <0x263>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x270>;
|
|
phandle = <0x26d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x271>;
|
|
phandle = <0x2d5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@13864000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x13864000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x42>;
|
|
qcom,dsb-elem-size = <0x02 0x20 0x04 0x20 0x05 0x20 0x08 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x03 0x20 0x06 0x40 0x07 0x40>;
|
|
coresight-name = "coresight-tpda-apss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x498>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x272>;
|
|
phandle = <0x1f7>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x273>;
|
|
phandle = <0x1f8>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x274>;
|
|
phandle = <0x1f9>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x275>;
|
|
phandle = <0x1fa>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x276>;
|
|
phandle = <0x1fb>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x277>;
|
|
phandle = <0x1fc>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x278>;
|
|
phandle = <0x1fd>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x279>;
|
|
phandle = <0x1fe>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <0x08>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x27a>;
|
|
phandle = <0x1ff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x27b>;
|
|
phandle = <0x27c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@13810000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x13810000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-apss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x499>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x27c>;
|
|
phandle = <0x27b>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x27d>;
|
|
phandle = <0x2c8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x27e>;
|
|
phandle = <0x2d4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10c2c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10c2c000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x4e>;
|
|
qcom,dsb-elem-size = <0x00 0x20 0x04 0x20 0x05 0x20 0x06 0x20 0x08 0x20 0x0b 0x20 0x16 0x20 0x17 0x20 0x1d 0x20>;
|
|
qcom,cmb-elem-size = <0x07 0x40 0x09 0x20 0x0d 0x40 0x0e 0x40 0x0f 0x40 0x10 0x40 0x15 0x40 0x18 0x20 0x1a 0x40 0x1e 0x40>;
|
|
coresight-name = "coresight-tpda-dl_center";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49a>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x27f>;
|
|
phandle = <0x220>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x280>;
|
|
phandle = <0x233>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x281>;
|
|
phandle = <0x235>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x282>;
|
|
phandle = <0x237>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x283>;
|
|
phandle = <0x239>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <0x08>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x284>;
|
|
phandle = <0x24d>;
|
|
};
|
|
};
|
|
|
|
port@9 {
|
|
reg = <0x09>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x285>;
|
|
phandle = <0x24f>;
|
|
};
|
|
};
|
|
|
|
port@11 {
|
|
reg = <0x0b>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x286>;
|
|
phandle = <0x251>;
|
|
};
|
|
};
|
|
|
|
port@13 {
|
|
reg = <0x0d>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x287>;
|
|
phandle = <0x253>;
|
|
};
|
|
};
|
|
|
|
port@14 {
|
|
reg = <0x0e>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x288>;
|
|
phandle = <0x255>;
|
|
};
|
|
};
|
|
|
|
port@15 {
|
|
reg = <0x0f>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x289>;
|
|
phandle = <0x257>;
|
|
};
|
|
};
|
|
|
|
port@16 {
|
|
reg = <0x10>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x28a>;
|
|
phandle = <0x259>;
|
|
};
|
|
};
|
|
|
|
port@19 {
|
|
reg = <0x13>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x28b>;
|
|
phandle = <0x20a>;
|
|
};
|
|
};
|
|
|
|
port@21 {
|
|
reg = <0x15>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x28c>;
|
|
phandle = <0x1dd>;
|
|
};
|
|
};
|
|
|
|
port@22 {
|
|
reg = <0x16>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x28d>;
|
|
phandle = <0x1de>;
|
|
};
|
|
};
|
|
|
|
port@23 {
|
|
reg = <0x17>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x28e>;
|
|
phandle = <0x1e0>;
|
|
};
|
|
};
|
|
|
|
port@24 {
|
|
reg = <0x18>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x28f>;
|
|
phandle = <0x1e1>;
|
|
};
|
|
};
|
|
|
|
port@26 {
|
|
reg = <0x1a>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x290>;
|
|
phandle = <0x1e2>;
|
|
};
|
|
};
|
|
|
|
port@29 {
|
|
reg = <0x1d>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x291>;
|
|
phandle = <0x1e3>;
|
|
};
|
|
};
|
|
|
|
port@30 {
|
|
reg = <0x1e>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x292>;
|
|
phandle = <0x1e4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x293>;
|
|
phandle = <0x294>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10c2d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10c2d000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dl_center";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49b>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x294>;
|
|
phandle = <0x293>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x295>;
|
|
phandle = <0x23b>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x296>;
|
|
phandle = <0x25b>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x297>;
|
|
phandle = <0x20c>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x298>;
|
|
phandle = <0x247>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x299>;
|
|
phandle = <0x2d1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10004000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10004000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x41>;
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20>;
|
|
coresight-name = "coresight-tpda-qdss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49c>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x29a>;
|
|
phandle = <0x1e5>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x29b>;
|
|
phandle = <0x1e6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x29c>;
|
|
phandle = <0x29d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10041000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10041000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-in0";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49d>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x29d>;
|
|
phandle = <0x29c>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x29e>;
|
|
phandle = <0x1c0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x29f>;
|
|
phandle = <0x2a0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10045000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10045000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-qdss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49e>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a0>;
|
|
phandle = <0x29f>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a1>;
|
|
phandle = <0x2d6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a2>;
|
|
phandle = <0x2ac>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10b08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10b08000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
qcom,tpda-atid = <0x47>;
|
|
qcom,cmb-elem-size = <0x00 0x40 0x01 0x40 0x02 0x40 0x03 0x40>;
|
|
qcom,dsb-elem-size = <0x04 0x20>;
|
|
coresight-name = "coresight-tpda-aoss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49f>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a3>;
|
|
phandle = <0x1cb>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a4>;
|
|
phandle = <0x1cc>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a5>;
|
|
phandle = <0x1cd>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a6>;
|
|
phandle = <0x1ce>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a7>;
|
|
phandle = <0x1cf>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a8>;
|
|
phandle = <0x2ab>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b04000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10b04000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-aoss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a0>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2a9>;
|
|
phandle = <0x206>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2aa>;
|
|
phandle = <0x1ca>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2ab>;
|
|
phandle = <0x2a8>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2ac>;
|
|
phandle = <0x2a2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2ad>;
|
|
phandle = <0x2ae>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@10b05000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x10b05000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a1>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2ae>;
|
|
phandle = <0x2ad>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2af>;
|
|
phandle = <0x2b0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@10b06000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x10b06000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator_swao";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a2>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b0>;
|
|
phandle = <0x2af>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b1>;
|
|
phandle = <0x2b3>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b2>;
|
|
phandle = <0x2d7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@10046000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x10046000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator_qdss";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a3>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b3>;
|
|
phandle = <0x2b1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b4>;
|
|
phandle = <0x2b5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@1004e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x1004e000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator_etr";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a4>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b5>;
|
|
phandle = <0x2b4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b6>;
|
|
phandle = <0x2be>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b7>;
|
|
phandle = <0x2b8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dummy_replicator {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-replicator-dummy";
|
|
qcom,dummy-link;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b8>;
|
|
phandle = <0x2b7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b9>;
|
|
phandle = <0x2bd>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2ba>;
|
|
phandle = <0x2bf>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc_modem {
|
|
compatible = "qcom,coresight-secure-etr";
|
|
coresight-name = "coresight-modem-etr1";
|
|
real-name = "coresight-tmc-etr1";
|
|
qdss,support-remote-etm = <0x02>;
|
|
memory-region = <0x2bb>;
|
|
qdss,buffer-size = <0x2000000>;
|
|
qcom,secure-component;
|
|
coresight-csr = <0x2bc>;
|
|
csr-atid-offset = <0x108>;
|
|
csr-irqctrl-offset = <0x70>;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a5>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2bd>;
|
|
phandle = <0x2b9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@10048000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x10048000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
qcom,iommu-dma = "bypass";
|
|
iommus = <0x4f 0x4e0 0x00 0x4f 0x4c0 0x00>;
|
|
qcom,iommu-dma-addr-pool = <0x00 0xffc00000>;
|
|
qcom,sw-usb;
|
|
dma-coherent;
|
|
coresight-name = "coresight-tmc-etr";
|
|
coresight-csr = <0x2bc>;
|
|
csr-atid-offset = <0xf8>;
|
|
csr-irqctrl-offset = <0x6c>;
|
|
byte-cntr-name = "byte-cntr";
|
|
byte-cntr-class-name = "coresight-tmc-etr-stream";
|
|
interrupts = <0x00 0x10e 0x01>;
|
|
interrupt-names = "byte-cntr-irq";
|
|
arm,scatter-gather;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a6>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2be>;
|
|
phandle = <0x2b6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@1004f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x1004f000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etr1";
|
|
iommus = <0x4f 0x500 0x00>;
|
|
qcom,iommu-dma-addr-pool = <0x00 0xffc00000>;
|
|
coresight-csr = <0x2bc>;
|
|
csr-atid-offset = <0x108>;
|
|
csr-irqctrl-offset = <0x70>;
|
|
byte-cntr-name = "byte-cntr1";
|
|
byte-cntr-class-name = "coresight-tmc-etr1-stream";
|
|
interrupts = <0x00 0x10d 0x01>;
|
|
interrupt-names = "byte-cntr-irq";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a7>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2bf>;
|
|
phandle = <0x2ba>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
csr@10001000 {
|
|
compatible = "qcom,coresight-csr";
|
|
reg = <0x10001000 0x1000>;
|
|
reg-names = "csr-base";
|
|
coresight-name = "coresight-csr";
|
|
qcom,hwctrl-set-support;
|
|
qcom,set-byte-cntr-support;
|
|
qcom,blk-size = <0x01>;
|
|
phandle = <0x2bc>;
|
|
};
|
|
|
|
csr@10b11000 {
|
|
compatible = "qcom,coresight-csr";
|
|
reg = <0x10b11000 0x1000 0x10b110f8 0x70>;
|
|
reg-names = "csr-base", "msr-base";
|
|
coresight-name = "coresight-swao-csr";
|
|
qcom,timestamp-support;
|
|
qcom,msr-support;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
qcom,blk-size = <0x01>;
|
|
phandle = <0x4a8>;
|
|
};
|
|
|
|
ete0 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x19>;
|
|
coresight-name = "coresight-ete0";
|
|
qcom,skip-power-up;
|
|
atid = <0x01>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c0>;
|
|
phandle = <0x2c9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete1 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x1a>;
|
|
coresight-name = "coresight-ete1";
|
|
qcom,skip-power-up;
|
|
atid = <0x02>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c1>;
|
|
phandle = <0x2ca>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete2 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x1b>;
|
|
coresight-name = "coresight-ete2";
|
|
qcom,skip-power-up;
|
|
atid = <0x03>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c2>;
|
|
phandle = <0x2cb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete3 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x1c>;
|
|
coresight-name = "coresight-ete3";
|
|
qcom,skip-power-up;
|
|
atid = <0x04>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c3>;
|
|
phandle = <0x2cc>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete4 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x1d>;
|
|
coresight-name = "coresight-ete4";
|
|
qcom,skip-power-up;
|
|
atid = <0x05>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c4>;
|
|
phandle = <0x2cd>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete5 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x1e>;
|
|
coresight-name = "coresight-ete5";
|
|
qcom,skip-power-up;
|
|
atid = <0x06>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c5>;
|
|
phandle = <0x2ce>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete6 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x1f>;
|
|
coresight-name = "coresight-ete6";
|
|
qcom,skip-power-up;
|
|
atid = <0x07>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c6>;
|
|
phandle = <0x2cf>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete7 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <0x20>;
|
|
coresight-name = "coresight-ete7";
|
|
qcom,skip-power-up;
|
|
atid = <0x08>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c7>;
|
|
phandle = <0x2d0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel_ete {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-ete";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c8>;
|
|
phandle = <0x27d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2c9>;
|
|
phandle = <0x2c0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2ca>;
|
|
phandle = <0x2c1>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2cb>;
|
|
phandle = <0x2c2>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2cc>;
|
|
phandle = <0x2c3>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2cd>;
|
|
phandle = <0x2c4>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2ce>;
|
|
phandle = <0x2c5>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2cf>;
|
|
phandle = <0x2c6>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d0>;
|
|
phandle = <0x2c7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10042000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10042000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-in1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4a9>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d1>;
|
|
phandle = <0x299>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d2>;
|
|
phandle = <0x261>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d3>;
|
|
phandle = <0x204>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d4>;
|
|
phandle = <0x27e>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d5>;
|
|
phandle = <0x271>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d6>;
|
|
phandle = <0x2a1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dummy_sink {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-eud";
|
|
qcom,dummy-sink;
|
|
phandle = <0x4aa>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d7>;
|
|
phandle = <0x2b2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
cti@10010000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10010000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-qdss_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
qcom,cti-gpio-trigout = <0x10>;
|
|
pinctrl-names = "cti-trigout-pctrl";
|
|
pinctrl-0 = <0x2d8>;
|
|
phandle = <0x4ab>;
|
|
};
|
|
|
|
cti@10c2a000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10c2a000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-cti0";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ac>;
|
|
};
|
|
|
|
cti@10c09000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10c09000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-dlmm_cti0";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ad>;
|
|
};
|
|
|
|
cti@10d02000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d02000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_dl_0_cti_0";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ae>;
|
|
};
|
|
|
|
cti@10d08000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d08000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_dl_1_cti_0";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4af>;
|
|
};
|
|
|
|
cti@10d21000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d21000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_ch02_dl_cti_0";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b0>;
|
|
};
|
|
|
|
cti@10d31000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d31000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_ch13_dl_cti_0";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b1>;
|
|
};
|
|
|
|
cti@10d11000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d11000 0x1000>;
|
|
status = "disabled";
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddrss_shrm2";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b2>;
|
|
};
|
|
|
|
cti@10b31000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b31000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_dl2_lpi";
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b3>;
|
|
};
|
|
|
|
cti@10845000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10845000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_dl_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b4>;
|
|
};
|
|
|
|
cti@10b41000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b41000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_lpi_cti1";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b5>;
|
|
};
|
|
|
|
cti@10b51000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b51000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_lpi_cti3";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b6>;
|
|
};
|
|
|
|
cti@10b42000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b42000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_ssc_sdc";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b7>;
|
|
};
|
|
|
|
cti@10b4b000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b4b000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_q6_cti";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b8>;
|
|
};
|
|
|
|
cti@12010000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12010000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe0";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4b9>;
|
|
};
|
|
|
|
cti@12020000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12020000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ba>;
|
|
};
|
|
|
|
cti@12030000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12030000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe2";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4bb>;
|
|
};
|
|
|
|
cti@12040000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12040000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe3";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4bc>;
|
|
};
|
|
|
|
cti@12050000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12050000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe4";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4bd>;
|
|
};
|
|
|
|
cti@12060000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12060000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe5";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4be>;
|
|
};
|
|
|
|
cti@12070000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12070000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe6";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4bf>;
|
|
};
|
|
|
|
cti@12080000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12080000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_pe7";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c0>;
|
|
};
|
|
|
|
cti@12230000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12230000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_cluster";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c1>;
|
|
};
|
|
|
|
cti@138e0000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x138e0000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_cti0";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c2>;
|
|
};
|
|
|
|
cti@138f0000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x138f0000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_cti1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c3>;
|
|
};
|
|
|
|
cti@13900000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x13900000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_cti2";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c4>;
|
|
};
|
|
|
|
cti@1382b000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x1382b000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-riscv_cti";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c5>;
|
|
};
|
|
|
|
cti@1382e000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x1382e000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-riscv_sifive_cti";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c6>;
|
|
};
|
|
|
|
cti@13863000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x13863000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_atb_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c7>;
|
|
};
|
|
|
|
cti@10961000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10961000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-gpu_isdb_cti";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c8>;
|
|
};
|
|
|
|
cti@10962000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10962000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-gpu_cortex_m3";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c9>;
|
|
};
|
|
|
|
cti@10901000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10901000 0x1000>;
|
|
status = "disabled";
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-gpu_dl";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ca>;
|
|
};
|
|
|
|
cti@10831000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10831000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-iris_dl_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4cb>;
|
|
};
|
|
|
|
cti@10c61000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10c61000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-mdss_dl_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4cc>;
|
|
};
|
|
|
|
cti@10985000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10985000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-turing_dl_cti_0";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4cd>;
|
|
};
|
|
|
|
cti@1098b000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x1098b000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-turing_q6_cti";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ce>;
|
|
};
|
|
|
|
cti@10c15000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10c15000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-camera_dl";
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4cf>;
|
|
};
|
|
|
|
cti@10b00000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b00000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-swao_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d0>;
|
|
};
|
|
|
|
cti@10b21000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b21000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-aop_rvss";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d1>;
|
|
};
|
|
|
|
cti@1080b000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x1080b000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-mss_q6_cti";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d2>;
|
|
};
|
|
|
|
cti@10813000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10813000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-mss_vq6_cti";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d3>;
|
|
};
|
|
|
|
cti@10802000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10802000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-modem_tp_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d4>;
|
|
};
|
|
|
|
cti@10cc2000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10cc2000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-tmess_cti_3";
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d5>;
|
|
};
|
|
|
|
cti@10cc3000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10cc3000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-tmess_cti_4";
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d6>;
|
|
};
|
|
|
|
cti@10cd1000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10cd1000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-tmess_cpu";
|
|
status = "disabled";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d7>;
|
|
};
|
|
|
|
tgu@10b0e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb999>;
|
|
reg = <0x10b0e000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
tgu-steps = <0x03>;
|
|
tgu-conditions = <0x04>;
|
|
tgu-regs = <0x04>;
|
|
tgu-timer-counters = <0x08>;
|
|
coresight-name = "coresight-tgu-ipcb";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d8>;
|
|
};
|
|
|
|
tgu@10b0f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb999>;
|
|
reg = <0x10b0f000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
tgu-steps = <0x03>;
|
|
tgu-conditions = <0x04>;
|
|
tgu-regs = <0x09>;
|
|
tgu-timer-counters = <0x08>;
|
|
coresight-name = "coresight-tgu-spmi0";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d9>;
|
|
};
|
|
|
|
tgu@10b10000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb999>;
|
|
reg = <0x10b10000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
tgu-steps = <0x03>;
|
|
tgu-conditions = <0x04>;
|
|
tgu-regs = <0x09>;
|
|
tgu-timer-counters = <0x08>;
|
|
coresight-name = "coresight-tgu-spmi1";
|
|
clocks = <0x3c>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4da>;
|
|
};
|
|
|
|
qcom,pcie@1c00000 {
|
|
compatible = "qcom,pci-msm";
|
|
reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000 0x1d07000 0x7000>;
|
|
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "pcie_sm";
|
|
cell-index = <0x00>;
|
|
linux,pci-domain = <0x00>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>;
|
|
interrupts = <0x00 0x8c 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04>;
|
|
interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d";
|
|
msi-map = <0x00 0x58 0x1400 0x01 0x100 0x58 0x1401 0x01>;
|
|
qcom,pcie-clkreq-gpio = <0x5f>;
|
|
perst-gpio = <0xc1 0x5e 0x00>;
|
|
wake-gpio = <0xc1 0x60 0x00>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x2d9 0x2da 0x2db>;
|
|
pinctrl-1 = <0x2d9 0x2dc 0x2db>;
|
|
qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x100 0x100 0x5f5e100>;
|
|
interconnect-names = "icc_path";
|
|
interconnects = <0xf4 0x138b 0x3e 0x1588>;
|
|
gdsc-phy-vdd-supply = <0x2dd>;
|
|
clocks = <0x2c 0x0b>;
|
|
clock-names = "gcc_cnoc_pcie_sf_axi_clk";
|
|
clock-frequency = <0x00>;
|
|
clock-suppressible = <0x01>;
|
|
resets = <0x2c 0x03 0x2c 0x06>;
|
|
reset-names = "pcie_0_core_reset", "pcie_0_phy_reset";
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1400>;
|
|
iommu-map = <0x00 0x4f 0x1400 0x01 0x100 0x4f 0x1401 0x01>;
|
|
qcom,boot-option = <0x01>;
|
|
qcom,aux-clk-freq = <0x14>;
|
|
qcom,drv-supported;
|
|
qcom,drv-l1ss-timeout-us = <0x1388>;
|
|
qcom,l1-2-th-scale = <0x02>;
|
|
qcom,l1-2-th-value = <0x96>;
|
|
qcom,slv-addr-space-size = <0x4000000>;
|
|
qcom,ep-latency = <0x0a>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
qcom,config-recovery;
|
|
qcom,pcie-phy-ver = <0x6b>;
|
|
qcom,phy-status-offset = <0x214>;
|
|
qcom,phy-status-bit = <0x06>;
|
|
qcom,phy-power-down-offset = <0x240>;
|
|
qcom,phy-sequence = <0x240 0x03 0x00 0xc0 0x01 0x00 0xcc 0x62 0x00 0xd0 0x02 0x00 0x60 0xf8 0x00 0x64 0x01 0x00 0x00 0x93 0x00 0x04 0x01 0x00 0xe0 0x90 0x00 0xe4 0x82 0x00 0xf4 0x07 0x00 0x70 0x02 0x00 0x10 0x02 0x00 0x74 0x16 0x00 0x14 0x16 0x00 0x78 0x36 0x00 0x18 0x36 0x00 0x110 0x08 0x00 0xbc 0x0a 0x00 0x120 0x42 0x00 0x80 0x04 0x00 0x84 0x0d 0x00 0x20 0x0a 0x00 0x24 0x1a 0x00 0x88 0x41 0x00 0x28 0x34 0x00 0x90 0xab 0x00 0x94 0xaa 0x00 0x98 0x01 0x00 0x30 0x55 0x00 0x34 0x55 0x00 0x38 0x01 0x00 0x140 0x14 0x00 0x164 0x34 0x00 0x3c 0x01 0x00 0x1c 0x04 0x00 0x174 0x16 0x00 0x1bc 0x0f 0x00 0x170 0xa0 0x00 0x11a4 0x38 0x00 0x10dc 0x11 0x00 0x1160 0xbf 0x00 0x1164 0xbf 0x00 0x1168 0xb7 0x00 0x116c 0xea 0x00 0x115c 0x3f 0x00 0x1174 0x5c 0x00 0x1178 0x9c 0x00 0x117c 0x1a 0x00 0x1180 0x89 0x00 0x1170 0xdc 0x00 0x1188 0x94 0x00 0x118c 0x5b 0x00 0x1190 0x1a 0x00 0x1194 0x89 0x00 0x10cc 0x00 0x00 0x1008 0x09 0x00 0x1014 0x05 0x00 0x104c 0x08 0x00 0x1050 0x08 0x00 0x10d8 0x0f 0x00 0x1118 0x1c 0x00 0x10f8 0x07 0x00 0x11f8 0x08 0x00 0x1600 0x00 0x00 0xe84 0x15 0x00 0xe90 0x3f 0x00 0xee4 0x02 0x00 0xe40 0x09 0x00 0xe3c 0x15 0x00 0x19a4 0x38 0x00 0x18dc 0x11 0x00 0x1960 0xbf 0x00 0x1964 0xbf 0x00 0x1968 0xb7 0x00 0x196c 0xea 0x00 0x195c 0x3f 0x00 0x1974 0x5c 0x00 0x1978 0x9c 0x00 0x197c 0x1a 0x00 0x1980 0x89 0x00 0x1970 0xdc 0x00 0x1988 0x94 0x00 0x198c 0x5b 0x00 0x1990 0x1a 0x00 0x1994 0x89 0x00 0x18cc 0x00 0x00 0x1808 0x09 0x00 0x1814 0x05 0x00 0x184c 0x08 0x00 0x1850 0x08 0x00 0x18d8 0x0f 0x00 0x1918 0x1c 0x00 0x18f8 0x07 0x00 0x19f8 0x08 0x00 0x1684 0x15 0x00 0x1690 0x3f 0x00 0x16e4 0x02 0x00 0x1640 0x09 0x00 0x163c 0x15 0x00 0x2dc 0x05 0x00 0x388 0x77 0x00 0x398 0x0b 0x00 0x6a4 0x1e 0x00 0x6f4 0x27 0x00 0x3e0 0x0f 0x00 0x60c 0x1d 0x00 0x614 0x07 0x00 0x620 0xc1 0x00 0x694 0x00 0x00 0x3d0 0x8c 0x00 0x368 0x17 0x00 0x370 0x2e 0x00 0x200 0x00 0x00 0x244 0x03 0x00>;
|
|
qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>;
|
|
qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>;
|
|
qcom,phy-debug-reg = <0x1cc 0x1d0 0x1d4 0x1d8 0x1dc 0x1e0 0x1e4 0x1f8 0xed0 0x16d0 0xedc 0x16dc 0x11e0 0x19e0 0xa00 0x1200 0xa04 0x1204 0xa08 0x1208 0xa0c 0x120c 0xa10 0x1210 0xa14 0x1214 0xa18 0x1218 0xc20 0x1420 0x214 0x218 0x21c 0x220 0x224 0x228 0x22c 0x230 0x234 0x238 0x23c 0x600 0x604>;
|
|
qcom,pcie-sm-branch-offset = <0x1000>;
|
|
qcom,pcie-sm-start-offset = <0x1090>;
|
|
qcom,pcie-sm-seq = <0x1c018081 0x70074002 0x50028000 0x28007003 0x80804002 0x70021c01 0x18001802 0x70005000 0x10004000 0x80814002 0x18001c01 0x1c018080 0x100>;
|
|
qcom,pcie-sm-branch-seq = <0x04 0x1c 0x24 0x2c 0x00 0x00 0x00>;
|
|
qcom,pcie-sm-debug = <0x1040 0x1048 0x1050 0x1058 0x1060 0x1068 0x1070 0x1078 0x1080 0x1088 0x1090 0x1094 0x1098 0x109c>;
|
|
phandle = <0x4db>;
|
|
|
|
pcie0_rp {
|
|
reg = <0x00 0x00 0x00 0x00 0x00>;
|
|
phandle = <0x4dc>;
|
|
};
|
|
};
|
|
|
|
qcom,pcie0_msi@0x17110040 {
|
|
compatible = "qcom,pci-msi";
|
|
msi-controller;
|
|
reg = <0x17110040 0x00>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x4dd>;
|
|
};
|
|
|
|
qcom,pcie@1c08000 {
|
|
compatible = "qcom,pci-msm";
|
|
reg = <0x1c08000 0x3000 0x1c0e000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000>;
|
|
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
|
|
cell-index = <0x01>;
|
|
linux,pci-domain = <0x01>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>;
|
|
interrupts = <0x00 0x132 0x04 0x00 0x1b2 0x04 0x00 0x1b3 0x04 0x00 0x1b6 0x04 0x00 0x1b7 0x04>;
|
|
interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d";
|
|
msi-map = <0x00 0x58 0x1480 0x01 0x100 0x58 0x1481 0x01>;
|
|
perst-gpio = <0xc1 0x61 0x00>;
|
|
wake-gpio = <0xc1 0x63 0x00>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x2de 0x2df 0x2e0>;
|
|
pinctrl-1 = <0x2de 0x2e1 0x2e0>;
|
|
gdsc-core-vdd-supply = <0x2e2>;
|
|
gdsc-phy-vdd-supply = <0x2e3>;
|
|
vreg-1p2-supply = <0x37>;
|
|
vreg-0p9-supply = <0x2e4>;
|
|
vreg-qref-supply = <0x36>;
|
|
vreg-cx-supply = <0x30>;
|
|
vreg-mx-supply = <0x33>;
|
|
qcom,vreg-1p2-voltage-level = <0x124f80 0x124f80 0x65f4>;
|
|
qcom,vreg-0p9-voltage-level = <0xdea80 0xd6d80 0x2f1e8>;
|
|
qcom,vreg-cx-voltage-level = <0xffff 0x100 0x00>;
|
|
qcom,vreg-mx-voltage-level = <0xffff 0x100 0x00>;
|
|
qcom,vreg-qref-voltage-level = <0xd6d80 0xd6d80 0x6464>;
|
|
qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x40 0x40 0x5f5e100 0x100 0x100 0x5f5e100>;
|
|
interconnect-names = "icc_path";
|
|
interconnects = <0xf4 0x30 0x3e 0x200>;
|
|
clocks = <0x2c 0x39 0x2d 0x00 0x2c 0x31 0x2c 0x33 0x2c 0x34 0x2c 0x3b 0x53 0x01 0x2c 0x3c 0x2c 0x37 0x2c 0x0f 0x2c 0x00 0x2c 0x0b 0x2c 0x3a 0x46 0x2c 0x35>;
|
|
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_clkref_en", "pcie_slv_q2a_axi_clk", "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
|
|
clock-frequency = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
clock-suppressible = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00>;
|
|
resets = <0x2c 0x08 0x2c 0x0b 0x2c 0x09 0x2c 0x0a>;
|
|
reset-names = "pcie_1_core_reset", "pcie_1_phy_reset", "pcie_1_link_down_reset", "pcie_1_phy_nocsr_com_phy_reset";
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1480>;
|
|
iommu-map = <0x00 0x4f 0x1480 0x01 0x100 0x4f 0x1481 0x01>;
|
|
qcom,boot-option = <0x01>;
|
|
qcom,aux-clk-freq = <0x11>;
|
|
qcom,drv-name = "lpass";
|
|
qcom,drv-l1ss-timeout-us = <0x1388>;
|
|
qcom,eq-fmdc-t-min-phase23 = <0x01>;
|
|
qcom,slv-addr-space-size = <0x20000000>;
|
|
qcom,ep-latency = <0x0a>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
qcom,l1-2-th-scale = <0x02>;
|
|
qcom,l1-2-th-value = <0x96>;
|
|
qcom,pcie-clkreq-offset = <0x2c48>;
|
|
qcom,pcie-phy-ver = <0x6d>;
|
|
qcom,phy-status-offset = <0x1214>;
|
|
qcom,phy-status-bit = <0x07>;
|
|
qcom,phy-power-down-offset = <0x1240>;
|
|
qcom,phy-sequence = <0x1240 0x03 0x00 0x30 0x1d 0x00 0x34 0x03 0x00 0x78 0x01 0x00 0x7c 0x00 0x00 0x80 0x51 0x00 0xac 0x34 0x00 0x208 0x0c 0x00 0x20c 0x0a 0x00 0x218 0x04 0x00 0x220 0x16 0x00 0x234 0x00 0x00 0x29c 0x80 0x00 0x2a0 0x7c 0x00 0x2b4 0x05 0x00 0x2d4 0x10 0x00 0x2e8 0x0a 0x00 0x30c 0x0d 0x00 0x320 0x0b 0x00 0x348 0x1c 0x00 0x388 0x20 0x00 0x394 0x30 0x00 0x3dc 0x09 0x00 0x3f4 0x14 0x00 0x3f8 0xb3 0x00 0x3fc 0x58 0x00 0x400 0x9a 0x00 0x404 0x26 0x00 0x408 0xb6 0x00 0x40c 0xee 0x00 0x410 0xdb 0x00 0x414 0xdb 0x00 0x418 0xa0 0x00 0x41c 0xdf 0x00 0x420 0x78 0x00 0x424 0x76 0x00 0x428 0xff 0x00 0x2e0 0x00 0x00 0x830 0x1d 0x00 0x834 0x03 0x00 0x878 0x01 0x00 0x87c 0x00 0x00 0x880 0x51 0x00 0x8ac 0x34 0x00 0xa08 0x0c 0x00 0xa0c 0x0a 0x00 0xa18 0x04 0x00 0xa20 0x16 0x00 0xa34 0x00 0x00 0xa9c 0x80 0x00 0xaa0 0x7c 0x00 0xab4 0x05 0x00 0xad4 0x10 0x00 0xae8 0x0a 0x00 0xb0c 0x0d 0x00 0xb20 0x0b 0x00 0xb48 0x1c 0x00 0xb88 0x20 0x00 0xb94 0x30 0x00 0xbdc 0x09 0x00 0xbf4 0x14 0x00 0xbf8 0xb3 0x00 0xbfc 0x58 0x00 0xc00 0x9a 0x00 0xc04 0x26 0x00 0xc08 0xb6 0x00 0xc0c 0xee 0x00 0xc10 0xdb 0x00 0xc14 0xdb 0x00 0xc18 0xa0 0x00 0xc1c 0xdf 0x00 0xc20 0x78 0x00 0xc24 0x76 0x00 0xc28 0xff 0x00 0xae0 0x00 0x00 0xea0 0x01 0x00 0xeb4 0x00 0x00 0xec4 0x02 0x00 0xec8 0x0d 0x00 0xed4 0x12 0x00 0xed8 0x12 0x00 0xedc 0xdb 0x00 0xee0 0x9a 0x00 0xee4 0x38 0x00 0xee8 0xb6 0x00 0xeec 0x64 0x00 0xef0 0x1f 0x00 0xef4 0x1f 0x00 0xef8 0x1f 0x00 0xefc 0x1f 0x00 0xf00 0x1f 0x00 0xf04 0x1f 0x00 0xf0c 0x1f 0x00 0xf14 0x1f 0x00 0xf1c 0x1f 0x00 0xf28 0x5b 0x00 0x1000 0x26 0x00 0x1004 0x03 0x00 0x1010 0x06 0x00 0x1014 0x16 0x00 0x1018 0x36 0x00 0x101c 0x04 0x00 0x1020 0x0a 0x00 0x1024 0x1a 0x00 0x1028 0x68 0x00 0x1030 0xab 0x00 0x1034 0xaa 0x00 0x1038 0x02 0x00 0x103c 0x12 0x00 0x1060 0xf8 0x00 0x1064 0x01 0x00 0x1070 0x06 0x00 0x1074 0x16 0x00 0x1078 0x36 0x00 0x107c 0x0a 0x00 0x1080 0x04 0x00 0x1084 0x0d 0x00 0x1088 0x41 0x00 0x1090 0xab 0x00 0x1094 0xaa 0x00 0x1098 0x01 0x00 0x109c 0x00 0x00 0x10bc 0x0a 0x00 0x10c0 0x01 0x00 0x10cc 0x62 0x00 0x10d0 0x02 0x00 0x10d8 0x40 0x00 0x10dc 0x14 0x00 0x10e0 0x90 0x00 0x10e4 0x82 0x00 0x10f4 0x0f 0x00 0x1110 0x08 0x00 0x1120 0x46 0x00 0x1124 0x04 0x00 0x1140 0x14 0x00 0x1164 0x34 0x00 0x1170 0xa0 0x00 0x1174 0x06 0x00 0x1184 0x88 0x00 0x1188 0x14 0x00 0x1198 0x0f 0x00 0x1378 0x2e 0x00 0x1390 0xcc 0x00 0x13f8 0x00 0x00 0x13fc 0x22 0x00 0x141c 0xc1 0x00 0x129c 0x87 0x00 0x12a0 0x05 0x00 0x12a4 0xa1 0x00 0x1450 0x0f 0x00 0x1490 0x00 0x00 0x14a0 0x16 0x00 0x14f0 0x27 0x00 0x14f4 0x27 0x00 0x1508 0x02 0x00 0x155c 0x2e 0x00 0x157c 0x03 0x00 0x1584 0x28 0x00 0x13dc 0x04 0x00 0x13e0 0x02 0x00 0x1418 0xc0 0x00 0x140c 0x1d 0x00 0x158c 0x0f 0x00 0x15ac 0xf2 0x00 0x15c0 0xf2 0x00 0x1370 0x17 0x00 0x1200 0x00 0x00 0x1244 0x03 0x00>;
|
|
qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>;
|
|
qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>;
|
|
qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc 0x11e0 0x11e4 0x11f8 0xb8 0x8b8 0xc4 0x8c4 0x464 0xc64 0x1800 0x1c00 0x1804 0x1c04 0x1808 0x1c08 0x180c 0x1c0c 0x1810 0x1c10 0x1814 0x1c14 0x1818 0x1c18 0x1a20 0x1e20 0x1214 0x1218 0x121c 0x1220 0x1224 0x1228 0x122c 0x1230 0x1234 0x1238 0x123c 0x1400 0x1404>;
|
|
phandle = <0x4de>;
|
|
|
|
pcie1_rp {
|
|
reg = <0x00 0x00 0x00 0x00 0x00>;
|
|
phandle = <0x4df>;
|
|
};
|
|
};
|
|
|
|
qcom,pcie1_msi@0x17110040 {
|
|
status = "disabled";
|
|
compatible = "qcom,pci-msi";
|
|
msi-controller;
|
|
reg = <0x17110040 0x00>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x320 0x01 0x00 0x321 0x01 0x00 0x322 0x01 0x00 0x323 0x01 0x00 0x324 0x01 0x00 0x325 0x01 0x00 0x326 0x01 0x00 0x327 0x01 0x00 0x328 0x01 0x00 0x329 0x01 0x00 0x32a 0x01 0x00 0x32b 0x01 0x00 0x32c 0x01 0x00 0x32d 0x01 0x00 0x32e 0x01 0x00 0x32f 0x01 0x00 0x330 0x01 0x00 0x331 0x01 0x00 0x332 0x01 0x00 0x333 0x01 0x00 0x334 0x01 0x00 0x335 0x01 0x00 0x336 0x01 0x00 0x337 0x01 0x00 0x338 0x01 0x00 0x339 0x01 0x00 0x33a 0x01 0x00 0x33b 0x01 0x00 0x33c 0x01 0x00 0x33d 0x01 0x00 0x33e 0x01 0x00 0x33f 0x01 0x00 0x340 0x01 0x00 0x341 0x01 0x00 0x342 0x01 0x00 0x343 0x01 0x00 0x344 0x01 0x00 0x345 0x01 0x00 0x346 0x01 0x00 0x347 0x01 0x00 0x348 0x01 0x00 0x349 0x01 0x00 0x34a 0x01 0x00 0x34b 0x01 0x00 0x34c 0x01 0x00 0x34d 0x01 0x00 0x34e 0x01 0x00 0x34f 0x01>;
|
|
phandle = <0x4e0>;
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_2_out {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-2-out";
|
|
qcom,smem-states = <0x2e5 0x00>;
|
|
qcom,smem-state-names = "rdbg-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_2_in {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
|
|
interrupts-extended = <0x2e6 0x00 0x00>;
|
|
interrupt-names = "rdbg-smp2p-in";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_5_out {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-5-out";
|
|
qcom,smem-states = <0x2e7 0x00>;
|
|
qcom,smem-state-names = "rdbg-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_5_in {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-5-in";
|
|
interrupts-extended = <0x2e8 0x00 0x00>;
|
|
interrupt-names = "rdbg-smp2p-in";
|
|
};
|
|
|
|
tsens0@c228000 {
|
|
compatible = "qcom,tsens-v2";
|
|
reg = <0xc228000 0x1ff 0xc222000 0x1ff>;
|
|
#qcom,sensors = <0x0f>;
|
|
interrupts = <0x00 0x1fa 0x04 0x00 0x280 0x04>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
tsens1@c229000 {
|
|
compatible = "qcom,tsens-v2";
|
|
reg = <0xc229000 0x1ff 0xc223000 0x1ff>;
|
|
#qcom,sensors = <0x10>;
|
|
interrupts = <0x00 0x1fb 0x04 0x00 0x281 0x04>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x79>;
|
|
};
|
|
|
|
tsens2@c22a000 {
|
|
compatible = "qcom,tsens-v2";
|
|
reg = <0xc22a000 0x1ff 0xc224000 0x1ff>;
|
|
#qcom,sensors = <0x0d>;
|
|
interrupts = <0x00 0x1fc 0x04 0x00 0x282 0x04>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x8d>;
|
|
};
|
|
|
|
qcom,cpu-pause {
|
|
compatible = "qcom,thermal-pause";
|
|
|
|
cpu0-pause {
|
|
qcom,cpus = <0x19>;
|
|
qcom,cdev-alias = "thermal-pause-1";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x84>;
|
|
};
|
|
|
|
cpu1-pause {
|
|
qcom,cpus = <0x1a>;
|
|
qcom,cdev-alias = "thermal-pause-2";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x88>;
|
|
};
|
|
|
|
cpu2-pause {
|
|
qcom,cpus = <0x1b>;
|
|
qcom,cdev-alias = "thermal-pause-4";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x5c>;
|
|
};
|
|
|
|
cpu3-pause {
|
|
qcom,cpus = <0x1c>;
|
|
qcom,cdev-alias = "thermal-pause-8";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x62>;
|
|
};
|
|
|
|
cpu4-pause {
|
|
qcom,cpus = <0x1d>;
|
|
qcom,cdev-alias = "thermal-pause-10";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x68>;
|
|
};
|
|
|
|
cpu5-pause {
|
|
qcom,cpus = <0x1e>;
|
|
qcom,cdev-alias = "thermal-pause-20";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x6e>;
|
|
};
|
|
|
|
cpu6-pause {
|
|
qcom,cpus = <0x1f>;
|
|
qcom,cdev-alias = "thermal-pause-40";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x74>;
|
|
};
|
|
|
|
cpu7-pause {
|
|
qcom,cpus = <0x20>;
|
|
qcom,cdev-alias = "thermal-pause-80";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x7b>;
|
|
};
|
|
|
|
apc2-pause {
|
|
qcom,cpus = <0x1b 0x1c 0x1d>;
|
|
qcom,cdev-alias = "thermal-pause-1C";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e1>;
|
|
};
|
|
|
|
apc1-pause {
|
|
qcom,cpus = <0x1e 0x1f 0x20>;
|
|
qcom,cdev-alias = "thermal-pause-E0";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e2>;
|
|
};
|
|
|
|
pause-cpu0 {
|
|
qcom,cpus = <0x19>;
|
|
qcom,cdev-alias = "pause-cpu0";
|
|
};
|
|
|
|
pause-cpu1 {
|
|
qcom,cpus = <0x1a>;
|
|
qcom,cdev-alias = "pause-cpu1";
|
|
};
|
|
|
|
pause-cpu2 {
|
|
qcom,cpus = <0x1b>;
|
|
qcom,cdev-alias = "pause-cpu2";
|
|
};
|
|
|
|
pause-cpu3 {
|
|
qcom,cpus = <0x1c>;
|
|
qcom,cdev-alias = "pause-cpu3";
|
|
};
|
|
|
|
pause-cpu4 {
|
|
qcom,cpus = <0x1d>;
|
|
qcom,cdev-alias = "pause-cpu4";
|
|
};
|
|
|
|
pause-cpu5 {
|
|
qcom,cpus = <0x1e>;
|
|
qcom,cdev-alias = "pause-cpu5";
|
|
};
|
|
|
|
pause-cpu6 {
|
|
qcom,cpus = <0x1f>;
|
|
qcom,cdev-alias = "pause-cpu6";
|
|
};
|
|
|
|
pause-cpu7 {
|
|
qcom,cpus = <0x20>;
|
|
qcom,cdev-alias = "pause-cpu7";
|
|
};
|
|
};
|
|
|
|
qcom,cpu-hotplug {
|
|
compatible = "qcom,cpu-hotplug";
|
|
|
|
cpu0-hotplug {
|
|
qcom,cpu = <0x19>;
|
|
qcom,cdev-alias = "cpu-hotplug0";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x86>;
|
|
};
|
|
|
|
cpu1-hotplug {
|
|
qcom,cpu = <0x1a>;
|
|
qcom,cdev-alias = "cpu-hotplug1";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x8a>;
|
|
};
|
|
|
|
cpu2-hotplug {
|
|
qcom,cpu = <0x1b>;
|
|
qcom,cdev-alias = "cpu-hotplug2";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x5e>;
|
|
};
|
|
|
|
cpu3-hotplug {
|
|
qcom,cpu = <0x1c>;
|
|
qcom,cdev-alias = "cpu-hotplug3";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
cpu4-hotplug {
|
|
qcom,cpu = <0x1d>;
|
|
qcom,cdev-alias = "cpu-hotplug4";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x6a>;
|
|
};
|
|
|
|
cpu5-hotplug {
|
|
qcom,cpu = <0x1e>;
|
|
qcom,cdev-alias = "cpu-hotplug5";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x70>;
|
|
};
|
|
|
|
cpu6-hotplug {
|
|
qcom,cpu = <0x1f>;
|
|
qcom,cdev-alias = "cpu-hotplug6";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x76>;
|
|
};
|
|
|
|
cpu7-hotplug {
|
|
qcom,cpu = <0x20>;
|
|
qcom,cdev-alias = "cpu-hotplug7";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x7d>;
|
|
};
|
|
};
|
|
|
|
qcom,cpu-voltage-cdev {
|
|
compatible = "qcom,cc-cooling-devices";
|
|
|
|
thermal-cluster-2-3 {
|
|
qcom,cluster0 = <0x1e 0x1f>;
|
|
qcom,cluster1 = <0x20>;
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e3>;
|
|
};
|
|
};
|
|
|
|
qcom,ddr-cdev {
|
|
compatible = "qcom,ddr-cooling-device";
|
|
#cooling-cells = <0x02>;
|
|
qcom,bus-width = <0x04>;
|
|
qcom,freq-table = <0x85980 0xbb800 0x17bb00 0x1a1300 0x1fef00 0x29bf80 0x30a200 0x384000 0x407400>;
|
|
interconnects = <0x3e 0x04 0x3e 0x200>;
|
|
phandle = <0x8c>;
|
|
};
|
|
|
|
qcom,limits-dcvs {
|
|
compatible = "qcom,msm-hw-limits";
|
|
isens_vref_0p8-supply = <0x2e9>;
|
|
isens-vref-0p8-settings = <0xd6d80 0xd6d80 0x7530>;
|
|
isens_vref_1p8-supply = <0x2ea>;
|
|
isens-vref-1p8-settings = <0x124f80 0x124f80 0x1f40>;
|
|
};
|
|
|
|
qmi-tmd-devices {
|
|
compatible = "qcom,qmi-cooling-devices";
|
|
phandle = <0x4e4>;
|
|
|
|
cdsp {
|
|
qcom,instance-id = <0x43>;
|
|
|
|
cdsp {
|
|
qcom,qmi-dev-name = "cdsp_sw";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e5>;
|
|
};
|
|
|
|
cdsp_sw_hvx {
|
|
qcom,qmi-dev-name = "cdsp_sw_hvx";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e6>;
|
|
};
|
|
|
|
cdsp_sw_hmx {
|
|
qcom,qmi-dev-name = "cdsp_sw_hmx";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e7>;
|
|
};
|
|
|
|
cdsp_hw {
|
|
qcom,qmi-dev-name = "cdsp_hw";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e8>;
|
|
};
|
|
};
|
|
|
|
modem {
|
|
qcom,instance-id = <0x00>;
|
|
|
|
modem_bcl {
|
|
qcom,qmi-dev-name = "bcl";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4e9>;
|
|
};
|
|
|
|
modem_lte_dsc {
|
|
qcom,qmi-dev-name = "modem_lte_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
modem_nr_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
modem_nr_scg_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_scg_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x99>;
|
|
};
|
|
|
|
sdr0_lte_dsc {
|
|
qcom,qmi-dev-name = "sdr0_lte_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4ea>;
|
|
};
|
|
|
|
sdr0_nr_dsc {
|
|
qcom,qmi-dev-name = "sdr0_nr_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4eb>;
|
|
};
|
|
|
|
pa_lte_sdr0_dsc {
|
|
qcom,qmi-dev-name = "pa_lte_sdr0_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4ec>;
|
|
};
|
|
|
|
pa_nr_sdr0_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4ed>;
|
|
};
|
|
|
|
pa_nr_sdr0_scg_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4ee>;
|
|
};
|
|
|
|
mmw0_dsc {
|
|
qcom,qmi-dev-name = "mmw0_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4ef>;
|
|
};
|
|
|
|
mmw1_dsc {
|
|
qcom,qmi-dev-name = "mmw1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f0>;
|
|
};
|
|
|
|
mmw2_dsc {
|
|
qcom,qmi-dev-name = "mmw2_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f1>;
|
|
};
|
|
|
|
mmw3_dsc {
|
|
qcom,qmi-dev-name = "mmw3_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f2>;
|
|
};
|
|
|
|
wlan {
|
|
qcom,qmi-dev-name = "wlan";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f3>;
|
|
};
|
|
|
|
modem_bw_backoff {
|
|
qcom,qmi-dev-name = "modem_bw_backoff";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f4>;
|
|
};
|
|
|
|
modem_vdd {
|
|
qcom,qmi-dev-name = "cpuv_restriction_cold";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f5>;
|
|
};
|
|
|
|
modem_nr_scg_sub1_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f6>;
|
|
};
|
|
|
|
modem_lte_sub1_dsc {
|
|
qcom,qmi-dev-name = "modem_lte_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f7>;
|
|
};
|
|
|
|
modem_nr_sub1_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f8>;
|
|
};
|
|
|
|
pa_nr_sdr0_sub1_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4f9>;
|
|
};
|
|
|
|
pa_lte_sdr0_sub1_dsc {
|
|
qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4fa>;
|
|
};
|
|
|
|
pa_nr_sdr0_scg_sub1_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_scg_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4fb>;
|
|
};
|
|
|
|
mmw0_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw0_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4fc>;
|
|
};
|
|
|
|
mmw1_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw1_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4fd>;
|
|
};
|
|
|
|
mmw2_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw2_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4fe>;
|
|
};
|
|
|
|
mmw3_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw3_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x4ff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,userspace-cdev {
|
|
compatible = "qcom,userspace-cooling-devices";
|
|
|
|
display-fps {
|
|
qcom,max-level = <0x10>;
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x500>;
|
|
};
|
|
};
|
|
|
|
qcom,cpufreq-cdev {
|
|
compatible = "qcom,cpufreq-cdev";
|
|
|
|
cpu-cluster0 {
|
|
qcom,cpus = <0x19 0x1a>;
|
|
};
|
|
|
|
cpu-cluster1 {
|
|
qcom,cpus = <0x1b 0x1c 0x1d>;
|
|
};
|
|
|
|
cpu-cluster2 {
|
|
qcom,cpus = <0x1e 0x1f>;
|
|
};
|
|
|
|
cpu-cluster3 {
|
|
qcom,cpus = <0x20>;
|
|
};
|
|
};
|
|
|
|
qcom,devfreq-cdev {
|
|
compatible = "qcom,devfreq-cdev";
|
|
qcom,devfreq = <0x8f>;
|
|
};
|
|
|
|
limits-stat {
|
|
compatible = "qcom,limits-stat";
|
|
qcom,limits-stat-sensor-names = "aoss-0", "cpuss-0", "cpuss-1", "cpuss-2", "cpuss-3", "cpu-2-0-0", "cpu-2-0-1", "cpu-2-1-0", "cpu-2-1-1", "cpu-2-2-0", "cpu-2-2-1", "cpu-1-0-0", "cpu-1-0-1", "cpu-1-1-0", "cpu-1-1-1", "aoss-1", "cpu-1-2-0", "cpu-1-2-1", "cpu-1-2-2", "cpu-0-0-0", "cpu-0-1-0", "nsphvx-0", "nsphvx-1", "nsphmx-0", "nsphmx-1", "nsphmx-2", "nsphmx-3", "video", "ddr", "camera-0", "camera-1", "aoss-2", "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7", "mdmss-0", "mdmss-1", "mdmss-2", "mdmss-3", "pm8550b-ibat-lvl0", "vbat";
|
|
phandle = <0x501>;
|
|
};
|
|
|
|
qmi-ts-sensors {
|
|
compatible = "qcom,qmi-sensors";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x59>;
|
|
|
|
modem {
|
|
qcom,instance-id = <0x00>;
|
|
qcom,qmi-sensor-names = "modem_tsens", "modem_tsens1", "pa", "pa_1", "modem_bcl_warn", "sdr0_pa", "sdr0", "mmw0", "mmw1", "mmw2", "mmw3", "mmw_pa1", "mmw_pa2", "mmw_pa3", "mmw_ific0", "epm0", "epm1", "epm2", "epm3", "epm4", "epm5", "epm6", "epm7", "sys_therm1", "sys_therm2", "sys_therm3", "sys_therm4", "sys_therm5", "sys_therm6", "sub0_sdr0_pa", "sdr_mmw_therm", "sub1_modem_cfg", "sub1_lte_cc", "sub1_mcg_fr1_cc", "sub1_mcg_fr2_cc", "sub1_scg_fr1_cc", "sub1_scg_fr2_cc";
|
|
};
|
|
};
|
|
|
|
qcom,hw-fence {
|
|
phandle = <0x505>;
|
|
qcom,hw-fence-client-type-ife0-extra = <0x14 0x1c 0x01 0x01>;
|
|
qcom,hw-fence-client-type-ife0 = <0x01 0x01 0x80 0x01>;
|
|
qcom,hw-fence-client-type-vpu = <0x01 0x02 0x320 0x00>;
|
|
qcom,hw-fence-client-type-ipe = <0x01 0x02 0x320 0x00>;
|
|
qcom,hw-fence-client-type-dpu = <0x06 0x02 0x80 0x01>;
|
|
qcom,hw-fence-ipc-ver = <0x20003>;
|
|
qcom,qtime-reg = <0xc221000 0x1000>;
|
|
qcom,ipcc-reg = <0x400000 0x200000>;
|
|
qcom,hw-fence-queue-entries = <0x320>;
|
|
qcom,hw-fence-table-entries = <0x2000>;
|
|
status = "ok";
|
|
compatible = "qcom,msm-hw-fence";
|
|
|
|
hw_fence@0 {
|
|
peer-name = <0x03>;
|
|
gunyah-label = <0x06>;
|
|
qcom,master;
|
|
compatible = "qcom,msm-hw-fence-db";
|
|
};
|
|
|
|
hw_fence@1 {
|
|
shared-buffer = <0xc2>;
|
|
peer-name = <0x03>;
|
|
gunyah-label = <0x05>;
|
|
qcom,master;
|
|
compatible = "qcom,msm-hw-fence-mem";
|
|
};
|
|
};
|
|
|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
qcom,ipa-napi-enable;
|
|
qcom,ipa-advertise-sg-support;
|
|
qcom,ipa-platform-type-msm;
|
|
qcom,rmnet-ipa-ssr;
|
|
compatible = "qcom,rmnet-ipa3";
|
|
};
|
|
|
|
qcom,ipa_fws {
|
|
status = "disabled";
|
|
qcom,pil-force-shutdown;
|
|
qcom,firmware-name = "ipa_fws";
|
|
qcom,pas-id = <0x0f>;
|
|
compatible = "qcom,pil-tz-generic";
|
|
};
|
|
|
|
qcom,ipa@3e00000 {
|
|
phandle = <0x506>;
|
|
qcom,ipa-gen-rx-ll-pool-sz-factor = <0x01>;
|
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
|
|
qcom,turbo = <0x36ee80 0x00 0x36ee80 0x53ec60 0x00 0x61a80>;
|
|
qcom,nominal = <0x249f00 0x00 0x249f00 0x53ec60 0x00 0x61a80>;
|
|
qcom,svs = <0x124f80 0x00 0x124f80 0x2ab980 0x00 0x249f0>;
|
|
qcom,svs2 = <0x00 0x00 0x00 0x13d620 0x00 0x12c00>;
|
|
qcom,no-vote = <0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
|
interconnects = <0x3d 0x2a 0x50 0x231 0x3e 0x04 0x3e 0x200 0x50 0x03 0x307 0x214>;
|
|
qcom,ipa-wdi-opt-dpath;
|
|
qcom,interconnect,num-paths = <0x03>;
|
|
qcom,interconnect,num-cases = <0x05>;
|
|
qcom,scaling-exceptions;
|
|
qcom,throughput-threshold = <0x7d0 0xfa0 0x1f40>;
|
|
clocks = <0x2d 0x0c>;
|
|
clock-names = "core_clk";
|
|
qcom,max_num_smmu_cb = <0x04>;
|
|
qcom,ulso-ip-id-max-windows-val = <0x7fff>;
|
|
qcom,ulso-ip-id-min-windows-val = <0x00>;
|
|
qcom,ulso-ip-id-max-linux-val = <0xffff>;
|
|
qcom,ulso-ip-id-min-linux-val = <0x00>;
|
|
qcom,ulso-supported;
|
|
qcom,ipa-gpi-event-rp-ddr;
|
|
qcom,tx-wrapper-cache-max-size = <0x190>;
|
|
qcom,ipa-holb-monitor-max-cnt-11ad = <0x0a>;
|
|
qcom,ipa-holb-monitor-max-cnt-usb = <0x0a>;
|
|
qcom,ipa-holb-monitor-max-cnt-wlan = <0x0a>;
|
|
qcom,ipa-holb-monitor-poll-period = <0x05>;
|
|
qcom,ipa-uc-holb-monitor;
|
|
qcom,rmnet-ll-enable;
|
|
qcom,rmnet-ctl-enable;
|
|
qcom,wan-use-skb-page;
|
|
qcom,non-tn-collection-on-crash;
|
|
qcom,testbus-collection-on-crash;
|
|
qcom,register-collection-on-crash;
|
|
qcom,tx-poll;
|
|
qcom,tx-napi;
|
|
qcom,lan-rx-napi;
|
|
qcom,ipa-endp-delay-wa-v2;
|
|
qcom,use-64-bit-dma-mask;
|
|
qcom,smmu-fast-map;
|
|
qcom,arm-smmu;
|
|
qcom,ipa-wdi3-over-gsi;
|
|
qcom,modem-cfg-emb-pipe-flt;
|
|
qcom,mhi-event-ring-id-limits = <0x09 0x0b>;
|
|
qcom,use-ipa-tethering-bridge;
|
|
qcom,entire-ipa-block-size = <0x200000>;
|
|
qcom,ee = <0x00>;
|
|
qcom,platform-type = <0x01>;
|
|
qcom,ipa-hw-mode = <0x00>;
|
|
qcom,ipa-hw-ver = <0x18>;
|
|
interrupt-names = "ipa-irq", "gsi-irq";
|
|
interrupts = <0x00 0x28e 0x04 0x00 0x1b0 0x04>;
|
|
qcom,ipa-cfg-offset = <0x140000>;
|
|
memory-regions = <0x2f8>;
|
|
firmware-names = "ipa_fws";
|
|
pas-ids = <0x0f>;
|
|
reg-names = "ipa-base", "gsi-base";
|
|
reg = <0x3e00000 0x84000 0x3e04000 0xfc000>;
|
|
compatible = "qcom,ipa";
|
|
|
|
qcom,smp2p_map_ipa_1_out {
|
|
qcom,smem-state-names = "ipa-smp2p-out";
|
|
qcom,smem-states = <0x3ca 0x00>;
|
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
|
};
|
|
|
|
qcom,smp2p_map_ipa_1_in {
|
|
interrupt-names = "ipa-smp2p-in";
|
|
interrupts-extended = <0x3cb 0x00 0x00>;
|
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
|
};
|
|
|
|
ipa_smmu_ap {
|
|
phandle = <0x507>;
|
|
qcom,ipa-q6-smem-size = <0xb000>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,additional-mapping = <0x14683000 0x14683000 0x2000>;
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
iommus = <0x4f 0x4a0 0x00>;
|
|
compatible = "qcom,ipa-smmu-ap-cb";
|
|
};
|
|
|
|
ipa_smmu_wlan {
|
|
phandle = <0x508>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "atomic";
|
|
iommus = <0x4f 0x4a1 0x00>;
|
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
|
};
|
|
|
|
ipa_smmu_uc {
|
|
phandle = <0x509>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
iommus = <0x4f 0x4a2 0x00>;
|
|
compatible = "qcom,ipa-smmu-uc-cb";
|
|
};
|
|
|
|
ipa_smmu_11ad {
|
|
phandle = <0x50a>;
|
|
qcom,iommu-group;
|
|
qcom,shared-cb;
|
|
dma-coherent;
|
|
iommus = <0x4f 0x4a4 0x00>;
|
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
|
};
|
|
};
|
|
|
|
qcom,kgsl-iommu@3da0000 {
|
|
phandle = <0x50f>;
|
|
vddcx-supply = <0xef>;
|
|
reg = <0x3da0000 0x40000>;
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
|
|
gfx3d_user {
|
|
phandle = <0x510>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0xf5 0x00 0x00>;
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
};
|
|
|
|
gfx3d_lpac {
|
|
phandle = <0x511>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0xf5 0x01 0x00>;
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
};
|
|
|
|
gfx3d_secure {
|
|
phandle = <0x512>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0xf5 0x02 0x00>;
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
};
|
|
};
|
|
|
|
qcom,gmu@3d69000 {
|
|
phandle = <0x513>;
|
|
mbox-names = "aop";
|
|
mboxes = <0x3c9 0x00>;
|
|
qcom,ipc-core = <0x400000 0x140000>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0xf5 0x05 0x00>;
|
|
qcom,gmu-perf-ddr-bw = <0x2dc6c0>;
|
|
qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>;
|
|
clock-names = "gmu_clk", "cxo_clk", "axi_clk", "memnoc_clk", "ahb_clk", "hub_clk";
|
|
clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>;
|
|
vdd-supply = <0x406>;
|
|
vddcx-supply = <0xef>;
|
|
regulator-names = "vddcx", "vdd";
|
|
interrupt-names = "hfi", "gmu";
|
|
interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>;
|
|
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
|
|
reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>;
|
|
compatible = "qcom,gen7-gmu";
|
|
};
|
|
|
|
qcom,gpu-coresight-cx {
|
|
phandle = <0x514>;
|
|
coresight-atid = <0x34>;
|
|
coresight-name = "coresight-gfx-cx";
|
|
compatible = "qcom,gpu-coresight-cx";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
phandle = <0x50e>;
|
|
remote-endpoint = <0x50b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,gpu-coresight-gx {
|
|
phandle = <0x515>;
|
|
coresight-atid = <0x35>;
|
|
coresight-name = "coresight-gfx";
|
|
compatible = "qcom,gpu-coresight-gx";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
phandle = <0x50d>;
|
|
remote-endpoint = <0x50c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,vidc@aa00000 {
|
|
phandle = <0x516>;
|
|
reset-names = "video_axi_reset", "video_xo_reset", "video_mvs0c_reset";
|
|
resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>;
|
|
memory-region = <0x2fb>;
|
|
interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";
|
|
interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe2 0x1f 0x50 0x231>;
|
|
clock-names = "gcc_video_axi0_clk", "video_cc_mvs0c_clk", "video_cc_mvs0_clk", "video_cc_mvs0_clk_src";
|
|
clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>;
|
|
vcodec-supply = <0x408>;
|
|
iris-ctl-supply = <0xf0>;
|
|
interrupts = <0x00 0xae 0x04>;
|
|
reg = <0xaa00000 0xf0000>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
status = "okay";
|
|
compatible = "qcom,sm8650-vidc-v2";
|
|
|
|
non_secure_pixel_cb {
|
|
dma-coherent;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>;
|
|
iommus = <0x4f 0x1947 0x00>;
|
|
compatible = "qcom,vidc,cb-ns-pxl";
|
|
};
|
|
|
|
non_secure_cb {
|
|
dma-coherent;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
|
|
iommus = <0x4f 0x1940 0x00>;
|
|
compatible = "qcom,vidc,cb-ns";
|
|
};
|
|
|
|
secure_non_pixel_cb {
|
|
qcom,secure-context-bank;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-vmid = <0x0b>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>;
|
|
iommus = <0x4f 0x1944 0x00>;
|
|
compatible = "qcom,vidc,cb-sec-non-pxl";
|
|
};
|
|
|
|
secure_bitstream_cb {
|
|
qcom,secure-context-bank;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-vmid = <0x09>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>;
|
|
iommus = <0x4f 0x1941 0x04>;
|
|
compatible = "qcom,vidc,cb-sec-bitstream";
|
|
};
|
|
|
|
secure_pixel_cb {
|
|
qcom,secure-context-bank;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-vmid = <0x0a>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>;
|
|
iommus = <0x4f 0x1943 0x00>;
|
|
compatible = "qcom,vidc,cb-sec-pxl";
|
|
};
|
|
};
|
|
|
|
qcom,msm-stub-codec {
|
|
phandle = <0x519>;
|
|
compatible = "qcom,msm-stub-codec";
|
|
};
|
|
|
|
qcom,audio-pkt-core-platform {
|
|
phandle = <0x51a>;
|
|
compatible = "qcom,audio-pkt-core-platform";
|
|
};
|
|
|
|
qcom,msm-adsp-loader {
|
|
phandle = <0x51b>;
|
|
qcom,adsp-state = <0x00>;
|
|
qcom,rproc-handle = <0xa9>;
|
|
compatible = "qcom,adsp-loader";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,msm-adsp-notify {
|
|
phandle = <0x51c>;
|
|
qcom,rproc-handle = <0xa9>;
|
|
compatible = "qcom,adsp-notify";
|
|
status = "ok";
|
|
};
|
|
|
|
spf_core_platform {
|
|
phandle = <0x51d>;
|
|
compatible = "qcom,spf-core-platform";
|
|
|
|
qcom,msm-audio-ion {
|
|
phandle = <0x51e>;
|
|
dma-coherent;
|
|
qcom,smmu-sid-mask = <0x00 0x0f>;
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>;
|
|
iommus = <0x4f 0x1001 0x80 0x4f 0x1061 0x00>;
|
|
qcom,smmu-enabled;
|
|
qcom,smmu-version = <0x02>;
|
|
compatible = "qcom,msm-audio-ion";
|
|
};
|
|
|
|
qcom,msm-audio-ion-cma {
|
|
phandle = <0x51f>;
|
|
compatible = "qcom,msm-audio-ion-cma";
|
|
};
|
|
|
|
lpi_pinctrl@6E80000 {
|
|
phandle = <0x520>;
|
|
clocks = <0x517 0x00 0x518 0x00>;
|
|
clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote";
|
|
qcom,lpi-slew-base-tbl = <0x6e80000 0x6e81000 0x6e82000 0x6e83000 0x6e84000 0x6e85000 0x6e86000 0x6e87000 0x6e88000 0x6e89000 0x6e8a000 0x6e8b000 0x6e8c000 0x6e8d000 0x6e8e000 0x6e8f000 0x6e90000 0x6e91000 0x6e92000 0x6e93000 0x6e94000 0x6e95000 0x6e96000>;
|
|
qcom,lpi-slew-offset-tbl = <0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b>;
|
|
qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>;
|
|
#gpio-cells = <0x02>;
|
|
gpio-controller;
|
|
qcom,slew-reg = <0x6e80000 0x00>;
|
|
qcom,gpios-count = <0x17>;
|
|
reg = <0x6e80000 0x00>;
|
|
compatible = "qcom,lpi-pinctrl";
|
|
};
|
|
|
|
lpass-cdc {
|
|
phandle = <0x521>;
|
|
clocks = <0x517 0x00 0x518 0x00>;
|
|
clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote";
|
|
compatible = "qcom,lpass-cdc";
|
|
|
|
lpass-cdc-clk-rsc-mngr {
|
|
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
|
};
|
|
|
|
va-macro@6D44000 {
|
|
phandle = <0x522>;
|
|
|
|
va_swr_master {
|
|
phandle = <0x523>;
|
|
};
|
|
};
|
|
|
|
tx-macro@6AE0000 {
|
|
phandle = <0x524>;
|
|
};
|
|
|
|
rx-macro@6AC0000 {
|
|
phandle = <0x525>;
|
|
|
|
rx_swr_master {
|
|
phandle = <0x526>;
|
|
};
|
|
};
|
|
|
|
wsa-macro@6B00000 {
|
|
phandle = <0x527>;
|
|
|
|
wsa_swr_master {
|
|
phandle = <0x528>;
|
|
};
|
|
};
|
|
|
|
wsa2-macro@6AA0000 {
|
|
phandle = <0x529>;
|
|
|
|
wsa2_swr_master {
|
|
phandle = <0x52a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sound {
|
|
phandle = <0x52b>;
|
|
wcd939x-i2c-handle = <0x41f>;
|
|
clocks = <0x518 0x00>;
|
|
clock-names = "lpass_audio_hw_vote";
|
|
qcom,afe-rxtx-lb = <0x00>;
|
|
qcom,ext-disp-audio-rx = <0x00>;
|
|
qcom,wcn-bt = <0x00>;
|
|
qcom,auxpcm-audio-intf = <0x01>;
|
|
qcom,tdm-audio-intf = <0x00>;
|
|
qcom,mi2s-audio-intf = <0x01>;
|
|
compatible = "qcom,pineapple-asoc-snd";
|
|
};
|
|
};
|
|
|
|
vote_lpass_core_hw {
|
|
phandle = <0x517>;
|
|
#clock-cells = <0x01>;
|
|
qcom,codec-ext-clk-src = <0x09>;
|
|
compatible = "qcom,audio-ref-clk";
|
|
};
|
|
|
|
vote_lpass_audio_hw {
|
|
phandle = <0x518>;
|
|
#clock-cells = <0x01>;
|
|
qcom,codec-ext-clk-src = <0x0b>;
|
|
compatible = "qcom,audio-ref-clk";
|
|
};
|
|
|
|
qcom,ipcc_compute_l0@443000 {
|
|
phandle = <0x52e>;
|
|
#mbox-cells = <0x02>;
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-controller;
|
|
interrupts = <0x00 0xe6 0x04>;
|
|
reg = <0x443000 0x1000>;
|
|
compatible = "qcom,ipcc";
|
|
};
|
|
|
|
ipclite {
|
|
ranges;
|
|
feature_mask_high = <0x00>;
|
|
feature_mask_low = <0x03>;
|
|
minor_version = <0x00>;
|
|
major_version = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
hwlocks = <0x02 0x0b>;
|
|
memory-region = <0xbd>;
|
|
compatible = "qcom,ipclite";
|
|
|
|
apss {
|
|
phandle = <0x52f>;
|
|
label = "apss";
|
|
qcom,remote-pid = <0x00>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x08 0x00 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x08 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0xf000 0x01 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0xf000 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x08 0x02 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x08 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x08 0x03 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x08 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x08 0x04 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x08 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x08 0x05 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x08 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
|
|
cdsp {
|
|
phandle = <0x530>;
|
|
label = "cdsp";
|
|
qcom,remote-pid = <0x05>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x06 0x00 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x06 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0x06 0x01 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x06 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x06 0x02 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x06 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x06 0x03 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x06 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x06 0x04 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x06 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x06 0x05 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x06 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
|
|
cvp {
|
|
phandle = <0x531>;
|
|
label = "cvp";
|
|
qcom,remote-pid = <0x06>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x0a 0x00 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0a 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0x0a 0x01 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0a 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x0a 0x02 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0a 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x0a 0x03 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0a 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x0a 0x04 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0a 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x0a 0x05 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0a 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
|
|
cam {
|
|
phandle = <0x532>;
|
|
label = "cam";
|
|
qcom,remote-pid = <0x07>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x0b 0x00 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0b 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0x0b 0x01 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0b 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x0b 0x02 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0b 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x0b 0x03 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0b 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x0b 0x04 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0b 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x0b 0x05 0x01>;
|
|
interrupt-parent = <0x52e>;
|
|
mboxes = <0x52e 0x0b 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mmrm-test {
|
|
phandle = <0x533>;
|
|
clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1c4fecc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x42294180 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x35a4e900 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>;
|
|
clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>;
|
|
clock-names = "cam_cc_ife_0_clk_src", "cam_cc_ife_1_clk_src", "cam_cc_ife_2_clk_src", "cam_cc_csid_clk_src", "cam_cc_sfe_0_clk_src", "cam_cc_sfe_1_clk_src", "cam_cc_sfe_2_clk_src", "cam_cc_ipe_nps_clk_src", "cam_cc_bps_clk_src", "cam_cc_ife_lite_clk_src", "cam_cc_jpeg_clk_src", "cam_cc_camnoc_axi_rt_clk_src", "cam_cc_ife_lite_csid_clk_src", "cam_cc_icp_clk_src", "cam_cc_cphy_rx_clk_src", "cam_cc_csi0phytimer_clk_src", "cam_cc_csi1phytimer_clk_src", "cam_cc_csi2phytimer_clk_src", "cam_cc_csi3phytimer_clk_src", "cam_cc_csi4phytimer_clk_src", "cam_cc_csi5phytimer_clk_src", "cam_cc_csi6phytimer_clk_src", "cam_cc_csi7phytimer_clk_src", "cam_cc_cci_0_clk_src", "cam_cc_cci_1_clk_src", "cam_cc_cci_2_clk_src", "cam_cc_slow_ahb_clk_src", "cam_cc_fast_ahb_clk_src", "cam_cc_cre_clk_src", "video_cc_mvs1_clk_src", "disp_cc_mdss_mdp_clk_src", "disp_cc_mdss_dptx0_link_clk_src", "video_cc_mvs0_clk_src";
|
|
status = "disable";
|
|
compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test";
|
|
};
|
|
|
|
qcom,mmrm {
|
|
phandle = <0x534>;
|
|
mmrm-client-info = <0x01 0x45 0x18612f6 0x4d1ec 0x01 0x01 0x49 0x18612f6 0x4d1ec 0x01 0x01 0x4d 0x18612f6 0x4d1ec 0x01 0x01 0x33 0x205ec7 0xdb65 0x03 0x01 0x8e 0x16e2329 0x55fc7 0x01 0x01 0x92 0x16e2329 0x55fc7 0x01 0x01 0x96 0x16e2329 0x55fc7 0x01 0x01 0x58 0x48eeb49 0xd570b 0x01 0x01 0x02 0x2617c8d 0x10709 0x01 0x01 0x52 0x144a28 0x7206 0x02 0x01 0x5f 0xbe037 0x47af 0x04 0x01 0x07 0x7a5b94 0x26a3e 0x01 0x01 0x55 0x3a42b 0x3b99 0x02 0x01 0x43 0x505bc 0x1da6 0x01 0x01 0x1e 0x4ccd 0x81df 0x0a 0x01 0x23 0x199a 0x05 0x01 0x01 0x25 0x199a 0x05 0x01 0x01 0x27 0x199a 0x05 0x01 0x01 0x29 0x199a 0x05 0x01 0x01 0x2b 0x199a 0x05 0x01 0x01 0x2d 0x199a 0x05 0x01 0x01 0x2f 0x199a 0x05 0x01 0x01 0x31 0x199a 0x05 0x01 0x01 0x0b 0x00 0x18d 0x01 0x01 0x0d 0x00 0x18d 0x01 0x01 0x0f 0x00 0x18d 0x01 0x01 0x9b 0xe667 0x2d92 0x01 0x01 0x3f 0x8000 0x195c 0x01 0x01 0x21 0x148d6 0x787 0x01 0x02 0x0a 0x85a51ec 0x13947b 0x01 0x03 0x3e 0xd9cccd 0x34290 0x01 0x03 0x10 0xacccd 0xdf4 0x01 0x04 0x03 0x271bd71 0x1d63d8 0x01>;
|
|
scaling-fact-leak = <0xcb0e6 0xd978e 0xe51aa 0xfa7af 0x13126f>;
|
|
scaling-fact-dyn = <0xc6a8 0xd99a 0xe8f6 0x1051f 0x14b44>;
|
|
mm-rail-fact-volt = <0x9811 0x9eb9 0xa3d8 0xaccd 0xc0c5>;
|
|
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
|
|
mmrm-peak-threshold = <0x2710>;
|
|
status = "okay";
|
|
compatible = "qcom,msm-mmrm", "qcom,pineapple-mmrm";
|
|
};
|
|
|
|
qcom,msm_fastrpc {
|
|
phandle = <0x535>;
|
|
qcom,fastrpc-gids = <0xb5c>;
|
|
qcom,rpc-latency-us = <0xeb>;
|
|
qcom,fastrpc-adsp-sensors-pdr;
|
|
qcom,fastrpc-adsp-audio-pdr;
|
|
qcom,adsp-remoteheap-vmid = <0x16 0x25>;
|
|
compatible = "qcom,msm-fastrpc-compute";
|
|
|
|
qcom,msm_fastrpc_compute_cb1 {
|
|
pd-type = <0x01>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb2 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb3 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb4 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb5 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb6 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb7 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb8 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb9 {
|
|
pd-type = <0x06>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
shared-cb = <0x03>;
|
|
qcom,iommu-vmid = <0x0a>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>;
|
|
qcom,secure-context-bank;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb10 {
|
|
pd-type = <0x01>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>;
|
|
label = "adsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb11 {
|
|
pd-type = <0x03>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
shared-cb = <0x08>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>;
|
|
label = "adsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb12 {
|
|
pd-type = <0x02>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>;
|
|
label = "adsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb13 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>;
|
|
label = "adsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb14 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>;
|
|
label = "adsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb15 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb16 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb17 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>;
|
|
iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>;
|
|
label = "cdsprpc-smd";
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
};
|
|
};
|
|
|
|
qcom,cvp@ab00000 {
|
|
phandle = <0x537>;
|
|
cvp,firmware-name = "evass";
|
|
aon_mappings = <0xff80f000 0x1000 0xabe0000>;
|
|
hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>;
|
|
aon_timer_mappings = <0xffa00000 0x1000 0xc220000>;
|
|
ipclite_mappings = <0xfe500000 0x100000 0x82600000>;
|
|
memory-region = <0x2fc>;
|
|
pas-id = <0x1a>;
|
|
qcom,gcc-reg = <0x110000 0x40000>;
|
|
qcom,ipcc-reg = <0x400000 0x100000>;
|
|
qcom,reg-presets = <0xb0088 0x00>;
|
|
reset-power-status = <0x00 0x01 0x00>;
|
|
reset-names = "cvp_axi_reset", "cvp_xo_reset", "cvp_core_reset";
|
|
resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>;
|
|
qcom,allowed-clock-rates = <0x160dc080 0x1ad27480 0x1dcd6500 0x20c85580>;
|
|
qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>;
|
|
qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src";
|
|
clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>;
|
|
clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>;
|
|
clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src";
|
|
cvp-core-supply = <0x409>;
|
|
cvp-supply = <0xf1>;
|
|
cache-slice-names = "cvp";
|
|
interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>;
|
|
reg = <0xab00000 0x100000>;
|
|
status = "ok";
|
|
compatible = "qcom,msm-cvp", "qcom,pineapple-cvp";
|
|
|
|
cvp_cnoc {
|
|
qcom,bus-range-kbps = <0x3e8 0x3e8>;
|
|
qcom,bus-governor = "performance";
|
|
qcom,bus-slave = <0x22b>;
|
|
qcom,bus-master = <0x03>;
|
|
label = "cvp-cnoc";
|
|
compatible = "qcom,msm-cvp,bus";
|
|
};
|
|
|
|
cvp_bus_ddr {
|
|
qcom,bus-range-kbps = <0x3e8 0x63af88>;
|
|
qcom,bus-governor = "performance";
|
|
qcom,bus-slave = <0x200>;
|
|
qcom,bus-master = <0x21>;
|
|
label = "cvp-ddr";
|
|
compatible = "qcom,msm-cvp,bus";
|
|
};
|
|
|
|
cvp_camera_cb {
|
|
qti,smmu-proxy-cb-id = <0x02>;
|
|
buffer-types = <0xfff>;
|
|
label = "cvp_camera";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_non_secure_cb_group {
|
|
phandle = <0x536>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
|
|
};
|
|
|
|
cvp_non_secure_cb {
|
|
qcom,iommu-group = <0x536>;
|
|
dma-coherent;
|
|
buffer-types = <0xfff>;
|
|
iommus = <0x4f 0x1920 0x00>;
|
|
label = "cvp_hlos";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_secure_nonpixel_cb {
|
|
qcom,iommu-vmid = <0x0b>;
|
|
qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
buffer-types = <0x741>;
|
|
iommus = <0x4f 0x1924 0x00>;
|
|
label = "cvp_sec_nonpixel";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_secure_pixel_cb {
|
|
qcom,iommu-vmid = <0x0a>;
|
|
qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
buffer-types = <0x106>;
|
|
iommus = <0x4f 0x1923 0x00>;
|
|
label = "cvp_sec_pixel";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_dsp_cb {
|
|
qcom,iommu-group = <0x536>;
|
|
buffer-types = <0xfff>;
|
|
iommus = <0x4f 0x1920 0x00>;
|
|
label = "cvp_dsp";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
qcom,msm-cvp,mem_cdsp {
|
|
memory-region = <0x2ff>;
|
|
compatible = "qcom,msm-cvp,mem-cdsp";
|
|
};
|
|
};
|
|
};
|
|
|
|
hypervisor {
|
|
phandle = <0x502>;
|
|
|
|
qcom,gh-watchdog {
|
|
phandle = <0x503>;
|
|
};
|
|
};
|
|
|
|
sched_walt {
|
|
panic_on_walt_bug = <0x4544de18>;
|
|
phandle = <0x504>;
|
|
};
|
|
|
|
__symbols__ {
|
|
non_secure_cb_group = "/soc/qcom,cvp@ab00000/cvp_non_secure_cb_group";
|
|
msm_cvp = "/soc/qcom,cvp@ab00000";
|
|
msm_fastrpc = "/soc/qcom,msm_fastrpc";
|
|
msm_mmrm = "/soc/qcom,mmrm";
|
|
msm_mmrm_test = "/soc/qcom,mmrm-test";
|
|
ipclite_cam = "/soc/ipclite/cam";
|
|
ipclite_cvp = "/soc/ipclite/cvp";
|
|
ipclite_cdsp = "/soc/ipclite/cdsp";
|
|
ipclite_apss = "/soc/ipclite/apss";
|
|
ipcc_compute_l0 = "/soc/qcom,ipcc_compute_l0@443000";
|
|
audio_prm = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr/q6prm";
|
|
audio_gpr = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr";
|
|
lpass_audio_hw_vote = "/soc/vote_lpass_audio_hw";
|
|
lpass_core_hw_vote = "/soc/vote_lpass_core_hw";
|
|
pineapple_snd = "/soc/spf_core_platform/sound";
|
|
swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000/wsa2_swr_master";
|
|
wsa2_macro = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000";
|
|
swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
|
|
wsa_macro = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000";
|
|
swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
|
|
rx_macro = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000";
|
|
tx_macro = "/soc/spf_core_platform/lpass-cdc/tx-macro@6AE0000";
|
|
swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@6D44000/va_swr_master";
|
|
va_macro = "/soc/spf_core_platform/lpass-cdc/va-macro@6D44000";
|
|
lpass_cdc = "/soc/spf_core_platform/lpass-cdc";
|
|
lpi_tlmm = "/soc/spf_core_platform/lpi_pinctrl@6E80000";
|
|
msm_audio_ion_cma = "/soc/spf_core_platform/qcom,msm-audio-ion-cma";
|
|
msm_audio_ion = "/soc/spf_core_platform/qcom,msm-audio-ion";
|
|
spf_core_platform = "/soc/spf_core_platform";
|
|
adsp_notify = "/soc/qcom,msm-adsp-notify";
|
|
adsp_loader = "/soc/qcom,msm-adsp-loader";
|
|
audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform";
|
|
stub_codec = "/soc/qcom,msm-stub-codec";
|
|
msm_vidc = "/soc/qcom,vidc@aa00000";
|
|
funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint";
|
|
funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint";
|
|
gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint";
|
|
coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx";
|
|
cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint";
|
|
coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx";
|
|
gmu = "/soc/qcom,gmu@3d69000";
|
|
gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure";
|
|
gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac";
|
|
gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user";
|
|
kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000";
|
|
ipa_smmu_11ad = "/soc/qcom,ipa@3e00000/ipa_smmu_11ad";
|
|
ipa_smmu_uc = "/soc/qcom,ipa@3e00000/ipa_smmu_uc";
|
|
ipa_smmu_wlan = "/soc/qcom,ipa@3e00000/ipa_smmu_wlan";
|
|
ipa_smmu_ap = "/soc/qcom,ipa@3e00000/ipa_smmu_ap";
|
|
ipa_hw = "/soc/qcom,ipa@3e00000";
|
|
msm_hw_fence = "/soc/qcom,hw-fence";
|
|
chosen = "/chosen";
|
|
aliases = "/aliases";
|
|
reserved_memory = "/reserved-memory";
|
|
gunyah_hyp_mem = "/reserved-memory/gunyah_hyp_region@80000000";
|
|
cpusys_vm_mem = "/reserved-memory/cpusys_vm_region@80e00000";
|
|
xbl_aop_merged_mem = "/reserved-memory/xbl_aop_merged_region@81a00000";
|
|
aop_cmd_db_mem = "/reserved-memory/aop_cmd_db_region@81c60000";
|
|
aop_tme_uefi_merged_mem = "/reserved-memory/aop_tme_uefi_merged_region@81c80000";
|
|
chipinfo_mem = "/reserved-memory/chipinfo_region@81cf4000";
|
|
smem_mem = "/reserved-memory/smem_region@81d00000";
|
|
adsp_mhi_mem = "/reserved-memory/adsp_mhi_region@81f00000";
|
|
pvmfw_mem = "/reserved-memory/pvmfw_region@0x824a0000";
|
|
global_sync_mem = "/reserved-memory/global_sync_region@82600000";
|
|
tz_stat_mem = "/reserved-memory/tz_stat_region@82700000";
|
|
qdss_mem = "/reserved-memory/qdss_region@82800000";
|
|
qlink_logging_mem = "/reserved-memory/qlink_logging_region@84800000";
|
|
mpss_dsm_mem = "/reserved-memory/mpss_dsm_region@86b00000";
|
|
mpss_dsm_mem_2 = "/reserved-memory/mpss_dsm_region_2@8b400000";
|
|
mpss_mem = "/reserved-memory/mpss_region@8bc00000";
|
|
q6_mpss_dtb_mem = "/reserved-memory/q6_mpss_dtb_region@9b000000";
|
|
ipa_fw_mem = "/reserved-memory/ipa_fw_region@9b080000";
|
|
ipa_gsi_mem = "/reserved-memory/ipa_gsi_region@9b090000";
|
|
qseecom_mem = "/reserved-memory/qseecom_region";
|
|
qseecom_ta_mem = "/reserved-memory/qseecom_ta_region";
|
|
qmc_dma_mem = "/reserved-memory/qmc_dma_region";
|
|
non_secure_display_memory = "/reserved-memory/non_secure_display_region";
|
|
gpu_micro_code_mem = "/reserved-memory/gpu_microcode_region@9b09a000";
|
|
spss_region_mem = "/reserved-memory/spss_region_region@9b0a0000";
|
|
spu_tz_shared_mem = "/reserved-memory/spu_secure_shared_memory_region@9b280000";
|
|
spu_modem_shared_mem = "/reserved-memory/spu_secure_shared_memory_region@9b2e0000";
|
|
camera_mem = "/reserved-memory/camera_region@9b300000";
|
|
video_mem = "/reserved-memory/video_region@9bb00000";
|
|
cvp_mem = "/reserved-memory/cvp_region@9c300000";
|
|
cdsp_mem = "/reserved-memory/cdsp_region@9ca00000";
|
|
q6_cdsp_dtb_mem = "/reserved-memory/q6_cdsp_dtb_region@9de00000";
|
|
q6_adsp_dtb_mem = "/reserved-memory/q6_adsp_dtb_region@9de80000";
|
|
adsp_slpi_mem = "/reserved-memory/adspslpi_region@9df00000";
|
|
tz_merged_mem = "/reserved-memory/tz_merged_region@d8000000";
|
|
hwfence_shbuf = "/reserved-memory/hwfence-shmem";
|
|
vm_comm_mem = "/reserved-memory/vm_comm_mem_region";
|
|
trust_ui_vm_dump = "/reserved-memory/trust_ui_vm_dump@0xf37ff000";
|
|
trust_ui_vm_mem = "/reserved-memory/trust_ui_vm_region@f3800000";
|
|
llcc_lpi_mem = "/reserved-memory/llcc_lpi_region@ff800000";
|
|
va_md_mem = "/reserved-memory/va_md_mem_region";
|
|
sp_mem = "/reserved-memory/sp_region";
|
|
cdsp_eva_mem = "/reserved-memory/cdsp_eva_region";
|
|
adsp_mem_heap = "/reserved-memory/adsp_heap_region";
|
|
system_cma = "/reserved-memory/linux,cma";
|
|
cdsp_secure_heap_cma = "/reserved-memory/secure_cdsp_region";
|
|
kinfo_mem = "/reserved-memory/debug_kinfo_region";
|
|
ramoops_mem = "/reserved-memory/ramoops_region";
|
|
dump_mem = "/reserved-memory/mem_dump_region";
|
|
firmware = "/firmware";
|
|
CPU0 = "/cpus/cpu@0";
|
|
L2_0 = "/cpus/cpu@0/l2-cache";
|
|
L3_0 = "/cpus/cpu@0/l2-cache/l3-cache";
|
|
CPU1 = "/cpus/cpu@100";
|
|
CPU2 = "/cpus/cpu@200";
|
|
L2_2 = "/cpus/cpu@200/l2-cache";
|
|
CPU3 = "/cpus/cpu@300";
|
|
L2_3 = "/cpus/cpu@300/l2-cache";
|
|
CPU4 = "/cpus/cpu@400";
|
|
L2_4 = "/cpus/cpu@400/l2-cache";
|
|
CPU5 = "/cpus/cpu@500";
|
|
L2_5 = "/cpus/cpu@500/l2-cache";
|
|
CPU6 = "/cpus/cpu@600";
|
|
L2_6 = "/cpus/cpu@600/l2-cache";
|
|
CPU7 = "/cpus/cpu@700";
|
|
L2_7 = "/cpus/cpu@700/l2-cache";
|
|
SILVER_OFF_CL0 = "/idle-states/silver-cluster0-c4";
|
|
GOLD_OFF_CL1 = "/idle-states/gold-cluster1-c4";
|
|
GOLD_OFF_CL2 = "/idle-states/gold-cluster2-c4";
|
|
GOLD_OFF_CL3 = "/idle-states/gold-plus-cluster3-c4";
|
|
CLUSTER_PWR_DN = "/idle-states/cluster-d4";
|
|
APSS_OFF = "/idle-states/cluster-e3";
|
|
soc = "/soc";
|
|
CPU_PD0 = "/soc/psci/cpu-pd0";
|
|
CPU_PD1 = "/soc/psci/cpu-pd1";
|
|
CPU_PD2 = "/soc/psci/cpu-pd2";
|
|
CPU_PD3 = "/soc/psci/cpu-pd3";
|
|
CPU_PD4 = "/soc/psci/cpu-pd4";
|
|
CPU_PD5 = "/soc/psci/cpu-pd5";
|
|
CPU_PD6 = "/soc/psci/cpu-pd6";
|
|
CPU_PD7 = "/soc/psci/cpu-pd7";
|
|
CLUSTER_PD = "/soc/psci/cluster-pd";
|
|
slimbam = "/soc/bamdma@6C04000";
|
|
slim_msm = "/soc/slim@6C40000";
|
|
intc = "/soc/interrupt-controller@17100000";
|
|
gic_its = "/soc/interrupt-controller@17100000/msi-controller@17140000";
|
|
arch_timer = "/soc/timer";
|
|
memtimer = "/soc/timer@17420000";
|
|
cpu_pmu = "/soc/cpu-pmu";
|
|
pcie_crm_hw_0_bcm_voter = "/soc/bcm_voter@0";
|
|
pcie_crm_hw_1_bcm_voter = "/soc/bcm_voter@1";
|
|
clk_virt = "/soc/interconnect@0";
|
|
mc_virt = "/soc/interconnect@1";
|
|
config_noc = "/soc/interconnect@1600000";
|
|
cnoc_main = "/soc/interconnect@1500000";
|
|
system_noc = "/soc/interconnect@1680000";
|
|
pcie_noc = "/soc/interconnect@16c0000";
|
|
aggre1_noc = "/soc/interconnect@16e0000";
|
|
aggre2_noc = "/soc/interconnect@1700000";
|
|
mmss_noc = "/soc/interconnect@1780000";
|
|
gem_noc = "/soc/interconnect@24100000";
|
|
nsp_noc = "/soc/interconnect@320c0000";
|
|
lpass_ag_noc = "/soc/interconnect@7e40000";
|
|
lpass_lpiaon_noc = "/soc/interconnect@7400000";
|
|
lpass_lpicx_noc = "/soc/interconnect@7430000";
|
|
pdc = "/soc/interrupt-controller@b220000";
|
|
pcie_pdc = "/soc/pdc@b350000";
|
|
tlmm = "/soc/pinctrl@f000000";
|
|
qupv3_se15_2uart_pins = "/soc/pinctrl@f000000/qupv3_se15_2uart_pins";
|
|
qupv3_se15_2uart_tx_active = "/soc/pinctrl@f000000/qupv3_se15_2uart_pins/qupv3_se15_2uart_tx_active";
|
|
qupv3_se15_2uart_rx_active = "/soc/pinctrl@f000000/qupv3_se15_2uart_pins/qupv3_se15_2uart_rx_active";
|
|
qupv3_se15_2uart_sleep = "/soc/pinctrl@f000000/qupv3_se15_2uart_pins/qupv3_se15_2uart_sleep";
|
|
trigout_a = "/soc/pinctrl@f000000/trigout_a";
|
|
pcie0_perst_default = "/soc/pinctrl@f000000/pcie0/pcie0_perst_default";
|
|
pcie0_clkreq_default = "/soc/pinctrl@f000000/pcie0/pcie0_clkreq_default";
|
|
pcie0_wake_default = "/soc/pinctrl@f000000/pcie0/pcie0_wake_default";
|
|
pcie0_clkreq_sleep = "/soc/pinctrl@f000000/pcie0/pcie0_clkreq_sleep";
|
|
pcie1_perst_default = "/soc/pinctrl@f000000/pcie1/pcie1_perst_default";
|
|
pcie1_clkreq_default = "/soc/pinctrl@f000000/pcie1/pcie1_clkreq_default";
|
|
pcie1_wake_default = "/soc/pinctrl@f000000/pcie1/pcie1_wake_default";
|
|
pcie1_clkreq_sleep = "/soc/pinctrl@f000000/pcie1/pcie1_clkreq_sleep";
|
|
qupv3_se14_4uart_pins = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins";
|
|
qupv3_se14_default_cts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_cts";
|
|
qupv3_se14_default_rts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_rts";
|
|
qupv3_se14_default_tx = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_tx";
|
|
qupv3_se14_default_rx = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_rx";
|
|
qupv3_se14_cts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_cts";
|
|
qupv3_se14_rts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_rts";
|
|
qupv3_se14_tx = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_tx";
|
|
qupv3_se14_rx = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_rx";
|
|
qupv3_se0_i2c_pins = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins";
|
|
qupv3_se0_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sda_active";
|
|
qupv3_se0_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_scl_active";
|
|
qupv3_se0_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep";
|
|
qupv3_se0_i3c_pins = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins";
|
|
qupv3_se0_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_sda_active";
|
|
qupv3_se0_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_scl_active";
|
|
qupv3_se0_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_sda_sleep";
|
|
qupv3_se0_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_scl_sleep";
|
|
qupv3_se0_i3c_disable = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_disable";
|
|
qupv3_se0_spi_pins = "/soc/pinctrl@f000000/qupv3_se0_spi_pins";
|
|
qupv3_se0_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_miso_active";
|
|
qupv3_se0_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_mosi_active";
|
|
qupv3_se0_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_clk_active";
|
|
qupv3_se0_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_cs_active";
|
|
qupv3_se0_spi_sleep = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_sleep";
|
|
qupv3_se1_i2c_pins = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins";
|
|
qupv3_se1_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sda_active";
|
|
qupv3_se1_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_scl_active";
|
|
qupv3_se1_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep";
|
|
qupv3_se1_spi_pins = "/soc/pinctrl@f000000/qupv3_se1_spi_pins";
|
|
qupv3_se1_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_miso_active";
|
|
qupv3_se1_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_mosi_active";
|
|
qupv3_se1_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_clk_active";
|
|
qupv3_se1_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_cs_active";
|
|
qupv3_se1_spi_sleep = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep";
|
|
qupv3_se2_i2c_pins = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins";
|
|
qupv3_se2_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sda_active";
|
|
qupv3_se2_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins/qupv3_se2_i2c_scl_active";
|
|
qupv3_se2_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep";
|
|
qupv3_se2_spi_pins = "/soc/pinctrl@f000000/qupv3_se2_spi_pins";
|
|
qupv3_se2_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_miso_active";
|
|
qupv3_se2_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_mosi_active";
|
|
qupv3_se2_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_clk_active";
|
|
qupv3_se2_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_cs_active";
|
|
qupv3_se2_spi_sleep = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_sleep";
|
|
qupv3_se3_i2c_pins = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins";
|
|
qupv3_se3_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sda_active";
|
|
qupv3_se3_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_scl_active";
|
|
qupv3_se3_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sleep";
|
|
qupv3_se3_spi_pins = "/soc/pinctrl@f000000/qupv3_se3_spi_pins";
|
|
qupv3_se3_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_miso_active";
|
|
qupv3_se3_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_mosi_active";
|
|
qupv3_se3_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_clk_active";
|
|
qupv3_se3_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_cs_active";
|
|
qupv3_se3_spi_sleep = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_sleep";
|
|
qupv3_se4_i2c_pins = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins";
|
|
qupv3_se4_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sda_active";
|
|
qupv3_se4_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_scl_active";
|
|
qupv3_se4_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sleep";
|
|
qupv3_se4_i3c_pins = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins";
|
|
qupv3_se4_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_sda_active";
|
|
qupv3_se4_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_scl_active";
|
|
qupv3_se4_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_sda_sleep";
|
|
qupv3_se4_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_scl_sleep";
|
|
qupv3_se4_i3c_disable = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_disable";
|
|
qupv3_se4_spi_pins = "/soc/pinctrl@f000000/qupv3_se4_spi_pins";
|
|
qupv3_se4_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_miso_active";
|
|
qupv3_se4_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_mosi_active";
|
|
qupv3_se4_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_clk_active";
|
|
qupv3_se4_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_cs_active";
|
|
qupv3_se4_spi_sleep = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_sleep";
|
|
qupv3_se5_i2c_pins = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins";
|
|
qupv3_se5_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sda_active";
|
|
qupv3_se5_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_scl_active";
|
|
qupv3_se5_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sleep";
|
|
qupv3_se5_spi_pins = "/soc/pinctrl@f000000/qupv3_se5_spi_pins";
|
|
qupv3_se5_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_miso_active";
|
|
qupv3_se5_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_mosi_active";
|
|
qupv3_se5_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_clk_active";
|
|
qupv3_se5_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_cs_active";
|
|
qupv3_se5_spi_sleep = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_sleep";
|
|
qupv3_se6_i2c_pins = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins";
|
|
qupv3_se6_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sda_active";
|
|
qupv3_se6_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_scl_active";
|
|
qupv3_se6_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sleep";
|
|
qupv3_se6_spi_pins = "/soc/pinctrl@f000000/qupv3_se6_spi_pins";
|
|
qupv3_se6_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_miso_active";
|
|
qupv3_se6_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_mosi_active";
|
|
qupv3_se6_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_clk_active";
|
|
qupv3_se6_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_cs_active";
|
|
qupv3_se6_spi_sleep = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_sleep";
|
|
qupv3_se7_i2c_pins = "/soc/pinctrl@f000000/qupv3_se7_i2c_pins";
|
|
qupv3_se7_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se7_i2c_pins/qupv3_se7_i2c_sda_active";
|
|
qupv3_se7_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se7_i2c_pins/qupv3_se7_i2c_scl_active";
|
|
qupv3_se7_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se7_i2c_pins/qupv3_se7_i2c_sleep";
|
|
qupv3_se7_spi_pins = "/soc/pinctrl@f000000/qupv3_se7_spi_pins";
|
|
qupv3_se7_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se7_spi_pins/qupv3_se7_spi_miso_active";
|
|
qupv3_se7_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se7_spi_pins/qupv3_se7_spi_mosi_active";
|
|
qupv3_se7_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se7_spi_pins/qupv3_se7_spi_clk_active";
|
|
qupv3_se7_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se7_spi_pins/qupv3_se7_spi_cs_active";
|
|
qupv3_se7_spi_sleep = "/soc/pinctrl@f000000/qupv3_se7_spi_pins/qupv3_se7_spi_sleep";
|
|
qupv3_se8_i2c_pins = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins";
|
|
qupv3_se8_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sda_active";
|
|
qupv3_se8_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_scl_active";
|
|
qupv3_se8_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sleep";
|
|
qupv3_se8_spi_pins = "/soc/pinctrl@f000000/qupv3_se8_spi_pins";
|
|
qupv3_se8_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_miso_active";
|
|
qupv3_se8_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_mosi_active";
|
|
qupv3_se8_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_clk_active";
|
|
qupv3_se8_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_cs_active";
|
|
qupv3_se8_spi_sleep = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_sleep";
|
|
qupv3_se8_i3c_pins = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins";
|
|
qupv3_se8_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_sda_active";
|
|
qupv3_se8_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_scl_active";
|
|
qupv3_se8_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_sda_sleep";
|
|
qupv3_se8_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_scl_sleep";
|
|
qupv3_se8_i3c_disable = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_disable";
|
|
qupv3_se9_i2c_pins = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins";
|
|
qupv3_se9_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sda_active";
|
|
qupv3_se9_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_scl_active";
|
|
qupv3_se9_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sleep";
|
|
qupv3_se9_spi_pins = "/soc/pinctrl@f000000/qupv3_se9_spi_pins";
|
|
qupv3_se9_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_miso_active";
|
|
qupv3_se9_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_mosi_active";
|
|
qupv3_se9_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_clk_active";
|
|
qupv3_se9_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_cs_active";
|
|
qupv3_se9_spi_sleep = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_sleep";
|
|
qupv3_se10_i2c_pins = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins";
|
|
qupv3_se10_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sda_active";
|
|
qupv3_se10_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins/qupv3_se10_i2c_scl_active";
|
|
qupv3_se10_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sleep";
|
|
qupv3_se10_spi_pins = "/soc/pinctrl@f000000/qupv3_se10_spi_pins";
|
|
qupv3_se10_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_miso_active";
|
|
qupv3_se10_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_mosi_active";
|
|
qupv3_se10_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_clk_active";
|
|
qupv3_se10_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_cs_active";
|
|
qupv3_se10_spi_sleep = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_sleep";
|
|
qupv3_se10_i3c_pins = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins";
|
|
qupv3_se10_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_sda_active";
|
|
qupv3_se10_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_scl_active";
|
|
qupv3_se10_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_sda_sleep";
|
|
qupv3_se10_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_scl_sleep";
|
|
qupv3_se10_i3c_disable = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_disable";
|
|
qupv3_se11_i2c_pins = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins";
|
|
qupv3_se11_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sda_active";
|
|
qupv3_se11_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins/qupv3_se11_i2c_scl_active";
|
|
qupv3_se11_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sleep";
|
|
qupv3_se11_spi_pins = "/soc/pinctrl@f000000/qupv3_se11_spi_pins";
|
|
qupv3_se11_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_miso_active";
|
|
qupv3_se11_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_mosi_active";
|
|
qupv3_se11_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_clk_active";
|
|
qupv3_se11_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_cs_active";
|
|
qupv3_se11_spi_sleep = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_sleep";
|
|
qupv3_se11_i3c_pins = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins";
|
|
qupv3_se11_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_sda_active";
|
|
qupv3_se11_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_scl_active";
|
|
qupv3_se11_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_sda_sleep";
|
|
qupv3_se11_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_scl_sleep";
|
|
qupv3_se11_i3c_disable = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_disable";
|
|
qupv3_se12_i2c_pins = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins";
|
|
qupv3_se12_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins/qupv3_se12_i2c_sda_active";
|
|
qupv3_se12_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins/qupv3_se12_i2c_scl_active";
|
|
qupv3_se12_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins/qupv3_se12_i2c_sleep";
|
|
qupv3_se12_spi_pins = "/soc/pinctrl@f000000/qupv3_se12_spi_pins";
|
|
qupv3_se12_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_miso_active";
|
|
qupv3_se12_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_mosi_active";
|
|
qupv3_se12_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_clk_active";
|
|
qupv3_se12_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_cs_active";
|
|
qupv3_se12_spi_sleep = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_sleep";
|
|
qupv3_se13_i2c_pins = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins";
|
|
qupv3_se13_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins/qupv3_se13_i2c_sda_active";
|
|
qupv3_se13_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins/qupv3_se13_i2c_scl_active";
|
|
qupv3_se13_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins/qupv3_se13_i2c_sleep";
|
|
qupv3_se13_spi_pins = "/soc/pinctrl@f000000/qupv3_se13_spi_pins";
|
|
qupv3_se13_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_miso_active";
|
|
qupv3_se13_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_mosi_active";
|
|
qupv3_se13_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_clk_active";
|
|
qupv3_se13_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_cs_active";
|
|
qupv3_se13_spi_sleep = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_sleep";
|
|
qupv3_se13_q2spi_pins = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins";
|
|
qupv3_se13_q2spi_default = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_default";
|
|
qupv3_se13_q2spi_miso_default = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_miso_default";
|
|
qupv3_se13_q2spi_miso_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_miso_active";
|
|
qupv3_se13_q2spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_mosi_active";
|
|
qupv3_se13_q2spi_clk_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_clk_active";
|
|
qupv3_se13_q2spi_doorbell_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_doorbell_active";
|
|
qupv3_se13_q2spi_doorbell_sleep = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_doorbell_sleep";
|
|
qupv3_se13_q2spi_miso_sleep = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_miso_sleep";
|
|
qupv3_hub_i2c0_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins";
|
|
qupv3_hub_i2c0_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins/qupv3_hub_i2c0_sda_active";
|
|
qupv3_hub_i2c0_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins/qupv3_hub_i2c0_scl_active";
|
|
qupv3_hub_i2c0_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins/qupv3_hub_i2c0_sleep";
|
|
qupv3_hub_i2c1_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins";
|
|
qupv3_hub_i2c1_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins/qupv3_hub_i2c1_sda_active";
|
|
qupv3_hub_i2c1_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins/qupv3_hub_i2c1_scl_active";
|
|
qupv3_hub_i2c1_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins/qupv3_hub_i2c1_sleep";
|
|
qupv3_hub_i2c2_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins";
|
|
qupv3_hub_i2c2_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins/qupv3_hub_i2c2_sda_active";
|
|
qupv3_hub_i2c2_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins/qupv3_hub_i2c2_scl_active";
|
|
qupv3_hub_i2c2_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins/qupv3_hub_i2c2_sleep";
|
|
qupv3_hub_i2c3_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins";
|
|
qupv3_hub_i2c3_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins/qupv3_hub_i2c3_sda_active";
|
|
qupv3_hub_i2c3_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins/qupv3_hub_i2c3_scl_active";
|
|
qupv3_hub_i2c3_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins/qupv3_hub_i2c3_sleep";
|
|
qupv3_hub_i2c4_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins";
|
|
qupv3_hub_i2c4_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins/qupv3_hub_i2c4_sda_active";
|
|
qupv3_hub_i2c4_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins/qupv3_hub_i2c4_scl_active";
|
|
qupv3_hub_i2c4_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins/qupv3_hub_i2c4_sleep";
|
|
qupv3_hub_i2c5_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins";
|
|
qupv3_hub_i2c5_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins/qupv3_hub_i2c5_sda_active";
|
|
qupv3_hub_i2c5_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins/qupv3_hub_i2c5_scl_active";
|
|
qupv3_hub_i2c5_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins/qupv3_hub_i2c5_sleep";
|
|
qupv3_hub_i2c6_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins";
|
|
qupv3_hub_i2c6_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins/qupv3_hub_i2c6_sda_active";
|
|
qupv3_hub_i2c6_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins/qupv3_hub_i2c6_scl_active";
|
|
qupv3_hub_i2c6_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins/qupv3_hub_i2c6_sleep";
|
|
qupv3_hub_i2c7_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins";
|
|
qupv3_hub_i2c7_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins/qupv3_hub_i2c7_sda_active";
|
|
qupv3_hub_i2c7_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins/qupv3_hub_i2c7_scl_active";
|
|
qupv3_hub_i2c7_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins/qupv3_hub_i2c7_sleep";
|
|
qupv3_hub_i2c8_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins";
|
|
qupv3_hub_i2c8_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins/qupv3_hub_i2c8_sda_active";
|
|
qupv3_hub_i2c8_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins/qupv3_hub_i2c8_scl_active";
|
|
qupv3_hub_i2c8_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins/qupv3_hub_i2c8_sleep";
|
|
qupv3_hub_i2c9_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins";
|
|
qupv3_hub_i2c9_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins/qupv3_hub_i2c9_sda_active";
|
|
qupv3_hub_i2c9_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins/qupv3_hub_i2c9_scl_active";
|
|
qupv3_hub_i2c9_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins/qupv3_hub_i2c9_sleep";
|
|
aux0_pcm_clk_sleep = "/soc/pinctrl@f000000/aux0_pcm_clk/aux0_pcm_clk_sleep";
|
|
aux0_pcm_clk_active = "/soc/pinctrl@f000000/aux0_pcm_clk/aux0_pcm_clk_active";
|
|
aux0_pcm_ws_sleep = "/soc/pinctrl@f000000/aux0_pcm_ws/aux0_pcm_ws_sleep";
|
|
aux0_pcm_ws_active = "/soc/pinctrl@f000000/aux0_pcm_ws/aux0_pcm_ws_active";
|
|
aux0_pcm_din_sleep = "/soc/pinctrl@f000000/aux0_pcm_din/aux0_pcm_din_sleep";
|
|
aux0_pcm_din_active = "/soc/pinctrl@f000000/aux0_pcm_din/aux0_pcm_din_active";
|
|
aux0_pcm_dout_sleep = "/soc/pinctrl@f000000/aux0_pcm_dout/aux0_pcm_dout_sleep";
|
|
aux0_pcm_dout_active = "/soc/pinctrl@f000000/aux0_pcm_dout/aux0_pcm_dout_active";
|
|
aux1_pcm_clk_sleep = "/soc/pinctrl@f000000/aux1_pcm_clk/aux1_pcm_clk_sleep";
|
|
aux1_pcm_clk_active = "/soc/pinctrl@f000000/aux1_pcm_clk/aux1_pcm_clk_active";
|
|
aux1_pcm_ws_sleep = "/soc/pinctrl@f000000/aux1_pcm_ws/aux1_pcm_ws_sleep";
|
|
aux1_pcm_ws_active = "/soc/pinctrl@f000000/aux1_pcm_ws/aux1_pcm_ws_active";
|
|
aux1_pcm_din_sleep = "/soc/pinctrl@f000000/aux1_pcm_din/aux1_pcm_din_sleep";
|
|
aux1_pcm_din_active = "/soc/pinctrl@f000000/aux1_pcm_din/aux1_pcm_din_active";
|
|
aux1_pcm_dout_sleep = "/soc/pinctrl@f000000/aux1_pcm_dout/aux1_pcm_dout_sleep";
|
|
aux1_pcm_dout_active = "/soc/pinctrl@f000000/aux1_pcm_dout/aux1_pcm_dout_active";
|
|
tdm0_clk_sleep = "/soc/pinctrl@f000000/tdm0_clk/tdm0_clk_sleep";
|
|
tdm0_clk_active = "/soc/pinctrl@f000000/tdm0_clk/tdm0_clk_active";
|
|
tdm0_ws_sleep = "/soc/pinctrl@f000000/tdm0_ws/tdm0_ws_sleep";
|
|
tdm0_ws_active = "/soc/pinctrl@f000000/tdm0_ws/tdm0_ws_active";
|
|
tdm0_din_sleep = "/soc/pinctrl@f000000/tdm0_din/tdm0_din_sleep";
|
|
tdm0_din_active = "/soc/pinctrl@f000000/tdm0_din/tdm0_din_active";
|
|
tdm0_dout_sleep = "/soc/pinctrl@f000000/tdm0_dout/tdm0_dout_sleep";
|
|
tdm0_dout_active = "/soc/pinctrl@f000000/tdm0_dout/tdm0_dout_active";
|
|
tdm1_clk_sleep = "/soc/pinctrl@f000000/tdm1_clk/tdm1_clk_sleep";
|
|
tdm1_clk_active = "/soc/pinctrl@f000000/tdm1_clk/tdm1_clk_active";
|
|
tdm1_ws_sleep = "/soc/pinctrl@f000000/tdm1_ws/tdm1_ws_sleep";
|
|
tdm1_ws_active = "/soc/pinctrl@f000000/tdm1_ws/tdm1_ws_active";
|
|
tdm1_din_sleep = "/soc/pinctrl@f000000/tdm1_din/tdm1_din_sleep";
|
|
tdm1_din_active = "/soc/pinctrl@f000000/tdm1_din/tdm1_din_active";
|
|
tdm1_dout_sleep = "/soc/pinctrl@f000000/tdm1_dout/tdm1_dout_sleep";
|
|
tdm1_dout_active = "/soc/pinctrl@f000000/tdm1_dout/tdm1_dout_active";
|
|
i2s0_sck_sleep = "/soc/pinctrl@f000000/i2s0_sck/i2s0_sck_sleep";
|
|
i2s0_sck_active = "/soc/pinctrl@f000000/i2s0_sck/i2s0_sck_active";
|
|
i2s0_ws_sleep = "/soc/pinctrl@f000000/i2s0_ws/i2s0_ws_sleep";
|
|
i2s0_ws_active = "/soc/pinctrl@f000000/i2s0_ws/i2s0_ws_active";
|
|
i2s0_sd0_sleep = "/soc/pinctrl@f000000/i2s0_sd0/i2s0_sd0_sleep";
|
|
i2s0_sd0_active = "/soc/pinctrl@f000000/i2s0_sd0/i2s0_sd0_active";
|
|
i2s0_sd1_sleep = "/soc/pinctrl@f000000/i2s0_sd1/i2s0_sd1_sleep";
|
|
i2s0_sd1_active = "/soc/pinctrl@f000000/i2s0_sd1/i2s0_sd1_active";
|
|
i2s1_sck_sleep = "/soc/pinctrl@f000000/i2s1_sck/i2s1_sck_sleep";
|
|
i2s1_sck_active = "/soc/pinctrl@f000000/i2s1_sck/i2s1_sck_active";
|
|
i2s1_ws_sleep = "/soc/pinctrl@f000000/i2s1_ws/i2s1_ws_sleep";
|
|
i2s1_ws_active = "/soc/pinctrl@f000000/i2s1_ws/i2s1_ws_active";
|
|
i2s1_sd0_sleep = "/soc/pinctrl@f000000/i2s1_sd0/i2s1_sd0_sleep";
|
|
i2s1_sd0_active = "/soc/pinctrl@f000000/i2s1_sd0/i2s1_sd0_active";
|
|
i2s1_sd1_sleep = "/soc/pinctrl@f000000/i2s1_sd1/i2s1_sd1_sleep";
|
|
i2s1_sd1_active = "/soc/pinctrl@f000000/i2s1_sd1/i2s1_sd1_active";
|
|
sdc2_on = "/soc/pinctrl@f000000/sdc2_on";
|
|
sdc2_off = "/soc/pinctrl@f000000/sdc2_off";
|
|
wcd939x_reset_active = "/soc/pinctrl@f000000/wcd939x_reset_active";
|
|
wcd939x_reset_sleep = "/soc/pinctrl@f000000/wcd939x_reset_sleep";
|
|
spkr_13_sd_n_sleep = "/soc/pinctrl@f000000/spkr_13_sd_n/spkr_13_sd_n_sleep";
|
|
spkr_13_sd_n_active = "/soc/pinctrl@f000000/spkr_13_sd_n/spkr_13_sd_n_active";
|
|
usb_phy_ps = "/soc/pinctrl@f000000/usb_phy_ps";
|
|
usb3phy_portselect_default = "/soc/pinctrl@f000000/usb_phy_ps/usb3phy_portselect_default";
|
|
usb3phy_portselect_gpio = "/soc/pinctrl@f000000/usb_phy_ps/usb3phy_portselect_gpio";
|
|
ts_active = "/soc/pinctrl@f000000/pmx_ts_active/ts_active";
|
|
ts_reset_suspend = "/soc/pinctrl@f000000/pmx_ts_reset_suspend/ts_reset_suspend";
|
|
ts_int_suspend = "/soc/pinctrl@f000000/pmx_ts_int_suspend/ts_int_suspend";
|
|
ts_release = "/soc/pinctrl@f000000/pmx_ts_release/ts_release";
|
|
qca_intn_wol_sig = "/soc/pinctrl@f000000/qps615_intn_wol/qca_intn_wol_sig";
|
|
vendor_hooks = "/soc/qcom,cpu-vendor-hooks";
|
|
logbuf = "/soc/qcom,logbuf-vendor-hooks";
|
|
apps_rsc = "/soc/rsc@17a00000";
|
|
apps_rsc_drv2 = "/soc/rsc@17a00000/drv@2";
|
|
apps_bcm_voter = "/soc/rsc@17a00000/drv@2/bcm_voter";
|
|
rpmhcc = "/soc/rsc@17a00000/drv@2/clock-controller";
|
|
dcvs_fp = "/soc/rsc@17a00000/drv@2/qcom,dcvs-fp";
|
|
VDD_LPI_CX_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-lcxlvl/regulator-pm-v6d-s4-level";
|
|
S4D_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-lcxlvl/regulator-pm-v6d-s4-level";
|
|
pm_v6d_s4_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-lcxlvl/regulator-pm-v6d-s4-level";
|
|
VDD_GFX_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-gfxlvl/regulator-pm-v6d-s5-level";
|
|
S5D_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-gfxlvl/regulator-pm-v6d-s5-level";
|
|
pm_v6d_s5_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-gfxlvl/regulator-pm-v6d-s5-level";
|
|
VDD_LPI_MX_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-lmxlvl/regulator-pm-v6d-l2-level";
|
|
L2D_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-lmxlvl/regulator-pm-v6d-l2-level";
|
|
pm_v6d_l2_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-lmxlvl/regulator-pm-v6d-l2-level";
|
|
VDD_NSP2_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-nsp2lvl/regulator-pm-v6g-s1-level";
|
|
S1G_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-nsp2lvl/regulator-pm-v6g-s1-level";
|
|
pm_v6g_s1_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-nsp2lvl/regulator-pm-v6g-s1-level";
|
|
VDD_EBI_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ebilvl/regulator-pm-v6g-s4-level";
|
|
S4G_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ebilvl/regulator-pm-v6g-s4-level";
|
|
pm_v6g_s4_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ebilvl/regulator-pm-v6g-s4-level";
|
|
VDD_MODEM_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-msslvl/regulator-pm-v6g-s5-level";
|
|
S5G_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-msslvl/regulator-pm-v6g-s5-level";
|
|
pm_v6g_s5_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-msslvl/regulator-pm-v6g-s5-level";
|
|
VDD_CX_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v8-s8-level";
|
|
S8I_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v8-s8-level";
|
|
pm_v8_s8_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v8-s8-level";
|
|
VDD_CX_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v8-s8-level-ao";
|
|
S8I_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v8-s8-level-ao";
|
|
pm_v8_s8_level_ao = "/soc/rsc@17a00000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v8-s8-level-ao";
|
|
VDD_CX_MMCX_SUPPLY_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v8-s8-mmcx-sup-level";
|
|
VDD_MMCX_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level";
|
|
VDD_MM_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level";
|
|
S1I_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level";
|
|
pm_v8_s1_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level";
|
|
VDD_MMCX_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level-ao";
|
|
VDD_MM_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level-ao";
|
|
S1I_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level-ao";
|
|
pm_v8_s1_level_ao = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8-s1-level-ao";
|
|
VDD_MXA_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxlvl/regulator-pm-v8-s3-level";
|
|
S3I_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxlvl/regulator-pm-v8-s3-level";
|
|
pm_v8_s3_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxlvl/regulator-pm-v8-s3-level";
|
|
VDD_MXA_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxlvl/regulator-pm-v8-s3-level-ao";
|
|
S3I_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxlvl/regulator-pm-v8-s3-level-ao";
|
|
pm_v8_s3_level_ao = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxlvl/regulator-pm-v8-s3-level-ao";
|
|
VDD_MXC_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-level";
|
|
S3D_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-level";
|
|
pm_v6d_s3_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-level";
|
|
VDD_MXC_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-level-ao";
|
|
S3D_LEVEL_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-level-ao";
|
|
pm_v6d_s3_level_ao = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-level-ao";
|
|
VDD_MXC_MMCX_VOTER_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-mmcx-voter-level";
|
|
VDD_MXC_MM_VOTER_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-mmcx-voter-level";
|
|
VDD_MM_MXC_VOTER_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-mmcx-voter-level";
|
|
VDD_MXC_GFX_VOTER_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-gfx-voter-level";
|
|
VDD_GFX_MXC_VOTER_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v6d-s3-gfx-voter-level";
|
|
VDD_NSP1_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-nsplvl/regulator-pm-v8-s6-level";
|
|
S6I_LEVEL = "/soc/rsc@17a00000/drv@2/rpmh-regulator-nsplvl/regulator-pm-v8-s6-level";
|
|
pm_v8_s6_level = "/soc/rsc@17a00000/drv@2/rpmh-regulator-nsplvl/regulator-pm-v8-s6-level";
|
|
L1B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob1/regulator-pm-humu-l1";
|
|
pm_humu_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob1/regulator-pm-humu-l1";
|
|
L2B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob2/regulator-pm-humu-l2";
|
|
pm_humu_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob2/regulator-pm-humu-l2";
|
|
L4B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob4/regulator-pm-humu-l4";
|
|
pm_humu_l4 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob4/regulator-pm-humu-l4";
|
|
L5B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob5/regulator-pm-humu-l5";
|
|
pm_humu_l5 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob5/regulator-pm-humu-l5";
|
|
L6B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob6/regulator-pm-humu-l6";
|
|
pm_humu_l6 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob6/regulator-pm-humu-l6";
|
|
L7B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob7/regulator-pm-humu-l7";
|
|
pm_humu_l7 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob7/regulator-pm-humu-l7";
|
|
L8B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob8/regulator-pm-humu-l8";
|
|
pm_humu_l8 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob8/regulator-pm-humu-l8";
|
|
L9B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob9/regulator-pm-humu-l9";
|
|
pm_humu_l9 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob9/regulator-pm-humu-l9";
|
|
L10B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob10/regulator-pm-humu-l10";
|
|
pm_humu_l10 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob10/regulator-pm-humu-l10";
|
|
L11B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob11/regulator-pm-humu-l11";
|
|
pm_humu_l11 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob11/regulator-pm-humu-l11";
|
|
L12B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob12/regulator-pm-humu-l12";
|
|
pm_humu_l12 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob12/regulator-pm-humu-l12";
|
|
L13B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob13/regulator-pm-humu-l13";
|
|
pm_humu_l13 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob13/regulator-pm-humu-l13";
|
|
L14B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob14/regulator-pm-humu-l14";
|
|
pm_humu_l14 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob14/regulator-pm-humu-l14";
|
|
L15B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob15/regulator-pm-humu-l15";
|
|
pm_humu_l15 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob15/regulator-pm-humu-l15";
|
|
L16B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob16/regulator-pm-humu-l16";
|
|
pm_humu_l16 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob16/regulator-pm-humu-l16";
|
|
L17B = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob17/regulator-pm-humu-l17";
|
|
pm_humu_l17 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldob17/regulator-pm-humu-l17";
|
|
BOB1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-bobb1/regulator-pm-humu-bob1";
|
|
pm_humu_bob1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-bobb1/regulator-pm-humu-bob1";
|
|
BOB2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-bobb2/regulator-pm-humu-bob2";
|
|
pm_humu_bob2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-bobb2/regulator-pm-humu-bob2";
|
|
S1C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc1/regulator-pm-v6c-s1";
|
|
pm_v6c_s1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc1/regulator-pm-v6c-s1";
|
|
S2C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc2/regulator-pm-v6c-s2";
|
|
pm_v6c_s2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc2/regulator-pm-v6c-s2";
|
|
S3C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc3/regulator-pm-v6c-s3";
|
|
pm_v6c_s3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc3/regulator-pm-v6c-s3";
|
|
S4C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc4/regulator-pm-v6c-s4";
|
|
pm_v6c_s4 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc4/regulator-pm-v6c-s4";
|
|
S5C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc5/regulator-pm-v6c-s5";
|
|
pm_v6c_s5 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc5/regulator-pm-v6c-s5";
|
|
S6C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc6/regulator-pm-v6c-s6";
|
|
pm_v6c_s6 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpc6/regulator-pm-v6c-s6";
|
|
L1C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoc1/regulator-pm-v6c-l1";
|
|
pm_v6c_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoc1/regulator-pm-v6c-l1";
|
|
L2C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoc2/regulator-pm-v6c-l2";
|
|
pm_v6c_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoc2/regulator-pm-v6c-l2";
|
|
L3C = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoc3/regulator-pm-v6c-l3";
|
|
pm_v6c_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoc3/regulator-pm-v6c-l3";
|
|
L1D = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldod1/regulator-pm-v6d-l1";
|
|
pm_v6d_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldod1/regulator-pm-v6d-l1";
|
|
L3D = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldod3/regulator-pm-v6d-l3";
|
|
pm_v6d_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldod3/regulator-pm-v6d-l3";
|
|
L1E = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoe1/regulator-pm-v6e-l1";
|
|
pm_v6e_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoe1/regulator-pm-v6e-l1";
|
|
L2E = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoe2/regulator-pm-v6e-l2";
|
|
pm_v6e_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoe2/regulator-pm-v6e-l2";
|
|
L3E = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoe3/regulator-pm-v6e-l3";
|
|
pm_v6e_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoe3/regulator-pm-v6e-l3";
|
|
S3G = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpg3/regulator-pm-v6g-s3";
|
|
pm_v6g_s3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpg3/regulator-pm-v6g-s3";
|
|
L1G = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldog1/regulator-pm-v6g-l1";
|
|
pm_v6g_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldog1/regulator-pm-v6g-l1";
|
|
L2G = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldog2/regulator-pm-v6g-l2";
|
|
pm_v6g_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldog2/regulator-pm-v6g-l2";
|
|
L3G = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldog3/regulator-pm-v6g-l3";
|
|
pm_v6g_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldog3/regulator-pm-v6g-l3";
|
|
S4I = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpi4/regulator-pm-v8-s4";
|
|
pm_v8_s4 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpi4/regulator-pm-v8-s4";
|
|
S5I = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpi5/regulator-pm-v8-s5";
|
|
pm_v8_s5 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-smpi5/regulator-pm-v8-s5";
|
|
L1I = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi1/regulator-pm-v8-l1";
|
|
pm_v8_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi1/regulator-pm-v8-l1";
|
|
L1I_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi1/regulator-pm-v8-l1-ao";
|
|
pm_v8_l1_ao = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi1/regulator-pm-v8-l1-ao";
|
|
L2I = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi2/regulator-pm-v8-l2";
|
|
pm_v8_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi2/regulator-pm-v8-l2";
|
|
L3I = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi3/regulator-pm-v8-l3";
|
|
pm_v8_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi3/regulator-pm-v8-l3";
|
|
L3I_AO = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi3/regulator-pm-v8-l3-ao";
|
|
pm_v8_l3_ao = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldoi3/regulator-pm-v8-l3-ao";
|
|
L1K = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok1/regulator-pmr-nalojr-l1";
|
|
pmr_nalojr_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok1/regulator-pmr-nalojr-l1";
|
|
L2K = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok2/regulator-pmr-nalojr-l2";
|
|
pmr_nalojr_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok2/regulator-pmr-nalojr-l2";
|
|
L3K = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok3/regulator-pmr-nalojr-l3";
|
|
pmr_nalojr_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok3/regulator-pmr-nalojr-l3";
|
|
L4K = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok4/regulator-pmr-nalojr-l4";
|
|
pmr_nalojr_l4 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok4/regulator-pmr-nalojr-l4";
|
|
L5K = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok5/regulator-pmr-nalojr-l5";
|
|
pmr_nalojr_l5 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok5/regulator-pmr-nalojr-l5";
|
|
L6K = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok6/regulator-pmr-nalojr-l6";
|
|
pmr_nalojr_l6 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok6/regulator-pmr-nalojr-l6";
|
|
L7K = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok7/regulator-pmr-nalojr-l7";
|
|
pmr_nalojr_l7 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldok7/regulator-pmr-nalojr-l7";
|
|
L1M = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom1/regulator-pm8010m-l1";
|
|
pm8010m_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom1/regulator-pm8010m-l1";
|
|
L2M = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom2/regulator-pm8010m-l2";
|
|
pm8010m_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom2/regulator-pm8010m-l2";
|
|
L3M = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom3/regulator-pm8010m-l3";
|
|
pm8010m_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom3/regulator-pm8010m-l3";
|
|
L4M = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom4/regulator-pm8010m-l4";
|
|
pm8010m_l4 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom4/regulator-pm8010m-l4";
|
|
L5M = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom5/regulator-pm8010m-l5";
|
|
pm8010m_l5 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom5/regulator-pm8010m-l5";
|
|
L6M = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom6/regulator-pm8010m-l6";
|
|
pm8010m_l6 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom6/regulator-pm8010m-l6";
|
|
L7M = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom7/regulator-pm8010m-l7";
|
|
pm8010m_l7 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldom7/regulator-pm8010m-l7";
|
|
L1N = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon1/regulator-pm8010n-l1";
|
|
pm8010n_l1 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon1/regulator-pm8010n-l1";
|
|
L2N = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon2/regulator-pm8010n-l2";
|
|
pm8010n_l2 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon2/regulator-pm8010n-l2";
|
|
L3N = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon3/regulator-pm8010n-l3";
|
|
pm8010n_l3 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon3/regulator-pm8010n-l3";
|
|
L4N = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon4/regulator-pm8010n-l4";
|
|
pm8010n_l4 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon4/regulator-pm8010n-l4";
|
|
L5N = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon5/regulator-pm8010n-l5";
|
|
pm8010n_l5 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon5/regulator-pm8010n-l5";
|
|
L6N = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon6/regulator-pm8010n-l6";
|
|
pm8010n_l6 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon6/regulator-pm8010n-l6";
|
|
L7N = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon7/regulator-pm8010n-l7";
|
|
pm8010n_l7 = "/soc/rsc@17a00000/drv@2/rpmh-regulator-ldon7/regulator-pm8010n-l7";
|
|
cam_rsc = "/soc/rsc@add9000";
|
|
cam_rsc_drv0 = "/soc/rsc@add9000/drv@0";
|
|
cam_bcm_voter0 = "/soc/rsc@add9000/drv@0/bcm_voter";
|
|
cam_rsc_drv1 = "/soc/rsc@add9000/drv@1";
|
|
cam_bcm_voter1 = "/soc/rsc@add9000/drv@1/bcm_voter";
|
|
cam_rsc_drv2 = "/soc/rsc@add9000/drv@2";
|
|
cam_bcm_voter2 = "/soc/rsc@add9000/drv@2/bcm_voter";
|
|
disp_rsc = "/soc/rsc@af20000";
|
|
disp_rsc_drv0 = "/soc/rsc@af20000/drv@0";
|
|
disp_bcm_voter = "/soc/rsc@af20000/drv@0/bcm_voter";
|
|
cam_crm = "/soc/crm@add7000";
|
|
pcie_crm = "/soc/crm@1d01000";
|
|
spss_pas = "/soc/remoteproc-spss@1880000";
|
|
spss_utils = "/soc/qcom,spss_utils";
|
|
xo_board = "/soc/clocks/xo_board";
|
|
sleep_clk = "/soc/clocks/sleep_clk";
|
|
pcie_0_pipe_clk = "/soc/clocks/pcie_0_pipe_clk";
|
|
pcie_1_phy_aux_clk = "/soc/clocks/pcie_1_phy_aux_clk";
|
|
pcie_1_pipe_clk = "/soc/clocks/pcie_1_pipe_clk";
|
|
ufs_phy_rx_symbol_0_clk = "/soc/clocks/ufs_phy_rx_symbol_0_clk";
|
|
ufs_phy_rx_symbol_1_clk = "/soc/clocks/ufs_phy_rx_symbol_1_clk";
|
|
ufs_phy_tx_symbol_0_clk = "/soc/clocks/ufs_phy_tx_symbol_0_clk";
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk = "/soc/clocks/usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
camcc_crmc = "/soc/syscon@adda000";
|
|
camcc = "/soc/clock-controller@ade0000";
|
|
dispcc = "/soc/clock-controller@af00000";
|
|
gcc = "/soc/clock-controller@100000";
|
|
gpucc = "/soc/clock-controller@3d90000";
|
|
tcsrcc = "/soc/clock-controller@1f40000";
|
|
videocc = "/soc/clock-controller@aaf0000";
|
|
apsscc = "/soc/syscon@17a80000";
|
|
mccc = "/soc/syscon@240ba000";
|
|
debugcc = "/soc/qcom,cc-debug";
|
|
cpufreq_hw = "/soc/qcom,cpufreq-hw";
|
|
sdhc2_opp_table = "/soc/sdhc2-opp-table";
|
|
sdhc_2 = "/soc/sdhci@8804000";
|
|
ufsphy_mem = "/soc/ufsphy_mem@1d80000";
|
|
ice_cfg = "/soc/shared_ice";
|
|
ufshc_mem = "/soc/ufshc@1d84000";
|
|
thermal_zones = "/soc/thermal-zones";
|
|
cpu2_emerg0 = "/soc/thermal-zones/cpu-2-0-0/trips/cpu2-emerg0-cfg";
|
|
cpu2_emerg0_1 = "/soc/thermal-zones/cpu-2-0-0/trips/cpu2-emerg0-1-cfg";
|
|
cpu2_emerg1 = "/soc/thermal-zones/cpu-2-0-1/trips/cpu2-emerg1-cfg";
|
|
cpu2_emerg1_1 = "/soc/thermal-zones/cpu-2-0-1/trips/cpu2-emerg1-1-cfg";
|
|
cpu3_emerg0 = "/soc/thermal-zones/cpu-2-1-0/trips/cpu3-emerg0-cfg";
|
|
cpu3_emerg0_1 = "/soc/thermal-zones/cpu-2-1-0/trips/cpu3-emerg0-1-cfg";
|
|
cpu3_emerg1 = "/soc/thermal-zones/cpu-2-1-1/trips/cpu3-emerg1-cfg";
|
|
cpu3_emerg1_1 = "/soc/thermal-zones/cpu-2-1-1/trips/cpu3-emerg1-1-cfg";
|
|
cpu4_emerg0 = "/soc/thermal-zones/cpu-2-2-0/trips/cpu4-emerg0-cfg";
|
|
cpu4_emerg0_1 = "/soc/thermal-zones/cpu-2-2-0/trips/cpu4-emerg0-1-cfg";
|
|
cpu4_emerg1 = "/soc/thermal-zones/cpu-2-2-1/trips/cpu4-emerg1-cfg";
|
|
cpu4_emerg1_1 = "/soc/thermal-zones/cpu-2-2-1/trips/cpu4-emerg1-1-cfg";
|
|
cpu5_emerg0 = "/soc/thermal-zones/cpu-1-0-0/trips/cpu5-emerg0-cfg";
|
|
cpu5_emerg0_1 = "/soc/thermal-zones/cpu-1-0-0/trips/cpu5-emerg0-1-cfg";
|
|
cpu5_emerg1 = "/soc/thermal-zones/cpu-1-0-1/trips/cpu5-emerg1-cfg";
|
|
cpu5_emerg1_1 = "/soc/thermal-zones/cpu-1-0-1/trips/cpu5-emerg1-1-cfg";
|
|
cpu6_emerg0 = "/soc/thermal-zones/cpu-1-1-0/trips/cpu6-emerg0-cfg";
|
|
cpu6_emerg0_1 = "/soc/thermal-zones/cpu-1-1-0/trips/cpu6-emerg0-1-cfg";
|
|
cpu6_emerg1 = "/soc/thermal-zones/cpu-1-1-1/trips/cpu6-emerg1-cfg";
|
|
cpu6_emerg1_1 = "/soc/thermal-zones/cpu-1-1-1/trips/cpu6-emerg1-1-cfg";
|
|
cpu7_emerg0 = "/soc/thermal-zones/cpu-1-2-0/trips/cpu7-emerg0-cfg";
|
|
cpu7_emerg0_1 = "/soc/thermal-zones/cpu-1-2-0/trips/cpu7-emerg0-1-cfg";
|
|
cpu7_mon_trip1 = "/soc/thermal-zones/cpu-1-2-1/trips/cpu7-mon-trip";
|
|
cpu7_emerg1 = "/soc/thermal-zones/cpu-1-2-1/trips/cpu7-emerg1-cfg";
|
|
cpu7_emerg1_1 = "/soc/thermal-zones/cpu-1-2-1/trips/cpu7-emerg1-1-cfg";
|
|
cpu7_emerg2 = "/soc/thermal-zones/cpu-1-2-2/trips/cpu7-emerg2-cfg";
|
|
cpu7_emerg2_1 = "/soc/thermal-zones/cpu-1-2-2/trips/cpu7-emerg2-1-cfg";
|
|
cpu0_emerg = "/soc/thermal-zones/cpu-0-0-0/trips/cpu0-emerg-cfg";
|
|
cpu0_emerg1 = "/soc/thermal-zones/cpu-0-0-0/trips/cpu0-emerg1-cfg";
|
|
cpu1_emerg = "/soc/thermal-zones/cpu-0-1-0/trips/cpu1-emerg-cfg";
|
|
cpu1_emerg1 = "/soc/thermal-zones/cpu-0-1-0/trips/cpu1-emerg1-cfg";
|
|
ddr_config0 = "/soc/thermal-zones/ddr/trips/ddr0-config";
|
|
gpu0_tj_cfg = "/soc/thermal-zones/gpuss-0/trips/tj_cfg";
|
|
gpu1_tj_cfg = "/soc/thermal-zones/gpuss-1/trips/tj_cfg";
|
|
gpu2_tj_cfg = "/soc/thermal-zones/gpuss-2/trips/tj_cfg";
|
|
gpu3_tj_cfg = "/soc/thermal-zones/gpuss-3/trips/tj_cfg";
|
|
gpu4_tj_cfg = "/soc/thermal-zones/gpuss-4/trips/tj_cfg";
|
|
gpu5_tj_cfg = "/soc/thermal-zones/gpuss-5/trips/tj_cfg";
|
|
gpu6_tj_cfg = "/soc/thermal-zones/gpuss-6/trips/tj_cfg";
|
|
gpu7_tj_cfg = "/soc/thermal-zones/gpuss-7/trips/tj_cfg";
|
|
mdmss0_config0 = "/soc/thermal-zones/mdmss-0/trips/mdmss0-config0";
|
|
mdmss0_config1 = "/soc/thermal-zones/mdmss-0/trips/mdmss0-config1";
|
|
mdmss1_config0 = "/soc/thermal-zones/mdmss-1/trips/mdmss1-config0";
|
|
mdmss1_config1 = "/soc/thermal-zones/mdmss-1/trips/mdmss1-config1";
|
|
mdmss2_config0 = "/soc/thermal-zones/mdmss-2/trips/mdmss2-config0";
|
|
mdmss2_config1 = "/soc/thermal-zones/mdmss-2/trips/mdmss2-config1";
|
|
mdmss3_config0 = "/soc/thermal-zones/mdmss-3/trips/mdmss3-config0";
|
|
mdmss3_config1 = "/soc/thermal-zones/mdmss-3/trips/mdmss3-config1";
|
|
spmi_bus = "/soc/qcom,spmi@c42d000";
|
|
spmi0_bus = "/soc/qcom,spmi@c42d000";
|
|
spmi1_bus = "/soc/qcom,spmi@c432000";
|
|
spmi0_debug_bus = "/soc/qcom,spmi-debug@10b14000";
|
|
tcsr_mutex_block = "/soc/syscon@1f40000";
|
|
tcsr_mutex = "/soc/hwlock";
|
|
tcsr = "/soc/syscon@1fc0000";
|
|
qcom_tzlog = "/soc/tz-log@14680720";
|
|
qcom_qseecom = "/soc/qseecom@c1700000";
|
|
qcom_cedev = "/soc/qcedev@1de0000";
|
|
qcom_rng = "/soc/qrng@10c3000";
|
|
eud = "/soc/qcom,msm-eud@88e0000";
|
|
ipcc_mproc = "/soc/qcom,ipcc@406000";
|
|
aoss_qmp = "/soc/power-controller@c300000";
|
|
qmp_aop = "/soc/qcom,qmp-aop";
|
|
qmp_tme = "/soc/qcom,qmp-tme";
|
|
adsp_smp2p_out = "/soc/qcom,smp2p-adsp/master-kernel";
|
|
adsp_smp2p_in = "/soc/qcom,smp2p-adsp/slave-kernel";
|
|
sleepstate_smp2p_out = "/soc/qcom,smp2p-adsp/sleepstate-out";
|
|
sleepstate_smp2p_in = "/soc/qcom,smp2p-adsp/qcom,sleepstate-in";
|
|
smp2p_rdbg2_out = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-out";
|
|
smp2p_rdbg2_in = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-in";
|
|
cdsp_smp2p_out = "/soc/qcom,smp2p-cdsp/master-kernel";
|
|
cdsp_smp2p_in = "/soc/qcom,smp2p-cdsp/slave-kernel";
|
|
smp2p_rdbg5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-out";
|
|
smp2p_rdbg5_in = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-in";
|
|
modem_smp2p_out = "/soc/qcom,smp2p-modem/master-kernel";
|
|
modem_smp2p_in = "/soc/qcom,smp2p-modem/slave-kernel";
|
|
smp2p_ipa_1_out = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-out";
|
|
smp2p_ipa_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-in";
|
|
adsp_sleepmon = "/soc/adsp-sleepmon";
|
|
adsp_pas = "/soc/remoteproc-adsp@03000000";
|
|
glink_edge = "/soc/remoteproc-adsp@03000000/glink-edge";
|
|
modem_pas = "/soc/remoteproc-mss@04080000";
|
|
cdsp_pas = "/soc/remoteproc-cdsp@32300000";
|
|
msm_cdsp_rm = "/soc/remoteproc-cdsp@32300000/glink-edge/qcom,msm_cdsprm_rpmsg/qcom,msm_cdsp_rm";
|
|
trust_ui_vm_vblk0_ring = "/soc/trust_ui_vm_vblk0_ring";
|
|
trust_ui_vm_vblk1_ring = "/soc/trust_ui_vm_vblk1_ring";
|
|
trust_ui_vm_swiotlb = "/soc/trust_ui_vm_swiotlb";
|
|
trust_ui_vm = "/soc/qcom,trust_ui_vm";
|
|
trust_ui_vm_virt_be0 = "/soc/trust_ui_vm_virt_be0@11";
|
|
trust_ui_vm_virt_be1 = "/soc/trust_ui_vm_virt_be1@10";
|
|
gh_secure_vm_loader0 = "/soc/gh-secure-vm-loader@0";
|
|
battery_charger = "/soc/qcom,pmic_glink/qcom,battery_charger";
|
|
ucsi = "/soc/qcom,pmic_glink/qcom,ucsi";
|
|
altmode = "/soc/qcom,pmic_glink/qcom,altmode";
|
|
pmic_glink_debug = "/soc/qcom,pmic_glink_log/qcom,pmic_glink_debug";
|
|
pm8550b_glink_debug = "/soc/qcom,pmic_glink_log/qcom,pmic_glink_debug/spmi@0/qcom,pm8550b-debug@7";
|
|
pmic_glink_adc = "/soc/qcom,pmic_glink_log/qcom,glink-adc";
|
|
msm_gpu = "/soc/qcom,kgsl-3d0@3d00000";
|
|
mmio_sram = "/soc/mmio-sram@17D09400";
|
|
cpu_scp_lpri = "/soc/mmio-sram@17D09400/scmi-shmem@0";
|
|
cpucp = "/soc/qcom,cpucp@17400000";
|
|
scmi = "/soc/qcom,scmi";
|
|
scmi_memlat = "/soc/qcom,scmi/protocol@80";
|
|
scmi_plh = "/soc/qcom,scmi/protocol@81";
|
|
scmi_pmu = "/soc/qcom,scmi/protocol@86";
|
|
scmi_c1dcvs = "/soc/qcom,scmi/protocol@87";
|
|
cpucp_log = "/soc/qcom,cpucp_log@d8140000";
|
|
qcom_c1dcvs = "/soc/qcom,c1dcvs";
|
|
qcom_mpam = "/soc/qcom,mpam";
|
|
qcom_dynpf = "/soc/qcom,dynpf";
|
|
qcom_cpufreq_stats = "/soc/qcom,cpufreq_stats";
|
|
llcc_pmu = "/soc/llcc-pmu@24095000";
|
|
qcom_pmu = "/soc/qcom,pmu";
|
|
ddr_freq_table = "/soc/ddr-freq-table";
|
|
llcc_freq_table = "/soc/llcc-freq-table";
|
|
ddrqos_freq_table = "/soc/ddrqos-freq-table";
|
|
qcom_dcvs = "/soc/qcom,dcvs";
|
|
qcom_l3_dcvs_hw = "/soc/qcom,dcvs/l3";
|
|
l3_dcvs_sp = "/soc/qcom,dcvs/l3/sp";
|
|
qcom_ddr_dcvs_hw = "/soc/qcom,dcvs/ddr";
|
|
ddr_dcvs_sp = "/soc/qcom,dcvs/ddr/sp";
|
|
ddr_dcvs_fp = "/soc/qcom,dcvs/ddr/fp";
|
|
qcom_llcc_dcvs_hw = "/soc/qcom,dcvs/llcc";
|
|
llcc_dcvs_sp = "/soc/qcom,dcvs/llcc/sp";
|
|
llcc_dcvs_fp = "/soc/qcom,dcvs/llcc/fp";
|
|
qcom_ddrqos_dcvs_hw = "/soc/qcom,dcvs/ddrqos";
|
|
ddrqos_dcvs_sp = "/soc/qcom,dcvs/ddrqos/sp";
|
|
qcom_memlat = "/soc/qcom,memlat";
|
|
ddrqos_gold_lat = "/soc/qcom,memlat/ddrqos/gold";
|
|
ddrqos_prime_lat = "/soc/qcom,memlat/ddrqos/prime";
|
|
ddrqos_prime_latfloor = "/soc/qcom,memlat/ddrqos/prime-latfloor";
|
|
qcom_llcc_l3_vote = "/soc/qcom,llcc-l3-vote";
|
|
bwmon_llcc = "/soc/qcom,bwmon-llcc@240B7300";
|
|
bwmon_ddr = "/soc/qcom,bwmon-ddr@24091000";
|
|
qfprom = "/soc/qfprom@221c2000";
|
|
gpu_speed_bin = "/soc/qfprom@221c2000/gpu_speed_bin@9b";
|
|
ipcc_self_ping_apss = "/soc/ipcc-self-ping-apss";
|
|
ipcc_self_ping_cdsp = "/soc/ipcc-self-ping-cdsp";
|
|
ipcc_self_ping_adsp = "/soc/ipcc-self-ping-adsp";
|
|
ipcc_self_ping_slpi = "/soc/ipcc-self-ping-slpi";
|
|
cam_cc_bps_gdsc = "/soc/qcom,gdsc@adf0004";
|
|
cam_cc_camss_top_gdsc = "/soc/qcom,gdsc@add5004";
|
|
cam_cc_ife_0_gdsc = "/soc/qcom,gdsc@adf1004";
|
|
cam_cc_ife_1_gdsc = "/soc/qcom,gdsc@adf2004";
|
|
cam_cc_ife_2_gdsc = "/soc/qcom,gdsc@adf2054";
|
|
cam_cc_ipe_0_gdsc = "/soc/qcom,gdsc@adf0080";
|
|
cam_cc_sbi_gdsc = "/soc/qcom,gdsc@adf00e4";
|
|
cam_cc_sfe_0_gdsc = "/soc/qcom,gdsc@adf3058";
|
|
cam_cc_sfe_1_gdsc = "/soc/qcom,gdsc@adf30a8";
|
|
cam_cc_sfe_2_gdsc = "/soc/qcom,gdsc@adf30f8";
|
|
cam_cc_titan_top_gdsc = "/soc/qcom,gdsc@adf32bc";
|
|
disp_cc_mdss_core_gdsc = "/soc/qcom,gdsc@af09000";
|
|
mdss_0_disp_cc_mdss_core_gdsc = "/soc/qcom,gdsc@af09000";
|
|
disp_cc_mdss_core_int2_gdsc = "/soc/qcom,gdsc@af0b000";
|
|
mdss_0_disp_cc_mdss_core_int2_gdsc = "/soc/qcom,gdsc@af0b000";
|
|
mdss_1_disp_cc_mdss_core_gdsc = "/soc/qcom,gdsc@a909000";
|
|
mdss_1_disp_cc_mdss_core_int2_gdsc = "/soc/qcom,gdsc@a90b000";
|
|
gcc_apcs_gdsc_vote_ctrl = "/soc/syscon@15214c";
|
|
gcc_apcs_gdsc_sleep_ctrl = "/soc/syscon@152150";
|
|
apss_ubwcp_pwr_ctrl = "/soc/qcom,gdsc@17891000";
|
|
gcc_pcie_0_gdsc = "/soc/qcom,gdsc@16b004";
|
|
gcc_pcie_0_phy_gdsc = "/soc/qcom,gdsc@16c000";
|
|
gcc_pcie_1_gdsc = "/soc/qcom,gdsc@18d004";
|
|
gcc_pcie_1_phy_gdsc = "/soc/qcom,gdsc@18e000";
|
|
gcc_pcie_2_gdsc = "/soc/qcom,gdsc@117004";
|
|
gcc_pcie_2_phy_gdsc = "/soc/qcom,gdsc@1a3000";
|
|
gcc_ufs_mem_phy_gdsc = "/soc/qcom,gdsc@19e000";
|
|
gcc_ufs_phy_gdsc = "/soc/qcom,gdsc@177004";
|
|
gcc_usb30_prim_gdsc = "/soc/qcom,gdsc@139004";
|
|
gcc_usb3_phy_gdsc = "/soc/qcom,gdsc@150018";
|
|
gcc_usb30_sec_gdsc = "/soc/qcom,gdsc@1a5004";
|
|
gcc_usb3_sec_phy_gdsc = "/soc/qcom,gdsc@1a600c";
|
|
gpu_cc_cx_gdsc_hw_ctrl = "/soc/syscon@3d99168";
|
|
gpu_cc_cx_gdsc = "/soc/qcom,gdsc@3d99108";
|
|
gpu_cc_gx_domain_addr = "/soc/syscon@3d99504";
|
|
gpu_cc_gx_sw_reset = "/soc/syscon@3d99058";
|
|
gpu_cc_gx_acd_reset = "/soc/syscon@3d99358";
|
|
gpu_cc_gx_acd_iroot_reset = "/soc/syscon@3d9958c";
|
|
gpu_cc_gx_gdsc = "/soc/qcom,gdsc@3d9905c";
|
|
gx_clkctl_gx_gdsc = "/soc/qcom,gdsc@3d68024";
|
|
video_cc_mvs0_gdsc = "/soc/qcom,gdsc@aaf80a4";
|
|
video_cc_mvs0c_gdsc = "/soc/qcom,gdsc@aaf804c";
|
|
video_cc_mvs1_gdsc = "/soc/qcom,gdsc@aaf80cc";
|
|
video_cc_mvs1c_gdsc = "/soc/qcom,gdsc@aaf8078";
|
|
kgsl_smmu = "/soc/kgsl-smmu@3da0000";
|
|
gpu_qtb = "/soc/kgsl-smmu@3da0000/gpu_qtb@3de8000";
|
|
ubwcp_smmu = "/soc/ubwcp-smmu@179a0000";
|
|
ubwcp_qtb = "/soc/ubwcp-smmu@179a0000/ubwcp_qtb@179e8000";
|
|
apps_smmu = "/soc/apps-smmu@15000000";
|
|
anoc_1_qtb = "/soc/apps-smmu@15000000/anoc_1_qtb@16f1000";
|
|
anoc_2_qtb = "/soc/apps-smmu@15000000/anoc_2_qtb@171a000";
|
|
cam_hf_qtb = "/soc/apps-smmu@15000000/cam_hf_qtb@17d2000";
|
|
nsp_qtb = "/soc/apps-smmu@15000000/nsp_qtb@7d3000";
|
|
lpass_qtb = "/soc/apps-smmu@15000000/lpass_qtb@7b3000";
|
|
pcie_qtb = "/soc/apps-smmu@15000000/pcie_qtb@16cd000";
|
|
sf_qtb = "/soc/apps-smmu@15000000/sf_qtb@17d1000";
|
|
mdp_hf_qtb = "/soc/apps-smmu@15000000/mdp_hf_qtb@17d0000";
|
|
dcc = "/soc/dcc_v2@100ff000";
|
|
gpi_dma1 = "/soc/qcom,gpi-dma@a00000";
|
|
qupv3_1 = "/soc/qcom,qupv3_1_geni_se@ac0000";
|
|
qupv3_se0_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a80000";
|
|
qupv3_se0_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a80000";
|
|
i3c0 = "/soc/qcom,qupv3_1_geni_se@ac0000/i3c-master@a80000";
|
|
qupv3_se1_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a84000";
|
|
qupv3_se1_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a84000";
|
|
qupv3_se2_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a88000";
|
|
qupv3_se2_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a88000";
|
|
qupv3_se3_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a8c000";
|
|
wcd_usbss = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a8c000/wcd939x_i2c@e";
|
|
qupv3_se3_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a8c000";
|
|
qupv3_se4_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a90000";
|
|
qupv3_se4_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a90000";
|
|
i3c1 = "/soc/qcom,qupv3_1_geni_se@ac0000/i3c-master@a90000";
|
|
qupv3_se5_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a94000";
|
|
qupv3_se5_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a94000";
|
|
qupv3_se6_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a98000";
|
|
qupv3_se6_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a98000";
|
|
qupv3_se7_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a9c000";
|
|
qupv3_se7_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a9c000";
|
|
gpi_dma2 = "/soc/qcom,gpi-dma@800000";
|
|
qupv3_2 = "/soc/qcom,qupv3_2_geni_se@8c0000";
|
|
qupv3_se8_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@880000";
|
|
qupv3_se8_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@880000";
|
|
i3c2 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@880000";
|
|
qupv3_se9_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@884000";
|
|
qupv3_se9_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@884000";
|
|
qupv3_se10_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@888000";
|
|
qupv3_se10_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@888000";
|
|
i3c3 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@888000";
|
|
i3c4 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@88c000";
|
|
qupv3_se11_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@88c000";
|
|
qupv3_se11_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@88c000";
|
|
qupv3_se12_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@890000";
|
|
qupv3_se12_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@890000";
|
|
qupv3_se13_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@894000";
|
|
qupv3_se13_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@894000";
|
|
qupv3_se13_q2spi = "/soc/qcom,qupv3_2_geni_se@8c0000/q2spi@894000";
|
|
qupv3_se14_4uart = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000";
|
|
qupv3_se15_2uart = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000";
|
|
qupv3_0_i2c_hub = "/soc/qcom,qupv3_i2c_geni_se@9c0000";
|
|
qupv3_hub_i2c0 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@980000";
|
|
qupv3_hub_i2c1 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@984000";
|
|
qupv3_hub_i2c2 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@988000";
|
|
qupv3_hub_i2c3 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@98c000";
|
|
qupv3_hub_i2c4 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@990000";
|
|
qupv3_hub_i2c5 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@994000";
|
|
qupv3_hub_i2c6 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@998000";
|
|
qupv3_hub_i2c7 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@99c000";
|
|
qupv3_hub_i2c8 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@9a0000";
|
|
qupv3_hub_i2c9 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@9a4000";
|
|
usb0 = "/soc/ssusb@a600000";
|
|
eusb2_phy0 = "/soc/hsphy@88e3000";
|
|
usb_qmp_dp_phy = "/soc/ssphy@88e8000";
|
|
stm = "/soc/stm@10002000";
|
|
stm_out_funnel_in0 = "/soc/stm@10002000/out-ports/port/endpoint";
|
|
audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port/endpoint";
|
|
tpdm_ddr_lpi = "/soc/tpdm@10b30000";
|
|
tpdm_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint";
|
|
tpdm_lpass_lpi = "/soc/tpdm@10b46000";
|
|
tpdm_lpass_lpi_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b46000/out-ports/port/endpoint";
|
|
lpass_stm = "/soc/lpass_stm";
|
|
lpass_stm_out_funnel_lpass_lpi_1 = "/soc/lpass_stm/out-ports/port/endpoint";
|
|
funnel_lpass_lpi_1 = "/soc/funnel@10b50000";
|
|
funnel_lpass_lpi_1_in_lpass_stm = "/soc/funnel@10b50000/in-ports/port@0/endpoint";
|
|
funnel_lpass_lpi_1_in_tpdm_lpass_lpi = "/soc/funnel@10b50000/in-ports/port@1/endpoint";
|
|
funnel_lpass_lpi_1_out_funnel_lpass_lpi_0 = "/soc/funnel@10b50000/out-ports/port/endpoint";
|
|
funnel_lpass_lpi_0 = "/soc/funnel@10b44000";
|
|
funnel_lpass_lpi_in_audio_etm0 = "/soc/funnel@10b44000/in-ports/port@0/endpoint";
|
|
funnel_lpass_lpi_0_in_funnel_lpass_lpi_1 = "/soc/funnel@10b44000/in-ports/port@7/endpoint";
|
|
funnel_lpass_lpi_out_funnel_aoss = "/soc/funnel@10b44000/out-ports/port/endpoint";
|
|
tpdm_swao_prio0 = "/soc/tpdm@10b09000";
|
|
tpdm_swao_prio0_out_tpda_aoss = "/soc/tpdm@10b09000/out-ports/port/endpoint";
|
|
tpdm_swao_prio1 = "/soc/tpdm@10b0a000";
|
|
tpdm_swao_prio1_out_tpda_aoss = "/soc/tpdm@10b0a000/out-ports/port/endpoint";
|
|
tpdm_swao_prio2 = "/soc/tpdm@10b0b000";
|
|
tpdm_swao_prio2_out_tpda_aoss = "/soc/tpdm@10b0b000/out-ports/port/endpoint";
|
|
tpdm_swao_prio3 = "/soc/tpdm@10b0c000";
|
|
tpdm_swao_prio3_out_tpda_aoss = "/soc/tpdm@10b0c000/out-ports/port/endpoint";
|
|
tpdm_swao = "/soc/tpdm@10b0d000";
|
|
tpdm_swao_out_tpda_aoss = "/soc/tpdm@10b0d000/out-ports/port/endpoint";
|
|
tpdm_lpass = "/soc/tpdm@10844000";
|
|
tpdm_lpass_out_funnel_lpass = "/soc/tpdm@10844000/out-ports/port/endpoint";
|
|
tpdm_ddr_ch02 = "/soc/tpdm@10d20000";
|
|
tpdm_ddr_ch02_out_funnel_ddr_ch02 = "/soc/tpdm@10d20000/out-ports/port/endpoint";
|
|
tpdm_ddr_ch13 = "/soc/tpdm@10d30000";
|
|
tpdm_ddr_ch13_out_funnel_ddr_ch13 = "/soc/tpdm@10d30000/out-ports/port/endpoint";
|
|
tpdm_ddr0 = "/soc/tpdm@10d00000";
|
|
tpdm_ddr0_out_funnel_ddr_dl0 = "/soc/tpdm@10d00000/out-ports/port/endpoint";
|
|
tpdm_ddr1 = "/soc/tpdm@10d01000";
|
|
tpdm_ddr1_out_funnel_ddr_dl0 = "/soc/tpdm@10d01000/out-ports/port/endpoint";
|
|
tpdm_video = "/soc/tpdm@10830000";
|
|
tpdm_video_out_funnel_video = "/soc/tpdm@10830000/out-ports/port/endpoint";
|
|
tpdm_mdss = "/soc/tpdm@10c60000";
|
|
tpdm_mdss_out_funnel_multimedia = "/soc/tpdm@10c60000/out-ports/port/endpoint";
|
|
tpdm_dl_mm = "/soc/tpdm@10c08000";
|
|
tpdm_dl_mm_out_funnel_multimedia = "/soc/tpdm@10c08000/out-ports/port/endpoint";
|
|
tpdm_rdpm0 = "/soc/tpdm@10c38000";
|
|
tpdm_rdpm0_out_funnel_dl_west = "/soc/tpdm@10c38000/out-ports/port/endpoint";
|
|
tpdm_rdpm1 = "/soc/tpdm@10c39000";
|
|
tpdm_rdpm1_out_funnel_dl_west = "/soc/tpdm@10c39000/out-ports/port/endpoint";
|
|
tpdm_rdpm2 = "/soc/tpdm@10c3a000";
|
|
tpdm_rdpm2_out_funnel_dl_west = "/soc/tpdm@10c3a000/out-ports/port/endpoint";
|
|
tpdm_spare = "/soc/tpdm@10c3b000";
|
|
tpdm_spare_out_funnel_dl_west = "/soc/tpdm@10c3b000/out-ports/port/endpoint";
|
|
tpdm_gfx = "/soc/tpdm@10900000";
|
|
tpdm_gfx_out_funnel_gfx_dl = "/soc/tpdm@10900000/out-ports/port/endpoint";
|
|
tpdm_prng = "/soc/tpdm@10841000";
|
|
tpdm_prng_out_tpda_dl_center_21 = "/soc/tpdm@10841000/out-ports/port/endpoint";
|
|
tpdm_qm = "/soc/tpdm@109d0000";
|
|
tpdm_qm_out_tpda_dl_center_22 = "/soc/tpdm@109d0000/out-ports/port/endpoint";
|
|
tpdm_trace_noc = "/soc/tpdm@10ac0000";
|
|
tpdm_trace_noc_out_trace_noc = "/soc/tpdm@10ac0000/out-ports/port/endpoint";
|
|
tpdm_gcc = "/soc/tpdm@1082c000";
|
|
tpdm_gcc_out_tpda_dl_center_23 = "/soc/tpdm@1082c000/out-ports/port/endpoint";
|
|
tpdm_vsense = "/soc/tpdm@10840000";
|
|
tpdm_vsense_out_tpda_dl_center_24 = "/soc/tpdm@10840000/out-ports/port/endpoint";
|
|
tpdm_ipa = "/soc/tpdm@10c22000";
|
|
tpdm_ipa_out_tpda_dl_center_26 = "/soc/tpdm@10c22000/out-ports/port/endpoint";
|
|
tpdm_dl_ct = "/soc/tpdm@10c28000";
|
|
tpdm_dl_ct_out_tpda_dl_center_29 = "/soc/tpdm@10c28000/out-ports/port/endpoint";
|
|
tpdm_ipcc = "/soc/tpdm@10c29000";
|
|
tpdm_ipcc_out_tpda_dl_center_30 = "/soc/tpdm@10c29000/out-ports/port/endpoint";
|
|
tpdm_dcc = "/soc/tpdm@10003000";
|
|
tpdm_dcc_out_tpda_qdss = "/soc/tpdm@10003000/out-ports/port/endpoint";
|
|
tpdm_spdm = "/soc/tpdm@1000f000";
|
|
tpdm_spdm_out_tpda_qdss = "/soc/tpdm@1000f000/out-ports/port/endpoint";
|
|
tpdm_ddrss_llcc0 = "/soc/tpdm@10d40000";
|
|
tpdm_ddrss_llcc0_out_tpda_ddr = "/soc/tpdm@10d40000/out-ports/port/endpoint";
|
|
tpdm_ddrss_llcc1 = "/soc/tpdm@10d41000";
|
|
tpdm_ddrss_llcc1_out_tpda_ddr = "/soc/tpdm@10d41000/out-ports/port/endpoint";
|
|
tpdm_ddrss_llcc2 = "/soc/tpdm@10d42000";
|
|
tpdm_ddrss_llcc2_out_tpda_ddr = "/soc/tpdm@10d42000/out-ports/port/endpoint";
|
|
tpdm_ddrss_llcc3 = "/soc/tpdm@10d43000";
|
|
tpdm_ddrss_llcc3_out_tpda_ddr = "/soc/tpdm@10d43000/out-ports/port/endpoint";
|
|
tpdm_titan = "/soc/tpdm@10c16000";
|
|
tpdm_titan_out_tpda_titan = "/soc/tpdm@10c16000/out-ports/port/endpoint";
|
|
tpdm_tmess_prng = "/soc/tpdm@10cc9000";
|
|
tpdm_tmess_prng_out_tpda_tmess = "/soc/tpdm@10cc9000/out-ports/port/endpoint";
|
|
tpdm_tmess0 = "/soc/tpdm@10cc1000";
|
|
tpdm_tmess0_out_tpda_tmess = "/soc/tpdm@10cc1000/out-ports/port/endpoint";
|
|
tpdm_tmess1 = "/soc/tpdm@10cc0000";
|
|
tpdm_tmess1_out_tpda_tmess = "/soc/tpdm@10cc0000/out-ports/port/endpoint";
|
|
tpdm_turing = "/soc/tpdm@10980000";
|
|
tpdm_turing_out_tpda_turing = "/soc/tpdm@10980000/out-ports/port/endpoint";
|
|
tpdm_turing_llm = "/soc/tpdm@10981000";
|
|
tpdm_turing_llm_out_tpda_turing = "/soc/tpdm@10981000/out-ports/port/endpoint";
|
|
tpdm_turing_llm2 = "/soc/tpdm@10982000";
|
|
tpdm_turing_llm2_out_tpda_turing = "/soc/tpdm@10982000/out-ports/port/endpoint";
|
|
tpdm_dpm1 = "/soc/tpdm@10983000";
|
|
tpdm_dpm1_out_tpda_turing = "/soc/tpdm@10983000/out-ports/port/endpoint";
|
|
tpdm_dmp2 = "/soc/tpdm@10984000";
|
|
tpdm_dmp2_out_tpda_turing = "/soc/tpdm@10984000/out-ports/port/endpoint";
|
|
tpdm_sdcc4 = "/soc/tpdm@10c21000";
|
|
tpdm_sdcc4_out_tpda_dl_south = "/soc/tpdm@10c21000/out-ports/port/endpoint";
|
|
tpdm_ufs = "/soc/tpdm@10c23000";
|
|
tpdm_ufs_out_tpda_dl_south = "/soc/tpdm@10c23000/out-ports/port/endpoint";
|
|
tpdm_dl_south = "/soc/tpdm@109c0000";
|
|
tpdm_dl_south_out_tpda_dl_south = "/soc/tpdm@109c0000/out-ports/port/endpoint";
|
|
tpdm_llm_silver = "/soc/tpdm@138a0000";
|
|
tpdm_llm_silver_out_tpda_apss = "/soc/tpdm@138a0000/out-ports/port/endpoint";
|
|
tpdm_llm_gold = "/soc/tpdm@138b0000";
|
|
tpdm_llm_gold_out_tpda_apss = "/soc/tpdm@138b0000/out-ports/port/endpoint";
|
|
tpdm_llm_ext = "/soc/tpdm@138c0000";
|
|
tpdm_llm_ext_out_tpda_apss = "/soc/tpdm@138c0000/out-ports/port/endpoint";
|
|
tpdm_llm_gold_apc = "/soc/tpdm@13880000";
|
|
tpdm_llm_gold_apc_out_tpda_apss = "/soc/tpdm@13880000/out-ports/port/endpoint";
|
|
tpdm_apss_ubwcp = "/soc/tpdm@138d0000";
|
|
tpdm_apss_ubwcp_out_tpda_apss = "/soc/tpdm@138d0000/out-ports/port/endpoint";
|
|
tpdm_apss_apc2 = "/soc/tpdm@13890000";
|
|
tpdm_apss_apc2_out_tpda_apss = "/soc/tpdm@13890000/out-ports/port/endpoint";
|
|
tpdm_apss0 = "/soc/tpdm@13860000";
|
|
tpdm_apss_0_out_tpda_apss = "/soc/tpdm@13860000/out-ports/port/endpoint";
|
|
tpdm_apss1 = "/soc/tpdm@13861000";
|
|
tpdm_apss1_out_tpda_apss = "/soc/tpdm@13861000/out-ports/port/endpoint";
|
|
tpdm_apss2 = "/soc/tpdm@13862000";
|
|
tpdm_apss2_out_tpda_apss = "/soc/tpdm@13862000/out-ports/port/endpoint";
|
|
tpdm_modem0 = "/soc/tpdm@10800000";
|
|
tpdm_modem0_out_tpda_modem = "/soc/tpdm@10800000/out-ports/port/endpoint";
|
|
tpdm_modem1 = "/soc/tpdm@10801000";
|
|
tpdm_modem1_out_tpda_modem = "/soc/tpdm@10801000/out-ports/port/endpoint";
|
|
tpdm_modem_rscc = "/soc/tpdm@1080d000";
|
|
tpdm_modem_rscc_out_funnel_modem_q6 = "/soc/tpdm@1080d000/out-ports/port/endpoint";
|
|
trace_noc = "/soc/traceNoc@10ac1000";
|
|
trace_noc_in_tpdm_trace_noc = "/soc/traceNoc@10ac1000/in-ports/port@1/endpoint";
|
|
trace_noc_out_funnel_in1 = "/soc/traceNoc@10ac1000/out-ports/port/endpoint";
|
|
funnel_ddr_lpi = "/soc/funnel@10b33000";
|
|
funnel_ddr_lpi_in_tpdm_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint";
|
|
funnel_ddr_out_funnel_aoss = "/soc/funnel@10b33000/out-ports/port@0/endpoint";
|
|
funnel_gfx = "/soc/funnel@10963000";
|
|
funnel_gfx_out_funnel_gfx_dl = "/soc/funnel@10963000/out-ports/port/endpoint";
|
|
funnel_gfx_dl = "/soc/funnel@10902000";
|
|
funnel_gfx_dl_in_tpdm_gfx = "/soc/funnel@10902000/in-ports/port@0/endpoint";
|
|
funnel_gfx_dl_in_funnel_gfx = "/soc/funnel@10902000/in-ports/port@1/endpoint";
|
|
funnel_gfx_dl_out_tpda_dl_center_19 = "/soc/funnel@10902000/out-ports/port@0/endpoint";
|
|
funnel_gfx_dl_out_funnel_dl_center = "/soc/funnel@10902000/out-ports/port@1/endpoint";
|
|
funnel_video = "/soc/funnel@10832000";
|
|
funnel_video_in_tpdm_video = "/soc/funnel@10832000/in-ports/port@0/endpoint";
|
|
funnel_video_out_funnel_multimedia = "/soc/funnel@10832000/out-ports/port@0/endpoint";
|
|
tpda_titan = "/soc/tpda@10c17000";
|
|
tpda_titan_in_tpdm_titan = "/soc/tpda@10c17000/in-ports/port@0/endpoint";
|
|
tpda_titan_out_funnel_titan = "/soc/tpda@10c17000/out-ports/port@0/endpoint";
|
|
funnel_titan = "/soc/funnel@10c14000";
|
|
funnel_titan_in_tpda_titan = "/soc/funnel@10c14000/in-ports/port@2/endpoint";
|
|
funnel_titan_out_funnel_multimedia = "/soc/funnel@10c14000/out-ports/port@0/endpoint";
|
|
tpda_tmess = "/soc/tpda@10cc4000";
|
|
tpda_tmess_in_tpdm_tmess_prng = "/soc/tpda@10cc4000/in-ports/port@0/endpoint";
|
|
tpda_tmess_in_tpdm_tmess0 = "/soc/tpda@10cc4000/in-ports/port@1/endpoint";
|
|
tpda_tmess_in_tpdm_tmess1 = "/soc/tpda@10cc4000/in-ports/port@2/endpoint";
|
|
tpda_tmess_out_funnel_tmess = "/soc/tpda@10cc4000/out-ports/port/endpoint";
|
|
funnel_tmess = "/soc/funnel@10cc5000";
|
|
funnel_tmess_in_tpda_tmess = "/soc/funnel@10cc5000/in-ports/port@0/endpoint";
|
|
funnel_tmess_out_funnel_multimedia = "/soc/funnel@10cc5000/out-ports/port@0/endpoint";
|
|
funnel_multimedia = "/soc/funnel@10c0a000";
|
|
funnel_multimedia_in_funnel_video = "/soc/funnel@10c0a000/in-ports/port@0/endpoint";
|
|
funnel_multimedia_in_tpdm_mdss = "/soc/funnel@10c0a000/in-ports/port@1/endpoint";
|
|
funnel_multimedia_in_tpdm_dl_mm = "/soc/funnel@10c0a000/in-ports/port@3/endpoint";
|
|
funnel_multimedia_in_funnel_titan = "/soc/funnel@10c0a000/in-ports/port@5/endpoint";
|
|
funnel_multimedia_in_funnel_tmess = "/soc/funnel@10c0a000/in-ports/port@6/endpoint";
|
|
funnel_multimedia_out_funnel_dl_west = "/soc/funnel@10c0a000/out-ports/port@0/endpoint";
|
|
funnel_lpass = "/soc/funnel@10846000";
|
|
funnel_lpass_in_tpdm_lpass = "/soc/funnel@10846000/in-ports/port@0/endpoint";
|
|
funnel_lpass_out_tpda_dl_center = "/soc/funnel@10846000/out-ports/port@0/endpoint";
|
|
funnel_ddr_ch02 = "/soc/funnel@10d22000";
|
|
funnel_ddr_ch02_in_tpdm_ddr_ch02 = "/soc/funnel@10d22000/in-ports/port@0/endpoint";
|
|
funnel_ddr_ch02_out_funnel_ddr_dl0 = "/soc/funnel@10d22000/out-ports/port@0/endpoint";
|
|
funnel_ddr_ch13 = "/soc/funnel@10d32000";
|
|
funnel_ddr_ch13_in_tpdm_ddr_ch13 = "/soc/funnel@10d32000/in-ports/port@0/endpoint";
|
|
funnel_ddr_ch13_out_funnel_ddr_dl0 = "/soc/funnel@10d32000/out-ports/port@0/endpoint";
|
|
tpda_ddr = "/soc/tpda@10d09000";
|
|
tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint";
|
|
tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint";
|
|
tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint";
|
|
tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint";
|
|
tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint";
|
|
gladiator = "/soc/gladiator";
|
|
gladiator_out_funnel_ddr_dl1 = "/soc/gladiator/out-ports/port/endpoint";
|
|
funnel_ddr_dl1 = "/soc/funnel@10d0a000";
|
|
funnel_ddr_dl1_in_tpda_ddr = "/soc/funnel@10d0a000/in-ports/port@0/endpoint";
|
|
funnel_ddr_dl1_in_gladiator = "/soc/funnel@10d0a000/in-ports/port@3/endpoint";
|
|
funnel_ddr_dl1_out_funnel_ddr_dl0 = "/soc/funnel@10d0a000/out-ports/port@0/endpoint";
|
|
funnel_ddr_dl0 = "/soc/funnel@10d03000";
|
|
funnel_ddr_dl0_in_funnel_ddr_ch02 = "/soc/funnel@10d03000/in-ports/port@0/endpoint";
|
|
funnel_ddr_dl0_in_funnel_ddr_ch13 = "/soc/funnel@10d03000/in-ports/port@1/endpoint";
|
|
funnel_ddr_dl0_in_tpdm_ddr0 = "/soc/funnel@10d03000/in-ports/port@2/endpoint";
|
|
funnel_ddr_dl0_in_tpdm_ddr1 = "/soc/funnel@10d03000/in-ports/port@3/endpoint";
|
|
funnel_ddr_dl0_in_funnel_ddr_dl1 = "/soc/funnel@10d03000/in-ports/port@4/endpoint";
|
|
funnel_ddr_dl0_out_tpda_dl_center_4 = "/soc/funnel@10d03000/out-ports/port@0/endpoint";
|
|
funnel_ddr_dl0_out_tpda_dl_center_5 = "/soc/funnel@10d03000/out-ports/port@1/endpoint";
|
|
funnel_ddr_dl0_out_tpda_dl_center_6 = "/soc/funnel@10d03000/out-ports/port@2/endpoint";
|
|
funnel_ddr_dl0_out_tpda_dl_center_7 = "/soc/funnel@10d03000/out-ports/port@3/endpoint";
|
|
funnel_ddr_dl0_out_funnel_dl_center = "/soc/funnel@10d03000/out-ports/port@4/endpoint";
|
|
tpda_turing = "/soc/tpda@10986000";
|
|
tpda_turing_in_tpdm_turing = "/soc/tpda@10986000/in-ports/port@0/endpoint";
|
|
tpda_turing_in_tpdm_turing_llm = "/soc/tpda@10986000/in-ports/port@1/endpoint";
|
|
tpda_turing_in_tpdm_turing_llm2 = "/soc/tpda@10986000/in-ports/port@2/endpoint";
|
|
tpda_turing_in_tpdm_dpm1 = "/soc/tpda@10986000/in-ports/port@3/endpoint";
|
|
tpda_turing_in_tpdm_dmp2 = "/soc/tpda@10986000/in-ports/port@4/endpoint";
|
|
tpda_turing_out_funnel_turing = "/soc/tpda@10986000/out-ports/port@0/endpoint";
|
|
turing_etm0 = "/soc/turing_etm0";
|
|
turing_etm0_out_funnel_turing_dup = "/soc/turing_etm0/out-ports/port/endpoint";
|
|
funnel_turing_dup = "/soc/funnel@10940000";
|
|
funnel_turing_dup_in_turing_etm0 = "/soc/funnel@10940000/in-ports/port@4/endpoint";
|
|
funnel_turing_dup_out_funnel_turing = "/soc/funnel@10940000/out-ports/port/endpoint";
|
|
funnel_turing = "/soc/funnel@10987000";
|
|
funnel_turing_in_tpda_turing = "/soc/funnel@10987000/in-ports/port@0/endpoint";
|
|
funnel_turing_in_funnel_turing_dup = "/soc/funnel@10987000/in-ports/port@4/endpoint";
|
|
funnel_turing_out_funnel_dl_center = "/soc/funnel@10987000/out-ports/port@0/endpoint";
|
|
funnel_dl_west = "/soc/funnel@10c3c000";
|
|
funnel_dl_west_in_funnel_multimedia = "/soc/funnel@10c3c000/in-ports/port@0/endpoint";
|
|
funnel_dl_west_in_tpdm_rdpm0 = "/soc/funnel@10c3c000/in-ports/port@1/endpoint";
|
|
funnel_dl_west_in_tpdm_rdpm1 = "/soc/funnel@10c3c000/in-ports/port@2/endpoint";
|
|
funnel_dl_west_in_tpdm_rdpm2 = "/soc/funnel@10c3c000/in-ports/port@3/endpoint";
|
|
funnel_dl_west_in_tpdm_spare = "/soc/funnel@10c3c000/in-ports/port@4/endpoint";
|
|
funnel_dl_west_out_tpda_dl_center_8 = "/soc/funnel@10c3c000/out-ports/port@0/endpoint";
|
|
funnel_dl_west_out_tpda_dl_center_9 = "/soc/funnel@10c3c000/out-ports/port@1/endpoint";
|
|
funnel_dl_west_out_tpda_dl_center_11 = "/soc/funnel@10c3c000/out-ports/port@2/endpoint";
|
|
funnel_dl_west_out_tpda_dl_center_13 = "/soc/funnel@10c3c000/out-ports/port@3/endpoint";
|
|
funnel_dl_west_out_tpda_dl_center_14 = "/soc/funnel@10c3c000/out-ports/port@4/endpoint";
|
|
funnel_dl_west_out_tpda_dl_center_15 = "/soc/funnel@10c3c000/out-ports/port@5/endpoint";
|
|
funnel_dl_west_out_tpda_dl_center_16 = "/soc/funnel@10c3c000/out-ports/port@6/endpoint";
|
|
funnel_dl_west_out_funnel_dl_center = "/soc/funnel@10c3c000/out-ports/port@7/endpoint";
|
|
tpda_dl_south = "/soc/tpda@109c1000";
|
|
tpda_dl_south_in_tpdm_sdcc4 = "/soc/tpda@109c1000/in-ports/port@1/endpoint";
|
|
tpda_dl_south_in_tpdm_ufs = "/soc/tpda@109c1000/in-ports/port@2/endpoint";
|
|
tpda_dl_south_in_tpdm_dl_south = "/soc/tpda@109c1000/in-ports/port@4/endpoint";
|
|
tpda_dl_south_out_funnel_dl_south = "/soc/tpda@109c1000/out-ports/port@0/endpoint";
|
|
funnel_dl_south = "/soc/funnel@109c2000";
|
|
funnel_dl_south_in_tpda_dl_south = "/soc/funnel@109c2000/in-ports/port@0/endpoint";
|
|
funnel_dl_south_out_funnel_in1 = "/soc/funnel@109c2000/out-ports/port@0/endpoint";
|
|
modem_etm0_out_funnel_modem_q6_dup = "/soc/modem_etm0/out-ports/port/endpoint";
|
|
modem2_etm0_out_funnel_modem = "/soc/modem2_etm0/out-ports/port/endpoint";
|
|
modem_diag = "/soc/modem_diag";
|
|
modem_diag_out_funnel_modem_q6 = "/soc/modem_diag/out-ports/port/endpoint";
|
|
tpda_modem = "/soc/tpda@10803000";
|
|
tpda_modem_in_tpdm_modem0 = "/soc/tpda@10803000/in-ports/port@0/endpoint";
|
|
tpda_modem_in_tpdm_modem1 = "/soc/tpda@10803000/in-ports/port@1/endpoint";
|
|
tpda_modem_out_funnel_modem_dl = "/soc/tpda@10803000/out-ports/port/endpoint";
|
|
funnel_modem_q6_dup = "/soc/funnel@1080d000";
|
|
funnel_modem_q6_dup_in_modem_etm0 = "/soc/funnel@1080d000/in-ports/port@0/endpoint";
|
|
funnel_modem_q6_dup_out_funnel_modem_q6 = "/soc/funnel@1080d000/out-ports/port/endpoint";
|
|
funnel_modem_q6 = "/soc/funnel@1080c000";
|
|
funnel_modem_q6_in_funnel_modem_q6_dup = "/soc/funnel@1080c000/in-ports/port@1/endpoint";
|
|
funnel_modem_q6_in_modem_diag = "/soc/funnel@1080c000/in-ports/port@2/endpoint";
|
|
funnel_modem_q6_in_tpdm_modem_rscc = "/soc/funnel@1080c000/in-ports/port@3/endpoint";
|
|
funnel_modem_q6_out_funnel_modem_dl = "/soc/funnel@1080c000/out-ports/port/endpoint";
|
|
funnel_modem_dl = "/soc/funnel@10804000";
|
|
funnel_modem_dl_in_tpda_modem = "/soc/funnel@10804000/in-ports/port@0/endpoint";
|
|
funnel_modem_in_modem2_etm0 = "/soc/funnel@10804000/in-ports/port@1/endpoint";
|
|
funnel_modem_dl_in_funnel_modem_q6 = "/soc/funnel@10804000/in-ports/port@3/endpoint";
|
|
funnel_modem_dl_out_funnel_in1 = "/soc/funnel@10804000/out-ports/port/endpoint";
|
|
tpda_apss = "/soc/tpda@13864000";
|
|
tpda_apss_in_tpdm_llm_silver = "/soc/tpda@13864000/in-ports/port@0/endpoint";
|
|
tpda_apss_in_tpdm_llm_gold = "/soc/tpda@13864000/in-ports/port@1/endpoint";
|
|
tpda_apss_in_tpdm_llm_ext = "/soc/tpda@13864000/in-ports/port@2/endpoint";
|
|
tpda_apss_in_tpdm_llm_gold_apc = "/soc/tpda@13864000/in-ports/port@3/endpoint";
|
|
tpda_apss_in_tpdm_apss_ubwcp = "/soc/tpda@13864000/in-ports/port@4/endpoint";
|
|
tpda_apss_in_tpdm_apss_apc2 = "/soc/tpda@13864000/in-ports/port@5/endpoint";
|
|
tpda_apss_in_tpdm_apss_0 = "/soc/tpda@13864000/in-ports/port@6/endpoint";
|
|
tpda_apss_in_tpdm_apss1 = "/soc/tpda@13864000/in-ports/port@7/endpoint";
|
|
tpda_apss_in_tpdm_apss2 = "/soc/tpda@13864000/in-ports/port@8/endpoint";
|
|
tpda_apss_out_funnel_apss = "/soc/tpda@13864000/out-ports/port/endpoint";
|
|
funnel_apss = "/soc/funnel@13810000";
|
|
funnel_apss_in_tpda_apss = "/soc/funnel@13810000/in-ports/port@3/endpoint";
|
|
funnel_apss_in_funnel_ete = "/soc/funnel@13810000/in-ports/port@0/endpoint";
|
|
funnel_apss_out_funnel_in1 = "/soc/funnel@13810000/out-ports/port/endpoint";
|
|
tpda_dl_center = "/soc/tpda@10c2c000";
|
|
tpda_dl_center_in_funnel_lpass = "/soc/tpda@10c2c000/in-ports/port@0/endpoint";
|
|
tpda_dl_center_4_in_funnel_ddr_dl0 = "/soc/tpda@10c2c000/in-ports/port@4/endpoint";
|
|
tpda_dl_center_5_in_funnel_ddr_dl0 = "/soc/tpda@10c2c000/in-ports/port@5/endpoint";
|
|
tpda_dl_center_6_in_funnel_ddr_dl0 = "/soc/tpda@10c2c000/in-ports/port@6/endpoint";
|
|
tpda_dl_center_7_in_funnel_ddr_dl0 = "/soc/tpda@10c2c000/in-ports/port@7/endpoint";
|
|
tpda_dl_center_8_in_funnel_dl_west = "/soc/tpda@10c2c000/in-ports/port@8/endpoint";
|
|
tpda_dl_center_9_in_funnel_dl_west = "/soc/tpda@10c2c000/in-ports/port@9/endpoint";
|
|
tpda_dl_center_11_in_funnel_dl_west = "/soc/tpda@10c2c000/in-ports/port@11/endpoint";
|
|
tpda_dl_center_13_in_funnel_dl_west = "/soc/tpda@10c2c000/in-ports/port@13/endpoint";
|
|
tpda_dl_center_14_in_funnel_dl_west = "/soc/tpda@10c2c000/in-ports/port@14/endpoint";
|
|
tpda_dl_center_15_in_funnel_dl_west = "/soc/tpda@10c2c000/in-ports/port@15/endpoint";
|
|
tpda_dl_center_16_in_funnel_dl_west = "/soc/tpda@10c2c000/in-ports/port@16/endpoint";
|
|
tpda_dl_center_19_in_funnel_gfx_dl = "/soc/tpda@10c2c000/in-ports/port@19/endpoint";
|
|
tpda_dl_center_21_in_tpdm_prng = "/soc/tpda@10c2c000/in-ports/port@21/endpoint";
|
|
tpda_dl_center_22_in_tpdm_qm = "/soc/tpda@10c2c000/in-ports/port@22/endpoint";
|
|
tpda_dl_center_23_in_tpdm_gcc = "/soc/tpda@10c2c000/in-ports/port@23/endpoint";
|
|
tpda_dl_center_24_in_tpdm_vsense = "/soc/tpda@10c2c000/in-ports/port@24/endpoint";
|
|
tpda_dl_center_26_in_tpdm_ipa = "/soc/tpda@10c2c000/in-ports/port@26/endpoint";
|
|
tpda_dl_center_29_in_tpdm_dl_ct = "/soc/tpda@10c2c000/in-ports/port@29/endpoint";
|
|
tpda_dl_center_30_in_tpdm_ipcc = "/soc/tpda@10c2c000/in-ports/port@30/endpoint";
|
|
tpda_dl_center_out_funnel_dl_center = "/soc/tpda@10c2c000/out-ports/port/endpoint";
|
|
funnel_dl_center = "/soc/funnel@10c2d000";
|
|
funnel_dl_center_in_tpda_dl_center = "/soc/funnel@10c2d000/in-ports/port@0/endpoint";
|
|
funnel_dl_center_in_funnel_ddr_dl0 = "/soc/funnel@10c2d000/in-ports/port@2/endpoint";
|
|
funnel_dl_center_in_funnel_dl_west = "/soc/funnel@10c2d000/in-ports/port@3/endpoint";
|
|
funnel_dl_center_in_funnel_gfx_dl = "/soc/funnel@10c2d000/in-ports/port@5/endpoint";
|
|
funnel_dl_center_in_funnel_turing = "/soc/funnel@10c2d000/in-ports/port@7/endpoint";
|
|
funnel_dl_center_out_funnel_in1 = "/soc/funnel@10c2d000/out-ports/port/endpoint";
|
|
tpda_qdss = "/soc/tpda@10004000";
|
|
tpda_qdss_in_tpdm_dcc = "/soc/tpda@10004000/in-ports/port@0/endpoint";
|
|
tpda_qdss_in_tpdm_spdm = "/soc/tpda@10004000/in-ports/port@1/endpoint";
|
|
tpda_qdss_out_funnel_in0 = "/soc/tpda@10004000/out-ports/port/endpoint";
|
|
funnel_in0 = "/soc/funnel@10041000";
|
|
funnel_in0_in_tpda_qdss = "/soc/funnel@10041000/in-ports/port@6/endpoint";
|
|
funnel_in0_in_stm = "/soc/funnel@10041000/in-ports/port@7/endpoint";
|
|
funnel_in0_out_funnel_qdss = "/soc/funnel@10041000/out-ports/port/endpoint";
|
|
funnel_qdss = "/soc/funnel@10045000";
|
|
funnel_qdss_in_funnel_in0 = "/soc/funnel@10045000/in-ports/port@0/endpoint";
|
|
funnel_qdss_in_funnel_in1 = "/soc/funnel@10045000/in-ports/port@1/endpoint";
|
|
funnel_qdss_out_funnel_aoss = "/soc/funnel@10045000/out-ports/port/endpoint";
|
|
tpda_aoss = "/soc/tpda@10b08000";
|
|
tpda_aoss_in_tpdm_swao_prio0 = "/soc/tpda@10b08000/in-ports/port@0/endpoint";
|
|
tpda_aoss_in_tpdm_swao_prio1 = "/soc/tpda@10b08000/in-ports/port@1/endpoint";
|
|
tpda_aoss_in_tpdm_swao_prio2 = "/soc/tpda@10b08000/in-ports/port@2/endpoint";
|
|
tpda_aoss_in_tpdm_swao_prio3 = "/soc/tpda@10b08000/in-ports/port@3/endpoint";
|
|
tpda_aoss_in_tpdm_swao = "/soc/tpda@10b08000/in-ports/port@4/endpoint";
|
|
tpda_aoss_out_funnel_aoss = "/soc/tpda@10b08000/out-ports/port/endpoint";
|
|
funnel_aoss = "/soc/funnel@10b04000";
|
|
funnel_aoss_in_funnel_ddr = "/soc/funnel@10b04000/in-ports/port@3/endpoint";
|
|
funnel_aoss_in_funnel_lpass_lpi = "/soc/funnel@10b04000/in-ports/port@5/endpoint";
|
|
funnel_aoss_in_tpda_aoss = "/soc/funnel@10b04000/in-ports/port@6/endpoint";
|
|
funnel_aoss_in_funnel_qdss = "/soc/funnel@10b04000/in-ports/port@7/endpoint";
|
|
funnel_aoss_out_tmc_etf = "/soc/funnel@10b04000/out-ports/port/endpoint";
|
|
tmc_etf = "/soc/tmc@10b05000";
|
|
tmc_etf_in_funnel_aoss = "/soc/tmc@10b05000/in-ports/port/endpoint";
|
|
tmc_etf_out_replicator_swao = "/soc/tmc@10b05000/out-ports/port/endpoint";
|
|
replicator_swao = "/soc/replicator@10b06000";
|
|
replicator_swao_in_tmc_etf = "/soc/replicator@10b06000/in-ports/port/endpoint";
|
|
replicator_swao_out_replicator_qdss = "/soc/replicator@10b06000/out-ports/port@0/endpoint";
|
|
replicator_swao_out_eud = "/soc/replicator@10b06000/out-ports/port@1/endpoint";
|
|
replicator_qdss = "/soc/replicator@10046000";
|
|
replicator_qdss_in_replicator_swao = "/soc/replicator@10046000/in-ports/port/endpoint";
|
|
replicator_qdss_out_replicator_etr = "/soc/replicator@10046000/out-ports/port@0/endpoint";
|
|
replicator_etr = "/soc/replicator@1004e000";
|
|
replicator_etr_in_replicator_qdss = "/soc/replicator@1004e000/in-ports/port/endpoint";
|
|
replicator_etr_out_tmc_etr = "/soc/replicator@1004e000/out-ports/port@0/endpoint";
|
|
replicator_etr_out_replicator_dummy = "/soc/replicator@1004e000/out-ports/port@1/endpoint";
|
|
replicator_dummy_in_replicator_etr = "/soc/dummy_replicator/in-ports/port/endpoint";
|
|
replicator_dummy_out_tmc_modem = "/soc/dummy_replicator/out-ports/port@0/endpoint";
|
|
replicator_dummy_out_tmc_etr1 = "/soc/dummy_replicator/out-ports/port@1/endpoint";
|
|
tmc_modem = "/soc/tmc_modem";
|
|
tmc_modem_in_replicator_dummy = "/soc/tmc_modem/in-ports/port/endpoint";
|
|
tmc_etr = "/soc/tmc@10048000";
|
|
tmc_etr_in_replicator_etr = "/soc/tmc@10048000/in-ports/port/endpoint";
|
|
tmc_etr1 = "/soc/tmc@1004f000";
|
|
tmc_etr1_in_replicator_dummy = "/soc/tmc@1004f000/in-ports/port/endpoint";
|
|
csr = "/soc/csr@10001000";
|
|
swao_csr = "/soc/csr@10b11000";
|
|
ete0_out_funnel_ete = "/soc/ete0/out-ports/port/endpoint";
|
|
ete1_out_funnel_ete = "/soc/ete1/out-ports/port/endpoint";
|
|
ete2_out_funnel_ete = "/soc/ete2/out-ports/port/endpoint";
|
|
ete3_out_funnel_ete = "/soc/ete3/out-ports/port/endpoint";
|
|
ete4_out_funnel_ete = "/soc/ete4/out-ports/port/endpoint";
|
|
ete5_out_funnel_ete = "/soc/ete5/out-ports/port/endpoint";
|
|
ete6_out_funnel_ete = "/soc/ete6/out-ports/port/endpoint";
|
|
ete7_out_funnel_ete = "/soc/ete7/out-ports/port/endpoint";
|
|
funnel_ete_out_funnel_apss = "/soc/funnel_ete/out-ports/port/endpoint";
|
|
funnel_ete_in_ete0 = "/soc/funnel_ete/in-ports/port@0/endpoint";
|
|
funnel_ete_in_ete1 = "/soc/funnel_ete/in-ports/port@1/endpoint";
|
|
funnel_ete_in_ete2 = "/soc/funnel_ete/in-ports/port@2/endpoint";
|
|
funnel_ete_in_ete3 = "/soc/funnel_ete/in-ports/port@3/endpoint";
|
|
funnel_ete_in_ete4 = "/soc/funnel_ete/in-ports/port@4/endpoint";
|
|
funnel_ete_in_ete5 = "/soc/funnel_ete/in-ports/port@5/endpoint";
|
|
funnel_ete_in_ete6 = "/soc/funnel_ete/in-ports/port@6/endpoint";
|
|
funnel_ete_in_ete7 = "/soc/funnel_ete/in-ports/port@7/endpoint";
|
|
funnel_in1 = "/soc/funnel@10042000";
|
|
funnel_in1_in_funnel_dl_center = "/soc/funnel@10042000/in-ports/port@6/endpoint";
|
|
funnel_in1_in_funnel_dl_south = "/soc/funnel@10042000/in-ports/port@0/endpoint";
|
|
funnel_in1_in_trace_noc = "/soc/funnel@10042000/in-ports/port@1/endpoint";
|
|
funnel_in1_in_funnel_apss = "/soc/funnel@10042000/in-ports/port@4/endpoint";
|
|
funnel_in1_in_funnel_modem_dl = "/soc/funnel@10042000/in-ports/port@5/endpoint";
|
|
funnel_in1_out_funnel_qdss = "/soc/funnel@10042000/out-ports/port/endpoint";
|
|
dummy_eud = "/soc/dummy_sink";
|
|
eud_in_replicator_swao = "/soc/dummy_sink/in-ports/port/endpoint";
|
|
qdss_cti = "/soc/cti@10010000";
|
|
cti0 = "/soc/cti@10c2a000";
|
|
dlmm_cti0 = "/soc/cti@10c09000";
|
|
ddr_dl_0_cti_0 = "/soc/cti@10d02000";
|
|
ddr_dl_1_cti_0 = "/soc/cti@10d08000";
|
|
ddr_ch02_dl_cti_0 = "/soc/cti@10d21000";
|
|
ddr_ch13_dl_cti_0 = "/soc/cti@10d31000";
|
|
ddrss_shrm2 = "/soc/cti@10d11000";
|
|
ddr_dl2_lpi = "/soc/cti@10b31000";
|
|
lpass_dl_cti = "/soc/cti@10845000";
|
|
lpass_lpi_cti1 = "/soc/cti@10b41000";
|
|
lpass_lpi_cti3 = "/soc/cti@10b51000";
|
|
lpass_ssc_sdc = "/soc/cti@10b42000";
|
|
lpass_q6_cti = "/soc/cti@10b4b000";
|
|
apss_pe0 = "/soc/cti@12010000";
|
|
apss_pe1 = "/soc/cti@12020000";
|
|
apss_pe2 = "/soc/cti@12030000";
|
|
apss_pe3 = "/soc/cti@12040000";
|
|
apss_pe4 = "/soc/cti@12050000";
|
|
apss_pe5 = "/soc/cti@12060000";
|
|
apss_pe6 = "/soc/cti@12070000";
|
|
apss_pe7 = "/soc/cti@12080000";
|
|
apss_cluster = "/soc/cti@12230000";
|
|
apss_cti0 = "/soc/cti@138e0000";
|
|
apss_cti1 = "/soc/cti@138f0000";
|
|
apss_cti2 = "/soc/cti@13900000";
|
|
riscv_cti = "/soc/cti@1382b000";
|
|
riscv_sifive_cti = "/soc/cti@1382e000";
|
|
apss_atb_cti = "/soc/cti@13863000";
|
|
gpu_isdb_cti = "/soc/cti@10961000";
|
|
gpu_cortex_m3 = "/soc/cti@10962000";
|
|
gpu_dl = "/soc/cti@10901000";
|
|
iris_dl_cti = "/soc/cti@10831000";
|
|
mdss_dl_cti = "/soc/cti@10c61000";
|
|
turing_dl_cti_0 = "/soc/cti@10985000";
|
|
turing_q6_cti = "/soc/cti@1098b000";
|
|
camera_dl = "/soc/cti@10c15000";
|
|
swao_cti = "/soc/cti@10b00000";
|
|
aop_rvss = "/soc/cti@10b21000";
|
|
mss_q6_cti = "/soc/cti@1080b000";
|
|
mss_vq6_cti = "/soc/cti@10813000";
|
|
modem_tp_cti = "/soc/cti@10802000";
|
|
tmess_cti_3 = "/soc/cti@10cc2000";
|
|
tmess_cti_2 = "/soc/cti@10cc2000";
|
|
tmess_cti_1 = "/soc/cti@10cc2000";
|
|
tmess_cti_0 = "/soc/cti@10cc2000";
|
|
tmess_cti_4 = "/soc/cti@10cc3000";
|
|
tmess_cpu = "/soc/cti@10cd1000";
|
|
ipcb_tgu = "/soc/tgu@10b0e000";
|
|
spmi_tgu0 = "/soc/tgu@10b0f000";
|
|
spmi_tgu1 = "/soc/tgu@10b10000";
|
|
pcie0 = "/soc/qcom,pcie@1c00000";
|
|
pcie0_rp = "/soc/qcom,pcie@1c00000/pcie0_rp";
|
|
pcie0_msi = "/soc/qcom,pcie0_msi@0x17110040";
|
|
pcie1 = "/soc/qcom,pcie@1c08000";
|
|
pcie1_rp = "/soc/qcom,pcie@1c08000/pcie1_rp";
|
|
pcie1_msi = "/soc/qcom,pcie1_msi@0x17110040";
|
|
tsens0 = "/soc/tsens0@c228000";
|
|
tsens1 = "/soc/tsens1@c229000";
|
|
tsens2 = "/soc/tsens2@c22a000";
|
|
cpu0_pause = "/soc/qcom,cpu-pause/cpu0-pause";
|
|
cpu1_pause = "/soc/qcom,cpu-pause/cpu1-pause";
|
|
cpu2_pause = "/soc/qcom,cpu-pause/cpu2-pause";
|
|
cpu3_pause = "/soc/qcom,cpu-pause/cpu3-pause";
|
|
cpu4_pause = "/soc/qcom,cpu-pause/cpu4-pause";
|
|
cpu5_pause = "/soc/qcom,cpu-pause/cpu5-pause";
|
|
cpu6_pause = "/soc/qcom,cpu-pause/cpu6-pause";
|
|
cpu7_pause = "/soc/qcom,cpu-pause/cpu7-pause";
|
|
APC2_pause = "/soc/qcom,cpu-pause/apc2-pause";
|
|
APC1_pause = "/soc/qcom,cpu-pause/apc1-pause";
|
|
cpu0_hotplug = "/soc/qcom,cpu-hotplug/cpu0-hotplug";
|
|
cpu1_hotplug = "/soc/qcom,cpu-hotplug/cpu1-hotplug";
|
|
cpu2_hotplug = "/soc/qcom,cpu-hotplug/cpu2-hotplug";
|
|
cpu3_hotplug = "/soc/qcom,cpu-hotplug/cpu3-hotplug";
|
|
cpu4_hotplug = "/soc/qcom,cpu-hotplug/cpu4-hotplug";
|
|
cpu5_hotplug = "/soc/qcom,cpu-hotplug/cpu5-hotplug";
|
|
cpu6_hotplug = "/soc/qcom,cpu-hotplug/cpu6-hotplug";
|
|
cpu7_hotplug = "/soc/qcom,cpu-hotplug/cpu7-hotplug";
|
|
apc1_cluster = "/soc/qcom,cpu-voltage-cdev/thermal-cluster-2-3";
|
|
ddr_cdev = "/soc/qcom,ddr-cdev";
|
|
qmi_tmd = "/soc/qmi-tmd-devices";
|
|
cdsp_sw = "/soc/qmi-tmd-devices/cdsp/cdsp";
|
|
cdsp_sw_hvx = "/soc/qmi-tmd-devices/cdsp/cdsp_sw_hvx";
|
|
cdsp_sw_hmx = "/soc/qmi-tmd-devices/cdsp/cdsp_sw_hmx";
|
|
cdsp_hw = "/soc/qmi-tmd-devices/cdsp/cdsp_hw";
|
|
modem_bcl = "/soc/qmi-tmd-devices/modem/modem_bcl";
|
|
modem_lte_dsc = "/soc/qmi-tmd-devices/modem/modem_lte_dsc";
|
|
modem_nr_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_dsc";
|
|
modem_nr_scg_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_scg_dsc";
|
|
sdr0_lte_dsc = "/soc/qmi-tmd-devices/modem/sdr0_lte_dsc";
|
|
sdr0_nr_dsc = "/soc/qmi-tmd-devices/modem/sdr0_nr_dsc";
|
|
pa_lte_sdr0_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr0_dsc";
|
|
pa_nr_sdr0_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_dsc";
|
|
pa_nr_sdr0_scg_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_scg_dsc";
|
|
mmw0_dsc = "/soc/qmi-tmd-devices/modem/mmw0_dsc";
|
|
mmw1_dsc = "/soc/qmi-tmd-devices/modem/mmw1_dsc";
|
|
mmw2_dsc = "/soc/qmi-tmd-devices/modem/mmw2_dsc";
|
|
mmw3_dsc = "/soc/qmi-tmd-devices/modem/mmw3_dsc";
|
|
qmi_wlan = "/soc/qmi-tmd-devices/modem/wlan";
|
|
modem_bw_backoff = "/soc/qmi-tmd-devices/modem/modem_bw_backoff";
|
|
modem_vdd = "/soc/qmi-tmd-devices/modem/modem_vdd";
|
|
modem_nr_scg_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_scg_sub1_dsc";
|
|
modem_lte_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_lte_sub1_dsc";
|
|
modem_nr_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_sub1_dsc";
|
|
pa_nr_sdr0_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_sub1_dsc";
|
|
pa_lte_sdr0_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr0_sub1_dsc";
|
|
pa_nr_sdr0_scg_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_scg_sub1_dsc";
|
|
mmw0_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw0_sub1_dsc";
|
|
mmw1_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw1_sub1_dsc";
|
|
mmw2_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw2_sub1_dsc";
|
|
mmw3_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw3_sub1_dsc";
|
|
display_fps = "/soc/qcom,userspace-cdev/display-fps";
|
|
limits_stat = "/soc/limits-stat";
|
|
qmi_sensor = "/soc/qmi-ts-sensors";
|
|
hypervisor = "/hypervisor";
|
|
gh_watchdog = "/hypervisor/qcom,gh-watchdog";
|
|
sched_walt = "/sched_walt";
|
|
};
|
|
};
|